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// SPDX-License-Identifier: GPL-2.0+
/*
* Advantech Single Board Computer WDT driver
*
* (c) Copyright 2000-2001 Marek Michalkiewicz <[email protected]>
*
* Based on acquirewdt.c which is based on wdt.c.
* Original copyright messages:
*
* (c) Copyright 1996 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>
*
* 14-Dec-2001 Matt Domsch <[email protected]>
* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
*
* 16-Oct-2002 Rob Radez <[email protected]>
* Clean up ioctls, clean up init + exit, add expect close support,
* add wdt_start and wdt_stop as parameters.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#define DRV_NAME "advantechwdt"
#define WATCHDOG_NAME "Advantech WDT"
#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
/* the watchdog platform device */
static struct platform_device *advwdt_platform_device;
static unsigned long advwdt_is_open;
static char adv_expect_close;
/*
* You must set these - there is no sane way to probe for this board.
*
* To enable or restart, write the timeout value in seconds (1 to 63)
* to I/O port wdt_start. To disable, read I/O port wdt_stop.
* Both are 0x443 for most boards (tested on a PCA-6276VE-00B1), but
* check your manual (at least the PCA-6159 seems to be different -
* the manual says wdt_stop is 0x43, not 0x443).
* (0x43 is also a write-only control register for the 8254 timer!)
*/
static int wdt_stop = 0x443;
module_param(wdt_stop, int, 0);
MODULE_PARM_DESC(wdt_stop, "Advantech WDT 'stop' io port (default 0x443)");
static int wdt_start = 0x443;
module_param(wdt_start, int, 0);
MODULE_PARM_DESC(wdt_start, "Advantech WDT 'start' io port (default 0x443)");
static int timeout = WATCHDOG_TIMEOUT; /* in seconds */
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. 1<= timeout <=63, default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Watchdog Operations
*/
static void advwdt_ping(void)
{
/* Write a watchdog value */
outb_p(timeout, wdt_start);
}
static void advwdt_disable(void)
{
inb_p(wdt_stop);
}
static int advwdt_set_heartbeat(int t)
{
if (t < 1 || t > 63)
return -EINVAL;
timeout = t;
return 0;
}
/*
* /dev/watchdog handling
*/
static ssize_t advwdt_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count) {
if (!nowayout) {
size_t i;
adv_expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
adv_expect_close = 42;
}
}
advwdt_ping();
}
return count;
}
static long advwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int new_timeout;
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = WATCHDOG_NAME,
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident)))
return -EFAULT;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
int options, retval = -EINVAL;
if (get_user(options, p))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
advwdt_disable();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
advwdt_ping();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
advwdt_ping();
break;
case WDIOC_SETTIMEOUT:
if (get_user(new_timeout, p))
return -EFAULT;
if (advwdt_set_heartbeat(new_timeout))
return -EINVAL;
advwdt_ping();
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(timeout, p);
default:
return -ENOTTY;
}
return 0;
}
static int advwdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &advwdt_is_open))
return -EBUSY;
/*
* Activate
*/
advwdt_ping();
return stream_open(inode, file);
}
static int advwdt_close(struct inode *inode, struct file *file)
{
if (adv_expect_close == 42) {
advwdt_disable();
} else {
pr_crit("Unexpected close, not stopping watchdog!\n");
advwdt_ping();
}
clear_bit(0, &advwdt_is_open);
adv_expect_close = 0;
return 0;
}
/*
* Kernel Interfaces
*/
static const struct file_operations advwdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = advwdt_write,
.unlocked_ioctl = advwdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = advwdt_open,
.release = advwdt_close,
};
static struct miscdevice advwdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &advwdt_fops,
};
/*
* Init & exit routines
*/
static int __init advwdt_probe(struct platform_device *dev)
{
int ret;
if (wdt_stop != wdt_start) {
if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n",
wdt_stop);
ret = -EIO;
goto out;
}
}
if (!request_region(wdt_start, 1, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n", wdt_start);
ret = -EIO;
goto unreg_stop;
}
/* Check that the heartbeat value is within it's range ;
* if not reset to the default */
if (advwdt_set_heartbeat(timeout)) {
advwdt_set_heartbeat(WATCHDOG_TIMEOUT);
pr_info("timeout value must be 1<=x<=63, using %d\n", timeout);
}
ret = misc_register(&advwdt_miscdev);
if (ret != 0) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
goto unreg_regions;
}
pr_info("initialized. timeout=%d sec (nowayout=%d)\n",
timeout, nowayout);
out:
return ret;
unreg_regions:
release_region(wdt_start, 1);
unreg_stop:
if (wdt_stop != wdt_start)
release_region(wdt_stop, 1);
goto out;
}
static void advwdt_remove(struct platform_device *dev)
{
misc_deregister(&advwdt_miscdev);
release_region(wdt_start, 1);
if (wdt_stop != wdt_start)
release_region(wdt_stop, 1);
}
static void advwdt_shutdown(struct platform_device *dev)
{
/* Turn the WDT off if we have a soft shutdown */
advwdt_disable();
}
static struct platform_driver advwdt_driver = {
.remove_new = advwdt_remove,
.shutdown = advwdt_shutdown,
.driver = {
.name = DRV_NAME,
},
};
static int __init advwdt_init(void)
{
int err;
pr_info("WDT driver for Advantech single board computer initialising\n");
advwdt_platform_device = platform_device_register_simple(DRV_NAME,
-1, NULL, 0);
if (IS_ERR(advwdt_platform_device))
return PTR_ERR(advwdt_platform_device);
err = platform_driver_probe(&advwdt_driver, advwdt_probe);
if (err)
goto unreg_platform_device;
return 0;
unreg_platform_device:
platform_device_unregister(advwdt_platform_device);
return err;
}
static void __exit advwdt_exit(void)
{
platform_device_unregister(advwdt_platform_device);
platform_driver_unregister(&advwdt_driver);
pr_info("Watchdog Module Unloaded\n");
}
module_init(advwdt_init);
module_exit(advwdt_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Marek Michalkiewicz <[email protected]>");
MODULE_DESCRIPTION("Advantech Single Board Computer WDT driver");
| linux-master | drivers/watchdog/advantechwdt.c |
/*
* Watchdog driver for SiByte SB1 SoCs
*
* Copyright (C) 2007 OnStor, Inc. * Andrew Sharp <[email protected]>
*
* This driver is intended to make the second of two hardware watchdogs
* on the Sibyte 12XX and 11XX SoCs available to the user. There are two
* such devices available on the SoC, but it seems that there isn't an
* enumeration class for watchdogs in Linux like there is for RTCs.
* The second is used rather than the first because it uses IRQ 1,
* thereby avoiding all that IRQ 0 problematic nonsense.
*
* I have not tried this driver on a 1480 processor; it might work
* just well enough to really screw things up.
*
* It is a simple timer, and there is an interrupt that is raised the
* first time the timer expires. The second time it expires, the chip
* is reset and there is no way to redirect that NMI. Which could
* be problematic in some cases where this chip is sitting on the HT
* bus and has just taken responsibility for providing a cache block.
* Since the reset can't be redirected to the external reset pin, it is
* possible that other HT connected processors might hang and not reset.
* For Linux, a soft reset would probably be even worse than a hard reset.
* There you have it.
*
* The timer takes 23 bits of a 64 bit register (?) as a count value,
* and decrements the count every microsecond, for a max value of
* 0x7fffff usec or about 8.3ish seconds.
*
* This watchdog borrows some user semantics from the softdog driver,
* in that if you close the fd, it leaves the watchdog running, unless
* you previously wrote a 'V' to the fd, in which case it disables
* the watchdog when you close the fd like some other drivers.
*
* Based on various other watchdog drivers, which are probably all
* loosely based on something Alan Cox wrote years ago.
*
* (c) Copyright 1996 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 1 or 2 as published by the Free Software Foundation.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#include <linux/reboot.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/interrupt.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_scd.h>
static DEFINE_SPINLOCK(sbwd_lock);
/*
* set the initial count value of a timer
*
* wdog is the iomem address of the cfg register
*/
static void sbwdog_set(char __iomem *wdog, unsigned long t)
{
spin_lock(&sbwd_lock);
__raw_writeb(0, wdog);
__raw_writeq(t & 0x7fffffUL, wdog - 0x10);
spin_unlock(&sbwd_lock);
}
/*
* cause the timer to [re]load it's initial count and start counting
* all over again
*
* wdog is the iomem address of the cfg register
*/
static void sbwdog_pet(char __iomem *wdog)
{
spin_lock(&sbwd_lock);
__raw_writeb(__raw_readb(wdog) | 1, wdog);
spin_unlock(&sbwd_lock);
}
static unsigned long sbwdog_gate; /* keeps it to one thread only */
static char __iomem *kern_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_0));
static char __iomem *user_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_1));
static unsigned long timeout = 0x7fffffUL; /* useconds: 8.3ish secs. */
static int expect_close;
static const struct watchdog_info ident = {
.options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "SiByte Watchdog",
};
/*
* Allow only a single thread to walk the dog
*/
static int sbwdog_open(struct inode *inode, struct file *file)
{
stream_open(inode, file);
if (test_and_set_bit(0, &sbwdog_gate))
return -EBUSY;
__module_get(THIS_MODULE);
/*
* Activate the timer
*/
sbwdog_set(user_dog, timeout);
__raw_writeb(1, user_dog);
return 0;
}
/*
* Put the dog back in the kennel.
*/
static int sbwdog_release(struct inode *inode, struct file *file)
{
if (expect_close == 42) {
__raw_writeb(0, user_dog);
module_put(THIS_MODULE);
} else {
pr_crit("%s: Unexpected close, not stopping watchdog!\n",
ident.identity);
sbwdog_pet(user_dog);
}
clear_bit(0, &sbwdog_gate);
expect_close = 0;
return 0;
}
/*
* 42 - the answer
*/
static ssize_t sbwdog_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
int i;
if (len) {
/*
* restart the timer
*/
expect_close = 0;
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
sbwdog_pet(user_dog);
}
return len;
}
static long sbwdog_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int ret = -ENOTTY;
unsigned long time;
void __user *argp = (void __user *)arg;
int __user *p = argp;
switch (cmd) {
case WDIOC_GETSUPPORT:
ret = copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
ret = put_user(0, p);
break;
case WDIOC_KEEPALIVE:
sbwdog_pet(user_dog);
ret = 0;
break;
case WDIOC_SETTIMEOUT:
ret = get_user(time, p);
if (ret)
break;
time *= 1000000;
if (time > 0x7fffffUL) {
ret = -EINVAL;
break;
}
timeout = time;
sbwdog_set(user_dog, timeout);
sbwdog_pet(user_dog);
fallthrough;
case WDIOC_GETTIMEOUT:
/*
* get the remaining count from the ... count register
* which is 1*8 before the config register
*/
ret = put_user((u32)__raw_readq(user_dog - 8) / 1000000, p);
break;
}
return ret;
}
/*
* Notifier for system down
*/
static int sbwdog_notify_sys(struct notifier_block *this, unsigned long code,
void *erf)
{
if (code == SYS_DOWN || code == SYS_HALT) {
/*
* sit and sit
*/
__raw_writeb(0, user_dog);
__raw_writeb(0, kern_dog);
}
return NOTIFY_DONE;
}
static const struct file_operations sbwdog_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = sbwdog_write,
.unlocked_ioctl = sbwdog_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = sbwdog_open,
.release = sbwdog_release,
};
static struct miscdevice sbwdog_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &sbwdog_fops,
};
static struct notifier_block sbwdog_notifier = {
.notifier_call = sbwdog_notify_sys,
};
/*
* interrupt handler
*
* doesn't do a whole lot for user, but oh so cleverly written so kernel
* code can use it to re-up the watchdog, thereby saving the kernel from
* having to create and maintain a timer, just to tickle another timer,
* which is just so wrong.
*/
irqreturn_t sbwdog_interrupt(int irq, void *addr)
{
unsigned long wd_init;
char *wd_cfg_reg = (char *)addr;
u8 cfg;
cfg = __raw_readb(wd_cfg_reg);
wd_init = __raw_readq(wd_cfg_reg - 8) & 0x7fffff;
/*
* if it's the second watchdog timer, it's for those users
*/
if (wd_cfg_reg == user_dog)
pr_crit("%s in danger of initiating system reset "
"in %ld.%01ld seconds\n",
ident.identity,
wd_init / 1000000, (wd_init / 100000) % 10);
else
cfg |= 1;
__raw_writeb(cfg, wd_cfg_reg);
return IRQ_HANDLED;
}
static int __init sbwdog_init(void)
{
int ret;
/*
* register a reboot notifier
*/
ret = register_reboot_notifier(&sbwdog_notifier);
if (ret) {
pr_err("%s: cannot register reboot notifier (err=%d)\n",
ident.identity, ret);
return ret;
}
/*
* get the resources
*/
ret = request_irq(1, sbwdog_interrupt, IRQF_SHARED,
ident.identity, (void *)user_dog);
if (ret) {
pr_err("%s: failed to request irq 1 - %d\n",
ident.identity, ret);
goto out;
}
ret = misc_register(&sbwdog_miscdev);
if (ret == 0) {
pr_info("%s: timeout is %ld.%ld secs\n",
ident.identity,
timeout / 1000000, (timeout / 100000) % 10);
return 0;
}
free_irq(1, (void *)user_dog);
out:
unregister_reboot_notifier(&sbwdog_notifier);
return ret;
}
static void __exit sbwdog_exit(void)
{
misc_deregister(&sbwdog_miscdev);
free_irq(1, (void *)user_dog);
unregister_reboot_notifier(&sbwdog_notifier);
}
module_init(sbwdog_init);
module_exit(sbwdog_exit);
MODULE_AUTHOR("Andrew Sharp <[email protected]>");
MODULE_DESCRIPTION("SiByte Watchdog");
module_param(timeout, ulong, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in microseconds (max/default 8388607 or 8.3ish secs)");
MODULE_LICENSE("GPL");
/*
* example code that can be put in a platform code area to utilize the
* first watchdog timer for the kernels own purpose.
void platform_wd_setup(void)
{
int ret;
ret = request_irq(1, sbwdog_interrupt, IRQF_SHARED,
"Kernel Watchdog", IOADDR(A_SCD_WDOG_CFG_0));
if (ret) {
pr_crit("Watchdog IRQ zero(0) failed to be requested - %d\n", ret);
}
}
*/
| linux-master | drivers/watchdog/sb_wdog.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
enum wdt_reg {
WDT_RST,
WDT_EN,
WDT_STS,
WDT_BARK_TIME,
WDT_BITE_TIME,
};
#define QCOM_WDT_ENABLE BIT(0)
static const u32 reg_offset_data_apcs_tmr[] = {
[WDT_RST] = 0x38,
[WDT_EN] = 0x40,
[WDT_STS] = 0x44,
[WDT_BARK_TIME] = 0x4C,
[WDT_BITE_TIME] = 0x5C,
};
static const u32 reg_offset_data_kpss[] = {
[WDT_RST] = 0x4,
[WDT_EN] = 0x8,
[WDT_STS] = 0xC,
[WDT_BARK_TIME] = 0x10,
[WDT_BITE_TIME] = 0x14,
};
struct qcom_wdt_match_data {
const u32 *offset;
bool pretimeout;
};
struct qcom_wdt {
struct watchdog_device wdd;
unsigned long rate;
void __iomem *base;
const u32 *layout;
};
static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
{
return wdt->base + wdt->layout[reg];
}
static inline
struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
{
return container_of(wdd, struct qcom_wdt, wdd);
}
static irqreturn_t qcom_wdt_isr(int irq, void *arg)
{
struct watchdog_device *wdd = arg;
watchdog_notify_pretimeout(wdd);
return IRQ_HANDLED;
}
static int qcom_wdt_start(struct watchdog_device *wdd)
{
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
unsigned int bark = wdd->timeout - wdd->pretimeout;
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
return 0;
}
static int qcom_wdt_stop(struct watchdog_device *wdd)
{
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
writel(0, wdt_addr(wdt, WDT_EN));
return 0;
}
static int qcom_wdt_ping(struct watchdog_device *wdd)
{
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
writel(1, wdt_addr(wdt, WDT_RST));
return 0;
}
static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->timeout = timeout;
return qcom_wdt_start(wdd);
}
static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->pretimeout = timeout;
return qcom_wdt_start(wdd);
}
static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
void *data)
{
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
u32 timeout;
/*
* Trigger watchdog bite:
* Setup BITE_TIME to be 128ms, and enable WDT.
*/
timeout = 128 * wdt->rate / 1000;
writel(0, wdt_addr(wdt, WDT_EN));
writel(1, wdt_addr(wdt, WDT_RST));
writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
/*
* Actually make sure the above sequence hits hardware before sleeping.
*/
wmb();
mdelay(150);
return 0;
}
static int qcom_wdt_is_running(struct watchdog_device *wdd)
{
struct qcom_wdt *wdt = to_qcom_wdt(wdd);
return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
}
static const struct watchdog_ops qcom_wdt_ops = {
.start = qcom_wdt_start,
.stop = qcom_wdt_stop,
.ping = qcom_wdt_ping,
.set_timeout = qcom_wdt_set_timeout,
.set_pretimeout = qcom_wdt_set_pretimeout,
.restart = qcom_wdt_restart,
.owner = THIS_MODULE,
};
static const struct watchdog_info qcom_wdt_info = {
.options = WDIOF_KEEPALIVEPING
| WDIOF_MAGICCLOSE
| WDIOF_SETTIMEOUT
| WDIOF_CARDRESET,
.identity = KBUILD_MODNAME,
};
static const struct watchdog_info qcom_wdt_pt_info = {
.options = WDIOF_KEEPALIVEPING
| WDIOF_MAGICCLOSE
| WDIOF_SETTIMEOUT
| WDIOF_PRETIMEOUT
| WDIOF_CARDRESET,
.identity = KBUILD_MODNAME,
};
static const struct qcom_wdt_match_data match_data_apcs_tmr = {
.offset = reg_offset_data_apcs_tmr,
.pretimeout = false,
};
static const struct qcom_wdt_match_data match_data_kpss = {
.offset = reg_offset_data_kpss,
.pretimeout = true,
};
static int qcom_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct qcom_wdt *wdt;
struct resource *res;
struct device_node *np = dev->of_node;
const struct qcom_wdt_match_data *data;
u32 percpu_offset;
int irq, ret;
struct clk *clk;
data = of_device_get_match_data(dev);
if (!data) {
dev_err(dev, "Unsupported QCOM WDT module\n");
return -ENODEV;
}
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOMEM;
/* We use CPU0's DGT for the watchdog */
if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
percpu_offset = 0;
res->start += percpu_offset;
res->end += percpu_offset;
wdt->base = devm_ioremap_resource(dev, res);
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk)) {
dev_err(dev, "failed to get input clock\n");
return PTR_ERR(clk);
}
/*
* We use the clock rate to calculate the max timeout, so ensure it's
* not zero to avoid a divide-by-zero exception.
*
* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
* that it would bite before a second elapses it's usefulness is
* limited. Bail if this is the case.
*/
wdt->rate = clk_get_rate(clk);
if (wdt->rate == 0 ||
wdt->rate > 0x10000000U) {
dev_err(dev, "invalid clock rate\n");
return -EINVAL;
}
/* check if there is pretimeout support */
irq = platform_get_irq_optional(pdev, 0);
if (data->pretimeout && irq > 0) {
ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
"wdt_bark", &wdt->wdd);
if (ret)
return ret;
wdt->wdd.info = &qcom_wdt_pt_info;
wdt->wdd.pretimeout = 1;
} else {
if (irq == -EPROBE_DEFER)
return -EPROBE_DEFER;
wdt->wdd.info = &qcom_wdt_info;
}
wdt->wdd.ops = &qcom_wdt_ops;
wdt->wdd.min_timeout = 1;
wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
wdt->wdd.parent = dev;
wdt->layout = data->offset;
if (readl(wdt_addr(wdt, WDT_STS)) & 1)
wdt->wdd.bootstatus = WDIOF_CARDRESET;
/*
* If 'timeout-sec' unspecified in devicetree, assume a 30 second
* default, unless the max timeout is less than 30 seconds, then use
* the max instead.
*/
wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
watchdog_init_timeout(&wdt->wdd, 0, dev);
/*
* If WDT is already running, call WDT start which
* will stop the WDT, set timeouts as bootloader
* might use different ones and set running bit
* to inform the WDT subsystem to ping the WDT
*/
if (qcom_wdt_is_running(&wdt->wdd)) {
qcom_wdt_start(&wdt->wdd);
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
}
ret = devm_watchdog_register_device(dev, &wdt->wdd);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
return 0;
}
static int __maybe_unused qcom_wdt_suspend(struct device *dev)
{
struct qcom_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
qcom_wdt_stop(&wdt->wdd);
return 0;
}
static int __maybe_unused qcom_wdt_resume(struct device *dev)
{
struct qcom_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
qcom_wdt_start(&wdt->wdd);
return 0;
}
static const struct dev_pm_ops qcom_wdt_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
};
static const struct of_device_id qcom_wdt_of_table[] = {
{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
{ },
};
MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
static struct platform_driver qcom_watchdog_driver = {
.probe = qcom_wdt_probe,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = qcom_wdt_of_table,
.pm = &qcom_wdt_pm_ops,
},
};
module_platform_driver(qcom_watchdog_driver);
MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/qcom-wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Octeon Watchdog driver
*
* Copyright (C) 2007-2017 Cavium, Inc.
*
* Converted to use WATCHDOG_CORE by Aaro Koskinen <[email protected]>.
*
* Some parts derived from wdt.c
*
* (c) Copyright 1996-1997 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>
*
* The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
* For most systems this is less than 10 seconds, so to allow for
* software to request longer watchdog heartbeats, we maintain software
* counters to count multiples of the base rate. If the system locks
* up in such a manner that we can not run the software counters, the
* only result is a watchdog reset sooner than was requested. But
* that is OK, because in this case userspace would likely not be able
* to do anything anyhow.
*
* The hardware watchdog interval we call the period. The OCTEON
* watchdog goes through several stages, after the first period an
* irq is asserted, then if it is not reset, after the next period NMI
* is asserted, then after an additional period a chip wide soft reset.
* So for the software counters, we reset watchdog after each period
* and decrement the counter. But for the last two periods we need to
* let the watchdog progress to the NMI stage so we disable the irq
* and let it proceed. Once in the NMI, we print the register state
* to the serial port and then wait for the reset.
*
* A watchdog is maintained for each CPU in the system, that way if
* one CPU suffers a lockup, we also get a register dump and reset.
* The userspace ping resets the watchdog on all CPUs.
*
* Before userspace opens the watchdog device, we still run the
* watchdogs to catch any lockups that may be kernel related.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/interrupt.h>
#include <linux/watchdog.h>
#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/cpu.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <asm/mipsregs.h>
#include <asm/uasm.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-boot-vector.h>
#include <asm/octeon/cvmx-ciu2-defs.h>
#include <asm/octeon/cvmx-rst-defs.h>
/* Watchdog interrupt major block number (8 MSBs of intsn) */
#define WD_BLOCK_NUMBER 0x01
static int divisor;
/* The count needed to achieve timeout_sec. */
static unsigned int timeout_cnt;
/* The maximum period supported. */
static unsigned int max_timeout_sec;
/* The current period. */
static unsigned int timeout_sec;
/* Set to non-zero when userspace countdown mode active */
static bool do_countdown;
static unsigned int countdown_reset;
static unsigned int per_cpu_countdown[NR_CPUS];
static cpumask_t irq_enabled_cpus;
#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
static int heartbeat = WD_TIMO;
module_param(heartbeat, int, 0444);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat in seconds. (0 < heartbeat, default="
__MODULE_STRING(WD_TIMO) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0444);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int disable;
module_param(disable, int, 0444);
MODULE_PARM_DESC(disable,
"Disable the watchdog entirely (default=0)");
static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
void octeon_wdt_nmi_stage2(void);
static int cpu2core(int cpu)
{
#ifdef CONFIG_SMP
return cpu_logical_map(cpu) & 0x3f;
#else
return cvmx_get_core_num();
#endif
}
/**
* octeon_wdt_poke_irq - Poke the watchdog when an interrupt is received
*
* @cpl:
* @dev_id:
*
* Returns
*/
static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
{
int cpu = raw_smp_processor_id();
unsigned int core = cpu2core(cpu);
int node = cpu_to_node(cpu);
if (do_countdown) {
if (per_cpu_countdown[cpu] > 0) {
/* We're alive, poke the watchdog */
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
per_cpu_countdown[cpu]--;
} else {
/* Bad news, you are about to reboot. */
disable_irq_nosync(cpl);
cpumask_clear_cpu(cpu, &irq_enabled_cpus);
}
} else {
/* Not open, just ping away... */
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
}
return IRQ_HANDLED;
}
/* From setup.c */
extern int prom_putchar(char c);
/**
* octeon_wdt_write_string - Write a string to the uart
*
* @str: String to write
*/
static void octeon_wdt_write_string(const char *str)
{
/* Just loop writing one byte at a time */
while (*str)
prom_putchar(*str++);
}
/**
* octeon_wdt_write_hex() - Write a hex number out of the uart
*
* @value: Number to display
* @digits: Number of digits to print (1 to 16)
*/
static void octeon_wdt_write_hex(u64 value, int digits)
{
int d;
int v;
for (d = 0; d < digits; d++) {
v = (value >> ((digits - d - 1) * 4)) & 0xf;
if (v >= 10)
prom_putchar('a' + v - 10);
else
prom_putchar('0' + v);
}
}
static const char reg_name[][3] = {
"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
/**
* octeon_wdt_nmi_stage3:
*
* NMI stage 3 handler. NMIs are handled in the following manner:
* 1) The first NMI handler enables CVMSEG and transfers from
* the bootbus region into normal memory. It is careful to not
* destroy any registers.
* 2) The second stage handler uses CVMSEG to save the registers
* and create a stack for C code. It then calls the third level
* handler with one argument, a pointer to the register values.
* 3) The third, and final, level handler is the following C
* function that prints out some useful infomration.
*
* @reg: Pointer to register state before the NMI
*/
void octeon_wdt_nmi_stage3(u64 reg[32])
{
u64 i;
unsigned int coreid = cvmx_get_core_num();
/*
* Save status and cause early to get them before any changes
* might happen.
*/
u64 cp0_cause = read_c0_cause();
u64 cp0_status = read_c0_status();
u64 cp0_error_epc = read_c0_errorepc();
u64 cp0_epc = read_c0_epc();
/* Delay so output from all cores output is not jumbled together. */
udelay(85000 * coreid);
octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
octeon_wdt_write_hex(coreid, 2);
octeon_wdt_write_string(" ***\r\n");
for (i = 0; i < 32; i++) {
octeon_wdt_write_string("\t");
octeon_wdt_write_string(reg_name[i]);
octeon_wdt_write_string("\t0x");
octeon_wdt_write_hex(reg[i], 16);
if (i & 1)
octeon_wdt_write_string("\r\n");
}
octeon_wdt_write_string("\terr_epc\t0x");
octeon_wdt_write_hex(cp0_error_epc, 16);
octeon_wdt_write_string("\tepc\t0x");
octeon_wdt_write_hex(cp0_epc, 16);
octeon_wdt_write_string("\r\n");
octeon_wdt_write_string("\tstatus\t0x");
octeon_wdt_write_hex(cp0_status, 16);
octeon_wdt_write_string("\tcause\t0x");
octeon_wdt_write_hex(cp0_cause, 16);
octeon_wdt_write_string("\r\n");
/* The CIU register is different for each Octeon model. */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
octeon_wdt_write_string("\tsrc_wd\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
octeon_wdt_write_string("\ten_wd\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
octeon_wdt_write_string("\r\n");
octeon_wdt_write_string("\tsrc_rml\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
octeon_wdt_write_string("\ten_rml\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
octeon_wdt_write_string("\r\n");
octeon_wdt_write_string("\tsum\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
octeon_wdt_write_string("\r\n");
} else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
octeon_wdt_write_string("\tsum0\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
octeon_wdt_write_string("\ten0\t0x");
octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
octeon_wdt_write_string("\r\n");
}
octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
/*
* G-30204: We must trigger a soft reset before watchdog
* does an incomplete job of doing it.
*/
if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
u64 scr;
unsigned int node = cvmx_get_node_num();
unsigned int lcore = cvmx_get_local_core_num();
union cvmx_ciu_wdogx ciu_wdog;
/*
* Wait for other cores to print out information, but
* not too long. Do the soft reset before watchdog
* can trigger it.
*/
do {
ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
} while (ciu_wdog.s.cnt > 0x10000);
scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
scr |= 1 << 11; /* Indicate watchdog in bit 11 */
cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
}
}
static int octeon_wdt_cpu_to_irq(int cpu)
{
unsigned int coreid;
int node;
int irq;
coreid = cpu2core(cpu);
node = cpu_to_node(cpu);
if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
struct irq_domain *domain;
int hwirq;
domain = octeon_irq_get_block_domain(node,
WD_BLOCK_NUMBER);
hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
irq = irq_find_mapping(domain, hwirq);
} else {
irq = OCTEON_IRQ_WDOG0 + coreid;
}
return irq;
}
static int octeon_wdt_cpu_pre_down(unsigned int cpu)
{
unsigned int core;
int node;
union cvmx_ciu_wdogx ciu_wdog;
core = cpu2core(cpu);
node = cpu_to_node(cpu);
/* Poke the watchdog to clear out its state */
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
/* Disable the hardware. */
ciu_wdog.u64 = 0;
cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
return 0;
}
static int octeon_wdt_cpu_online(unsigned int cpu)
{
unsigned int core;
unsigned int irq;
union cvmx_ciu_wdogx ciu_wdog;
int node;
struct irq_domain *domain;
int hwirq;
core = cpu2core(cpu);
node = cpu_to_node(cpu);
octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
/* Disable it before doing anything with the interrupts. */
ciu_wdog.u64 = 0;
cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
per_cpu_countdown[cpu] = countdown_reset;
if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
/* Must get the domain for the watchdog block */
domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
/* Get a irq for the wd intsn (hardware interrupt) */
hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
irq = irq_create_mapping(domain, hwirq);
irqd_set_trigger_type(irq_get_irq_data(irq),
IRQ_TYPE_EDGE_RISING);
} else
irq = OCTEON_IRQ_WDOG0 + core;
if (request_irq(irq, octeon_wdt_poke_irq,
IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
panic("octeon_wdt: Couldn't obtain irq %d", irq);
/* Must set the irq affinity here */
if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
cpumask_t mask;
cpumask_clear(&mask);
cpumask_set_cpu(cpu, &mask);
irq_set_affinity(irq, &mask);
}
cpumask_set_cpu(cpu, &irq_enabled_cpus);
/* Poke the watchdog to clear out its state */
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
/* Finally enable the watchdog now that all handlers are installed */
ciu_wdog.u64 = 0;
ciu_wdog.s.len = timeout_cnt;
ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
return 0;
}
static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
{
int cpu;
int coreid;
int node;
if (disable)
return 0;
for_each_online_cpu(cpu) {
coreid = cpu2core(cpu);
node = cpu_to_node(cpu);
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
per_cpu_countdown[cpu] = countdown_reset;
if ((countdown_reset || !do_countdown) &&
!cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
/* We have to enable the irq */
enable_irq(octeon_wdt_cpu_to_irq(cpu));
cpumask_set_cpu(cpu, &irq_enabled_cpus);
}
}
return 0;
}
static void octeon_wdt_calc_parameters(int t)
{
unsigned int periods;
timeout_sec = max_timeout_sec;
/*
* Find the largest interrupt period, that can evenly divide
* the requested heartbeat time.
*/
while ((t % timeout_sec) != 0)
timeout_sec--;
periods = t / timeout_sec;
/*
* The last two periods are after the irq is disabled, and
* then to the nmi, so we subtract them off.
*/
countdown_reset = periods > 2 ? periods - 2 : 0;
heartbeat = t;
timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
}
static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int t)
{
int cpu;
int coreid;
union cvmx_ciu_wdogx ciu_wdog;
int node;
if (t <= 0)
return -1;
octeon_wdt_calc_parameters(t);
if (disable)
return 0;
for_each_online_cpu(cpu) {
coreid = cpu2core(cpu);
node = cpu_to_node(cpu);
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
ciu_wdog.u64 = 0;
ciu_wdog.s.len = timeout_cnt;
ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
}
octeon_wdt_ping(wdog); /* Get the irqs back on. */
return 0;
}
static int octeon_wdt_start(struct watchdog_device *wdog)
{
octeon_wdt_ping(wdog);
do_countdown = 1;
return 0;
}
static int octeon_wdt_stop(struct watchdog_device *wdog)
{
do_countdown = 0;
octeon_wdt_ping(wdog);
return 0;
}
static const struct watchdog_info octeon_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
.identity = "OCTEON",
};
static const struct watchdog_ops octeon_wdt_ops = {
.owner = THIS_MODULE,
.start = octeon_wdt_start,
.stop = octeon_wdt_stop,
.ping = octeon_wdt_ping,
.set_timeout = octeon_wdt_set_timeout,
};
static struct watchdog_device octeon_wdt = {
.info = &octeon_wdt_info,
.ops = &octeon_wdt_ops,
};
static enum cpuhp_state octeon_wdt_online;
/**
* octeon_wdt_init - Module/ driver initialization.
*
* Returns Zero on success
*/
static int __init octeon_wdt_init(void)
{
int ret;
octeon_wdt_bootvector = cvmx_boot_vector_get();
if (!octeon_wdt_bootvector) {
pr_err("Error: Cannot allocate boot vector.\n");
return -ENOMEM;
}
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
divisor = 0x200;
else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
divisor = 0x400;
else
divisor = 0x100;
/*
* Watchdog time expiration length = The 16 bits of LEN
* represent the most significant bits of a 24 bit decrementer
* that decrements every divisor cycle.
*
* Try for a timeout of 5 sec, if that fails a smaller number
* of even seconds,
*/
max_timeout_sec = 6;
do {
max_timeout_sec--;
timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
} while (timeout_cnt > 65535);
BUG_ON(timeout_cnt == 0);
octeon_wdt_calc_parameters(heartbeat);
pr_info("Initial granularity %d Sec\n", timeout_sec);
octeon_wdt.timeout = timeout_sec;
octeon_wdt.max_timeout = UINT_MAX;
watchdog_set_nowayout(&octeon_wdt, nowayout);
ret = watchdog_register_device(&octeon_wdt);
if (ret) {
pr_err("watchdog_register_device() failed: %d\n", ret);
return ret;
}
if (disable) {
pr_notice("disabled\n");
return 0;
}
cpumask_clear(&irq_enabled_cpus);
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
if (ret < 0)
goto err;
octeon_wdt_online = ret;
return 0;
err:
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
watchdog_unregister_device(&octeon_wdt);
return ret;
}
/**
* octeon_wdt_cleanup - Module / driver shutdown
*/
static void __exit octeon_wdt_cleanup(void)
{
watchdog_unregister_device(&octeon_wdt);
if (disable)
return;
cpuhp_remove_state(octeon_wdt_online);
/*
* Disable the boot-bus memory, the code it points to is soon
* to go missing.
*/
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
}
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Cavium Inc. <[email protected]>");
MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
module_init(octeon_wdt_init);
module_exit(octeon_wdt_cleanup);
| linux-master | drivers/watchdog/octeon-wdt-main.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MEN 14F021P00 Board Management Controller (BMC) Watchdog Driver.
*
* Copyright (C) 2014 MEN Mikro Elektronik Nuernberg GmbH
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#define DEVNAME "menf21bmc_wdt"
#define BMC_CMD_WD_ON 0x11
#define BMC_CMD_WD_OFF 0x12
#define BMC_CMD_WD_TRIG 0x13
#define BMC_CMD_WD_TIME 0x14
#define BMC_CMD_WD_STATE 0x17
#define BMC_WD_OFF_VAL 0x69
#define BMC_CMD_RST_RSN 0x92
#define BMC_WD_TIMEOUT_MIN 1 /* in sec */
#define BMC_WD_TIMEOUT_MAX 6553 /* in sec */
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
struct menf21bmc_wdt {
struct watchdog_device wdt;
struct i2c_client *i2c_client;
};
static int menf21bmc_wdt_set_bootstatus(struct menf21bmc_wdt *data)
{
int rst_rsn;
rst_rsn = i2c_smbus_read_byte_data(data->i2c_client, BMC_CMD_RST_RSN);
if (rst_rsn < 0)
return rst_rsn;
if (rst_rsn == 0x02)
data->wdt.bootstatus |= WDIOF_CARDRESET;
else if (rst_rsn == 0x05)
data->wdt.bootstatus |= WDIOF_EXTERN1;
else if (rst_rsn == 0x06)
data->wdt.bootstatus |= WDIOF_EXTERN2;
else if (rst_rsn == 0x0A)
data->wdt.bootstatus |= WDIOF_POWERUNDER;
return 0;
}
static int menf21bmc_wdt_start(struct watchdog_device *wdt)
{
struct menf21bmc_wdt *drv_data = watchdog_get_drvdata(wdt);
return i2c_smbus_write_byte(drv_data->i2c_client, BMC_CMD_WD_ON);
}
static int menf21bmc_wdt_stop(struct watchdog_device *wdt)
{
struct menf21bmc_wdt *drv_data = watchdog_get_drvdata(wdt);
return i2c_smbus_write_byte_data(drv_data->i2c_client,
BMC_CMD_WD_OFF, BMC_WD_OFF_VAL);
}
static int
menf21bmc_wdt_settimeout(struct watchdog_device *wdt, unsigned int timeout)
{
int ret;
struct menf21bmc_wdt *drv_data = watchdog_get_drvdata(wdt);
/*
* BMC Watchdog does have a resolution of 100ms.
* Watchdog API defines the timeout in seconds, so we have to
* multiply the value.
*/
ret = i2c_smbus_write_word_data(drv_data->i2c_client,
BMC_CMD_WD_TIME, timeout * 10);
if (ret < 0)
return ret;
wdt->timeout = timeout;
return 0;
}
static int menf21bmc_wdt_ping(struct watchdog_device *wdt)
{
struct menf21bmc_wdt *drv_data = watchdog_get_drvdata(wdt);
return i2c_smbus_write_byte(drv_data->i2c_client, BMC_CMD_WD_TRIG);
}
static const struct watchdog_info menf21bmc_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = DEVNAME,
};
static const struct watchdog_ops menf21bmc_wdt_ops = {
.owner = THIS_MODULE,
.start = menf21bmc_wdt_start,
.stop = menf21bmc_wdt_stop,
.ping = menf21bmc_wdt_ping,
.set_timeout = menf21bmc_wdt_settimeout,
};
static int menf21bmc_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret, bmc_timeout;
struct menf21bmc_wdt *drv_data;
struct i2c_client *i2c_client = to_i2c_client(dev->parent);
drv_data = devm_kzalloc(dev, sizeof(struct menf21bmc_wdt), GFP_KERNEL);
if (!drv_data)
return -ENOMEM;
drv_data->wdt.ops = &menf21bmc_wdt_ops;
drv_data->wdt.info = &menf21bmc_wdt_info;
drv_data->wdt.min_timeout = BMC_WD_TIMEOUT_MIN;
drv_data->wdt.max_timeout = BMC_WD_TIMEOUT_MAX;
drv_data->wdt.parent = dev;
drv_data->i2c_client = i2c_client;
/*
* Get the current wdt timeout value from the BMC because
* the BMC will save the value set before if the system restarts.
*/
bmc_timeout = i2c_smbus_read_word_data(drv_data->i2c_client,
BMC_CMD_WD_TIME);
if (bmc_timeout < 0) {
dev_err(dev, "failed to get current WDT timeout\n");
return bmc_timeout;
}
watchdog_init_timeout(&drv_data->wdt, bmc_timeout / 10, dev);
watchdog_set_nowayout(&drv_data->wdt, nowayout);
watchdog_set_drvdata(&drv_data->wdt, drv_data);
platform_set_drvdata(pdev, drv_data);
ret = menf21bmc_wdt_set_bootstatus(drv_data);
if (ret < 0) {
dev_err(dev, "failed to set Watchdog bootstatus\n");
return ret;
}
ret = devm_watchdog_register_device(dev, &drv_data->wdt);
if (ret)
return ret;
dev_info(dev, "MEN 14F021P00 BMC Watchdog device enabled\n");
return 0;
}
static void menf21bmc_wdt_shutdown(struct platform_device *pdev)
{
struct menf21bmc_wdt *drv_data = platform_get_drvdata(pdev);
i2c_smbus_write_word_data(drv_data->i2c_client,
BMC_CMD_WD_OFF, BMC_WD_OFF_VAL);
}
static struct platform_driver menf21bmc_wdt = {
.driver = {
.name = DEVNAME,
},
.probe = menf21bmc_wdt_probe,
.shutdown = menf21bmc_wdt_shutdown,
};
module_platform_driver(menf21bmc_wdt);
MODULE_DESCRIPTION("MEN 14F021P00 BMC Watchdog driver");
MODULE_AUTHOR("Andreas Werner <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:menf21bmc_wdt");
| linux-master | drivers/watchdog/menf21bmc_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* watchdog_dev.c
*
* (c) Copyright 2008-2011 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* (c) Copyright 2008-2011 Wim Van Sebroeck <[email protected]>.
*
* (c) Copyright 2021 Hewlett Packard Enterprise Development LP.
*
* This source code is part of the generic code that can be used
* by all the watchdog timer drivers.
*
* This part of the generic code takes care of the following
* misc device: /dev/watchdog.
*
* Based on source code of the following authors:
* Matt Domsch <[email protected]>,
* Rob Radez <[email protected]>,
* Rusty Lynch <[email protected]>
* Satyam Sharma <[email protected]>
* Randy Dunlap <[email protected]>
*
* Neither Alan Cox, CymruNet Ltd., Wim Van Sebroeck nor Iguana vzw.
* admit liability nor provide warranty for any of this software.
* This material is provided "AS-IS" and at no charge.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/cdev.h> /* For character device */
#include <linux/errno.h> /* For the -ENODEV/... values */
#include <linux/fs.h> /* For file operations */
#include <linux/init.h> /* For __init/__exit/... */
#include <linux/hrtimer.h> /* For hrtimers */
#include <linux/kernel.h> /* For printk/panic/... */
#include <linux/kstrtox.h> /* For kstrto* */
#include <linux/kthread.h> /* For kthread_work */
#include <linux/miscdevice.h> /* For handling misc devices */
#include <linux/module.h> /* For module stuff/... */
#include <linux/mutex.h> /* For mutexes */
#include <linux/slab.h> /* For memory functions */
#include <linux/types.h> /* For standard types (like size_t) */
#include <linux/watchdog.h> /* For watchdog specific items */
#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
#include "watchdog_core.h"
#include "watchdog_pretimeout.h"
#include <trace/events/watchdog.h>
/* the dev_t structure to store the dynamically allocated watchdog devices */
static dev_t watchdog_devt;
/* Reference to watchdog device behind /dev/watchdog */
static struct watchdog_core_data *old_wd_data;
static struct kthread_worker *watchdog_kworker;
static bool handle_boot_enabled =
IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED);
static unsigned open_timeout = CONFIG_WATCHDOG_OPEN_TIMEOUT;
static bool watchdog_past_open_deadline(struct watchdog_core_data *data)
{
return ktime_after(ktime_get(), data->open_deadline);
}
static void watchdog_set_open_deadline(struct watchdog_core_data *data)
{
data->open_deadline = open_timeout ?
ktime_get() + ktime_set(open_timeout, 0) : KTIME_MAX;
}
static inline bool watchdog_need_worker(struct watchdog_device *wdd)
{
/* All variables in milli-seconds */
unsigned int hm = wdd->max_hw_heartbeat_ms;
unsigned int t = wdd->timeout * 1000;
/*
* A worker to generate heartbeat requests is needed if all of the
* following conditions are true.
* - Userspace activated the watchdog.
* - The driver provided a value for the maximum hardware timeout, and
* thus is aware that the framework supports generating heartbeat
* requests.
* - Userspace requests a longer timeout than the hardware can handle.
*
* Alternatively, if userspace has not opened the watchdog
* device, we take care of feeding the watchdog if it is
* running.
*/
return (hm && watchdog_active(wdd) && t > hm) ||
(t && !watchdog_active(wdd) && watchdog_hw_running(wdd));
}
static ktime_t watchdog_next_keepalive(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
unsigned int timeout_ms = wdd->timeout * 1000;
ktime_t keepalive_interval;
ktime_t last_heartbeat, latest_heartbeat;
ktime_t virt_timeout;
unsigned int hw_heartbeat_ms;
if (watchdog_active(wdd))
virt_timeout = ktime_add(wd_data->last_keepalive,
ms_to_ktime(timeout_ms));
else
virt_timeout = wd_data->open_deadline;
hw_heartbeat_ms = min_not_zero(timeout_ms, wdd->max_hw_heartbeat_ms);
keepalive_interval = ms_to_ktime(hw_heartbeat_ms / 2);
/*
* To ensure that the watchdog times out wdd->timeout seconds
* after the most recent ping from userspace, the last
* worker ping has to come in hw_heartbeat_ms before this timeout.
*/
last_heartbeat = ktime_sub(virt_timeout, ms_to_ktime(hw_heartbeat_ms));
latest_heartbeat = ktime_sub(last_heartbeat, ktime_get());
if (ktime_before(latest_heartbeat, keepalive_interval))
return latest_heartbeat;
return keepalive_interval;
}
static inline void watchdog_update_worker(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
if (watchdog_need_worker(wdd)) {
ktime_t t = watchdog_next_keepalive(wdd);
if (t > 0)
hrtimer_start(&wd_data->timer, t,
HRTIMER_MODE_REL_HARD);
} else {
hrtimer_cancel(&wd_data->timer);
}
}
static int __watchdog_ping(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
ktime_t earliest_keepalive, now;
int err;
earliest_keepalive = ktime_add(wd_data->last_hw_keepalive,
ms_to_ktime(wdd->min_hw_heartbeat_ms));
now = ktime_get();
if (ktime_after(earliest_keepalive, now)) {
hrtimer_start(&wd_data->timer,
ktime_sub(earliest_keepalive, now),
HRTIMER_MODE_REL_HARD);
return 0;
}
wd_data->last_hw_keepalive = now;
if (wdd->ops->ping) {
err = wdd->ops->ping(wdd); /* ping the watchdog */
trace_watchdog_ping(wdd, err);
} else {
err = wdd->ops->start(wdd); /* restart watchdog */
trace_watchdog_start(wdd, err);
}
if (err == 0)
watchdog_hrtimer_pretimeout_start(wdd);
watchdog_update_worker(wdd);
return err;
}
/*
* watchdog_ping - ping the watchdog
* @wdd: The watchdog device to ping
*
* If the watchdog has no own ping operation then it needs to be
* restarted via the start operation. This wrapper function does
* exactly that.
* We only ping when the watchdog device is running.
* The caller must hold wd_data->lock.
*
* Return: 0 on success, error otherwise.
*/
static int watchdog_ping(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
if (!watchdog_hw_running(wdd))
return 0;
set_bit(_WDOG_KEEPALIVE, &wd_data->status);
wd_data->last_keepalive = ktime_get();
return __watchdog_ping(wdd);
}
static bool watchdog_worker_should_ping(struct watchdog_core_data *wd_data)
{
struct watchdog_device *wdd = wd_data->wdd;
if (!wdd)
return false;
if (watchdog_active(wdd))
return true;
return watchdog_hw_running(wdd) && !watchdog_past_open_deadline(wd_data);
}
static void watchdog_ping_work(struct kthread_work *work)
{
struct watchdog_core_data *wd_data;
wd_data = container_of(work, struct watchdog_core_data, work);
mutex_lock(&wd_data->lock);
if (watchdog_worker_should_ping(wd_data))
__watchdog_ping(wd_data->wdd);
mutex_unlock(&wd_data->lock);
}
static enum hrtimer_restart watchdog_timer_expired(struct hrtimer *timer)
{
struct watchdog_core_data *wd_data;
wd_data = container_of(timer, struct watchdog_core_data, timer);
kthread_queue_work(watchdog_kworker, &wd_data->work);
return HRTIMER_NORESTART;
}
/*
* watchdog_start - wrapper to start the watchdog
* @wdd: The watchdog device to start
*
* Start the watchdog if it is not active and mark it active.
* The caller must hold wd_data->lock.
*
* Return: 0 on success or a negative errno code for failure.
*/
static int watchdog_start(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
ktime_t started_at;
int err;
if (watchdog_active(wdd))
return 0;
set_bit(_WDOG_KEEPALIVE, &wd_data->status);
started_at = ktime_get();
if (watchdog_hw_running(wdd) && wdd->ops->ping) {
err = __watchdog_ping(wdd);
if (err == 0) {
set_bit(WDOG_ACTIVE, &wdd->status);
watchdog_hrtimer_pretimeout_start(wdd);
}
} else {
err = wdd->ops->start(wdd);
trace_watchdog_start(wdd, err);
if (err == 0) {
set_bit(WDOG_ACTIVE, &wdd->status);
set_bit(WDOG_HW_RUNNING, &wdd->status);
wd_data->last_keepalive = started_at;
wd_data->last_hw_keepalive = started_at;
watchdog_update_worker(wdd);
watchdog_hrtimer_pretimeout_start(wdd);
}
}
return err;
}
/*
* watchdog_stop - wrapper to stop the watchdog
* @wdd: The watchdog device to stop
*
* Stop the watchdog if it is still active and unmark it active.
* If the 'nowayout' feature was set, the watchdog cannot be stopped.
* The caller must hold wd_data->lock.
*
* Return: 0 on success or a negative errno code for failure.
*/
static int watchdog_stop(struct watchdog_device *wdd)
{
int err = 0;
if (!watchdog_active(wdd))
return 0;
if (test_bit(WDOG_NO_WAY_OUT, &wdd->status)) {
pr_info("watchdog%d: nowayout prevents watchdog being stopped!\n",
wdd->id);
return -EBUSY;
}
if (wdd->ops->stop) {
clear_bit(WDOG_HW_RUNNING, &wdd->status);
err = wdd->ops->stop(wdd);
trace_watchdog_stop(wdd, err);
} else {
set_bit(WDOG_HW_RUNNING, &wdd->status);
}
if (err == 0) {
clear_bit(WDOG_ACTIVE, &wdd->status);
watchdog_update_worker(wdd);
watchdog_hrtimer_pretimeout_stop(wdd);
}
return err;
}
/*
* watchdog_get_status - wrapper to get the watchdog status
* @wdd: The watchdog device to get the status from
*
* Get the watchdog's status flags.
* The caller must hold wd_data->lock.
*
* Return: watchdog's status flags.
*/
static unsigned int watchdog_get_status(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
unsigned int status;
if (wdd->ops->status)
status = wdd->ops->status(wdd);
else
status = wdd->bootstatus & (WDIOF_CARDRESET |
WDIOF_OVERHEAT |
WDIOF_FANFAULT |
WDIOF_EXTERN1 |
WDIOF_EXTERN2 |
WDIOF_POWERUNDER |
WDIOF_POWEROVER);
if (test_bit(_WDOG_ALLOW_RELEASE, &wd_data->status))
status |= WDIOF_MAGICCLOSE;
if (test_and_clear_bit(_WDOG_KEEPALIVE, &wd_data->status))
status |= WDIOF_KEEPALIVEPING;
if (IS_ENABLED(CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT))
status |= WDIOF_PRETIMEOUT;
return status;
}
/*
* watchdog_set_timeout - set the watchdog timer timeout
* @wdd: The watchdog device to set the timeout for
* @timeout: Timeout to set in seconds
*
* The caller must hold wd_data->lock.
*
* Return: 0 if successful, error otherwise.
*/
static int watchdog_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
int err = 0;
if (!(wdd->info->options & WDIOF_SETTIMEOUT))
return -EOPNOTSUPP;
if (watchdog_timeout_invalid(wdd, timeout))
return -EINVAL;
if (wdd->ops->set_timeout) {
err = wdd->ops->set_timeout(wdd, timeout);
trace_watchdog_set_timeout(wdd, timeout, err);
} else {
wdd->timeout = timeout;
/* Disable pretimeout if it doesn't fit the new timeout */
if (wdd->pretimeout >= wdd->timeout)
wdd->pretimeout = 0;
}
watchdog_update_worker(wdd);
return err;
}
/*
* watchdog_set_pretimeout - set the watchdog timer pretimeout
* @wdd: The watchdog device to set the timeout for
* @timeout: pretimeout to set in seconds
*
* Return: 0 if successful, error otherwise.
*/
static int watchdog_set_pretimeout(struct watchdog_device *wdd,
unsigned int timeout)
{
int err = 0;
if (!watchdog_have_pretimeout(wdd))
return -EOPNOTSUPP;
if (watchdog_pretimeout_invalid(wdd, timeout))
return -EINVAL;
if (wdd->ops->set_pretimeout && (wdd->info->options & WDIOF_PRETIMEOUT))
err = wdd->ops->set_pretimeout(wdd, timeout);
else
wdd->pretimeout = timeout;
return err;
}
/*
* watchdog_get_timeleft - wrapper to get the time left before a reboot
* @wdd: The watchdog device to get the remaining time from
* @timeleft: The time that's left
*
* Get the time before a watchdog will reboot (if not pinged).
* The caller must hold wd_data->lock.
*
* Return: 0 if successful, error otherwise.
*/
static int watchdog_get_timeleft(struct watchdog_device *wdd,
unsigned int *timeleft)
{
*timeleft = 0;
if (!wdd->ops->get_timeleft)
return -EOPNOTSUPP;
*timeleft = wdd->ops->get_timeleft(wdd);
return 0;
}
#ifdef CONFIG_WATCHDOG_SYSFS
static ssize_t nowayout_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", !!test_bit(WDOG_NO_WAY_OUT,
&wdd->status));
}
static ssize_t nowayout_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
unsigned int value;
int ret;
ret = kstrtouint(buf, 0, &value);
if (ret)
return ret;
if (value > 1)
return -EINVAL;
/* nowayout cannot be disabled once set */
if (test_bit(WDOG_NO_WAY_OUT, &wdd->status) && !value)
return -EPERM;
watchdog_set_nowayout(wdd, value);
return len;
}
static DEVICE_ATTR_RW(nowayout);
static ssize_t status_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
struct watchdog_core_data *wd_data = wdd->wd_data;
unsigned int status;
mutex_lock(&wd_data->lock);
status = watchdog_get_status(wdd);
mutex_unlock(&wd_data->lock);
return sysfs_emit(buf, "0x%x\n", status);
}
static DEVICE_ATTR_RO(status);
static ssize_t bootstatus_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%u\n", wdd->bootstatus);
}
static DEVICE_ATTR_RO(bootstatus);
static ssize_t timeleft_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
struct watchdog_core_data *wd_data = wdd->wd_data;
ssize_t status;
unsigned int val;
mutex_lock(&wd_data->lock);
status = watchdog_get_timeleft(wdd, &val);
mutex_unlock(&wd_data->lock);
if (!status)
status = sysfs_emit(buf, "%u\n", val);
return status;
}
static DEVICE_ATTR_RO(timeleft);
static ssize_t timeout_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%u\n", wdd->timeout);
}
static DEVICE_ATTR_RO(timeout);
static ssize_t min_timeout_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%u\n", wdd->min_timeout);
}
static DEVICE_ATTR_RO(min_timeout);
static ssize_t max_timeout_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%u\n", wdd->max_timeout);
}
static DEVICE_ATTR_RO(max_timeout);
static ssize_t pretimeout_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%u\n", wdd->pretimeout);
}
static DEVICE_ATTR_RO(pretimeout);
static ssize_t options_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "0x%x\n", wdd->info->options);
}
static DEVICE_ATTR_RO(options);
static ssize_t fw_version_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", wdd->info->firmware_version);
}
static DEVICE_ATTR_RO(fw_version);
static ssize_t identity_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return sysfs_emit(buf, "%s\n", wdd->info->identity);
}
static DEVICE_ATTR_RO(identity);
static ssize_t state_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
if (watchdog_active(wdd))
return sysfs_emit(buf, "active\n");
return sysfs_emit(buf, "inactive\n");
}
static DEVICE_ATTR_RO(state);
static ssize_t pretimeout_available_governors_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return watchdog_pretimeout_available_governors_get(buf);
}
static DEVICE_ATTR_RO(pretimeout_available_governors);
static ssize_t pretimeout_governor_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
return watchdog_pretimeout_governor_get(wdd, buf);
}
static ssize_t pretimeout_governor_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct watchdog_device *wdd = dev_get_drvdata(dev);
int ret = watchdog_pretimeout_governor_set(wdd, buf);
if (!ret)
ret = count;
return ret;
}
static DEVICE_ATTR_RW(pretimeout_governor);
static umode_t wdt_is_visible(struct kobject *kobj, struct attribute *attr,
int n)
{
struct device *dev = kobj_to_dev(kobj);
struct watchdog_device *wdd = dev_get_drvdata(dev);
umode_t mode = attr->mode;
if (attr == &dev_attr_timeleft.attr && !wdd->ops->get_timeleft)
mode = 0;
else if (attr == &dev_attr_pretimeout.attr && !watchdog_have_pretimeout(wdd))
mode = 0;
else if ((attr == &dev_attr_pretimeout_governor.attr ||
attr == &dev_attr_pretimeout_available_governors.attr) &&
(!watchdog_have_pretimeout(wdd) || !IS_ENABLED(CONFIG_WATCHDOG_PRETIMEOUT_GOV)))
mode = 0;
return mode;
}
static struct attribute *wdt_attrs[] = {
&dev_attr_state.attr,
&dev_attr_options.attr,
&dev_attr_fw_version.attr,
&dev_attr_identity.attr,
&dev_attr_timeout.attr,
&dev_attr_min_timeout.attr,
&dev_attr_max_timeout.attr,
&dev_attr_pretimeout.attr,
&dev_attr_timeleft.attr,
&dev_attr_bootstatus.attr,
&dev_attr_status.attr,
&dev_attr_nowayout.attr,
&dev_attr_pretimeout_governor.attr,
&dev_attr_pretimeout_available_governors.attr,
NULL,
};
static const struct attribute_group wdt_group = {
.attrs = wdt_attrs,
.is_visible = wdt_is_visible,
};
__ATTRIBUTE_GROUPS(wdt);
#else
#define wdt_groups NULL
#endif
/*
* watchdog_ioctl_op - call the watchdog drivers ioctl op if defined
* @wdd: The watchdog device to do the ioctl on
* @cmd: Watchdog command
* @arg: Argument pointer
*
* The caller must hold wd_data->lock.
*
* Return: 0 if successful, error otherwise.
*/
static int watchdog_ioctl_op(struct watchdog_device *wdd, unsigned int cmd,
unsigned long arg)
{
if (!wdd->ops->ioctl)
return -ENOIOCTLCMD;
return wdd->ops->ioctl(wdd, cmd, arg);
}
/*
* watchdog_write - writes to the watchdog
* @file: File from VFS
* @data: User address of data
* @len: Length of data
* @ppos: Pointer to the file offset
*
* A write to a watchdog device is defined as a keepalive ping.
* Writing the magic 'V' sequence allows the next close to turn
* off the watchdog (if 'nowayout' is not set).
*
* Return: @len if successful, error otherwise.
*/
static ssize_t watchdog_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
struct watchdog_core_data *wd_data = file->private_data;
struct watchdog_device *wdd;
int err;
size_t i;
char c;
if (len == 0)
return 0;
/*
* Note: just in case someone wrote the magic character
* five months ago...
*/
clear_bit(_WDOG_ALLOW_RELEASE, &wd_data->status);
/* scan to see whether or not we got the magic character */
for (i = 0; i != len; i++) {
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
set_bit(_WDOG_ALLOW_RELEASE, &wd_data->status);
}
/* someone wrote to us, so we send the watchdog a keepalive ping */
err = -ENODEV;
mutex_lock(&wd_data->lock);
wdd = wd_data->wdd;
if (wdd)
err = watchdog_ping(wdd);
mutex_unlock(&wd_data->lock);
if (err < 0)
return err;
return len;
}
/*
* watchdog_ioctl - handle the different ioctl's for the watchdog device
* @file: File handle to the device
* @cmd: Watchdog command
* @arg: Argument pointer
*
* The watchdog API defines a common set of functions for all watchdogs
* according to their available features.
*
* Return: 0 if successful, error otherwise.
*/
static long watchdog_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct watchdog_core_data *wd_data = file->private_data;
void __user *argp = (void __user *)arg;
struct watchdog_device *wdd;
int __user *p = argp;
unsigned int val;
int err;
mutex_lock(&wd_data->lock);
wdd = wd_data->wdd;
if (!wdd) {
err = -ENODEV;
goto out_ioctl;
}
err = watchdog_ioctl_op(wdd, cmd, arg);
if (err != -ENOIOCTLCMD)
goto out_ioctl;
switch (cmd) {
case WDIOC_GETSUPPORT:
err = copy_to_user(argp, wdd->info,
sizeof(struct watchdog_info)) ? -EFAULT : 0;
break;
case WDIOC_GETSTATUS:
val = watchdog_get_status(wdd);
err = put_user(val, p);
break;
case WDIOC_GETBOOTSTATUS:
err = put_user(wdd->bootstatus, p);
break;
case WDIOC_SETOPTIONS:
if (get_user(val, p)) {
err = -EFAULT;
break;
}
if (val & WDIOS_DISABLECARD) {
err = watchdog_stop(wdd);
if (err < 0)
break;
}
if (val & WDIOS_ENABLECARD)
err = watchdog_start(wdd);
break;
case WDIOC_KEEPALIVE:
if (!(wdd->info->options & WDIOF_KEEPALIVEPING)) {
err = -EOPNOTSUPP;
break;
}
err = watchdog_ping(wdd);
break;
case WDIOC_SETTIMEOUT:
if (get_user(val, p)) {
err = -EFAULT;
break;
}
err = watchdog_set_timeout(wdd, val);
if (err < 0)
break;
/* If the watchdog is active then we send a keepalive ping
* to make sure that the watchdog keep's running (and if
* possible that it takes the new timeout) */
err = watchdog_ping(wdd);
if (err < 0)
break;
fallthrough;
case WDIOC_GETTIMEOUT:
/* timeout == 0 means that we don't know the timeout */
if (wdd->timeout == 0) {
err = -EOPNOTSUPP;
break;
}
err = put_user(wdd->timeout, p);
break;
case WDIOC_GETTIMELEFT:
err = watchdog_get_timeleft(wdd, &val);
if (err < 0)
break;
err = put_user(val, p);
break;
case WDIOC_SETPRETIMEOUT:
if (get_user(val, p)) {
err = -EFAULT;
break;
}
err = watchdog_set_pretimeout(wdd, val);
break;
case WDIOC_GETPRETIMEOUT:
err = put_user(wdd->pretimeout, p);
break;
default:
err = -ENOTTY;
break;
}
out_ioctl:
mutex_unlock(&wd_data->lock);
return err;
}
/*
* watchdog_open - open the /dev/watchdog* devices
* @inode: Inode of device
* @file: File handle to device
*
* When the /dev/watchdog* device gets opened, we start the watchdog.
* Watch out: the /dev/watchdog device is single open, so we make sure
* it can only be opened once.
*
* Return: 0 if successful, error otherwise.
*/
static int watchdog_open(struct inode *inode, struct file *file)
{
struct watchdog_core_data *wd_data;
struct watchdog_device *wdd;
bool hw_running;
int err;
/* Get the corresponding watchdog device */
if (imajor(inode) == MISC_MAJOR)
wd_data = old_wd_data;
else
wd_data = container_of(inode->i_cdev, struct watchdog_core_data,
cdev);
/* the watchdog is single open! */
if (test_and_set_bit(_WDOG_DEV_OPEN, &wd_data->status))
return -EBUSY;
wdd = wd_data->wdd;
/*
* If the /dev/watchdog device is open, we don't want the module
* to be unloaded.
*/
hw_running = watchdog_hw_running(wdd);
if (!hw_running && !try_module_get(wdd->ops->owner)) {
err = -EBUSY;
goto out_clear;
}
err = watchdog_start(wdd);
if (err < 0)
goto out_mod;
file->private_data = wd_data;
if (!hw_running)
get_device(&wd_data->dev);
/*
* open_timeout only applies for the first open from
* userspace. Set open_deadline to infinity so that the kernel
* will take care of an always-running hardware watchdog in
* case the device gets magic-closed or WDIOS_DISABLECARD is
* applied.
*/
wd_data->open_deadline = KTIME_MAX;
/* dev/watchdog is a virtual (and thus non-seekable) filesystem */
return stream_open(inode, file);
out_mod:
module_put(wd_data->wdd->ops->owner);
out_clear:
clear_bit(_WDOG_DEV_OPEN, &wd_data->status);
return err;
}
static void watchdog_core_data_release(struct device *dev)
{
struct watchdog_core_data *wd_data;
wd_data = container_of(dev, struct watchdog_core_data, dev);
kfree(wd_data);
}
/*
* watchdog_release - release the watchdog device
* @inode: Inode of device
* @file: File handle to device
*
* This is the code for when /dev/watchdog gets closed. We will only
* stop the watchdog when we have received the magic char (and nowayout
* was not set), else the watchdog will keep running.
*
* Always returns 0.
*/
static int watchdog_release(struct inode *inode, struct file *file)
{
struct watchdog_core_data *wd_data = file->private_data;
struct watchdog_device *wdd;
int err = -EBUSY;
bool running;
mutex_lock(&wd_data->lock);
wdd = wd_data->wdd;
if (!wdd)
goto done;
/*
* We only stop the watchdog if we received the magic character
* or if WDIOF_MAGICCLOSE is not set. If nowayout was set then
* watchdog_stop will fail.
*/
if (!watchdog_active(wdd))
err = 0;
else if (test_and_clear_bit(_WDOG_ALLOW_RELEASE, &wd_data->status) ||
!(wdd->info->options & WDIOF_MAGICCLOSE))
err = watchdog_stop(wdd);
/* If the watchdog was not stopped, send a keepalive ping */
if (err < 0) {
pr_crit("watchdog%d: watchdog did not stop!\n", wdd->id);
watchdog_ping(wdd);
}
watchdog_update_worker(wdd);
/* make sure that /dev/watchdog can be re-opened */
clear_bit(_WDOG_DEV_OPEN, &wd_data->status);
done:
running = wdd && watchdog_hw_running(wdd);
mutex_unlock(&wd_data->lock);
/*
* Allow the owner module to be unloaded again unless the watchdog
* is still running. If the watchdog is still running, it can not
* be stopped, and its driver must not be unloaded.
*/
if (!running) {
module_put(wd_data->cdev.owner);
put_device(&wd_data->dev);
}
return 0;
}
static const struct file_operations watchdog_fops = {
.owner = THIS_MODULE,
.write = watchdog_write,
.unlocked_ioctl = watchdog_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = watchdog_open,
.release = watchdog_release,
};
static struct miscdevice watchdog_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &watchdog_fops,
};
static struct class watchdog_class = {
.name = "watchdog",
.dev_groups = wdt_groups,
};
/*
* watchdog_cdev_register - register watchdog character device
* @wdd: Watchdog device
*
* Register a watchdog character device including handling the legacy
* /dev/watchdog node. /dev/watchdog is actually a miscdevice and
* thus we set it up like that.
*
* Return: 0 if successful, error otherwise.
*/
static int watchdog_cdev_register(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data;
int err;
wd_data = kzalloc(sizeof(struct watchdog_core_data), GFP_KERNEL);
if (!wd_data)
return -ENOMEM;
mutex_init(&wd_data->lock);
wd_data->wdd = wdd;
wdd->wd_data = wd_data;
if (IS_ERR_OR_NULL(watchdog_kworker)) {
kfree(wd_data);
return -ENODEV;
}
device_initialize(&wd_data->dev);
wd_data->dev.devt = MKDEV(MAJOR(watchdog_devt), wdd->id);
wd_data->dev.class = &watchdog_class;
wd_data->dev.parent = wdd->parent;
wd_data->dev.groups = wdd->groups;
wd_data->dev.release = watchdog_core_data_release;
dev_set_drvdata(&wd_data->dev, wdd);
err = dev_set_name(&wd_data->dev, "watchdog%d", wdd->id);
if (err) {
put_device(&wd_data->dev);
return err;
}
kthread_init_work(&wd_data->work, watchdog_ping_work);
hrtimer_init(&wd_data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_HARD);
wd_data->timer.function = watchdog_timer_expired;
watchdog_hrtimer_pretimeout_init(wdd);
if (wdd->id == 0) {
old_wd_data = wd_data;
watchdog_miscdev.parent = wdd->parent;
err = misc_register(&watchdog_miscdev);
if (err != 0) {
pr_err("%s: cannot register miscdev on minor=%d (err=%d).\n",
wdd->info->identity, WATCHDOG_MINOR, err);
if (err == -EBUSY)
pr_err("%s: a legacy watchdog module is probably present.\n",
wdd->info->identity);
old_wd_data = NULL;
put_device(&wd_data->dev);
return err;
}
}
/* Fill in the data structures */
cdev_init(&wd_data->cdev, &watchdog_fops);
/* Add the device */
err = cdev_device_add(&wd_data->cdev, &wd_data->dev);
if (err) {
pr_err("watchdog%d unable to add device %d:%d\n",
wdd->id, MAJOR(watchdog_devt), wdd->id);
if (wdd->id == 0) {
misc_deregister(&watchdog_miscdev);
old_wd_data = NULL;
}
put_device(&wd_data->dev);
return err;
}
wd_data->cdev.owner = wdd->ops->owner;
/* Record time of most recent heartbeat as 'just before now'. */
wd_data->last_hw_keepalive = ktime_sub(ktime_get(), 1);
watchdog_set_open_deadline(wd_data);
/*
* If the watchdog is running, prevent its driver from being unloaded,
* and schedule an immediate ping.
*/
if (watchdog_hw_running(wdd)) {
__module_get(wdd->ops->owner);
get_device(&wd_data->dev);
if (handle_boot_enabled)
hrtimer_start(&wd_data->timer, 0,
HRTIMER_MODE_REL_HARD);
else
pr_info("watchdog%d running and kernel based pre-userspace handler disabled\n",
wdd->id);
}
return 0;
}
/*
* watchdog_cdev_unregister - unregister watchdog character device
* @wdd: Watchdog device
*
* Unregister watchdog character device and if needed the legacy
* /dev/watchdog device.
*/
static void watchdog_cdev_unregister(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
cdev_device_del(&wd_data->cdev, &wd_data->dev);
if (wdd->id == 0) {
misc_deregister(&watchdog_miscdev);
old_wd_data = NULL;
}
if (watchdog_active(wdd) &&
test_bit(WDOG_STOP_ON_UNREGISTER, &wdd->status)) {
watchdog_stop(wdd);
}
watchdog_hrtimer_pretimeout_stop(wdd);
mutex_lock(&wd_data->lock);
wd_data->wdd = NULL;
wdd->wd_data = NULL;
mutex_unlock(&wd_data->lock);
hrtimer_cancel(&wd_data->timer);
kthread_cancel_work_sync(&wd_data->work);
put_device(&wd_data->dev);
}
/**
* watchdog_dev_register - register a watchdog device
* @wdd: Watchdog device
*
* Register a watchdog device including handling the legacy
* /dev/watchdog node. /dev/watchdog is actually a miscdevice and
* thus we set it up like that.
*
* Return: 0 if successful, error otherwise.
*/
int watchdog_dev_register(struct watchdog_device *wdd)
{
int ret;
ret = watchdog_cdev_register(wdd);
if (ret)
return ret;
ret = watchdog_register_pretimeout(wdd);
if (ret)
watchdog_cdev_unregister(wdd);
return ret;
}
/**
* watchdog_dev_unregister - unregister a watchdog device
* @wdd: watchdog device
*
* Unregister watchdog device and if needed the legacy
* /dev/watchdog device.
*/
void watchdog_dev_unregister(struct watchdog_device *wdd)
{
watchdog_unregister_pretimeout(wdd);
watchdog_cdev_unregister(wdd);
}
/**
* watchdog_set_last_hw_keepalive - set last HW keepalive time for watchdog
* @wdd: Watchdog device
* @last_ping_ms: Time since last HW heartbeat
*
* Adjusts the last known HW keepalive time for a watchdog timer.
* This is needed if the watchdog is already running when the probe
* function is called, and it can't be pinged immediately. This
* function must be called immediately after watchdog registration,
* and min_hw_heartbeat_ms must be set for this to be useful.
*
* Return: 0 if successful, error otherwise.
*/
int watchdog_set_last_hw_keepalive(struct watchdog_device *wdd,
unsigned int last_ping_ms)
{
struct watchdog_core_data *wd_data;
ktime_t now;
if (!wdd)
return -EINVAL;
wd_data = wdd->wd_data;
now = ktime_get();
wd_data->last_hw_keepalive = ktime_sub(now, ms_to_ktime(last_ping_ms));
if (watchdog_hw_running(wdd) && handle_boot_enabled)
return __watchdog_ping(wdd);
return 0;
}
EXPORT_SYMBOL_GPL(watchdog_set_last_hw_keepalive);
/**
* watchdog_dev_init - init dev part of watchdog core
*
* Allocate a range of chardev nodes to use for watchdog devices.
*
* Return: 0 if successful, error otherwise.
*/
int __init watchdog_dev_init(void)
{
int err;
watchdog_kworker = kthread_create_worker(0, "watchdogd");
if (IS_ERR(watchdog_kworker)) {
pr_err("Failed to create watchdog kworker\n");
return PTR_ERR(watchdog_kworker);
}
sched_set_fifo(watchdog_kworker->task);
err = class_register(&watchdog_class);
if (err < 0) {
pr_err("couldn't register class\n");
goto err_register;
}
err = alloc_chrdev_region(&watchdog_devt, 0, MAX_DOGS, "watchdog");
if (err < 0) {
pr_err("watchdog: unable to allocate char dev region\n");
goto err_alloc;
}
return 0;
err_alloc:
class_unregister(&watchdog_class);
err_register:
kthread_destroy_worker(watchdog_kworker);
return err;
}
/**
* watchdog_dev_exit - exit dev part of watchdog core
*
* Release the range of chardev nodes used for watchdog devices.
*/
void __exit watchdog_dev_exit(void)
{
unregister_chrdev_region(watchdog_devt, MAX_DOGS);
class_unregister(&watchdog_class);
kthread_destroy_worker(watchdog_kworker);
}
int watchdog_dev_suspend(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
int ret = 0;
if (!wdd->wd_data)
return -ENODEV;
/* ping for the last time before suspend */
mutex_lock(&wd_data->lock);
if (watchdog_worker_should_ping(wd_data))
ret = __watchdog_ping(wd_data->wdd);
mutex_unlock(&wd_data->lock);
if (ret)
return ret;
/*
* make sure that watchdog worker will not kick in when the wdog is
* suspended
*/
hrtimer_cancel(&wd_data->timer);
kthread_cancel_work_sync(&wd_data->work);
return 0;
}
int watchdog_dev_resume(struct watchdog_device *wdd)
{
struct watchdog_core_data *wd_data = wdd->wd_data;
int ret = 0;
if (!wdd->wd_data)
return -ENODEV;
/*
* __watchdog_ping will also retrigger hrtimer and therefore restore the
* ping worker if needed.
*/
mutex_lock(&wd_data->lock);
if (watchdog_worker_should_ping(wd_data))
ret = __watchdog_ping(wd_data->wdd);
mutex_unlock(&wd_data->lock);
return ret;
}
module_param(handle_boot_enabled, bool, 0444);
MODULE_PARM_DESC(handle_boot_enabled,
"Watchdog core auto-updates boot enabled watchdogs before userspace takes over (default="
__MODULE_STRING(IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) ")");
module_param(open_timeout, uint, 0644);
MODULE_PARM_DESC(open_timeout,
"Maximum time (in seconds, 0 means infinity) for userspace to take over a running watchdog (default="
__MODULE_STRING(CONFIG_WATCHDOG_OPEN_TIMEOUT) ")");
| linux-master | drivers/watchdog/watchdog_dev.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Broadcom Corporation
*
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/platform_data/bcm7038_wdt.h>
#include <linux/pm.h>
#include <linux/watchdog.h>
#define WDT_START_1 0xff00
#define WDT_START_2 0x00ff
#define WDT_STOP_1 0xee00
#define WDT_STOP_2 0x00ee
#define WDT_TIMEOUT_REG 0x0
#define WDT_CMD_REG 0x4
#define WDT_MIN_TIMEOUT 1 /* seconds */
#define WDT_DEFAULT_TIMEOUT 30 /* seconds */
#define WDT_DEFAULT_RATE 27000000
struct bcm7038_watchdog {
void __iomem *base;
struct watchdog_device wdd;
u32 rate;
struct clk *clk;
};
static bool nowayout = WATCHDOG_NOWAYOUT;
static inline void bcm7038_wdt_write(u32 value, void __iomem *addr)
{
/* MIPS chips strapped for BE will automagically configure the
* peripheral registers for CPU-native byte order.
*/
if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
__raw_writel(value, addr);
else
writel_relaxed(value, addr);
}
static inline u32 bcm7038_wdt_read(void __iomem *addr)
{
if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
return __raw_readl(addr);
else
return readl_relaxed(addr);
}
static void bcm7038_wdt_set_timeout_reg(struct watchdog_device *wdog)
{
struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
u32 timeout;
timeout = wdt->rate * wdog->timeout;
bcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG);
}
static int bcm7038_wdt_ping(struct watchdog_device *wdog)
{
struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
bcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG);
bcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG);
return 0;
}
static int bcm7038_wdt_start(struct watchdog_device *wdog)
{
bcm7038_wdt_set_timeout_reg(wdog);
bcm7038_wdt_ping(wdog);
return 0;
}
static int bcm7038_wdt_stop(struct watchdog_device *wdog)
{
struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
bcm7038_wdt_write(WDT_STOP_1, wdt->base + WDT_CMD_REG);
bcm7038_wdt_write(WDT_STOP_2, wdt->base + WDT_CMD_REG);
return 0;
}
static int bcm7038_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int t)
{
/* Can't modify timeout value if watchdog timer is running */
bcm7038_wdt_stop(wdog);
wdog->timeout = t;
bcm7038_wdt_start(wdog);
return 0;
}
static unsigned int bcm7038_wdt_get_timeleft(struct watchdog_device *wdog)
{
struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
u32 time_left;
time_left = bcm7038_wdt_read(wdt->base + WDT_CMD_REG);
return time_left / wdt->rate;
}
static const struct watchdog_info bcm7038_wdt_info = {
.identity = "Broadcom BCM7038 Watchdog Timer",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE
};
static const struct watchdog_ops bcm7038_wdt_ops = {
.owner = THIS_MODULE,
.start = bcm7038_wdt_start,
.stop = bcm7038_wdt_stop,
.set_timeout = bcm7038_wdt_set_timeout,
.get_timeleft = bcm7038_wdt_get_timeleft,
};
static int bcm7038_wdt_probe(struct platform_device *pdev)
{
struct bcm7038_wdt_platform_data *pdata = pdev->dev.platform_data;
struct device *dev = &pdev->dev;
struct bcm7038_watchdog *wdt;
const char *clk_name = NULL;
int err;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
platform_set_drvdata(pdev, wdt);
wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
if (pdata && pdata->clk_name)
clk_name = pdata->clk_name;
wdt->clk = devm_clk_get_enabled(dev, clk_name);
/* If unable to get clock, use default frequency */
if (!IS_ERR(wdt->clk)) {
wdt->rate = clk_get_rate(wdt->clk);
/* Prevent divide-by-zero exception */
if (!wdt->rate)
wdt->rate = WDT_DEFAULT_RATE;
} else {
wdt->rate = WDT_DEFAULT_RATE;
wdt->clk = NULL;
}
wdt->wdd.info = &bcm7038_wdt_info;
wdt->wdd.ops = &bcm7038_wdt_ops;
wdt->wdd.min_timeout = WDT_MIN_TIMEOUT;
wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
wdt->wdd.max_timeout = 0xffffffff / wdt->rate;
wdt->wdd.parent = dev;
watchdog_set_drvdata(&wdt->wdd, wdt);
watchdog_stop_on_reboot(&wdt->wdd);
watchdog_stop_on_unregister(&wdt->wdd);
err = devm_watchdog_register_device(dev, &wdt->wdd);
if (err)
return err;
dev_info(dev, "Registered BCM7038 Watchdog\n");
return 0;
}
static int bcm7038_wdt_suspend(struct device *dev)
{
struct bcm7038_watchdog *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
return bcm7038_wdt_stop(&wdt->wdd);
return 0;
}
static int bcm7038_wdt_resume(struct device *dev)
{
struct bcm7038_watchdog *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
return bcm7038_wdt_start(&wdt->wdd);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_ops,
bcm7038_wdt_suspend, bcm7038_wdt_resume);
static const struct of_device_id bcm7038_wdt_match[] = {
{ .compatible = "brcm,bcm6345-wdt" },
{ .compatible = "brcm,bcm7038-wdt" },
{},
};
MODULE_DEVICE_TABLE(of, bcm7038_wdt_match);
static const struct platform_device_id bcm7038_wdt_devtype[] = {
{ .name = "bcm63xx-wdt" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(platform, bcm7038_wdt_devtype);
static struct platform_driver bcm7038_wdt_driver = {
.probe = bcm7038_wdt_probe,
.id_table = bcm7038_wdt_devtype,
.driver = {
.name = "bcm7038-wdt",
.of_match_table = bcm7038_wdt_match,
.pm = pm_sleep_ptr(&bcm7038_wdt_pm_ops),
}
};
module_platform_driver(bcm7038_wdt_driver);
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Driver for Broadcom 7038 SoCs Watchdog");
MODULE_AUTHOR("Justin Chen");
| linux-master | drivers/watchdog/bcm7038_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for STM32 Independent Watchdog
*
* Copyright (C) STMicroelectronics 2017
* Author: Yannick Fertre <[email protected]> for STMicroelectronics.
*
* This driver is based on tegra_wdt.c
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
/* IWDG registers */
#define IWDG_KR 0x00 /* Key register */
#define IWDG_PR 0x04 /* Prescaler Register */
#define IWDG_RLR 0x08 /* ReLoad Register */
#define IWDG_SR 0x0C /* Status Register */
#define IWDG_WINR 0x10 /* Windows Register */
/* IWDG_KR register bit mask */
#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
#define KR_KEY_EWA 0x5555 /* write access enable */
#define KR_KEY_DWA 0x0000 /* write access disable */
/* IWDG_PR register */
#define PR_SHIFT 2
#define PR_MIN BIT(PR_SHIFT)
/* IWDG_RLR register values */
#define RLR_MIN 0x2 /* min value recommended */
#define RLR_MAX GENMASK(11, 0) /* max value of reload register */
/* IWDG_SR register bit mask */
#define SR_PVU BIT(0) /* Watchdog prescaler value update */
#define SR_RVU BIT(1) /* Watchdog counter reload value update */
/* set timeout to 100000 us */
#define TIMEOUT_US 100000
#define SLEEP_US 1000
struct stm32_iwdg_data {
bool has_pclk;
u32 max_prescaler;
};
static const struct stm32_iwdg_data stm32_iwdg_data = {
.has_pclk = false,
.max_prescaler = 256,
};
static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
.has_pclk = true,
.max_prescaler = 1024,
};
struct stm32_iwdg {
struct watchdog_device wdd;
const struct stm32_iwdg_data *data;
void __iomem *regs;
struct clk *clk_lsi;
struct clk *clk_pclk;
unsigned int rate;
};
static inline u32 reg_read(void __iomem *base, u32 reg)
{
return readl_relaxed(base + reg);
}
static inline void reg_write(void __iomem *base, u32 reg, u32 val)
{
writel_relaxed(val, base + reg);
}
static int stm32_iwdg_start(struct watchdog_device *wdd)
{
struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
int ret;
dev_dbg(wdd->parent, "%s\n", __func__);
tout = clamp_t(unsigned int, wdd->timeout,
wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
presc = roundup_pow_of_two(presc);
iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
/* enable write access */
reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
/* set prescaler & reload registers */
reg_write(wdt->regs, IWDG_PR, iwdg_pr);
reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
/* wait for the registers to be updated (max 100ms) */
ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
!(iwdg_sr & (SR_PVU | SR_RVU)),
SLEEP_US, TIMEOUT_US);
if (ret) {
dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
return ret;
}
/* reload watchdog */
reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
return 0;
}
static int stm32_iwdg_ping(struct watchdog_device *wdd)
{
struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
dev_dbg(wdd->parent, "%s\n", __func__);
/* reload watchdog */
reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
return 0;
}
static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
wdd->timeout = timeout;
if (watchdog_active(wdd))
return stm32_iwdg_start(wdd);
return 0;
}
static void stm32_clk_disable_unprepare(void *data)
{
clk_disable_unprepare(data);
}
static int stm32_iwdg_clk_init(struct platform_device *pdev,
struct stm32_iwdg *wdt)
{
struct device *dev = &pdev->dev;
u32 ret;
wdt->clk_lsi = devm_clk_get(dev, "lsi");
if (IS_ERR(wdt->clk_lsi))
return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
/* optional peripheral clock */
if (wdt->data->has_pclk) {
wdt->clk_pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(wdt->clk_pclk))
return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
"Unable to get pclk clock\n");
ret = clk_prepare_enable(wdt->clk_pclk);
if (ret) {
dev_err(dev, "Unable to prepare pclk clock\n");
return ret;
}
ret = devm_add_action_or_reset(dev,
stm32_clk_disable_unprepare,
wdt->clk_pclk);
if (ret)
return ret;
}
ret = clk_prepare_enable(wdt->clk_lsi);
if (ret) {
dev_err(dev, "Unable to prepare lsi clock\n");
return ret;
}
ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
wdt->clk_lsi);
if (ret)
return ret;
wdt->rate = clk_get_rate(wdt->clk_lsi);
return 0;
}
static const struct watchdog_info stm32_iwdg_info = {
.options = WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "STM32 Independent Watchdog",
};
static const struct watchdog_ops stm32_iwdg_ops = {
.owner = THIS_MODULE,
.start = stm32_iwdg_start,
.ping = stm32_iwdg_ping,
.set_timeout = stm32_iwdg_set_timeout,
};
static const struct of_device_id stm32_iwdg_of_match[] = {
{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
{ /* end node */ }
};
MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
static int stm32_iwdg_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct stm32_iwdg *wdt;
int ret;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->data = of_device_get_match_data(&pdev->dev);
if (!wdt->data)
return -ENODEV;
/* This is the timer base. */
wdt->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->regs))
return PTR_ERR(wdt->regs);
ret = stm32_iwdg_clk_init(pdev, wdt);
if (ret)
return ret;
/* Initialize struct watchdog_device. */
wdd = &wdt->wdd;
wdd->parent = dev;
wdd->info = &stm32_iwdg_info;
wdd->ops = &stm32_iwdg_ops;
wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
1000) / wdt->rate;
watchdog_set_drvdata(wdd, wdt);
watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
watchdog_init_timeout(wdd, 0, dev);
/*
* In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
* (Means U-Boot/bootloaders leaves the watchdog running)
* When we get here we should make a decision to prevent
* any side effects before user space daemon will take care of it.
* The best option, taking into consideration that there is no
* way to read values back from hardware, is to enforce watchdog
* being run with deterministic values.
*/
if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
ret = stm32_iwdg_start(wdd);
if (ret)
return ret;
/* Make sure the watchdog is serviced */
set_bit(WDOG_HW_RUNNING, &wdd->status);
}
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
return 0;
}
static struct platform_driver stm32_iwdg_driver = {
.probe = stm32_iwdg_probe,
.driver = {
.name = "iwdg",
.of_match_table = stm32_iwdg_of_match,
},
};
module_platform_driver(stm32_iwdg_driver);
MODULE_AUTHOR("Yannick Fertre <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/stm32_iwdg.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Ralink MT7621/MT7628 built-in hardware watchdog timer
*
* Copyright (C) 2014 John Crispin <[email protected]>
*
* This driver was based on: drivers/watchdog/rt2880_wdt.c
*/
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#define SYSC_RSTSTAT 0x38
#define WDT_RST_CAUSE BIT(1)
#define RALINK_WDT_TIMEOUT 30
#define TIMER_REG_TMRSTAT 0x00
#define TIMER_REG_TMR1LOAD 0x24
#define TIMER_REG_TMR1CTL 0x20
#define TMR1CTL_ENABLE BIT(7)
#define TMR1CTL_RESTART BIT(9)
#define TMR1CTL_PRESCALE_SHIFT 16
struct mt7621_wdt_data {
void __iomem *base;
struct reset_control *rst;
struct regmap *sysc;
struct watchdog_device wdt;
};
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
{
iowrite32(val, base + reg);
}
static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
{
return ioread32(base + reg);
}
static int mt7621_wdt_ping(struct watchdog_device *w)
{
struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
return 0;
}
static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
{
struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
w->timeout = t;
rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
mt7621_wdt_ping(w);
return 0;
}
static int mt7621_wdt_start(struct watchdog_device *w)
{
struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
u32 t;
/* set the prescaler to 1ms == 1000us */
rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
mt7621_wdt_set_timeout(w, w->timeout);
t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
t |= TMR1CTL_ENABLE;
rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
return 0;
}
static int mt7621_wdt_stop(struct watchdog_device *w)
{
struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
u32 t;
mt7621_wdt_ping(w);
t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
t &= ~TMR1CTL_ENABLE;
rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
return 0;
}
static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
{
u32 val;
regmap_read(d->sysc, SYSC_RSTSTAT, &val);
if (val & WDT_RST_CAUSE)
return WDIOF_CARDRESET;
return 0;
}
static int mt7621_wdt_is_running(struct watchdog_device *w)
{
struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
}
static const struct watchdog_info mt7621_wdt_info = {
.identity = "Mediatek Watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops mt7621_wdt_ops = {
.owner = THIS_MODULE,
.start = mt7621_wdt_start,
.stop = mt7621_wdt_stop,
.ping = mt7621_wdt_ping,
.set_timeout = mt7621_wdt_set_timeout,
};
static int mt7621_wdt_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct watchdog_device *mt7621_wdt;
struct mt7621_wdt_data *drvdata;
int err;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
if (IS_ERR(drvdata->sysc)) {
drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
if (IS_ERR(drvdata->sysc))
return PTR_ERR(drvdata->sysc);
}
drvdata->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(drvdata->base))
return PTR_ERR(drvdata->base);
drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
if (!IS_ERR(drvdata->rst))
reset_control_deassert(drvdata->rst);
mt7621_wdt = &drvdata->wdt;
mt7621_wdt->info = &mt7621_wdt_info;
mt7621_wdt->ops = &mt7621_wdt_ops;
mt7621_wdt->min_timeout = 1;
mt7621_wdt->max_timeout = 0xfffful / 1000;
mt7621_wdt->parent = dev;
mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);
watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
watchdog_set_nowayout(mt7621_wdt, nowayout);
watchdog_set_drvdata(mt7621_wdt, drvdata);
if (mt7621_wdt_is_running(mt7621_wdt)) {
/*
* Make sure to apply timeout from watchdog core, taking
* the prescaler of this driver here into account (the
* boot loader might be using a different prescaler).
*
* To avoid spurious resets because of different scaling,
* we first disable the watchdog, set the new prescaler
* and timeout, and then re-enable the watchdog.
*/
mt7621_wdt_stop(mt7621_wdt);
mt7621_wdt_start(mt7621_wdt);
set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
}
err = devm_watchdog_register_device(dev, &drvdata->wdt);
if (err)
return err;
platform_set_drvdata(pdev, drvdata);
return 0;
}
static void mt7621_wdt_shutdown(struct platform_device *pdev)
{
struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);
mt7621_wdt_stop(&drvdata->wdt);
}
static const struct of_device_id mt7621_wdt_match[] = {
{ .compatible = "mediatek,mt7621-wdt" },
{},
};
MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
static struct platform_driver mt7621_wdt_driver = {
.probe = mt7621_wdt_probe,
.shutdown = mt7621_wdt_shutdown,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = mt7621_wdt_match,
},
};
module_platform_driver(mt7621_wdt_driver);
MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
MODULE_AUTHOR("John Crispin <[email protected]");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/mt7621_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Maxim MAX77620 Watchdog Driver
*
* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
* Copyright (C) 2022 Luca Ceresoli
*
* Author: Laxman Dewangan <[email protected]>
* Author: Luca Ceresoli <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mfd/max77620.h>
#include <linux/mfd/max77714.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/watchdog.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
/**
* struct max77620_variant - Data specific to a chip variant
* @wdt_info: watchdog descriptor
* @reg_onoff_cnfg2: ONOFF_CNFG2 register offset
* @reg_cnfg_glbl2: CNFG_GLBL2 register offset
* @reg_cnfg_glbl3: CNFG_GLBL3 register offset
* @wdtc_mask: WDTC bit mask in CNFG_GLBL3 (=bits to update to ping the watchdog)
* @bit_wd_rst_wk: WD_RST_WK bit offset within ONOFF_CNFG2
* @cnfg_glbl2_cfg_bits: configuration bits to enable in CNFG_GLBL2 register
*/
struct max77620_variant {
u8 reg_onoff_cnfg2;
u8 reg_cnfg_glbl2;
u8 reg_cnfg_glbl3;
u8 wdtc_mask;
u8 bit_wd_rst_wk;
u8 cnfg_glbl2_cfg_bits;
};
struct max77620_wdt {
struct device *dev;
struct regmap *rmap;
const struct max77620_variant *drv_data;
struct watchdog_device wdt_dev;
};
static const struct max77620_variant max77620_wdt_data = {
.reg_onoff_cnfg2 = MAX77620_REG_ONOFFCNFG2,
.reg_cnfg_glbl2 = MAX77620_REG_CNFGGLBL2,
.reg_cnfg_glbl3 = MAX77620_REG_CNFGGLBL3,
.wdtc_mask = MAX77620_WDTC_MASK,
.bit_wd_rst_wk = MAX77620_ONOFFCNFG2_WD_RST_WK,
/* Set WDT clear in OFF and sleep mode */
.cnfg_glbl2_cfg_bits = MAX77620_WDTSLPC | MAX77620_WDTOFFC,
};
static const struct max77620_variant max77714_wdt_data = {
.reg_onoff_cnfg2 = MAX77714_CNFG2_ONOFF,
.reg_cnfg_glbl2 = MAX77714_CNFG_GLBL2,
.reg_cnfg_glbl3 = MAX77714_CNFG_GLBL3,
.wdtc_mask = MAX77714_WDTC,
.bit_wd_rst_wk = MAX77714_WD_RST_WK,
/* Set WDT clear in sleep mode (there is no WDTOFFC on MAX77714) */
.cnfg_glbl2_cfg_bits = MAX77714_WDTSLPC,
};
static int max77620_wdt_start(struct watchdog_device *wdt_dev)
{
struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
MAX77620_WDTEN, MAX77620_WDTEN);
}
static int max77620_wdt_stop(struct watchdog_device *wdt_dev)
{
struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
MAX77620_WDTEN, 0);
}
static int max77620_wdt_ping(struct watchdog_device *wdt_dev)
{
struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl3,
wdt->drv_data->wdtc_mask, 0x1);
}
static int max77620_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
unsigned int wdt_timeout;
u8 regval;
int ret;
switch (timeout) {
case 0 ... 2:
regval = MAX77620_TWD_2s;
wdt_timeout = 2;
break;
case 3 ... 16:
regval = MAX77620_TWD_16s;
wdt_timeout = 16;
break;
case 17 ... 64:
regval = MAX77620_TWD_64s;
wdt_timeout = 64;
break;
default:
regval = MAX77620_TWD_128s;
wdt_timeout = 128;
break;
}
/*
* "If the value of TWD needs to be changed, clear the system
* watchdog timer first [...], then change the value of TWD."
* (MAX77714 datasheet but applies to MAX77620 too)
*/
ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl3,
wdt->drv_data->wdtc_mask, 0x1);
if (ret < 0)
return ret;
ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
MAX77620_TWD_MASK, regval);
if (ret < 0)
return ret;
wdt_dev->timeout = wdt_timeout;
return 0;
}
static const struct watchdog_info max77620_wdt_info = {
.identity = "max77620-watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops max77620_wdt_ops = {
.start = max77620_wdt_start,
.stop = max77620_wdt_stop,
.ping = max77620_wdt_ping,
.set_timeout = max77620_wdt_set_timeout,
};
static int max77620_wdt_probe(struct platform_device *pdev)
{
const struct platform_device_id *id = platform_get_device_id(pdev);
struct device *dev = &pdev->dev;
struct max77620_wdt *wdt;
struct watchdog_device *wdt_dev;
unsigned int regval;
int ret;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->dev = dev;
wdt->drv_data = (const struct max77620_variant *) id->driver_data;
wdt->rmap = dev_get_regmap(dev->parent, NULL);
if (!wdt->rmap) {
dev_err(wdt->dev, "Failed to get parent regmap\n");
return -ENODEV;
}
wdt_dev = &wdt->wdt_dev;
wdt_dev->info = &max77620_wdt_info;
wdt_dev->ops = &max77620_wdt_ops;
wdt_dev->min_timeout = 2;
wdt_dev->max_timeout = 128;
wdt_dev->max_hw_heartbeat_ms = 128 * 1000;
platform_set_drvdata(pdev, wdt);
/* Enable WD_RST_WK - WDT expire results in a restart */
ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_onoff_cnfg2,
wdt->drv_data->bit_wd_rst_wk,
wdt->drv_data->bit_wd_rst_wk);
if (ret < 0) {
dev_err(wdt->dev, "Failed to set WD_RST_WK: %d\n", ret);
return ret;
}
/* Set the "auto WDT clear" bits available on the chip */
ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
wdt->drv_data->cnfg_glbl2_cfg_bits,
wdt->drv_data->cnfg_glbl2_cfg_bits);
if (ret < 0) {
dev_err(wdt->dev, "Failed to set WDT OFF mode: %d\n", ret);
return ret;
}
/* Check if WDT running and if yes then set flags properly */
ret = regmap_read(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2, ®val);
if (ret < 0) {
dev_err(wdt->dev, "Failed to read WDT CFG register: %d\n", ret);
return ret;
}
switch (regval & MAX77620_TWD_MASK) {
case MAX77620_TWD_2s:
wdt_dev->timeout = 2;
break;
case MAX77620_TWD_16s:
wdt_dev->timeout = 16;
break;
case MAX77620_TWD_64s:
wdt_dev->timeout = 64;
break;
default:
wdt_dev->timeout = 128;
break;
}
if (regval & MAX77620_WDTEN)
set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
watchdog_set_nowayout(wdt_dev, nowayout);
watchdog_set_drvdata(wdt_dev, wdt);
watchdog_stop_on_unregister(wdt_dev);
return devm_watchdog_register_device(dev, wdt_dev);
}
static const struct platform_device_id max77620_wdt_devtype[] = {
{ "max77620-watchdog", (kernel_ulong_t)&max77620_wdt_data },
{ "max77714-watchdog", (kernel_ulong_t)&max77714_wdt_data },
{ },
};
MODULE_DEVICE_TABLE(platform, max77620_wdt_devtype);
static struct platform_driver max77620_wdt_driver = {
.driver = {
.name = "max77620-watchdog",
},
.probe = max77620_wdt_probe,
.id_table = max77620_wdt_devtype,
};
module_platform_driver(max77620_wdt_driver);
MODULE_DESCRIPTION("Max77620 watchdog timer driver");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
MODULE_AUTHOR("Luca Ceresoli <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/max77620_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
*
* Authors: Dave Updegraff <[email protected]>
* Kumar Gala <[email protected]>
* Attribution: from 83xx_wst: Florian Schirmer <[email protected]>
* ..and from sc520_wdt
* Copyright (c) 2008 MontaVista Software, Inc.
* Anton Vorontsov <[email protected]>
*
* Note: it appears that you can only actually ENABLE or DISABLE the thing
* once after POR. Once enabled, you cannot disable, and vice versa.
*/
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/watchdog.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <sysdev/fsl_soc.h>
#define WATCHDOG_TIMEOUT 10
struct mpc8xxx_wdt {
__be32 res0;
__be32 swcrr; /* System watchdog control register */
#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
#define SWCRR_SWF 0x00000008 /* Software Watchdog Freeze (mpc8xx). */
#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
__be32 swcnr; /* System watchdog count register */
u8 res1[2];
__be16 swsrr; /* System watchdog service register */
u8 res2[0xF0];
};
struct mpc8xxx_wdt_type {
int prescaler;
bool hw_enabled;
u32 rsr_mask;
};
struct mpc8xxx_wdt_ddata {
struct mpc8xxx_wdt __iomem *base;
struct watchdog_device wdd;
spinlock_t lock;
u16 swtc;
};
static u16 timeout;
module_param(timeout, ushort, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. (1<timeout<65535, default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
static bool reset = 1;
module_param(reset, bool, 0);
MODULE_PARM_DESC(reset,
"Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
{
/* Ping the WDT */
spin_lock(&ddata->lock);
out_be16(&ddata->base->swsrr, 0x556c);
out_be16(&ddata->base->swsrr, 0xaa39);
spin_unlock(&ddata->lock);
}
static int mpc8xxx_wdt_start(struct watchdog_device *w)
{
struct mpc8xxx_wdt_ddata *ddata =
container_of(w, struct mpc8xxx_wdt_ddata, wdd);
u32 tmp = in_be32(&ddata->base->swcrr);
/* Good, fire up the show */
tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
if (reset)
tmp |= SWCRR_SWRI;
out_be32(&ddata->base->swcrr, tmp);
tmp = in_be32(&ddata->base->swcrr);
if (!(tmp & SWCRR_SWEN))
return -EOPNOTSUPP;
ddata->swtc = tmp >> 16;
set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
return 0;
}
static int mpc8xxx_wdt_ping(struct watchdog_device *w)
{
struct mpc8xxx_wdt_ddata *ddata =
container_of(w, struct mpc8xxx_wdt_ddata, wdd);
mpc8xxx_wdt_keepalive(ddata);
return 0;
}
static struct watchdog_info mpc8xxx_wdt_info = {
.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
.firmware_version = 1,
.identity = "MPC8xxx",
};
static const struct watchdog_ops mpc8xxx_wdt_ops = {
.owner = THIS_MODULE,
.start = mpc8xxx_wdt_start,
.ping = mpc8xxx_wdt_ping,
};
static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
{
int ret;
struct resource *res;
const struct mpc8xxx_wdt_type *wdt_type;
struct mpc8xxx_wdt_ddata *ddata;
u32 freq = fsl_get_sys_freq();
bool enabled;
struct device *dev = &ofdev->dev;
wdt_type = of_device_get_match_data(dev);
if (!wdt_type)
return -EINVAL;
if (!freq || freq == -1)
return -EINVAL;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->base = devm_platform_ioremap_resource(ofdev, 0);
if (IS_ERR(ddata->base))
return PTR_ERR(ddata->base);
enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
if (!enabled && wdt_type->hw_enabled) {
dev_info(dev, "could not be enabled in software\n");
return -ENODEV;
}
res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
if (res) {
bool status;
u32 __iomem *rsr = ioremap(res->start, resource_size(res));
if (!rsr)
return -ENOMEM;
status = in_be32(rsr) & wdt_type->rsr_mask;
ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
/* clear reset status bits related to watchdog timer */
out_be32(rsr, wdt_type->rsr_mask);
iounmap(rsr);
dev_info(dev, "Last boot was %scaused by watchdog\n",
status ? "" : "not ");
}
spin_lock_init(&ddata->lock);
ddata->wdd.info = &mpc8xxx_wdt_info;
ddata->wdd.ops = &mpc8xxx_wdt_ops;
ddata->wdd.timeout = WATCHDOG_TIMEOUT;
watchdog_init_timeout(&ddata->wdd, timeout, dev);
watchdog_set_nowayout(&ddata->wdd, nowayout);
ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
0xffffU);
/*
* If the watchdog was previously enabled or we're running on
* MPC8xxx, we should ping the wdt from the kernel until the
* userspace handles it.
*/
if (enabled)
mpc8xxx_wdt_start(&ddata->wdd);
ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
(freq / 1000);
ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
if (ddata->wdd.timeout < ddata->wdd.min_timeout)
ddata->wdd.timeout = ddata->wdd.min_timeout;
ret = devm_watchdog_register_device(dev, &ddata->wdd);
if (ret)
return ret;
dev_info(dev,
"WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
reset ? "reset" : "interrupt", ddata->wdd.timeout);
platform_set_drvdata(ofdev, ddata);
return 0;
}
static const struct of_device_id mpc8xxx_wdt_match[] = {
{
.compatible = "mpc83xx_wdt",
.data = &(struct mpc8xxx_wdt_type) {
.prescaler = 0x10000,
.rsr_mask = BIT(3), /* RSR Bit SWRS */
},
},
{
.compatible = "fsl,mpc8610-wdt",
.data = &(struct mpc8xxx_wdt_type) {
.prescaler = 0x10000,
.hw_enabled = true,
.rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
},
},
{
.compatible = "fsl,mpc823-wdt",
.data = &(struct mpc8xxx_wdt_type) {
.prescaler = 0x800,
.hw_enabled = true,
.rsr_mask = BIT(28), /* RSR Bit SWRS */
},
},
{},
};
MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
static struct platform_driver mpc8xxx_wdt_driver = {
.probe = mpc8xxx_wdt_probe,
.driver = {
.name = "mpc8xxx_wdt",
.of_match_table = mpc8xxx_wdt_match,
},
};
static int __init mpc8xxx_wdt_init(void)
{
return platform_driver_register(&mpc8xxx_wdt_driver);
}
arch_initcall(mpc8xxx_wdt_init);
static void __exit mpc8xxx_wdt_exit(void)
{
platform_driver_unregister(&mpc8xxx_wdt_driver);
}
module_exit(mpc8xxx_wdt_exit);
MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
"uProcessors");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/mpc8xxx_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#define MASK_WDGCS_ENABLE 0x01
#define MASK_WDGCS_RELOAD 0x04
#define MASK_WDGCS_NMIEN 0x08
#define MASK_WDGCS_WARN 0x80
#define WDT_MAX_TIMEOUT_MS 655350
#define WDT_DEFAULT_TIMEOUT 30
#define SECS_TO_WDOG_TICKS(x) ((x) * 100)
#define WDOG_TICKS_TO_SECS(x) ((x) / 100)
#define GXP_WDT_CNT_OFS 0x10
#define GXP_WDT_CTRL_OFS 0x16
struct gxp_wdt {
void __iomem *base;
struct watchdog_device wdd;
};
static void gxp_wdt_enable_reload(struct gxp_wdt *drvdata)
{
u8 val;
val = readb(drvdata->base + GXP_WDT_CTRL_OFS);
val |= (MASK_WDGCS_ENABLE | MASK_WDGCS_RELOAD);
writeb(val, drvdata->base + GXP_WDT_CTRL_OFS);
}
static int gxp_wdt_start(struct watchdog_device *wdd)
{
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
writew(SECS_TO_WDOG_TICKS(wdd->timeout), drvdata->base + GXP_WDT_CNT_OFS);
gxp_wdt_enable_reload(drvdata);
return 0;
}
static int gxp_wdt_stop(struct watchdog_device *wdd)
{
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
u8 val;
val = readb_relaxed(drvdata->base + GXP_WDT_CTRL_OFS);
val &= ~MASK_WDGCS_ENABLE;
writeb(val, drvdata->base + GXP_WDT_CTRL_OFS);
return 0;
}
static int gxp_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
u32 actual;
wdd->timeout = timeout;
actual = min(timeout * 100, wdd->max_hw_heartbeat_ms / 10);
writew(actual, drvdata->base + GXP_WDT_CNT_OFS);
return 0;
}
static unsigned int gxp_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
u32 val = readw(drvdata->base + GXP_WDT_CNT_OFS);
return WDOG_TICKS_TO_SECS(val);
}
static int gxp_wdt_ping(struct watchdog_device *wdd)
{
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
gxp_wdt_enable_reload(drvdata);
return 0;
}
static int gxp_restart(struct watchdog_device *wdd, unsigned long action,
void *data)
{
struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
writew(1, drvdata->base + GXP_WDT_CNT_OFS);
gxp_wdt_enable_reload(drvdata);
mdelay(100);
return 0;
}
static const struct watchdog_ops gxp_wdt_ops = {
.owner = THIS_MODULE,
.start = gxp_wdt_start,
.stop = gxp_wdt_stop,
.ping = gxp_wdt_ping,
.set_timeout = gxp_wdt_set_timeout,
.get_timeleft = gxp_wdt_get_timeleft,
.restart = gxp_restart,
};
static const struct watchdog_info gxp_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
.identity = "HPE GXP Watchdog timer",
};
static int gxp_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct gxp_wdt *drvdata;
int err;
u8 val;
drvdata = devm_kzalloc(dev, sizeof(struct gxp_wdt), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
/*
* The register area where the timer and watchdog reside is disarranged.
* Hence mapping individual register blocks for the timer and watchdog
* is not recommended as they would have access to each others
* registers. Based on feedback the watchdog is no longer part of the
* device tree file and the timer driver now creates the watchdog as a
* child device. During the watchdogs creation, the timer driver passes
* the base address to the watchdog over the private interface.
*/
drvdata->base = (void __iomem *)dev->platform_data;
drvdata->wdd.info = &gxp_wdt_info;
drvdata->wdd.ops = &gxp_wdt_ops;
drvdata->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
drvdata->wdd.parent = dev;
drvdata->wdd.timeout = WDT_DEFAULT_TIMEOUT;
watchdog_set_drvdata(&drvdata->wdd, drvdata);
watchdog_set_nowayout(&drvdata->wdd, WATCHDOG_NOWAYOUT);
val = readb(drvdata->base + GXP_WDT_CTRL_OFS);
if (val & MASK_WDGCS_ENABLE)
set_bit(WDOG_HW_RUNNING, &drvdata->wdd.status);
watchdog_set_restart_priority(&drvdata->wdd, 128);
watchdog_stop_on_reboot(&drvdata->wdd);
err = devm_watchdog_register_device(dev, &drvdata->wdd);
if (err) {
dev_err(dev, "Failed to register watchdog device");
return err;
}
dev_info(dev, "HPE GXP watchdog timer");
return 0;
}
static struct platform_driver gxp_wdt_driver = {
.probe = gxp_wdt_probe,
.driver = {
.name = "gxp-wdt",
},
};
module_platform_driver(gxp_wdt_driver);
MODULE_AUTHOR("Nick Hawkins <[email protected]>");
MODULE_AUTHOR("Jean-Marie Verdun <[email protected]>");
MODULE_DESCRIPTION("Driver for GXP watchdog timer");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/gxp-wdt.c |
// SPDX-License-Identifier: GPL-1.0+
/*
* IBM Automatic Server Restart driver.
*
* Copyright (c) 2005 Andrey Panin <[email protected]>
*
* Based on driver written by Pete Reynolds.
* Copyright (c) IBM Corporation, 1998-2004.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/timer.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/dmi.h>
#include <linux/io.h>
#include <linux/uaccess.h>
enum {
ASMTYPE_UNKNOWN,
ASMTYPE_TOPAZ,
ASMTYPE_JASPER,
ASMTYPE_PEARL,
ASMTYPE_JUNIPER,
ASMTYPE_SPRUCE,
};
#define TOPAZ_ASR_REG_OFFSET 4
#define TOPAZ_ASR_TOGGLE 0x40
#define TOPAZ_ASR_DISABLE 0x80
/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
#define PEARL_BASE 0xe04
#define PEARL_WRITE 0xe06
#define PEARL_READ 0xe07
#define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
#define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
#define JASPER_ASR_REG_OFFSET 0x38
#define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
#define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
#define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
#define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
#define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */
#define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned long asr_is_open;
static char asr_expect_close;
static unsigned int asr_type, asr_base, asr_length;
static unsigned int asr_read_addr, asr_write_addr;
static unsigned char asr_toggle_mask, asr_disable_mask;
static DEFINE_SPINLOCK(asr_lock);
static void __asr_toggle(void)
{
unsigned char reg;
reg = inb(asr_read_addr);
outb(reg & ~asr_toggle_mask, asr_write_addr);
reg = inb(asr_read_addr);
outb(reg | asr_toggle_mask, asr_write_addr);
reg = inb(asr_read_addr);
outb(reg & ~asr_toggle_mask, asr_write_addr);
reg = inb(asr_read_addr);
}
static void asr_toggle(void)
{
spin_lock(&asr_lock);
__asr_toggle();
spin_unlock(&asr_lock);
}
static void asr_enable(void)
{
unsigned char reg;
spin_lock(&asr_lock);
if (asr_type == ASMTYPE_TOPAZ) {
/* asr_write_addr == asr_read_addr */
reg = inb(asr_read_addr);
outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
asr_read_addr);
} else {
/*
* First make sure the hardware timer is reset by toggling
* ASR hardware timer line.
*/
__asr_toggle();
reg = inb(asr_read_addr);
outb(reg & ~asr_disable_mask, asr_write_addr);
}
reg = inb(asr_read_addr);
spin_unlock(&asr_lock);
}
static void asr_disable(void)
{
unsigned char reg;
spin_lock(&asr_lock);
reg = inb(asr_read_addr);
if (asr_type == ASMTYPE_TOPAZ)
/* asr_write_addr == asr_read_addr */
outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
asr_read_addr);
else {
outb(reg | asr_toggle_mask, asr_write_addr);
reg = inb(asr_read_addr);
outb(reg | asr_disable_mask, asr_write_addr);
}
reg = inb(asr_read_addr);
spin_unlock(&asr_lock);
}
static int __init asr_get_base_address(void)
{
unsigned char low, high;
const char *type = "";
asr_length = 1;
switch (asr_type) {
case ASMTYPE_TOPAZ:
/* SELECT SuperIO CHIP FOR QUERYING
(WRITE 0x07 TO BOTH 0x2E and 0x2F) */
outb(0x07, 0x2e);
outb(0x07, 0x2f);
/* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
outb(0x60, 0x2e);
high = inb(0x2f);
/* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
outb(0x61, 0x2e);
low = inb(0x2f);
asr_base = (high << 16) | low;
asr_read_addr = asr_write_addr =
asr_base + TOPAZ_ASR_REG_OFFSET;
asr_length = 5;
break;
case ASMTYPE_JASPER:
type = "Jaspers ";
#if 0
u32 r;
/* Suggested fix */
pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
if (pdev == NULL)
return -ENODEV;
pci_read_config_dword(pdev, 0x58, &r);
asr_base = r & 0xFFFE;
pci_dev_put(pdev);
#else
/* FIXME: need to use pci_config_lock here,
but it's not exported */
/* spin_lock_irqsave(&pci_config_lock, flags);*/
/* Select the SuperIO chip in the PCI I/O port register */
outl(0x8000f858, 0xcf8);
/* BUS 0, Slot 1F, fnc 0, offset 58 */
/*
* Read the base address for the SuperIO chip.
* Only the lower 16 bits are valid, but the address is word
* aligned so the last bit must be masked off.
*/
asr_base = inl(0xcfc) & 0xfffe;
/* spin_unlock_irqrestore(&pci_config_lock, flags);*/
#endif
asr_read_addr = asr_write_addr =
asr_base + JASPER_ASR_REG_OFFSET;
asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
asr_disable_mask = JASPER_ASR_DISABLE_MASK;
asr_length = JASPER_ASR_REG_OFFSET + 1;
break;
case ASMTYPE_PEARL:
type = "Pearls ";
asr_base = PEARL_BASE;
asr_read_addr = PEARL_READ;
asr_write_addr = PEARL_WRITE;
asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
asr_disable_mask = PEARL_ASR_DISABLE_MASK;
asr_length = 4;
break;
case ASMTYPE_JUNIPER:
type = "Junipers ";
asr_base = JUNIPER_BASE_ADDRESS;
asr_read_addr = asr_write_addr = asr_base;
asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
break;
case ASMTYPE_SPRUCE:
type = "Spruce's ";
asr_base = SPRUCE_BASE_ADDRESS;
asr_read_addr = asr_write_addr = asr_base;
asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
break;
}
if (!request_region(asr_base, asr_length, "ibmasr")) {
pr_err("address %#x already in use\n", asr_base);
return -EBUSY;
}
pr_info("found %sASR @ addr %#x\n", type, asr_base);
return 0;
}
static ssize_t asr_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count) {
if (!nowayout) {
size_t i;
/* In case it was set long ago */
asr_expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
asr_expect_close = 42;
}
}
asr_toggle();
}
return count;
}
static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
.identity = "IBM ASR",
};
void __user *argp = (void __user *)arg;
int __user *p = argp;
int heartbeat;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
int new_options, retval = -EINVAL;
if (get_user(new_options, p))
return -EFAULT;
if (new_options & WDIOS_DISABLECARD) {
asr_disable();
retval = 0;
}
if (new_options & WDIOS_ENABLECARD) {
asr_enable();
asr_toggle();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
asr_toggle();
return 0;
/*
* The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
* and WDIOC_GETTIMEOUT always returns 256.
*/
case WDIOC_GETTIMEOUT:
heartbeat = 256;
return put_user(heartbeat, p);
default:
return -ENOTTY;
}
}
static int asr_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &asr_is_open))
return -EBUSY;
asr_toggle();
asr_enable();
return stream_open(inode, file);
}
static int asr_release(struct inode *inode, struct file *file)
{
if (asr_expect_close == 42)
asr_disable();
else {
pr_crit("unexpected close, not stopping watchdog!\n");
asr_toggle();
}
clear_bit(0, &asr_is_open);
asr_expect_close = 0;
return 0;
}
static const struct file_operations asr_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = asr_write,
.unlocked_ioctl = asr_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = asr_open,
.release = asr_release,
};
static struct miscdevice asr_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &asr_fops,
};
struct ibmasr_id {
const char *desc;
int type;
};
static struct ibmasr_id ibmasr_id_table[] __initdata = {
{ "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
{ "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
{ "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
{ "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
{ "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
{ NULL }
};
static int __init ibmasr_init(void)
{
struct ibmasr_id *id;
int rc;
for (id = ibmasr_id_table; id->desc; id++) {
if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
asr_type = id->type;
break;
}
}
if (!asr_type)
return -ENODEV;
rc = asr_get_base_address();
if (rc)
return rc;
rc = misc_register(&asr_miscdev);
if (rc < 0) {
release_region(asr_base, asr_length);
pr_err("failed to register misc device\n");
return rc;
}
return 0;
}
static void __exit ibmasr_exit(void)
{
if (!nowayout)
asr_disable();
misc_deregister(&asr_miscdev);
release_region(asr_base, asr_length);
}
module_init(ibmasr_init);
module_exit(ibmasr_exit);
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
MODULE_AUTHOR("Andrey Panin");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/ibmasr.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Watchdog driver for Cirrus Logic EP93xx family of devices.
*
* Copyright (c) 2004 Ray Lehtiniemi
* Copyright (c) 2006 Tower Technologies
* Based on ep93xx driver, bits from alim7101_wdt.c
*
* Authors: Ray Lehtiniemi <[email protected]>,
* Alessandro Zummo <[email protected]>
*
* Copyright (c) 2012 H Hartley Sweeten <[email protected]>
* Convert to a platform device and use the watchdog framework API
*
* This watchdog fires after 250msec, which is a too short interval
* for us to rely on the user space daemon alone. So we ping the
* wdt each ~200msec and eventually stop doing it if the user space
* daemon dies.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/watchdog.h>
#include <linux/io.h>
/* default timeout (secs) */
#define WDT_TIMEOUT 30
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
static unsigned int timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds.");
#define EP93XX_WATCHDOG 0x00
#define EP93XX_WDSTATUS 0x04
struct ep93xx_wdt_priv {
void __iomem *mmio;
struct watchdog_device wdd;
};
static int ep93xx_wdt_start(struct watchdog_device *wdd)
{
struct ep93xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
writel(0xaaaa, priv->mmio + EP93XX_WATCHDOG);
return 0;
}
static int ep93xx_wdt_stop(struct watchdog_device *wdd)
{
struct ep93xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
writel(0xaa55, priv->mmio + EP93XX_WATCHDOG);
return 0;
}
static int ep93xx_wdt_ping(struct watchdog_device *wdd)
{
struct ep93xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
writel(0x5555, priv->mmio + EP93XX_WATCHDOG);
return 0;
}
static const struct watchdog_info ep93xx_wdt_ident = {
.options = WDIOF_CARDRESET |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "EP93xx Watchdog",
};
static const struct watchdog_ops ep93xx_wdt_ops = {
.owner = THIS_MODULE,
.start = ep93xx_wdt_start,
.stop = ep93xx_wdt_stop,
.ping = ep93xx_wdt_ping,
};
static int ep93xx_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ep93xx_wdt_priv *priv;
struct watchdog_device *wdd;
unsigned long val;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->mmio))
return PTR_ERR(priv->mmio);
val = readl(priv->mmio + EP93XX_WATCHDOG);
wdd = &priv->wdd;
wdd->bootstatus = (val & 0x01) ? WDIOF_CARDRESET : 0;
wdd->info = &ep93xx_wdt_ident;
wdd->ops = &ep93xx_wdt_ops;
wdd->min_timeout = 1;
wdd->max_hw_heartbeat_ms = 200;
wdd->parent = dev;
watchdog_set_nowayout(wdd, nowayout);
wdd->timeout = WDT_TIMEOUT;
watchdog_init_timeout(wdd, timeout, dev);
watchdog_set_drvdata(wdd, priv);
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
dev_info(dev, "EP93XX watchdog driver %s\n",
(val & 0x08) ? " (nCS1 disable detected)" : "");
return 0;
}
static struct platform_driver ep93xx_wdt_driver = {
.driver = {
.name = "ep93xx-wdt",
},
.probe = ep93xx_wdt_probe,
};
module_platform_driver(ep93xx_wdt_driver);
MODULE_AUTHOR("Ray Lehtiniemi <[email protected]>");
MODULE_AUTHOR("Alessandro Zummo <[email protected]>");
MODULE_AUTHOR("H Hartley Sweeten <[email protected]>");
MODULE_DESCRIPTION("EP93xx Watchdog");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/ep93xx_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2010-2011 Picochip Ltd., Jamie Iles
* https://www.picochip.com
*
* This file implements a driver for the Synopsys DesignWare watchdog device
* in the many subsystems. The watchdog has 16 different timeout periods
* and these are a function of the input clock frequency.
*
* The DesignWare watchdog cannot be stopped once it has been started so we
* do not implement a stop function. The watchdog core will continue to send
* heartbeat requests after the watchdog device has been closed.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/limits.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/reset.h>
#include <linux/watchdog.h>
#define WDOG_CONTROL_REG_OFFSET 0x00
#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
#define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
#define WDOG_INTERRUPT_STATUS_REG_OFFSET 0x10
#define WDOG_INTERRUPT_CLEAR_REG_OFFSET 0x14
#define WDOG_COMP_PARAMS_5_REG_OFFSET 0xe4
#define WDOG_COMP_PARAMS_4_REG_OFFSET 0xe8
#define WDOG_COMP_PARAMS_3_REG_OFFSET 0xec
#define WDOG_COMP_PARAMS_2_REG_OFFSET 0xf0
#define WDOG_COMP_PARAMS_1_REG_OFFSET 0xf4
#define WDOG_COMP_PARAMS_1_USE_FIX_TOP BIT(6)
#define WDOG_COMP_VERSION_REG_OFFSET 0xf8
#define WDOG_COMP_TYPE_REG_OFFSET 0xfc
/* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
#define DW_WDT_NUM_TOPS 16
#define DW_WDT_FIX_TOP(_idx) (1U << (16 + _idx))
#define DW_WDT_DEFAULT_SECONDS 30
static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = {
DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2),
DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5),
DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8),
DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11),
DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14),
DW_WDT_FIX_TOP(15)
};
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
enum dw_wdt_rmod {
DW_WDT_RMOD_RESET = 1,
DW_WDT_RMOD_IRQ = 2
};
struct dw_wdt_timeout {
u32 top_val;
unsigned int sec;
unsigned int msec;
};
struct dw_wdt {
void __iomem *regs;
struct clk *clk;
struct clk *pclk;
unsigned long rate;
enum dw_wdt_rmod rmod;
struct dw_wdt_timeout timeouts[DW_WDT_NUM_TOPS];
struct watchdog_device wdd;
struct reset_control *rst;
/* Save/restore */
u32 control;
u32 timeout;
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif
};
#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
{
return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
WDOG_CONTROL_REG_WDT_EN_MASK;
}
static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
{
u32 val;
val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
if (rmod == DW_WDT_RMOD_IRQ)
val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
else
val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
dw_wdt->rmod = rmod;
}
static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
unsigned int timeout, u32 *top_val)
{
int idx;
/*
* Find a TOP with timeout greater or equal to the requested number.
* Note we'll select a TOP with maximum timeout if the requested
* timeout couldn't be reached.
*/
for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
if (dw_wdt->timeouts[idx].sec >= timeout)
break;
}
if (idx == DW_WDT_NUM_TOPS)
--idx;
*top_val = dw_wdt->timeouts[idx].top_val;
return dw_wdt->timeouts[idx].sec;
}
static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
{
int idx;
/*
* We'll find a timeout greater or equal to one second anyway because
* the driver probe would have failed if there was none.
*/
for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
if (dw_wdt->timeouts[idx].sec)
break;
}
return dw_wdt->timeouts[idx].sec;
}
static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
{
struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
u64 msec;
msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;
return msec < UINT_MAX ? msec : UINT_MAX;
}
static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
{
int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
int idx;
for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
if (dw_wdt->timeouts[idx].top_val == top_val)
break;
}
/*
* In IRQ mode due to the two stages counter, the actual timeout is
* twice greater than the TOP setting.
*/
return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
}
static int dw_wdt_ping(struct watchdog_device *wdd)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
WDOG_COUNTER_RESTART_REG_OFFSET);
return 0;
}
static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
unsigned int timeout;
u32 top_val;
/*
* Note IRQ mode being enabled means having a non-zero pre-timeout
* setup. In this case we try to find a TOP as close to the half of the
* requested timeout as possible since DW Watchdog IRQ mode is designed
* in two stages way - first timeout rises the pre-timeout interrupt,
* second timeout performs the system reset. So basically the effective
* watchdog-caused reset happens after two watchdog TOPs elapsed.
*/
timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
&top_val);
if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
wdd->pretimeout = timeout;
else
wdd->pretimeout = 0;
/*
* Set the new value in the watchdog. Some versions of dw_wdt
* have TOPINIT in the TIMEOUT_RANGE register (as per
* CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
* effectively get a pat of the watchdog right here.
*/
writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
/* Kick new TOP value into the watchdog counter if activated. */
if (watchdog_active(wdd))
dw_wdt_ping(wdd);
/*
* In case users set bigger timeout value than HW can support,
* kernel(watchdog_dev.c) helps to feed watchdog before
* wdd->max_hw_heartbeat_ms
*/
if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
wdd->timeout = timeout * dw_wdt->rmod;
else
wdd->timeout = top_s;
return 0;
}
static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
/*
* We ignore actual value of the timeout passed from user-space
* using it as a flag whether the pretimeout functionality is intended
* to be activated.
*/
dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
dw_wdt_set_timeout(wdd, wdd->timeout);
return 0;
}
static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
{
u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
/* Disable/enable interrupt mode depending on the RMOD flag. */
if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
else
val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
/* Enable watchdog. */
val |= WDOG_CONTROL_REG_WDT_EN_MASK;
writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
}
static int dw_wdt_start(struct watchdog_device *wdd)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
dw_wdt_set_timeout(wdd, wdd->timeout);
dw_wdt_ping(&dw_wdt->wdd);
dw_wdt_arm_system_reset(dw_wdt);
return 0;
}
static int dw_wdt_stop(struct watchdog_device *wdd)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
if (!dw_wdt->rst) {
set_bit(WDOG_HW_RUNNING, &wdd->status);
return 0;
}
reset_control_assert(dw_wdt->rst);
reset_control_deassert(dw_wdt->rst);
return 0;
}
static int dw_wdt_restart(struct watchdog_device *wdd,
unsigned long action, void *data)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
if (dw_wdt_is_enabled(dw_wdt))
writel(WDOG_COUNTER_RESTART_KICK_VALUE,
dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
else
dw_wdt_arm_system_reset(dw_wdt);
/* wait for reset to assert... */
mdelay(500);
return 0;
}
static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
unsigned int sec;
u32 val;
val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
sec = val / dw_wdt->rate;
if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
if (!val)
sec += wdd->pretimeout;
}
return sec;
}
static const struct watchdog_info dw_wdt_ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.identity = "Synopsys DesignWare Watchdog",
};
static const struct watchdog_info dw_wdt_pt_ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE,
.identity = "Synopsys DesignWare Watchdog",
};
static const struct watchdog_ops dw_wdt_ops = {
.owner = THIS_MODULE,
.start = dw_wdt_start,
.stop = dw_wdt_stop,
.ping = dw_wdt_ping,
.set_timeout = dw_wdt_set_timeout,
.set_pretimeout = dw_wdt_set_pretimeout,
.get_timeleft = dw_wdt_get_timeleft,
.restart = dw_wdt_restart,
};
static irqreturn_t dw_wdt_irq(int irq, void *devid)
{
struct dw_wdt *dw_wdt = devid;
u32 val;
/*
* We don't clear the IRQ status. It's supposed to be done by the
* following ping operations.
*/
val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
if (!val)
return IRQ_NONE;
watchdog_notify_pretimeout(&dw_wdt->wdd);
return IRQ_HANDLED;
}
static int dw_wdt_suspend(struct device *dev)
{
struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
clk_disable_unprepare(dw_wdt->pclk);
clk_disable_unprepare(dw_wdt->clk);
return 0;
}
static int dw_wdt_resume(struct device *dev)
{
struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
int err = clk_prepare_enable(dw_wdt->clk);
if (err)
return err;
err = clk_prepare_enable(dw_wdt->pclk);
if (err) {
clk_disable_unprepare(dw_wdt->clk);
return err;
}
writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
dw_wdt_ping(&dw_wdt->wdd);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
/*
* In case if DW WDT IP core is synthesized with fixed TOP feature disabled the
* TOPs array can be arbitrary ordered with nearly any sixteen uint numbers
* depending on the system engineer imagination. The next method handles the
* passed TOPs array to pre-calculate the effective timeouts and to sort the
* TOP items out in the ascending order with respect to the timeouts.
*/
static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
{
struct dw_wdt_timeout tout, *dst;
int val, tidx;
u64 msec;
/*
* We walk over the passed TOPs array and calculate corresponding
* timeouts in seconds and milliseconds. The milliseconds granularity
* is needed to distinguish the TOPs with very close timeouts and to
* set the watchdog max heartbeat setting further.
*/
for (val = 0; val < DW_WDT_NUM_TOPS; ++val) {
tout.top_val = val;
tout.sec = tops[val] / dw_wdt->rate;
msec = (u64)tops[val] * MSEC_PER_SEC;
do_div(msec, dw_wdt->rate);
tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);
/*
* Find a suitable place for the current TOP in the timeouts
* array so that the list is remained in the ascending order.
*/
for (tidx = 0; tidx < val; ++tidx) {
dst = &dw_wdt->timeouts[tidx];
if (tout.sec > dst->sec || (tout.sec == dst->sec &&
tout.msec >= dst->msec))
continue;
else
swap(*dst, tout);
}
dw_wdt->timeouts[val] = tout;
}
}
static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
{
u32 data, of_tops[DW_WDT_NUM_TOPS];
const u32 *tops;
int ret;
/*
* Retrieve custom or fixed counter values depending on the
* WDT_USE_FIX_TOP flag found in the component specific parameters
* #1 register.
*/
data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) {
tops = dw_wdt_fix_tops;
} else {
ret = of_property_read_variable_u32_array(dev_of_node(dev),
"snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,
DW_WDT_NUM_TOPS);
if (ret < 0) {
dev_warn(dev, "No valid TOPs array specified\n");
tops = dw_wdt_fix_tops;
} else {
tops = of_tops;
}
}
/* Convert the specified TOPs into an array of watchdog timeouts. */
dw_wdt_handle_tops(dw_wdt, tops);
if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
dev_err(dev, "No any valid TOP detected\n");
return -EINVAL;
}
return 0;
}
#ifdef CONFIG_DEBUG_FS
#define DW_WDT_DBGFS_REG(_name, _off) \
{ \
.name = _name, \
.offset = _off \
}
static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = {
DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET),
DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET),
DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET),
DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET),
DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET),
DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET),
DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET),
DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET),
DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET),
DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET),
DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET),
DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET)
};
static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
{
struct device *dev = dw_wdt->wdd.parent;
struct debugfs_regset32 *regset;
regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
if (!regset)
return;
regset->regs = dw_wdt_dbgfs_regs;
regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);
regset->base = dw_wdt->regs;
dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
}
static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
{
debugfs_remove_recursive(dw_wdt->dbgfs_dir);
}
#else /* !CONFIG_DEBUG_FS */
static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
#endif /* !CONFIG_DEBUG_FS */
static int dw_wdt_drv_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct dw_wdt *dw_wdt;
int ret;
dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
if (!dw_wdt)
return -ENOMEM;
dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dw_wdt->regs))
return PTR_ERR(dw_wdt->regs);
/*
* Try to request the watchdog dedicated timer clock source. It must
* be supplied if asynchronous mode is enabled. Otherwise fallback
* to the common timer/bus clocks configuration, in which the very
* first found clock supply both timer and APB signals.
*/
dw_wdt->clk = devm_clk_get_enabled(dev, "tclk");
if (IS_ERR(dw_wdt->clk)) {
dw_wdt->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(dw_wdt->clk))
return PTR_ERR(dw_wdt->clk);
}
dw_wdt->rate = clk_get_rate(dw_wdt->clk);
if (dw_wdt->rate == 0)
return -EINVAL;
/*
* Request APB clock if device is configured with async clocks mode.
* In this case both tclk and pclk clocks are supposed to be specified.
* Alas we can't know for sure whether async mode was really activated,
* so the pclk phandle reference is left optional. If it couldn't be
* found we consider the device configured in synchronous clocks mode.
*/
dw_wdt->pclk = devm_clk_get_optional_enabled(dev, "pclk");
if (IS_ERR(dw_wdt->pclk))
return PTR_ERR(dw_wdt->pclk);
dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(dw_wdt->rst))
return PTR_ERR(dw_wdt->rst);
/* Enable normal reset without pre-timeout by default. */
dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
/*
* Pre-timeout IRQ is optional, since some hardware may lack support
* of it. Note we must request rising-edge IRQ, since the lane is left
* pending either until the next watchdog kick event or up to the
* system reset.
*/
ret = platform_get_irq_optional(pdev, 0);
if (ret > 0) {
ret = devm_request_irq(dev, ret, dw_wdt_irq,
IRQF_SHARED | IRQF_TRIGGER_RISING,
pdev->name, dw_wdt);
if (ret)
return ret;
dw_wdt->wdd.info = &dw_wdt_pt_ident;
} else {
if (ret == -EPROBE_DEFER)
return ret;
dw_wdt->wdd.info = &dw_wdt_ident;
}
reset_control_deassert(dw_wdt->rst);
ret = dw_wdt_init_timeouts(dw_wdt, dev);
if (ret)
goto out_assert_rst;
wdd = &dw_wdt->wdd;
wdd->ops = &dw_wdt_ops;
wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
wdd->parent = dev;
watchdog_set_drvdata(wdd, dw_wdt);
watchdog_set_nowayout(wdd, nowayout);
watchdog_init_timeout(wdd, 0, dev);
/*
* If the watchdog is already running, use its already configured
* timeout. Otherwise use the default or the value provided through
* devicetree.
*/
if (dw_wdt_is_enabled(dw_wdt)) {
wdd->timeout = dw_wdt_get_timeout(dw_wdt);
set_bit(WDOG_HW_RUNNING, &wdd->status);
} else {
wdd->timeout = DW_WDT_DEFAULT_SECONDS;
watchdog_init_timeout(wdd, 0, dev);
}
platform_set_drvdata(pdev, dw_wdt);
watchdog_set_restart_priority(wdd, 128);
watchdog_stop_on_reboot(wdd);
ret = watchdog_register_device(wdd);
if (ret)
goto out_assert_rst;
dw_wdt_dbgfs_init(dw_wdt);
return 0;
out_assert_rst:
reset_control_assert(dw_wdt->rst);
return ret;
}
static void dw_wdt_drv_remove(struct platform_device *pdev)
{
struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
dw_wdt_dbgfs_clear(dw_wdt);
watchdog_unregister_device(&dw_wdt->wdd);
reset_control_assert(dw_wdt->rst);
}
#ifdef CONFIG_OF
static const struct of_device_id dw_wdt_of_match[] = {
{ .compatible = "snps,dw-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
#endif
static struct platform_driver dw_wdt_driver = {
.probe = dw_wdt_drv_probe,
.remove_new = dw_wdt_drv_remove,
.driver = {
.name = "dw_wdt",
.of_match_table = of_match_ptr(dw_wdt_of_match),
.pm = pm_sleep_ptr(&dw_wdt_pm_ops),
},
};
module_platform_driver(dw_wdt_driver);
MODULE_AUTHOR("Jamie Iles");
MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/dw_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Window watchdog device driver for Xilinx Versal WWDT
*
* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/math64.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
/* Max timeout is calculated at 100MHz source clock */
#define XWWDT_DEFAULT_TIMEOUT 42
#define XWWDT_MIN_TIMEOUT 1
/* Register offsets for the WWDT device */
#define XWWDT_MWR_OFFSET 0x00
#define XWWDT_ESR_OFFSET 0x04
#define XWWDT_FCR_OFFSET 0x08
#define XWWDT_FWR_OFFSET 0x0c
#define XWWDT_SWR_OFFSET 0x10
/* Master Write Control Register Masks */
#define XWWDT_MWR_MASK BIT(0)
/* Enable and Status Register Masks */
#define XWWDT_ESR_WINT_MASK BIT(16)
#define XWWDT_ESR_WSW_MASK BIT(8)
#define XWWDT_ESR_WEN_MASK BIT(0)
#define XWWDT_CLOSE_WINDOW_PERCENT 50
static int wwdt_timeout;
static int closed_window_percent;
module_param(wwdt_timeout, int, 0);
MODULE_PARM_DESC(wwdt_timeout,
"Watchdog time in seconds. (default="
__MODULE_STRING(XWWDT_DEFAULT_TIMEOUT) ")");
module_param(closed_window_percent, int, 0);
MODULE_PARM_DESC(closed_window_percent,
"Watchdog closed window percentage. (default="
__MODULE_STRING(XWWDT_CLOSE_WINDOW_PERCENT) ")");
/**
* struct xwwdt_device - Watchdog device structure
* @base: base io address of WDT device
* @spinlock: spinlock for IO register access
* @xilinx_wwdt_wdd: watchdog device structure
* @freq: source clock frequency of WWDT
* @close_percent: Closed window percent
*/
struct xwwdt_device {
void __iomem *base;
spinlock_t spinlock; /* spinlock for register handling */
struct watchdog_device xilinx_wwdt_wdd;
unsigned long freq;
u32 close_percent;
};
static int xilinx_wwdt_start(struct watchdog_device *wdd)
{
struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
u64 time_out, closed_timeout, open_timeout;
u32 control_status_reg;
/* Calculate timeout count */
time_out = xdev->freq * wdd->timeout;
closed_timeout = div_u64(time_out * xdev->close_percent, 100);
open_timeout = time_out - closed_timeout;
wdd->min_hw_heartbeat_ms = xdev->close_percent * 10 * wdd->timeout;
spin_lock(&xdev->spinlock);
iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET);
iowrite32((u32)closed_timeout, xdev->base + XWWDT_FWR_OFFSET);
iowrite32((u32)open_timeout, xdev->base + XWWDT_SWR_OFFSET);
/* Enable the window watchdog timer */
control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
control_status_reg |= XWWDT_ESR_WEN_MASK;
iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
spin_unlock(&xdev->spinlock);
dev_dbg(xilinx_wwdt_wdd->parent, "Watchdog Started!\n");
return 0;
}
static int xilinx_wwdt_keepalive(struct watchdog_device *wdd)
{
struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
u32 control_status_reg;
spin_lock(&xdev->spinlock);
/* Enable write access control bit for the window watchdog */
iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
/* Trigger restart kick to watchdog */
control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
control_status_reg |= XWWDT_ESR_WSW_MASK;
iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
spin_unlock(&xdev->spinlock);
return 0;
}
static const struct watchdog_info xilinx_wwdt_ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT,
.firmware_version = 1,
.identity = "xlnx_window watchdog",
};
static const struct watchdog_ops xilinx_wwdt_ops = {
.owner = THIS_MODULE,
.start = xilinx_wwdt_start,
.ping = xilinx_wwdt_keepalive,
};
static int xwwdt_probe(struct platform_device *pdev)
{
struct watchdog_device *xilinx_wwdt_wdd;
struct device *dev = &pdev->dev;
struct xwwdt_device *xdev;
struct clk *clk;
int ret;
xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
if (!xdev)
return -ENOMEM;
xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
xilinx_wwdt_wdd->info = &xilinx_wwdt_ident;
xilinx_wwdt_wdd->ops = &xilinx_wwdt_ops;
xilinx_wwdt_wdd->parent = dev;
xdev->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xdev->base))
return PTR_ERR(xdev->base);
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
xdev->freq = clk_get_rate(clk);
if (!xdev->freq)
return -EINVAL;
xilinx_wwdt_wdd->min_timeout = XWWDT_MIN_TIMEOUT;
xilinx_wwdt_wdd->timeout = XWWDT_DEFAULT_TIMEOUT;
xilinx_wwdt_wdd->max_hw_heartbeat_ms = 1000 * xilinx_wwdt_wdd->timeout;
if (closed_window_percent == 0 || closed_window_percent >= 100)
xdev->close_percent = XWWDT_CLOSE_WINDOW_PERCENT;
else
xdev->close_percent = closed_window_percent;
watchdog_init_timeout(xilinx_wwdt_wdd, wwdt_timeout, &pdev->dev);
spin_lock_init(&xdev->spinlock);
watchdog_set_drvdata(xilinx_wwdt_wdd, xdev);
watchdog_set_nowayout(xilinx_wwdt_wdd, 1);
ret = devm_watchdog_register_device(dev, xilinx_wwdt_wdd);
if (ret)
return ret;
dev_info(dev, "Xilinx window watchdog Timer with timeout %ds\n",
xilinx_wwdt_wdd->timeout);
return 0;
}
static const struct of_device_id xwwdt_of_match[] = {
{ .compatible = "xlnx,versal-wwdt", },
{},
};
MODULE_DEVICE_TABLE(of, xwwdt_of_match);
static struct platform_driver xwwdt_driver = {
.probe = xwwdt_probe,
.driver = {
.name = "Xilinx window watchdog",
.of_match_table = xwwdt_of_match,
},
};
module_platform_driver(xwwdt_driver);
MODULE_AUTHOR("Neeli Srinivas <[email protected]>");
MODULE_DESCRIPTION("Xilinx window watchdog driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/xilinx_wwdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* IDT Interprise 79RC32434 watchdog driver
*
* Copyright (C) 2006, Ondrej Zajicek <[email protected]>
* Copyright (C) 2008, Florian Fainelli <[email protected]>
*
* based on
* SoftDog 0.05: A Software Watchdog Device
*
* (c) Copyright 1996 Alan Cox <[email protected]>,
* All Rights Reserved.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h> /* For module specific items */
#include <linux/moduleparam.h> /* For new moduleparam's */
#include <linux/types.h> /* For standard types (like size_t) */
#include <linux/errno.h> /* For the -ENODEV/... values */
#include <linux/kernel.h> /* For printk/panic/... */
#include <linux/fs.h> /* For file operations */
#include <linux/miscdevice.h> /* For struct miscdevice */
#include <linux/watchdog.h> /* For the watchdog specific items */
#include <linux/init.h> /* For __init/__exit/... */
#include <linux/platform_device.h> /* For platform_driver framework */
#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
#include <linux/io.h> /* For devm_ioremap */
#include <asm/mach-rc32434/integ.h> /* For the Watchdog registers */
#define VERSION "1.0"
static struct {
unsigned long inuse;
spinlock_t io_lock;
} rc32434_wdt_device;
static struct integ __iomem *wdt_reg;
static int expect_close;
/* Board internal clock speed in Hz,
* the watchdog timer ticks at. */
extern unsigned int idt_cpu_freq;
/* translate wtcompare value to seconds and vice versa */
#define WTCOMP2SEC(x) (x / idt_cpu_freq)
#define SEC2WTCOMP(x) (x * idt_cpu_freq)
/* Use a default timeout of 20s. This should be
* safe for CPU clock speeds up to 400MHz, as
* ((2 ^ 32) - 1) / (400MHz / 2) = 21s. */
#define WATCHDOG_TIMEOUT 20
static int timeout = WATCHDOG_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout value, in seconds (default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/* apply or and nand masks to data read from addr and write back */
#define SET_BITS(addr, or, nand) \
writel((readl(&addr) | or) & ~nand, &addr)
static int rc32434_wdt_set(int new_timeout)
{
int max_to = WTCOMP2SEC((u32)-1);
if (new_timeout < 0 || new_timeout > max_to) {
pr_err("timeout value must be between 0 and %d\n", max_to);
return -EINVAL;
}
timeout = new_timeout;
spin_lock(&rc32434_wdt_device.io_lock);
writel(SEC2WTCOMP(timeout), &wdt_reg->wtcompare);
spin_unlock(&rc32434_wdt_device.io_lock);
return 0;
}
static void rc32434_wdt_start(void)
{
u32 or, nand;
spin_lock(&rc32434_wdt_device.io_lock);
/* zero the counter before enabling */
writel(0, &wdt_reg->wtcount);
/* don't generate a non-maskable interrupt,
* do a warm reset instead */
nand = 1 << RC32434_ERR_WNE;
or = 1 << RC32434_ERR_WRE;
/* reset the ERRCS timeout bit in case it's set */
nand |= 1 << RC32434_ERR_WTO;
SET_BITS(wdt_reg->errcs, or, nand);
/* set the timeout (either default or based on module param) */
rc32434_wdt_set(timeout);
/* reset WTC timeout bit and enable WDT */
nand = 1 << RC32434_WTC_TO;
or = 1 << RC32434_WTC_EN;
SET_BITS(wdt_reg->wtc, or, nand);
spin_unlock(&rc32434_wdt_device.io_lock);
pr_info("Started watchdog timer\n");
}
static void rc32434_wdt_stop(void)
{
spin_lock(&rc32434_wdt_device.io_lock);
/* Disable WDT */
SET_BITS(wdt_reg->wtc, 0, 1 << RC32434_WTC_EN);
spin_unlock(&rc32434_wdt_device.io_lock);
pr_info("Stopped watchdog timer\n");
}
static void rc32434_wdt_ping(void)
{
spin_lock(&rc32434_wdt_device.io_lock);
writel(0, &wdt_reg->wtcount);
spin_unlock(&rc32434_wdt_device.io_lock);
}
static int rc32434_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &rc32434_wdt_device.inuse))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
rc32434_wdt_start();
rc32434_wdt_ping();
return stream_open(inode, file);
}
static int rc32434_wdt_release(struct inode *inode, struct file *file)
{
if (expect_close == 42) {
rc32434_wdt_stop();
module_put(THIS_MODULE);
} else {
pr_crit("device closed unexpectedly. WDT will not stop!\n");
rc32434_wdt_ping();
}
clear_bit(0, &rc32434_wdt_device.inuse);
return 0;
}
static ssize_t rc32434_wdt_write(struct file *file, const char *data,
size_t len, loff_t *ppos)
{
if (len) {
if (!nowayout) {
size_t i;
/* In case it was set long ago */
expect_close = 0;
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
rc32434_wdt_ping();
return len;
}
return 0;
}
static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
void __user *argp = (void __user *)arg;
int new_timeout;
unsigned int value;
static const struct watchdog_info ident = {
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
.identity = "RC32434_WDT Watchdog",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident)))
return -EFAULT;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
value = 0;
if (copy_to_user(argp, &value, sizeof(int)))
return -EFAULT;
break;
case WDIOC_SETOPTIONS:
if (copy_from_user(&value, argp, sizeof(int)))
return -EFAULT;
switch (value) {
case WDIOS_ENABLECARD:
rc32434_wdt_start();
break;
case WDIOS_DISABLECARD:
rc32434_wdt_stop();
break;
default:
return -EINVAL;
}
break;
case WDIOC_KEEPALIVE:
rc32434_wdt_ping();
break;
case WDIOC_SETTIMEOUT:
if (copy_from_user(&new_timeout, argp, sizeof(int)))
return -EFAULT;
if (rc32434_wdt_set(new_timeout))
return -EINVAL;
fallthrough;
case WDIOC_GETTIMEOUT:
return copy_to_user(argp, &timeout, sizeof(int)) ? -EFAULT : 0;
default:
return -ENOTTY;
}
return 0;
}
static const struct file_operations rc32434_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = rc32434_wdt_write,
.unlocked_ioctl = rc32434_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = rc32434_wdt_open,
.release = rc32434_wdt_release,
};
static struct miscdevice rc32434_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &rc32434_wdt_fops,
};
static int rc32434_wdt_probe(struct platform_device *pdev)
{
int ret;
struct resource *r;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb532_wdt_res");
if (!r) {
pr_err("failed to retrieve resources\n");
return -ENODEV;
}
wdt_reg = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!wdt_reg) {
pr_err("failed to remap I/O resources\n");
return -ENXIO;
}
spin_lock_init(&rc32434_wdt_device.io_lock);
/* Make sure the watchdog is not running */
rc32434_wdt_stop();
/* Check that the heartbeat value is within it's range;
* if not reset to the default */
if (rc32434_wdt_set(timeout)) {
rc32434_wdt_set(WATCHDOG_TIMEOUT);
pr_info("timeout value must be between 0 and %d\n",
WTCOMP2SEC((u32)-1));
}
ret = misc_register(&rc32434_wdt_miscdev);
if (ret < 0) {
pr_err("failed to register watchdog device\n");
return ret;
}
pr_info("Watchdog Timer version " VERSION ", timer margin: %d sec\n",
timeout);
return 0;
}
static void rc32434_wdt_remove(struct platform_device *pdev)
{
misc_deregister(&rc32434_wdt_miscdev);
}
static void rc32434_wdt_shutdown(struct platform_device *pdev)
{
rc32434_wdt_stop();
}
static struct platform_driver rc32434_wdt_driver = {
.probe = rc32434_wdt_probe,
.remove_new = rc32434_wdt_remove,
.shutdown = rc32434_wdt_shutdown,
.driver = {
.name = "rc32434_wdt",
}
};
module_platform_driver(rc32434_wdt_driver);
MODULE_AUTHOR("Ondrej Zajicek <[email protected]>,"
"Florian Fainelli <[email protected]>");
MODULE_DESCRIPTION("Driver for the IDT RC32434 SoC watchdog");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/rc32434_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GE watchdog userspace interface
*
* Author: Martyn Welch <[email protected]>
*
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
*
* Based on: mv64x60_wdt.c (MV64X60 watchdog userspace interface)
* Author: James Chapman <[email protected]>
*/
/* TODO:
* This driver does not provide support for the hardwares capability of sending
* an interrupt at a programmable threshold.
*
* This driver currently can only support 1 watchdog - there are 2 in the
* hardware that this driver supports. Thus one could be configured as a
* process-based watchdog (via /dev/watchdog), the second (using the interrupt
* capabilities) a kernel-based watchdog.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <sysdev/fsl_soc.h>
/*
* The watchdog configuration register contains a pair of 2-bit fields,
* 1. a reload field, bits 27-26, which triggers a reload of
* the countdown register, and
* 2. an enable field, bits 25-24, which toggles between
* enabling and disabling the watchdog timer.
* Bit 31 is a read-only field which indicates whether the
* watchdog timer is currently enabled.
*
* The low 24 bits contain the timer reload value.
*/
#define GEF_WDC_ENABLE_SHIFT 24
#define GEF_WDC_SERVICE_SHIFT 26
#define GEF_WDC_ENABLED_SHIFT 31
#define GEF_WDC_ENABLED_TRUE 1
#define GEF_WDC_ENABLED_FALSE 0
/* Flags bits */
#define GEF_WDOG_FLAG_OPENED 0
static unsigned long wdt_flags;
static int wdt_status;
static void __iomem *gef_wdt_regs;
static int gef_wdt_timeout;
static int gef_wdt_count;
static unsigned int bus_clk;
static char expect_close;
static DEFINE_SPINLOCK(gef_wdt_spinlock);
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int gef_wdt_toggle_wdc(int enabled_predicate, int field_shift)
{
u32 data;
u32 enabled;
int ret = 0;
spin_lock(&gef_wdt_spinlock);
data = ioread32be(gef_wdt_regs);
enabled = (data >> GEF_WDC_ENABLED_SHIFT) & 1;
/* only toggle the requested field if enabled state matches predicate */
if ((enabled ^ enabled_predicate) == 0) {
/* We write a 1, then a 2 -- to the appropriate field */
data = (1 << field_shift) | gef_wdt_count;
iowrite32be(data, gef_wdt_regs);
data = (2 << field_shift) | gef_wdt_count;
iowrite32be(data, gef_wdt_regs);
ret = 1;
}
spin_unlock(&gef_wdt_spinlock);
return ret;
}
static void gef_wdt_service(void)
{
gef_wdt_toggle_wdc(GEF_WDC_ENABLED_TRUE,
GEF_WDC_SERVICE_SHIFT);
}
static void gef_wdt_handler_enable(void)
{
if (gef_wdt_toggle_wdc(GEF_WDC_ENABLED_FALSE,
GEF_WDC_ENABLE_SHIFT)) {
gef_wdt_service();
pr_notice("watchdog activated\n");
}
}
static void gef_wdt_handler_disable(void)
{
if (gef_wdt_toggle_wdc(GEF_WDC_ENABLED_TRUE,
GEF_WDC_ENABLE_SHIFT))
pr_notice("watchdog deactivated\n");
}
static void gef_wdt_set_timeout(unsigned int timeout)
{
/* maximum bus cycle count is 0xFFFFFFFF */
if (timeout > 0xFFFFFFFF / bus_clk)
timeout = 0xFFFFFFFF / bus_clk;
/* Register only holds upper 24 bits, bit shifted into lower 24 */
gef_wdt_count = (timeout * bus_clk) >> 8;
gef_wdt_timeout = timeout;
}
static ssize_t gef_wdt_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
if (len) {
if (!nowayout) {
size_t i;
expect_close = 0;
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
gef_wdt_service();
}
return len;
}
static long gef_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int timeout;
int options;
void __user *argp = (void __user *)arg;
static const struct watchdog_info info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.firmware_version = 0,
.identity = "GE watchdog",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &info, sizeof(info)))
return -EFAULT;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
if (put_user(wdt_status, (int __user *)argp))
return -EFAULT;
wdt_status &= ~WDIOF_KEEPALIVEPING;
break;
case WDIOC_SETOPTIONS:
if (get_user(options, (int __user *)argp))
return -EFAULT;
if (options & WDIOS_DISABLECARD)
gef_wdt_handler_disable();
if (options & WDIOS_ENABLECARD)
gef_wdt_handler_enable();
break;
case WDIOC_KEEPALIVE:
gef_wdt_service();
wdt_status |= WDIOF_KEEPALIVEPING;
break;
case WDIOC_SETTIMEOUT:
if (get_user(timeout, (int __user *)argp))
return -EFAULT;
gef_wdt_set_timeout(timeout);
fallthrough;
case WDIOC_GETTIMEOUT:
if (put_user(gef_wdt_timeout, (int __user *)argp))
return -EFAULT;
break;
default:
return -ENOTTY;
}
return 0;
}
static int gef_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(GEF_WDOG_FLAG_OPENED, &wdt_flags))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
gef_wdt_handler_enable();
return stream_open(inode, file);
}
static int gef_wdt_release(struct inode *inode, struct file *file)
{
if (expect_close == 42)
gef_wdt_handler_disable();
else {
pr_crit("unexpected close, not stopping timer!\n");
gef_wdt_service();
}
expect_close = 0;
clear_bit(GEF_WDOG_FLAG_OPENED, &wdt_flags);
return 0;
}
static const struct file_operations gef_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = gef_wdt_write,
.unlocked_ioctl = gef_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = gef_wdt_open,
.release = gef_wdt_release,
};
static struct miscdevice gef_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &gef_wdt_fops,
};
static int gef_wdt_probe(struct platform_device *dev)
{
int timeout = 10;
u32 freq;
bus_clk = 133; /* in MHz */
freq = fsl_get_sys_freq();
if (freq != -1)
bus_clk = freq;
/* Map devices registers into memory */
gef_wdt_regs = of_iomap(dev->dev.of_node, 0);
if (gef_wdt_regs == NULL)
return -ENOMEM;
gef_wdt_set_timeout(timeout);
gef_wdt_handler_disable(); /* in case timer was already running */
return misc_register(&gef_wdt_miscdev);
}
static void gef_wdt_remove(struct platform_device *dev)
{
misc_deregister(&gef_wdt_miscdev);
gef_wdt_handler_disable();
iounmap(gef_wdt_regs);
}
static const struct of_device_id gef_wdt_ids[] = {
{
.compatible = "gef,fpga-wdt",
},
{},
};
MODULE_DEVICE_TABLE(of, gef_wdt_ids);
static struct platform_driver gef_wdt_driver = {
.driver = {
.name = "gef_wdt",
.of_match_table = gef_wdt_ids,
},
.probe = gef_wdt_probe,
.remove_new = gef_wdt_remove,
};
static int __init gef_wdt_init(void)
{
pr_info("GE watchdog driver\n");
return platform_driver_register(&gef_wdt_driver);
}
static void __exit gef_wdt_exit(void)
{
platform_driver_unregister(&gef_wdt_driver);
}
module_init(gef_wdt_init);
module_exit(gef_wdt_exit);
MODULE_AUTHOR("Martyn Welch <[email protected]>");
MODULE_DESCRIPTION("GE watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:gef_wdt");
| linux-master | drivers/watchdog/gef_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for Conexant Digicolor
*
* Copyright (C) 2015 Paradox Innovation Ltd.
*
*/
#include <linux/types.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
#define TIMER_A_CONTROL 0
#define TIMER_A_COUNT 4
#define TIMER_A_ENABLE_COUNT BIT(0)
#define TIMER_A_ENABLE_WATCHDOG BIT(1)
struct dc_wdt {
void __iomem *base;
struct clk *clk;
spinlock_t lock;
};
static unsigned timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
static void dc_wdt_set(struct dc_wdt *wdt, u32 ticks)
{
unsigned long flags;
spin_lock_irqsave(&wdt->lock, flags);
writel_relaxed(0, wdt->base + TIMER_A_CONTROL);
writel_relaxed(ticks, wdt->base + TIMER_A_COUNT);
writel_relaxed(TIMER_A_ENABLE_COUNT | TIMER_A_ENABLE_WATCHDOG,
wdt->base + TIMER_A_CONTROL);
spin_unlock_irqrestore(&wdt->lock, flags);
}
static int dc_wdt_restart(struct watchdog_device *wdog, unsigned long action,
void *data)
{
struct dc_wdt *wdt = watchdog_get_drvdata(wdog);
dc_wdt_set(wdt, 1);
/* wait for reset to assert... */
mdelay(500);
return 0;
}
static int dc_wdt_start(struct watchdog_device *wdog)
{
struct dc_wdt *wdt = watchdog_get_drvdata(wdog);
dc_wdt_set(wdt, wdog->timeout * clk_get_rate(wdt->clk));
return 0;
}
static int dc_wdt_stop(struct watchdog_device *wdog)
{
struct dc_wdt *wdt = watchdog_get_drvdata(wdog);
writel_relaxed(0, wdt->base + TIMER_A_CONTROL);
return 0;
}
static int dc_wdt_set_timeout(struct watchdog_device *wdog, unsigned int t)
{
struct dc_wdt *wdt = watchdog_get_drvdata(wdog);
dc_wdt_set(wdt, t * clk_get_rate(wdt->clk));
wdog->timeout = t;
return 0;
}
static unsigned int dc_wdt_get_timeleft(struct watchdog_device *wdog)
{
struct dc_wdt *wdt = watchdog_get_drvdata(wdog);
uint32_t count = readl_relaxed(wdt->base + TIMER_A_COUNT);
return count / clk_get_rate(wdt->clk);
}
static const struct watchdog_ops dc_wdt_ops = {
.owner = THIS_MODULE,
.start = dc_wdt_start,
.stop = dc_wdt_stop,
.set_timeout = dc_wdt_set_timeout,
.get_timeleft = dc_wdt_get_timeleft,
.restart = dc_wdt_restart,
};
static const struct watchdog_info dc_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE
| WDIOF_KEEPALIVEPING,
.identity = "Conexant Digicolor Watchdog",
};
static struct watchdog_device dc_wdt_wdd = {
.info = &dc_wdt_info,
.ops = &dc_wdt_ops,
.min_timeout = 1,
};
static int dc_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct dc_wdt *wdt;
wdt = devm_kzalloc(dev, sizeof(struct dc_wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
wdt->clk = devm_clk_get(dev, NULL);
if (IS_ERR(wdt->clk))
return PTR_ERR(wdt->clk);
dc_wdt_wdd.max_timeout = U32_MAX / clk_get_rate(wdt->clk);
dc_wdt_wdd.timeout = dc_wdt_wdd.max_timeout;
dc_wdt_wdd.parent = dev;
spin_lock_init(&wdt->lock);
watchdog_set_drvdata(&dc_wdt_wdd, wdt);
watchdog_set_restart_priority(&dc_wdt_wdd, 128);
watchdog_init_timeout(&dc_wdt_wdd, timeout, dev);
watchdog_stop_on_reboot(&dc_wdt_wdd);
return devm_watchdog_register_device(dev, &dc_wdt_wdd);
}
static const struct of_device_id dc_wdt_of_match[] = {
{ .compatible = "cnxt,cx92755-wdt", },
{},
};
MODULE_DEVICE_TABLE(of, dc_wdt_of_match);
static struct platform_driver dc_wdt_driver = {
.probe = dc_wdt_probe,
.driver = {
.name = "digicolor-wdt",
.of_match_table = dc_wdt_of_match,
},
};
module_platform_driver(dc_wdt_driver);
MODULE_AUTHOR("Baruch Siach <[email protected]>");
MODULE_DESCRIPTION("Driver for Conexant Digicolor watchdog timer");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/digicolor_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for TQMx86 PLD.
*
* The watchdog supports power of 2 timeouts from 1 to 4096sec.
* Once started, it cannot be stopped.
*
* Based on the vendor code written by Vadim V.Vlasov
* <[email protected]>
*/
#include <linux/io.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/timer.h>
#include <linux/watchdog.h>
/* default timeout (secs) */
#define WDT_TIMEOUT 32
static unsigned int timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. (1<=timeout<=4096, default="
__MODULE_STRING(WDT_TIMEOUT) ")");
struct tqmx86_wdt {
struct watchdog_device wdd;
void __iomem *io_base;
};
#define TQMX86_WDCFG 0x00 /* Watchdog Configuration Register */
#define TQMX86_WDCS 0x01 /* Watchdog Config/Status Register */
static int tqmx86_wdt_start(struct watchdog_device *wdd)
{
struct tqmx86_wdt *priv = watchdog_get_drvdata(wdd);
iowrite8(0x81, priv->io_base + TQMX86_WDCS);
return 0;
}
static int tqmx86_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t)
{
struct tqmx86_wdt *priv = watchdog_get_drvdata(wdd);
u8 val;
t = roundup_pow_of_two(t);
val = ilog2(t) | 0x90;
val += 3; /* values 0,1,2 correspond to 0.125,0.25,0.5s timeouts */
iowrite8(val, priv->io_base + TQMX86_WDCFG);
wdd->timeout = t;
return 0;
}
static const struct watchdog_info tqmx86_wdt_info = {
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING,
.identity = "TQMx86 Watchdog",
};
static const struct watchdog_ops tqmx86_wdt_ops = {
.owner = THIS_MODULE,
.start = tqmx86_wdt_start,
.set_timeout = tqmx86_wdt_set_timeout,
};
static int tqmx86_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tqmx86_wdt *priv;
struct resource *res;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!res)
return -ENODEV;
priv->io_base = devm_ioport_map(dev, res->start, resource_size(res));
if (!priv->io_base)
return -ENOMEM;
watchdog_set_drvdata(&priv->wdd, priv);
priv->wdd.parent = dev;
priv->wdd.info = &tqmx86_wdt_info;
priv->wdd.ops = &tqmx86_wdt_ops;
priv->wdd.min_timeout = 1;
priv->wdd.max_timeout = 4096;
priv->wdd.max_hw_heartbeat_ms = 4096*1000;
priv->wdd.timeout = WDT_TIMEOUT;
watchdog_init_timeout(&priv->wdd, timeout, dev);
watchdog_set_nowayout(&priv->wdd, WATCHDOG_NOWAYOUT);
tqmx86_wdt_set_timeout(&priv->wdd, priv->wdd.timeout);
err = devm_watchdog_register_device(dev, &priv->wdd);
if (err)
return err;
dev_info(dev, "TQMx86 watchdog\n");
return 0;
}
static struct platform_driver tqmx86_wdt_driver = {
.driver = {
.name = "tqmx86-wdt",
},
.probe = tqmx86_wdt_probe,
};
module_platform_driver(tqmx86_wdt_driver);
MODULE_AUTHOR("Andrew Lunn <[email protected]>");
MODULE_DESCRIPTION("TQMx86 Watchdog");
MODULE_ALIAS("platform:tqmx86-wdt");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/tqmx86_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HPE WatchDog Driver
* based on
*
* SoftDog 0.05: A Software Watchdog Device
*
* (c) Copyright 2018 Hewlett Packard Enterprise Development LP
* Thomas Mingarelli <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/device.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#ifdef CONFIG_HPWDT_NMI_DECODING
#include <asm/nmi.h>
#endif
#include <linux/crash_dump.h>
#define HPWDT_VERSION "2.0.4"
#define SECS_TO_TICKS(secs) ((secs) * 1000 / 128)
#define TICKS_TO_SECS(ticks) ((ticks) * 128 / 1000)
#define HPWDT_MAX_TICKS 65535
#define HPWDT_MAX_TIMER TICKS_TO_SECS(HPWDT_MAX_TICKS)
#define DEFAULT_MARGIN 30
#define PRETIMEOUT_SEC 9
static bool ilo5;
static unsigned int soft_margin = DEFAULT_MARGIN; /* in seconds */
static bool nowayout = WATCHDOG_NOWAYOUT;
static bool pretimeout = IS_ENABLED(CONFIG_HPWDT_NMI_DECODING);
static int kdumptimeout = -1;
static void __iomem *pci_mem_addr; /* the PCI-memory address */
static unsigned long __iomem *hpwdt_nmistat;
static unsigned long __iomem *hpwdt_timer_reg;
static unsigned long __iomem *hpwdt_timer_con;
static const struct pci_device_id hpwdt_devices[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xB203) }, /* iLO2 */
{ PCI_DEVICE(PCI_VENDOR_ID_HP, 0x3306) }, /* iLO3 */
{ PCI_DEVICE(PCI_VENDOR_ID_HP_3PAR, 0x0389) }, /* PCtrl */
{0}, /* terminate list */
};
MODULE_DEVICE_TABLE(pci, hpwdt_devices);
static const struct pci_device_id hpwdt_blacklist[] = {
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_HP, 0x3306, PCI_VENDOR_ID_HP, 0x1979) }, /* auxilary iLO */
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_HP, 0x3306, PCI_VENDOR_ID_HP_3PAR, 0x0289) }, /* CL */
{0}, /* terminate list */
};
static struct watchdog_device hpwdt_dev;
/*
* Watchdog operations
*/
static int hpwdt_hw_is_running(void)
{
return ioread8(hpwdt_timer_con) & 0x01;
}
static int hpwdt_start(struct watchdog_device *wdd)
{
int control = 0x81 | (pretimeout ? 0x4 : 0);
int reload = SECS_TO_TICKS(min(wdd->timeout, wdd->max_hw_heartbeat_ms/1000));
dev_dbg(wdd->parent, "start watchdog 0x%08x:0x%08x:0x%02x\n", wdd->timeout, reload, control);
iowrite16(reload, hpwdt_timer_reg);
iowrite8(control, hpwdt_timer_con);
return 0;
}
static void hpwdt_stop(void)
{
unsigned long data;
pr_debug("stop watchdog\n");
data = ioread8(hpwdt_timer_con);
data &= 0xFE;
iowrite8(data, hpwdt_timer_con);
}
static int hpwdt_stop_core(struct watchdog_device *wdd)
{
hpwdt_stop();
return 0;
}
static void hpwdt_ping_ticks(int val)
{
val = min(val, HPWDT_MAX_TICKS);
iowrite16(val, hpwdt_timer_reg);
}
static int hpwdt_ping(struct watchdog_device *wdd)
{
int reload = SECS_TO_TICKS(min(wdd->timeout, wdd->max_hw_heartbeat_ms/1000));
dev_dbg(wdd->parent, "ping watchdog 0x%08x:0x%08x\n", wdd->timeout, reload);
hpwdt_ping_ticks(reload);
return 0;
}
static unsigned int hpwdt_gettimeleft(struct watchdog_device *wdd)
{
return TICKS_TO_SECS(ioread16(hpwdt_timer_reg));
}
static int hpwdt_settimeout(struct watchdog_device *wdd, unsigned int val)
{
dev_dbg(wdd->parent, "set_timeout = %d\n", val);
wdd->timeout = val;
if (val <= wdd->pretimeout) {
dev_dbg(wdd->parent, "pretimeout < timeout. Setting to zero\n");
wdd->pretimeout = 0;
pretimeout = false;
if (watchdog_active(wdd))
hpwdt_start(wdd);
}
hpwdt_ping(wdd);
return 0;
}
#ifdef CONFIG_HPWDT_NMI_DECODING
static int hpwdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
{
unsigned int val = 0;
dev_dbg(wdd->parent, "set_pretimeout = %d\n", req);
if (req) {
val = PRETIMEOUT_SEC;
if (val >= wdd->timeout)
return -EINVAL;
}
if (val != req)
dev_dbg(wdd->parent, "Rounding pretimeout to: %d\n", val);
wdd->pretimeout = val;
pretimeout = !!val;
if (watchdog_active(wdd))
hpwdt_start(wdd);
return 0;
}
static int hpwdt_my_nmi(void)
{
return ioread8(hpwdt_nmistat) & 0x6;
}
/*
* NMI Handler
*/
static int hpwdt_pretimeout(unsigned int ulReason, struct pt_regs *regs)
{
unsigned int mynmi = hpwdt_my_nmi();
static char panic_msg[] =
"00: An NMI occurred. Depending on your system the reason "
"for the NMI is logged in any one of the following resources:\n"
"1. Integrated Management Log (IML)\n"
"2. OA Syslog\n"
"3. OA Forward Progress Log\n"
"4. iLO Event Log";
if (ilo5 && ulReason == NMI_UNKNOWN && !mynmi)
return NMI_DONE;
if (ilo5 && !pretimeout && !mynmi)
return NMI_DONE;
if (kdumptimeout < 0)
hpwdt_stop();
else if (kdumptimeout == 0)
;
else {
unsigned int val = max((unsigned int)kdumptimeout, hpwdt_dev.timeout);
hpwdt_ping_ticks(SECS_TO_TICKS(val));
}
hex_byte_pack(panic_msg, mynmi);
nmi_panic(regs, panic_msg);
return NMI_HANDLED;
}
#endif /* CONFIG_HPWDT_NMI_DECODING */
static const struct watchdog_info ident = {
.options = WDIOF_PRETIMEOUT |
WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
.identity = "HPE iLO2+ HW Watchdog Timer",
};
/*
* Kernel interfaces
*/
static const struct watchdog_ops hpwdt_ops = {
.owner = THIS_MODULE,
.start = hpwdt_start,
.stop = hpwdt_stop_core,
.ping = hpwdt_ping,
.set_timeout = hpwdt_settimeout,
.get_timeleft = hpwdt_gettimeleft,
#ifdef CONFIG_HPWDT_NMI_DECODING
.set_pretimeout = hpwdt_set_pretimeout,
#endif
};
static struct watchdog_device hpwdt_dev = {
.info = &ident,
.ops = &hpwdt_ops,
.min_timeout = 1,
.timeout = DEFAULT_MARGIN,
.pretimeout = PRETIMEOUT_SEC,
.max_hw_heartbeat_ms = HPWDT_MAX_TIMER * 1000,
};
/*
* Init & Exit
*/
static int hpwdt_init_nmi_decoding(struct pci_dev *dev)
{
#ifdef CONFIG_HPWDT_NMI_DECODING
int retval;
/*
* Only one function can register for NMI_UNKNOWN
*/
retval = register_nmi_handler(NMI_UNKNOWN, hpwdt_pretimeout, 0, "hpwdt");
if (retval)
goto error;
retval = register_nmi_handler(NMI_SERR, hpwdt_pretimeout, 0, "hpwdt");
if (retval)
goto error1;
retval = register_nmi_handler(NMI_IO_CHECK, hpwdt_pretimeout, 0, "hpwdt");
if (retval)
goto error2;
dev_info(&dev->dev,
"HPE Watchdog Timer Driver: NMI decoding initialized\n");
return 0;
error2:
unregister_nmi_handler(NMI_SERR, "hpwdt");
error1:
unregister_nmi_handler(NMI_UNKNOWN, "hpwdt");
error:
dev_warn(&dev->dev,
"Unable to register a die notifier (err=%d).\n",
retval);
return retval;
#endif /* CONFIG_HPWDT_NMI_DECODING */
return 0;
}
static void hpwdt_exit_nmi_decoding(void)
{
#ifdef CONFIG_HPWDT_NMI_DECODING
unregister_nmi_handler(NMI_UNKNOWN, "hpwdt");
unregister_nmi_handler(NMI_SERR, "hpwdt");
unregister_nmi_handler(NMI_IO_CHECK, "hpwdt");
#endif
}
static int hpwdt_init_one(struct pci_dev *dev,
const struct pci_device_id *ent)
{
int retval;
/*
* First let's find out if we are on an iLO2+ server. We will
* not run on a legacy ASM box.
* So we only support the G5 ProLiant servers and higher.
*/
if (dev->subsystem_vendor != PCI_VENDOR_ID_HP &&
dev->subsystem_vendor != PCI_VENDOR_ID_HP_3PAR) {
dev_warn(&dev->dev,
"This server does not have an iLO2+ ASIC.\n");
return -ENODEV;
}
if (pci_match_id(hpwdt_blacklist, dev)) {
dev_dbg(&dev->dev, "Not supported on this device\n");
return -ENODEV;
}
if (pci_enable_device(dev)) {
dev_warn(&dev->dev,
"Not possible to enable PCI Device: 0x%x:0x%x.\n",
ent->vendor, ent->device);
return -ENODEV;
}
pci_mem_addr = pci_iomap(dev, 1, 0x80);
if (!pci_mem_addr) {
dev_warn(&dev->dev,
"Unable to detect the iLO2+ server memory.\n");
retval = -ENOMEM;
goto error_pci_iomap;
}
hpwdt_nmistat = pci_mem_addr + 0x6e;
hpwdt_timer_reg = pci_mem_addr + 0x70;
hpwdt_timer_con = pci_mem_addr + 0x72;
/* Have the core update running timer until user space is ready */
if (hpwdt_hw_is_running()) {
dev_info(&dev->dev, "timer is running\n");
set_bit(WDOG_HW_RUNNING, &hpwdt_dev.status);
}
/* Initialize NMI Decoding functionality */
retval = hpwdt_init_nmi_decoding(dev);
if (retval != 0)
goto error_init_nmi_decoding;
watchdog_stop_on_unregister(&hpwdt_dev);
watchdog_set_nowayout(&hpwdt_dev, nowayout);
watchdog_init_timeout(&hpwdt_dev, soft_margin, NULL);
if (is_kdump_kernel()) {
pretimeout = false;
kdumptimeout = 0;
}
if (pretimeout && hpwdt_dev.timeout <= PRETIMEOUT_SEC) {
dev_warn(&dev->dev, "timeout <= pretimeout. Setting pretimeout to zero\n");
pretimeout = false;
}
hpwdt_dev.pretimeout = pretimeout ? PRETIMEOUT_SEC : 0;
kdumptimeout = min(kdumptimeout, HPWDT_MAX_TIMER);
hpwdt_dev.parent = &dev->dev;
retval = watchdog_register_device(&hpwdt_dev);
if (retval < 0)
goto error_wd_register;
dev_info(&dev->dev, "HPE Watchdog Timer Driver: Version: %s\n",
HPWDT_VERSION);
dev_info(&dev->dev, "timeout: %d seconds (nowayout=%d)\n",
hpwdt_dev.timeout, nowayout);
dev_info(&dev->dev, "pretimeout: %s.\n",
pretimeout ? "on" : "off");
dev_info(&dev->dev, "kdumptimeout: %d.\n", kdumptimeout);
if (dev->subsystem_vendor == PCI_VENDOR_ID_HP_3PAR)
ilo5 = true;
return 0;
error_wd_register:
hpwdt_exit_nmi_decoding();
error_init_nmi_decoding:
pci_iounmap(dev, pci_mem_addr);
error_pci_iomap:
pci_disable_device(dev);
return retval;
}
static void hpwdt_exit(struct pci_dev *dev)
{
watchdog_unregister_device(&hpwdt_dev);
hpwdt_exit_nmi_decoding();
pci_iounmap(dev, pci_mem_addr);
pci_disable_device(dev);
}
static struct pci_driver hpwdt_driver = {
.name = "hpwdt",
.id_table = hpwdt_devices,
.probe = hpwdt_init_one,
.remove = hpwdt_exit,
};
MODULE_AUTHOR("Tom Mingarelli");
MODULE_DESCRIPTION("hpe watchdog driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(HPWDT_VERSION);
module_param(soft_margin, int, 0);
MODULE_PARM_DESC(soft_margin, "Watchdog timeout in seconds");
module_param_named(timeout, soft_margin, int, 0);
MODULE_PARM_DESC(timeout, "Alias of soft_margin");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
module_param(kdumptimeout, int, 0444);
MODULE_PARM_DESC(kdumptimeout, "Timeout applied for crash kernel transition in seconds");
#ifdef CONFIG_HPWDT_NMI_DECODING
module_param(pretimeout, bool, 0);
MODULE_PARM_DESC(pretimeout, "Watchdog pretimeout enabled");
#endif
module_pci_driver(hpwdt_driver);
| linux-master | drivers/watchdog/hpwdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for watchdog device controlled through GPIO-line
*
* Author: 2013, Alexander Shiyan <[email protected]>
*/
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#define SOFT_TIMEOUT_MIN 1
#define SOFT_TIMEOUT_DEF 60
enum {
HW_ALGO_TOGGLE,
HW_ALGO_LEVEL,
};
struct gpio_wdt_priv {
struct gpio_desc *gpiod;
bool state;
bool always_running;
unsigned int hw_algo;
struct watchdog_device wdd;
};
static void gpio_wdt_disable(struct gpio_wdt_priv *priv)
{
/* Eternal ping */
gpiod_set_value_cansleep(priv->gpiod, 1);
/* Put GPIO back to tristate */
if (priv->hw_algo == HW_ALGO_TOGGLE)
gpiod_direction_input(priv->gpiod);
}
static int gpio_wdt_ping(struct watchdog_device *wdd)
{
struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd);
switch (priv->hw_algo) {
case HW_ALGO_TOGGLE:
/* Toggle output pin */
priv->state = !priv->state;
gpiod_set_value_cansleep(priv->gpiod, priv->state);
break;
case HW_ALGO_LEVEL:
/* Pulse */
gpiod_set_value_cansleep(priv->gpiod, 1);
udelay(1);
gpiod_set_value_cansleep(priv->gpiod, 0);
break;
}
return 0;
}
static int gpio_wdt_start(struct watchdog_device *wdd)
{
struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd);
priv->state = 0;
gpiod_direction_output(priv->gpiod, priv->state);
set_bit(WDOG_HW_RUNNING, &wdd->status);
return gpio_wdt_ping(wdd);
}
static int gpio_wdt_stop(struct watchdog_device *wdd)
{
struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd);
if (!priv->always_running) {
gpio_wdt_disable(priv);
} else {
set_bit(WDOG_HW_RUNNING, &wdd->status);
}
return 0;
}
static const struct watchdog_info gpio_wdt_ident = {
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT,
.identity = "GPIO Watchdog",
};
static const struct watchdog_ops gpio_wdt_ops = {
.owner = THIS_MODULE,
.start = gpio_wdt_start,
.stop = gpio_wdt_stop,
.ping = gpio_wdt_ping,
};
static int gpio_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct gpio_wdt_priv *priv;
enum gpiod_flags gflags;
unsigned int hw_margin;
const char *algo;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
ret = of_property_read_string(np, "hw_algo", &algo);
if (ret)
return ret;
if (!strcmp(algo, "toggle")) {
priv->hw_algo = HW_ALGO_TOGGLE;
gflags = GPIOD_IN;
} else if (!strcmp(algo, "level")) {
priv->hw_algo = HW_ALGO_LEVEL;
gflags = GPIOD_OUT_LOW;
} else {
return -EINVAL;
}
priv->gpiod = devm_gpiod_get(dev, NULL, gflags);
if (IS_ERR(priv->gpiod))
return PTR_ERR(priv->gpiod);
ret = of_property_read_u32(np,
"hw_margin_ms", &hw_margin);
if (ret)
return ret;
/* Disallow values lower than 2 and higher than 65535 ms */
if (hw_margin < 2 || hw_margin > 65535)
return -EINVAL;
priv->always_running = of_property_read_bool(np,
"always-running");
watchdog_set_drvdata(&priv->wdd, priv);
priv->wdd.info = &gpio_wdt_ident;
priv->wdd.ops = &gpio_wdt_ops;
priv->wdd.min_timeout = SOFT_TIMEOUT_MIN;
priv->wdd.max_hw_heartbeat_ms = hw_margin;
priv->wdd.parent = dev;
priv->wdd.timeout = SOFT_TIMEOUT_DEF;
watchdog_init_timeout(&priv->wdd, 0, dev);
watchdog_set_nowayout(&priv->wdd, nowayout);
watchdog_stop_on_reboot(&priv->wdd);
if (priv->always_running)
gpio_wdt_start(&priv->wdd);
return devm_watchdog_register_device(dev, &priv->wdd);
}
static const struct of_device_id gpio_wdt_dt_ids[] = {
{ .compatible = "linux,wdt-gpio", },
{ }
};
MODULE_DEVICE_TABLE(of, gpio_wdt_dt_ids);
static struct platform_driver gpio_wdt_driver = {
.driver = {
.name = "gpio-wdt",
.of_match_table = gpio_wdt_dt_ids,
},
.probe = gpio_wdt_probe,
};
#ifdef CONFIG_GPIO_WATCHDOG_ARCH_INITCALL
static int __init gpio_wdt_init(void)
{
return platform_driver_register(&gpio_wdt_driver);
}
arch_initcall(gpio_wdt_init);
#else
module_platform_driver(gpio_wdt_driver);
#endif
MODULE_AUTHOR("Alexander Shiyan <[email protected]>");
MODULE_DESCRIPTION("GPIO Watchdog");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/gpio_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Watchdog driver for IMX2 and later processors
*
* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <[email protected]>
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* some parts adapted by similar drivers from Darius Augulis and Vladimir
* Zapolskiy, additional improvements by Wim Van Sebroeck.
*
* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
*
* MX1: MX2+:
* ---- -----
* Registers: 32-bit 16-bit
* Stopable timer: Yes No
* Need to enable clk: No Yes
* Halt on suspend: Manual Can be automatic
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
#define DRIVER_NAME "imx2-wdt"
#define IMX2_WDT_WCR 0x00 /* Control Register */
#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WDW BIT(7) /* -> Watchdog disable for WAIT */
#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
#define IMX2_WDT_WSR 0x02 /* Service Register */
#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
#define IMX2_WDT_WMCR 0x08 /* Misc Register */
#define IMX2_WDT_MAX_TIME 128U
#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
struct imx2_wdt_data {
bool wdw_supported;
};
struct imx2_wdt_device {
struct clk *clk;
struct regmap *regmap;
struct watchdog_device wdog;
const struct imx2_wdt_data *data;
bool ext_reset;
bool clk_is_on;
bool no_ping;
bool sleep_wait;
};
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static unsigned timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
static const struct watchdog_info imx2_wdt_info = {
.identity = "imx2+ watchdog",
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};
static const struct watchdog_info imx2_wdt_pretimeout_info = {
.identity = "imx2+ watchdog",
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_PRETIMEOUT,
};
static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
void *data)
{
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
/* Use internal reset or external - not both */
if (wdev->ext_reset)
wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
else
wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
/* Assert SRS signal */
regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
/*
* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
* written twice), we add another two writes to ensure there must be at
* least two writes happen in the same one 32kHz clock period. We save
* the target check here, since the writes shouldn't be a huge burden
* for other platforms.
*/
regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
/* wait for reset to assert... */
mdelay(500);
return 0;
}
static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
u32 val;
regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
/* Suspend timer in low power mode, write once-only */
val |= IMX2_WDT_WCR_WDZST;
/* Suspend timer in low power WAIT mode, write once-only */
if (wdev->sleep_wait)
val |= IMX2_WDT_WCR_WDW;
/* Strip the old watchdog Time-Out value */
val &= ~IMX2_WDT_WCR_WT;
/* Generate internal chip-level reset if WDOG times out */
if (!wdev->ext_reset)
val &= ~IMX2_WDT_WCR_WRE;
/* Or if external-reset assert WDOG_B reset only on time-out */
else
val |= IMX2_WDT_WCR_WRE;
/* Keep Watchdog Disabled */
val &= ~IMX2_WDT_WCR_WDE;
/* Set the watchdog's Time-Out value */
val |= WDOG_SEC_TO_COUNT(wdog->timeout);
regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
/* enable the watchdog */
val |= IMX2_WDT_WCR_WDE;
regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}
static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
u32 val;
regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
return val & IMX2_WDT_WCR_WDE;
}
static int imx2_wdt_ping(struct watchdog_device *wdog)
{
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
if (!wdev->clk_is_on)
return 0;
regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
return 0;
}
static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int new_timeout)
{
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
WDOG_SEC_TO_COUNT(new_timeout));
}
static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int new_timeout)
{
unsigned int actual;
actual = min(new_timeout, IMX2_WDT_MAX_TIME);
__imx2_wdt_set_timeout(wdog, actual);
wdog->timeout = new_timeout;
return 0;
}
static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
unsigned int new_pretimeout)
{
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
if (new_pretimeout >= IMX2_WDT_MAX_TIME)
return -EINVAL;
wdog->pretimeout = new_pretimeout;
regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
return 0;
}
static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
{
struct watchdog_device *wdog = wdog_arg;
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
watchdog_notify_pretimeout(wdog);
return IRQ_HANDLED;
}
static int imx2_wdt_start(struct watchdog_device *wdog)
{
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
if (imx2_wdt_is_running(wdev))
imx2_wdt_set_timeout(wdog, wdog->timeout);
else
imx2_wdt_setup(wdog);
set_bit(WDOG_HW_RUNNING, &wdog->status);
return imx2_wdt_ping(wdog);
}
static const struct watchdog_ops imx2_wdt_ops = {
.owner = THIS_MODULE,
.start = imx2_wdt_start,
.ping = imx2_wdt_ping,
.set_timeout = imx2_wdt_set_timeout,
.set_pretimeout = imx2_wdt_set_pretimeout,
.restart = imx2_wdt_restart,
};
static const struct regmap_config imx2_wdt_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x8,
};
static void imx2_wdt_action(void *data)
{
clk_disable_unprepare(data);
}
static int __init imx2_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct imx2_wdt_device *wdev;
struct watchdog_device *wdog;
void __iomem *base;
int ret;
u32 val;
wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
if (!wdev)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
&imx2_wdt_regmap_config);
if (IS_ERR(wdev->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(wdev->regmap);
}
wdev->clk = devm_clk_get(dev, NULL);
if (IS_ERR(wdev->clk)) {
dev_err(dev, "can't get Watchdog clock\n");
return PTR_ERR(wdev->clk);
}
wdog = &wdev->wdog;
wdog->info = &imx2_wdt_info;
wdog->ops = &imx2_wdt_ops;
wdog->min_timeout = 1;
wdog->timeout = IMX2_WDT_DEFAULT_TIME;
wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
wdog->parent = dev;
wdev->data = of_device_get_match_data(dev);
ret = platform_get_irq(pdev, 0);
if (ret > 0)
if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
dev_name(dev), wdog))
wdog->info = &imx2_wdt_pretimeout_info;
ret = clk_prepare_enable(wdev->clk);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
if (ret)
return ret;
wdev->clk_is_on = true;
regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
wdev->ext_reset = of_property_read_bool(dev->of_node,
"fsl,ext-reset-output");
if (of_property_read_bool(dev->of_node, "fsl,suspend-in-wait")) {
if (!wdev->data->wdw_supported) {
dev_err(dev, "suspend-in-wait not supported\n");
return -EINVAL;
}
wdev->sleep_wait = true;
}
/*
* The i.MX7D doesn't support low power mode, so we need to ping the watchdog
* during suspend. Interaction with "fsl,suspend-in-wait" is unknown!
*/
wdev->no_ping = !of_device_is_compatible(dev->of_node, "fsl,imx7d-wdt");
platform_set_drvdata(pdev, wdog);
watchdog_set_drvdata(wdog, wdev);
watchdog_set_nowayout(wdog, nowayout);
watchdog_set_restart_priority(wdog, 128);
watchdog_init_timeout(wdog, timeout, dev);
if (wdev->no_ping)
watchdog_stop_ping_on_suspend(wdog);
if (imx2_wdt_is_running(wdev)) {
imx2_wdt_set_timeout(wdog, wdog->timeout);
set_bit(WDOG_HW_RUNNING, &wdog->status);
}
/*
* Disable the watchdog power down counter at boot. Otherwise the power
* down counter will pull down the #WDOG interrupt line for one clock
* cycle.
*/
regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
return devm_watchdog_register_device(dev, wdog);
}
static void imx2_wdt_shutdown(struct platform_device *pdev)
{
struct watchdog_device *wdog = platform_get_drvdata(pdev);
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
if (imx2_wdt_is_running(wdev)) {
/*
* We are running, configure max timeout before reboot
* will take place.
*/
imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
imx2_wdt_ping(wdog);
dev_crit(&pdev->dev, "Device shutdown.\n");
}
}
/* Disable watchdog if it is active or non-active but still running */
static int __maybe_unused imx2_wdt_suspend(struct device *dev)
{
struct watchdog_device *wdog = dev_get_drvdata(dev);
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
/* The watchdog IP block is running */
if (imx2_wdt_is_running(wdev)) {
/*
* Don't update wdog->timeout, we'll restore the current value
* during resume.
*/
__imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
imx2_wdt_ping(wdog);
}
if (wdev->no_ping) {
clk_disable_unprepare(wdev->clk);
wdev->clk_is_on = false;
}
return 0;
}
/* Enable watchdog and configure it if necessary */
static int __maybe_unused imx2_wdt_resume(struct device *dev)
{
struct watchdog_device *wdog = dev_get_drvdata(dev);
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
int ret;
if (wdev->no_ping) {
ret = clk_prepare_enable(wdev->clk);
if (ret)
return ret;
wdev->clk_is_on = true;
}
if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
/*
* If the watchdog is still active and resumes
* from deep sleep state, need to restart the
* watchdog again.
*/
imx2_wdt_setup(wdog);
}
if (imx2_wdt_is_running(wdev)) {
imx2_wdt_set_timeout(wdog, wdog->timeout);
imx2_wdt_ping(wdog);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
imx2_wdt_resume);
static struct imx2_wdt_data imx_wdt = {
.wdw_supported = true,
};
static struct imx2_wdt_data imx_wdt_legacy = {
.wdw_supported = false,
};
static const struct of_device_id imx2_wdt_dt_ids[] = {
{ .compatible = "fsl,imx21-wdt", .data = &imx_wdt_legacy },
{ .compatible = "fsl,imx25-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx27-wdt", .data = &imx_wdt_legacy },
{ .compatible = "fsl,imx31-wdt", .data = &imx_wdt_legacy },
{ .compatible = "fsl,imx35-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx50-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx51-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx53-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx6q-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx6sl-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx6sll-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx6sx-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx6ul-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx7d-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx8mm-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx8mn-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx8mp-wdt", .data = &imx_wdt },
{ .compatible = "fsl,imx8mq-wdt", .data = &imx_wdt },
{ .compatible = "fsl,ls1012a-wdt", .data = &imx_wdt_legacy },
{ .compatible = "fsl,ls1043a-wdt", .data = &imx_wdt_legacy },
{ .compatible = "fsl,vf610-wdt", .data = &imx_wdt },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
static struct platform_driver imx2_wdt_driver = {
.shutdown = imx2_wdt_shutdown,
.driver = {
.name = DRIVER_NAME,
.pm = &imx2_wdt_pm_ops,
.of_match_table = imx2_wdt_dt_ids,
},
};
module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
| linux-master | drivers/watchdog/imx2_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Spreadtrum watchdog driver
* Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define SPRD_WDT_LOAD_LOW 0x0
#define SPRD_WDT_LOAD_HIGH 0x4
#define SPRD_WDT_CTRL 0x8
#define SPRD_WDT_INT_CLR 0xc
#define SPRD_WDT_INT_RAW 0x10
#define SPRD_WDT_INT_MSK 0x14
#define SPRD_WDT_CNT_LOW 0x18
#define SPRD_WDT_CNT_HIGH 0x1c
#define SPRD_WDT_LOCK 0x20
#define SPRD_WDT_IRQ_LOAD_LOW 0x2c
#define SPRD_WDT_IRQ_LOAD_HIGH 0x30
/* WDT_CTRL */
#define SPRD_WDT_INT_EN_BIT BIT(0)
#define SPRD_WDT_CNT_EN_BIT BIT(1)
#define SPRD_WDT_NEW_VER_EN BIT(2)
#define SPRD_WDT_RST_EN_BIT BIT(3)
/* WDT_INT_CLR */
#define SPRD_WDT_INT_CLEAR_BIT BIT(0)
#define SPRD_WDT_RST_CLEAR_BIT BIT(3)
/* WDT_INT_RAW */
#define SPRD_WDT_INT_RAW_BIT BIT(0)
#define SPRD_WDT_RST_RAW_BIT BIT(3)
#define SPRD_WDT_LD_BUSY_BIT BIT(4)
/* 1s equal to 32768 counter steps */
#define SPRD_WDT_CNT_STEP 32768
#define SPRD_WDT_UNLOCK_KEY 0xe551
#define SPRD_WDT_MIN_TIMEOUT 3
#define SPRD_WDT_MAX_TIMEOUT 60
#define SPRD_WDT_CNT_HIGH_SHIFT 16
#define SPRD_WDT_LOW_VALUE_MASK GENMASK(15, 0)
#define SPRD_WDT_LOAD_TIMEOUT 11
struct sprd_wdt {
void __iomem *base;
struct watchdog_device wdd;
struct clk *enable;
struct clk *rtc_enable;
int irq;
};
static inline struct sprd_wdt *to_sprd_wdt(struct watchdog_device *wdd)
{
return container_of(wdd, struct sprd_wdt, wdd);
}
static inline void sprd_wdt_lock(void __iomem *addr)
{
writel_relaxed(0x0, addr + SPRD_WDT_LOCK);
}
static inline void sprd_wdt_unlock(void __iomem *addr)
{
writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK);
}
static irqreturn_t sprd_wdt_isr(int irq, void *dev_id)
{
struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id;
sprd_wdt_unlock(wdt->base);
writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR);
sprd_wdt_lock(wdt->base);
watchdog_notify_pretimeout(&wdt->wdd);
return IRQ_HANDLED;
}
static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt)
{
u32 val;
val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) <<
SPRD_WDT_CNT_HIGH_SHIFT;
val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) &
SPRD_WDT_LOW_VALUE_MASK;
return val;
}
static int sprd_wdt_load_value(struct sprd_wdt *wdt, u32 timeout,
u32 pretimeout)
{
u32 val, delay_cnt = 0;
u32 tmr_step = timeout * SPRD_WDT_CNT_STEP;
u32 prtmr_step = pretimeout * SPRD_WDT_CNT_STEP;
/*
* Checking busy bit to make sure the previous loading operation is
* done. According to the specification, the busy bit would be set
* after a new loading operation and last 2 or 3 RTC clock
* cycles (about 60us~92us).
*/
do {
val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW);
if (!(val & SPRD_WDT_LD_BUSY_BIT))
break;
usleep_range(10, 100);
} while (delay_cnt++ < SPRD_WDT_LOAD_TIMEOUT);
if (delay_cnt >= SPRD_WDT_LOAD_TIMEOUT)
return -EBUSY;
sprd_wdt_unlock(wdt->base);
writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
SPRD_WDT_LOW_VALUE_MASK, wdt->base + SPRD_WDT_LOAD_HIGH);
writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK),
wdt->base + SPRD_WDT_LOAD_LOW);
writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
SPRD_WDT_LOW_VALUE_MASK,
wdt->base + SPRD_WDT_IRQ_LOAD_HIGH);
writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK,
wdt->base + SPRD_WDT_IRQ_LOAD_LOW);
sprd_wdt_lock(wdt->base);
return 0;
}
static int sprd_wdt_enable(struct sprd_wdt *wdt)
{
u32 val;
int ret;
ret = clk_prepare_enable(wdt->enable);
if (ret)
return ret;
ret = clk_prepare_enable(wdt->rtc_enable);
if (ret) {
clk_disable_unprepare(wdt->enable);
return ret;
}
sprd_wdt_unlock(wdt->base);
val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
val |= SPRD_WDT_NEW_VER_EN;
writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
sprd_wdt_lock(wdt->base);
return 0;
}
static void sprd_wdt_disable(void *_data)
{
struct sprd_wdt *wdt = _data;
sprd_wdt_unlock(wdt->base);
writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL);
sprd_wdt_lock(wdt->base);
clk_disable_unprepare(wdt->rtc_enable);
clk_disable_unprepare(wdt->enable);
}
static int sprd_wdt_start(struct watchdog_device *wdd)
{
struct sprd_wdt *wdt = to_sprd_wdt(wdd);
u32 val;
int ret;
ret = sprd_wdt_load_value(wdt, wdd->timeout, wdd->pretimeout);
if (ret)
return ret;
sprd_wdt_unlock(wdt->base);
val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
val |= SPRD_WDT_CNT_EN_BIT | SPRD_WDT_INT_EN_BIT | SPRD_WDT_RST_EN_BIT;
writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
sprd_wdt_lock(wdt->base);
set_bit(WDOG_HW_RUNNING, &wdd->status);
return 0;
}
static int sprd_wdt_stop(struct watchdog_device *wdd)
{
struct sprd_wdt *wdt = to_sprd_wdt(wdd);
u32 val;
sprd_wdt_unlock(wdt->base);
val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
val &= ~(SPRD_WDT_CNT_EN_BIT | SPRD_WDT_RST_EN_BIT |
SPRD_WDT_INT_EN_BIT);
writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
sprd_wdt_lock(wdt->base);
return 0;
}
static int sprd_wdt_set_timeout(struct watchdog_device *wdd,
u32 timeout)
{
struct sprd_wdt *wdt = to_sprd_wdt(wdd);
if (timeout == wdd->timeout)
return 0;
wdd->timeout = timeout;
return sprd_wdt_load_value(wdt, timeout, wdd->pretimeout);
}
static int sprd_wdt_set_pretimeout(struct watchdog_device *wdd,
u32 new_pretimeout)
{
struct sprd_wdt *wdt = to_sprd_wdt(wdd);
if (new_pretimeout < wdd->min_timeout)
return -EINVAL;
wdd->pretimeout = new_pretimeout;
return sprd_wdt_load_value(wdt, wdd->timeout, new_pretimeout);
}
static u32 sprd_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct sprd_wdt *wdt = to_sprd_wdt(wdd);
u32 val;
val = sprd_wdt_get_cnt_value(wdt);
return val / SPRD_WDT_CNT_STEP;
}
static const struct watchdog_ops sprd_wdt_ops = {
.owner = THIS_MODULE,
.start = sprd_wdt_start,
.stop = sprd_wdt_stop,
.set_timeout = sprd_wdt_set_timeout,
.set_pretimeout = sprd_wdt_set_pretimeout,
.get_timeleft = sprd_wdt_get_timeleft,
};
static const struct watchdog_info sprd_wdt_info = {
.options = WDIOF_SETTIMEOUT |
WDIOF_PRETIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "Spreadtrum Watchdog Timer",
};
static int sprd_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct sprd_wdt *wdt;
int ret;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
wdt->enable = devm_clk_get(dev, "enable");
if (IS_ERR(wdt->enable)) {
dev_err(dev, "can't get the enable clock\n");
return PTR_ERR(wdt->enable);
}
wdt->rtc_enable = devm_clk_get(dev, "rtc_enable");
if (IS_ERR(wdt->rtc_enable)) {
dev_err(dev, "can't get the rtc enable clock\n");
return PTR_ERR(wdt->rtc_enable);
}
wdt->irq = platform_get_irq(pdev, 0);
if (wdt->irq < 0)
return wdt->irq;
ret = devm_request_irq(dev, wdt->irq, sprd_wdt_isr, IRQF_NO_SUSPEND,
"sprd-wdt", (void *)wdt);
if (ret) {
dev_err(dev, "failed to register irq\n");
return ret;
}
wdt->wdd.info = &sprd_wdt_info;
wdt->wdd.ops = &sprd_wdt_ops;
wdt->wdd.parent = dev;
wdt->wdd.min_timeout = SPRD_WDT_MIN_TIMEOUT;
wdt->wdd.max_timeout = SPRD_WDT_MAX_TIMEOUT;
wdt->wdd.timeout = SPRD_WDT_MAX_TIMEOUT;
ret = sprd_wdt_enable(wdt);
if (ret) {
dev_err(dev, "failed to enable wdt\n");
return ret;
}
ret = devm_add_action_or_reset(dev, sprd_wdt_disable, wdt);
if (ret) {
dev_err(dev, "Failed to add wdt disable action\n");
return ret;
}
watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT);
watchdog_init_timeout(&wdt->wdd, 0, dev);
ret = devm_watchdog_register_device(dev, &wdt->wdd);
if (ret) {
sprd_wdt_disable(wdt);
return ret;
}
platform_set_drvdata(pdev, wdt);
return 0;
}
static int __maybe_unused sprd_wdt_pm_suspend(struct device *dev)
{
struct sprd_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
sprd_wdt_stop(&wdt->wdd);
sprd_wdt_disable(wdt);
return 0;
}
static int __maybe_unused sprd_wdt_pm_resume(struct device *dev)
{
struct sprd_wdt *wdt = dev_get_drvdata(dev);
int ret;
ret = sprd_wdt_enable(wdt);
if (ret)
return ret;
if (watchdog_active(&wdt->wdd))
ret = sprd_wdt_start(&wdt->wdd);
return ret;
}
static const struct dev_pm_ops sprd_wdt_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(sprd_wdt_pm_suspend,
sprd_wdt_pm_resume)
};
static const struct of_device_id sprd_wdt_match_table[] = {
{ .compatible = "sprd,sp9860-wdt", },
{},
};
MODULE_DEVICE_TABLE(of, sprd_wdt_match_table);
static struct platform_driver sprd_watchdog_driver = {
.probe = sprd_wdt_probe,
.driver = {
.name = "sprd-wdt",
.of_match_table = sprd_wdt_match_table,
.pm = &sprd_wdt_pm_ops,
},
};
module_platform_driver(sprd_watchdog_driver);
MODULE_AUTHOR("Eric Long <[email protected]>");
MODULE_DESCRIPTION("Spreadtrum Watchdog Timer Controller Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/sprd_wdt.c |
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <[email protected]>
*
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#define DEFAULT_TIMEOUT 30 /* seconds */
#define GXBB_WDT_CTRL_REG 0x0
#define GXBB_WDT_TCNT_REG 0x8
#define GXBB_WDT_RSET_REG 0xc
#define GXBB_WDT_CTRL_CLKDIV_EN BIT(25)
#define GXBB_WDT_CTRL_CLK_EN BIT(24)
#define GXBB_WDT_CTRL_EN BIT(18)
#define GXBB_WDT_CTRL_DIV_MASK (BIT(18) - 1)
#define GXBB_WDT_TCNT_SETUP_MASK (BIT(16) - 1)
#define GXBB_WDT_TCNT_CNT_SHIFT 16
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static unsigned int timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds="
__MODULE_STRING(DEFAULT_TIMEOUT) ")");
struct meson_gxbb_wdt {
void __iomem *reg_base;
struct watchdog_device wdt_dev;
struct clk *clk;
};
struct wdt_params {
u32 rst;
};
static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev)
{
struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
data->reg_base + GXBB_WDT_CTRL_REG);
return 0;
}
static int meson_gxbb_wdt_stop(struct watchdog_device *wdt_dev)
{
struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
data->reg_base + GXBB_WDT_CTRL_REG);
return 0;
}
static int meson_gxbb_wdt_ping(struct watchdog_device *wdt_dev)
{
struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
writel(0, data->reg_base + GXBB_WDT_RSET_REG);
return 0;
}
static int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
unsigned long tcnt = timeout * 1000;
if (tcnt > GXBB_WDT_TCNT_SETUP_MASK)
tcnt = GXBB_WDT_TCNT_SETUP_MASK;
wdt_dev->timeout = timeout;
meson_gxbb_wdt_ping(wdt_dev);
writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
return 0;
}
static unsigned int meson_gxbb_wdt_get_timeleft(struct watchdog_device *wdt_dev)
{
struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
unsigned long reg;
reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
(reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
}
static const struct watchdog_ops meson_gxbb_wdt_ops = {
.start = meson_gxbb_wdt_start,
.stop = meson_gxbb_wdt_stop,
.ping = meson_gxbb_wdt_ping,
.set_timeout = meson_gxbb_wdt_set_timeout,
.get_timeleft = meson_gxbb_wdt_get_timeleft,
};
static const struct watchdog_info meson_gxbb_wdt_info = {
.identity = "Meson GXBB Watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};
static int __maybe_unused meson_gxbb_wdt_resume(struct device *dev)
{
struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
if (watchdog_active(&data->wdt_dev))
meson_gxbb_wdt_start(&data->wdt_dev);
return 0;
}
static int __maybe_unused meson_gxbb_wdt_suspend(struct device *dev)
{
struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
if (watchdog_active(&data->wdt_dev))
meson_gxbb_wdt_stop(&data->wdt_dev);
return 0;
}
static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume)
};
static const struct wdt_params gxbb_params = {
.rst = BIT(21),
};
static const struct wdt_params t7_params = {
.rst = BIT(22),
};
static const struct of_device_id meson_gxbb_wdt_dt_ids[] = {
{ .compatible = "amlogic,meson-gxbb-wdt", .data = &gxbb_params, },
{ .compatible = "amlogic,t7-wdt", .data = &t7_params, },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids);
static int meson_gxbb_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct meson_gxbb_wdt *data;
struct wdt_params *params;
u32 ctrl_reg;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
data->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(data->clk))
return PTR_ERR(data->clk);
params = (struct wdt_params *)of_device_get_match_data(dev);
platform_set_drvdata(pdev, data);
data->wdt_dev.parent = dev;
data->wdt_dev.info = &meson_gxbb_wdt_info;
data->wdt_dev.ops = &meson_gxbb_wdt_ops;
data->wdt_dev.max_hw_heartbeat_ms = GXBB_WDT_TCNT_SETUP_MASK;
data->wdt_dev.min_timeout = 1;
data->wdt_dev.timeout = DEFAULT_TIMEOUT;
watchdog_init_timeout(&data->wdt_dev, timeout, dev);
watchdog_set_nowayout(&data->wdt_dev, nowayout);
watchdog_set_drvdata(&data->wdt_dev, data);
ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) &
GXBB_WDT_CTRL_EN;
if (ctrl_reg) {
/* Watchdog is running - keep it running but extend timeout
* to the maximum while setting the timebase
*/
set_bit(WDOG_HW_RUNNING, &data->wdt_dev.status);
meson_gxbb_wdt_set_timeout(&data->wdt_dev,
GXBB_WDT_TCNT_SETUP_MASK / 1000);
}
/* Setup with 1ms timebase */
ctrl_reg |= ((clk_get_rate(data->clk) / 1000) &
GXBB_WDT_CTRL_DIV_MASK) |
params->rst |
GXBB_WDT_CTRL_CLK_EN |
GXBB_WDT_CTRL_CLKDIV_EN;
writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);
meson_gxbb_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
return devm_watchdog_register_device(dev, &data->wdt_dev);
}
static struct platform_driver meson_gxbb_wdt_driver = {
.probe = meson_gxbb_wdt_probe,
.driver = {
.name = "meson-gxbb-wdt",
.pm = &meson_gxbb_wdt_pm_ops,
.of_match_table = meson_gxbb_wdt_dt_ids,
},
};
module_platform_driver(meson_gxbb_wdt_driver);
MODULE_AUTHOR("Neil Armstrong <[email protected]>");
MODULE_DESCRIPTION("Amlogic Meson GXBB Watchdog timer driver");
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | drivers/watchdog/meson_gxbb_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* sun4v watchdog timer
* (c) Copyright 2016 Oracle Corporation
*
* Implement a simple watchdog driver using the built-in sun4v hypervisor
* watchdog support. If time expires, the hypervisor stops or bounces
* the guest domain.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/watchdog.h>
#include <asm/hypervisor.h>
#include <asm/mdesc.h>
#define WDT_TIMEOUT 60
#define WDT_MAX_TIMEOUT 31536000
#define WDT_MIN_TIMEOUT 1
#define WDT_DEFAULT_RESOLUTION_MS 1000 /* 1 second */
static unsigned int timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
__MODULE_STRING(WDT_TIMEOUT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, S_IRUGO);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int sun4v_wdt_stop(struct watchdog_device *wdd)
{
sun4v_mach_set_watchdog(0, NULL);
return 0;
}
static int sun4v_wdt_ping(struct watchdog_device *wdd)
{
int hverr;
/*
* HV watchdog timer will round up the timeout
* passed in to the nearest multiple of the
* watchdog resolution in milliseconds.
*/
hverr = sun4v_mach_set_watchdog(wdd->timeout * 1000, NULL);
if (hverr == HV_EINVAL)
return -EINVAL;
return 0;
}
static int sun4v_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->timeout = timeout;
return 0;
}
static const struct watchdog_info sun4v_wdt_ident = {
.options = WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "sun4v hypervisor watchdog",
.firmware_version = 0,
};
static const struct watchdog_ops sun4v_wdt_ops = {
.owner = THIS_MODULE,
.start = sun4v_wdt_ping,
.stop = sun4v_wdt_stop,
.ping = sun4v_wdt_ping,
.set_timeout = sun4v_wdt_set_timeout,
};
static struct watchdog_device wdd = {
.info = &sun4v_wdt_ident,
.ops = &sun4v_wdt_ops,
.min_timeout = WDT_MIN_TIMEOUT,
.max_timeout = WDT_MAX_TIMEOUT,
.timeout = WDT_TIMEOUT,
};
static int __init sun4v_wdt_init(void)
{
struct mdesc_handle *handle;
u64 node;
const u64 *value;
int err = 0;
unsigned long major = 1, minor = 1;
/*
* There are 2 properties that can be set from the control
* domain for the watchdog.
* watchdog-resolution
* watchdog-max-timeout
*
* We can expect a handle to be returned otherwise something
* serious is wrong. Correct to return -ENODEV here.
*/
handle = mdesc_grab();
if (!handle)
return -ENODEV;
node = mdesc_node_by_name(handle, MDESC_NODE_NULL, "platform");
err = -ENODEV;
if (node == MDESC_NODE_NULL)
goto out_release;
/*
* This is a safe way to validate if we are on the right
* platform.
*/
if (sun4v_hvapi_register(HV_GRP_CORE, major, &minor))
goto out_hv_unreg;
/* Allow value of watchdog-resolution up to 1s (default) */
value = mdesc_get_property(handle, node, "watchdog-resolution", NULL);
err = -EINVAL;
if (value) {
if (*value == 0 ||
*value > WDT_DEFAULT_RESOLUTION_MS)
goto out_hv_unreg;
}
value = mdesc_get_property(handle, node, "watchdog-max-timeout", NULL);
if (value) {
/*
* If the property value (in ms) is smaller than
* min_timeout, return -EINVAL.
*/
if (*value < wdd.min_timeout * 1000)
goto out_hv_unreg;
/*
* If the property value is smaller than
* default max_timeout then set watchdog max_timeout to
* the value of the property in seconds.
*/
if (*value < wdd.max_timeout * 1000)
wdd.max_timeout = *value / 1000;
}
watchdog_init_timeout(&wdd, timeout, NULL);
watchdog_set_nowayout(&wdd, nowayout);
err = watchdog_register_device(&wdd);
if (err)
goto out_hv_unreg;
pr_info("initialized (timeout=%ds, nowayout=%d)\n",
wdd.timeout, nowayout);
mdesc_release(handle);
return 0;
out_hv_unreg:
sun4v_hvapi_unregister(HV_GRP_CORE);
out_release:
mdesc_release(handle);
return err;
}
static void __exit sun4v_wdt_exit(void)
{
sun4v_hvapi_unregister(HV_GRP_CORE);
watchdog_unregister_device(&wdd);
}
module_init(sun4v_wdt_init);
module_exit(sun4v_wdt_exit);
MODULE_AUTHOR("Wim Coekaerts <[email protected]>");
MODULE_DESCRIPTION("sun4v watchdog driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sun4v_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Mediatek Watchdog Driver
*
* Copyright (C) 2014 Matthias Brugger
*
* Matthias Brugger <[email protected]>
*
* Based on sunxi_wdt.c
*/
#include <dt-bindings/reset/mt2712-resets.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/reset/mt8186-resets.h>
#include <dt-bindings/reset/mt8188-resets.h>
#include <dt-bindings/reset/mt8192-resets.h>
#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/interrupt.h>
#define WDT_MAX_TIMEOUT 31
#define WDT_MIN_TIMEOUT 2
#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
#define WDT_LENGTH 0x04
#define WDT_LENGTH_KEY 0x8
#define WDT_RST 0x08
#define WDT_RST_RELOAD 0x1971
#define WDT_MODE 0x00
#define WDT_MODE_EN (1 << 0)
#define WDT_MODE_EXT_POL_LOW (0 << 1)
#define WDT_MODE_EXT_POL_HIGH (1 << 1)
#define WDT_MODE_EXRST_EN (1 << 2)
#define WDT_MODE_IRQ_EN (1 << 3)
#define WDT_MODE_AUTO_START (1 << 4)
#define WDT_MODE_DUAL_EN (1 << 6)
#define WDT_MODE_CNT_SEL (1 << 8)
#define WDT_MODE_KEY 0x22000000
#define WDT_SWRST 0x14
#define WDT_SWRST_KEY 0x1209
#define WDT_SWSYSRST 0x18U
#define WDT_SWSYS_RST_KEY 0x88000000
#define DRV_NAME "mtk-wdt"
#define DRV_VERSION "1.0"
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;
struct mtk_wdt_dev {
struct watchdog_device wdt_dev;
void __iomem *wdt_base;
spinlock_t lock; /* protects WDT_SWSYSRST reg */
struct reset_controller_dev rcdev;
bool disable_wdt_extrst;
bool reset_by_toprgu;
};
struct mtk_wdt_data {
int toprgu_sw_rst_num;
};
static const struct mtk_wdt_data mt2712_data = {
.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt6795_data = {
.toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt7986_data = {
.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt8183_data = {
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt8186_data = {
.toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt8188_data = {
.toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt8192_data = {
.toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
};
static const struct mtk_wdt_data mt8195_data = {
.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
};
static int toprgu_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
unsigned int tmp;
unsigned long flags;
struct mtk_wdt_dev *data =
container_of(rcdev, struct mtk_wdt_dev, rcdev);
spin_lock_irqsave(&data->lock, flags);
tmp = readl(data->wdt_base + WDT_SWSYSRST);
if (assert)
tmp |= BIT(id);
else
tmp &= ~BIT(id);
tmp |= WDT_SWSYS_RST_KEY;
writel(tmp, data->wdt_base + WDT_SWSYSRST);
spin_unlock_irqrestore(&data->lock, flags);
return 0;
}
static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return toprgu_reset_update(rcdev, id, true);
}
static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return toprgu_reset_update(rcdev, id, false);
}
static int toprgu_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = toprgu_reset_assert(rcdev, id);
if (ret)
return ret;
return toprgu_reset_deassert(rcdev, id);
}
static const struct reset_control_ops toprgu_reset_ops = {
.assert = toprgu_reset_assert,
.deassert = toprgu_reset_deassert,
.reset = toprgu_reset,
};
static int toprgu_register_reset_controller(struct platform_device *pdev,
int rst_num)
{
int ret;
struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
spin_lock_init(&mtk_wdt->lock);
mtk_wdt->rcdev.owner = THIS_MODULE;
mtk_wdt->rcdev.nr_resets = rst_num;
mtk_wdt->rcdev.ops = &toprgu_reset_ops;
mtk_wdt->rcdev.of_node = pdev->dev.of_node;
ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
if (ret != 0)
dev_err(&pdev->dev,
"couldn't register wdt reset controller: %d\n", ret);
return ret;
}
static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
unsigned long action, void *data)
{
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base;
wdt_base = mtk_wdt->wdt_base;
while (1) {
writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
mdelay(5);
}
return 0;
}
static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
{
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = mtk_wdt->wdt_base;
iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
return 0;
}
static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = mtk_wdt->wdt_base;
u32 reg;
wdt_dev->timeout = timeout;
/*
* In dual mode, irq will be triggered at timeout / 2
* the real timeout occurs at timeout
*/
if (wdt_dev->pretimeout)
wdt_dev->pretimeout = timeout / 2;
/*
* One bit is the value of 512 ticks
* The clock has 32 KHz
*/
reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
| WDT_LENGTH_KEY;
iowrite32(reg, wdt_base + WDT_LENGTH);
mtk_wdt_ping(wdt_dev);
return 0;
}
static void mtk_wdt_init(struct watchdog_device *wdt_dev)
{
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base;
wdt_base = mtk_wdt->wdt_base;
if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
}
}
static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
{
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = mtk_wdt->wdt_base;
u32 reg;
reg = readl(wdt_base + WDT_MODE);
reg &= ~WDT_MODE_EN;
reg |= WDT_MODE_KEY;
iowrite32(reg, wdt_base + WDT_MODE);
return 0;
}
static int mtk_wdt_start(struct watchdog_device *wdt_dev)
{
u32 reg;
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = mtk_wdt->wdt_base;
int ret;
ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
if (ret < 0)
return ret;
reg = ioread32(wdt_base + WDT_MODE);
if (wdt_dev->pretimeout)
reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
else
reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
if (mtk_wdt->disable_wdt_extrst)
reg &= ~WDT_MODE_EXRST_EN;
if (mtk_wdt->reset_by_toprgu)
reg |= WDT_MODE_CNT_SEL;
reg |= (WDT_MODE_EN | WDT_MODE_KEY);
iowrite32(reg, wdt_base + WDT_MODE);
return 0;
}
static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
void __iomem *wdt_base = mtk_wdt->wdt_base;
u32 reg = ioread32(wdt_base + WDT_MODE);
if (timeout && !wdd->pretimeout) {
wdd->pretimeout = wdd->timeout / 2;
reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
} else if (!timeout && wdd->pretimeout) {
wdd->pretimeout = 0;
reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
} else {
return 0;
}
reg |= WDT_MODE_KEY;
iowrite32(reg, wdt_base + WDT_MODE);
return mtk_wdt_set_timeout(wdd, wdd->timeout);
}
static irqreturn_t mtk_wdt_isr(int irq, void *arg)
{
struct watchdog_device *wdd = arg;
watchdog_notify_pretimeout(wdd);
return IRQ_HANDLED;
}
static const struct watchdog_info mtk_wdt_info = {
.identity = DRV_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static const struct watchdog_info mtk_wdt_pt_info = {
.identity = DRV_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_PRETIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops mtk_wdt_ops = {
.owner = THIS_MODULE,
.start = mtk_wdt_start,
.stop = mtk_wdt_stop,
.ping = mtk_wdt_ping,
.set_timeout = mtk_wdt_set_timeout,
.set_pretimeout = mtk_wdt_set_pretimeout,
.restart = mtk_wdt_restart,
};
static int mtk_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_wdt_dev *mtk_wdt;
const struct mtk_wdt_data *wdt_data;
int err, irq;
mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
if (!mtk_wdt)
return -ENOMEM;
platform_set_drvdata(pdev, mtk_wdt);
mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mtk_wdt->wdt_base))
return PTR_ERR(mtk_wdt->wdt_base);
irq = platform_get_irq_optional(pdev, 0);
if (irq > 0) {
err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
&mtk_wdt->wdt_dev);
if (err)
return err;
mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
} else {
if (irq == -EPROBE_DEFER)
return -EPROBE_DEFER;
mtk_wdt->wdt_dev.info = &mtk_wdt_info;
}
mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
mtk_wdt->wdt_dev.parent = dev;
watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
mtk_wdt_init(&mtk_wdt->wdt_dev);
watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
if (unlikely(err))
return err;
dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
mtk_wdt->wdt_dev.timeout, nowayout);
wdt_data = of_device_get_match_data(dev);
if (wdt_data) {
err = toprgu_register_reset_controller(pdev,
wdt_data->toprgu_sw_rst_num);
if (err)
return err;
}
mtk_wdt->disable_wdt_extrst =
of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
mtk_wdt->reset_by_toprgu =
of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");
return 0;
}
static int mtk_wdt_suspend(struct device *dev)
{
struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
if (watchdog_active(&mtk_wdt->wdt_dev))
mtk_wdt_stop(&mtk_wdt->wdt_dev);
return 0;
}
static int mtk_wdt_resume(struct device *dev)
{
struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
if (watchdog_active(&mtk_wdt->wdt_dev)) {
mtk_wdt_start(&mtk_wdt->wdt_dev);
mtk_wdt_ping(&mtk_wdt->wdt_dev);
}
return 0;
}
static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
mtk_wdt_suspend, mtk_wdt_resume);
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.driver = {
.name = DRV_NAME,
.pm = pm_sleep_ptr(&mtk_wdt_pm_ops),
.of_match_table = mtk_wdt_dt_ids,
},
};
module_platform_driver(mtk_wdt_driver);
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Matthias Brugger <[email protected]>");
MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
| linux-master | drivers/watchdog/mtk_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Watchdog driver for Renesas WDT watchdog
*
* Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <[email protected]>
* Copyright (C) 2015-17 Renesas Electronics Corporation
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/smp.h>
#include <linux/sys_soc.h>
#include <linux/watchdog.h>
#define RWTCNT 0
#define RWTCSRA 4
#define RWTCSRA_WOVF BIT(4)
#define RWTCSRA_WRFLG BIT(5)
#define RWTCSRA_TME BIT(7)
#define RWTCSRB 8
#define RWDT_DEFAULT_TIMEOUT 60U
/*
* In probe, clk_rate is checked to be not more than 16 bit * biggest clock
* divider (12 bits). d is only a factor to fully utilize the WDT counter and
* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
*/
#define MUL_BY_CLKS_PER_SEC(p, d) \
DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
struct rwdt_priv {
void __iomem *base;
struct watchdog_device wdev;
unsigned long clk_rate;
u8 cks;
struct clk *clk;
};
static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
{
if (reg == RWTCNT)
val |= 0x5a5a0000;
else
val |= 0xa5a5a500;
writel_relaxed(val, priv->base + reg);
}
static int rwdt_init_timeout(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
return 0;
}
static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
{
unsigned int delay;
delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
usleep_range(delay, 2 * delay);
}
static int rwdt_start(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
u8 val;
pm_runtime_get_sync(wdev->parent);
/* Stop the timer before we modify any register */
val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
rwdt_write(priv, val, RWTCSRA);
/* Delay 2 cycles before setting watchdog counter */
rwdt_wait_cycles(priv, 2);
rwdt_init_timeout(wdev);
rwdt_write(priv, priv->cks, RWTCSRA);
rwdt_write(priv, 0, RWTCSRB);
while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
cpu_relax();
rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
return 0;
}
static int rwdt_stop(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
rwdt_write(priv, priv->cks, RWTCSRA);
/* Delay 3 cycles before disabling module clock */
rwdt_wait_cycles(priv, 3);
pm_runtime_put(wdev->parent);
return 0;
}
static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
u16 val = readw_relaxed(priv->base + RWTCNT);
return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
}
/* needs to be atomic - no RPM, no usleep_range, no scheduling! */
static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
void *data)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
u8 val;
clk_prepare_enable(priv->clk);
/* Stop the timer before we modify any register */
val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
rwdt_write(priv, val, RWTCSRA);
/* Delay 2 cycles before setting watchdog counter */
udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
rwdt_write(priv, 0xffff, RWTCNT);
/* smallest divider to reboot soon */
rwdt_write(priv, 0, RWTCSRA);
readb_poll_timeout_atomic(priv->base + RWTCSRA, val,
!(val & RWTCSRA_WRFLG), 1, 100);
rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
/* wait 2 cycles, so watchdog will trigger */
udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
return 0;
}
static const struct watchdog_info rwdt_ident = {
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
WDIOF_CARDRESET,
.identity = "Renesas WDT Watchdog",
};
static const struct watchdog_ops rwdt_ops = {
.owner = THIS_MODULE,
.start = rwdt_start,
.stop = rwdt_stop,
.ping = rwdt_init_timeout,
.get_timeleft = rwdt_get_timeleft,
.restart = rwdt_restart,
};
#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
/*
* Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
*/
static const struct soc_device_attribute rwdt_quirks_match[] = {
{
.soc_id = "r8a7790",
.revision = "ES1.*",
.data = (void *)1, /* needs single CPU */
}, {
.soc_id = "r8a7791",
.revision = "ES1.*",
.data = (void *)1, /* needs single CPU */
}, {
.soc_id = "r8a7792",
.data = (void *)0, /* needs SMP disabled */
},
{ /* sentinel */ }
};
static bool rwdt_blacklisted(struct device *dev)
{
const struct soc_device_attribute *attr;
attr = soc_device_match(rwdt_quirks_match);
if (attr && setup_max_cpus > (uintptr_t)attr->data) {
dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
attr->revision);
return true;
}
return false;
}
#else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
static inline bool rwdt_blacklisted(struct device *dev) { return false; }
#endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
static int rwdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rwdt_priv *priv;
unsigned long clks_per_sec;
int ret, i;
u8 csra;
if (rwdt_blacklisted(dev))
return -ENODEV;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
priv->clk_rate = clk_get_rate(priv->clk);
csra = readb_relaxed(priv->base + RWTCSRA);
priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
pm_runtime_put(dev);
if (!priv->clk_rate) {
ret = -ENOENT;
goto out_pm_disable;
}
for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
clks_per_sec = priv->clk_rate / clk_divs[i];
if (clks_per_sec && clks_per_sec < 65536) {
priv->cks = i;
break;
}
}
if (i < 0) {
dev_err(dev, "Can't find suitable clock divider\n");
ret = -ERANGE;
goto out_pm_disable;
}
priv->wdev.info = &rwdt_ident;
priv->wdev.ops = &rwdt_ops;
priv->wdev.parent = dev;
priv->wdev.min_timeout = 1;
priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
platform_set_drvdata(pdev, priv);
watchdog_set_drvdata(&priv->wdev, priv);
watchdog_set_nowayout(&priv->wdev, nowayout);
watchdog_set_restart_priority(&priv->wdev, 0);
watchdog_stop_on_unregister(&priv->wdev);
/* This overrides the default timeout only if DT configuration was found */
watchdog_init_timeout(&priv->wdev, 0, dev);
/* Check if FW enabled the watchdog */
if (csra & RWTCSRA_TME) {
/* Ensure properly initialized dividers */
rwdt_start(&priv->wdev);
set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
}
ret = watchdog_register_device(&priv->wdev);
if (ret < 0)
goto out_pm_disable;
return 0;
out_pm_disable:
pm_runtime_disable(dev);
return ret;
}
static void rwdt_remove(struct platform_device *pdev)
{
struct rwdt_priv *priv = platform_get_drvdata(pdev);
watchdog_unregister_device(&priv->wdev);
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused rwdt_suspend(struct device *dev)
{
struct rwdt_priv *priv = dev_get_drvdata(dev);
if (watchdog_active(&priv->wdev))
rwdt_stop(&priv->wdev);
return 0;
}
static int __maybe_unused rwdt_resume(struct device *dev)
{
struct rwdt_priv *priv = dev_get_drvdata(dev);
if (watchdog_active(&priv->wdev))
rwdt_start(&priv->wdev);
return 0;
}
static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
static const struct of_device_id rwdt_ids[] = {
{ .compatible = "renesas,rcar-gen2-wdt", },
{ .compatible = "renesas,rcar-gen3-wdt", },
{ .compatible = "renesas,rcar-gen4-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rwdt_ids);
static struct platform_driver rwdt_driver = {
.driver = {
.name = "renesas_wdt",
.of_match_table = rwdt_ids,
.pm = &rwdt_pm_ops,
},
.probe = rwdt_probe,
.remove_new = rwdt_remove,
};
module_platform_driver(rwdt_driver);
MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Wolfram Sang <[email protected]>");
| linux-master | drivers/watchdog/renesas_wdt.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/property.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
#define PON_POFF_REASON1 0x0c
#define PON_POFF_REASON1_PMIC_WD BIT(2)
#define PON_POFF_REASON2 0x0d
#define PON_POFF_REASON2_UVLO BIT(5)
#define PON_POFF_REASON2_OTST3 BIT(6)
#define PON_INT_RT_STS 0x10
#define PMIC_WD_BARK_STS_BIT BIT(6)
#define PON_PMIC_WD_RESET_S1_TIMER 0x54
#define PON_PMIC_WD_RESET_S2_TIMER 0x55
#define PON_PMIC_WD_RESET_S2_CTL 0x56
#define RESET_TYPE_WARM 0x01
#define RESET_TYPE_SHUTDOWN 0x04
#define RESET_TYPE_HARD 0x07
#define PON_PMIC_WD_RESET_S2_CTL2 0x57
#define S2_RESET_EN_BIT BIT(7)
#define PON_PMIC_WD_RESET_PET 0x58
#define WATCHDOG_PET_BIT BIT(0)
#define PM8916_WDT_DEFAULT_TIMEOUT 32
#define PM8916_WDT_MIN_TIMEOUT 1
#define PM8916_WDT_MAX_TIMEOUT 127
struct pm8916_wdt {
struct regmap *regmap;
struct watchdog_device wdev;
u32 baseaddr;
};
static int pm8916_wdt_start(struct watchdog_device *wdev)
{
struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
return regmap_update_bits(wdt->regmap,
wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
S2_RESET_EN_BIT, S2_RESET_EN_BIT);
}
static int pm8916_wdt_stop(struct watchdog_device *wdev)
{
struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
return regmap_update_bits(wdt->regmap,
wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
S2_RESET_EN_BIT, 0);
}
static int pm8916_wdt_ping(struct watchdog_device *wdev)
{
struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
return regmap_write(wdt->regmap, wdt->baseaddr + PON_PMIC_WD_RESET_PET,
WATCHDOG_PET_BIT);
}
static int pm8916_wdt_configure_timers(struct watchdog_device *wdev)
{
struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
int err;
err = regmap_write(wdt->regmap,
wdt->baseaddr + PON_PMIC_WD_RESET_S1_TIMER,
wdev->timeout - wdev->pretimeout);
if (err)
return err;
return regmap_write(wdt->regmap,
wdt->baseaddr + PON_PMIC_WD_RESET_S2_TIMER,
wdev->pretimeout);
}
static int pm8916_wdt_set_timeout(struct watchdog_device *wdev,
unsigned int timeout)
{
wdev->timeout = timeout;
return pm8916_wdt_configure_timers(wdev);
}
static int pm8916_wdt_set_pretimeout(struct watchdog_device *wdev,
unsigned int pretimeout)
{
wdev->pretimeout = pretimeout;
return pm8916_wdt_configure_timers(wdev);
}
static irqreturn_t pm8916_wdt_isr(int irq, void *arg)
{
struct pm8916_wdt *wdt = arg;
int err, sts;
err = regmap_read(wdt->regmap, wdt->baseaddr + PON_INT_RT_STS, &sts);
if (err)
return IRQ_HANDLED;
if (sts & PMIC_WD_BARK_STS_BIT)
watchdog_notify_pretimeout(&wdt->wdev);
return IRQ_HANDLED;
}
static const struct watchdog_info pm8916_wdt_ident = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE |
WDIOF_OVERHEAT | WDIOF_CARDRESET | WDIOF_POWERUNDER,
.identity = "QCOM PM8916 PON WDT",
};
static const struct watchdog_info pm8916_wdt_pt_ident = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE |
WDIOF_OVERHEAT | WDIOF_CARDRESET | WDIOF_POWERUNDER |
WDIOF_PRETIMEOUT,
.identity = "QCOM PM8916 PON WDT",
};
static const struct watchdog_ops pm8916_wdt_ops = {
.owner = THIS_MODULE,
.start = pm8916_wdt_start,
.stop = pm8916_wdt_stop,
.ping = pm8916_wdt_ping,
.set_timeout = pm8916_wdt_set_timeout,
.set_pretimeout = pm8916_wdt_set_pretimeout,
};
static int pm8916_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pm8916_wdt *wdt;
struct device *parent;
unsigned int val;
int err, irq;
u8 poff[2];
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
parent = dev->parent;
/*
* The pm8916-pon-wdt is a child of the pon device, which is a child
* of the pm8916 mfd device. We want access to the pm8916 registers.
* Retrieve regmap from pm8916 (parent->parent) and base address
* from pm8916-pon (pon).
*/
wdt->regmap = dev_get_regmap(parent->parent, NULL);
if (!wdt->regmap) {
dev_err(dev, "failed to locate regmap\n");
return -ENODEV;
}
err = device_property_read_u32(parent, "reg", &wdt->baseaddr);
if (err) {
dev_err(dev, "failed to get pm8916-pon address\n");
return err;
}
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
err = devm_request_irq(dev, irq, pm8916_wdt_isr, 0,
"pm8916_wdt", wdt);
if (err)
return err;
wdt->wdev.info = &pm8916_wdt_pt_ident;
} else {
if (irq == -EPROBE_DEFER)
return -EPROBE_DEFER;
wdt->wdev.info = &pm8916_wdt_ident;
}
err = regmap_bulk_read(wdt->regmap, wdt->baseaddr + PON_POFF_REASON1,
&poff, ARRAY_SIZE(poff));
if (err) {
dev_err(dev, "failed to read POFF reason: %d\n", err);
return err;
}
dev_dbg(dev, "POFF reason: %#x %#x\n", poff[0], poff[1]);
if (poff[0] & PON_POFF_REASON1_PMIC_WD)
wdt->wdev.bootstatus |= WDIOF_CARDRESET;
if (poff[1] & PON_POFF_REASON2_UVLO)
wdt->wdev.bootstatus |= WDIOF_POWERUNDER;
if (poff[1] & PON_POFF_REASON2_OTST3)
wdt->wdev.bootstatus |= WDIOF_OVERHEAT;
err = regmap_read(wdt->regmap, wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
&val);
if (err) {
dev_err(dev, "failed to check if watchdog is active: %d\n", err);
return err;
}
if (val & S2_RESET_EN_BIT)
set_bit(WDOG_HW_RUNNING, &wdt->wdev.status);
/* Configure watchdog to hard-reset mode */
err = regmap_write(wdt->regmap,
wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL,
RESET_TYPE_HARD);
if (err) {
dev_err(dev, "failed configure watchdog\n");
return err;
}
wdt->wdev.ops = &pm8916_wdt_ops,
wdt->wdev.parent = dev;
wdt->wdev.min_timeout = PM8916_WDT_MIN_TIMEOUT;
wdt->wdev.max_timeout = PM8916_WDT_MAX_TIMEOUT;
wdt->wdev.timeout = PM8916_WDT_DEFAULT_TIMEOUT;
wdt->wdev.pretimeout = 0;
watchdog_set_drvdata(&wdt->wdev, wdt);
platform_set_drvdata(pdev, wdt);
watchdog_init_timeout(&wdt->wdev, 0, dev);
pm8916_wdt_configure_timers(&wdt->wdev);
return devm_watchdog_register_device(dev, &wdt->wdev);
}
static int __maybe_unused pm8916_wdt_suspend(struct device *dev)
{
struct pm8916_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdev))
return pm8916_wdt_stop(&wdt->wdev);
return 0;
}
static int __maybe_unused pm8916_wdt_resume(struct device *dev)
{
struct pm8916_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdev))
return pm8916_wdt_start(&wdt->wdev);
return 0;
}
static SIMPLE_DEV_PM_OPS(pm8916_wdt_pm_ops, pm8916_wdt_suspend,
pm8916_wdt_resume);
static const struct of_device_id pm8916_wdt_id_table[] = {
{ .compatible = "qcom,pm8916-wdt" },
{ }
};
MODULE_DEVICE_TABLE(of, pm8916_wdt_id_table);
static struct platform_driver pm8916_wdt_driver = {
.probe = pm8916_wdt_probe,
.driver = {
.name = "pm8916-wdt",
.of_match_table = pm8916_wdt_id_table,
.pm = &pm8916_wdt_pm_ops,
},
};
module_platform_driver(pm8916_wdt_driver);
MODULE_AUTHOR("Loic Poulain <[email protected]>");
MODULE_DESCRIPTION("Qualcomm pm8916 watchdog driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/pm8916_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* intel-mid_wdt: generic Intel MID SCU watchdog driver
*
* Platforms supported so far:
* - Merrifield only
*
* Copyright (C) 2014 Intel Corporation. All rights reserved.
* Contact: David Cohen <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/nmi.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/platform_data/intel-mid_wdt.h>
#include <asm/intel_scu_ipc.h>
#include <asm/intel-mid.h>
#define IPC_WATCHDOG 0xf8
#define MID_WDT_PRETIMEOUT 15
#define MID_WDT_TIMEOUT_MIN (1 + MID_WDT_PRETIMEOUT)
#define MID_WDT_TIMEOUT_MAX 170
#define MID_WDT_DEFAULT_TIMEOUT 90
/* SCU watchdog messages */
enum {
SCU_WATCHDOG_START = 0,
SCU_WATCHDOG_STOP,
SCU_WATCHDOG_KEEPALIVE,
};
struct mid_wdt {
struct watchdog_device wd;
struct device *dev;
struct intel_scu_ipc_dev *scu;
};
static inline int
wdt_command(struct mid_wdt *mid, int sub, const void *in, size_t inlen, size_t size)
{
struct intel_scu_ipc_dev *scu = mid->scu;
return intel_scu_ipc_dev_command_with_size(scu, IPC_WATCHDOG, sub, in,
inlen, size, NULL, 0);
}
static int wdt_start(struct watchdog_device *wd)
{
struct mid_wdt *mid = watchdog_get_drvdata(wd);
int ret, in_size;
int timeout = wd->timeout;
struct ipc_wd_start {
u32 pretimeout;
u32 timeout;
} ipc_wd_start = { timeout - MID_WDT_PRETIMEOUT, timeout };
/*
* SCU expects the input size for watchdog IPC to be 2 which is the
* size of the structure in dwords. SCU IPC normally takes bytes
* but this is a special case where we specify size to be different
* than inlen.
*/
in_size = DIV_ROUND_UP(sizeof(ipc_wd_start), 4);
ret = wdt_command(mid, SCU_WATCHDOG_START, &ipc_wd_start,
sizeof(ipc_wd_start), in_size);
if (ret)
dev_crit(mid->dev, "error starting watchdog: %d\n", ret);
return ret;
}
static int wdt_ping(struct watchdog_device *wd)
{
struct mid_wdt *mid = watchdog_get_drvdata(wd);
int ret;
ret = wdt_command(mid, SCU_WATCHDOG_KEEPALIVE, NULL, 0, 0);
if (ret)
dev_crit(mid->dev, "Error executing keepalive: %d\n", ret);
return ret;
}
static int wdt_stop(struct watchdog_device *wd)
{
struct mid_wdt *mid = watchdog_get_drvdata(wd);
int ret;
ret = wdt_command(mid, SCU_WATCHDOG_STOP, NULL, 0, 0);
if (ret)
dev_crit(mid->dev, "Error stopping watchdog: %d\n", ret);
return ret;
}
static irqreturn_t mid_wdt_irq(int irq, void *dev_id)
{
panic("Kernel Watchdog");
/* This code should not be reached */
return IRQ_HANDLED;
}
static const struct watchdog_info mid_wdt_info = {
.identity = "Intel MID SCU watchdog",
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops mid_wdt_ops = {
.owner = THIS_MODULE,
.start = wdt_start,
.stop = wdt_stop,
.ping = wdt_ping,
};
static int mid_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdt_dev;
struct intel_mid_wdt_pdata *pdata = dev->platform_data;
struct mid_wdt *mid;
int ret;
if (!pdata) {
dev_err(dev, "missing platform data\n");
return -EINVAL;
}
if (pdata->probe) {
ret = pdata->probe(pdev);
if (ret)
return ret;
}
mid = devm_kzalloc(dev, sizeof(*mid), GFP_KERNEL);
if (!mid)
return -ENOMEM;
mid->dev = dev;
wdt_dev = &mid->wd;
wdt_dev->info = &mid_wdt_info;
wdt_dev->ops = &mid_wdt_ops;
wdt_dev->min_timeout = MID_WDT_TIMEOUT_MIN;
wdt_dev->max_timeout = MID_WDT_TIMEOUT_MAX;
wdt_dev->timeout = MID_WDT_DEFAULT_TIMEOUT;
wdt_dev->parent = dev;
watchdog_set_nowayout(wdt_dev, WATCHDOG_NOWAYOUT);
watchdog_set_drvdata(wdt_dev, mid);
mid->scu = devm_intel_scu_ipc_dev_get(dev);
if (!mid->scu)
return -EPROBE_DEFER;
ret = devm_request_irq(dev, pdata->irq, mid_wdt_irq,
IRQF_SHARED | IRQF_NO_SUSPEND, "watchdog",
wdt_dev);
if (ret) {
dev_err(dev, "error requesting warning irq %d\n", pdata->irq);
return ret;
}
/*
* The firmware followed by U-Boot leaves the watchdog running
* with the default threshold which may vary. When we get here
* we should make a decision to prevent any side effects before
* user space daemon will take care of it. The best option,
* taking into consideration that there is no way to read values
* back from hardware, is to enforce watchdog being run with
* deterministic values.
*/
ret = wdt_start(wdt_dev);
if (ret)
return ret;
/* Make sure the watchdog is serviced */
set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
ret = devm_watchdog_register_device(dev, wdt_dev);
if (ret)
return ret;
dev_info(dev, "Intel MID watchdog device probed\n");
return 0;
}
static struct platform_driver mid_wdt_driver = {
.probe = mid_wdt_probe,
.driver = {
.name = "intel_mid_wdt",
},
};
module_platform_driver(mid_wdt_driver);
MODULE_AUTHOR("David Cohen <[email protected]>");
MODULE_DESCRIPTION("Watchdog Driver for Intel MID platform");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:intel_mid_wdt");
| linux-master | drivers/watchdog/intel-mid_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PIC32 watchdog driver
*
* Joshua Henderson <[email protected]>
* Copyright (c) 2016, Microchip Technology Inc.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/watchdog.h>
#include <asm/mach-pic32/pic32.h>
/* Watchdog Timer Registers */
#define WDTCON_REG 0x00
/* Watchdog Timer Control Register fields */
#define WDTCON_WIN_EN BIT(0)
#define WDTCON_RMCS_MASK 0x0003
#define WDTCON_RMCS_SHIFT 0x0006
#define WDTCON_RMPS_MASK 0x001F
#define WDTCON_RMPS_SHIFT 0x0008
#define WDTCON_ON BIT(15)
#define WDTCON_CLR_KEY 0x5743
/* Reset Control Register fields for watchdog */
#define RESETCON_TIMEOUT_IDLE BIT(2)
#define RESETCON_TIMEOUT_SLEEP BIT(3)
#define RESETCON_WDT_TIMEOUT BIT(4)
struct pic32_wdt {
void __iomem *regs;
void __iomem *rst_base;
struct clk *clk;
};
static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt)
{
return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN);
}
static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt)
{
u32 v = readl(wdt->regs + WDTCON_REG);
return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK;
}
static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt)
{
u32 v = readl(wdt->regs + WDTCON_REG);
return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK;
}
static int pic32_wdt_bootstatus(struct pic32_wdt *wdt)
{
u32 v = readl(wdt->rst_base);
writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base));
return v & RESETCON_WDT_TIMEOUT;
}
static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt *wdt, struct device *dev)
{
unsigned long rate;
u32 period, ps, terminal;
rate = clk_get_rate(wdt->clk);
dev_dbg(dev, "wdt: clk_id %d, clk_rate %lu (prescale)\n",
pic32_wdt_get_clk_id(wdt), rate);
/* default, prescaler of 32 (i.e. div-by-32) is implicit. */
rate >>= 5;
if (!rate)
return 0;
/* calculate terminal count from postscaler. */
ps = pic32_wdt_get_post_scaler(wdt);
terminal = BIT(ps);
/* find time taken (in secs) to reach terminal count */
period = terminal / rate;
dev_dbg(dev,
"wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n",
rate, terminal, period);
return period;
}
static void pic32_wdt_keepalive(struct pic32_wdt *wdt)
{
/* write key through single half-word */
writew(WDTCON_CLR_KEY, wdt->regs + WDTCON_REG + 2);
}
static int pic32_wdt_start(struct watchdog_device *wdd)
{
struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));
pic32_wdt_keepalive(wdt);
return 0;
}
static int pic32_wdt_stop(struct watchdog_device *wdd)
{
struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG));
/*
* Cannot touch registers in the CPU cycle following clearing the
* ON bit.
*/
nop();
return 0;
}
static int pic32_wdt_ping(struct watchdog_device *wdd)
{
struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
pic32_wdt_keepalive(wdt);
return 0;
}
static const struct watchdog_ops pic32_wdt_fops = {
.owner = THIS_MODULE,
.start = pic32_wdt_start,
.stop = pic32_wdt_stop,
.ping = pic32_wdt_ping,
};
static const struct watchdog_info pic32_wdt_ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
.identity = "PIC32 Watchdog",
};
static struct watchdog_device pic32_wdd = {
.info = &pic32_wdt_ident,
.ops = &pic32_wdt_fops,
};
static const struct of_device_id pic32_wdt_dt_ids[] = {
{ .compatible = "microchip,pic32mzda-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pic32_wdt_dt_ids);
static int pic32_wdt_drv_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret;
struct watchdog_device *wdd = &pic32_wdd;
struct pic32_wdt *wdt;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->regs))
return PTR_ERR(wdt->regs);
wdt->rst_base = devm_ioremap(dev, PIC32_BASE_RESET, 0x10);
if (!wdt->rst_base)
return -ENOMEM;
wdt->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(wdt->clk)) {
dev_err(dev, "clk not found\n");
return PTR_ERR(wdt->clk);
}
if (pic32_wdt_is_win_enabled(wdt)) {
dev_err(dev, "windowed-clear mode is not supported.\n");
return -ENODEV;
}
wdd->timeout = pic32_wdt_get_timeout_secs(wdt, dev);
if (!wdd->timeout) {
dev_err(dev, "failed to read watchdog register timeout\n");
return -EINVAL;
}
dev_info(dev, "timeout %d\n", wdd->timeout);
wdd->bootstatus = pic32_wdt_bootstatus(wdt) ? WDIOF_CARDRESET : 0;
watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
watchdog_set_drvdata(wdd, wdt);
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
platform_set_drvdata(pdev, wdd);
return 0;
}
static struct platform_driver pic32_wdt_driver = {
.probe = pic32_wdt_drv_probe,
.driver = {
.name = "pic32-wdt",
.of_match_table = of_match_ptr(pic32_wdt_dt_ids),
}
};
module_platform_driver(pic32_wdt_driver);
MODULE_AUTHOR("Joshua Henderson <[email protected]>");
MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/pic32-wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* System monitoring driver for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/delay.h>
#include <linux/mfd/da9055/core.h>
#include <linux/mfd/da9055/reg.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#define DA9055_DEF_TIMEOUT 4
#define DA9055_TWDMIN 256
struct da9055_wdt_data {
struct watchdog_device wdt;
struct da9055 *da9055;
};
static const struct {
u8 reg_val;
int user_time; /* In seconds */
} da9055_wdt_maps[] = {
{ 0, 0 },
{ 1, 2 },
{ 2, 4 },
{ 3, 8 },
{ 4, 16 },
{ 5, 32 },
{ 5, 33 }, /* Actual time 32.768s so included both 32s and 33s */
{ 6, 65 },
{ 6, 66 }, /* Actual time 65.536s so include both, 65s and 66s */
{ 7, 131 },
};
static int da9055_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct da9055_wdt_data *driver_data = watchdog_get_drvdata(wdt_dev);
struct da9055 *da9055 = driver_data->da9055;
int ret, i;
for (i = 0; i < ARRAY_SIZE(da9055_wdt_maps); i++)
if (da9055_wdt_maps[i].user_time == timeout)
break;
if (i == ARRAY_SIZE(da9055_wdt_maps))
ret = -EINVAL;
else
ret = da9055_reg_update(da9055, DA9055_REG_CONTROL_B,
DA9055_TWDSCALE_MASK,
da9055_wdt_maps[i].reg_val <<
DA9055_TWDSCALE_SHIFT);
if (ret < 0) {
dev_err(da9055->dev,
"Failed to update timescale bit, %d\n", ret);
return ret;
}
wdt_dev->timeout = timeout;
return 0;
}
static int da9055_wdt_ping(struct watchdog_device *wdt_dev)
{
struct da9055_wdt_data *driver_data = watchdog_get_drvdata(wdt_dev);
struct da9055 *da9055 = driver_data->da9055;
/*
* We have a minimum time for watchdog window called TWDMIN. A write
* to the watchdog before this elapsed time will cause an error.
*/
mdelay(DA9055_TWDMIN);
/* Reset the watchdog timer */
return da9055_reg_update(da9055, DA9055_REG_CONTROL_E,
DA9055_WATCHDOG_MASK, 1);
}
static int da9055_wdt_start(struct watchdog_device *wdt_dev)
{
return da9055_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
}
static int da9055_wdt_stop(struct watchdog_device *wdt_dev)
{
return da9055_wdt_set_timeout(wdt_dev, 0);
}
static const struct watchdog_info da9055_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "DA9055 Watchdog",
};
static const struct watchdog_ops da9055_wdt_ops = {
.owner = THIS_MODULE,
.start = da9055_wdt_start,
.stop = da9055_wdt_stop,
.ping = da9055_wdt_ping,
.set_timeout = da9055_wdt_set_timeout,
};
static int da9055_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct da9055 *da9055 = dev_get_drvdata(dev->parent);
struct da9055_wdt_data *driver_data;
struct watchdog_device *da9055_wdt;
int ret;
driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
if (!driver_data)
return -ENOMEM;
driver_data->da9055 = da9055;
da9055_wdt = &driver_data->wdt;
da9055_wdt->timeout = DA9055_DEF_TIMEOUT;
da9055_wdt->info = &da9055_wdt_info;
da9055_wdt->ops = &da9055_wdt_ops;
da9055_wdt->parent = dev;
watchdog_set_nowayout(da9055_wdt, nowayout);
watchdog_set_drvdata(da9055_wdt, driver_data);
ret = da9055_wdt_stop(da9055_wdt);
if (ret < 0) {
dev_err(dev, "Failed to stop watchdog, %d\n", ret);
return ret;
}
ret = devm_watchdog_register_device(dev, &driver_data->wdt);
if (ret != 0)
dev_err(da9055->dev, "watchdog_register_device() failed: %d\n",
ret);
return ret;
}
static struct platform_driver da9055_wdt_driver = {
.probe = da9055_wdt_probe,
.driver = {
.name = "da9055-watchdog",
},
};
module_platform_driver(da9055_wdt_driver);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("DA9055 watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9055-watchdog");
| linux-master | drivers/watchdog/da9055_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <[email protected]>
*
* S3C2410 Watchdog Timer Support
*
* Based on, softdog.c by Alan Cox,
* (c) Copyright 1996 Alan Cox <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#define S3C2410_WTCON 0x00
#define S3C2410_WTDAT 0x04
#define S3C2410_WTCNT 0x08
#define S3C2410_WTCLRINT 0x0c
#define S3C2410_WTCNT_MAXCNT 0xffff
#define S3C2410_WTCON_RSTEN (1 << 0)
#define S3C2410_WTCON_INTEN (1 << 2)
#define S3C2410_WTCON_ENABLE (1 << 5)
#define S3C2410_WTCON_DIV16 (0 << 3)
#define S3C2410_WTCON_DIV32 (1 << 3)
#define S3C2410_WTCON_DIV64 (2 << 3)
#define S3C2410_WTCON_DIV128 (3 << 3)
#define S3C2410_WTCON_MAXDIV 0x80
#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
#define S3C2410_WTCON_PRESCALE_MAX 0xff
#define S3C2410_WATCHDOG_ATBOOT (0)
#define S3C2410_WATCHDOG_DEFAULT_TIME (15)
#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
#define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220
#define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244
#define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620
#define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
#define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
#define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
#define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
#define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
#define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
#define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
/**
* DOC: Quirk flags for different Samsung watchdog IP-cores
*
* This driver supports multiple Samsung SoCs, each of which might have
* different set of registers and features supported. As watchdog block
* sometimes requires modifying PMU registers for proper functioning, register
* differences in both watchdog and PMU IP-cores should be accounted for. Quirk
* flags described below serve the purpose of telling the driver about mentioned
* SoC traits, and can be specified in driver data for each particular supported
* device.
*
* %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to
* clear the interrupt once the interrupt service routine is complete. It's
* write-only, writing any values to this register clears the interrupt, but
* reading is not permitted.
*
* %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling
* WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST,
* new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is
* inverted compared to the former one.
*
* %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register,
* which contains bits indicating the reason for most recent CPU reset. If
* present, driver will use this register to check if previous reboot was due to
* watchdog timer reset.
*
* %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE
* register. If 'mask_bit' bit is set, PMU will disable WDT reset when
* corresponding processor is in reset state.
*
* %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT)
* with "watchdog counter enable" bit. That bit should be set to make watchdog
* counter running.
*/
#define QUIRK_HAS_WTCLRINT_REG (1 << 0)
#define QUIRK_HAS_PMU_MASK_RESET (1 << 1)
#define QUIRK_HAS_PMU_RST_STAT (1 << 2)
#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
#define QUIRK_HAS_PMU_CNT_EN (1 << 4)
/* These quirks require that we have a PMU register map */
#define QUIRKS_HAVE_PMUREG \
(QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | \
QUIRK_HAS_PMU_AUTO_DISABLE | QUIRK_HAS_PMU_CNT_EN)
static bool nowayout = WATCHDOG_NOWAYOUT;
static int tmr_margin;
static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
static int soft_noboot;
module_param(tmr_margin, int, 0);
module_param(tmr_atboot, int, 0);
module_param(nowayout, bool, 0);
module_param(soft_noboot, int, 0);
MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
__MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
MODULE_PARM_DESC(tmr_atboot,
"Watchdog is started at boot time if set to 1, default="
__MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
/**
* struct s3c2410_wdt_variant - Per-variant config data
*
* @disable_reg: Offset in pmureg for the register that disables the watchdog
* timer reset functionality.
* @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
* timer reset functionality.
* @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning.
* @mask_bit: Bit number for the watchdog timer in the disable register and the
* mask reset register.
* @rst_stat_reg: Offset in pmureg for the register that has the reset status.
* @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
* reset.
* @cnt_en_reg: Offset in pmureg for the register that enables WDT counter.
* @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register.
* @quirks: A bitfield of quirks.
*/
struct s3c2410_wdt_variant {
int disable_reg;
int mask_reset_reg;
bool mask_reset_inv;
int mask_bit;
int rst_stat_reg;
int rst_stat_bit;
int cnt_en_reg;
int cnt_en_bit;
u32 quirks;
};
struct s3c2410_wdt {
struct device *dev;
struct clk *bus_clk; /* for register interface (PCLK) */
struct clk *src_clk; /* for WDT counter */
void __iomem *reg_base;
unsigned int count;
spinlock_t lock;
unsigned long wtcon_save;
unsigned long wtdat_save;
struct watchdog_device wdt_device;
struct notifier_block freq_transition;
const struct s3c2410_wdt_variant *drv_data;
struct regmap *pmureg;
};
static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
.quirks = 0
};
#ifdef CONFIG_OF
static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
.quirks = QUIRK_HAS_WTCLRINT_REG,
};
static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 20,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 20,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
};
static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 0,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 9,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
};
static const struct s3c2410_wdt_variant drv_data_exynos7 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 23,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 23, /* A57 WDTRESET */
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
};
static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = {
.mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN,
.mask_bit = 2,
.mask_reset_inv = true,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = EXYNOS850_CLUSTER0_WDTRESET_BIT,
.cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT,
.cnt_en_bit = 7,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = {
.mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN,
.mask_bit = 2,
.mask_reset_inv = true,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = EXYNOS850_CLUSTER1_WDTRESET_BIT,
.cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT,
.cnt_en_bit = 7,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 = {
.mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN,
.mask_bit = 2,
.mask_reset_inv = true,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
.cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT,
.cnt_en_bit = 7,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
.mask_reset_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN,
.mask_bit = 2,
.mask_reset_inv = true,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
.cnt_en_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT,
.cnt_en_bit = 7,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
};
static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "samsung,s3c2410-wdt",
.data = &drv_data_s3c2410 },
{ .compatible = "samsung,s3c6410-wdt",
.data = &drv_data_s3c6410 },
{ .compatible = "samsung,exynos5250-wdt",
.data = &drv_data_exynos5250 },
{ .compatible = "samsung,exynos5420-wdt",
.data = &drv_data_exynos5420 },
{ .compatible = "samsung,exynos7-wdt",
.data = &drv_data_exynos7 },
{ .compatible = "samsung,exynos850-wdt",
.data = &drv_data_exynos850_cl0 },
{ .compatible = "samsung,exynosautov9-wdt",
.data = &drv_data_exynosautov9_cl0 },
{},
};
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
#endif
static const struct platform_device_id s3c2410_wdt_ids[] = {
{
.name = "s3c2410-wdt",
.driver_data = (unsigned long)&drv_data_s3c2410,
},
{}
};
MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
/* functions */
static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt)
{
return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk);
}
static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt)
{
const unsigned long freq = s3c2410wdt_get_freq(wdt);
return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
/ S3C2410_WTCON_MAXDIV);
}
static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
{
const u32 mask_val = BIT(wdt->drv_data->mask_bit);
const u32 val = mask ? mask_val : 0;
int ret;
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,
mask_val, val);
if (ret < 0)
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
return ret;
}
static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
{
const u32 mask_val = BIT(wdt->drv_data->mask_bit);
const bool val_inv = wdt->drv_data->mask_reset_inv;
const u32 val = (mask ^ val_inv) ? mask_val : 0;
int ret;
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
mask_val, val);
if (ret < 0)
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
return ret;
}
static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en)
{
const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit);
const u32 val = en ? mask_val : 0;
int ret;
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg,
mask_val, val);
if (ret < 0)
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
return ret;
}
static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
{
int ret;
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
ret = s3c2410wdt_disable_wdt_reset(wdt, !en);
if (ret < 0)
return ret;
}
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) {
ret = s3c2410wdt_mask_wdt_reset(wdt, !en);
if (ret < 0)
return ret;
}
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) {
ret = s3c2410wdt_enable_counter(wdt, en);
if (ret < 0)
return ret;
}
return 0;
}
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
unsigned long flags;
spin_lock_irqsave(&wdt->lock, flags);
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
spin_unlock_irqrestore(&wdt->lock, flags);
return 0;
}
static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
{
unsigned long wtcon;
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
}
static int s3c2410wdt_stop(struct watchdog_device *wdd)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
unsigned long flags;
spin_lock_irqsave(&wdt->lock, flags);
__s3c2410wdt_stop(wdt);
spin_unlock_irqrestore(&wdt->lock, flags);
return 0;
}
static int s3c2410wdt_start(struct watchdog_device *wdd)
{
unsigned long wtcon;
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
unsigned long flags;
spin_lock_irqsave(&wdt->lock, flags);
__s3c2410wdt_stop(wdt);
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
if (soft_noboot) {
wtcon |= S3C2410_WTCON_INTEN;
wtcon &= ~S3C2410_WTCON_RSTEN;
} else {
wtcon &= ~S3C2410_WTCON_INTEN;
wtcon |= S3C2410_WTCON_RSTEN;
}
dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
wdt->count, wtcon);
writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
spin_unlock_irqrestore(&wdt->lock, flags);
return 0;
}
static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
unsigned int timeout)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
unsigned long freq = s3c2410wdt_get_freq(wdt);
unsigned int count;
unsigned int divisor = 1;
unsigned long wtcon;
if (timeout < 1)
return -EINVAL;
freq = DIV_ROUND_UP(freq, 128);
count = timeout * freq;
dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
count, timeout, freq);
/* if the count is bigger than the watchdog register,
then work out what we need to do (and if) we can
actually make this value
*/
if (count >= 0x10000) {
divisor = DIV_ROUND_UP(count, 0xffff);
if (divisor > 0x100) {
dev_err(wdt->dev, "timeout %d too big\n", timeout);
return -EINVAL;
}
}
dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
timeout, divisor, count, DIV_ROUND_UP(count, divisor));
count = DIV_ROUND_UP(count, divisor);
wdt->count = count;
/* update the pre-scaler */
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
writel(count, wdt->reg_base + S3C2410_WTDAT);
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
wdd->timeout = (count * divisor) / freq;
return 0;
}
static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
void *data)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
void __iomem *wdt_base = wdt->reg_base;
/* disable watchdog, to be safe */
writel(0, wdt_base + S3C2410_WTCON);
/* put initial values into count and data */
writel(0x80, wdt_base + S3C2410_WTCNT);
writel(0x80, wdt_base + S3C2410_WTDAT);
/* set the watchdog to go and reset... */
writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
wdt_base + S3C2410_WTCON);
/* wait for reset to assert... */
mdelay(500);
return 0;
}
#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
static const struct watchdog_info s3c2410_wdt_ident = {
.options = OPTIONS,
.firmware_version = 0,
.identity = "S3C2410 Watchdog",
};
static const struct watchdog_ops s3c2410wdt_ops = {
.owner = THIS_MODULE,
.start = s3c2410wdt_start,
.stop = s3c2410wdt_stop,
.ping = s3c2410wdt_keepalive,
.set_timeout = s3c2410wdt_set_heartbeat,
.restart = s3c2410wdt_restart,
};
static const struct watchdog_device s3c2410_wdd = {
.info = &s3c2410_wdt_ident,
.ops = &s3c2410wdt_ops,
.timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
};
/* interrupt handler code */
static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
{
struct s3c2410_wdt *wdt = platform_get_drvdata(param);
dev_info(wdt->dev, "watchdog timer expired (irq)\n");
s3c2410wdt_keepalive(&wdt->wdt_device);
if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
return IRQ_HANDLED;
}
static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
{
unsigned int rst_stat;
int ret;
if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT))
return 0;
ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
if (ret)
dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
return WDIOF_CARDRESET;
return 0;
}
static inline int
s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
{
const struct s3c2410_wdt_variant *variant;
struct device *dev = &pdev->dev;
variant = of_device_get_match_data(dev);
if (!variant) {
/* Device matched by platform_device_id */
variant = (struct s3c2410_wdt_variant *)
platform_get_device_id(pdev)->driver_data;
}
#ifdef CONFIG_OF
/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
if (variant == &drv_data_exynos850_cl0 ||
variant == &drv_data_exynosautov9_cl0) {
u32 index;
int err;
err = of_property_read_u32(dev->of_node,
"samsung,cluster-index", &index);
if (err)
return dev_err_probe(dev, -EINVAL, "failed to get cluster index\n");
switch (index) {
case 0:
break;
case 1:
variant = (variant == &drv_data_exynos850_cl0) ?
&drv_data_exynos850_cl1 :
&drv_data_exynosautov9_cl1;
break;
default:
return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
}
}
#endif
wdt->drv_data = variant;
return 0;
}
static void s3c2410wdt_wdt_disable_action(void *data)
{
s3c2410wdt_enable(data, false);
}
static int s3c2410wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct s3c2410_wdt *wdt;
unsigned int wtcon;
int wdt_irq;
int ret;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->dev = dev;
spin_lock_init(&wdt->lock);
wdt->wdt_device = s3c2410_wdd;
ret = s3c2410_get_wdt_drv_data(pdev, wdt);
if (ret)
return ret;
if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
"samsung,syscon-phandle");
if (IS_ERR(wdt->pmureg))
return dev_err_probe(dev, PTR_ERR(wdt->pmureg),
"syscon regmap lookup failed.\n");
}
wdt_irq = platform_get_irq(pdev, 0);
if (wdt_irq < 0)
return wdt_irq;
/* get the memory region for the watchdog timer */
wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->reg_base))
return PTR_ERR(wdt->reg_base);
wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog");
if (IS_ERR(wdt->bus_clk))
return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n");
/*
* "watchdog_src" clock is optional; if it's not present -- just skip it
* and use "watchdog" clock as both bus and source clock.
*/
wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src");
if (IS_ERR(wdt->src_clk))
return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n");
wdt->wdt_device.min_timeout = 1;
wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt);
watchdog_set_drvdata(&wdt->wdt_device, wdt);
/* see if we can actually set the requested timer margin, and if
* not, try the default value */
watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
wdt->wdt_device.timeout);
if (ret) {
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
S3C2410_WATCHDOG_DEFAULT_TIME);
if (ret == 0)
dev_warn(dev, "tmr_margin value out of range, default %d used\n",
S3C2410_WATCHDOG_DEFAULT_TIME);
else
return dev_err_probe(dev, ret, "failed to use default timeout\n");
}
ret = devm_request_irq(dev, wdt_irq, s3c2410wdt_irq, 0,
pdev->name, pdev);
if (ret != 0)
return dev_err_probe(dev, ret, "failed to install irq (%d)\n", ret);
watchdog_set_nowayout(&wdt->wdt_device, nowayout);
watchdog_set_restart_priority(&wdt->wdt_device, 128);
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
wdt->wdt_device.parent = dev;
/*
* If "tmr_atboot" param is non-zero, start the watchdog right now. Also
* set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
*
* If we're not enabling the watchdog, then ensure it is disabled if it
* has been left running from the bootloader or other source.
*/
if (tmr_atboot) {
dev_info(dev, "starting watchdog timer\n");
s3c2410wdt_start(&wdt->wdt_device);
set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
} else {
s3c2410wdt_stop(&wdt->wdt_device);
}
ret = devm_watchdog_register_device(dev, &wdt->wdt_device);
if (ret)
return ret;
ret = s3c2410wdt_enable(wdt, true);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(dev, s3c2410wdt_wdt_disable_action, wdt);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
/* print out a statement of readiness */
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
(wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
return 0;
}
static void s3c2410wdt_shutdown(struct platform_device *dev)
{
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
s3c2410wdt_enable(wdt, false);
s3c2410wdt_stop(&wdt->wdt_device);
}
static int s3c2410wdt_suspend(struct device *dev)
{
int ret;
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
/* Save watchdog state, and turn it off. */
wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
ret = s3c2410wdt_enable(wdt, false);
if (ret < 0)
return ret;
/* Note that WTCNT doesn't need to be saved. */
s3c2410wdt_stop(&wdt->wdt_device);
return 0;
}
static int s3c2410wdt_resume(struct device *dev)
{
int ret;
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
/* Restore watchdog state. */
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
ret = s3c2410wdt_enable(wdt, true);
if (ret < 0)
return ret;
dev_info(dev, "watchdog %sabled\n",
(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops,
s3c2410wdt_suspend, s3c2410wdt_resume);
static struct platform_driver s3c2410wdt_driver = {
.probe = s3c2410wdt_probe,
.shutdown = s3c2410wdt_shutdown,
.id_table = s3c2410_wdt_ids,
.driver = {
.name = "s3c2410-wdt",
.pm = pm_sleep_ptr(&s3c2410wdt_pm_ops),
.of_match_table = of_match_ptr(s3c2410_wdt_match),
},
};
module_platform_driver(s3c2410wdt_driver);
MODULE_AUTHOR("Ben Dooks <[email protected]>, Dimitry Andric <[email protected]>");
MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/s3c2410_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for Broadcom BCM2835
*
* "bcm2708_wdog" driver written by Luke Diamand that was obtained from
* branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used
* as a hardware reference for the Broadcom BCM2835 watchdog timer.
*
* Copyright (C) 2013 Lubomir Rintel <[email protected]>
*
*/
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/mfd/bcm2835-pm.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#define PM_RSTC 0x1c
#define PM_RSTS 0x20
#define PM_WDOG 0x24
#define PM_PASSWORD 0x5a000000
#define PM_WDOG_TIME_SET 0x000fffff
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
#define PM_RSTC_RESET 0x00000102
/*
* The Raspberry Pi firmware uses the RSTS register to know which partition
* to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10.
* Partition 63 is a special partition used by the firmware to indicate halt.
*/
#define PM_RSTS_RASPBERRYPI_HALT 0x555
#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
struct bcm2835_wdt {
void __iomem *base;
spinlock_t lock;
};
static struct bcm2835_wdt *bcm2835_power_off_wdt;
static unsigned int heartbeat;
static bool nowayout = WATCHDOG_NOWAYOUT;
static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt)
{
uint32_t cur;
cur = readl(wdt->base + PM_RSTC);
return !!(cur & PM_RSTC_WRCFG_FULL_RESET);
}
static int bcm2835_wdt_start(struct watchdog_device *wdog)
{
struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
uint32_t cur;
unsigned long flags;
spin_lock_irqsave(&wdt->lock, flags);
writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) &
PM_WDOG_TIME_SET), wdt->base + PM_WDOG);
cur = readl_relaxed(wdt->base + PM_RSTC);
writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC);
spin_unlock_irqrestore(&wdt->lock, flags);
return 0;
}
static int bcm2835_wdt_stop(struct watchdog_device *wdog)
{
struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC);
return 0;
}
static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog)
{
struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
uint32_t ret = readl_relaxed(wdt->base + PM_WDOG);
return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
}
static void __bcm2835_restart(struct bcm2835_wdt *wdt)
{
u32 val;
/* use a timeout of 10 ticks (~150us) */
writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
val = readl_relaxed(wdt->base + PM_RSTC);
val &= PM_RSTC_WRCFG_CLR;
val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
writel_relaxed(val, wdt->base + PM_RSTC);
/* No sleeping, possibly atomic. */
mdelay(1);
}
static int bcm2835_restart(struct watchdog_device *wdog,
unsigned long action, void *data)
{
struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
__bcm2835_restart(wdt);
return 0;
}
static const struct watchdog_ops bcm2835_wdt_ops = {
.owner = THIS_MODULE,
.start = bcm2835_wdt_start,
.stop = bcm2835_wdt_stop,
.get_timeleft = bcm2835_wdt_get_timeleft,
.restart = bcm2835_restart,
};
static const struct watchdog_info bcm2835_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "Broadcom BCM2835 Watchdog timer",
};
static struct watchdog_device bcm2835_wdt_wdd = {
.info = &bcm2835_wdt_info,
.ops = &bcm2835_wdt_ops,
.min_timeout = 1,
.max_timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
.timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
};
/*
* We can't really power off, but if we do the normal reset scheme, and
* indicate to bootcode.bin not to reboot, then most of the chip will be
* powered off.
*/
static void bcm2835_power_off(void)
{
struct bcm2835_wdt *wdt = bcm2835_power_off_wdt;
u32 val;
/*
* We set the watchdog hard reset bit here to distinguish this reset
* from the normal (full) reset. bootcode.bin will not reboot after a
* hard reset.
*/
val = readl_relaxed(wdt->base + PM_RSTS);
val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT;
writel_relaxed(val, wdt->base + PM_RSTS);
/* Continue with normal reset mechanism */
__bcm2835_restart(wdt);
}
static int bcm2835_wdt_probe(struct platform_device *pdev)
{
struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct bcm2835_wdt *wdt;
int err;
wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
spin_lock_init(&wdt->lock);
wdt->base = pm->base;
watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt);
watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev);
watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout);
bcm2835_wdt_wdd.parent = dev;
if (bcm2835_wdt_is_running(wdt)) {
/*
* The currently active timeout value (set by the
* bootloader) may be different from the module
* heartbeat parameter or the value in device
* tree. But we just need to set WDOG_HW_RUNNING,
* because then the framework will "immediately" ping
* the device, updating the timeout.
*/
set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status);
}
watchdog_set_restart_priority(&bcm2835_wdt_wdd, 128);
watchdog_stop_on_reboot(&bcm2835_wdt_wdd);
err = devm_watchdog_register_device(dev, &bcm2835_wdt_wdd);
if (err)
return err;
if (of_device_is_system_power_controller(pdev->dev.parent->of_node)) {
if (!pm_power_off) {
pm_power_off = bcm2835_power_off;
bcm2835_power_off_wdt = wdt;
} else {
dev_info(dev, "Poweroff handler already present!\n");
}
}
dev_info(dev, "Broadcom BCM2835 watchdog timer");
return 0;
}
static void bcm2835_wdt_remove(struct platform_device *pdev)
{
if (pm_power_off == bcm2835_power_off)
pm_power_off = NULL;
}
static struct platform_driver bcm2835_wdt_driver = {
.probe = bcm2835_wdt_probe,
.remove_new = bcm2835_wdt_remove,
.driver = {
.name = "bcm2835-wdt",
},
};
module_platform_driver(bcm2835_wdt_driver);
module_param(heartbeat, uint, 0);
MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_ALIAS("platform:bcm2835-wdt");
MODULE_AUTHOR("Lubomir Rintel <[email protected]>");
MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/bcm2835_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Zodiac Inflight Innovations
*
* Author: Martyn Welch <[email protected]>
*
* Based on twl4030_wdt.c by Timo Kokkonen <timo.t.kokkonen at nokia.com>:
*
* Copyright (C) Nokia Corporation
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/ihex.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <asm/unaligned.h>
#define ZIIRAVE_TIMEOUT_MIN 3
#define ZIIRAVE_TIMEOUT_MAX 255
#define ZIIRAVE_TIMEOUT_DEFAULT 30
#define ZIIRAVE_PING_VALUE 0x0
#define ZIIRAVE_STATE_INITIAL 0x0
#define ZIIRAVE_STATE_OFF 0x1
#define ZIIRAVE_STATE_ON 0x2
#define ZIIRAVE_FW_NAME "ziirave_wdt.fw"
static char *ziirave_reasons[] = {"power cycle", "hw watchdog", NULL, NULL,
"host request", NULL, "illegal configuration",
"illegal instruction", "illegal trap",
"unknown"};
#define ZIIRAVE_WDT_FIRM_VER_MAJOR 0x1
#define ZIIRAVE_WDT_BOOT_VER_MAJOR 0x3
#define ZIIRAVE_WDT_RESET_REASON 0x5
#define ZIIRAVE_WDT_STATE 0x6
#define ZIIRAVE_WDT_TIMEOUT 0x7
#define ZIIRAVE_WDT_TIME_LEFT 0x8
#define ZIIRAVE_WDT_PING 0x9
#define ZIIRAVE_WDT_RESET_DURATION 0xa
#define ZIIRAVE_FIRM_PKT_TOTAL_SIZE 20
#define ZIIRAVE_FIRM_PKT_DATA_SIZE 16
#define ZIIRAVE_FIRM_FLASH_MEMORY_START (2 * 0x1600)
#define ZIIRAVE_FIRM_FLASH_MEMORY_END (2 * 0x2bbf)
#define ZIIRAVE_FIRM_PAGE_SIZE 128
/* Received and ready for next Download packet. */
#define ZIIRAVE_FIRM_DOWNLOAD_ACK 1
/* Firmware commands */
#define ZIIRAVE_CMD_DOWNLOAD_START 0x10
#define ZIIRAVE_CMD_DOWNLOAD_END 0x11
#define ZIIRAVE_CMD_DOWNLOAD_SET_READ_ADDR 0x12
#define ZIIRAVE_CMD_DOWNLOAD_READ_BYTE 0x13
#define ZIIRAVE_CMD_RESET_PROCESSOR 0x0b
#define ZIIRAVE_CMD_JUMP_TO_BOOTLOADER 0x0c
#define ZIIRAVE_CMD_DOWNLOAD_PACKET 0x0e
#define ZIIRAVE_CMD_JUMP_TO_BOOTLOADER_MAGIC 1
#define ZIIRAVE_CMD_RESET_PROCESSOR_MAGIC 1
struct ziirave_wdt_rev {
unsigned char major;
unsigned char minor;
};
struct ziirave_wdt_data {
struct mutex sysfs_mutex;
struct watchdog_device wdd;
struct ziirave_wdt_rev bootloader_rev;
struct ziirave_wdt_rev firmware_rev;
int reset_reason;
};
static int wdt_timeout;
module_param(wdt_timeout, int, 0);
MODULE_PARM_DESC(wdt_timeout, "Watchdog timeout in seconds");
static int reset_duration;
module_param(reset_duration, int, 0);
MODULE_PARM_DESC(reset_duration,
"Watchdog reset pulse duration in milliseconds");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int ziirave_wdt_revision(struct i2c_client *client,
struct ziirave_wdt_rev *rev, u8 command)
{
int ret;
ret = i2c_smbus_read_byte_data(client, command);
if (ret < 0)
return ret;
rev->major = ret;
ret = i2c_smbus_read_byte_data(client, command + 1);
if (ret < 0)
return ret;
rev->minor = ret;
return 0;
}
static int ziirave_wdt_set_state(struct watchdog_device *wdd, int state)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
return i2c_smbus_write_byte_data(client, ZIIRAVE_WDT_STATE, state);
}
static int ziirave_wdt_start(struct watchdog_device *wdd)
{
return ziirave_wdt_set_state(wdd, ZIIRAVE_STATE_ON);
}
static int ziirave_wdt_stop(struct watchdog_device *wdd)
{
return ziirave_wdt_set_state(wdd, ZIIRAVE_STATE_OFF);
}
static int ziirave_wdt_ping(struct watchdog_device *wdd)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
return i2c_smbus_write_byte_data(client, ZIIRAVE_WDT_PING,
ZIIRAVE_PING_VALUE);
}
static int ziirave_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
int ret;
ret = i2c_smbus_write_byte_data(client, ZIIRAVE_WDT_TIMEOUT, timeout);
if (!ret)
wdd->timeout = timeout;
return ret;
}
static unsigned int ziirave_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
int ret;
ret = i2c_smbus_read_byte_data(client, ZIIRAVE_WDT_TIME_LEFT);
if (ret < 0)
ret = 0;
return ret;
}
static int ziirave_firm_read_ack(struct watchdog_device *wdd)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
int ret;
ret = i2c_smbus_read_byte(client);
if (ret < 0) {
dev_err(&client->dev, "Failed to read status byte\n");
return ret;
}
return ret == ZIIRAVE_FIRM_DOWNLOAD_ACK ? 0 : -EIO;
}
static int ziirave_firm_set_read_addr(struct watchdog_device *wdd, u32 addr)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
const u16 addr16 = (u16)addr / 2;
u8 address[2];
put_unaligned_le16(addr16, address);
return i2c_smbus_write_block_data(client,
ZIIRAVE_CMD_DOWNLOAD_SET_READ_ADDR,
sizeof(address), address);
}
static bool ziirave_firm_addr_readonly(u32 addr)
{
return addr < ZIIRAVE_FIRM_FLASH_MEMORY_START ||
addr > ZIIRAVE_FIRM_FLASH_MEMORY_END;
}
/*
* ziirave_firm_write_pkt() - Build and write a firmware packet
*
* A packet to send to the firmware is composed by following bytes:
* Length | Addr0 | Addr1 | Data0 .. Data15 | Checksum |
* Where,
* Length: A data byte containing the length of the data.
* Addr0: Low byte of the address.
* Addr1: High byte of the address.
* Data0 .. Data15: Array of 16 bytes of data.
* Checksum: Checksum byte to verify data integrity.
*/
static int __ziirave_firm_write_pkt(struct watchdog_device *wdd,
u32 addr, const u8 *data, u8 len)
{
const u16 addr16 = (u16)addr / 2;
struct i2c_client *client = to_i2c_client(wdd->parent);
u8 i, checksum = 0, packet[ZIIRAVE_FIRM_PKT_TOTAL_SIZE];
int ret;
/* Check max data size */
if (len > ZIIRAVE_FIRM_PKT_DATA_SIZE) {
dev_err(&client->dev, "Firmware packet too long (%d)\n",
len);
return -EMSGSIZE;
}
/*
* Ignore packets that are targeting program memory outisde of
* app partition, since they will be ignored by the
* bootloader. At the same time, we need to make sure we'll
* allow zero length packet that will be sent as the last step
* of firmware update
*/
if (len && ziirave_firm_addr_readonly(addr))
return 0;
/* Packet length */
packet[0] = len;
/* Packet address */
put_unaligned_le16(addr16, packet + 1);
memcpy(packet + 3, data, len);
memset(packet + 3 + len, 0, ZIIRAVE_FIRM_PKT_DATA_SIZE - len);
/* Packet checksum */
for (i = 0; i < len + 3; i++)
checksum += packet[i];
packet[ZIIRAVE_FIRM_PKT_TOTAL_SIZE - 1] = checksum;
ret = i2c_smbus_write_block_data(client, ZIIRAVE_CMD_DOWNLOAD_PACKET,
sizeof(packet), packet);
if (ret) {
dev_err(&client->dev,
"Failed to send DOWNLOAD_PACKET: %d\n", ret);
return ret;
}
ret = ziirave_firm_read_ack(wdd);
if (ret)
dev_err(&client->dev,
"Failed to write firmware packet at address 0x%04x: %d\n",
addr, ret);
return ret;
}
static int ziirave_firm_write_pkt(struct watchdog_device *wdd,
u32 addr, const u8 *data, u8 len)
{
const u8 max_write_len = ZIIRAVE_FIRM_PAGE_SIZE -
(addr - ALIGN_DOWN(addr, ZIIRAVE_FIRM_PAGE_SIZE));
int ret;
if (len > max_write_len) {
/*
* If data crossed page boundary we need to split this
* write in two
*/
ret = __ziirave_firm_write_pkt(wdd, addr, data, max_write_len);
if (ret)
return ret;
addr += max_write_len;
data += max_write_len;
len -= max_write_len;
}
return __ziirave_firm_write_pkt(wdd, addr, data, len);
}
static int ziirave_firm_verify(struct watchdog_device *wdd,
const struct firmware *fw)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
const struct ihex_binrec *rec;
int i, ret;
u8 data[ZIIRAVE_FIRM_PKT_DATA_SIZE];
for (rec = (void *)fw->data; rec; rec = ihex_next_binrec(rec)) {
const u16 len = be16_to_cpu(rec->len);
const u32 addr = be32_to_cpu(rec->addr);
if (ziirave_firm_addr_readonly(addr))
continue;
ret = ziirave_firm_set_read_addr(wdd, addr);
if (ret) {
dev_err(&client->dev,
"Failed to send SET_READ_ADDR command: %d\n",
ret);
return ret;
}
for (i = 0; i < len; i++) {
ret = i2c_smbus_read_byte_data(client,
ZIIRAVE_CMD_DOWNLOAD_READ_BYTE);
if (ret < 0) {
dev_err(&client->dev,
"Failed to READ DATA: %d\n", ret);
return ret;
}
data[i] = ret;
}
if (memcmp(data, rec->data, len)) {
dev_err(&client->dev,
"Firmware mismatch at address 0x%04x\n", addr);
return -EINVAL;
}
}
return 0;
}
static int ziirave_firm_upload(struct watchdog_device *wdd,
const struct firmware *fw)
{
struct i2c_client *client = to_i2c_client(wdd->parent);
const struct ihex_binrec *rec;
int ret;
ret = i2c_smbus_write_byte_data(client,
ZIIRAVE_CMD_JUMP_TO_BOOTLOADER,
ZIIRAVE_CMD_JUMP_TO_BOOTLOADER_MAGIC);
if (ret) {
dev_err(&client->dev, "Failed to jump to bootloader\n");
return ret;
}
msleep(500);
ret = i2c_smbus_write_byte(client, ZIIRAVE_CMD_DOWNLOAD_START);
if (ret) {
dev_err(&client->dev, "Failed to start download\n");
return ret;
}
ret = ziirave_firm_read_ack(wdd);
if (ret) {
dev_err(&client->dev, "No ACK for start download\n");
return ret;
}
msleep(500);
for (rec = (void *)fw->data; rec; rec = ihex_next_binrec(rec)) {
ret = ziirave_firm_write_pkt(wdd, be32_to_cpu(rec->addr),
rec->data, be16_to_cpu(rec->len));
if (ret)
return ret;
}
/*
* Finish firmware download process by sending a zero length
* payload
*/
ret = ziirave_firm_write_pkt(wdd, 0, NULL, 0);
if (ret) {
dev_err(&client->dev, "Failed to send EMPTY packet: %d\n", ret);
return ret;
}
/* This sleep seems to be required */
msleep(20);
/* Start firmware verification */
ret = ziirave_firm_verify(wdd, fw);
if (ret) {
dev_err(&client->dev,
"Failed to verify firmware: %d\n", ret);
return ret;
}
/* End download operation */
ret = i2c_smbus_write_byte(client, ZIIRAVE_CMD_DOWNLOAD_END);
if (ret) {
dev_err(&client->dev,
"Failed to end firmware download: %d\n", ret);
return ret;
}
/* Reset the processor */
ret = i2c_smbus_write_byte_data(client,
ZIIRAVE_CMD_RESET_PROCESSOR,
ZIIRAVE_CMD_RESET_PROCESSOR_MAGIC);
if (ret) {
dev_err(&client->dev,
"Failed to reset the watchdog: %d\n", ret);
return ret;
}
msleep(500);
return 0;
}
static const struct watchdog_info ziirave_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
.identity = "RAVE Switch Watchdog",
};
static const struct watchdog_ops ziirave_wdt_ops = {
.owner = THIS_MODULE,
.start = ziirave_wdt_start,
.stop = ziirave_wdt_stop,
.ping = ziirave_wdt_ping,
.set_timeout = ziirave_wdt_set_timeout,
.get_timeleft = ziirave_wdt_get_timeleft,
};
static ssize_t ziirave_wdt_sysfs_show_firm(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct i2c_client *client = to_i2c_client(dev->parent);
struct ziirave_wdt_data *w_priv = i2c_get_clientdata(client);
int ret;
ret = mutex_lock_interruptible(&w_priv->sysfs_mutex);
if (ret)
return ret;
ret = sysfs_emit(buf, "02.%02u.%02u\n",
w_priv->firmware_rev.major,
w_priv->firmware_rev.minor);
mutex_unlock(&w_priv->sysfs_mutex);
return ret;
}
static DEVICE_ATTR(firmware_version, S_IRUGO, ziirave_wdt_sysfs_show_firm,
NULL);
static ssize_t ziirave_wdt_sysfs_show_boot(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct i2c_client *client = to_i2c_client(dev->parent);
struct ziirave_wdt_data *w_priv = i2c_get_clientdata(client);
int ret;
ret = mutex_lock_interruptible(&w_priv->sysfs_mutex);
if (ret)
return ret;
ret = sysfs_emit(buf, "01.%02u.%02u\n",
w_priv->bootloader_rev.major,
w_priv->bootloader_rev.minor);
mutex_unlock(&w_priv->sysfs_mutex);
return ret;
}
static DEVICE_ATTR(bootloader_version, S_IRUGO, ziirave_wdt_sysfs_show_boot,
NULL);
static ssize_t ziirave_wdt_sysfs_show_reason(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct i2c_client *client = to_i2c_client(dev->parent);
struct ziirave_wdt_data *w_priv = i2c_get_clientdata(client);
int ret;
ret = mutex_lock_interruptible(&w_priv->sysfs_mutex);
if (ret)
return ret;
ret = sysfs_emit(buf, "%s\n", ziirave_reasons[w_priv->reset_reason]);
mutex_unlock(&w_priv->sysfs_mutex);
return ret;
}
static DEVICE_ATTR(reset_reason, S_IRUGO, ziirave_wdt_sysfs_show_reason,
NULL);
static ssize_t ziirave_wdt_sysfs_store_firm(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct i2c_client *client = to_i2c_client(dev->parent);
struct ziirave_wdt_data *w_priv = i2c_get_clientdata(client);
const struct firmware *fw;
int err;
err = request_ihex_firmware(&fw, ZIIRAVE_FW_NAME, dev);
if (err) {
dev_err(&client->dev, "Failed to request ihex firmware\n");
return err;
}
err = mutex_lock_interruptible(&w_priv->sysfs_mutex);
if (err)
goto release_firmware;
err = ziirave_firm_upload(&w_priv->wdd, fw);
if (err) {
dev_err(&client->dev, "The firmware update failed: %d\n", err);
goto unlock_mutex;
}
/* Update firmware version */
err = ziirave_wdt_revision(client, &w_priv->firmware_rev,
ZIIRAVE_WDT_FIRM_VER_MAJOR);
if (err) {
dev_err(&client->dev, "Failed to read firmware version: %d\n",
err);
goto unlock_mutex;
}
dev_info(&client->dev,
"Firmware updated to version 02.%02u.%02u\n",
w_priv->firmware_rev.major, w_priv->firmware_rev.minor);
/* Restore the watchdog timeout */
err = ziirave_wdt_set_timeout(&w_priv->wdd, w_priv->wdd.timeout);
if (err)
dev_err(&client->dev, "Failed to set timeout: %d\n", err);
unlock_mutex:
mutex_unlock(&w_priv->sysfs_mutex);
release_firmware:
release_firmware(fw);
return err ? err : count;
}
static DEVICE_ATTR(update_firmware, S_IWUSR, NULL,
ziirave_wdt_sysfs_store_firm);
static struct attribute *ziirave_wdt_attrs[] = {
&dev_attr_firmware_version.attr,
&dev_attr_bootloader_version.attr,
&dev_attr_reset_reason.attr,
&dev_attr_update_firmware.attr,
NULL
};
ATTRIBUTE_GROUPS(ziirave_wdt);
static int ziirave_wdt_init_duration(struct i2c_client *client)
{
int ret;
if (!reset_duration) {
/* See if the reset pulse duration is provided in an of_node */
if (!client->dev.of_node)
ret = -ENODEV;
else
ret = of_property_read_u32(client->dev.of_node,
"reset-duration-ms",
&reset_duration);
if (ret) {
dev_info(&client->dev,
"No reset pulse duration specified, using default\n");
return 0;
}
}
if (reset_duration < 1 || reset_duration > 255)
return -EINVAL;
dev_info(&client->dev, "Setting reset duration to %dms",
reset_duration);
return i2c_smbus_write_byte_data(client, ZIIRAVE_WDT_RESET_DURATION,
reset_duration);
}
static int ziirave_wdt_probe(struct i2c_client *client)
{
int ret;
struct ziirave_wdt_data *w_priv;
int val;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE |
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WRITE_BLOCK_DATA))
return -ENODEV;
w_priv = devm_kzalloc(&client->dev, sizeof(*w_priv), GFP_KERNEL);
if (!w_priv)
return -ENOMEM;
mutex_init(&w_priv->sysfs_mutex);
w_priv->wdd.info = &ziirave_wdt_info;
w_priv->wdd.ops = &ziirave_wdt_ops;
w_priv->wdd.min_timeout = ZIIRAVE_TIMEOUT_MIN;
w_priv->wdd.max_timeout = ZIIRAVE_TIMEOUT_MAX;
w_priv->wdd.parent = &client->dev;
w_priv->wdd.groups = ziirave_wdt_groups;
watchdog_init_timeout(&w_priv->wdd, wdt_timeout, &client->dev);
/*
* The default value set in the watchdog should be perfectly valid, so
* pass that in if we haven't provided one via the module parameter or
* of property.
*/
if (w_priv->wdd.timeout == 0) {
val = i2c_smbus_read_byte_data(client, ZIIRAVE_WDT_TIMEOUT);
if (val < 0) {
dev_err(&client->dev, "Failed to read timeout\n");
return val;
}
if (val > ZIIRAVE_TIMEOUT_MAX ||
val < ZIIRAVE_TIMEOUT_MIN)
val = ZIIRAVE_TIMEOUT_DEFAULT;
w_priv->wdd.timeout = val;
}
ret = ziirave_wdt_set_timeout(&w_priv->wdd, w_priv->wdd.timeout);
if (ret) {
dev_err(&client->dev, "Failed to set timeout\n");
return ret;
}
dev_info(&client->dev, "Timeout set to %ds\n", w_priv->wdd.timeout);
watchdog_set_nowayout(&w_priv->wdd, nowayout);
i2c_set_clientdata(client, w_priv);
/* If in unconfigured state, set to stopped */
val = i2c_smbus_read_byte_data(client, ZIIRAVE_WDT_STATE);
if (val < 0) {
dev_err(&client->dev, "Failed to read state\n");
return val;
}
if (val == ZIIRAVE_STATE_INITIAL)
ziirave_wdt_stop(&w_priv->wdd);
ret = ziirave_wdt_init_duration(client);
if (ret) {
dev_err(&client->dev, "Failed to init duration\n");
return ret;
}
ret = ziirave_wdt_revision(client, &w_priv->firmware_rev,
ZIIRAVE_WDT_FIRM_VER_MAJOR);
if (ret) {
dev_err(&client->dev, "Failed to read firmware version\n");
return ret;
}
dev_info(&client->dev,
"Firmware version: 02.%02u.%02u\n",
w_priv->firmware_rev.major, w_priv->firmware_rev.minor);
ret = ziirave_wdt_revision(client, &w_priv->bootloader_rev,
ZIIRAVE_WDT_BOOT_VER_MAJOR);
if (ret) {
dev_err(&client->dev, "Failed to read bootloader version\n");
return ret;
}
dev_info(&client->dev,
"Bootloader version: 01.%02u.%02u\n",
w_priv->bootloader_rev.major, w_priv->bootloader_rev.minor);
w_priv->reset_reason = i2c_smbus_read_byte_data(client,
ZIIRAVE_WDT_RESET_REASON);
if (w_priv->reset_reason < 0) {
dev_err(&client->dev, "Failed to read reset reason\n");
return w_priv->reset_reason;
}
if (w_priv->reset_reason >= ARRAY_SIZE(ziirave_reasons) ||
!ziirave_reasons[w_priv->reset_reason]) {
dev_err(&client->dev, "Invalid reset reason\n");
return -ENODEV;
}
ret = watchdog_register_device(&w_priv->wdd);
return ret;
}
static void ziirave_wdt_remove(struct i2c_client *client)
{
struct ziirave_wdt_data *w_priv = i2c_get_clientdata(client);
watchdog_unregister_device(&w_priv->wdd);
}
static const struct i2c_device_id ziirave_wdt_id[] = {
{ "rave-wdt", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ziirave_wdt_id);
static const struct of_device_id zrv_wdt_of_match[] = {
{ .compatible = "zii,rave-wdt", },
{ },
};
MODULE_DEVICE_TABLE(of, zrv_wdt_of_match);
static struct i2c_driver ziirave_wdt_driver = {
.driver = {
.name = "ziirave_wdt",
.of_match_table = zrv_wdt_of_match,
},
.probe = ziirave_wdt_probe,
.remove = ziirave_wdt_remove,
.id_table = ziirave_wdt_id,
};
module_i2c_driver(ziirave_wdt_driver);
MODULE_AUTHOR("Martyn Welch <[email protected]");
MODULE_DESCRIPTION("Zodiac Aerospace RAVE Switch Watchdog Processor Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/ziirave_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Watchdog driver for the MEN z069 IP-Core
*
* Copyright (C) 2018 Johannes Thumshirn <[email protected]>
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mcb.h>
#include <linux/module.h>
#include <linux/watchdog.h>
struct men_z069_drv {
struct watchdog_device wdt;
void __iomem *base;
struct resource *mem;
};
#define MEN_Z069_WTR 0x10
#define MEN_Z069_WTR_WDEN BIT(15)
#define MEN_Z069_WTR_WDET_MASK 0x7fff
#define MEN_Z069_WVR 0x14
#define MEN_Z069_TIMER_FREQ 500 /* 500 Hz */
#define MEN_Z069_WDT_COUNTER_MIN 1
#define MEN_Z069_WDT_COUNTER_MAX 0x7fff
#define MEN_Z069_DEFAULT_TIMEOUT 30
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int men_z069_wdt_start(struct watchdog_device *wdt)
{
struct men_z069_drv *drv = watchdog_get_drvdata(wdt);
u16 val;
val = readw(drv->base + MEN_Z069_WTR);
val |= MEN_Z069_WTR_WDEN;
writew(val, drv->base + MEN_Z069_WTR);
return 0;
}
static int men_z069_wdt_stop(struct watchdog_device *wdt)
{
struct men_z069_drv *drv = watchdog_get_drvdata(wdt);
u16 val;
val = readw(drv->base + MEN_Z069_WTR);
val &= ~MEN_Z069_WTR_WDEN;
writew(val, drv->base + MEN_Z069_WTR);
return 0;
}
static int men_z069_wdt_ping(struct watchdog_device *wdt)
{
struct men_z069_drv *drv = watchdog_get_drvdata(wdt);
u16 val;
/* The watchdog trigger value toggles between 0x5555 and 0xaaaa */
val = readw(drv->base + MEN_Z069_WVR);
val ^= 0xffff;
writew(val, drv->base + MEN_Z069_WVR);
return 0;
}
static int men_z069_wdt_set_timeout(struct watchdog_device *wdt,
unsigned int timeout)
{
struct men_z069_drv *drv = watchdog_get_drvdata(wdt);
u16 reg, val, ena;
wdt->timeout = timeout;
val = timeout * MEN_Z069_TIMER_FREQ;
reg = readw(drv->base + MEN_Z069_WTR);
ena = reg & MEN_Z069_WTR_WDEN;
reg = ena | val;
writew(reg, drv->base + MEN_Z069_WTR);
return 0;
}
static const struct watchdog_info men_z069_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "MEN z069 Watchdog",
};
static const struct watchdog_ops men_z069_ops = {
.owner = THIS_MODULE,
.start = men_z069_wdt_start,
.stop = men_z069_wdt_stop,
.ping = men_z069_wdt_ping,
.set_timeout = men_z069_wdt_set_timeout,
};
static int men_z069_probe(struct mcb_device *dev,
const struct mcb_device_id *id)
{
struct men_z069_drv *drv;
struct resource *mem;
drv = devm_kzalloc(&dev->dev, sizeof(struct men_z069_drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
mem = mcb_request_mem(dev, "z069-wdt");
if (IS_ERR(mem))
return PTR_ERR(mem);
drv->base = devm_ioremap(&dev->dev, mem->start, resource_size(mem));
if (drv->base == NULL)
goto release_mem;
drv->mem = mem;
drv->wdt.info = &men_z069_info;
drv->wdt.ops = &men_z069_ops;
drv->wdt.timeout = MEN_Z069_DEFAULT_TIMEOUT;
drv->wdt.min_timeout = 1;
drv->wdt.max_timeout = MEN_Z069_WDT_COUNTER_MAX / MEN_Z069_TIMER_FREQ;
watchdog_init_timeout(&drv->wdt, 0, &dev->dev);
watchdog_set_nowayout(&drv->wdt, nowayout);
watchdog_set_drvdata(&drv->wdt, drv);
drv->wdt.parent = &dev->dev;
mcb_set_drvdata(dev, drv);
return watchdog_register_device(&drv->wdt);
release_mem:
mcb_release_mem(mem);
return -ENOMEM;
}
static void men_z069_remove(struct mcb_device *dev)
{
struct men_z069_drv *drv = mcb_get_drvdata(dev);
watchdog_unregister_device(&drv->wdt);
mcb_release_mem(drv->mem);
}
static const struct mcb_device_id men_z069_ids[] = {
{ .device = 0x45 },
{ }
};
MODULE_DEVICE_TABLE(mcb, men_z069_ids);
static struct mcb_driver men_z069_driver = {
.driver = {
.name = "z069-wdt",
},
.probe = men_z069_probe,
.remove = men_z069_remove,
.id_table = men_z069_ids,
};
module_mcb_driver(men_z069_driver);
MODULE_AUTHOR("Johannes Thumshirn <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mcb:16z069");
MODULE_IMPORT_NS(MCB);
| linux-master | drivers/watchdog/menz69_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Realtek RTD129x watchdog
*
* Copyright (c) 2017 Andreas Färber
*
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define RTD119X_TCWCR 0x0
#define RTD119X_TCWTR 0x4
#define RTD119X_TCWOV 0xc
#define RTD119X_TCWCR_WDEN_DISABLED 0xa5
#define RTD119X_TCWCR_WDEN_ENABLED 0xff
#define RTD119X_TCWCR_WDEN_MASK 0xff
#define RTD119X_TCWTR_WDCLR BIT(0)
struct rtd119x_watchdog_device {
struct watchdog_device wdt_dev;
void __iomem *base;
struct clk *clk;
};
static int rtd119x_wdt_start(struct watchdog_device *wdev)
{
struct rtd119x_watchdog_device *data = watchdog_get_drvdata(wdev);
u32 val;
val = readl_relaxed(data->base + RTD119X_TCWCR);
val &= ~RTD119X_TCWCR_WDEN_MASK;
val |= RTD119X_TCWCR_WDEN_ENABLED;
writel(val, data->base + RTD119X_TCWCR);
return 0;
}
static int rtd119x_wdt_stop(struct watchdog_device *wdev)
{
struct rtd119x_watchdog_device *data = watchdog_get_drvdata(wdev);
u32 val;
val = readl_relaxed(data->base + RTD119X_TCWCR);
val &= ~RTD119X_TCWCR_WDEN_MASK;
val |= RTD119X_TCWCR_WDEN_DISABLED;
writel(val, data->base + RTD119X_TCWCR);
return 0;
}
static int rtd119x_wdt_ping(struct watchdog_device *wdev)
{
struct rtd119x_watchdog_device *data = watchdog_get_drvdata(wdev);
writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR);
return rtd119x_wdt_start(wdev);
}
static int rtd119x_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
{
struct rtd119x_watchdog_device *data = watchdog_get_drvdata(wdev);
writel(val * clk_get_rate(data->clk), data->base + RTD119X_TCWOV);
data->wdt_dev.timeout = val;
return 0;
}
static const struct watchdog_ops rtd119x_wdt_ops = {
.owner = THIS_MODULE,
.start = rtd119x_wdt_start,
.stop = rtd119x_wdt_stop,
.ping = rtd119x_wdt_ping,
.set_timeout = rtd119x_wdt_set_timeout,
};
static const struct watchdog_info rtd119x_wdt_info = {
.identity = "rtd119x-wdt",
.options = 0,
};
static const struct of_device_id rtd119x_wdt_dt_ids[] = {
{ .compatible = "realtek,rtd1295-watchdog" },
{ }
};
static int rtd119x_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rtd119x_watchdog_device *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->base))
return PTR_ERR(data->base);
data->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(data->clk))
return PTR_ERR(data->clk);
data->wdt_dev.info = &rtd119x_wdt_info;
data->wdt_dev.ops = &rtd119x_wdt_ops;
data->wdt_dev.timeout = 120;
data->wdt_dev.max_timeout = 0xffffffff / clk_get_rate(data->clk);
data->wdt_dev.min_timeout = 1;
data->wdt_dev.parent = dev;
watchdog_stop_on_reboot(&data->wdt_dev);
watchdog_set_drvdata(&data->wdt_dev, data);
platform_set_drvdata(pdev, data);
writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR);
rtd119x_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
rtd119x_wdt_stop(&data->wdt_dev);
return devm_watchdog_register_device(dev, &data->wdt_dev);
}
static struct platform_driver rtd119x_wdt_driver = {
.probe = rtd119x_wdt_probe,
.driver = {
.name = "rtd1295-watchdog",
.of_match_table = rtd119x_wdt_dt_ids,
},
};
builtin_platform_driver(rtd119x_wdt_driver);
| linux-master | drivers/watchdog/rtd119x_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* NS pc87413-wdt Watchdog Timer driver for Linux 2.6.x.x
*
* This code is based on wdt.c with original copyright.
*
* (C) Copyright 2006 Sven Anders, <[email protected]>
* and Marcus Junker, <[email protected]>
*
* Neither Sven Anders, Marcus Junker nor ANDURAS AG
* admit liability nor provide warranty for any of this software.
* This material is provided "AS-IS" and at no charge.
*
* Release 1.1
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/notifier.h>
#include <linux/fs.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/uaccess.h>
/* #define DEBUG 1 */
#define DEFAULT_TIMEOUT 1 /* 1 minute */
#define MAX_TIMEOUT 255
#define VERSION "1.1"
#define MODNAME "pc87413 WDT"
#define DPFX MODNAME " - DEBUG: "
#define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */
#define WDT_DATA_IO_PORT (WDT_INDEX_IO_PORT+1)
#define SWC_LDN 0x04
#define SIOCFG2 0x22 /* Serial IO register */
#define WDCTL 0x10 /* Watchdog-Timer-Control-Register */
#define WDTO 0x11 /* Watchdog timeout register */
#define WDCFG 0x12 /* Watchdog config register */
#define IO_DEFAULT 0x2E /* Address used on Portwell Boards */
static int io = IO_DEFAULT;
static int swc_base_addr = -1;
static int timeout = DEFAULT_TIMEOUT; /* timeout value */
static unsigned long timer_enabled; /* is the timer enabled? */
static char expect_close; /* is the close expected? */
static DEFINE_SPINLOCK(io_lock); /* to guard us from io races */
static bool nowayout = WATCHDOG_NOWAYOUT;
/* -- Low level function ----------------------------------------*/
/* Select pins for Watchdog output */
static inline void pc87413_select_wdt_out(void)
{
unsigned int cr_data = 0;
/* Step 1: Select multiple pin,pin55,as WDT output */
outb_p(SIOCFG2, WDT_INDEX_IO_PORT);
cr_data = inb(WDT_DATA_IO_PORT);
cr_data |= 0x80; /* Set Bit7 to 1*/
outb_p(SIOCFG2, WDT_INDEX_IO_PORT);
outb_p(cr_data, WDT_DATA_IO_PORT);
#ifdef DEBUG
pr_info(DPFX
"Select multiple pin,pin55,as WDT output: Bit7 to 1: %d\n",
cr_data);
#endif
}
/* Enable SWC functions */
static inline void pc87413_enable_swc(void)
{
unsigned int cr_data = 0;
/* Step 2: Enable SWC functions */
outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */
outb_p(SWC_LDN, WDT_DATA_IO_PORT);
outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */
cr_data = inb(WDT_DATA_IO_PORT);
cr_data |= 0x01; /* Set Bit0 to 1 */
outb_p(0x30, WDT_INDEX_IO_PORT);
outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */
#ifdef DEBUG
pr_info(DPFX "pc87413 - Enable SWC functions\n");
#endif
}
/* Read SWC I/O base address */
static void pc87413_get_swc_base_addr(void)
{
unsigned char addr_l, addr_h = 0;
/* Step 3: Read SWC I/O Base Address */
outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */
addr_h = inb(WDT_DATA_IO_PORT);
outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */
addr_l = inb(WDT_DATA_IO_PORT);
swc_base_addr = (addr_h << 8) + addr_l;
#ifdef DEBUG
pr_info(DPFX
"Read SWC I/O Base Address: low %d, high %d, res %d\n",
addr_l, addr_h, swc_base_addr);
#endif
}
/* Select Bank 3 of SWC */
static inline void pc87413_swc_bank3(void)
{
/* Step 4: Select Bank3 of SWC */
outb_p(inb(swc_base_addr + 0x0f) | 0x03, swc_base_addr + 0x0f);
#ifdef DEBUG
pr_info(DPFX "Select Bank3 of SWC\n");
#endif
}
/* Set watchdog timeout to x minutes */
static inline void pc87413_programm_wdto(char pc87413_time)
{
/* Step 5: Programm WDTO, Twd. */
outb_p(pc87413_time, swc_base_addr + WDTO);
#ifdef DEBUG
pr_info(DPFX "Set WDTO to %d minutes\n", pc87413_time);
#endif
}
/* Enable WDEN */
static inline void pc87413_enable_wden(void)
{
/* Step 6: Enable WDEN */
outb_p(inb(swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL);
#ifdef DEBUG
pr_info(DPFX "Enable WDEN\n");
#endif
}
/* Enable SW_WD_TREN */
static inline void pc87413_enable_sw_wd_tren(void)
{
/* Enable SW_WD_TREN */
outb_p(inb(swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG);
#ifdef DEBUG
pr_info(DPFX "Enable SW_WD_TREN\n");
#endif
}
/* Disable SW_WD_TREN */
static inline void pc87413_disable_sw_wd_tren(void)
{
/* Disable SW_WD_TREN */
outb_p(inb(swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG);
#ifdef DEBUG
pr_info(DPFX "pc87413 - Disable SW_WD_TREN\n");
#endif
}
/* Enable SW_WD_TRG */
static inline void pc87413_enable_sw_wd_trg(void)
{
/* Enable SW_WD_TRG */
outb_p(inb(swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL);
#ifdef DEBUG
pr_info(DPFX "pc87413 - Enable SW_WD_TRG\n");
#endif
}
/* Disable SW_WD_TRG */
static inline void pc87413_disable_sw_wd_trg(void)
{
/* Disable SW_WD_TRG */
outb_p(inb(swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL);
#ifdef DEBUG
pr_info(DPFX "Disable SW_WD_TRG\n");
#endif
}
/* -- Higher level functions ------------------------------------*/
/* Enable the watchdog */
static void pc87413_enable(void)
{
spin_lock(&io_lock);
pc87413_swc_bank3();
pc87413_programm_wdto(timeout);
pc87413_enable_wden();
pc87413_enable_sw_wd_tren();
pc87413_enable_sw_wd_trg();
spin_unlock(&io_lock);
}
/* Disable the watchdog */
static void pc87413_disable(void)
{
spin_lock(&io_lock);
pc87413_swc_bank3();
pc87413_disable_sw_wd_tren();
pc87413_disable_sw_wd_trg();
pc87413_programm_wdto(0);
spin_unlock(&io_lock);
}
/* Refresh the watchdog */
static void pc87413_refresh(void)
{
spin_lock(&io_lock);
pc87413_swc_bank3();
pc87413_disable_sw_wd_tren();
pc87413_disable_sw_wd_trg();
pc87413_programm_wdto(timeout);
pc87413_enable_wden();
pc87413_enable_sw_wd_tren();
pc87413_enable_sw_wd_trg();
spin_unlock(&io_lock);
}
/* -- File operations -------------------------------------------*/
/**
* pc87413_open:
* @inode: inode of device
* @file: file handle to device
*
*/
static int pc87413_open(struct inode *inode, struct file *file)
{
/* /dev/watchdog can only be opened once */
if (test_and_set_bit(0, &timer_enabled))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Reload and activate timer */
pc87413_refresh();
pr_info("Watchdog enabled. Timeout set to %d minute(s).\n", timeout);
return stream_open(inode, file);
}
/**
* pc87413_release:
* @inode: inode to board
* @file: file handle to board
*
* The watchdog has a configurable API. There is a religious dispute
* between people who want their watchdog to be able to shut down and
* those who want to be sure if the watchdog manager dies the machine
* reboots. In the former case we disable the counters, in the latter
* case you have to open it again very soon.
*/
static int pc87413_release(struct inode *inode, struct file *file)
{
/* Shut off the timer. */
if (expect_close == 42) {
pc87413_disable();
pr_info("Watchdog disabled, sleeping again...\n");
} else {
pr_crit("Unexpected close, not stopping watchdog!\n");
pc87413_refresh();
}
clear_bit(0, &timer_enabled);
expect_close = 0;
return 0;
}
/**
* pc87413_status:
*
* return, if the watchdog is enabled (timeout is set...)
*/
static int pc87413_status(void)
{
return 0; /* currently not supported */
}
/**
* pc87413_write:
* @file: file handle to the watchdog
* @data: data buffer to write
* @len: length in bytes
* @ppos: pointer to the position to write. No seeks allowed
*
* A write to a watchdog device is defined as a keepalive signal. Any
* write of data will do, as we we don't define content meaning.
*/
static ssize_t pc87413_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
/* See if we got the magic character 'V' and reload the timer */
if (len) {
if (!nowayout) {
size_t i;
/* reset expect flag */
expect_close = 0;
/* scan to see whether or not we got the
magic character */
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
/* someone wrote to us, we should reload the timer */
pc87413_refresh();
}
return len;
}
/**
* pc87413_ioctl:
* @file: file handle to the device
* @cmd: watchdog command
* @arg: argument pointer
*
* The watchdog API defines a common set of functions for all watchdogs
* according to their available features. We only actually usefully support
* querying capabilities and current status.
*/
static long pc87413_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int new_timeout;
union {
struct watchdog_info __user *ident;
int __user *i;
} uarg;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = "PC87413(HF/F) watchdog",
};
uarg.i = (int __user *)arg;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(uarg.ident, &ident,
sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
return put_user(pc87413_status(), uarg.i);
case WDIOC_GETBOOTSTATUS:
return put_user(0, uarg.i);
case WDIOC_SETOPTIONS:
{
int options, retval = -EINVAL;
if (get_user(options, uarg.i))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
pc87413_disable();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
pc87413_enable();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
pc87413_refresh();
#ifdef DEBUG
pr_info(DPFX "keepalive\n");
#endif
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_timeout, uarg.i))
return -EFAULT;
/* the API states this is given in secs */
new_timeout /= 60;
if (new_timeout < 0 || new_timeout > MAX_TIMEOUT)
return -EINVAL;
timeout = new_timeout;
pc87413_refresh();
fallthrough; /* and return the new timeout */
case WDIOC_GETTIMEOUT:
new_timeout = timeout * 60;
return put_user(new_timeout, uarg.i);
default:
return -ENOTTY;
}
}
/* -- Notifier functions -----------------------------------------*/
/**
* pc87413_notify_sys:
* @this: our notifier block
* @code: the event being reported
* @unused: unused
*
* Our notifier is called on system shutdowns. We want to turn the card
* off at reboot otherwise the machine will reboot again during memory
* test or worse yet during the following fsck. This would suck, in fact
* trust me - if it happens it does suck.
*/
static int pc87413_notify_sys(struct notifier_block *this,
unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
/* Turn the card off */
pc87413_disable();
return NOTIFY_DONE;
}
/* -- Module's structures ---------------------------------------*/
static const struct file_operations pc87413_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = pc87413_write,
.unlocked_ioctl = pc87413_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = pc87413_open,
.release = pc87413_release,
};
static struct notifier_block pc87413_notifier = {
.notifier_call = pc87413_notify_sys,
};
static struct miscdevice pc87413_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &pc87413_fops,
};
/* -- Module init functions -------------------------------------*/
/**
* pc87413_init: module's "constructor"
*
* Set up the WDT watchdog board. All we have to do is grab the
* resources we require and bitch if anyone beat us to them.
* The open() function will actually kick the board off.
*/
static int __init pc87413_init(void)
{
int ret;
pr_info("Version " VERSION " at io 0x%X\n",
WDT_INDEX_IO_PORT);
if (!request_muxed_region(io, 2, MODNAME))
return -EBUSY;
ret = register_reboot_notifier(&pc87413_notifier);
if (ret != 0)
pr_err("cannot register reboot notifier (err=%d)\n", ret);
ret = misc_register(&pc87413_miscdev);
if (ret != 0) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
goto reboot_unreg;
}
pr_info("initialized. timeout=%d min\n", timeout);
pc87413_select_wdt_out();
pc87413_enable_swc();
pc87413_get_swc_base_addr();
if (!request_region(swc_base_addr, 0x20, MODNAME)) {
pr_err("cannot request SWC region at 0x%x\n", swc_base_addr);
ret = -EBUSY;
goto misc_unreg;
}
pc87413_enable();
release_region(io, 2);
return 0;
misc_unreg:
misc_deregister(&pc87413_miscdev);
reboot_unreg:
unregister_reboot_notifier(&pc87413_notifier);
release_region(io, 2);
return ret;
}
/**
* pc87413_exit: module's "destructor"
*
* Unload the watchdog. You cannot do this with any file handles open.
* If your watchdog is set to continue ticking on close and you unload
* it, well it keeps ticking. We won't get the interrupt but the board
* will not touch PC memory so all is fine. You just have to load a new
* module in 60 seconds or reboot.
*/
static void __exit pc87413_exit(void)
{
/* Stop the timer before we leave */
if (!nowayout) {
pc87413_disable();
pr_info("Watchdog disabled\n");
}
misc_deregister(&pc87413_miscdev);
unregister_reboot_notifier(&pc87413_notifier);
release_region(swc_base_addr, 0x20);
pr_info("watchdog component driver removed\n");
}
module_init(pc87413_init);
module_exit(pc87413_exit);
MODULE_AUTHOR("Sven Anders <[email protected]>");
MODULE_AUTHOR("Marcus Junker <[email protected]>");
MODULE_DESCRIPTION("PC87413 WDT driver");
MODULE_LICENSE("GPL");
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, MODNAME " I/O port (default: "
__MODULE_STRING(IO_DEFAULT) ").");
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in minutes (default="
__MODULE_STRING(DEFAULT_TIMEOUT) ").");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
| linux-master | drivers/watchdog/pc87413_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* sp5100_tco : TCO timer driver for sp5100 chipsets
*
* (c) Copyright 2009 Google Inc., All Rights Reserved.
*
* Based on i8xx_tco.c:
* (c) Copyright 2000 kernel concepts <[email protected]>, All Rights
* Reserved.
* https://www.kernelconcepts.de
*
* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
* AMD Publication 44413 "AMD SP5100 Register Reference Guide"
* AMD Publication 45482 "AMD SB800-Series Southbridges Register
* Reference Guide"
* AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
* for AMD Family 16h Models 00h-0Fh Processors"
* AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
* AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
* for AMD Family 16h Models 30h-3Fh Processors"
* AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
* for AMD Family 17h Model 18h, Revision B1
* Processors (PUB)
* AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
* for AMD Family 17h Model 20h, Revision A1
* Processors (PUB)
*/
/*
* Includes, defines, variables, module parameters, ...
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include "sp5100_tco.h"
#define TCO_DRIVER_NAME "sp5100-tco"
/* internal variables */
enum tco_reg_layout {
sp5100, sb800, efch, efch_mmio
};
struct sp5100_tco {
struct watchdog_device wdd;
void __iomem *tcobase;
enum tco_reg_layout tco_reg_layout;
};
/* the watchdog platform device */
static struct platform_device *sp5100_tco_platform_device;
/* the associated PCI device */
static struct pci_dev *sp5100_tco_pci;
/* module parameters */
#define WATCHDOG_ACTION 0
static bool action = WATCHDOG_ACTION;
module_param(action, bool, 0);
MODULE_PARM_DESC(action, "Action taken when watchdog expires, 0 to reset, 1 to poweroff (default="
__MODULE_STRING(WATCHDOG_ACTION) ")");
#define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Some TCO specific functions
*/
static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
{
if (dev->vendor == PCI_VENDOR_ID_ATI &&
dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
dev->revision < 0x40) {
return sp5100;
} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
return efch_mmio;
} else if ((dev->vendor == PCI_VENDOR_ID_AMD || dev->vendor == PCI_VENDOR_ID_HYGON) &&
((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
dev->revision >= 0x41) ||
(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
dev->revision >= 0x49))) {
return efch;
}
return sb800;
}
static int tco_timer_start(struct watchdog_device *wdd)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
u32 val;
val = readl(SP5100_WDT_CONTROL(tco->tcobase));
val |= SP5100_WDT_START_STOP_BIT;
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
/* This must be a distinct write. */
val |= SP5100_WDT_TRIGGER_BIT;
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
return 0;
}
static int tco_timer_stop(struct watchdog_device *wdd)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
u32 val;
val = readl(SP5100_WDT_CONTROL(tco->tcobase));
val &= ~SP5100_WDT_START_STOP_BIT;
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
return 0;
}
static int tco_timer_ping(struct watchdog_device *wdd)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
u32 val;
val = readl(SP5100_WDT_CONTROL(tco->tcobase));
val |= SP5100_WDT_TRIGGER_BIT;
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
return 0;
}
static int tco_timer_set_timeout(struct watchdog_device *wdd,
unsigned int t)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
/* Write new heartbeat to watchdog */
writel(t, SP5100_WDT_COUNT(tco->tcobase));
wdd->timeout = t;
return 0;
}
static unsigned int tco_timer_get_timeleft(struct watchdog_device *wdd)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
return readl(SP5100_WDT_COUNT(tco->tcobase));
}
static u8 sp5100_tco_read_pm_reg8(u8 index)
{
outb(index, SP5100_IO_PM_INDEX_REG);
return inb(SP5100_IO_PM_DATA_REG);
}
static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
{
u8 val;
outb(index, SP5100_IO_PM_INDEX_REG);
val = inb(SP5100_IO_PM_DATA_REG);
val &= reset;
val |= set;
outb(val, SP5100_IO_PM_DATA_REG);
}
static void tco_timer_enable(struct sp5100_tco *tco)
{
u32 val;
switch (tco->tco_reg_layout) {
case sb800:
/* For SB800 or later */
/* Set the Watchdog timer resolution to 1 sec */
sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
0xff, SB800_PM_WATCHDOG_SECOND_RES);
/* Enable watchdog decode bit and watchdog timer */
sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
~SB800_PM_WATCHDOG_DISABLE,
SB800_PCI_WATCHDOG_DECODE_EN);
break;
case sp5100:
/* For SP5100 or SB7x0 */
/* Enable watchdog decode bit */
pci_read_config_dword(sp5100_tco_pci,
SP5100_PCI_WATCHDOG_MISC_REG,
&val);
val |= SP5100_PCI_WATCHDOG_DECODE_EN;
pci_write_config_dword(sp5100_tco_pci,
SP5100_PCI_WATCHDOG_MISC_REG,
val);
/* Enable Watchdog timer and set the resolution to 1 sec */
sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
~SP5100_PM_WATCHDOG_DISABLE,
SP5100_PM_WATCHDOG_SECOND_RES);
break;
case efch:
/* Set the Watchdog timer resolution to 1 sec and enable */
sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
~EFCH_PM_WATCHDOG_DISABLE,
EFCH_PM_DECODEEN_SECOND_RES);
break;
default:
break;
}
}
static u32 sp5100_tco_read_pm_reg32(u8 index)
{
u32 val = 0;
int i;
for (i = 3; i >= 0; i--)
val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
return val;
}
static u32 sp5100_tco_request_region(struct device *dev,
u32 mmio_addr,
const char *dev_name)
{
if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
dev_name)) {
dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
return 0;
}
return mmio_addr;
}
static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
u32 mmio_addr,
u32 alt_mmio_addr,
const char *dev_name)
{
struct device *dev = tco->wdd.parent;
dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);
if (!mmio_addr && !alt_mmio_addr)
return -ENODEV;
/* Check for MMIO address and alternate MMIO address conflicts */
if (mmio_addr)
mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);
if (!mmio_addr && alt_mmio_addr)
mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);
if (!mmio_addr) {
dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
return -EBUSY;
}
tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
if (!tco->tcobase) {
dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
return -ENOMEM;
}
dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
return 0;
}
static int sp5100_tco_timer_init(struct sp5100_tco *tco)
{
struct watchdog_device *wdd = &tco->wdd;
struct device *dev = wdd->parent;
u32 val;
val = readl(SP5100_WDT_CONTROL(tco->tcobase));
if (val & SP5100_WDT_DISABLED) {
dev_err(dev, "Watchdog hardware is disabled\n");
return -ENODEV;
}
/*
* Save WatchDogFired status, because WatchDogFired flag is
* cleared here.
*/
if (val & SP5100_WDT_FIRED)
wdd->bootstatus = WDIOF_CARDRESET;
/* Set watchdog action */
if (action)
val |= SP5100_WDT_ACTION_RESET;
else
val &= ~SP5100_WDT_ACTION_RESET;
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
/* Set a reasonable heartbeat before we stop the timer */
tco_timer_set_timeout(wdd, wdd->timeout);
/*
* Stop the TCO before we change anything so we don't race with
* a zeroed timer.
*/
tco_timer_stop(wdd);
return 0;
}
static u8 efch_read_pm_reg8(void __iomem *addr, u8 index)
{
return readb(addr + index);
}
static void efch_update_pm_reg8(void __iomem *addr, u8 index, u8 reset, u8 set)
{
u8 val;
val = readb(addr + index);
val &= reset;
val |= set;
writeb(val, addr + index);
}
static void tco_timer_enable_mmio(void __iomem *addr)
{
efch_update_pm_reg8(addr, EFCH_PM_DECODEEN3,
~EFCH_PM_WATCHDOG_DISABLE,
EFCH_PM_DECODEEN_SECOND_RES);
}
static int sp5100_tco_setupdevice_mmio(struct device *dev,
struct watchdog_device *wdd)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
const char *dev_name = SB800_DEVNAME;
u32 mmio_addr = 0, alt_mmio_addr = 0;
struct resource *res;
void __iomem *addr;
int ret;
u32 val;
res = request_mem_region_muxed(EFCH_PM_ACPI_MMIO_PM_ADDR,
EFCH_PM_ACPI_MMIO_PM_SIZE,
"sp5100_tco");
if (!res) {
dev_err(dev,
"Memory region 0x%08x already in use\n",
EFCH_PM_ACPI_MMIO_PM_ADDR);
return -EBUSY;
}
addr = ioremap(EFCH_PM_ACPI_MMIO_PM_ADDR, EFCH_PM_ACPI_MMIO_PM_SIZE);
if (!addr) {
dev_err(dev, "Address mapping failed\n");
ret = -ENOMEM;
goto out;
}
/*
* EFCH_PM_DECODEEN_WDT_TMREN is dual purpose. This bitfield
* enables sp5100_tco register MMIO space decoding. The bitfield
* also starts the timer operation. Enable if not already enabled.
*/
val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
efch_update_pm_reg8(addr, EFCH_PM_DECODEEN, 0xff,
EFCH_PM_DECODEEN_WDT_TMREN);
}
/* Error if the timer could not be enabled */
val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
dev_err(dev, "Failed to enable the timer\n");
ret = -EFAULT;
goto out;
}
mmio_addr = EFCH_PM_WDT_ADDR;
/* Determine alternate MMIO base address */
val = efch_read_pm_reg8(addr, EFCH_PM_ISACONTROL);
if (val & EFCH_PM_ISACONTROL_MMIOEN)
alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
EFCH_PM_ACPI_MMIO_WDT_OFFSET;
ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
if (!ret) {
tco_timer_enable_mmio(addr);
ret = sp5100_tco_timer_init(tco);
}
out:
if (addr)
iounmap(addr);
release_resource(res);
kfree(res);
return ret;
}
static int sp5100_tco_setupdevice(struct device *dev,
struct watchdog_device *wdd)
{
struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
const char *dev_name;
u32 mmio_addr = 0, val;
u32 alt_mmio_addr = 0;
int ret;
if (tco->tco_reg_layout == efch_mmio)
return sp5100_tco_setupdevice_mmio(dev, wdd);
/* Request the IO ports used by this driver */
if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
dev_err(dev, "I/O address 0x%04x already in use\n",
SP5100_IO_PM_INDEX_REG);
return -EBUSY;
}
/*
* Determine type of southbridge chipset.
*/
switch (tco->tco_reg_layout) {
case sp5100:
dev_name = SP5100_DEVNAME;
mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
0xfffffff8;
/*
* Secondly, find the watchdog timer MMIO address
* from SBResource_MMIO register.
*/
/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
pci_read_config_dword(sp5100_tco_pci,
SP5100_SB_RESOURCE_MMIO_BASE,
&val);
/* Verify MMIO is enabled and using bar0 */
if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
break;
case sb800:
dev_name = SB800_DEVNAME;
mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
0xfffffff8;
/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
/* Verify MMIO is enabled and using bar0 */
if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
break;
case efch:
dev_name = SB800_DEVNAME;
val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
if (val & EFCH_PM_DECODEEN_WDT_TMREN)
mmio_addr = EFCH_PM_WDT_ADDR;
val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
if (val & EFCH_PM_ISACONTROL_MMIOEN)
alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
EFCH_PM_ACPI_MMIO_WDT_OFFSET;
break;
default:
return -ENODEV;
}
ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
if (!ret) {
/* Setup the watchdog timer */
tco_timer_enable(tco);
ret = sp5100_tco_timer_init(tco);
}
release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
return ret;
}
static struct watchdog_info sp5100_tco_wdt_info = {
.identity = "SP5100 TCO timer",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops sp5100_tco_wdt_ops = {
.owner = THIS_MODULE,
.start = tco_timer_start,
.stop = tco_timer_stop,
.ping = tco_timer_ping,
.set_timeout = tco_timer_set_timeout,
.get_timeleft = tco_timer_get_timeleft,
};
static int sp5100_tco_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct sp5100_tco *tco;
int ret;
tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
if (!tco)
return -ENOMEM;
tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
wdd = &tco->wdd;
wdd->parent = dev;
wdd->info = &sp5100_tco_wdt_info;
wdd->ops = &sp5100_tco_wdt_ops;
wdd->timeout = WATCHDOG_HEARTBEAT;
wdd->min_timeout = 1;
wdd->max_timeout = 0xffff;
watchdog_init_timeout(wdd, heartbeat, NULL);
watchdog_set_nowayout(wdd, nowayout);
watchdog_stop_on_reboot(wdd);
watchdog_stop_on_unregister(wdd);
watchdog_set_drvdata(wdd, tco);
ret = sp5100_tco_setupdevice(dev, wdd);
if (ret)
return ret;
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
/* Show module parameters */
dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
wdd->timeout, nowayout);
return 0;
}
static struct platform_driver sp5100_tco_driver = {
.probe = sp5100_tco_probe,
.driver = {
.name = TCO_DRIVER_NAME,
},
};
/*
* Data for PCI driver interface
*
* This data only exists for exporting the supported
* PCI ids via MODULE_DEVICE_TABLE. We do not actually
* register a pci_driver, because someone else might
* want to register another driver on the same PCI id.
*/
static const struct pci_device_id sp5100_tco_pci_tbl[] = {
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
PCI_ANY_ID, },
{ PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
PCI_ANY_ID, },
{ 0, }, /* End of list */
};
MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
static int __init sp5100_tco_init(void)
{
struct pci_dev *dev = NULL;
int err;
/* Match the PCI device */
for_each_pci_dev(dev) {
if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
sp5100_tco_pci = dev;
break;
}
}
if (!sp5100_tco_pci)
return -ENODEV;
pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
err = platform_driver_register(&sp5100_tco_driver);
if (err)
return err;
sp5100_tco_platform_device =
platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
if (IS_ERR(sp5100_tco_platform_device)) {
err = PTR_ERR(sp5100_tco_platform_device);
goto unreg_platform_driver;
}
return 0;
unreg_platform_driver:
platform_driver_unregister(&sp5100_tco_driver);
return err;
}
static void __exit sp5100_tco_exit(void)
{
platform_device_unregister(sp5100_tco_platform_device);
platform_driver_unregister(&sp5100_tco_driver);
}
module_init(sp5100_tco_init);
module_exit(sp5100_tco_exit);
MODULE_AUTHOR("Priyanka Gupta");
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sp5100_tco.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Watchdog driver for Faraday Technology FTWDT010
*
* Copyright (C) 2017 Linus Walleij <[email protected]>
*
* Inspired by the out-of-tree drivers from OpenWRT:
* Copyright (C) 2009 Paulius Zaleckas <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/watchdog.h>
#define FTWDT010_WDCOUNTER 0x0
#define FTWDT010_WDLOAD 0x4
#define FTWDT010_WDRESTART 0x8
#define FTWDT010_WDCR 0xC
#define WDRESTART_MAGIC 0x5AB9
#define WDCR_CLOCK_5MHZ BIT(4)
#define WDCR_WDEXT BIT(3)
#define WDCR_WDINTR BIT(2)
#define WDCR_SYS_RST BIT(1)
#define WDCR_ENABLE BIT(0)
#define WDT_CLOCK 5000000 /* 5 MHz */
struct ftwdt010_wdt {
struct watchdog_device wdd;
struct device *dev;
void __iomem *base;
bool has_irq;
};
static inline
struct ftwdt010_wdt *to_ftwdt010_wdt(struct watchdog_device *wdd)
{
return container_of(wdd, struct ftwdt010_wdt, wdd);
}
static void ftwdt010_enable(struct ftwdt010_wdt *gwdt,
unsigned int timeout,
bool need_irq)
{
u32 enable;
writel(timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
/* set clock before enabling */
enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST;
writel(enable, gwdt->base + FTWDT010_WDCR);
if (need_irq)
enable |= WDCR_WDINTR;
enable |= WDCR_ENABLE;
writel(enable, gwdt->base + FTWDT010_WDCR);
}
static int ftwdt010_wdt_start(struct watchdog_device *wdd)
{
struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
ftwdt010_enable(gwdt, wdd->timeout, gwdt->has_irq);
return 0;
}
static int ftwdt010_wdt_stop(struct watchdog_device *wdd)
{
struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
writel(0, gwdt->base + FTWDT010_WDCR);
return 0;
}
static int ftwdt010_wdt_ping(struct watchdog_device *wdd)
{
struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
return 0;
}
static int ftwdt010_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->timeout = timeout;
if (watchdog_active(wdd))
ftwdt010_wdt_start(wdd);
return 0;
}
static int ftwdt010_wdt_restart(struct watchdog_device *wdd,
unsigned long action, void *data)
{
ftwdt010_enable(to_ftwdt010_wdt(wdd), 0, false);
return 0;
}
static irqreturn_t ftwdt010_wdt_interrupt(int irq, void *data)
{
struct ftwdt010_wdt *gwdt = data;
watchdog_notify_pretimeout(&gwdt->wdd);
return IRQ_HANDLED;
}
static const struct watchdog_ops ftwdt010_wdt_ops = {
.start = ftwdt010_wdt_start,
.stop = ftwdt010_wdt_stop,
.ping = ftwdt010_wdt_ping,
.set_timeout = ftwdt010_wdt_set_timeout,
.restart = ftwdt010_wdt_restart,
.owner = THIS_MODULE,
};
static const struct watchdog_info ftwdt010_wdt_info = {
.options = WDIOF_KEEPALIVEPING
| WDIOF_MAGICCLOSE
| WDIOF_SETTIMEOUT,
.identity = KBUILD_MODNAME,
};
static int ftwdt010_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ftwdt010_wdt *gwdt;
unsigned int reg;
int irq;
int ret;
gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
if (!gwdt)
return -ENOMEM;
gwdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gwdt->base))
return PTR_ERR(gwdt->base);
gwdt->dev = dev;
gwdt->wdd.info = &ftwdt010_wdt_info;
gwdt->wdd.ops = &ftwdt010_wdt_ops;
gwdt->wdd.min_timeout = 1;
gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK;
gwdt->wdd.parent = dev;
/*
* If 'timeout-sec' unspecified in devicetree, assume a 13 second
* default.
*/
gwdt->wdd.timeout = 13U;
watchdog_init_timeout(&gwdt->wdd, 0, dev);
reg = readw(gwdt->base + FTWDT010_WDCR);
if (reg & WDCR_ENABLE) {
/* Watchdog was enabled by the bootloader, disable it. */
reg &= ~WDCR_ENABLE;
writel(reg, gwdt->base + FTWDT010_WDCR);
}
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
"watchdog bark", gwdt);
if (ret)
return ret;
gwdt->has_irq = true;
}
ret = devm_watchdog_register_device(dev, &gwdt->wdd);
if (ret)
return ret;
/* Set up platform driver data */
platform_set_drvdata(pdev, gwdt);
dev_info(dev, "FTWDT010 watchdog driver enabled\n");
return 0;
}
static int __maybe_unused ftwdt010_wdt_suspend(struct device *dev)
{
struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
unsigned int reg;
reg = readw(gwdt->base + FTWDT010_WDCR);
reg &= ~WDCR_ENABLE;
writel(reg, gwdt->base + FTWDT010_WDCR);
return 0;
}
static int __maybe_unused ftwdt010_wdt_resume(struct device *dev)
{
struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
unsigned int reg;
if (watchdog_active(&gwdt->wdd)) {
reg = readw(gwdt->base + FTWDT010_WDCR);
reg |= WDCR_ENABLE;
writel(reg, gwdt->base + FTWDT010_WDCR);
}
return 0;
}
static const struct dev_pm_ops ftwdt010_wdt_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(ftwdt010_wdt_suspend,
ftwdt010_wdt_resume)
};
static const struct of_device_id ftwdt010_wdt_match[] = {
{ .compatible = "faraday,ftwdt010" },
{ .compatible = "cortina,gemini-watchdog" },
{},
};
MODULE_DEVICE_TABLE(of, ftwdt010_wdt_match);
static struct platform_driver ftwdt010_wdt_driver = {
.probe = ftwdt010_wdt_probe,
.driver = {
.name = "ftwdt010-wdt",
.of_match_table = ftwdt010_wdt_match,
.pm = &ftwdt010_wdt_dev_pm_ops,
},
};
module_platform_driver(ftwdt010_wdt_driver);
MODULE_AUTHOR("Linus Walleij");
MODULE_DESCRIPTION("Watchdog driver for Faraday Technology FTWDT010");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/ftwdt010_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for the wm8350
*
* Copyright (C) 2007, 2008 Wolfson Microelectronics <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/uaccess.h>
#include <linux/mfd/wm8350/core.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static DEFINE_MUTEX(wdt_mutex);
static struct {
unsigned int time; /* Seconds */
u16 val; /* To be set in WM8350_SYSTEM_CONTROL_2 */
} wm8350_wdt_cfgs[] = {
{ 1, 0x02 },
{ 2, 0x04 },
{ 4, 0x05 },
};
static int wm8350_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct wm8350 *wm8350 = watchdog_get_drvdata(wdt_dev);
int ret, i;
u16 reg;
for (i = 0; i < ARRAY_SIZE(wm8350_wdt_cfgs); i++)
if (wm8350_wdt_cfgs[i].time == timeout)
break;
if (i == ARRAY_SIZE(wm8350_wdt_cfgs))
return -EINVAL;
mutex_lock(&wdt_mutex);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= ~WM8350_WDOG_TO_MASK;
reg |= wm8350_wdt_cfgs[i].val;
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
wm8350_reg_lock(wm8350);
mutex_unlock(&wdt_mutex);
wdt_dev->timeout = timeout;
return ret;
}
static int wm8350_wdt_start(struct watchdog_device *wdt_dev)
{
struct wm8350 *wm8350 = watchdog_get_drvdata(wdt_dev);
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= ~WM8350_WDOG_MODE_MASK;
reg |= 0x20;
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
wm8350_reg_lock(wm8350);
mutex_unlock(&wdt_mutex);
return ret;
}
static int wm8350_wdt_stop(struct watchdog_device *wdt_dev)
{
struct wm8350 *wm8350 = watchdog_get_drvdata(wdt_dev);
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
wm8350_reg_unlock(wm8350);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
reg &= ~WM8350_WDOG_MODE_MASK;
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
wm8350_reg_lock(wm8350);
mutex_unlock(&wdt_mutex);
return ret;
}
static int wm8350_wdt_ping(struct watchdog_device *wdt_dev)
{
struct wm8350 *wm8350 = watchdog_get_drvdata(wdt_dev);
int ret;
u16 reg;
mutex_lock(&wdt_mutex);
reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
mutex_unlock(&wdt_mutex);
return ret;
}
static const struct watchdog_info wm8350_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "WM8350 Watchdog",
};
static const struct watchdog_ops wm8350_wdt_ops = {
.owner = THIS_MODULE,
.start = wm8350_wdt_start,
.stop = wm8350_wdt_stop,
.ping = wm8350_wdt_ping,
.set_timeout = wm8350_wdt_set_timeout,
};
static struct watchdog_device wm8350_wdt = {
.info = &wm8350_wdt_info,
.ops = &wm8350_wdt_ops,
.timeout = 4,
.min_timeout = 1,
.max_timeout = 4,
};
static int wm8350_wdt_probe(struct platform_device *pdev)
{
struct wm8350 *wm8350 = platform_get_drvdata(pdev);
if (!wm8350) {
pr_err("No driver data supplied\n");
return -ENODEV;
}
watchdog_set_nowayout(&wm8350_wdt, nowayout);
watchdog_set_drvdata(&wm8350_wdt, wm8350);
wm8350_wdt.parent = &pdev->dev;
/* Default to 4s timeout */
wm8350_wdt_set_timeout(&wm8350_wdt, 4);
return devm_watchdog_register_device(&pdev->dev, &wm8350_wdt);
}
static struct platform_driver wm8350_wdt_driver = {
.probe = wm8350_wdt_probe,
.driver = {
.name = "wm8350-wdt",
},
};
module_platform_driver(wm8350_wdt_driver);
MODULE_AUTHOR("Mark Brown");
MODULE_DESCRIPTION("WM8350 Watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm8350-wdt");
| linux-master | drivers/watchdog/wm8350_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* sunxi Watchdog Driver
*
* Copyright (c) 2013 Carlo Caione
* 2012 Henrik Nordstrom
*
* Based on xen_wdt.c
* (c) Copyright 2010 Novell, Inc.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#define WDT_MAX_TIMEOUT 16
#define WDT_MIN_TIMEOUT 1
#define WDT_TIMEOUT_MASK 0x0F
#define WDT_CTRL_RELOAD ((1 << 0) | (0x0a57 << 1))
#define WDT_MODE_EN (1 << 0)
#define DRV_NAME "sunxi-wdt"
#define DRV_VERSION "1.0"
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;
/*
* This structure stores the register offsets for different variants
* of Allwinner's watchdog hardware.
*/
struct sunxi_wdt_reg {
u8 wdt_ctrl;
u8 wdt_cfg;
u8 wdt_mode;
u8 wdt_timeout_shift;
u8 wdt_reset_mask;
u8 wdt_reset_val;
u32 wdt_key_val;
};
struct sunxi_wdt_dev {
struct watchdog_device wdt_dev;
void __iomem *wdt_base;
const struct sunxi_wdt_reg *wdt_regs;
};
/*
* wdt_timeout_map maps the watchdog timer interval value in seconds to
* the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
*
* [timeout seconds] = register value
*
*/
static const int wdt_timeout_map[] = {
[1] = 0x1, /* 1s */
[2] = 0x2, /* 2s */
[3] = 0x3, /* 3s */
[4] = 0x4, /* 4s */
[5] = 0x5, /* 5s */
[6] = 0x6, /* 6s */
[8] = 0x7, /* 8s */
[10] = 0x8, /* 10s */
[12] = 0x9, /* 12s */
[14] = 0xA, /* 14s */
[16] = 0xB, /* 16s */
};
static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
unsigned long action, void *data)
{
struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = sunxi_wdt->wdt_base;
const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
u32 val;
/* Set system reset function */
val = readl(wdt_base + regs->wdt_cfg);
val &= ~(regs->wdt_reset_mask);
val |= regs->wdt_reset_val;
val |= regs->wdt_key_val;
writel(val, wdt_base + regs->wdt_cfg);
/* Set lowest timeout and enable watchdog */
val = readl(wdt_base + regs->wdt_mode);
val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
val |= WDT_MODE_EN;
val |= regs->wdt_key_val;
writel(val, wdt_base + regs->wdt_mode);
/*
* Restart the watchdog. The default (and lowest) interval
* value for the watchdog is 0.5s.
*/
writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
while (1) {
mdelay(5);
val = readl(wdt_base + regs->wdt_mode);
val |= WDT_MODE_EN;
val |= regs->wdt_key_val;
writel(val, wdt_base + regs->wdt_mode);
}
return 0;
}
static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
{
struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = sunxi_wdt->wdt_base;
const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
return 0;
}
static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = sunxi_wdt->wdt_base;
const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
u32 reg;
if (wdt_timeout_map[timeout] == 0)
timeout++;
sunxi_wdt->wdt_dev.timeout = timeout;
reg = readl(wdt_base + regs->wdt_mode);
reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
reg |= regs->wdt_key_val;
writel(reg, wdt_base + regs->wdt_mode);
sunxi_wdt_ping(wdt_dev);
return 0;
}
static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
{
struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = sunxi_wdt->wdt_base;
const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
writel(regs->wdt_key_val, wdt_base + regs->wdt_mode);
return 0;
}
static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
{
u32 reg;
struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
void __iomem *wdt_base = sunxi_wdt->wdt_base;
const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
int ret;
ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
sunxi_wdt->wdt_dev.timeout);
if (ret < 0)
return ret;
/* Set system reset function */
reg = readl(wdt_base + regs->wdt_cfg);
reg &= ~(regs->wdt_reset_mask);
reg |= regs->wdt_reset_val;
reg |= regs->wdt_key_val;
writel(reg, wdt_base + regs->wdt_cfg);
/* Enable watchdog */
reg = readl(wdt_base + regs->wdt_mode);
reg |= WDT_MODE_EN;
reg |= regs->wdt_key_val;
writel(reg, wdt_base + regs->wdt_mode);
return 0;
}
static const struct watchdog_info sunxi_wdt_info = {
.identity = DRV_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops sunxi_wdt_ops = {
.owner = THIS_MODULE,
.start = sunxi_wdt_start,
.stop = sunxi_wdt_stop,
.ping = sunxi_wdt_ping,
.set_timeout = sunxi_wdt_set_timeout,
.restart = sunxi_wdt_restart,
};
static const struct sunxi_wdt_reg sun4i_wdt_reg = {
.wdt_ctrl = 0x00,
.wdt_cfg = 0x04,
.wdt_mode = 0x04,
.wdt_timeout_shift = 3,
.wdt_reset_mask = 0x02,
.wdt_reset_val = 0x02,
};
static const struct sunxi_wdt_reg sun6i_wdt_reg = {
.wdt_ctrl = 0x10,
.wdt_cfg = 0x14,
.wdt_mode = 0x18,
.wdt_timeout_shift = 4,
.wdt_reset_mask = 0x03,
.wdt_reset_val = 0x01,
};
static const struct sunxi_wdt_reg sun20i_wdt_reg = {
.wdt_ctrl = 0x10,
.wdt_cfg = 0x14,
.wdt_mode = 0x18,
.wdt_timeout_shift = 4,
.wdt_reset_mask = 0x03,
.wdt_reset_val = 0x01,
.wdt_key_val = 0x16aa0000,
};
static const struct of_device_id sunxi_wdt_dt_ids[] = {
{ .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
{ .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
{ .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
static int sunxi_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct sunxi_wdt_dev *sunxi_wdt;
int err;
sunxi_wdt = devm_kzalloc(dev, sizeof(*sunxi_wdt), GFP_KERNEL);
if (!sunxi_wdt)
return -ENOMEM;
sunxi_wdt->wdt_regs = of_device_get_match_data(dev);
if (!sunxi_wdt->wdt_regs)
return -ENODEV;
sunxi_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sunxi_wdt->wdt_base))
return PTR_ERR(sunxi_wdt->wdt_base);
sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
sunxi_wdt->wdt_dev.parent = dev;
watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, dev);
watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
watchdog_set_restart_priority(&sunxi_wdt->wdt_dev, 128);
watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);
sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
watchdog_stop_on_reboot(&sunxi_wdt->wdt_dev);
err = devm_watchdog_register_device(dev, &sunxi_wdt->wdt_dev);
if (unlikely(err))
return err;
dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
sunxi_wdt->wdt_dev.timeout, nowayout);
return 0;
}
static struct platform_driver sunxi_wdt_driver = {
.probe = sunxi_wdt_probe,
.driver = {
.name = DRV_NAME,
.of_match_table = sunxi_wdt_dt_ids,
},
};
module_platform_driver(sunxi_wdt_driver);
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Carlo Caione <[email protected]>");
MODULE_AUTHOR("Henrik Nordstrom <[email protected]>");
MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
| linux-master | drivers/watchdog/sunxi_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* System monitoring driver for DA9052 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: Anthony Olech <[email protected]>
*
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/uaccess.h>
#include <linux/platform_device.h>
#include <linux/time.h>
#include <linux/watchdog.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/jiffies.h>
#include <linux/mfd/da9052/reg.h>
#include <linux/mfd/da9052/da9052.h>
#define DA9052_DEF_TIMEOUT 4
#define DA9052_TWDMIN 256
struct da9052_wdt_data {
struct watchdog_device wdt;
struct da9052 *da9052;
unsigned long jpast;
};
static const struct {
u8 reg_val;
int time; /* Seconds */
} da9052_wdt_maps[] = {
{ 1, 2 },
{ 2, 4 },
{ 3, 8 },
{ 4, 16 },
{ 5, 32 },
{ 5, 33 }, /* Actual time 32.768s so included both 32s and 33s */
{ 6, 65 },
{ 6, 66 }, /* Actual time 65.536s so include both, 65s and 66s */
{ 7, 131 },
};
static int da9052_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct da9052_wdt_data *driver_data = watchdog_get_drvdata(wdt_dev);
struct da9052 *da9052 = driver_data->da9052;
int ret, i;
/*
* Disable the Watchdog timer before setting
* new time out.
*/
ret = da9052_reg_update(da9052, DA9052_CONTROL_D_REG,
DA9052_CONTROLD_TWDSCALE, 0);
if (ret < 0) {
dev_err(da9052->dev, "Failed to disable watchdog bit, %d\n",
ret);
return ret;
}
if (timeout) {
/*
* To change the timeout, da9052 needs to
* be disabled for at least 150 us.
*/
udelay(150);
/* Set the desired timeout */
for (i = 0; i < ARRAY_SIZE(da9052_wdt_maps); i++)
if (da9052_wdt_maps[i].time == timeout)
break;
if (i == ARRAY_SIZE(da9052_wdt_maps))
ret = -EINVAL;
else
ret = da9052_reg_update(da9052, DA9052_CONTROL_D_REG,
DA9052_CONTROLD_TWDSCALE,
da9052_wdt_maps[i].reg_val);
if (ret < 0) {
dev_err(da9052->dev,
"Failed to update timescale bit, %d\n", ret);
return ret;
}
wdt_dev->timeout = timeout;
driver_data->jpast = jiffies;
}
return 0;
}
static int da9052_wdt_start(struct watchdog_device *wdt_dev)
{
return da9052_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
}
static int da9052_wdt_stop(struct watchdog_device *wdt_dev)
{
return da9052_wdt_set_timeout(wdt_dev, 0);
}
static int da9052_wdt_ping(struct watchdog_device *wdt_dev)
{
struct da9052_wdt_data *driver_data = watchdog_get_drvdata(wdt_dev);
struct da9052 *da9052 = driver_data->da9052;
unsigned long msec, jnow = jiffies;
int ret;
/*
* We have a minimum time for watchdog window called TWDMIN. A write
* to the watchdog before this elapsed time should cause an error.
*/
msec = (jnow - driver_data->jpast) * 1000/HZ;
if (msec < DA9052_TWDMIN)
mdelay(msec);
/* Reset the watchdog timer */
ret = da9052_reg_update(da9052, DA9052_CONTROL_D_REG,
DA9052_CONTROLD_WATCHDOG, 1 << 7);
if (ret < 0)
return ret;
/*
* FIXME: Reset the watchdog core, in general PMIC
* is supposed to do this
*/
return da9052_reg_update(da9052, DA9052_CONTROL_D_REG,
DA9052_CONTROLD_WATCHDOG, 0 << 7);
}
static const struct watchdog_info da9052_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "DA9052 Watchdog",
};
static const struct watchdog_ops da9052_wdt_ops = {
.owner = THIS_MODULE,
.start = da9052_wdt_start,
.stop = da9052_wdt_stop,
.ping = da9052_wdt_ping,
.set_timeout = da9052_wdt_set_timeout,
};
static int da9052_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct da9052 *da9052 = dev_get_drvdata(dev->parent);
struct da9052_wdt_data *driver_data;
struct watchdog_device *da9052_wdt;
int ret;
driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
if (!driver_data)
return -ENOMEM;
driver_data->da9052 = da9052;
da9052_wdt = &driver_data->wdt;
da9052_wdt->timeout = DA9052_DEF_TIMEOUT;
da9052_wdt->info = &da9052_wdt_info;
da9052_wdt->ops = &da9052_wdt_ops;
da9052_wdt->parent = dev;
watchdog_set_drvdata(da9052_wdt, driver_data);
ret = da9052_reg_update(da9052, DA9052_CONTROL_D_REG,
DA9052_CONTROLD_TWDSCALE, 0);
if (ret < 0) {
dev_err(dev, "Failed to disable watchdog bits, %d\n", ret);
return ret;
}
return devm_watchdog_register_device(dev, &driver_data->wdt);
}
static struct platform_driver da9052_wdt_driver = {
.probe = da9052_wdt_probe,
.driver = {
.name = "da9052-watchdog",
},
};
module_platform_driver(da9052_wdt_driver);
MODULE_AUTHOR("Anthony Olech <[email protected]>");
MODULE_DESCRIPTION("DA9052 SM Device Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9052-watchdog");
| linux-master | drivers/watchdog/da9052_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 NXP.
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/watchdog.h>
#define WDOG_CS 0x0
#define WDOG_CS_FLG BIT(14)
#define WDOG_CS_CMD32EN BIT(13)
#define WDOG_CS_PRES BIT(12)
#define WDOG_CS_ULK BIT(11)
#define WDOG_CS_RCS BIT(10)
#define LPO_CLK 0x1
#define LPO_CLK_SHIFT 8
#define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT)
#define WDOG_CS_EN BIT(7)
#define WDOG_CS_UPDATE BIT(5)
#define WDOG_CS_WAIT BIT(1)
#define WDOG_CS_STOP BIT(0)
#define WDOG_CNT 0x4
#define WDOG_TOVAL 0x8
#define REFRESH_SEQ0 0xA602
#define REFRESH_SEQ1 0xB480
#define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)
#define UNLOCK_SEQ0 0xC520
#define UNLOCK_SEQ1 0xD928
#define UNLOCK ((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0)
#define DEFAULT_TIMEOUT 60
#define MAX_TIMEOUT 128
#define WDOG_CLOCK_RATE 1000
#define WDOG_ULK_WAIT_TIMEOUT 1000
#define WDOG_RCS_WAIT_TIMEOUT 10000
#define WDOG_RCS_POST_WAIT 3000
#define RETRY_MAX 5
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0000);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
struct imx_wdt_hw_feature {
bool prescaler_enable;
u32 wdog_clock_rate;
};
struct imx7ulp_wdt_device {
struct watchdog_device wdd;
void __iomem *base;
struct clk *clk;
bool post_rcs_wait;
const struct imx_wdt_hw_feature *hw;
};
static int imx7ulp_wdt_wait_ulk(void __iomem *base)
{
u32 val = readl(base + WDOG_CS);
if (!(val & WDOG_CS_ULK) &&
readl_poll_timeout_atomic(base + WDOG_CS, val,
val & WDOG_CS_ULK, 0,
WDOG_ULK_WAIT_TIMEOUT))
return -ETIMEDOUT;
return 0;
}
static int imx7ulp_wdt_wait_rcs(struct imx7ulp_wdt_device *wdt)
{
int ret = 0;
u32 val = readl(wdt->base + WDOG_CS);
u64 timeout = (val & WDOG_CS_PRES) ?
WDOG_RCS_WAIT_TIMEOUT * 256 : WDOG_RCS_WAIT_TIMEOUT;
unsigned long wait_min = (val & WDOG_CS_PRES) ?
WDOG_RCS_POST_WAIT * 256 : WDOG_RCS_POST_WAIT;
if (!(val & WDOG_CS_RCS) &&
readl_poll_timeout(wdt->base + WDOG_CS, val, val & WDOG_CS_RCS, 100,
timeout))
ret = -ETIMEDOUT;
/* Wait 2.5 clocks after RCS done */
if (wdt->post_rcs_wait)
usleep_range(wait_min, wait_min + 2000);
return ret;
}
static int _imx7ulp_wdt_enable(struct imx7ulp_wdt_device *wdt, bool enable)
{
u32 val = readl(wdt->base + WDOG_CS);
int ret;
local_irq_disable();
writel(UNLOCK, wdt->base + WDOG_CNT);
ret = imx7ulp_wdt_wait_ulk(wdt->base);
if (ret)
goto enable_out;
if (enable)
writel(val | WDOG_CS_EN, wdt->base + WDOG_CS);
else
writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
local_irq_enable();
ret = imx7ulp_wdt_wait_rcs(wdt);
return ret;
enable_out:
local_irq_enable();
return ret;
}
static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable)
{
struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
int ret;
u32 val;
u32 loop = RETRY_MAX;
do {
ret = _imx7ulp_wdt_enable(wdt, enable);
val = readl(wdt->base + WDOG_CS);
} while (--loop > 0 && ((!!(val & WDOG_CS_EN)) != enable || ret));
if (loop == 0)
return -EBUSY;
return ret;
}
static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
{
struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
writel(REFRESH, wdt->base + WDOG_CNT);
return 0;
}
static int imx7ulp_wdt_start(struct watchdog_device *wdog)
{
return imx7ulp_wdt_enable(wdog, true);
}
static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
{
return imx7ulp_wdt_enable(wdog, false);
}
static int _imx7ulp_wdt_set_timeout(struct imx7ulp_wdt_device *wdt,
unsigned int toval)
{
int ret;
local_irq_disable();
writel(UNLOCK, wdt->base + WDOG_CNT);
ret = imx7ulp_wdt_wait_ulk(wdt->base);
if (ret)
goto timeout_out;
writel(toval, wdt->base + WDOG_TOVAL);
local_irq_enable();
ret = imx7ulp_wdt_wait_rcs(wdt);
return ret;
timeout_out:
local_irq_enable();
return ret;
}
static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int timeout)
{
struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
u32 toval = wdt->hw->wdog_clock_rate * timeout;
u32 val;
int ret;
u32 loop = RETRY_MAX;
do {
ret = _imx7ulp_wdt_set_timeout(wdt, toval);
val = readl(wdt->base + WDOG_TOVAL);
} while (--loop > 0 && (val != toval || ret));
if (loop == 0)
return -EBUSY;
wdog->timeout = timeout;
return ret;
}
static int imx7ulp_wdt_restart(struct watchdog_device *wdog,
unsigned long action, void *data)
{
struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
int ret;
ret = imx7ulp_wdt_enable(wdog, true);
if (ret)
return ret;
ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1);
if (ret)
return ret;
/* wait for wdog to fire */
while (true)
;
return NOTIFY_DONE;
}
static const struct watchdog_ops imx7ulp_wdt_ops = {
.owner = THIS_MODULE,
.start = imx7ulp_wdt_start,
.stop = imx7ulp_wdt_stop,
.ping = imx7ulp_wdt_ping,
.set_timeout = imx7ulp_wdt_set_timeout,
.restart = imx7ulp_wdt_restart,
};
static const struct watchdog_info imx7ulp_wdt_info = {
.identity = "i.MX7ULP watchdog timer",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static int _imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout, unsigned int cs)
{
u32 val;
int ret;
local_irq_disable();
val = readl(wdt->base + WDOG_CS);
if (val & WDOG_CS_CMD32EN) {
writel(UNLOCK, wdt->base + WDOG_CNT);
} else {
mb();
/* unlock the wdog for reconfiguration */
writel_relaxed(UNLOCK_SEQ0, wdt->base + WDOG_CNT);
writel_relaxed(UNLOCK_SEQ1, wdt->base + WDOG_CNT);
mb();
}
ret = imx7ulp_wdt_wait_ulk(wdt->base);
if (ret)
goto init_out;
/* set an initial timeout value in TOVAL */
writel(timeout, wdt->base + WDOG_TOVAL);
writel(cs, wdt->base + WDOG_CS);
local_irq_enable();
ret = imx7ulp_wdt_wait_rcs(wdt);
return ret;
init_out:
local_irq_enable();
return ret;
}
static int imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout)
{
/* enable 32bit command sequence and reconfigure */
u32 val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE |
WDOG_CS_WAIT | WDOG_CS_STOP;
u32 cs, toval;
int ret;
u32 loop = RETRY_MAX;
if (wdt->hw->prescaler_enable)
val |= WDOG_CS_PRES;
do {
ret = _imx7ulp_wdt_init(wdt, timeout, val);
toval = readl(wdt->base + WDOG_TOVAL);
cs = readl(wdt->base + WDOG_CS);
cs &= ~(WDOG_CS_FLG | WDOG_CS_ULK | WDOG_CS_RCS);
} while (--loop > 0 && (cs != val || toval != timeout || ret));
if (loop == 0)
return -EBUSY;
return ret;
}
static int imx7ulp_wdt_probe(struct platform_device *pdev)
{
struct imx7ulp_wdt_device *imx7ulp_wdt;
struct device *dev = &pdev->dev;
struct watchdog_device *wdog;
int ret;
imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
if (!imx7ulp_wdt)
return -ENOMEM;
platform_set_drvdata(pdev, imx7ulp_wdt);
imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(imx7ulp_wdt->base))
return PTR_ERR(imx7ulp_wdt->base);
imx7ulp_wdt->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(imx7ulp_wdt->clk)) {
dev_err(dev, "Failed to get watchdog clock\n");
return PTR_ERR(imx7ulp_wdt->clk);
}
imx7ulp_wdt->post_rcs_wait = true;
if (of_device_is_compatible(dev->of_node,
"fsl,imx8ulp-wdt")) {
dev_info(dev, "imx8ulp wdt probe\n");
imx7ulp_wdt->post_rcs_wait = false;
} else {
dev_info(dev, "imx7ulp wdt probe\n");
}
wdog = &imx7ulp_wdt->wdd;
wdog->info = &imx7ulp_wdt_info;
wdog->ops = &imx7ulp_wdt_ops;
wdog->min_timeout = 1;
wdog->max_timeout = MAX_TIMEOUT;
wdog->parent = dev;
wdog->timeout = DEFAULT_TIMEOUT;
watchdog_init_timeout(wdog, 0, dev);
watchdog_stop_on_reboot(wdog);
watchdog_stop_on_unregister(wdog);
watchdog_set_drvdata(wdog, imx7ulp_wdt);
imx7ulp_wdt->hw = of_device_get_match_data(dev);
ret = imx7ulp_wdt_init(imx7ulp_wdt, wdog->timeout * imx7ulp_wdt->hw->wdog_clock_rate);
if (ret)
return ret;
return devm_watchdog_register_device(dev, wdog);
}
static int __maybe_unused imx7ulp_wdt_suspend_noirq(struct device *dev)
{
struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
if (watchdog_active(&imx7ulp_wdt->wdd))
imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
clk_disable_unprepare(imx7ulp_wdt->clk);
return 0;
}
static int __maybe_unused imx7ulp_wdt_resume_noirq(struct device *dev)
{
struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
u32 timeout = imx7ulp_wdt->wdd.timeout * imx7ulp_wdt->hw->wdog_clock_rate;
int ret;
ret = clk_prepare_enable(imx7ulp_wdt->clk);
if (ret)
return ret;
if (watchdog_active(&imx7ulp_wdt->wdd)) {
imx7ulp_wdt_init(imx7ulp_wdt, timeout);
imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
imx7ulp_wdt_ping(&imx7ulp_wdt->wdd);
}
return 0;
}
static const struct dev_pm_ops imx7ulp_wdt_pm_ops = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx7ulp_wdt_suspend_noirq,
imx7ulp_wdt_resume_noirq)
};
static const struct imx_wdt_hw_feature imx7ulp_wdt_hw = {
.prescaler_enable = false,
.wdog_clock_rate = 1000,
};
static const struct imx_wdt_hw_feature imx93_wdt_hw = {
.prescaler_enable = true,
.wdog_clock_rate = 125,
};
static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
{ .compatible = "fsl,imx8ulp-wdt", .data = &imx7ulp_wdt_hw, },
{ .compatible = "fsl,imx7ulp-wdt", .data = &imx7ulp_wdt_hw, },
{ .compatible = "fsl,imx93-wdt", .data = &imx93_wdt_hw, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
static struct platform_driver imx7ulp_wdt_driver = {
.probe = imx7ulp_wdt_probe,
.driver = {
.name = "imx7ulp-wdt",
.pm = &imx7ulp_wdt_pm_ops,
.of_match_table = imx7ulp_wdt_dt_ids,
},
};
module_platform_driver(imx7ulp_wdt_driver);
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/imx7ulp_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Watchdog driver for Technologic Systems TS-72xx based SBCs
* (TS-7200, TS-7250 and TS-7260). These boards have external
* glue logic CPLD chip, which includes programmable watchdog
* timer.
*
* Copyright (c) 2009 Mika Westerberg <[email protected]>
*
* This driver is based on ep93xx_wdt and wm831x_wdt drivers.
*
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/watchdog.h>
#include <linux/io.h>
#define TS72XX_WDT_DEFAULT_TIMEOUT 30
static int timeout;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds.");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
/* priv->control_reg */
#define TS72XX_WDT_CTRL_DISABLE 0x00
#define TS72XX_WDT_CTRL_250MS 0x01
#define TS72XX_WDT_CTRL_500MS 0x02
#define TS72XX_WDT_CTRL_1SEC 0x03
#define TS72XX_WDT_CTRL_RESERVED 0x04
#define TS72XX_WDT_CTRL_2SEC 0x05
#define TS72XX_WDT_CTRL_4SEC 0x06
#define TS72XX_WDT_CTRL_8SEC 0x07
/* priv->feed_reg */
#define TS72XX_WDT_FEED_VAL 0x05
struct ts72xx_wdt_priv {
void __iomem *control_reg;
void __iomem *feed_reg;
struct watchdog_device wdd;
unsigned char regval;
};
static int ts72xx_wdt_start(struct watchdog_device *wdd)
{
struct ts72xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
writeb(TS72XX_WDT_FEED_VAL, priv->feed_reg);
writeb(priv->regval, priv->control_reg);
return 0;
}
static int ts72xx_wdt_stop(struct watchdog_device *wdd)
{
struct ts72xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
writeb(TS72XX_WDT_FEED_VAL, priv->feed_reg);
writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg);
return 0;
}
static int ts72xx_wdt_ping(struct watchdog_device *wdd)
{
struct ts72xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
writeb(TS72XX_WDT_FEED_VAL, priv->feed_reg);
return 0;
}
static int ts72xx_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
{
struct ts72xx_wdt_priv *priv = watchdog_get_drvdata(wdd);
if (to == 1) {
priv->regval = TS72XX_WDT_CTRL_1SEC;
} else if (to == 2) {
priv->regval = TS72XX_WDT_CTRL_2SEC;
} else if (to <= 4) {
priv->regval = TS72XX_WDT_CTRL_4SEC;
to = 4;
} else {
priv->regval = TS72XX_WDT_CTRL_8SEC;
if (to <= 8)
to = 8;
}
wdd->timeout = to;
if (watchdog_active(wdd)) {
ts72xx_wdt_stop(wdd);
ts72xx_wdt_start(wdd);
}
return 0;
}
static const struct watchdog_info ts72xx_wdt_ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = "TS-72XX WDT",
};
static const struct watchdog_ops ts72xx_wdt_ops = {
.owner = THIS_MODULE,
.start = ts72xx_wdt_start,
.stop = ts72xx_wdt_stop,
.ping = ts72xx_wdt_ping,
.set_timeout = ts72xx_wdt_settimeout,
};
static int ts72xx_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ts72xx_wdt_priv *priv;
struct watchdog_device *wdd;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->control_reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->control_reg))
return PTR_ERR(priv->control_reg);
priv->feed_reg = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(priv->feed_reg))
return PTR_ERR(priv->feed_reg);
wdd = &priv->wdd;
wdd->info = &ts72xx_wdt_ident;
wdd->ops = &ts72xx_wdt_ops;
wdd->min_timeout = 1;
wdd->max_hw_heartbeat_ms = 8000;
wdd->parent = dev;
watchdog_set_nowayout(wdd, nowayout);
wdd->timeout = TS72XX_WDT_DEFAULT_TIMEOUT;
watchdog_init_timeout(wdd, timeout, dev);
watchdog_set_drvdata(wdd, priv);
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
dev_info(dev, "TS-72xx Watchdog driver\n");
return 0;
}
static struct platform_driver ts72xx_wdt_driver = {
.probe = ts72xx_wdt_probe,
.driver = {
.name = "ts72xx-wdt",
},
};
module_platform_driver(ts72xx_wdt_driver);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("TS-72xx SBC Watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ts72xx-wdt");
| linux-master | drivers/watchdog/ts72xx_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
/* minimum and maximum watchdog trigger timeout, in seconds */
#define MIN_WDT_TIMEOUT 1
#define MAX_WDT_TIMEOUT 255
/*
* Base of the WDT registers, from the timer base address. There are
* actually 5 watchdogs that can be configured (by pairing with an available
* timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.
* This driver only configures the first watchdog (WDT ID 0).
*/
#define WDT_BASE 0x100
#define WDT_ID 0
/*
* Register base of the timer that's selected for pairing with the watchdog.
* This driver arbitrarily uses timer 5, which is currently unused by
* other drivers (in particular, the Tegra clocksource driver). If this
* needs to change, take care that the new timer is not used by the
* clocksource driver.
*/
#define WDT_TIMER_BASE 0x60
#define WDT_TIMER_ID 5
/* WDT registers */
#define WDT_CFG 0x0
#define WDT_CFG_PERIOD_SHIFT 4
#define WDT_CFG_PERIOD_MASK 0xff
#define WDT_CFG_INT_EN (1 << 12)
#define WDT_CFG_PMC2CAR_RST_EN (1 << 15)
#define WDT_STS 0x4
#define WDT_STS_COUNT_SHIFT 4
#define WDT_STS_COUNT_MASK 0xff
#define WDT_STS_EXP_SHIFT 12
#define WDT_STS_EXP_MASK 0x3
#define WDT_CMD 0x8
#define WDT_CMD_START_COUNTER (1 << 0)
#define WDT_CMD_DISABLE_COUNTER (1 << 1)
#define WDT_UNLOCK (0xc)
#define WDT_UNLOCK_PATTERN (0xc45a << 0)
/* Timer registers */
#define TIMER_PTV 0x0
#define TIMER_EN (1 << 31)
#define TIMER_PERIODIC (1 << 30)
struct tegra_wdt {
struct watchdog_device wdd;
void __iomem *wdt_regs;
void __iomem *tmr_regs;
};
#define WDT_HEARTBEAT 120
static int heartbeat = WDT_HEARTBEAT;
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeats in seconds. (default = "
__MODULE_STRING(WDT_HEARTBEAT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int tegra_wdt_start(struct watchdog_device *wdd)
{
struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
u32 val;
/*
* This thing has a fixed 1MHz clock. Normally, we would set the
* period to 1 second by writing 1000000ul, but the watchdog system
* reset actually occurs on the 4th expiration of this counter,
* so we set the period to 1/4 of this amount.
*/
val = 1000000ul / 4;
val |= (TIMER_EN | TIMER_PERIODIC);
writel(val, wdt->tmr_regs + TIMER_PTV);
/*
* Set number of periods and start counter.
*
* Interrupt handler is not required for user space
* WDT accesses, since the caller is responsible to ping the
* WDT to reset the counter before expiration, through ioctls.
*/
val = WDT_TIMER_ID |
(wdd->timeout << WDT_CFG_PERIOD_SHIFT) |
WDT_CFG_PMC2CAR_RST_EN;
writel(val, wdt->wdt_regs + WDT_CFG);
writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
return 0;
}
static int tegra_wdt_stop(struct watchdog_device *wdd)
{
struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
writel(0, wdt->tmr_regs + TIMER_PTV);
return 0;
}
static int tegra_wdt_ping(struct watchdog_device *wdd)
{
struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
return 0;
}
static int tegra_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->timeout = timeout;
if (watchdog_active(wdd)) {
tegra_wdt_stop(wdd);
return tegra_wdt_start(wdd);
}
return 0;
}
static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
u32 val;
int count;
int exp;
val = readl(wdt->wdt_regs + WDT_STS);
/* Current countdown (from timeout) */
count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK;
/* Number of expirations (we are waiting for the 4th expiration) */
exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK;
/*
* The entire thing is divided by 4 because we are ticking down 4 times
* faster due to needing to wait for the 4th expiration.
*/
return (((3 - exp) * wdd->timeout) + count) / 4;
}
static const struct watchdog_info tegra_wdt_info = {
.options = WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.firmware_version = 0,
.identity = "Tegra Watchdog",
};
static const struct watchdog_ops tegra_wdt_ops = {
.owner = THIS_MODULE,
.start = tegra_wdt_start,
.stop = tegra_wdt_stop,
.ping = tegra_wdt_ping,
.set_timeout = tegra_wdt_set_timeout,
.get_timeleft = tegra_wdt_get_timeleft,
};
static int tegra_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct tegra_wdt *wdt;
void __iomem *regs;
int ret;
/* This is the timer base. */
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
/*
* Allocate our watchdog driver data, which has the
* struct watchdog_device nested within it.
*/
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
/* Initialize struct tegra_wdt. */
wdt->wdt_regs = regs + WDT_BASE;
wdt->tmr_regs = regs + WDT_TIMER_BASE;
/* Initialize struct watchdog_device. */
wdd = &wdt->wdd;
wdd->timeout = heartbeat;
wdd->info = &tegra_wdt_info;
wdd->ops = &tegra_wdt_ops;
wdd->min_timeout = MIN_WDT_TIMEOUT;
wdd->max_timeout = MAX_WDT_TIMEOUT;
wdd->parent = dev;
watchdog_set_drvdata(wdd, wdt);
watchdog_set_nowayout(wdd, nowayout);
watchdog_stop_on_unregister(wdd);
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
dev_info(dev, "initialized (heartbeat = %d sec, nowayout = %d)\n",
heartbeat, nowayout);
return 0;
}
static int tegra_wdt_suspend(struct device *dev)
{
struct tegra_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
tegra_wdt_stop(&wdt->wdd);
return 0;
}
static int tegra_wdt_resume(struct device *dev)
{
struct tegra_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
tegra_wdt_start(&wdt->wdd);
return 0;
}
static const struct of_device_id tegra_wdt_of_match[] = {
{ .compatible = "nvidia,tegra30-timer", },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_wdt_of_match);
static DEFINE_SIMPLE_DEV_PM_OPS(tegra_wdt_pm_ops,
tegra_wdt_suspend, tegra_wdt_resume);
static struct platform_driver tegra_wdt_driver = {
.probe = tegra_wdt_probe,
.driver = {
.name = "tegra-wdt",
.pm = pm_sleep_ptr(&tegra_wdt_pm_ops),
.of_match_table = tegra_wdt_of_match,
},
};
module_platform_driver(tegra_wdt_driver);
MODULE_AUTHOR("NVIDIA Corporation");
MODULE_DESCRIPTION("Tegra Watchdog Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/tegra_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RDC321x watchdog driver
*
* Copyright (C) 2007-2010 Florian Fainelli <[email protected]>
*
* This driver is highly inspired from the cpu5_wdt driver
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/timer.h>
#include <linux/completion.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/mfd/rdc321x.h>
#define RDC_WDT_MASK 0x80000000 /* Mask */
#define RDC_WDT_EN 0x00800000 /* Enable bit */
#define RDC_WDT_WTI 0x00200000 /* Generate CPU reset/NMI/WDT on timeout */
#define RDC_WDT_RST 0x00100000 /* Reset bit */
#define RDC_WDT_WIF 0x00040000 /* WDT IRQ Flag */
#define RDC_WDT_IRT 0x00000100 /* IRQ Routing table */
#define RDC_WDT_CNT 0x00000001 /* WDT count */
#define RDC_CLS_TMR 0x80003844 /* Clear timer */
#define RDC_WDT_INTERVAL (HZ/10+1)
static int ticks = 1000;
/* some device data */
static struct {
struct completion stop;
int running;
struct timer_list timer;
int queue;
int default_ticks;
unsigned long inuse;
spinlock_t lock;
struct pci_dev *sb_pdev;
int base_reg;
} rdc321x_wdt_device;
/* generic helper functions */
static void rdc321x_wdt_trigger(struct timer_list *unused)
{
unsigned long flags;
u32 val;
if (rdc321x_wdt_device.running)
ticks--;
/* keep watchdog alive */
spin_lock_irqsave(&rdc321x_wdt_device.lock, flags);
pci_read_config_dword(rdc321x_wdt_device.sb_pdev,
rdc321x_wdt_device.base_reg, &val);
val |= RDC_WDT_EN;
pci_write_config_dword(rdc321x_wdt_device.sb_pdev,
rdc321x_wdt_device.base_reg, val);
spin_unlock_irqrestore(&rdc321x_wdt_device.lock, flags);
/* requeue?? */
if (rdc321x_wdt_device.queue && ticks)
mod_timer(&rdc321x_wdt_device.timer,
jiffies + RDC_WDT_INTERVAL);
else {
/* ticks doesn't matter anyway */
complete(&rdc321x_wdt_device.stop);
}
}
static void rdc321x_wdt_reset(void)
{
ticks = rdc321x_wdt_device.default_ticks;
}
static void rdc321x_wdt_start(void)
{
unsigned long flags;
if (!rdc321x_wdt_device.queue) {
rdc321x_wdt_device.queue = 1;
/* Clear the timer */
spin_lock_irqsave(&rdc321x_wdt_device.lock, flags);
pci_write_config_dword(rdc321x_wdt_device.sb_pdev,
rdc321x_wdt_device.base_reg, RDC_CLS_TMR);
/* Enable watchdog and set the timeout to 81.92 us */
pci_write_config_dword(rdc321x_wdt_device.sb_pdev,
rdc321x_wdt_device.base_reg,
RDC_WDT_EN | RDC_WDT_CNT);
spin_unlock_irqrestore(&rdc321x_wdt_device.lock, flags);
mod_timer(&rdc321x_wdt_device.timer,
jiffies + RDC_WDT_INTERVAL);
}
/* if process dies, counter is not decremented */
rdc321x_wdt_device.running++;
}
static int rdc321x_wdt_stop(void)
{
if (rdc321x_wdt_device.running)
rdc321x_wdt_device.running = 0;
ticks = rdc321x_wdt_device.default_ticks;
return -EIO;
}
/* filesystem operations */
static int rdc321x_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &rdc321x_wdt_device.inuse))
return -EBUSY;
return stream_open(inode, file);
}
static int rdc321x_wdt_release(struct inode *inode, struct file *file)
{
clear_bit(0, &rdc321x_wdt_device.inuse);
return 0;
}
static long rdc321x_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
void __user *argp = (void __user *)arg;
u32 value;
static const struct watchdog_info ident = {
.options = WDIOF_CARDRESET,
.identity = "RDC321x WDT",
};
unsigned long flags;
switch (cmd) {
case WDIOC_KEEPALIVE:
rdc321x_wdt_reset();
break;
case WDIOC_GETSTATUS:
/* Read the value from the DATA register */
spin_lock_irqsave(&rdc321x_wdt_device.lock, flags);
pci_read_config_dword(rdc321x_wdt_device.sb_pdev,
rdc321x_wdt_device.base_reg, &value);
spin_unlock_irqrestore(&rdc321x_wdt_device.lock, flags);
if (copy_to_user(argp, &value, sizeof(u32)))
return -EFAULT;
break;
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident)))
return -EFAULT;
break;
case WDIOC_SETOPTIONS:
if (copy_from_user(&value, argp, sizeof(int)))
return -EFAULT;
switch (value) {
case WDIOS_ENABLECARD:
rdc321x_wdt_start();
break;
case WDIOS_DISABLECARD:
return rdc321x_wdt_stop();
default:
return -EINVAL;
}
break;
default:
return -ENOTTY;
}
return 0;
}
static ssize_t rdc321x_wdt_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (!count)
return -EIO;
rdc321x_wdt_reset();
return count;
}
static const struct file_operations rdc321x_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.unlocked_ioctl = rdc321x_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = rdc321x_wdt_open,
.write = rdc321x_wdt_write,
.release = rdc321x_wdt_release,
};
static struct miscdevice rdc321x_wdt_misc = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &rdc321x_wdt_fops,
};
static int rdc321x_wdt_probe(struct platform_device *pdev)
{
int err;
struct resource *r;
struct rdc321x_wdt_pdata *pdata;
pdata = dev_get_platdata(&pdev->dev);
if (!pdata) {
dev_err(&pdev->dev, "no platform data supplied\n");
return -ENODEV;
}
r = platform_get_resource_byname(pdev, IORESOURCE_IO, "wdt-reg");
if (!r) {
dev_err(&pdev->dev, "failed to get wdt-reg resource\n");
return -ENODEV;
}
rdc321x_wdt_device.sb_pdev = pdata->sb_pdev;
rdc321x_wdt_device.base_reg = r->start;
rdc321x_wdt_device.queue = 0;
rdc321x_wdt_device.default_ticks = ticks;
err = misc_register(&rdc321x_wdt_misc);
if (err < 0) {
dev_err(&pdev->dev, "misc_register failed\n");
return err;
}
spin_lock_init(&rdc321x_wdt_device.lock);
/* Reset the watchdog */
pci_write_config_dword(rdc321x_wdt_device.sb_pdev,
rdc321x_wdt_device.base_reg, RDC_WDT_RST);
init_completion(&rdc321x_wdt_device.stop);
clear_bit(0, &rdc321x_wdt_device.inuse);
timer_setup(&rdc321x_wdt_device.timer, rdc321x_wdt_trigger, 0);
dev_info(&pdev->dev, "watchdog init success\n");
return 0;
}
static void rdc321x_wdt_remove(struct platform_device *pdev)
{
if (rdc321x_wdt_device.queue) {
rdc321x_wdt_device.queue = 0;
wait_for_completion(&rdc321x_wdt_device.stop);
}
misc_deregister(&rdc321x_wdt_misc);
}
static struct platform_driver rdc321x_wdt_driver = {
.probe = rdc321x_wdt_probe,
.remove_new = rdc321x_wdt_remove,
.driver = {
.name = "rdc321x-wdt",
},
};
module_platform_driver(rdc321x_wdt_driver);
MODULE_AUTHOR("Florian Fainelli <[email protected]>");
MODULE_DESCRIPTION("RDC321x watchdog driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/rdc321x_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) Nokia Corporation
*
* Written by Timo Kokkonen <timo.t.kokkonen at nokia.com>
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/mfd/twl.h>
#define TWL4030_WATCHDOG_CFG_REG_OFFS 0x3
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int twl4030_wdt_write(unsigned char val)
{
return twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, val,
TWL4030_WATCHDOG_CFG_REG_OFFS);
}
static int twl4030_wdt_start(struct watchdog_device *wdt)
{
return twl4030_wdt_write(wdt->timeout + 1);
}
static int twl4030_wdt_stop(struct watchdog_device *wdt)
{
return twl4030_wdt_write(0);
}
static int twl4030_wdt_set_timeout(struct watchdog_device *wdt,
unsigned int timeout)
{
wdt->timeout = timeout;
return 0;
}
static const struct watchdog_info twl4030_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
.identity = "TWL4030 Watchdog",
};
static const struct watchdog_ops twl4030_wdt_ops = {
.owner = THIS_MODULE,
.start = twl4030_wdt_start,
.stop = twl4030_wdt_stop,
.set_timeout = twl4030_wdt_set_timeout,
};
static int twl4030_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdt;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->info = &twl4030_wdt_info;
wdt->ops = &twl4030_wdt_ops;
wdt->status = 0;
wdt->timeout = 30;
wdt->min_timeout = 1;
wdt->max_timeout = 30;
wdt->parent = dev;
watchdog_set_nowayout(wdt, nowayout);
platform_set_drvdata(pdev, wdt);
twl4030_wdt_stop(wdt);
return devm_watchdog_register_device(dev, wdt);
}
static int twl4030_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
struct watchdog_device *wdt = platform_get_drvdata(pdev);
if (watchdog_active(wdt))
return twl4030_wdt_stop(wdt);
return 0;
}
static int twl4030_wdt_resume(struct platform_device *pdev)
{
struct watchdog_device *wdt = platform_get_drvdata(pdev);
if (watchdog_active(wdt))
return twl4030_wdt_start(wdt);
return 0;
}
static const struct of_device_id twl_wdt_of_match[] = {
{ .compatible = "ti,twl4030-wdt", },
{ },
};
MODULE_DEVICE_TABLE(of, twl_wdt_of_match);
static struct platform_driver twl4030_wdt_driver = {
.probe = twl4030_wdt_probe,
.suspend = pm_ptr(twl4030_wdt_suspend),
.resume = pm_ptr(twl4030_wdt_resume),
.driver = {
.name = "twl4030_wdt",
.of_match_table = twl_wdt_of_match,
},
};
module_platform_driver(twl4030_wdt_driver);
MODULE_AUTHOR("Nokia Corporation");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:twl4030_wdt");
| linux-master | drivers/watchdog/twl4030_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* drivers/char/watchdog/sp805-wdt.c
*
* Watchdog driver for ARM SP805 watchdog module
*
* Copyright (C) 2010 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2 or later. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/device.h>
#include <linux/resource.h>
#include <linux/amba/bus.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/watchdog.h>
/* default timeout in seconds */
#define DEFAULT_TIMEOUT 60
#define MODULE_NAME "sp805-wdt"
/* watchdog register offsets and masks */
#define WDTLOAD 0x000
#define LOAD_MIN 0x00000001
#define LOAD_MAX 0xFFFFFFFF
#define WDTVALUE 0x004
#define WDTCONTROL 0x008
/* control register masks */
#define INT_ENABLE (1 << 0)
#define RESET_ENABLE (1 << 1)
#define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
#define WDTINTCLR 0x00C
#define WDTRIS 0x010
#define WDTMIS 0x014
#define INT_MASK (1 << 0)
#define WDTLOCK 0xC00
#define UNLOCK 0x1ACCE551
#define LOCK 0x00000001
/**
* struct sp805_wdt: sp805 wdt device structure
* @wdd: instance of struct watchdog_device
* @lock: spin lock protecting dev structure and io access
* @base: base address of wdt
* @clk: (optional) clock structure of wdt
* @rate: (optional) clock rate when provided via properties
* @adev: amba device structure of wdt
* @status: current status of wdt
* @load_val: load value to be set for current timeout
*/
struct sp805_wdt {
struct watchdog_device wdd;
spinlock_t lock;
void __iomem *base;
struct clk *clk;
u64 rate;
struct amba_device *adev;
unsigned int load_val;
};
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Set to 1 to keep watchdog running after device release");
/* returns true if wdt is running; otherwise returns false */
static bool wdt_is_running(struct watchdog_device *wdd)
{
struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
}
/* This routine finds load value that will reset system in required timeout */
static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
{
struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
u64 load, rate;
rate = wdt->rate;
/*
* sp805 runs counter with given value twice, after the end of first
* counter it gives an interrupt and then starts counter again. If
* interrupt already occurred then it resets the system. This is why
* load is half of what should be required.
*/
load = div_u64(rate, 2) * timeout - 1;
load = (load > LOAD_MAX) ? LOAD_MAX : load;
load = (load < LOAD_MIN) ? LOAD_MIN : load;
spin_lock(&wdt->lock);
wdt->load_val = load;
/* roundup timeout to closest positive integer value */
wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
spin_unlock(&wdt->lock);
return 0;
}
/* returns number of seconds left for reset to occur */
static unsigned int wdt_timeleft(struct watchdog_device *wdd)
{
struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
u64 load;
spin_lock(&wdt->lock);
load = readl_relaxed(wdt->base + WDTVALUE);
/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
load += wdt->load_val + 1;
spin_unlock(&wdt->lock);
return div_u64(load, wdt->rate);
}
static int
wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd)
{
struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
writel_relaxed(0, wdt->base + WDTCONTROL);
writel_relaxed(0, wdt->base + WDTLOAD);
writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
/* Flush posted writes. */
readl_relaxed(wdt->base + WDTLOCK);
return 0;
}
static int wdt_config(struct watchdog_device *wdd, bool ping)
{
struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
int ret;
if (!ping) {
ret = clk_prepare_enable(wdt->clk);
if (ret) {
dev_err(&wdt->adev->dev, "clock enable fail");
return ret;
}
}
spin_lock(&wdt->lock);
writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
if (!ping)
writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
WDTCONTROL);
writel_relaxed(LOCK, wdt->base + WDTLOCK);
/* Flush posted writes. */
readl_relaxed(wdt->base + WDTLOCK);
spin_unlock(&wdt->lock);
return 0;
}
static int wdt_ping(struct watchdog_device *wdd)
{
return wdt_config(wdd, true);
}
/* enables watchdog timers reset */
static int wdt_enable(struct watchdog_device *wdd)
{
return wdt_config(wdd, false);
}
/* disables watchdog timers reset */
static int wdt_disable(struct watchdog_device *wdd)
{
struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
spin_lock(&wdt->lock);
writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
writel_relaxed(0, wdt->base + WDTCONTROL);
writel_relaxed(LOCK, wdt->base + WDTLOCK);
/* Flush posted writes. */
readl_relaxed(wdt->base + WDTLOCK);
spin_unlock(&wdt->lock);
clk_disable_unprepare(wdt->clk);
return 0;
}
static const struct watchdog_info wdt_info = {
.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = MODULE_NAME,
};
static const struct watchdog_ops wdt_ops = {
.owner = THIS_MODULE,
.start = wdt_enable,
.stop = wdt_disable,
.ping = wdt_ping,
.set_timeout = wdt_setload,
.get_timeleft = wdt_timeleft,
.restart = wdt_restart,
};
static int
sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
{
struct sp805_wdt *wdt;
u64 rate = 0;
int ret = 0;
wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt) {
ret = -ENOMEM;
goto err;
}
wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
/*
* When driver probe with ACPI device, clock devices
* are not available, so watchdog rate get from
* clock-frequency property given in _DSD object.
*/
device_property_read_u64(&adev->dev, "clock-frequency", &rate);
wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
if (IS_ERR(wdt->clk))
return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");
wdt->rate = clk_get_rate(wdt->clk);
if (!wdt->rate)
wdt->rate = rate;
if (!wdt->rate) {
dev_err(&adev->dev, "no clock-frequency property\n");
return -ENODEV;
}
wdt->adev = adev;
wdt->wdd.info = &wdt_info;
wdt->wdd.ops = &wdt_ops;
wdt->wdd.parent = &adev->dev;
spin_lock_init(&wdt->lock);
watchdog_set_nowayout(&wdt->wdd, nowayout);
watchdog_set_drvdata(&wdt->wdd, wdt);
watchdog_set_restart_priority(&wdt->wdd, 128);
watchdog_stop_on_unregister(&wdt->wdd);
/*
* If 'timeout-sec' devicetree property is specified, use that.
* Otherwise, use DEFAULT_TIMEOUT
*/
wdt->wdd.timeout = DEFAULT_TIMEOUT;
watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
wdt_setload(&wdt->wdd, wdt->wdd.timeout);
/*
* If HW is already running, enable/reset the wdt and set the running
* bit to tell the wdt subsystem
*/
if (wdt_is_running(&wdt->wdd)) {
wdt_enable(&wdt->wdd);
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
}
watchdog_stop_on_reboot(&wdt->wdd);
ret = watchdog_register_device(&wdt->wdd);
if (ret)
goto err;
amba_set_drvdata(adev, wdt);
dev_info(&adev->dev, "registration successful\n");
return 0;
err:
dev_err(&adev->dev, "Probe Failed!!!\n");
return ret;
}
static void sp805_wdt_remove(struct amba_device *adev)
{
struct sp805_wdt *wdt = amba_get_drvdata(adev);
watchdog_unregister_device(&wdt->wdd);
watchdog_set_drvdata(&wdt->wdd, NULL);
}
static int __maybe_unused sp805_wdt_suspend(struct device *dev)
{
struct sp805_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
return wdt_disable(&wdt->wdd);
return 0;
}
static int __maybe_unused sp805_wdt_resume(struct device *dev)
{
struct sp805_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->wdd))
return wdt_enable(&wdt->wdd);
return 0;
}
static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
sp805_wdt_resume);
static const struct amba_id sp805_wdt_ids[] = {
{
.id = 0x00141805,
.mask = 0x00ffffff,
},
{
.id = 0x001bb824,
.mask = 0x00ffffff,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
static struct amba_driver sp805_wdt_driver = {
.drv = {
.name = MODULE_NAME,
.pm = &sp805_wdt_dev_pm_ops,
},
.id_table = sp805_wdt_ids,
.probe = sp805_wdt_probe,
.remove = sp805_wdt_remove,
};
module_amba_driver(sp805_wdt_driver);
MODULE_AUTHOR("Viresh Kumar <[email protected]>");
MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sp805_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SBC EPX C3 0.1 A Hardware Watchdog Device for the Winsystems EPX-C3
* single board computer
*
* (c) Copyright 2006 Calin A. Culianu <[email protected]>, All Rights
* Reserved.
*
* based on softdog.c by Alan Cox <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/uaccess.h>
#include <linux/io.h>
static int epx_c3_alive;
#define WATCHDOG_TIMEOUT 1 /* 1 sec default timeout */
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#define EPXC3_WATCHDOG_CTL_REG 0x1ee /* write 1 to enable, 0 to disable */
#define EPXC3_WATCHDOG_PET_REG 0x1ef /* write anything to pet once enabled */
static void epx_c3_start(void)
{
outb(1, EPXC3_WATCHDOG_CTL_REG);
}
static void epx_c3_stop(void)
{
outb(0, EPXC3_WATCHDOG_CTL_REG);
pr_info("Stopped watchdog timer\n");
}
static void epx_c3_pet(void)
{
outb(1, EPXC3_WATCHDOG_PET_REG);
}
/*
* Allow only one person to hold it open
*/
static int epx_c3_open(struct inode *inode, struct file *file)
{
if (epx_c3_alive)
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Activate timer */
epx_c3_start();
epx_c3_pet();
epx_c3_alive = 1;
pr_info("Started watchdog timer\n");
return stream_open(inode, file);
}
static int epx_c3_release(struct inode *inode, struct file *file)
{
/* Shut off the timer.
* Lock it in if it's a module and we defined ...NOWAYOUT */
if (!nowayout)
epx_c3_stop(); /* Turn the WDT off */
epx_c3_alive = 0;
return 0;
}
static ssize_t epx_c3_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
/* Refresh the timer. */
if (len)
epx_c3_pet();
return len;
}
static long epx_c3_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int options, retval = -EINVAL;
int __user *argp = (void __user *)arg;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING,
.firmware_version = 0,
.identity = "Winsystems EPX-C3 H/W Watchdog",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident)))
return -EFAULT;
return 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, argp);
case WDIOC_SETOPTIONS:
if (get_user(options, argp))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
epx_c3_stop();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
epx_c3_start();
retval = 0;
}
return retval;
case WDIOC_KEEPALIVE:
epx_c3_pet();
return 0;
case WDIOC_GETTIMEOUT:
return put_user(WATCHDOG_TIMEOUT, argp);
default:
return -ENOTTY;
}
}
static int epx_c3_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
epx_c3_stop(); /* Turn the WDT off */
return NOTIFY_DONE;
}
static const struct file_operations epx_c3_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = epx_c3_write,
.unlocked_ioctl = epx_c3_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = epx_c3_open,
.release = epx_c3_release,
};
static struct miscdevice epx_c3_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &epx_c3_fops,
};
static struct notifier_block epx_c3_notifier = {
.notifier_call = epx_c3_notify_sys,
};
static int __init watchdog_init(void)
{
int ret;
if (!request_region(EPXC3_WATCHDOG_CTL_REG, 2, "epxc3_watchdog"))
return -EBUSY;
ret = register_reboot_notifier(&epx_c3_notifier);
if (ret) {
pr_err("cannot register reboot notifier (err=%d)\n", ret);
goto out;
}
ret = misc_register(&epx_c3_miscdev);
if (ret) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
unregister_reboot_notifier(&epx_c3_notifier);
goto out;
}
pr_info("Hardware Watchdog Timer for Winsystems EPX-C3 SBC: 0.1\n");
return 0;
out:
release_region(EPXC3_WATCHDOG_CTL_REG, 2);
return ret;
}
static void __exit watchdog_exit(void)
{
misc_deregister(&epx_c3_miscdev);
unregister_reboot_notifier(&epx_c3_notifier);
release_region(EPXC3_WATCHDOG_CTL_REG, 2);
}
module_init(watchdog_init);
module_exit(watchdog_exit);
MODULE_AUTHOR("Calin A. Culianu <[email protected]>");
MODULE_DESCRIPTION("Hardware Watchdog Device for Winsystems EPX-C3 SBC. "
"Note that there is no way to probe for this device -- "
"so only use it if you are *sure* you are running on this specific "
"SBC system from Winsystems! It writes to IO ports 0x1ee and 0x1ef!");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sbc_epx_c3.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
*
* (C) Copyright 2013 - 2014 Xilinx, Inc.
* (C) Copyright 2011 (Alejandro Cabrera <[email protected]>)
*/
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/watchdog.h>
#include <linux/io.h>
#include <linux/of.h>
/* Register offsets for the Wdt device */
#define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
#define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
#define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
/* Control/Status Register Masks */
#define XWT_CSR0_WRS_MASK BIT(3) /* Reset status */
#define XWT_CSR0_WDS_MASK BIT(2) /* Timer state */
#define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
/* Control/Status Register 0/1 bits */
#define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */
/* SelfTest constants */
#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
#define XWT_TIMER_FAILED 0xFFFFFFFF
#define WATCHDOG_NAME "Xilinx Watchdog"
struct xwdt_device {
void __iomem *base;
u32 wdt_interval;
spinlock_t spinlock; /* spinlock for register handling */
struct watchdog_device xilinx_wdt_wdd;
struct clk *clk;
};
static int xilinx_wdt_start(struct watchdog_device *wdd)
{
int ret;
u32 control_status_reg;
struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
ret = clk_enable(xdev->clk);
if (ret) {
dev_err(wdd->parent, "Failed to enable clock\n");
return ret;
}
spin_lock(&xdev->spinlock);
/* Clean previous status and enable the watchdog timer */
control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
xdev->base + XWT_TWCSR0_OFFSET);
iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
spin_unlock(&xdev->spinlock);
dev_dbg(wdd->parent, "Watchdog Started!\n");
return 0;
}
static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
u32 control_status_reg;
struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
spin_lock(&xdev->spinlock);
control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
xdev->base + XWT_TWCSR0_OFFSET);
iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
spin_unlock(&xdev->spinlock);
clk_disable(xdev->clk);
dev_dbg(wdd->parent, "Watchdog Stopped!\n");
return 0;
}
static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
u32 control_status_reg;
struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
spin_lock(&xdev->spinlock);
control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
spin_unlock(&xdev->spinlock);
return 0;
}
static const struct watchdog_info xilinx_wdt_ident = {
.options = WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.firmware_version = 1,
.identity = WATCHDOG_NAME,
};
static const struct watchdog_ops xilinx_wdt_ops = {
.owner = THIS_MODULE,
.start = xilinx_wdt_start,
.stop = xilinx_wdt_stop,
.ping = xilinx_wdt_keepalive,
};
static u32 xwdt_selftest(struct xwdt_device *xdev)
{
int i;
u32 timer_value1;
u32 timer_value2;
spin_lock(&xdev->spinlock);
timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
for (i = 0;
((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
(timer_value2 == timer_value1)); i++) {
timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
}
spin_unlock(&xdev->spinlock);
if (timer_value2 != timer_value1)
return ~XWT_TIMER_FAILED;
else
return XWT_TIMER_FAILED;
}
static int xwdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int rc;
u32 pfreq = 0, enable_once = 0;
struct xwdt_device *xdev;
struct watchdog_device *xilinx_wdt_wdd;
xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
if (!xdev)
return -ENOMEM;
xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
xilinx_wdt_wdd->info = &xilinx_wdt_ident;
xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
xilinx_wdt_wdd->parent = dev;
xdev->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xdev->base))
return PTR_ERR(xdev->base);
rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval",
&xdev->wdt_interval);
if (rc)
dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n");
rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once",
&enable_once);
if (rc)
dev_warn(dev,
"Parameter \"xlnx,wdt-enable-once\" not found\n");
watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
xdev->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(xdev->clk)) {
if (PTR_ERR(xdev->clk) != -ENOENT)
return PTR_ERR(xdev->clk);
/*
* Clock framework support is optional, continue on
* anyways if we don't find a matching clock.
*/
xdev->clk = NULL;
rc = of_property_read_u32(dev->of_node, "clock-frequency",
&pfreq);
if (rc)
dev_warn(dev,
"The watchdog clock freq cannot be obtained\n");
} else {
pfreq = clk_get_rate(xdev->clk);
}
/*
* Twice of the 2^wdt_interval / freq because the first wdt overflow is
* ignored (interrupt), reset is only generated at second wdt overflow
*/
if (pfreq && xdev->wdt_interval)
xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
pfreq);
spin_lock_init(&xdev->spinlock);
watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
rc = xwdt_selftest(xdev);
if (rc == XWT_TIMER_FAILED) {
dev_err(dev, "SelfTest routine error\n");
return rc;
}
rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd);
if (rc)
return rc;
clk_disable(xdev->clk);
dev_info(dev, "Xilinx Watchdog Timer with timeout %ds\n",
xilinx_wdt_wdd->timeout);
platform_set_drvdata(pdev, xdev);
return 0;
}
/**
* xwdt_suspend - Suspend the device.
*
* @dev: handle to the device structure.
* Return: 0 always.
*/
static int __maybe_unused xwdt_suspend(struct device *dev)
{
struct xwdt_device *xdev = dev_get_drvdata(dev);
if (watchdog_active(&xdev->xilinx_wdt_wdd))
xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
return 0;
}
/**
* xwdt_resume - Resume the device.
*
* @dev: handle to the device structure.
* Return: 0 on success, errno otherwise.
*/
static int __maybe_unused xwdt_resume(struct device *dev)
{
struct xwdt_device *xdev = dev_get_drvdata(dev);
int ret = 0;
if (watchdog_active(&xdev->xilinx_wdt_wdd))
ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
return ret;
}
static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
/* Match table for of_platform binding */
static const struct of_device_id xwdt_of_match[] = {
{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
{},
};
MODULE_DEVICE_TABLE(of, xwdt_of_match);
static struct platform_driver xwdt_driver = {
.probe = xwdt_probe,
.driver = {
.name = WATCHDOG_NAME,
.of_match_table = xwdt_of_match,
.pm = &xwdt_pm_ops,
},
};
module_platform_driver(xwdt_driver);
MODULE_AUTHOR("Alejandro Cabrera <[email protected]>");
MODULE_DESCRIPTION("Xilinx Watchdog driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/of_xilinx_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/* riowd.c - driver for hw watchdog inside Super I/O of RIO
*
* Copyright (C) 2001, 2008 David S. Miller ([email protected])
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
/* RIO uses the NatSemi Super I/O power management logical device
* as its' watchdog.
*
* When the watchdog triggers, it asserts a line to the BBC (Boot Bus
* Controller) of the machine. The BBC can only be configured to
* trigger a power-on reset when the signal is asserted. The BBC
* can be configured to ignore the signal entirely as well.
*
* The only Super I/O device register we care about is at index
* 0x05 (WDTO_INDEX) which is the watchdog time-out in minutes (1-255).
* If set to zero, this disables the watchdog. When set, the system
* must periodically (before watchdog expires) clear (set to zero) and
* re-set the watchdog else it will trigger.
*
* There are two other indexed watchdog registers inside this Super I/O
* logical device, but they are unused. The first, at index 0x06 is
* the watchdog control and can be used to make the watchdog timer re-set
* when the PS/2 mouse or serial lines show activity. The second, at
* index 0x07 is merely a sampling of the line from the watchdog to the
* BBC.
*
* The watchdog device generates no interrupts.
*/
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_DESCRIPTION("Hardware watchdog driver for Sun RIO");
MODULE_LICENSE("GPL");
#define DRIVER_NAME "riowd"
#define PFX DRIVER_NAME ": "
struct riowd {
void __iomem *regs;
spinlock_t lock;
};
static struct riowd *riowd_device;
#define WDTO_INDEX 0x05
static int riowd_timeout = 1; /* in minutes */
module_param(riowd_timeout, int, 0);
MODULE_PARM_DESC(riowd_timeout, "Watchdog timeout in minutes");
static void riowd_writereg(struct riowd *p, u8 val, int index)
{
unsigned long flags;
spin_lock_irqsave(&p->lock, flags);
writeb(index, p->regs + 0);
writeb(val, p->regs + 1);
spin_unlock_irqrestore(&p->lock, flags);
}
static int riowd_open(struct inode *inode, struct file *filp)
{
stream_open(inode, filp);
return 0;
}
static int riowd_release(struct inode *inode, struct file *filp)
{
return 0;
}
static long riowd_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
static const struct watchdog_info info = {
.options = WDIOF_SETTIMEOUT,
.firmware_version = 1,
.identity = DRIVER_NAME,
};
void __user *argp = (void __user *)arg;
struct riowd *p = riowd_device;
unsigned int options;
int new_margin;
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &info, sizeof(info)))
return -EFAULT;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
if (put_user(0, (int __user *)argp))
return -EFAULT;
break;
case WDIOC_KEEPALIVE:
riowd_writereg(p, riowd_timeout, WDTO_INDEX);
break;
case WDIOC_SETOPTIONS:
if (copy_from_user(&options, argp, sizeof(options)))
return -EFAULT;
if (options & WDIOS_DISABLECARD)
riowd_writereg(p, 0, WDTO_INDEX);
else if (options & WDIOS_ENABLECARD)
riowd_writereg(p, riowd_timeout, WDTO_INDEX);
else
return -EINVAL;
break;
case WDIOC_SETTIMEOUT:
if (get_user(new_margin, (int __user *)argp))
return -EFAULT;
if ((new_margin < 60) || (new_margin > (255 * 60)))
return -EINVAL;
riowd_timeout = (new_margin + 59) / 60;
riowd_writereg(p, riowd_timeout, WDTO_INDEX);
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(riowd_timeout * 60, (int __user *)argp);
default:
return -EINVAL;
}
return 0;
}
static ssize_t riowd_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
struct riowd *p = riowd_device;
if (count) {
riowd_writereg(p, riowd_timeout, WDTO_INDEX);
return 1;
}
return 0;
}
static const struct file_operations riowd_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.unlocked_ioctl = riowd_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = riowd_open,
.write = riowd_write,
.release = riowd_release,
};
static struct miscdevice riowd_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &riowd_fops
};
static int riowd_probe(struct platform_device *op)
{
struct riowd *p;
int err = -EINVAL;
if (riowd_device)
goto out;
err = -ENOMEM;
p = devm_kzalloc(&op->dev, sizeof(*p), GFP_KERNEL);
if (!p)
goto out;
spin_lock_init(&p->lock);
p->regs = of_ioremap(&op->resource[0], 0, 2, DRIVER_NAME);
if (!p->regs) {
pr_err("Cannot map registers\n");
goto out;
}
/* Make miscdev useable right away */
riowd_device = p;
err = misc_register(&riowd_miscdev);
if (err) {
pr_err("Cannot register watchdog misc device\n");
goto out_iounmap;
}
pr_info("Hardware watchdog [%i minutes], regs at %p\n",
riowd_timeout, p->regs);
platform_set_drvdata(op, p);
return 0;
out_iounmap:
riowd_device = NULL;
of_iounmap(&op->resource[0], p->regs, 2);
out:
return err;
}
static void riowd_remove(struct platform_device *op)
{
struct riowd *p = platform_get_drvdata(op);
misc_deregister(&riowd_miscdev);
of_iounmap(&op->resource[0], p->regs, 2);
}
static const struct of_device_id riowd_match[] = {
{
.name = "pmc",
},
{},
};
MODULE_DEVICE_TABLE(of, riowd_match);
static struct platform_driver riowd_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = riowd_match,
},
.probe = riowd_probe,
.remove_new = riowd_remove,
};
module_platform_driver(riowd_driver);
| linux-master | drivers/watchdog/riowd.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 Broadcom Corporation
*
*/
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define SECWDOG_CTRL_REG 0x00000000
#define SECWDOG_COUNT_REG 0x00000004
#define SECWDOG_RESERVED_MASK 0x1dffffff
#define SECWDOG_WD_LOAD_FLAG 0x10000000
#define SECWDOG_EN_MASK 0x08000000
#define SECWDOG_SRSTEN_MASK 0x04000000
#define SECWDOG_RES_MASK 0x00f00000
#define SECWDOG_COUNT_MASK 0x000fffff
#define SECWDOG_MAX_COUNT SECWDOG_COUNT_MASK
#define SECWDOG_CLKS_SHIFT 20
#define SECWDOG_MAX_RES 15
#define SECWDOG_DEFAULT_RESOLUTION 4
#define SECWDOG_MAX_TRY 1000
#define SECS_TO_TICKS(x, w) ((x) << (w)->resolution)
#define TICKS_TO_SECS(x, w) ((x) >> (w)->resolution)
#define BCM_KONA_WDT_NAME "bcm_kona_wdt"
struct bcm_kona_wdt {
void __iomem *base;
/*
* One watchdog tick is 1/(2^resolution) seconds. Resolution can take
* the values 0-15, meaning one tick can be 1s to 30.52us. Our default
* resolution of 4 means one tick is 62.5ms.
*
* The watchdog counter is 20 bits. Depending on resolution, the maximum
* counter value of 0xfffff expires after about 12 days (resolution 0)
* down to only 32s (resolution 15). The default resolution of 4 gives
* us a maximum of about 18 hours and 12 minutes before the watchdog
* times out.
*/
int resolution;
spinlock_t lock;
#ifdef CONFIG_BCM_KONA_WDT_DEBUG
unsigned long busy_count;
struct dentry *debugfs;
#endif
};
static int secure_register_read(struct bcm_kona_wdt *wdt, uint32_t offset)
{
uint32_t val;
unsigned count = 0;
/*
* If the WD_LOAD_FLAG is set, the watchdog counter field is being
* updated in hardware. Once the WD timer is updated in hardware, it
* gets cleared.
*/
do {
if (unlikely(count > 1))
udelay(5);
val = readl_relaxed(wdt->base + offset);
count++;
} while ((val & SECWDOG_WD_LOAD_FLAG) && count < SECWDOG_MAX_TRY);
#ifdef CONFIG_BCM_KONA_WDT_DEBUG
/* Remember the maximum number iterations due to WD_LOAD_FLAG */
if (count > wdt->busy_count)
wdt->busy_count = count;
#endif
/* This is the only place we return a negative value. */
if (val & SECWDOG_WD_LOAD_FLAG)
return -ETIMEDOUT;
/* We always mask out reserved bits. */
val &= SECWDOG_RESERVED_MASK;
return val;
}
#ifdef CONFIG_BCM_KONA_WDT_DEBUG
static int bcm_kona_show(struct seq_file *s, void *data)
{
int ctl_val, cur_val;
unsigned long flags;
struct bcm_kona_wdt *wdt = s->private;
if (!wdt) {
seq_puts(s, "No device pointer\n");
return 0;
}
spin_lock_irqsave(&wdt->lock, flags);
ctl_val = secure_register_read(wdt, SECWDOG_CTRL_REG);
cur_val = secure_register_read(wdt, SECWDOG_COUNT_REG);
spin_unlock_irqrestore(&wdt->lock, flags);
if (ctl_val < 0 || cur_val < 0) {
seq_puts(s, "Error accessing hardware\n");
} else {
int ctl, cur, ctl_sec, cur_sec, res;
ctl = ctl_val & SECWDOG_COUNT_MASK;
res = (ctl_val & SECWDOG_RES_MASK) >> SECWDOG_CLKS_SHIFT;
cur = cur_val & SECWDOG_COUNT_MASK;
ctl_sec = TICKS_TO_SECS(ctl, wdt);
cur_sec = TICKS_TO_SECS(cur, wdt);
seq_printf(s,
"Resolution: %d / %d\n"
"Control: %d s / %d (%#x) ticks\n"
"Current: %d s / %d (%#x) ticks\n"
"Busy count: %lu\n",
res, wdt->resolution,
ctl_sec, ctl, ctl,
cur_sec, cur, cur,
wdt->busy_count);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(bcm_kona);
static void bcm_kona_wdt_debug_init(struct platform_device *pdev)
{
struct dentry *dir;
struct bcm_kona_wdt *wdt = platform_get_drvdata(pdev);
if (!wdt)
return;
wdt->debugfs = NULL;
dir = debugfs_create_dir(BCM_KONA_WDT_NAME, NULL);
debugfs_create_file("info", S_IFREG | S_IRUGO, dir, wdt,
&bcm_kona_fops);
wdt->debugfs = dir;
}
static void bcm_kona_wdt_debug_exit(struct platform_device *pdev)
{
struct bcm_kona_wdt *wdt = platform_get_drvdata(pdev);
if (wdt)
debugfs_remove_recursive(wdt->debugfs);
}
#else
static void bcm_kona_wdt_debug_init(struct platform_device *pdev) {}
static void bcm_kona_wdt_debug_exit(struct platform_device *pdev) {}
#endif /* CONFIG_BCM_KONA_WDT_DEBUG */
static int bcm_kona_wdt_ctrl_reg_modify(struct bcm_kona_wdt *wdt,
unsigned mask, unsigned newval)
{
int val;
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&wdt->lock, flags);
val = secure_register_read(wdt, SECWDOG_CTRL_REG);
if (val < 0) {
ret = val;
} else {
val &= ~mask;
val |= newval;
writel_relaxed(val, wdt->base + SECWDOG_CTRL_REG);
}
spin_unlock_irqrestore(&wdt->lock, flags);
return ret;
}
static int bcm_kona_wdt_set_resolution_reg(struct bcm_kona_wdt *wdt)
{
if (wdt->resolution > SECWDOG_MAX_RES)
return -EINVAL;
return bcm_kona_wdt_ctrl_reg_modify(wdt, SECWDOG_RES_MASK,
wdt->resolution << SECWDOG_CLKS_SHIFT);
}
static int bcm_kona_wdt_set_timeout_reg(struct watchdog_device *wdog,
unsigned watchdog_flags)
{
struct bcm_kona_wdt *wdt = watchdog_get_drvdata(wdog);
return bcm_kona_wdt_ctrl_reg_modify(wdt, SECWDOG_COUNT_MASK,
SECS_TO_TICKS(wdog->timeout, wdt) |
watchdog_flags);
}
static int bcm_kona_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int t)
{
wdog->timeout = t;
return 0;
}
static unsigned int bcm_kona_wdt_get_timeleft(struct watchdog_device *wdog)
{
struct bcm_kona_wdt *wdt = watchdog_get_drvdata(wdog);
int val;
unsigned long flags;
spin_lock_irqsave(&wdt->lock, flags);
val = secure_register_read(wdt, SECWDOG_COUNT_REG);
spin_unlock_irqrestore(&wdt->lock, flags);
if (val < 0)
return val;
return TICKS_TO_SECS(val & SECWDOG_COUNT_MASK, wdt);
}
static int bcm_kona_wdt_start(struct watchdog_device *wdog)
{
return bcm_kona_wdt_set_timeout_reg(wdog,
SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK);
}
static int bcm_kona_wdt_stop(struct watchdog_device *wdog)
{
struct bcm_kona_wdt *wdt = watchdog_get_drvdata(wdog);
return bcm_kona_wdt_ctrl_reg_modify(wdt, SECWDOG_EN_MASK |
SECWDOG_SRSTEN_MASK, 0);
}
static const struct watchdog_ops bcm_kona_wdt_ops = {
.owner = THIS_MODULE,
.start = bcm_kona_wdt_start,
.stop = bcm_kona_wdt_stop,
.set_timeout = bcm_kona_wdt_set_timeout,
.get_timeleft = bcm_kona_wdt_get_timeleft,
};
static const struct watchdog_info bcm_kona_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "Broadcom Kona Watchdog Timer",
};
static struct watchdog_device bcm_kona_wdt_wdd = {
.info = &bcm_kona_wdt_info,
.ops = &bcm_kona_wdt_ops,
.min_timeout = 1,
.max_timeout = SECWDOG_MAX_COUNT >> SECWDOG_DEFAULT_RESOLUTION,
.timeout = SECWDOG_MAX_COUNT >> SECWDOG_DEFAULT_RESOLUTION,
};
static int bcm_kona_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct bcm_kona_wdt *wdt;
int ret;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
spin_lock_init(&wdt->lock);
wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
wdt->resolution = SECWDOG_DEFAULT_RESOLUTION;
ret = bcm_kona_wdt_set_resolution_reg(wdt);
if (ret) {
dev_err(dev, "Failed to set resolution (error: %d)", ret);
return ret;
}
platform_set_drvdata(pdev, wdt);
watchdog_set_drvdata(&bcm_kona_wdt_wdd, wdt);
bcm_kona_wdt_wdd.parent = dev;
ret = bcm_kona_wdt_set_timeout_reg(&bcm_kona_wdt_wdd, 0);
if (ret) {
dev_err(dev, "Failed set watchdog timeout");
return ret;
}
watchdog_stop_on_reboot(&bcm_kona_wdt_wdd);
watchdog_stop_on_unregister(&bcm_kona_wdt_wdd);
ret = devm_watchdog_register_device(dev, &bcm_kona_wdt_wdd);
if (ret)
return ret;
bcm_kona_wdt_debug_init(pdev);
dev_dbg(dev, "Broadcom Kona Watchdog Timer");
return 0;
}
static void bcm_kona_wdt_remove(struct platform_device *pdev)
{
bcm_kona_wdt_debug_exit(pdev);
dev_dbg(&pdev->dev, "Watchdog driver disabled");
}
static const struct of_device_id bcm_kona_wdt_of_match[] = {
{ .compatible = "brcm,kona-wdt", },
{},
};
MODULE_DEVICE_TABLE(of, bcm_kona_wdt_of_match);
static struct platform_driver bcm_kona_wdt_driver = {
.driver = {
.name = BCM_KONA_WDT_NAME,
.of_match_table = bcm_kona_wdt_of_match,
},
.probe = bcm_kona_wdt_probe,
.remove_new = bcm_kona_wdt_remove,
};
module_platform_driver(bcm_kona_wdt_driver);
MODULE_ALIAS("platform:" BCM_KONA_WDT_NAME);
MODULE_AUTHOR("Markus Mayer <[email protected]>");
MODULE_DESCRIPTION("Broadcom Kona Watchdog Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/bcm_kona_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Watchdog for the 7101 PMU version found in the ALi M1535 chipsets
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/pci.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#define WATCHDOG_NAME "ALi_M1535"
#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
/* internal variables */
static unsigned long ali_is_open;
static char ali_expect_release;
static struct pci_dev *ali_pci;
static u32 ali_timeout_bits; /* stores the computed timeout */
static DEFINE_SPINLOCK(ali_lock); /* Guards the hardware */
/* module parameters */
static int timeout = WATCHDOG_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. (0 < timeout < 18000, default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* ali_start - start watchdog countdown
*
* Starts the timer running providing the timer has a counter
* configuration set.
*/
static void ali_start(void)
{
u32 val;
spin_lock(&ali_lock);
pci_read_config_dword(ali_pci, 0xCC, &val);
val &= ~0x3F; /* Mask count */
val |= (1 << 25) | ali_timeout_bits;
pci_write_config_dword(ali_pci, 0xCC, val);
spin_unlock(&ali_lock);
}
/*
* ali_stop - stop the timer countdown
*
* Stop the ALi watchdog countdown
*/
static void ali_stop(void)
{
u32 val;
spin_lock(&ali_lock);
pci_read_config_dword(ali_pci, 0xCC, &val);
val &= ~0x3F; /* Mask count to zero (disabled) */
val &= ~(1 << 25); /* and for safety mask the reset enable */
pci_write_config_dword(ali_pci, 0xCC, val);
spin_unlock(&ali_lock);
}
/*
* ali_keepalive - send a keepalive to the watchdog
*
* Send a keepalive to the timer (actually we restart the timer).
*/
static void ali_keepalive(void)
{
ali_start();
}
/*
* ali_settimer - compute the timer reload value
* @t: time in seconds
*
* Computes the timeout values needed
*/
static int ali_settimer(int t)
{
if (t < 0)
return -EINVAL;
else if (t < 60)
ali_timeout_bits = t|(1 << 6);
else if (t < 3600)
ali_timeout_bits = (t / 60)|(1 << 7);
else if (t < 18000)
ali_timeout_bits = (t / 300)|(1 << 6)|(1 << 7);
else
return -EINVAL;
timeout = t;
return 0;
}
/*
* /dev/watchdog handling
*/
/*
* ali_write - writes to ALi watchdog
* @file: file from VFS
* @data: user address of data
* @len: length of data
* @ppos: pointer to the file offset
*
* Handle a write to the ALi watchdog. Writing to the file pings
* the watchdog and resets it. Writing the magic 'V' sequence allows
* the next close to turn off the watchdog.
*/
static ssize_t ali_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
/* See if we got the magic character 'V' and reload the timer */
if (len) {
if (!nowayout) {
size_t i;
/* note: just in case someone wrote the
magic character five months ago... */
ali_expect_release = 0;
/* scan to see whether or not we got
the magic character */
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
ali_expect_release = 42;
}
}
/* someone wrote to us, we should reload the timer */
ali_start();
}
return len;
}
/*
* ali_ioctl - handle watchdog ioctls
* @file: VFS file pointer
* @cmd: ioctl number
* @arg: arguments to the ioctl
*
* Handle the watchdog ioctls supported by the ALi driver. Really
* we want an extension to enable irq ack monitoring and the like
*/
static long ali_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.firmware_version = 0,
.identity = "ALi M1535 WatchDog Timer",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
int new_options, retval = -EINVAL;
if (get_user(new_options, p))
return -EFAULT;
if (new_options & WDIOS_DISABLECARD) {
ali_stop();
retval = 0;
}
if (new_options & WDIOS_ENABLECARD) {
ali_start();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
ali_keepalive();
return 0;
case WDIOC_SETTIMEOUT:
{
int new_timeout;
if (get_user(new_timeout, p))
return -EFAULT;
if (ali_settimer(new_timeout))
return -EINVAL;
ali_keepalive();
}
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(timeout, p);
default:
return -ENOTTY;
}
}
/*
* ali_open - handle open of ali watchdog
* @inode: inode from VFS
* @file: file from VFS
*
* Open the ALi watchdog device. Ensure only one person opens it
* at a time. Also start the watchdog running.
*/
static int ali_open(struct inode *inode, struct file *file)
{
/* /dev/watchdog can only be opened once */
if (test_and_set_bit(0, &ali_is_open))
return -EBUSY;
/* Activate */
ali_start();
return stream_open(inode, file);
}
/*
* ali_release - close an ALi watchdog
* @inode: inode from VFS
* @file: file from VFS
*
* Close the ALi watchdog device. Actual shutdown of the timer
* only occurs if the magic sequence has been set.
*/
static int ali_release(struct inode *inode, struct file *file)
{
/*
* Shut off the timer.
*/
if (ali_expect_release == 42)
ali_stop();
else {
pr_crit("Unexpected close, not stopping watchdog!\n");
ali_keepalive();
}
clear_bit(0, &ali_is_open);
ali_expect_release = 0;
return 0;
}
/*
* ali_notify_sys - System down notifier
*
* Notifier for system down
*/
static int ali_notify_sys(struct notifier_block *this,
unsigned long code, void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
ali_stop(); /* Turn the WDT off */
return NOTIFY_DONE;
}
/*
* Data for PCI driver interface
*
* This data only exists for exporting the supported
* PCI ids via MODULE_DEVICE_TABLE. We do not actually
* register a pci_driver, because someone else might one day
* want to register another driver on the same PCI id.
*/
static const struct pci_device_id ali_pci_tbl[] __used = {
{ PCI_VENDOR_ID_AL, 0x1533, PCI_ANY_ID, PCI_ANY_ID,},
{ PCI_VENDOR_ID_AL, 0x1535, PCI_ANY_ID, PCI_ANY_ID,},
{ 0, },
};
MODULE_DEVICE_TABLE(pci, ali_pci_tbl);
/*
* ali_find_watchdog - find a 1535 and 7101
*
* Scans the PCI hardware for a 1535 series bridge and matching 7101
* watchdog device. This may be overtight but it is better to be safe
*/
static int __init ali_find_watchdog(void)
{
struct pci_dev *pdev;
u32 wdog;
/* Check for a 1533/1535 series bridge */
pdev = pci_get_device(PCI_VENDOR_ID_AL, 0x1535, NULL);
if (pdev == NULL)
pdev = pci_get_device(PCI_VENDOR_ID_AL, 0x1533, NULL);
if (pdev == NULL)
return -ENODEV;
pci_dev_put(pdev);
/* Check for the a 7101 PMU */
pdev = pci_get_device(PCI_VENDOR_ID_AL, 0x7101, NULL);
if (pdev == NULL)
return -ENODEV;
if (pci_enable_device(pdev)) {
pci_dev_put(pdev);
return -EIO;
}
ali_pci = pdev;
/*
* Initialize the timer bits
*/
pci_read_config_dword(pdev, 0xCC, &wdog);
/* Timer bits */
wdog &= ~0x3F;
/* Issued events */
wdog &= ~((1 << 27)|(1 << 26)|(1 << 25)|(1 << 24));
/* No monitor bits */
wdog &= ~((1 << 16)|(1 << 13)|(1 << 12)|(1 << 11)|(1 << 10)|(1 << 9));
pci_write_config_dword(pdev, 0xCC, wdog);
return 0;
}
/*
* Kernel Interfaces
*/
static const struct file_operations ali_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = ali_write,
.unlocked_ioctl = ali_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = ali_open,
.release = ali_release,
};
static struct miscdevice ali_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &ali_fops,
};
static struct notifier_block ali_notifier = {
.notifier_call = ali_notify_sys,
};
/*
* watchdog_init - module initialiser
*
* Scan for a suitable watchdog and if so initialize it. Return an error
* if we cannot, the error causes the module to unload
*/
static int __init watchdog_init(void)
{
int ret;
/* Check whether or not the hardware watchdog is there */
if (ali_find_watchdog() != 0)
return -ENODEV;
/* Check that the timeout value is within it's range;
if not reset to the default */
if (timeout < 1 || timeout >= 18000) {
timeout = WATCHDOG_TIMEOUT;
pr_info("timeout value must be 0 < timeout < 18000, using %d\n",
timeout);
}
/* Calculate the watchdog's timeout */
ali_settimer(timeout);
ret = register_reboot_notifier(&ali_notifier);
if (ret != 0) {
pr_err("cannot register reboot notifier (err=%d)\n", ret);
goto out;
}
ret = misc_register(&ali_miscdev);
if (ret != 0) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
goto unreg_reboot;
}
pr_info("initialized. timeout=%d sec (nowayout=%d)\n",
timeout, nowayout);
out:
return ret;
unreg_reboot:
unregister_reboot_notifier(&ali_notifier);
goto out;
}
/*
* watchdog_exit - module de-initialiser
*
* Called while unloading a successfully installed watchdog module.
*/
static void __exit watchdog_exit(void)
{
/* Stop the timer before we leave */
ali_stop();
/* Deregister */
misc_deregister(&ali_miscdev);
unregister_reboot_notifier(&ali_notifier);
pci_dev_put(ali_pci);
}
module_init(watchdog_init);
module_exit(watchdog_exit);
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("ALi M1535 PMU Watchdog Timer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/alim1535_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for Atmel AT91RM9200 (Thunder)
*
* Copyright (C) 2003 SAN People (Pty) Ltd
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/atmel-st.h>
#include <linux/miscdevice.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/uaccess.h>
#define WDT_DEFAULT_TIME 5 /* seconds */
#define WDT_MAX_TIME 256 /* seconds */
static int wdt_time = WDT_DEFAULT_TIME;
static bool nowayout = WATCHDOG_NOWAYOUT;
static struct regmap *regmap_st;
module_param(wdt_time, int, 0);
MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="
__MODULE_STRING(WDT_DEFAULT_TIME) ")");
#ifdef CONFIG_WATCHDOG_NOWAYOUT
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#endif
static unsigned long at91wdt_busy;
/* ......................................................................... */
static int at91rm9200_restart(struct notifier_block *this,
unsigned long mode, void *cmd)
{
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
regmap_write(regmap_st, AT91_ST_WDMR,
AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
regmap_write(regmap_st, AT91_ST_CR, AT91_ST_WDRST);
mdelay(2000);
pr_emerg("Unable to restart system\n");
return NOTIFY_DONE;
}
static struct notifier_block at91rm9200_restart_nb = {
.notifier_call = at91rm9200_restart,
.priority = 192,
};
/*
* Disable the watchdog.
*/
static inline void at91_wdt_stop(void)
{
regmap_write(regmap_st, AT91_ST_WDMR, AT91_ST_EXTEN);
}
/*
* Enable and reset the watchdog.
*/
static inline void at91_wdt_start(void)
{
regmap_write(regmap_st, AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN |
(((65536 * wdt_time) >> 8) & AT91_ST_WDV));
regmap_write(regmap_st, AT91_ST_CR, AT91_ST_WDRST);
}
/*
* Reload the watchdog timer. (ie, pat the watchdog)
*/
static inline void at91_wdt_reload(void)
{
regmap_write(regmap_st, AT91_ST_CR, AT91_ST_WDRST);
}
/* ......................................................................... */
/*
* Watchdog device is opened, and watchdog starts running.
*/
static int at91_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &at91wdt_busy))
return -EBUSY;
at91_wdt_start();
return stream_open(inode, file);
}
/*
* Close the watchdog device.
* If CONFIG_WATCHDOG_NOWAYOUT is NOT defined then the watchdog is also
* disabled.
*/
static int at91_wdt_close(struct inode *inode, struct file *file)
{
/* Disable the watchdog when file is closed */
if (!nowayout)
at91_wdt_stop();
clear_bit(0, &at91wdt_busy);
return 0;
}
/*
* Change the watchdog time interval.
*/
static int at91_wdt_settimeout(int new_time)
{
/*
* All counting occurs at SLOW_CLOCK / 128 = 256 Hz
*
* Since WDV is a 16-bit counter, the maximum period is
* 65536 / 256 = 256 seconds.
*/
if ((new_time <= 0) || (new_time > WDT_MAX_TIME))
return -EINVAL;
/* Set new watchdog time. It will be used when
at91_wdt_start() is called. */
wdt_time = new_time;
return 0;
}
static const struct watchdog_info at91_wdt_info = {
.identity = "at91 watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
};
/*
* Handle commands from user-space.
*/
static long at91_wdt_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
int new_value;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &at91_wdt_info,
sizeof(at91_wdt_info)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
if (get_user(new_value, p))
return -EFAULT;
if (new_value & WDIOS_DISABLECARD)
at91_wdt_stop();
if (new_value & WDIOS_ENABLECARD)
at91_wdt_start();
return 0;
case WDIOC_KEEPALIVE:
at91_wdt_reload(); /* pat the watchdog */
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_value, p))
return -EFAULT;
if (at91_wdt_settimeout(new_value))
return -EINVAL;
/* Enable new time value */
at91_wdt_start();
/* Return current value */
return put_user(wdt_time, p);
case WDIOC_GETTIMEOUT:
return put_user(wdt_time, p);
default:
return -ENOTTY;
}
}
/*
* Pat the watchdog whenever device is written to.
*/
static ssize_t at91_wdt_write(struct file *file, const char *data,
size_t len, loff_t *ppos)
{
at91_wdt_reload(); /* pat the watchdog */
return len;
}
/* ......................................................................... */
static const struct file_operations at91wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.unlocked_ioctl = at91_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = at91_wdt_open,
.release = at91_wdt_close,
.write = at91_wdt_write,
};
static struct miscdevice at91wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &at91wdt_fops,
};
static int at91wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent;
int res;
if (at91wdt_miscdev.parent)
return -EBUSY;
at91wdt_miscdev.parent = &pdev->dev;
parent = dev->parent;
if (!parent) {
dev_err(dev, "no parent\n");
return -ENODEV;
}
regmap_st = syscon_node_to_regmap(parent->of_node);
if (IS_ERR(regmap_st))
return -ENODEV;
res = misc_register(&at91wdt_miscdev);
if (res)
return res;
res = register_restart_handler(&at91rm9200_restart_nb);
if (res)
dev_warn(dev, "failed to register restart handler\n");
pr_info("AT91 Watchdog Timer enabled (%d seconds%s)\n",
wdt_time, nowayout ? ", nowayout" : "");
return 0;
}
static void at91wdt_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int res;
res = unregister_restart_handler(&at91rm9200_restart_nb);
if (res)
dev_warn(dev, "failed to unregister restart handler\n");
misc_deregister(&at91wdt_miscdev);
at91wdt_miscdev.parent = NULL;
}
static void at91wdt_shutdown(struct platform_device *pdev)
{
at91_wdt_stop();
}
static int at91wdt_suspend(struct platform_device *pdev, pm_message_t message)
{
at91_wdt_stop();
return 0;
}
static int at91wdt_resume(struct platform_device *pdev)
{
if (at91wdt_busy)
at91_wdt_start();
return 0;
}
static const struct of_device_id at91_wdt_dt_ids[] = {
{ .compatible = "atmel,at91rm9200-wdt" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
static struct platform_driver at91wdt_driver = {
.probe = at91wdt_probe,
.remove_new = at91wdt_remove,
.shutdown = at91wdt_shutdown,
.suspend = pm_ptr(at91wdt_suspend),
.resume = pm_ptr(at91wdt_resume),
.driver = {
.name = "atmel_st_watchdog",
.of_match_table = at91_wdt_dt_ids,
},
};
static int __init at91_wdt_init(void)
{
/* Check that the heartbeat value is within range;
if not reset to the default */
if (at91_wdt_settimeout(wdt_time)) {
at91_wdt_settimeout(WDT_DEFAULT_TIME);
pr_info("wdt_time value must be 1 <= wdt_time <= 256, using %d\n",
wdt_time);
}
return platform_driver_register(&at91wdt_driver);
}
static void __exit at91_wdt_exit(void)
{
platform_driver_unregister(&at91wdt_driver);
}
module_init(at91_wdt_init);
module_exit(at91_wdt_exit);
MODULE_AUTHOR("Andrew Victor");
MODULE_DESCRIPTION("Watchdog driver for Atmel AT91RM9200");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:atmel_st_watchdog");
| linux-master | drivers/watchdog/at91rm9200_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* IndyDog 0.3 A Hardware Watchdog Device for SGI IP22
*
* (c) Copyright 2002 Guido Guenther <[email protected]>,
* All Rights Reserved.
*
* based on softdog.c by Alan Cox <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/uaccess.h>
#include <asm/sgi/mc.h>
static unsigned long indydog_alive;
static DEFINE_SPINLOCK(indydog_lock);
#define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static void indydog_start(void)
{
spin_lock(&indydog_lock);
sgimc->cpuctrl0 |= SGIMC_CCTRL0_WDOG;
spin_unlock(&indydog_lock);
}
static void indydog_stop(void)
{
spin_lock(&indydog_lock);
sgimc->cpuctrl0 &= ~SGIMC_CCTRL0_WDOG;
spin_unlock(&indydog_lock);
pr_info("Stopped watchdog timer\n");
}
static void indydog_ping(void)
{
sgimc->watchdogt = 0;
}
/*
* Allow only one person to hold it open
*/
static int indydog_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &indydog_alive))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Activate timer */
indydog_start();
indydog_ping();
pr_info("Started watchdog timer\n");
return stream_open(inode, file);
}
static int indydog_release(struct inode *inode, struct file *file)
{
/* Shut off the timer.
* Lock it in if it's a module and we defined ...NOWAYOUT */
if (!nowayout)
indydog_stop(); /* Turn the WDT off */
clear_bit(0, &indydog_alive);
return 0;
}
static ssize_t indydog_write(struct file *file, const char *data,
size_t len, loff_t *ppos)
{
/* Refresh the timer. */
if (len)
indydog_ping();
return len;
}
static long indydog_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int options, retval = -EINVAL;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING,
.firmware_version = 0,
.identity = "Hardware Watchdog for SGI IP22",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user((struct watchdog_info *)arg,
&ident, sizeof(ident)))
return -EFAULT;
return 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, (int *)arg);
case WDIOC_SETOPTIONS:
{
if (get_user(options, (int *)arg))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
indydog_stop();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
indydog_start();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
indydog_ping();
return 0;
case WDIOC_GETTIMEOUT:
return put_user(WATCHDOG_TIMEOUT, (int *)arg);
default:
return -ENOTTY;
}
}
static int indydog_notify_sys(struct notifier_block *this,
unsigned long code, void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
indydog_stop(); /* Turn the WDT off */
return NOTIFY_DONE;
}
static const struct file_operations indydog_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = indydog_write,
.unlocked_ioctl = indydog_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = indydog_open,
.release = indydog_release,
};
static struct miscdevice indydog_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &indydog_fops,
};
static struct notifier_block indydog_notifier = {
.notifier_call = indydog_notify_sys,
};
static int __init watchdog_init(void)
{
int ret;
ret = register_reboot_notifier(&indydog_notifier);
if (ret) {
pr_err("cannot register reboot notifier (err=%d)\n", ret);
return ret;
}
ret = misc_register(&indydog_miscdev);
if (ret) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
unregister_reboot_notifier(&indydog_notifier);
return ret;
}
pr_info("Hardware Watchdog Timer for SGI IP22: 0.3\n");
return 0;
}
static void __exit watchdog_exit(void)
{
misc_deregister(&indydog_miscdev);
unregister_reboot_notifier(&indydog_notifier);
}
module_init(watchdog_init);
module_exit(watchdog_exit);
MODULE_AUTHOR("Guido Guenther <[email protected]>");
MODULE_DESCRIPTION("Hardware Watchdog Device for SGI IP22");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/indydog.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Watchdog driver for the K3 RTI module
*
* (c) Copyright 2019-2020 Texas Instruments Inc.
* All rights reserved.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#define DEFAULT_HEARTBEAT 60
/* Max heartbeat is calculated at 32kHz source clock */
#define MAX_HEARTBEAT 1000
/* Timer register set definition */
#define RTIDWDCTRL 0x90
#define RTIDWDPRLD 0x94
#define RTIWDSTATUS 0x98
#define RTIWDKEY 0x9c
#define RTIDWDCNTR 0xa0
#define RTIWWDRXCTRL 0xa4
#define RTIWWDSIZECTRL 0xa8
#define RTIWWDRX_NMI 0xa
#define RTIWWDSIZE_50P 0x50
#define RTIWWDSIZE_25P 0x500
#define RTIWWDSIZE_12P5 0x5000
#define RTIWWDSIZE_6P25 0x50000
#define RTIWWDSIZE_3P125 0x500000
#define WDENABLE_KEY 0xa98559da
#define WDKEY_SEQ0 0xe51a
#define WDKEY_SEQ1 0xa35c
#define WDT_PRELOAD_SHIFT 13
#define WDT_PRELOAD_MAX 0xfff
#define DWDST BIT(1)
#define PON_REASON_SOF_NUM 0xBBBBCCCC
#define PON_REASON_MAGIC_NUM 0xDDDDDDDD
#define PON_REASON_EOF_NUM 0xCCCCBBBB
#define RESERVED_MEM_MIN_SIZE 12
static int heartbeat = DEFAULT_HEARTBEAT;
/*
* struct to hold data for each WDT device
* @base - base io address of WD device
* @freq - source clock frequency of WDT
* @wdd - hold watchdog device as is in WDT core
*/
struct rti_wdt_device {
void __iomem *base;
unsigned long freq;
struct watchdog_device wdd;
};
static int rti_wdt_start(struct watchdog_device *wdd)
{
u32 timer_margin;
struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
/* set timeout period */
timer_margin = (u64)wdd->timeout * wdt->freq;
timer_margin >>= WDT_PRELOAD_SHIFT;
if (timer_margin > WDT_PRELOAD_MAX)
timer_margin = WDT_PRELOAD_MAX;
writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD);
/*
* RTI only supports a windowed mode, where the watchdog can only
* be petted during the open window; not too early or not too late.
* The HW configuration options only allow for the open window size
* to be 50% or less than that; we obviouly want to configure the open
* window as large as possible so we select the 50% option.
*/
wdd->min_hw_heartbeat_ms = 500 * wdd->timeout;
/* Generate NMI when wdt expires */
writel_relaxed(RTIWWDRX_NMI, wdt->base + RTIWWDRXCTRL);
/* Open window size 50%; this is the largest window size available */
writel_relaxed(RTIWWDSIZE_50P, wdt->base + RTIWWDSIZECTRL);
readl_relaxed(wdt->base + RTIWWDSIZECTRL);
/* enable watchdog */
writel_relaxed(WDENABLE_KEY, wdt->base + RTIDWDCTRL);
return 0;
}
static int rti_wdt_ping(struct watchdog_device *wdd)
{
struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
/* put watchdog in service state */
writel_relaxed(WDKEY_SEQ0, wdt->base + RTIWDKEY);
/* put watchdog in active state */
writel_relaxed(WDKEY_SEQ1, wdt->base + RTIWDKEY);
return 0;
}
static int rti_wdt_setup_hw_hb(struct watchdog_device *wdd, u32 wsize)
{
/*
* RTI only supports a windowed mode, where the watchdog can only
* be petted during the open window; not too early or not too late.
* The HW configuration options only allow for the open window size
* to be 50% or less than that.
*/
switch (wsize) {
case RTIWWDSIZE_50P:
/* 50% open window => 50% min heartbeat */
wdd->min_hw_heartbeat_ms = 500 * heartbeat;
break;
case RTIWWDSIZE_25P:
/* 25% open window => 75% min heartbeat */
wdd->min_hw_heartbeat_ms = 750 * heartbeat;
break;
case RTIWWDSIZE_12P5:
/* 12.5% open window => 87.5% min heartbeat */
wdd->min_hw_heartbeat_ms = 875 * heartbeat;
break;
case RTIWWDSIZE_6P25:
/* 6.5% open window => 93.5% min heartbeat */
wdd->min_hw_heartbeat_ms = 935 * heartbeat;
break;
case RTIWWDSIZE_3P125:
/* 3.125% open window => 96.9% min heartbeat */
wdd->min_hw_heartbeat_ms = 969 * heartbeat;
break;
default:
return -EINVAL;
}
return 0;
}
static unsigned int rti_wdt_get_timeleft_ms(struct watchdog_device *wdd)
{
u64 timer_counter;
u32 val;
struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
/* if timeout has occurred then return 0 */
val = readl_relaxed(wdt->base + RTIWDSTATUS);
if (val & DWDST)
return 0;
timer_counter = readl_relaxed(wdt->base + RTIDWDCNTR);
timer_counter *= 1000;
do_div(timer_counter, wdt->freq);
return timer_counter;
}
static unsigned int rti_wdt_get_timeleft(struct watchdog_device *wdd)
{
return rti_wdt_get_timeleft_ms(wdd) / 1000;
}
static const struct watchdog_info rti_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
.identity = "K3 RTI Watchdog",
};
static const struct watchdog_ops rti_wdt_ops = {
.owner = THIS_MODULE,
.start = rti_wdt_start,
.ping = rti_wdt_ping,
.get_timeleft = rti_wdt_get_timeleft,
};
static int rti_wdt_probe(struct platform_device *pdev)
{
int ret = 0;
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct rti_wdt_device *wdt;
struct clk *clk;
u32 last_ping = 0;
struct device_node *node;
u32 reserved_mem_size;
struct resource res;
u32 *vaddr;
u64 paddr;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
clk = clk_get(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
wdt->freq = clk_get_rate(clk);
clk_put(clk);
if (!wdt->freq) {
dev_err(dev, "Failed to get fck rate.\n");
return -EINVAL;
}
/*
* If watchdog is running at 32k clock, it is not accurate.
* Adjust frequency down in this case so that we don't pet
* the watchdog too often.
*/
if (wdt->freq < 32768)
wdt->freq = wdt->freq * 9 / 10;
pm_runtime_enable(dev);
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
pm_runtime_disable(&pdev->dev);
return dev_err_probe(dev, ret, "runtime pm failed\n");
}
platform_set_drvdata(pdev, wdt);
wdd = &wdt->wdd;
wdd->info = &rti_wdt_info;
wdd->ops = &rti_wdt_ops;
wdd->min_timeout = 1;
wdd->max_hw_heartbeat_ms = (WDT_PRELOAD_MAX << WDT_PRELOAD_SHIFT) /
wdt->freq * 1000;
wdd->parent = dev;
watchdog_set_drvdata(wdd, wdt);
watchdog_set_nowayout(wdd, 1);
watchdog_set_restart_priority(wdd, 128);
wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->base)) {
ret = PTR_ERR(wdt->base);
goto err_iomap;
}
if (readl(wdt->base + RTIDWDCTRL) == WDENABLE_KEY) {
int preset_heartbeat;
u32 time_left_ms;
u64 heartbeat_ms;
u32 wsize;
set_bit(WDOG_HW_RUNNING, &wdd->status);
time_left_ms = rti_wdt_get_timeleft_ms(wdd);
heartbeat_ms = readl(wdt->base + RTIDWDPRLD);
heartbeat_ms <<= WDT_PRELOAD_SHIFT;
heartbeat_ms *= 1000;
do_div(heartbeat_ms, wdt->freq);
preset_heartbeat = heartbeat_ms + 500;
preset_heartbeat /= 1000;
if (preset_heartbeat != heartbeat)
dev_warn(dev, "watchdog already running, ignoring heartbeat config!\n");
heartbeat = preset_heartbeat;
wsize = readl(wdt->base + RTIWWDSIZECTRL);
ret = rti_wdt_setup_hw_hb(wdd, wsize);
if (ret) {
dev_err(dev, "bad window size.\n");
goto err_iomap;
}
last_ping = heartbeat_ms - time_left_ms;
if (time_left_ms > heartbeat_ms) {
dev_warn(dev, "time_left > heartbeat? Assuming last ping just before now.\n");
last_ping = 0;
}
}
node = of_parse_phandle(pdev->dev.of_node, "memory-region", 0);
if (node) {
ret = of_address_to_resource(node, 0, &res);
if (ret) {
dev_err(dev, "No memory address assigned to the region.\n");
goto err_iomap;
}
/*
* If reserved memory is defined for watchdog reset cause.
* Readout the Power-on(PON) reason and pass to bootstatus.
*/
paddr = res.start;
reserved_mem_size = resource_size(&res);
if (reserved_mem_size < RESERVED_MEM_MIN_SIZE) {
dev_err(dev, "The size of reserved memory is too small.\n");
ret = -EINVAL;
goto err_iomap;
}
vaddr = memremap(paddr, reserved_mem_size, MEMREMAP_WB);
if (!vaddr) {
dev_err(dev, "Failed to map memory-region.\n");
ret = -ENOMEM;
goto err_iomap;
}
if (vaddr[0] == PON_REASON_SOF_NUM &&
vaddr[1] == PON_REASON_MAGIC_NUM &&
vaddr[2] == PON_REASON_EOF_NUM) {
wdd->bootstatus |= WDIOF_CARDRESET;
}
memset(vaddr, 0, reserved_mem_size);
memunmap(vaddr);
}
watchdog_init_timeout(wdd, heartbeat, dev);
ret = watchdog_register_device(wdd);
if (ret) {
dev_err(dev, "cannot register watchdog device\n");
goto err_iomap;
}
if (last_ping)
watchdog_set_last_hw_keepalive(wdd, last_ping);
return 0;
err_iomap:
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return ret;
}
static void rti_wdt_remove(struct platform_device *pdev)
{
struct rti_wdt_device *wdt = platform_get_drvdata(pdev);
watchdog_unregister_device(&wdt->wdd);
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static const struct of_device_id rti_wdt_of_match[] = {
{ .compatible = "ti,j7-rti-wdt", },
{},
};
MODULE_DEVICE_TABLE(of, rti_wdt_of_match);
static struct platform_driver rti_wdt_driver = {
.driver = {
.name = "rti-wdt",
.of_match_table = rti_wdt_of_match,
},
.probe = rti_wdt_probe,
.remove_new = rti_wdt_remove,
};
module_platform_driver(rti_wdt_driver);
MODULE_AUTHOR("Tero Kristo <[email protected]>");
MODULE_DESCRIPTION("K3 RTI Watchdog Driver");
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat period in seconds from 1 to "
__MODULE_STRING(MAX_HEARTBEAT) ", default "
__MODULE_STRING(DEFAULT_HEARTBEAT));
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rti-wdt");
| linux-master | drivers/watchdog/rti_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* intel TCO Watchdog Driver
*
* (c) Copyright 2006-2011 Wim Van Sebroeck <[email protected]>.
*
* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
* provide warranty for any of this software. This material is
* provided "AS-IS" and at no charge.
*
* The TCO watchdog is implemented in the following I/O controller hubs:
* (See the intel documentation on http://developer.intel.com.)
* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
* document number 290687-002, 298242-027: 82801BA (ICH2)
* document number 290733-003, 290739-013: 82801CA (ICH3-S)
* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
* document number 290744-001, 290745-025: 82801DB (ICH4)
* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
* document number 273599-001, 273645-002: 82801E (C-ICH)
* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
* document number 300641-004, 300884-013: 6300ESB
* document number 301473-002, 301474-026: 82801F (ICH6)
* document number 313082-001, 313075-006: 631xESB, 632xESB
* document number 307013-003, 307014-024: 82801G (ICH7)
* document number 322896-001, 322897-001: NM10
* document number 313056-003, 313057-017: 82801H (ICH8)
* document number 316972-004, 316973-012: 82801I (ICH9)
* document number 319973-002, 319974-002: 82801J (ICH10)
* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
* document number 320066-003, 320257-008: EP80597 (IICH)
* document number 324645-001, 324646-001: Cougar Point (CPT)
* document number TBD : Patsburg (PBG)
* document number TBD : DH89xxCC
* document number TBD : Panther Point
* document number TBD : Lynx Point
* document number TBD : Lynx Point-LP
*/
/*
* Includes, defines, variables, module parameters, ...
*/
/* Module and version information */
#define DRV_NAME "iTCO_wdt"
#define DRV_VERSION "1.11"
/* Includes */
#include <linux/acpi.h> /* For ACPI support */
#include <linux/bits.h> /* For BIT() */
#include <linux/module.h> /* For module specific items */
#include <linux/moduleparam.h> /* For new moduleparam's */
#include <linux/types.h> /* For standard types (like size_t) */
#include <linux/errno.h> /* For the -ENODEV/... values */
#include <linux/kernel.h> /* For printk/panic/... */
#include <linux/watchdog.h> /* For the watchdog specific items */
#include <linux/init.h> /* For __init/__exit/... */
#include <linux/fs.h> /* For file operations */
#include <linux/platform_device.h> /* For platform_driver framework */
#include <linux/pci.h> /* For pci functions */
#include <linux/ioport.h> /* For io-port access */
#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
#include <linux/io.h> /* For inb/outb/... */
#include <linux/platform_data/itco_wdt.h>
#include <linux/mfd/intel_pmc_bxt.h>
#include "iTCO_vendor.h"
/* Address definitions for the TCO */
/* TCO base address */
#define TCOBASE(p) ((p)->tco_res->start)
/* SMI Control and Enable Register */
#define SMI_EN(p) ((p)->smi_res->start)
#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
/* internal variables */
struct iTCO_wdt_private {
struct watchdog_device wddev;
/* TCO version/generation */
unsigned int iTCO_version;
struct resource *tco_res;
struct resource *smi_res;
/*
* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
* or memory-mapped PMC register bit 4 (TCO version 3).
*/
unsigned long __iomem *gcs_pmc;
/* the lock for io operations */
spinlock_t io_lock;
/* the PCI-device */
struct pci_dev *pci_dev;
/* whether or not the watchdog has been suspended */
bool suspended;
/* no reboot API private data */
void *no_reboot_priv;
/* no reboot update function pointer */
int (*update_no_reboot_bit)(void *p, bool set);
};
/* module parameters */
#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
"5..76 (TCO v1) or 3..614 (TCO v2), default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int turn_SMI_watchdog_clear_off = 1;
module_param(turn_SMI_watchdog_clear_off, int, 0);
MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
/*
* Some TCO specific functions
*/
/*
* The iTCO v1 and v2's internal timer is stored as ticks which decrement
* every 0.6 seconds. v3's internal timer is stored as seconds (some
* datasheets incorrectly state 0.6 seconds).
*/
static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
int secs)
{
return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
}
static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
int ticks)
{
return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
}
static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
{
u32 enable_bit;
switch (p->iTCO_version) {
case 5:
case 3:
enable_bit = 0x00000010;
break;
case 2:
enable_bit = 0x00000020;
break;
case 4:
case 1:
default:
enable_bit = 0x00000002;
break;
}
return enable_bit;
}
static int update_no_reboot_bit_def(void *priv, bool set)
{
return 0;
}
static int update_no_reboot_bit_pci(void *priv, bool set)
{
struct iTCO_wdt_private *p = priv;
u32 val32 = 0, newval32 = 0;
pci_read_config_dword(p->pci_dev, 0xd4, &val32);
if (set)
val32 |= no_reboot_bit(p);
else
val32 &= ~no_reboot_bit(p);
pci_write_config_dword(p->pci_dev, 0xd4, val32);
pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
/* make sure the update is successful */
if (val32 != newval32)
return -EIO;
return 0;
}
static int update_no_reboot_bit_mem(void *priv, bool set)
{
struct iTCO_wdt_private *p = priv;
u32 val32 = 0, newval32 = 0;
val32 = readl(p->gcs_pmc);
if (set)
val32 |= no_reboot_bit(p);
else
val32 &= ~no_reboot_bit(p);
writel(val32, p->gcs_pmc);
newval32 = readl(p->gcs_pmc);
/* make sure the update is successful */
if (val32 != newval32)
return -EIO;
return 0;
}
static int update_no_reboot_bit_cnt(void *priv, bool set)
{
struct iTCO_wdt_private *p = priv;
u16 val, newval;
val = inw(TCO1_CNT(p));
if (set)
val |= BIT(0);
else
val &= ~BIT(0);
outw(val, TCO1_CNT(p));
newval = inw(TCO1_CNT(p));
/* make sure the update is successful */
return val != newval ? -EIO : 0;
}
static int update_no_reboot_bit_pmc(void *priv, bool set)
{
struct intel_pmc_dev *pmc = priv;
u32 bits = PMC_CFG_NO_REBOOT_EN;
u32 value = set ? bits : 0;
return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
}
static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
struct platform_device *pdev,
struct itco_wdt_platform_data *pdata)
{
if (pdata->no_reboot_use_pmc) {
struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
p->update_no_reboot_bit = update_no_reboot_bit_pmc;
p->no_reboot_priv = pmc;
return;
}
if (p->iTCO_version >= 6)
p->update_no_reboot_bit = update_no_reboot_bit_cnt;
else if (p->iTCO_version >= 2)
p->update_no_reboot_bit = update_no_reboot_bit_mem;
else if (p->iTCO_version == 1)
p->update_no_reboot_bit = update_no_reboot_bit_pci;
else
p->update_no_reboot_bit = update_no_reboot_bit_def;
p->no_reboot_priv = p;
}
static int iTCO_wdt_start(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsigned int val;
spin_lock(&p->io_lock);
iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
/* disable chipset's NO_REBOOT bit */
if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
spin_unlock(&p->io_lock);
dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
return -EIO;
}
/* Force the timer to its reload value by writing to the TCO_RLD
register */
if (p->iTCO_version >= 2)
outw(0x01, TCO_RLD(p));
else if (p->iTCO_version == 1)
outb(0x01, TCO_RLD(p));
/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
val = inw(TCO1_CNT(p));
val &= 0xf7ff;
outw(val, TCO1_CNT(p));
val = inw(TCO1_CNT(p));
spin_unlock(&p->io_lock);
if (val & 0x0800)
return -1;
return 0;
}
static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsigned int val;
spin_lock(&p->io_lock);
iTCO_vendor_pre_stop(p->smi_res);
/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
val = inw(TCO1_CNT(p));
val |= 0x0800;
outw(val, TCO1_CNT(p));
val = inw(TCO1_CNT(p));
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
p->update_no_reboot_bit(p->no_reboot_priv, true);
spin_unlock(&p->io_lock);
if ((val & 0x0800) == 0)
return -1;
return 0;
}
static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
spin_lock(&p->io_lock);
/* Reload the timer by writing to the TCO Timer Counter register */
if (p->iTCO_version >= 2) {
outw(0x01, TCO_RLD(p));
} else if (p->iTCO_version == 1) {
/* Reset the timeout status bit so that the timer
* needs to count down twice again before rebooting */
outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
outb(0x01, TCO_RLD(p));
}
spin_unlock(&p->io_lock);
return 0;
}
static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsigned int val16;
unsigned char val8;
unsigned int tmrval;
tmrval = seconds_to_ticks(p, t);
/* For TCO v1 the timer counts down twice before rebooting */
if (p->iTCO_version == 1)
tmrval /= 2;
/* from the specs: */
/* "Values of 0h-3h are ignored and should not be attempted" */
if (tmrval < 0x04)
return -EINVAL;
if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
(p->iTCO_version == 1 && tmrval > 0x03f))
return -EINVAL;
/* Write new heartbeat to watchdog */
if (p->iTCO_version >= 2) {
spin_lock(&p->io_lock);
val16 = inw(TCOv2_TMR(p));
val16 &= 0xfc00;
val16 |= tmrval;
outw(val16, TCOv2_TMR(p));
val16 = inw(TCOv2_TMR(p));
spin_unlock(&p->io_lock);
if ((val16 & 0x3ff) != tmrval)
return -EINVAL;
} else if (p->iTCO_version == 1) {
spin_lock(&p->io_lock);
val8 = inb(TCOv1_TMR(p));
val8 &= 0xc0;
val8 |= (tmrval & 0xff);
outb(val8, TCOv1_TMR(p));
val8 = inb(TCOv1_TMR(p));
spin_unlock(&p->io_lock);
if ((val8 & 0x3f) != tmrval)
return -EINVAL;
}
wd_dev->timeout = t;
return 0;
}
static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
unsigned int val16;
unsigned char val8;
unsigned int time_left = 0;
/* read the TCO Timer */
if (p->iTCO_version >= 2) {
spin_lock(&p->io_lock);
val16 = inw(TCO_RLD(p));
val16 &= 0x3ff;
spin_unlock(&p->io_lock);
time_left = ticks_to_seconds(p, val16);
} else if (p->iTCO_version == 1) {
spin_lock(&p->io_lock);
val8 = inb(TCO_RLD(p));
val8 &= 0x3f;
if (!(inw(TCO1_STS(p)) & 0x0008))
val8 += (inb(TCOv1_TMR(p)) & 0x3f);
spin_unlock(&p->io_lock);
time_left = ticks_to_seconds(p, val8);
}
return time_left;
}
/* Returns true if the watchdog was running */
static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
{
u16 val;
/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
val = inw(TCO1_CNT(p));
if (!(val & BIT(11))) {
set_bit(WDOG_HW_RUNNING, &p->wddev.status);
return true;
}
return false;
}
/*
* Kernel Interfaces
*/
static struct watchdog_info ident = {
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
.identity = DRV_NAME,
};
static const struct watchdog_ops iTCO_wdt_ops = {
.owner = THIS_MODULE,
.start = iTCO_wdt_start,
.stop = iTCO_wdt_stop,
.ping = iTCO_wdt_ping,
.set_timeout = iTCO_wdt_set_timeout,
.get_timeleft = iTCO_wdt_get_timeleft,
};
/*
* Init & exit routines
*/
static int iTCO_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
struct iTCO_wdt_private *p;
unsigned long val32;
int ret;
if (!pdata)
return -ENODEV;
p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
spin_lock_init(&p->io_lock);
p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
if (!p->tco_res)
return -ENODEV;
p->iTCO_version = pdata->version;
p->pci_dev = to_pci_dev(dev->parent);
p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
if (p->smi_res) {
/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
if (!devm_request_region(dev, p->smi_res->start,
resource_size(p->smi_res),
pdev->name)) {
dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
(u64)SMI_EN(p));
return -EBUSY;
}
} else if (iTCO_vendorsupport ||
turn_SMI_watchdog_clear_off >= p->iTCO_version) {
dev_err(dev, "SMI I/O resource is missing\n");
return -ENODEV;
}
iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
/*
* Get the Memory-Mapped GCS or PMC register, we need it for the
* NO_REBOOT flag (TCO v2 and v3).
*/
if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
!pdata->no_reboot_use_pmc) {
p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
if (IS_ERR(p->gcs_pmc))
return PTR_ERR(p->gcs_pmc);
}
/* Check chipset's NO_REBOOT bit */
if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
iTCO_vendor_check_noreboot_on()) {
dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
return -ENODEV; /* Cannot reset NO_REBOOT bit */
}
if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
/*
* Bit 13: TCO_EN -> 0
* Disables TCO logic generating an SMI#
*/
val32 = inl(SMI_EN(p));
val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
outl(val32, SMI_EN(p));
}
if (!devm_request_region(dev, p->tco_res->start,
resource_size(p->tco_res),
pdev->name)) {
dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
(u64)TCOBASE(p));
return -EBUSY;
}
dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
pdata->name, pdata->version, (u64)TCOBASE(p));
/* Clear out the (probably old) status */
switch (p->iTCO_version) {
case 6:
case 5:
case 4:
outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
break;
case 3:
outl(0x20008, TCO1_STS(p));
break;
case 2:
case 1:
default:
outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
break;
}
ident.firmware_version = p->iTCO_version;
p->wddev.info = &ident,
p->wddev.ops = &iTCO_wdt_ops,
p->wddev.bootstatus = 0;
p->wddev.timeout = WATCHDOG_TIMEOUT;
watchdog_set_nowayout(&p->wddev, nowayout);
p->wddev.parent = dev;
watchdog_set_drvdata(&p->wddev, p);
platform_set_drvdata(pdev, p);
if (!iTCO_wdt_set_running(p)) {
/*
* If the watchdog was not running set NO_REBOOT now to
* prevent later reboots.
*/
p->update_no_reboot_bit(p->no_reboot_priv, true);
}
/* Check that the heartbeat value is within it's range;
if not reset to the default */
if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
dev_info(dev, "timeout value out of range, using %d\n",
WATCHDOG_TIMEOUT);
}
watchdog_stop_on_reboot(&p->wddev);
watchdog_stop_on_unregister(&p->wddev);
ret = devm_watchdog_register_device(dev, &p->wddev);
if (ret != 0) {
dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
return ret;
}
dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
heartbeat, nowayout);
return 0;
}
/*
* Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
* the watchdog cannot be pinged while in that state. In ACPI sleep states the
* watchdog is stopped by the platform firmware.
*/
#ifdef CONFIG_ACPI
static inline bool __maybe_unused need_suspend(void)
{
return acpi_target_system_state() == ACPI_STATE_S0;
}
#else
static inline bool __maybe_unused need_suspend(void) { return true; }
#endif
static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
{
struct iTCO_wdt_private *p = dev_get_drvdata(dev);
int ret = 0;
p->suspended = false;
if (watchdog_active(&p->wddev) && need_suspend()) {
ret = iTCO_wdt_stop(&p->wddev);
if (!ret)
p->suspended = true;
}
return ret;
}
static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
{
struct iTCO_wdt_private *p = dev_get_drvdata(dev);
if (p->suspended)
iTCO_wdt_start(&p->wddev);
return 0;
}
static const struct dev_pm_ops iTCO_wdt_pm = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
iTCO_wdt_resume_noirq)
};
static struct platform_driver iTCO_wdt_driver = {
.probe = iTCO_wdt_probe,
.driver = {
.name = DRV_NAME,
.pm = &iTCO_wdt_pm,
},
};
module_platform_driver(iTCO_wdt_driver);
MODULE_AUTHOR("Wim Van Sebroeck <[email protected]>");
MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | drivers/watchdog/iTCO_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Watchdog driver for TS-4800 based boards
*
* Copyright (c) 2015 - Savoir-faire Linux
*
*/
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/* possible feed values */
#define TS4800_WDT_FEED_2S 0x1
#define TS4800_WDT_FEED_10S 0x2
#define TS4800_WDT_DISABLE 0x3
struct ts4800_wdt {
struct watchdog_device wdd;
struct regmap *regmap;
u32 feed_offset;
u32 feed_val;
};
/*
* TS-4800 supports the following timeout values:
*
* value desc
* ---------------------
* 0 feed for 338ms
* 1 feed for 2.706s
* 2 feed for 10.824s
* 3 disable watchdog
*
* Keep the regmap/timeout map ordered by timeout
*/
static const struct {
const int timeout;
const int regval;
} ts4800_wdt_map[] = {
{ 2, TS4800_WDT_FEED_2S },
{ 10, TS4800_WDT_FEED_10S },
};
#define MAX_TIMEOUT_INDEX (ARRAY_SIZE(ts4800_wdt_map) - 1)
static void ts4800_write_feed(struct ts4800_wdt *wdt, u32 val)
{
regmap_write(wdt->regmap, wdt->feed_offset, val);
}
static int ts4800_wdt_start(struct watchdog_device *wdd)
{
struct ts4800_wdt *wdt = watchdog_get_drvdata(wdd);
ts4800_write_feed(wdt, wdt->feed_val);
return 0;
}
static int ts4800_wdt_stop(struct watchdog_device *wdd)
{
struct ts4800_wdt *wdt = watchdog_get_drvdata(wdd);
ts4800_write_feed(wdt, TS4800_WDT_DISABLE);
return 0;
}
static int ts4800_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct ts4800_wdt *wdt = watchdog_get_drvdata(wdd);
int i;
for (i = 0; i < MAX_TIMEOUT_INDEX; i++) {
if (ts4800_wdt_map[i].timeout >= timeout)
break;
}
wdd->timeout = ts4800_wdt_map[i].timeout;
wdt->feed_val = ts4800_wdt_map[i].regval;
return 0;
}
static const struct watchdog_ops ts4800_wdt_ops = {
.owner = THIS_MODULE,
.start = ts4800_wdt_start,
.stop = ts4800_wdt_stop,
.set_timeout = ts4800_wdt_set_timeout,
};
static const struct watchdog_info ts4800_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
.identity = "TS-4800 Watchdog",
};
static int ts4800_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *syscon_np;
struct watchdog_device *wdd;
struct ts4800_wdt *wdt;
u32 reg;
int ret;
syscon_np = of_parse_phandle(np, "syscon", 0);
if (!syscon_np) {
dev_err(dev, "no syscon property\n");
return -ENODEV;
}
ret = of_property_read_u32_index(np, "syscon", 1, ®);
if (ret < 0) {
dev_err(dev, "no offset in syscon\n");
of_node_put(syscon_np);
return ret;
}
/* allocate memory for watchdog struct */
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt) {
of_node_put(syscon_np);
return -ENOMEM;
}
/* set regmap and offset to know where to write */
wdt->feed_offset = reg;
wdt->regmap = syscon_node_to_regmap(syscon_np);
of_node_put(syscon_np);
if (IS_ERR(wdt->regmap)) {
dev_err(dev, "cannot get parent's regmap\n");
return PTR_ERR(wdt->regmap);
}
/* Initialize struct watchdog_device */
wdd = &wdt->wdd;
wdd->parent = dev;
wdd->info = &ts4800_wdt_info;
wdd->ops = &ts4800_wdt_ops;
wdd->min_timeout = ts4800_wdt_map[0].timeout;
wdd->max_timeout = ts4800_wdt_map[MAX_TIMEOUT_INDEX].timeout;
watchdog_set_drvdata(wdd, wdt);
watchdog_set_nowayout(wdd, nowayout);
watchdog_init_timeout(wdd, 0, dev);
/*
* As this watchdog supports only a few values, ts4800_wdt_set_timeout
* must be called to initialize timeout and feed_val with valid values.
* Default to maximum timeout if none, or an invalid one, is provided in
* device tree.
*/
if (!wdd->timeout)
wdd->timeout = wdd->max_timeout;
ts4800_wdt_set_timeout(wdd, wdd->timeout);
/*
* The feed register is write-only, so it is not possible to determine
* watchdog's state. Disable it to be in a known state.
*/
ts4800_wdt_stop(wdd);
ret = devm_watchdog_register_device(dev, wdd);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
wdd->timeout, nowayout);
return 0;
}
static const struct of_device_id ts4800_wdt_of_match[] = {
{ .compatible = "technologic,ts4800-wdt", },
{ },
};
MODULE_DEVICE_TABLE(of, ts4800_wdt_of_match);
static struct platform_driver ts4800_wdt_driver = {
.probe = ts4800_wdt_probe,
.driver = {
.name = "ts4800_wdt",
.of_match_table = ts4800_wdt_of_match,
},
};
module_platform_driver(ts4800_wdt_driver);
MODULE_AUTHOR("Damien Riegel <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:ts4800_wdt");
| linux-master | drivers/watchdog/ts4800_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for the A21 VME CPU Boards
*
* Copyright (C) 2013 MEN Mikro Elektronik Nuernberg GmbH
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/uaccess.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/of.h>
#define NUM_GPIOS 6
enum a21_wdt_gpios {
GPIO_WD_ENAB,
GPIO_WD_FAST,
GPIO_WD_TRIG,
GPIO_WD_RST0,
GPIO_WD_RST1,
GPIO_WD_RST2,
};
struct a21_wdt_drv {
struct watchdog_device wdt;
struct gpio_desc *gpios[NUM_GPIOS];
};
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static unsigned int a21_wdt_get_bootstatus(struct a21_wdt_drv *drv)
{
int reset = 0;
reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0;
reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0;
reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0;
return reset;
}
static int a21_wdt_start(struct watchdog_device *wdt)
{
struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt);
gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1);
return 0;
}
static int a21_wdt_stop(struct watchdog_device *wdt)
{
struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt);
gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0);
return 0;
}
static int a21_wdt_ping(struct watchdog_device *wdt)
{
struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt);
gpiod_set_value(drv->gpios[GPIO_WD_TRIG], 0);
ndelay(10);
gpiod_set_value(drv->gpios[GPIO_WD_TRIG], 1);
return 0;
}
static int a21_wdt_set_timeout(struct watchdog_device *wdt,
unsigned int timeout)
{
struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt);
if (timeout != 1 && timeout != 30) {
dev_err(wdt->parent, "Only 1 and 30 allowed as timeout\n");
return -EINVAL;
}
if (timeout == 30 && wdt->timeout == 1) {
dev_err(wdt->parent,
"Transition from fast to slow mode not allowed\n");
return -EINVAL;
}
if (timeout == 1)
gpiod_set_value(drv->gpios[GPIO_WD_FAST], 1);
else
gpiod_set_value(drv->gpios[GPIO_WD_FAST], 0);
wdt->timeout = timeout;
return 0;
}
static const struct watchdog_info a21_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "MEN A21 Watchdog",
};
static const struct watchdog_ops a21_wdt_ops = {
.owner = THIS_MODULE,
.start = a21_wdt_start,
.stop = a21_wdt_stop,
.ping = a21_wdt_ping,
.set_timeout = a21_wdt_set_timeout,
};
static struct watchdog_device a21_wdt = {
.info = &a21_wdt_info,
.ops = &a21_wdt_ops,
.min_timeout = 1,
.max_timeout = 30,
};
static int a21_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct a21_wdt_drv *drv;
unsigned int reset = 0;
int num_gpios;
int ret;
int i;
drv = devm_kzalloc(dev, sizeof(struct a21_wdt_drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
num_gpios = gpiod_count(dev, NULL);
if (num_gpios != NUM_GPIOS) {
dev_err(dev, "gpios DT property wrong, got %d want %d",
num_gpios, NUM_GPIOS);
return -ENODEV;
}
/* Request the used GPIOs */
for (i = 0; i < num_gpios; i++) {
enum gpiod_flags gflags;
if (i < GPIO_WD_RST0)
gflags = GPIOD_ASIS;
else
gflags = GPIOD_IN;
drv->gpios[i] = devm_gpiod_get_index(dev, NULL, i, gflags);
if (IS_ERR(drv->gpios[i]))
return PTR_ERR(drv->gpios[i]);
gpiod_set_consumer_name(drv->gpios[i], "MEN A21 Watchdog");
/*
* Retrieve the initial value from the GPIOs that should be
* output, then set up the line as output with that value.
*/
if (i < GPIO_WD_RST0) {
int val;
val = gpiod_get_value(drv->gpios[i]);
gpiod_direction_output(drv->gpios[i], val);
}
}
watchdog_init_timeout(&a21_wdt, 30, dev);
watchdog_set_nowayout(&a21_wdt, nowayout);
watchdog_set_drvdata(&a21_wdt, drv);
a21_wdt.parent = dev;
reset = a21_wdt_get_bootstatus(drv);
if (reset == 2)
a21_wdt.bootstatus |= WDIOF_EXTERN1;
else if (reset == 4)
a21_wdt.bootstatus |= WDIOF_CARDRESET;
else if (reset == 5)
a21_wdt.bootstatus |= WDIOF_POWERUNDER;
else if (reset == 7)
a21_wdt.bootstatus |= WDIOF_EXTERN2;
drv->wdt = a21_wdt;
dev_set_drvdata(dev, drv);
ret = devm_watchdog_register_device(dev, &a21_wdt);
if (ret)
return ret;
dev_info(dev, "MEN A21 watchdog timer driver enabled\n");
return 0;
}
static void a21_wdt_shutdown(struct platform_device *pdev)
{
struct a21_wdt_drv *drv = dev_get_drvdata(&pdev->dev);
gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0);
}
static const struct of_device_id a21_wdt_ids[] = {
{ .compatible = "men,a021-wdt" },
{ },
};
MODULE_DEVICE_TABLE(of, a21_wdt_ids);
static struct platform_driver a21_wdt_driver = {
.probe = a21_wdt_probe,
.shutdown = a21_wdt_shutdown,
.driver = {
.name = "a21-watchdog",
.of_match_table = a21_wdt_ids,
},
};
module_platform_driver(a21_wdt_driver);
MODULE_AUTHOR("MEN Mikro Elektronik");
MODULE_DESCRIPTION("MEN A21 Watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:a21-watchdog");
| linux-master | drivers/watchdog/mena21_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALi M7101 PMU Computer Watchdog Timer driver
*
* Based on w83877f_wdt.c by Scott Jennings <[email protected]>
* and the Cobalt kernel WDT timer driver by Tim Hockin
* <[email protected]>
*
* (c)2002 Steve Hill <[email protected]>
*
* This WDT driver is different from most other Linux WDT
* drivers in that the driver will ping the watchdog by itself,
* because this particular WDT has a very short timeout (1.6
* seconds) and it would be insane to count on any userspace
* daemon always getting scheduled within that time frame.
*
* Additions:
* Aug 23, 2004 - Added use_gpio module parameter for use on revision a1d PMUs
* found on very old cobalt hardware.
* -- Mike Waychison <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#define WDT_ENABLE 0x9C
#define WDT_DISABLE 0x8C
#define ALI_7101_WDT 0x92
#define ALI_7101_GPIO 0x7D
#define ALI_7101_GPIO_O 0x7E
#define ALI_WDT_ARM 0x01
/*
* We're going to use a 1 second timeout.
* If we reset the watchdog every ~250ms we should be safe. */
#define WDT_INTERVAL (HZ/4+1)
/*
* We must not require too good response from the userspace daemon.
* Here we require the userspace daemon to send us a heartbeat
* char to /dev/watchdog every 30 seconds.
*/
#define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
/* in seconds, will be multiplied by HZ to get seconds to wait for a ping */
static int timeout = WATCHDOG_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. (1<=timeout<=3600, default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
static int use_gpio; /* Use the pic (for a1d revision alim7101) */
module_param(use_gpio, int, 0);
MODULE_PARM_DESC(use_gpio,
"Use the gpio watchdog (required by old cobalt boards).");
static void wdt_timer_ping(struct timer_list *);
static DEFINE_TIMER(timer, wdt_timer_ping);
static unsigned long next_heartbeat;
static unsigned long wdt_is_open;
static char wdt_expect_close;
static struct pci_dev *alim7101_pmu;
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Whack the dog
*/
static void wdt_timer_ping(struct timer_list *unused)
{
/* If we got a heartbeat pulse within the WDT_US_INTERVAL
* we agree to ping the WDT
*/
char tmp;
if (time_before(jiffies, next_heartbeat)) {
/* Ping the WDT (this is actually a disarm/arm sequence) */
pci_read_config_byte(alim7101_pmu, 0x92, &tmp);
pci_write_config_byte(alim7101_pmu,
ALI_7101_WDT, (tmp & ~ALI_WDT_ARM));
pci_write_config_byte(alim7101_pmu,
ALI_7101_WDT, (tmp | ALI_WDT_ARM));
if (use_gpio) {
pci_read_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, &tmp);
pci_write_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, tmp | 0x20);
pci_write_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, tmp & ~0x20);
}
} else {
pr_warn("Heartbeat lost! Will not ping the watchdog\n");
}
/* Re-set the timer interval */
mod_timer(&timer, jiffies + WDT_INTERVAL);
}
/*
* Utility routines
*/
static void wdt_change(int writeval)
{
char tmp;
pci_read_config_byte(alim7101_pmu, ALI_7101_WDT, &tmp);
if (writeval == WDT_ENABLE) {
pci_write_config_byte(alim7101_pmu,
ALI_7101_WDT, (tmp | ALI_WDT_ARM));
if (use_gpio) {
pci_read_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, &tmp);
pci_write_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, tmp & ~0x20);
}
} else {
pci_write_config_byte(alim7101_pmu,
ALI_7101_WDT, (tmp & ~ALI_WDT_ARM));
if (use_gpio) {
pci_read_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, &tmp);
pci_write_config_byte(alim7101_pmu,
ALI_7101_GPIO_O, tmp | 0x20);
}
}
}
static void wdt_startup(void)
{
next_heartbeat = jiffies + (timeout * HZ);
/* We must enable before we kick off the timer in case the timer
occurs as we ping it */
wdt_change(WDT_ENABLE);
/* Start the timer */
mod_timer(&timer, jiffies + WDT_INTERVAL);
pr_info("Watchdog timer is now enabled\n");
}
static void wdt_turnoff(void)
{
/* Stop the timer */
del_timer_sync(&timer);
wdt_change(WDT_DISABLE);
pr_info("Watchdog timer is now disabled...\n");
}
static void wdt_keepalive(void)
{
/* user land ping */
next_heartbeat = jiffies + (timeout * HZ);
}
/*
* /dev/watchdog handling
*/
static ssize_t fop_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
/* See if we got the magic character 'V' and reload the timer */
if (count) {
if (!nowayout) {
size_t ofs;
/* note: just in case someone wrote the magic character
* five months ago... */
wdt_expect_close = 0;
/* now scan */
for (ofs = 0; ofs != count; ofs++) {
char c;
if (get_user(c, buf + ofs))
return -EFAULT;
if (c == 'V')
wdt_expect_close = 42;
}
}
/* someone wrote to us, we should restart timer */
wdt_keepalive();
}
return count;
}
static int fop_open(struct inode *inode, struct file *file)
{
/* Just in case we're already talking to someone... */
if (test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
/* Good, fire up the show */
wdt_startup();
return stream_open(inode, file);
}
static int fop_close(struct inode *inode, struct file *file)
{
if (wdt_expect_close == 42)
wdt_turnoff();
else {
/* wim: shouldn't there be a: del_timer(&timer); */
pr_crit("device file closed unexpectedly. Will not stop the WDT!\n");
}
clear_bit(0, &wdt_is_open);
wdt_expect_close = 0;
return 0;
}
static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT
| WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = "ALiM7101",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
int new_options, retval = -EINVAL;
if (get_user(new_options, p))
return -EFAULT;
if (new_options & WDIOS_DISABLECARD) {
wdt_turnoff();
retval = 0;
}
if (new_options & WDIOS_ENABLECARD) {
wdt_startup();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
wdt_keepalive();
return 0;
case WDIOC_SETTIMEOUT:
{
int new_timeout;
if (get_user(new_timeout, p))
return -EFAULT;
/* arbitrary upper limit */
if (new_timeout < 1 || new_timeout > 3600)
return -EINVAL;
timeout = new_timeout;
wdt_keepalive();
}
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(timeout, p);
default:
return -ENOTTY;
}
}
static const struct file_operations wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = fop_write,
.open = fop_open,
.release = fop_close,
.unlocked_ioctl = fop_ioctl,
.compat_ioctl = compat_ptr_ioctl,
};
static struct miscdevice wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wdt_fops,
};
static int wdt_restart_handle(struct notifier_block *this, unsigned long mode,
void *cmd)
{
/*
* Cobalt devices have no way of rebooting themselves other
* than getting the watchdog to pull reset, so we restart the
* watchdog on reboot with no heartbeat.
*/
wdt_change(WDT_ENABLE);
/* loop until the watchdog fires */
while (true)
;
return NOTIFY_DONE;
}
static struct notifier_block wdt_restart_handler = {
.notifier_call = wdt_restart_handle,
.priority = 128,
};
/*
* Notifier for system down
*/
static int wdt_notify_sys(struct notifier_block *this,
unsigned long code, void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
wdt_turnoff();
return NOTIFY_DONE;
}
/*
* The WDT needs to learn about soft shutdowns in order to
* turn the timebomb registers off.
*/
static struct notifier_block wdt_notifier = {
.notifier_call = wdt_notify_sys,
};
static void __exit alim7101_wdt_unload(void)
{
wdt_turnoff();
/* Deregister */
misc_deregister(&wdt_miscdev);
unregister_reboot_notifier(&wdt_notifier);
unregister_restart_handler(&wdt_restart_handler);
pci_dev_put(alim7101_pmu);
}
static int __init alim7101_wdt_init(void)
{
int rc = -EBUSY;
struct pci_dev *ali1543_south;
char tmp;
pr_info("Steve Hill <[email protected]>\n");
alim7101_pmu = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101,
NULL);
if (!alim7101_pmu) {
pr_info("ALi M7101 PMU not present - WDT not set\n");
return -EBUSY;
}
/* Set the WDT in the PMU to 1 second */
pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, 0x02);
ali1543_south = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533,
NULL);
if (!ali1543_south) {
pr_info("ALi 1543 South-Bridge not present - WDT not set\n");
goto err_out;
}
pci_read_config_byte(ali1543_south, 0x5e, &tmp);
pci_dev_put(ali1543_south);
if ((tmp & 0x1e) == 0x00) {
if (!use_gpio) {
pr_info("Detected old alim7101 revision 'a1d'. If this is a cobalt board, set the 'use_gpio' module parameter.\n");
goto err_out;
}
nowayout = 1;
} else if ((tmp & 0x1e) != 0x12 && (tmp & 0x1e) != 0x00) {
pr_info("ALi 1543 South-Bridge does not have the correct revision number (???1001?) - WDT not set\n");
goto err_out;
}
if (timeout < 1 || timeout > 3600) {
/* arbitrary upper limit */
timeout = WATCHDOG_TIMEOUT;
pr_info("timeout value must be 1 <= x <= 3600, using %d\n",
timeout);
}
rc = register_reboot_notifier(&wdt_notifier);
if (rc) {
pr_err("cannot register reboot notifier (err=%d)\n", rc);
goto err_out;
}
rc = register_restart_handler(&wdt_restart_handler);
if (rc) {
pr_err("cannot register restart handler (err=%d)\n", rc);
goto err_out_reboot;
}
rc = misc_register(&wdt_miscdev);
if (rc) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
wdt_miscdev.minor, rc);
goto err_out_restart;
}
if (nowayout)
__module_get(THIS_MODULE);
pr_info("WDT driver for ALi M7101 initialised. timeout=%d sec (nowayout=%d)\n",
timeout, nowayout);
return 0;
err_out_restart:
unregister_restart_handler(&wdt_restart_handler);
err_out_reboot:
unregister_reboot_notifier(&wdt_notifier);
err_out:
pci_dev_put(alim7101_pmu);
return rc;
}
module_init(alim7101_wdt_init);
module_exit(alim7101_wdt_unload);
static const struct pci_device_id alim7101_pci_tbl[] __used = {
{ PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533) },
{ PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) },
{ }
};
MODULE_DEVICE_TABLE(pci, alim7101_pci_tbl);
MODULE_AUTHOR("Steve Hill");
MODULE_DESCRIPTION("ALi M7101 PMU Computer Watchdog Timer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/alim7101_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MachZ ZF-Logic Watchdog Timer driver for Linux
*
* The author does NOT admit liability nor provide warranty for
* any of this software. This material is provided "AS-IS" in
* the hope that it may be useful for others.
*
* Author: Fernando Fuganti <[email protected]>
*
* Based on sbc60xxwdt.c by Jakob Oestergaard
*
* We have two timers (wd#1, wd#2) driven by a 32 KHz clock with the
* following periods:
* wd#1 - 2 seconds;
* wd#2 - 7.2 ms;
* After the expiration of wd#1, it can generate a NMI, SCI, SMI, or
* a system RESET and it starts wd#2 that unconditionally will RESET
* the system when the counter reaches zero.
*
* 14-Dec-2001 Matt Domsch <[email protected]>
* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/jiffies.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/uaccess.h>
/* ports */
#define ZF_IOBASE 0x218
#define INDEX 0x218
#define DATA_B 0x219
#define DATA_W 0x21A
#define DATA_D 0x21A
/* indexes */ /* size */
#define ZFL_VERSION 0x02 /* 16 */
#define CONTROL 0x10 /* 16 */
#define STATUS 0x12 /* 8 */
#define COUNTER_1 0x0C /* 16 */
#define COUNTER_2 0x0E /* 8 */
#define PULSE_LEN 0x0F /* 8 */
/* controls */
#define ENABLE_WD1 0x0001
#define ENABLE_WD2 0x0002
#define RESET_WD1 0x0010
#define RESET_WD2 0x0020
#define GEN_SCI 0x0100
#define GEN_NMI 0x0200
#define GEN_SMI 0x0400
#define GEN_RESET 0x0800
/* utilities */
#define WD1 0
#define WD2 1
#define zf_writew(port, data) { outb(port, INDEX); outw(data, DATA_W); }
#define zf_writeb(port, data) { outb(port, INDEX); outb(data, DATA_B); }
#define zf_get_ZFL_version() zf_readw(ZFL_VERSION)
static unsigned short zf_readw(unsigned char port)
{
outb(port, INDEX);
return inw(DATA_W);
}
MODULE_AUTHOR("Fernando Fuganti <[email protected]>");
MODULE_DESCRIPTION("MachZ ZF-Logic Watchdog driver");
MODULE_LICENSE("GPL");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#define PFX "machzwd"
static const struct watchdog_info zf_info = {
.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = "ZF-Logic watchdog",
};
/*
* action refers to action taken when watchdog resets
* 0 = GEN_RESET
* 1 = GEN_SMI
* 2 = GEN_NMI
* 3 = GEN_SCI
* defaults to GEN_RESET (0)
*/
static int action;
module_param(action, int, 0);
MODULE_PARM_DESC(action, "after watchdog resets, generate: "
"0 = RESET(*) 1 = SMI 2 = NMI 3 = SCI");
static void zf_ping(struct timer_list *unused);
static int zf_action = GEN_RESET;
static unsigned long zf_is_open;
static char zf_expect_close;
static DEFINE_SPINLOCK(zf_port_lock);
static DEFINE_TIMER(zf_timer, zf_ping);
static unsigned long next_heartbeat;
/* timeout for user land heart beat (10 seconds) */
#define ZF_USER_TIMEO (HZ*10)
/* timeout for hardware watchdog (~500ms) */
#define ZF_HW_TIMEO (HZ/2)
/* number of ticks on WD#1 (driven by a 32KHz clock, 2s) */
#define ZF_CTIMEOUT 0xffff
#ifndef ZF_DEBUG
#define dprintk(format, args...)
#else
#define dprintk(format, args...) \
pr_debug(":%s:%d: " format, __func__, __LINE__ , ## args)
#endif
static inline void zf_set_status(unsigned char new)
{
zf_writeb(STATUS, new);
}
/* CONTROL register functions */
static inline unsigned short zf_get_control(void)
{
return zf_readw(CONTROL);
}
static inline void zf_set_control(unsigned short new)
{
zf_writew(CONTROL, new);
}
/* WD#? counter functions */
/*
* Just set counter value
*/
static inline void zf_set_timer(unsigned short new, unsigned char n)
{
switch (n) {
case WD1:
zf_writew(COUNTER_1, new);
fallthrough;
case WD2:
zf_writeb(COUNTER_2, new > 0xff ? 0xff : new);
fallthrough;
default:
return;
}
}
/*
* stop hardware timer
*/
static void zf_timer_off(void)
{
unsigned int ctrl_reg = 0;
unsigned long flags;
/* stop internal ping */
del_timer_sync(&zf_timer);
spin_lock_irqsave(&zf_port_lock, flags);
/* stop watchdog timer */
ctrl_reg = zf_get_control();
ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */
ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2);
zf_set_control(ctrl_reg);
spin_unlock_irqrestore(&zf_port_lock, flags);
pr_info("Watchdog timer is now disabled\n");
}
/*
* start hardware timer
*/
static void zf_timer_on(void)
{
unsigned int ctrl_reg = 0;
unsigned long flags;
spin_lock_irqsave(&zf_port_lock, flags);
zf_writeb(PULSE_LEN, 0xff);
zf_set_timer(ZF_CTIMEOUT, WD1);
/* user land ping */
next_heartbeat = jiffies + ZF_USER_TIMEO;
/* start the timer for internal ping */
mod_timer(&zf_timer, jiffies + ZF_HW_TIMEO);
/* start watchdog timer */
ctrl_reg = zf_get_control();
ctrl_reg |= (ENABLE_WD1|zf_action);
zf_set_control(ctrl_reg);
spin_unlock_irqrestore(&zf_port_lock, flags);
pr_info("Watchdog timer is now enabled\n");
}
static void zf_ping(struct timer_list *unused)
{
unsigned int ctrl_reg = 0;
unsigned long flags;
zf_writeb(COUNTER_2, 0xff);
if (time_before(jiffies, next_heartbeat)) {
dprintk("time_before: %ld\n", next_heartbeat - jiffies);
/*
* reset event is activated by transition from 0 to 1 on
* RESET_WD1 bit and we assume that it is already zero...
*/
spin_lock_irqsave(&zf_port_lock, flags);
ctrl_reg = zf_get_control();
ctrl_reg |= RESET_WD1;
zf_set_control(ctrl_reg);
/* ...and nothing changes until here */
ctrl_reg &= ~(RESET_WD1);
zf_set_control(ctrl_reg);
spin_unlock_irqrestore(&zf_port_lock, flags);
mod_timer(&zf_timer, jiffies + ZF_HW_TIMEO);
} else
pr_crit("I will reset your machine\n");
}
static ssize_t zf_write(struct file *file, const char __user *buf, size_t count,
loff_t *ppos)
{
/* See if we got the magic character */
if (count) {
/*
* no need to check for close confirmation
* no way to disable watchdog ;)
*/
if (!nowayout) {
size_t ofs;
/*
* note: just in case someone wrote the magic character
* five months ago...
*/
zf_expect_close = 0;
/* now scan */
for (ofs = 0; ofs != count; ofs++) {
char c;
if (get_user(c, buf + ofs))
return -EFAULT;
if (c == 'V') {
zf_expect_close = 42;
dprintk("zf_expect_close = 42\n");
}
}
}
/*
* Well, anyhow someone wrote to us,
* we should return that favour
*/
next_heartbeat = jiffies + ZF_USER_TIMEO;
dprintk("user ping at %ld\n", jiffies);
}
return count;
}
static long zf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &zf_info, sizeof(zf_info)))
return -EFAULT;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_KEEPALIVE:
zf_ping(NULL);
break;
default:
return -ENOTTY;
}
return 0;
}
static int zf_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &zf_is_open))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
zf_timer_on();
return stream_open(inode, file);
}
static int zf_close(struct inode *inode, struct file *file)
{
if (zf_expect_close == 42)
zf_timer_off();
else {
del_timer(&zf_timer);
pr_err("device file closed unexpectedly. Will not stop the WDT!\n");
}
clear_bit(0, &zf_is_open);
zf_expect_close = 0;
return 0;
}
/*
* Notifier for system down
*/
static int zf_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
zf_timer_off();
return NOTIFY_DONE;
}
static const struct file_operations zf_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = zf_write,
.unlocked_ioctl = zf_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = zf_open,
.release = zf_close,
};
static struct miscdevice zf_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &zf_fops,
};
/*
* The device needs to learn about soft shutdowns in order to
* turn the timebomb registers off.
*/
static struct notifier_block zf_notifier = {
.notifier_call = zf_notify_sys,
};
static void __init zf_show_action(int act)
{
static const char * const str[] = { "RESET", "SMI", "NMI", "SCI" };
pr_info("Watchdog using action = %s\n", str[act]);
}
static int __init zf_init(void)
{
int ret;
pr_info("MachZ ZF-Logic Watchdog driver initializing\n");
ret = zf_get_ZFL_version();
if (!ret || ret == 0xffff) {
pr_warn("no ZF-Logic found\n");
return -ENODEV;
}
if (action <= 3 && action >= 0)
zf_action = zf_action >> action;
else
action = 0;
zf_show_action(action);
if (!request_region(ZF_IOBASE, 3, "MachZ ZFL WDT")) {
pr_err("cannot reserve I/O ports at %d\n", ZF_IOBASE);
ret = -EBUSY;
goto no_region;
}
ret = register_reboot_notifier(&zf_notifier);
if (ret) {
pr_err("can't register reboot notifier (err=%d)\n", ret);
goto no_reboot;
}
ret = misc_register(&zf_miscdev);
if (ret) {
pr_err("can't misc_register on minor=%d\n", WATCHDOG_MINOR);
goto no_misc;
}
zf_set_status(0);
zf_set_control(0);
return 0;
no_misc:
unregister_reboot_notifier(&zf_notifier);
no_reboot:
release_region(ZF_IOBASE, 3);
no_region:
return ret;
}
static void __exit zf_exit(void)
{
zf_timer_off();
misc_deregister(&zf_miscdev);
unregister_reboot_notifier(&zf_notifier);
release_region(ZF_IOBASE, 3);
}
module_init(zf_init);
module_exit(zf_exit);
| linux-master | drivers/watchdog/machzwd.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Acquire Single Board Computer Watchdog Timer driver
*
* Based on wdt.c. Original copyright messages:
*
* (c) Copyright 1996 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>
*
* 14-Dec-2001 Matt Domsch <[email protected]>
* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
* Can't add timeout - driver doesn't allow changing value
*/
/*
* Theory of Operation:
* The Watch-Dog Timer is provided to ensure that standalone
* Systems can always recover from catastrophic conditions that
* caused the CPU to crash. This condition may have occurred by
* external EMI or a software bug. When the CPU stops working
* correctly, hardware on the board will either perform a hardware
* reset (cold boot) or a non-maskable interrupt (NMI) to bring the
* system back to a known state.
*
* The Watch-Dog Timer is controlled by two I/O Ports.
* 443 hex - Read - Enable or refresh the Watch-Dog Timer
* 043 hex - Read - Disable the Watch-Dog Timer
*
* To enable the Watch-Dog Timer, a read from I/O port 443h must
* be performed. This will enable and activate the countdown timer
* which will eventually time out and either reset the CPU or cause
* an NMI depending on the setting of a jumper. To ensure that this
* reset condition does not occur, the Watch-Dog Timer must be
* periodically refreshed by reading the same I/O port 443h.
* The Watch-Dog Timer is disabled by reading I/O port 043h.
*
* The Watch-Dog Timer Time-Out Period is set via jumpers.
* It can be 1, 2, 10, 20, 110 or 220 seconds.
*/
/*
* Includes, defines, variables, module parameters, ...
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
/* Includes */
#include <linux/module.h> /* For module specific items */
#include <linux/moduleparam.h> /* For new moduleparam's */
#include <linux/types.h> /* For standard types (like size_t) */
#include <linux/errno.h> /* For the -ENODEV/... values */
#include <linux/kernel.h> /* For printk/panic/... */
#include <linux/miscdevice.h> /* For struct miscdevice */
#include <linux/watchdog.h> /* For the watchdog specific items */
#include <linux/fs.h> /* For file operations */
#include <linux/ioport.h> /* For io-port access */
#include <linux/platform_device.h> /* For platform_driver framework */
#include <linux/init.h> /* For __init/__exit/... */
#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
#include <linux/io.h> /* For inb/outb/... */
/* Module information */
#define DRV_NAME "acquirewdt"
#define WATCHDOG_NAME "Acquire WDT"
/* There is no way to see what the correct time-out period is */
#define WATCHDOG_HEARTBEAT 0
/* internal variables */
/* the watchdog platform device */
static struct platform_device *acq_platform_device;
static unsigned long acq_is_open;
static char expect_close;
/* module parameters */
/* You must set this - there is no sane way to probe for this board. */
static int wdt_stop = 0x43;
module_param(wdt_stop, int, 0);
MODULE_PARM_DESC(wdt_stop, "Acquire WDT 'stop' io port (default 0x43)");
/* You must set this - there is no sane way to probe for this board. */
static int wdt_start = 0x443;
module_param(wdt_start, int, 0);
MODULE_PARM_DESC(wdt_start, "Acquire WDT 'start' io port (default 0x443)");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Watchdog Operations
*/
static void acq_keepalive(void)
{
/* Write a watchdog value */
inb_p(wdt_start);
}
static void acq_stop(void)
{
/* Turn the card off */
inb_p(wdt_stop);
}
/*
* /dev/watchdog handling
*/
static ssize_t acq_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
/* See if we got the magic character 'V' and reload the timer */
if (count) {
if (!nowayout) {
size_t i;
/* note: just in case someone wrote the magic character
five months ago... */
expect_close = 0;
/* scan to see whether or not we got the
magic character */
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
/* Well, anyhow someone wrote to us, we should
return that favour */
acq_keepalive();
}
return count;
}
static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int options, retval = -EINVAL;
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = WATCHDOG_NAME,
};
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
if (get_user(options, p))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
acq_stop();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
acq_keepalive();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
acq_keepalive();
return 0;
case WDIOC_GETTIMEOUT:
return put_user(WATCHDOG_HEARTBEAT, p);
default:
return -ENOTTY;
}
}
static int acq_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &acq_is_open))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Activate */
acq_keepalive();
return stream_open(inode, file);
}
static int acq_close(struct inode *inode, struct file *file)
{
if (expect_close == 42) {
acq_stop();
} else {
pr_crit("Unexpected close, not stopping watchdog!\n");
acq_keepalive();
}
clear_bit(0, &acq_is_open);
expect_close = 0;
return 0;
}
/*
* Kernel Interfaces
*/
static const struct file_operations acq_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = acq_write,
.unlocked_ioctl = acq_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = acq_open,
.release = acq_close,
};
static struct miscdevice acq_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &acq_fops,
};
/*
* Init & exit routines
*/
static int __init acq_probe(struct platform_device *dev)
{
int ret;
if (wdt_stop != wdt_start) {
if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n", wdt_stop);
ret = -EIO;
goto out;
}
}
if (!request_region(wdt_start, 1, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n", wdt_start);
ret = -EIO;
goto unreg_stop;
}
ret = misc_register(&acq_miscdev);
if (ret != 0) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
goto unreg_regions;
}
pr_info("initialized. (nowayout=%d)\n", nowayout);
return 0;
unreg_regions:
release_region(wdt_start, 1);
unreg_stop:
if (wdt_stop != wdt_start)
release_region(wdt_stop, 1);
out:
return ret;
}
static void acq_remove(struct platform_device *dev)
{
misc_deregister(&acq_miscdev);
release_region(wdt_start, 1);
if (wdt_stop != wdt_start)
release_region(wdt_stop, 1);
}
static void acq_shutdown(struct platform_device *dev)
{
/* Turn the WDT off if we have a soft shutdown */
acq_stop();
}
static struct platform_driver acquirewdt_driver = {
.remove_new = acq_remove,
.shutdown = acq_shutdown,
.driver = {
.name = DRV_NAME,
},
};
static int __init acq_init(void)
{
int err;
pr_info("WDT driver for Acquire single board computer initialising\n");
acq_platform_device = platform_device_register_simple(DRV_NAME,
-1, NULL, 0);
if (IS_ERR(acq_platform_device))
return PTR_ERR(acq_platform_device);
err = platform_driver_probe(&acquirewdt_driver, acq_probe);
if (err)
goto unreg_platform_device;
return 0;
unreg_platform_device:
platform_device_unregister(acq_platform_device);
return err;
}
static void __exit acq_exit(void)
{
platform_device_unregister(acq_platform_device);
platform_driver_unregister(&acquirewdt_driver);
pr_info("Watchdog Module Unloaded\n");
}
module_init(acq_init);
module_exit(acq_exit);
MODULE_AUTHOR("David Woodhouse");
MODULE_DESCRIPTION("Acquire Inc. Single Board Computer Watchdog Timer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/acquirewdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* i6300esb: Watchdog timer driver for Intel 6300ESB chipset
*
* (c) Copyright 2004 Google Inc.
* (c) Copyright 2005 David Härdeman <[email protected]>
*
* based on i810-tco.c which is in turn based on softdog.c
*
* The timer is implemented in the following I/O controller hubs:
* (See the intel documentation on http://developer.intel.com.)
* 6300ESB chip : document number 300641-004
*
* 2004YYZZ Ross Biro
* Initial version 0.01
* 2004YYZZ Ross Biro
* Version 0.02
* 20050210 David Härdeman <[email protected]>
* Ported driver to kernel 2.6
* 20171016 Radu Rendec <[email protected]>
* Change driver to use the watchdog subsystem
* Add support for multiple 6300ESB devices
*/
/*
* Includes, defines, variables, module parameters, ...
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/uaccess.h>
#include <linux/io.h>
/* Module and version information */
#define ESB_MODULE_NAME "i6300ESB timer"
/* PCI configuration registers */
#define ESB_CONFIG_REG 0x60 /* Config register */
#define ESB_LOCK_REG 0x68 /* WDT lock register */
/* Memory mapped registers */
#define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
#define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
#define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
#define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
/* Lock register bits */
#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
/* Config register bits */
#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
#define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
/* Reload register bits */
#define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
/* Magic constants */
#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
/* module parameters */
/* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
#define ESB_HEARTBEAT_MIN 1
#define ESB_HEARTBEAT_MAX 2046
#define ESB_HEARTBEAT_DEFAULT 30
#define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \
"<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX)
static int heartbeat; /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE
", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/* internal variables */
struct esb_dev {
struct watchdog_device wdd;
void __iomem *base;
struct pci_dev *pdev;
};
#define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)
/*
* Some i6300ESB specific functions
*/
/*
* Prepare for reloading the timer by unlocking the proper registers.
* This is performed by first writing 0x80 followed by 0x86 to the
* reload register. After this the appropriate registers can be written
* to once before they need to be unlocked again.
*/
static inline void esb_unlock_registers(struct esb_dev *edev)
{
writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev));
writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev));
}
static int esb_timer_start(struct watchdog_device *wdd)
{
struct esb_dev *edev = to_esb_dev(wdd);
int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status);
u8 val;
esb_unlock_registers(edev);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
/* Enable or Enable + Lock? */
val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00);
pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val);
return 0;
}
static int esb_timer_stop(struct watchdog_device *wdd)
{
struct esb_dev *edev = to_esb_dev(wdd);
u8 val;
/* First, reset timers as suggested by the docs */
esb_unlock_registers(edev);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
/* Then disable the WDT */
pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0);
pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val);
/* Returns 0 if the timer was disabled, non-zero otherwise */
return val & ESB_WDT_ENABLE;
}
static int esb_timer_keepalive(struct watchdog_device *wdd)
{
struct esb_dev *edev = to_esb_dev(wdd);
esb_unlock_registers(edev);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
/* FIXME: Do we need to flush anything here? */
return 0;
}
static int esb_timer_set_heartbeat(struct watchdog_device *wdd,
unsigned int time)
{
struct esb_dev *edev = to_esb_dev(wdd);
u32 val;
/* We shift by 9, so if we are passed a value of 1 sec,
* val will be 1 << 9 = 512, then write that to two
* timers => 2 * 512 = 1024 (which is decremented at 1KHz)
*/
val = time << 9;
/* Write timer 1 */
esb_unlock_registers(edev);
writel(val, ESB_TIMER1_REG(edev));
/* Write timer 2 */
esb_unlock_registers(edev);
writel(val, ESB_TIMER2_REG(edev));
/* Reload */
esb_unlock_registers(edev);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
/* FIXME: Do we need to flush everything out? */
/* Done */
wdd->timeout = time;
return 0;
}
/*
* Watchdog Subsystem Interfaces
*/
static struct watchdog_info esb_info = {
.identity = ESB_MODULE_NAME,
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops esb_ops = {
.owner = THIS_MODULE,
.start = esb_timer_start,
.stop = esb_timer_stop,
.set_timeout = esb_timer_set_heartbeat,
.ping = esb_timer_keepalive,
};
/*
* Data for PCI driver interface
*/
static const struct pci_device_id esb_pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
{ 0, }, /* End of list */
};
MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
/*
* Init & exit routines
*/
static unsigned char esb_getdevice(struct esb_dev *edev)
{
if (pci_enable_device(edev->pdev)) {
dev_err(&edev->pdev->dev, "failed to enable device\n");
goto err_devput;
}
if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) {
dev_err(&edev->pdev->dev, "failed to request region\n");
goto err_disable;
}
edev->base = pci_ioremap_bar(edev->pdev, 0);
if (edev->base == NULL) {
/* Something's wrong here, BASEADDR has to be set */
dev_err(&edev->pdev->dev, "failed to get BASEADDR\n");
goto err_release;
}
/* Done */
dev_set_drvdata(&edev->pdev->dev, edev);
return 1;
err_release:
pci_release_region(edev->pdev, 0);
err_disable:
pci_disable_device(edev->pdev);
err_devput:
return 0;
}
static void esb_initdevice(struct esb_dev *edev)
{
u8 val1;
u16 val2;
/*
* Config register:
* Bit 5 : 0 = Enable WDT_OUTPUT
* Bit 2 : 0 = set the timer frequency to the PCI clock
* divided by 2^15 (approx 1KHz).
* Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
* The watchdog has two timers, it can be setup so that the
* expiry of timer1 results in an interrupt and the expiry of
* timer2 results in a reboot. We set it to not generate
* any interrupts as there is not much we can do with it
* right now.
*/
pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003);
/* Check that the WDT isn't already locked */
pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1);
if (val1 & ESB_WDT_LOCK)
dev_warn(&edev->pdev->dev, "nowayout already set\n");
/* Set the timer to watchdog mode and disable it for now */
pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00);
/* Check if the watchdog was previously triggered */
esb_unlock_registers(edev);
val2 = readw(ESB_RELOAD_REG(edev));
if (val2 & ESB_WDT_TIMEOUT)
edev->wdd.bootstatus = WDIOF_CARDRESET;
/* Reset WDT_TIMEOUT flag and timers */
esb_unlock_registers(edev);
writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG(edev));
/* And set the correct timeout value */
esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout);
}
static int esb_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct esb_dev *edev;
int ret;
edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL);
if (!edev)
return -ENOMEM;
/* Check whether or not the hardware watchdog is there */
edev->pdev = pdev;
if (!esb_getdevice(edev))
return -ENODEV;
/* Initialize the watchdog and make sure it does not run */
edev->wdd.info = &esb_info;
edev->wdd.ops = &esb_ops;
edev->wdd.min_timeout = ESB_HEARTBEAT_MIN;
edev->wdd.max_timeout = ESB_HEARTBEAT_MAX;
edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT;
watchdog_init_timeout(&edev->wdd, heartbeat, NULL);
watchdog_set_nowayout(&edev->wdd, nowayout);
watchdog_stop_on_reboot(&edev->wdd);
watchdog_stop_on_unregister(&edev->wdd);
esb_initdevice(edev);
/* Register the watchdog so that userspace has access to it */
ret = watchdog_register_device(&edev->wdd);
if (ret != 0)
goto err_unmap;
dev_info(&pdev->dev,
"initialized. heartbeat=%d sec (nowayout=%d)\n",
edev->wdd.timeout, nowayout);
return 0;
err_unmap:
iounmap(edev->base);
pci_release_region(edev->pdev, 0);
pci_disable_device(edev->pdev);
return ret;
}
static void esb_remove(struct pci_dev *pdev)
{
struct esb_dev *edev = dev_get_drvdata(&pdev->dev);
watchdog_unregister_device(&edev->wdd);
iounmap(edev->base);
pci_release_region(edev->pdev, 0);
pci_disable_device(edev->pdev);
}
static struct pci_driver esb_driver = {
.name = ESB_MODULE_NAME,
.id_table = esb_pci_tbl,
.probe = esb_probe,
.remove = esb_remove,
};
module_pci_driver(esb_driver);
MODULE_AUTHOR("Ross Biro and David Härdeman");
MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/i6300esb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 National Instruments Corp.
*/
#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/watchdog.h>
#define NIWD_CONTROL 0x01
#define NIWD_COUNTER2 0x02
#define NIWD_COUNTER1 0x03
#define NIWD_COUNTER0 0x04
#define NIWD_SEED2 0x05
#define NIWD_SEED1 0x06
#define NIWD_SEED0 0x07
#define NIWD_IO_SIZE 0x08
#define NIWD_CONTROL_MODE 0x80
#define NIWD_CONTROL_PROC_RESET 0x20
#define NIWD_CONTROL_PET 0x10
#define NIWD_CONTROL_RUNNING 0x08
#define NIWD_CONTROL_CAPTURECOUNTER 0x04
#define NIWD_CONTROL_RESET 0x02
#define NIWD_CONTROL_ALARM 0x01
#define NIWD_PERIOD_NS 30720
#define NIWD_MIN_TIMEOUT 1
#define NIWD_MAX_TIMEOUT 515
#define NIWD_DEFAULT_TIMEOUT 60
#define NIWD_NAME "ni903x_wdt"
struct ni903x_wdt {
struct device *dev;
u16 io_base;
struct watchdog_device wdd;
};
static unsigned int timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. (default="
__MODULE_STRING(NIWD_DEFAULT_TIMEOUT) ")");
static int nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, int, S_IRUGO);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static void ni903x_start(struct ni903x_wdt *wdt)
{
u8 control = inb(wdt->io_base + NIWD_CONTROL);
outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL);
outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL);
}
static int ni903x_wdd_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd);
u32 counter = timeout * (1000000000 / NIWD_PERIOD_NS);
outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2);
outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1);
outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0);
wdd->timeout = timeout;
return 0;
}
static unsigned int ni903x_wdd_get_timeleft(struct watchdog_device *wdd)
{
struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd);
u8 control, counter0, counter1, counter2;
u32 counter;
control = inb(wdt->io_base + NIWD_CONTROL);
control |= NIWD_CONTROL_CAPTURECOUNTER;
outb(control, wdt->io_base + NIWD_CONTROL);
counter2 = inb(wdt->io_base + NIWD_COUNTER2);
counter1 = inb(wdt->io_base + NIWD_COUNTER1);
counter0 = inb(wdt->io_base + NIWD_COUNTER0);
counter = (counter2 << 16) | (counter1 << 8) | counter0;
return counter / (1000000000 / NIWD_PERIOD_NS);
}
static int ni903x_wdd_ping(struct watchdog_device *wdd)
{
struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd);
u8 control;
control = inb(wdt->io_base + NIWD_CONTROL);
outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL);
return 0;
}
static int ni903x_wdd_start(struct watchdog_device *wdd)
{
struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd);
outb(NIWD_CONTROL_RESET | NIWD_CONTROL_PROC_RESET,
wdt->io_base + NIWD_CONTROL);
ni903x_wdd_set_timeout(wdd, wdd->timeout);
ni903x_start(wdt);
return 0;
}
static int ni903x_wdd_stop(struct watchdog_device *wdd)
{
struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd);
outb(NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL);
return 0;
}
static acpi_status ni903x_resources(struct acpi_resource *res, void *data)
{
struct ni903x_wdt *wdt = data;
u16 io_size;
switch (res->type) {
case ACPI_RESOURCE_TYPE_IO:
if (wdt->io_base != 0) {
dev_err(wdt->dev, "too many IO resources\n");
return AE_ERROR;
}
wdt->io_base = res->data.io.minimum;
io_size = res->data.io.address_length;
if (io_size < NIWD_IO_SIZE) {
dev_err(wdt->dev, "memory region too small\n");
return AE_ERROR;
}
if (!devm_request_region(wdt->dev, wdt->io_base, io_size,
NIWD_NAME)) {
dev_err(wdt->dev, "failed to get memory region\n");
return AE_ERROR;
}
return AE_OK;
case ACPI_RESOURCE_TYPE_END_TAG:
default:
/* Ignore unsupported resources, e.g. IRQ */
return AE_OK;
}
}
static const struct watchdog_info ni903x_wdd_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "NI Watchdog",
};
static const struct watchdog_ops ni903x_wdd_ops = {
.owner = THIS_MODULE,
.start = ni903x_wdd_start,
.stop = ni903x_wdd_stop,
.ping = ni903x_wdd_ping,
.set_timeout = ni903x_wdd_set_timeout,
.get_timeleft = ni903x_wdd_get_timeleft,
};
static int ni903x_acpi_add(struct acpi_device *device)
{
struct device *dev = &device->dev;
struct watchdog_device *wdd;
struct ni903x_wdt *wdt;
acpi_status status;
int ret;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
device->driver_data = wdt;
wdt->dev = dev;
status = acpi_walk_resources(device->handle, METHOD_NAME__CRS,
ni903x_resources, wdt);
if (ACPI_FAILURE(status) || wdt->io_base == 0) {
dev_err(dev, "failed to get resources\n");
return -ENODEV;
}
wdd = &wdt->wdd;
wdd->info = &ni903x_wdd_info;
wdd->ops = &ni903x_wdd_ops;
wdd->min_timeout = NIWD_MIN_TIMEOUT;
wdd->max_timeout = NIWD_MAX_TIMEOUT;
wdd->timeout = NIWD_DEFAULT_TIMEOUT;
wdd->parent = dev;
watchdog_set_drvdata(wdd, wdt);
watchdog_set_nowayout(wdd, nowayout);
watchdog_init_timeout(wdd, timeout, dev);
ret = watchdog_register_device(wdd);
if (ret)
return ret;
/* Switch from boot mode to user mode */
outb(NIWD_CONTROL_RESET | NIWD_CONTROL_MODE,
wdt->io_base + NIWD_CONTROL);
dev_dbg(dev, "io_base=0x%04X, timeout=%d, nowayout=%d\n",
wdt->io_base, timeout, nowayout);
return 0;
}
static void ni903x_acpi_remove(struct acpi_device *device)
{
struct ni903x_wdt *wdt = acpi_driver_data(device);
ni903x_wdd_stop(&wdt->wdd);
watchdog_unregister_device(&wdt->wdd);
}
static const struct acpi_device_id ni903x_device_ids[] = {
{"NIC775C", 0},
{"", 0},
};
MODULE_DEVICE_TABLE(acpi, ni903x_device_ids);
static struct acpi_driver ni903x_acpi_driver = {
.name = NIWD_NAME,
.ids = ni903x_device_ids,
.ops = {
.add = ni903x_acpi_add,
.remove = ni903x_acpi_remove,
},
};
module_acpi_driver(ni903x_acpi_driver);
MODULE_DESCRIPTION("NI 903x Watchdog");
MODULE_AUTHOR("Jeff Westfahl <[email protected]>");
MODULE_AUTHOR("Kyle Roeschley <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/ni903x_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2018-2019 NXP.
*/
#include <linux/arm-smccc.h>
#include <linux/firmware/imx/sci.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define DEFAULT_TIMEOUT 60
/*
* Software timer tick implemented in scfw side, support 10ms to 0xffffffff ms
* in theory, but for normal case, 1s~128s is enough, you can change this max
* value in case it's not enough.
*/
#define MAX_TIMEOUT 128
#define IMX_SIP_TIMER 0xC2000002
#define IMX_SIP_TIMER_START_WDOG 0x01
#define IMX_SIP_TIMER_STOP_WDOG 0x02
#define IMX_SIP_TIMER_SET_WDOG_ACT 0x03
#define IMX_SIP_TIMER_PING_WDOG 0x04
#define IMX_SIP_TIMER_SET_TIMEOUT_WDOG 0x05
#define IMX_SIP_TIMER_GET_WDOG_STAT 0x06
#define IMX_SIP_TIMER_SET_PRETIME_WDOG 0x07
#define SC_TIMER_WDOG_ACTION_PARTITION 0
#define SC_IRQ_WDOG 1
#define SC_IRQ_GROUP_WDOG 1
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0000);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
struct imx_sc_wdt_device {
struct watchdog_device wdd;
struct notifier_block wdt_notifier;
};
static int imx_sc_wdt_ping(struct watchdog_device *wdog)
{
struct arm_smccc_res res;
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_PING_WDOG,
0, 0, 0, 0, 0, 0, &res);
return 0;
}
static int imx_sc_wdt_start(struct watchdog_device *wdog)
{
struct arm_smccc_res res;
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_START_WDOG,
0, 0, 0, 0, 0, 0, &res);
if (res.a0)
return -EACCES;
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_WDOG_ACT,
SC_TIMER_WDOG_ACTION_PARTITION,
0, 0, 0, 0, 0, &res);
return res.a0 ? -EACCES : 0;
}
static int imx_sc_wdt_stop(struct watchdog_device *wdog)
{
struct arm_smccc_res res;
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_STOP_WDOG,
0, 0, 0, 0, 0, 0, &res);
return res.a0 ? -EACCES : 0;
}
static int imx_sc_wdt_set_timeout(struct watchdog_device *wdog,
unsigned int timeout)
{
struct arm_smccc_res res;
wdog->timeout = timeout;
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_TIMEOUT_WDOG,
timeout * 1000, 0, 0, 0, 0, 0, &res);
return res.a0 ? -EACCES : 0;
}
static int imx_sc_wdt_set_pretimeout(struct watchdog_device *wdog,
unsigned int pretimeout)
{
struct arm_smccc_res res;
/*
* SCU firmware calculates pretimeout based on current time
* stamp instead of watchdog timeout stamp, need to convert
* the pretimeout to SCU firmware's timeout value.
*/
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_PRETIME_WDOG,
(wdog->timeout - pretimeout) * 1000, 0, 0, 0,
0, 0, &res);
if (res.a0)
return -EACCES;
wdog->pretimeout = pretimeout;
return 0;
}
static int imx_sc_wdt_notify(struct notifier_block *nb,
unsigned long event, void *group)
{
struct imx_sc_wdt_device *imx_sc_wdd =
container_of(nb,
struct imx_sc_wdt_device,
wdt_notifier);
if (event & SC_IRQ_WDOG &&
*(u8 *)group == SC_IRQ_GROUP_WDOG)
watchdog_notify_pretimeout(&imx_sc_wdd->wdd);
return 0;
}
static void imx_sc_wdt_action(void *data)
{
struct notifier_block *wdt_notifier = data;
imx_scu_irq_unregister_notifier(wdt_notifier);
imx_scu_irq_group_enable(SC_IRQ_GROUP_WDOG,
SC_IRQ_WDOG,
false);
}
static const struct watchdog_ops imx_sc_wdt_ops = {
.owner = THIS_MODULE,
.start = imx_sc_wdt_start,
.stop = imx_sc_wdt_stop,
.ping = imx_sc_wdt_ping,
.set_timeout = imx_sc_wdt_set_timeout,
.set_pretimeout = imx_sc_wdt_set_pretimeout,
};
static struct watchdog_info imx_sc_wdt_info = {
.identity = "i.MX SC watchdog timer",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static int imx_sc_wdt_probe(struct platform_device *pdev)
{
struct imx_sc_wdt_device *imx_sc_wdd;
struct watchdog_device *wdog;
struct device *dev = &pdev->dev;
int ret;
imx_sc_wdd = devm_kzalloc(dev, sizeof(*imx_sc_wdd), GFP_KERNEL);
if (!imx_sc_wdd)
return -ENOMEM;
platform_set_drvdata(pdev, imx_sc_wdd);
wdog = &imx_sc_wdd->wdd;
wdog->info = &imx_sc_wdt_info;
wdog->ops = &imx_sc_wdt_ops;
wdog->min_timeout = 1;
wdog->max_timeout = MAX_TIMEOUT;
wdog->parent = dev;
wdog->timeout = DEFAULT_TIMEOUT;
watchdog_init_timeout(wdog, 0, dev);
ret = imx_sc_wdt_set_timeout(wdog, wdog->timeout);
if (ret)
return ret;
watchdog_stop_on_reboot(wdog);
watchdog_stop_on_unregister(wdog);
ret = imx_scu_irq_group_enable(SC_IRQ_GROUP_WDOG,
SC_IRQ_WDOG,
true);
if (ret) {
dev_warn(dev, "Enable irq failed, pretimeout NOT supported\n");
goto register_device;
}
imx_sc_wdd->wdt_notifier.notifier_call = imx_sc_wdt_notify;
ret = imx_scu_irq_register_notifier(&imx_sc_wdd->wdt_notifier);
if (ret) {
imx_scu_irq_group_enable(SC_IRQ_GROUP_WDOG,
SC_IRQ_WDOG,
false);
dev_warn(dev,
"Register irq notifier failed, pretimeout NOT supported\n");
goto register_device;
}
ret = devm_add_action_or_reset(dev, imx_sc_wdt_action,
&imx_sc_wdd->wdt_notifier);
if (!ret)
imx_sc_wdt_info.options |= WDIOF_PRETIMEOUT;
else
dev_warn(dev, "Add action failed, pretimeout NOT supported\n");
register_device:
return devm_watchdog_register_device(dev, wdog);
}
static int __maybe_unused imx_sc_wdt_suspend(struct device *dev)
{
struct imx_sc_wdt_device *imx_sc_wdd = dev_get_drvdata(dev);
if (watchdog_active(&imx_sc_wdd->wdd))
imx_sc_wdt_stop(&imx_sc_wdd->wdd);
return 0;
}
static int __maybe_unused imx_sc_wdt_resume(struct device *dev)
{
struct imx_sc_wdt_device *imx_sc_wdd = dev_get_drvdata(dev);
if (watchdog_active(&imx_sc_wdd->wdd))
imx_sc_wdt_start(&imx_sc_wdd->wdd);
return 0;
}
static SIMPLE_DEV_PM_OPS(imx_sc_wdt_pm_ops,
imx_sc_wdt_suspend, imx_sc_wdt_resume);
static const struct of_device_id imx_sc_wdt_dt_ids[] = {
{ .compatible = "fsl,imx-sc-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_sc_wdt_dt_ids);
static struct platform_driver imx_sc_wdt_driver = {
.probe = imx_sc_wdt_probe,
.driver = {
.name = "imx-sc-wdt",
.of_match_table = imx_sc_wdt_dt_ids,
.pm = &imx_sc_wdt_pm_ops,
},
};
module_platform_driver(imx_sc_wdt_driver);
MODULE_AUTHOR("Robin Gong <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX system controller watchdog driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/imx_sc_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Industrial Computer Source WDT501 driver
*
* (c) Copyright 1996-1997 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>
*
* Release 0.10.
*
* Fixes
* Dave Gregorich : Modularisation and minor bugs
* Alan Cox : Added the watchdog ioctl() stuff
* Alan Cox : Fixed the reboot problem (as noted by
* Matt Crocker).
* Alan Cox : Added wdt= boot option
* Alan Cox : Cleaned up copy/user stuff
* Tim Hockin : Added insmod parameters, comment
* cleanup, parameterized timeout
* Tigran Aivazian : Restructured wdt_init() to handle
* failures
* Joel Becker : Added WDIOC_GET/SETTIMEOUT
* Matt Domsch : Added nowayout module option
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include "wd501p.h"
static unsigned long wdt_is_open;
static char expect_close;
/*
* Module parameters
*/
#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
static int heartbeat = WD_TIMO;
static int wd_heartbeat;
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default="
__MODULE_STRING(WD_TIMO) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/* You must set these - there is no sane way to probe for this board. */
static int io = 0x240;
static int irq = 11;
static DEFINE_SPINLOCK(wdt_lock);
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, "WDT io port (default=0x240)");
module_param_hw(irq, int, irq, 0);
MODULE_PARM_DESC(irq, "WDT irq (default=11)");
/* Support for the Fan Tachometer on the WDT501-P */
static int tachometer;
module_param(tachometer, int, 0);
MODULE_PARM_DESC(tachometer,
"WDT501-P Fan Tachometer support (0=disable, default=0)");
static int type = 500;
module_param(type, int, 0);
MODULE_PARM_DESC(type,
"WDT501-P Card type (500 or 501, default=500)");
/*
* Programming support
*/
static void wdt_ctr_mode(int ctr, int mode)
{
ctr <<= 6;
ctr |= 0x30;
ctr |= (mode << 1);
outb_p(ctr, WDT_CR);
}
static void wdt_ctr_load(int ctr, int val)
{
outb_p(val&0xFF, WDT_COUNT0+ctr);
outb_p(val>>8, WDT_COUNT0+ctr);
}
/**
* wdt_start:
*
* Start the watchdog driver.
*/
static int wdt_start(void)
{
unsigned long flags;
spin_lock_irqsave(&wdt_lock, flags);
inb_p(WDT_DC); /* Disable watchdog */
wdt_ctr_mode(0, 3); /* Program CTR0 for Mode 3:
Square Wave Generator */
wdt_ctr_mode(1, 2); /* Program CTR1 for Mode 2:
Rate Generator */
wdt_ctr_mode(2, 0); /* Program CTR2 for Mode 0:
Pulse on Terminal Count */
wdt_ctr_load(0, 8948); /* Count at 100Hz */
wdt_ctr_load(1, wd_heartbeat); /* Heartbeat */
wdt_ctr_load(2, 65535); /* Length of reset pulse */
outb_p(0, WDT_DC); /* Enable watchdog */
spin_unlock_irqrestore(&wdt_lock, flags);
return 0;
}
/**
* wdt_stop:
*
* Stop the watchdog driver.
*/
static int wdt_stop(void)
{
unsigned long flags;
spin_lock_irqsave(&wdt_lock, flags);
/* Turn the card off */
inb_p(WDT_DC); /* Disable watchdog */
wdt_ctr_load(2, 0); /* 0 length reset pulses now */
spin_unlock_irqrestore(&wdt_lock, flags);
return 0;
}
/**
* wdt_ping:
*
* Reload counter one with the watchdog heartbeat. We don't bother
* reloading the cascade counter.
*/
static void wdt_ping(void)
{
unsigned long flags;
spin_lock_irqsave(&wdt_lock, flags);
/* Write a watchdog value */
inb_p(WDT_DC); /* Disable watchdog */
wdt_ctr_mode(1, 2); /* Re-Program CTR1 for Mode 2:
Rate Generator */
wdt_ctr_load(1, wd_heartbeat); /* Heartbeat */
outb_p(0, WDT_DC); /* Enable watchdog */
spin_unlock_irqrestore(&wdt_lock, flags);
}
/**
* wdt_set_heartbeat:
* @t: the new heartbeat value that needs to be set.
*
* Set a new heartbeat value for the watchdog device. If the heartbeat
* value is incorrect we keep the old value and return -EINVAL. If
* successful we return 0.
*/
static int wdt_set_heartbeat(int t)
{
if (t < 1 || t > 65535)
return -EINVAL;
heartbeat = t;
wd_heartbeat = t * 100;
return 0;
}
/**
* wdt_get_status:
*
* Extract the status information from a WDT watchdog device. There are
* several board variants so we have to know which bits are valid. Some
* bits default to one and some to zero in order to be maximally painful.
*
* we then map the bits onto the status ioctl flags.
*/
static int wdt_get_status(void)
{
unsigned char new_status;
int status = 0;
unsigned long flags;
spin_lock_irqsave(&wdt_lock, flags);
new_status = inb_p(WDT_SR);
spin_unlock_irqrestore(&wdt_lock, flags);
if (new_status & WDC_SR_ISOI0)
status |= WDIOF_EXTERN1;
if (new_status & WDC_SR_ISII1)
status |= WDIOF_EXTERN2;
if (type == 501) {
if (!(new_status & WDC_SR_TGOOD))
status |= WDIOF_OVERHEAT;
if (!(new_status & WDC_SR_PSUOVER))
status |= WDIOF_POWEROVER;
if (!(new_status & WDC_SR_PSUUNDR))
status |= WDIOF_POWERUNDER;
if (tachometer) {
if (!(new_status & WDC_SR_FANGOOD))
status |= WDIOF_FANFAULT;
}
}
return status;
}
/**
* wdt_get_temperature:
*
* Reports the temperature in degrees Fahrenheit. The API is in
* farenheit. It was designed by an imperial measurement luddite.
*/
static int wdt_get_temperature(void)
{
unsigned short c;
unsigned long flags;
spin_lock_irqsave(&wdt_lock, flags);
c = inb_p(WDT_RT);
spin_unlock_irqrestore(&wdt_lock, flags);
return (c * 11 / 15) + 7;
}
static void wdt_decode_501(int status)
{
if (!(status & WDC_SR_TGOOD))
pr_crit("Overheat alarm (%d)\n", inb_p(WDT_RT));
if (!(status & WDC_SR_PSUOVER))
pr_crit("PSU over voltage\n");
if (!(status & WDC_SR_PSUUNDR))
pr_crit("PSU under voltage\n");
}
/**
* wdt_interrupt:
* @irq: Interrupt number
* @dev_id: Unused as we don't allow multiple devices.
*
* Handle an interrupt from the board. These are raised when the status
* map changes in what the board considers an interesting way. That means
* a failure condition occurring.
*/
static irqreturn_t wdt_interrupt(int irq, void *dev_id)
{
/*
* Read the status register see what is up and
* then printk it.
*/
unsigned char status;
spin_lock(&wdt_lock);
status = inb_p(WDT_SR);
pr_crit("WDT status %d\n", status);
if (type == 501) {
wdt_decode_501(status);
if (tachometer) {
if (!(status & WDC_SR_FANGOOD))
pr_crit("Possible fan fault\n");
}
}
if (!(status & WDC_SR_WCCR)) {
#ifdef SOFTWARE_REBOOT
#ifdef ONLY_TESTING
pr_crit("Would Reboot\n");
#else
pr_crit("Initiating system reboot\n");
emergency_restart();
#endif
#else
pr_crit("Reset in 5ms\n");
#endif
}
spin_unlock(&wdt_lock);
return IRQ_HANDLED;
}
/**
* wdt_write:
* @file: file handle to the watchdog
* @buf: buffer to write (unused as data does not matter here
* @count: count of bytes
* @ppos: pointer to the position to write. No seeks allowed
*
* A write to a watchdog device is defined as a keepalive signal. Any
* write of data will do, as we we don't define content meaning.
*/
static ssize_t wdt_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count) {
if (!nowayout) {
size_t i;
/* In case it was set long ago */
expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
wdt_ping();
}
return count;
}
/**
* wdt_ioctl:
* @file: file handle to the device
* @cmd: watchdog command
* @arg: argument pointer
*
* The watchdog API defines a common set of functions for all watchdogs
* according to their available features. We only actually usefully support
* querying capabilities and current status.
*/
static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
int new_heartbeat;
int status;
struct watchdog_info ident = {
.options = WDIOF_SETTIMEOUT|
WDIOF_MAGICCLOSE|
WDIOF_KEEPALIVEPING,
.firmware_version = 1,
.identity = "WDT500/501",
};
/* Add options according to the card we have */
ident.options |= (WDIOF_EXTERN1|WDIOF_EXTERN2);
if (type == 501) {
ident.options |= (WDIOF_OVERHEAT|WDIOF_POWERUNDER|
WDIOF_POWEROVER);
if (tachometer)
ident.options |= WDIOF_FANFAULT;
}
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
status = wdt_get_status();
return put_user(status, p);
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_KEEPALIVE:
wdt_ping();
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_heartbeat, p))
return -EFAULT;
if (wdt_set_heartbeat(new_heartbeat))
return -EINVAL;
wdt_ping();
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(heartbeat, p);
default:
return -ENOTTY;
}
}
/**
* wdt_open:
* @inode: inode of device
* @file: file handle to device
*
* The watchdog device has been opened. The watchdog device is single
* open and on opening we load the counters. Counter zero is a 100Hz
* cascade, into counter 1 which downcounts to reboot. When the counter
* triggers counter 2 downcounts the length of the reset pulse which
* set set to be as long as possible.
*/
static int wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
/*
* Activate
*/
wdt_start();
return stream_open(inode, file);
}
/**
* wdt_release:
* @inode: inode to board
* @file: file handle to board
*
* The watchdog has a configurable API. There is a religious dispute
* between people who want their watchdog to be able to shut down and
* those who want to be sure if the watchdog manager dies the machine
* reboots. In the former case we disable the counters, in the latter
* case you have to open it again very soon.
*/
static int wdt_release(struct inode *inode, struct file *file)
{
if (expect_close == 42) {
wdt_stop();
clear_bit(0, &wdt_is_open);
} else {
pr_crit("WDT device closed unexpectedly. WDT will not stop!\n");
wdt_ping();
}
expect_close = 0;
return 0;
}
/**
* wdt_temp_read:
* @file: file handle to the watchdog board
* @buf: buffer to write 1 byte into
* @count: length of buffer
* @ptr: offset (no seek allowed)
*
* Temp_read reports the temperature in degrees Fahrenheit. The API is in
* farenheit. It was designed by an imperial measurement luddite.
*/
static ssize_t wdt_temp_read(struct file *file, char __user *buf,
size_t count, loff_t *ptr)
{
int temperature = wdt_get_temperature();
if (copy_to_user(buf, &temperature, 1))
return -EFAULT;
return 1;
}
/**
* wdt_temp_open:
* @inode: inode of device
* @file: file handle to device
*
* The temperature device has been opened.
*/
static int wdt_temp_open(struct inode *inode, struct file *file)
{
return stream_open(inode, file);
}
/**
* wdt_temp_release:
* @inode: inode to board
* @file: file handle to board
*
* The temperature device has been closed.
*/
static int wdt_temp_release(struct inode *inode, struct file *file)
{
return 0;
}
/**
* wdt_notify_sys:
* @this: our notifier block
* @code: the event being reported
* @unused: unused
*
* Our notifier is called on system shutdowns. We want to turn the card
* off at reboot otherwise the machine will reboot again during memory
* test or worse yet during the following fsck. This would suck, in fact
* trust me - if it happens it does suck.
*/
static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
wdt_stop();
return NOTIFY_DONE;
}
/*
* Kernel Interfaces
*/
static const struct file_operations wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = wdt_write,
.unlocked_ioctl = wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = wdt_open,
.release = wdt_release,
};
static struct miscdevice wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wdt_fops,
};
static const struct file_operations wdt_temp_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.read = wdt_temp_read,
.open = wdt_temp_open,
.release = wdt_temp_release,
};
static struct miscdevice temp_miscdev = {
.minor = TEMP_MINOR,
.name = "temperature",
.fops = &wdt_temp_fops,
};
/*
* The WDT card needs to learn about soft shutdowns in order to
* turn the timebomb registers off.
*/
static struct notifier_block wdt_notifier = {
.notifier_call = wdt_notify_sys,
};
/**
* wdt_exit:
*
* Unload the watchdog. You cannot do this with any file handles open.
* If your watchdog is set to continue ticking on close and you unload
* it, well it keeps ticking. We won't get the interrupt but the board
* will not touch PC memory so all is fine. You just have to load a new
* module in 60 seconds or reboot.
*/
static void __exit wdt_exit(void)
{
misc_deregister(&wdt_miscdev);
if (type == 501)
misc_deregister(&temp_miscdev);
unregister_reboot_notifier(&wdt_notifier);
free_irq(irq, NULL);
release_region(io, 8);
}
/**
* wdt_init:
*
* Set up the WDT watchdog board. All we have to do is grab the
* resources we require and bitch if anyone beat us to them.
* The open() function will actually kick the board off.
*/
static int __init wdt_init(void)
{
int ret;
if (type != 500 && type != 501) {
pr_err("unknown card type '%d'\n", type);
return -ENODEV;
}
/* Check that the heartbeat value is within it's range;
if not reset to the default */
if (wdt_set_heartbeat(heartbeat)) {
wdt_set_heartbeat(WD_TIMO);
pr_info("heartbeat value must be 0 < heartbeat < 65536, using %d\n",
WD_TIMO);
}
if (!request_region(io, 8, "wdt501p")) {
pr_err("I/O address 0x%04x already in use\n", io);
ret = -EBUSY;
goto out;
}
ret = request_irq(irq, wdt_interrupt, 0, "wdt501p", NULL);
if (ret) {
pr_err("IRQ %d is not free\n", irq);
goto outreg;
}
ret = register_reboot_notifier(&wdt_notifier);
if (ret) {
pr_err("cannot register reboot notifier (err=%d)\n", ret);
goto outirq;
}
if (type == 501) {
ret = misc_register(&temp_miscdev);
if (ret) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
TEMP_MINOR, ret);
goto outrbt;
}
}
ret = misc_register(&wdt_miscdev);
if (ret) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
goto outmisc;
}
pr_info("WDT500/501-P driver 0.10 at 0x%04x (Interrupt %d). heartbeat=%d sec (nowayout=%d)\n",
io, irq, heartbeat, nowayout);
if (type == 501)
pr_info("Fan Tachometer is %s\n",
tachometer ? "Enabled" : "Disabled");
return 0;
outmisc:
if (type == 501)
misc_deregister(&temp_miscdev);
outrbt:
unregister_reboot_notifier(&wdt_notifier);
outirq:
free_irq(irq, NULL);
outreg:
release_region(io, 8);
out:
return ret;
}
module_init(wdt_init);
module_exit(wdt_exit);
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("Driver for ISA ICS watchdog cards (WDT500/501)");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Advantech Embedded Controller Watchdog Driver
*
* This driver supports Advantech products with ITE based Embedded Controller.
* It does not support Advantech products with other ECs or without EC.
*
* Copyright (C) 2022 Advantech Europe B.V.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/watchdog.h>
#define DRIVER_NAME "advantech_ec_wdt"
/* EC IO region */
#define EC_BASE_ADDR 0x299
#define EC_ADDR_EXTENT 2
/* EC minimum IO access delay in ms */
#define EC_MIN_DELAY 10
/* EC interface definitions */
#define EC_ADDR_CMD (EC_BASE_ADDR + 1)
#define EC_ADDR_DATA EC_BASE_ADDR
#define EC_CMD_EC_PROBE 0x30
#define EC_CMD_COMM 0x89
#define EC_CMD_WDT_START 0x28
#define EC_CMD_WDT_STOP 0x29
#define EC_CMD_WDT_RESET 0x2A
#define EC_DAT_EN_DLY_H 0x58
#define EC_DAT_EN_DLY_L 0x59
#define EC_DAT_RST_DLY_H 0x5E
#define EC_DAT_RST_DLY_L 0x5F
#define EC_MAGIC 0x95
/* module parameters */
#define MIN_TIME 1
#define MAX_TIME 6000 /* 100 minutes */
#define DEFAULT_TIME 60
static unsigned int timeout;
static ktime_t ec_timestamp;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout,
"Default Watchdog timer setting (" __MODULE_STRING(DEFAULT_TIME) "s). The range is from " __MODULE_STRING(MIN_TIME) " to " __MODULE_STRING(MAX_TIME) ".");
static void adv_ec_wdt_timing_gate(void)
{
ktime_t time_cur, time_delta;
/* ensure minimum delay between IO accesses*/
time_cur = ktime_get();
time_delta = ktime_to_ms(ktime_sub(time_cur, ec_timestamp));
if (time_delta < EC_MIN_DELAY) {
time_delta = EC_MIN_DELAY - time_delta;
usleep_range(time_delta * 1000, (time_delta + 1) * 1000);
}
ec_timestamp = ktime_get();
}
static void adv_ec_wdt_outb(unsigned char value, unsigned short port)
{
adv_ec_wdt_timing_gate();
outb(value, port);
}
static unsigned char adv_ec_wdt_inb(unsigned short port)
{
adv_ec_wdt_timing_gate();
return inb(port);
}
static int adv_ec_wdt_ping(struct watchdog_device *wdd)
{
adv_ec_wdt_outb(EC_CMD_WDT_RESET, EC_ADDR_CMD);
return 0;
}
static int adv_ec_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t)
{
unsigned int val;
/* scale time to EC 100 ms base */
val = t * 10;
/* reset enable delay, just in case it was set by BIOS etc. */
adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
adv_ec_wdt_outb(EC_DAT_EN_DLY_H, EC_ADDR_DATA);
adv_ec_wdt_outb(0, EC_ADDR_DATA);
adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
adv_ec_wdt_outb(EC_DAT_EN_DLY_L, EC_ADDR_DATA);
adv_ec_wdt_outb(0, EC_ADDR_DATA);
/* set reset delay */
adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
adv_ec_wdt_outb(EC_DAT_RST_DLY_H, EC_ADDR_DATA);
adv_ec_wdt_outb(val >> 8, EC_ADDR_DATA);
adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
adv_ec_wdt_outb(EC_DAT_RST_DLY_L, EC_ADDR_DATA);
adv_ec_wdt_outb(val & 0xFF, EC_ADDR_DATA);
wdd->timeout = t;
return 0;
}
static int adv_ec_wdt_start(struct watchdog_device *wdd)
{
adv_ec_wdt_set_timeout(wdd, wdd->timeout);
adv_ec_wdt_outb(EC_CMD_WDT_START, EC_ADDR_CMD);
return 0;
}
static int adv_ec_wdt_stop(struct watchdog_device *wdd)
{
adv_ec_wdt_outb(EC_CMD_WDT_STOP, EC_ADDR_CMD);
return 0;
}
static const struct watchdog_info adv_ec_wdt_info = {
.identity = DRIVER_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
};
static const struct watchdog_ops adv_ec_wdt_ops = {
.owner = THIS_MODULE,
.start = adv_ec_wdt_start,
.stop = adv_ec_wdt_stop,
.ping = adv_ec_wdt_ping,
.set_timeout = adv_ec_wdt_set_timeout,
};
static struct watchdog_device adv_ec_wdt_dev = {
.info = &adv_ec_wdt_info,
.ops = &adv_ec_wdt_ops,
.min_timeout = MIN_TIME,
.max_timeout = MAX_TIME,
.timeout = DEFAULT_TIME,
};
static int adv_ec_wdt_probe(struct device *dev, unsigned int id)
{
if (!devm_request_region(dev, EC_BASE_ADDR, EC_ADDR_EXTENT, dev_name(dev))) {
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
EC_BASE_ADDR, EC_BASE_ADDR + EC_ADDR_EXTENT);
return -EBUSY;
}
watchdog_init_timeout(&adv_ec_wdt_dev, timeout, dev);
watchdog_stop_on_reboot(&adv_ec_wdt_dev);
watchdog_stop_on_unregister(&adv_ec_wdt_dev);
return devm_watchdog_register_device(dev, &adv_ec_wdt_dev);
}
static struct isa_driver adv_ec_wdt_driver = {
.probe = adv_ec_wdt_probe,
.driver = {
.name = DRIVER_NAME,
},
};
static int __init adv_ec_wdt_init(void)
{
unsigned int val;
/* quick probe for EC */
if (!request_region(EC_BASE_ADDR, EC_ADDR_EXTENT, DRIVER_NAME))
return -EBUSY;
adv_ec_wdt_outb(EC_CMD_EC_PROBE, EC_ADDR_CMD);
val = adv_ec_wdt_inb(EC_ADDR_DATA);
release_region(EC_BASE_ADDR, EC_ADDR_EXTENT);
if (val != EC_MAGIC)
return -ENODEV;
return isa_register_driver(&adv_ec_wdt_driver, 1);
}
static void __exit adv_ec_wdt_exit(void)
{
isa_unregister_driver(&adv_ec_wdt_driver);
}
module_init(adv_ec_wdt_init);
module_exit(adv_ec_wdt_exit);
MODULE_AUTHOR("Thomas Kastner <[email protected]>");
MODULE_DESCRIPTION("Advantech Embedded Controller Watchdog Device Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION("20221019");
MODULE_ALIAS("isa:" DRIVER_NAME);
| linux-master | drivers/watchdog/advantech_ec_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Realtek Otto MIPS platform watchdog
*
* Watchdog timer that will reset the system after timeout, using the selected
* reset mode.
*
* Counter scaling and timeouts:
* - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
* - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
* - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
* Generates an interrupt, WDT cannot be stopped after phase 1
* - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
* Resets the system according to RST_MODE
*/
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/math.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/reboot.h>
#include <linux/watchdog.h>
#define OTTO_WDT_REG_CNTR 0x0
#define OTTO_WDT_CNTR_PING BIT(31)
#define OTTO_WDT_REG_INTR 0x4
#define OTTO_WDT_INTR_PHASE_1 BIT(31)
#define OTTO_WDT_INTR_PHASE_2 BIT(30)
#define OTTO_WDT_REG_CTRL 0x8
#define OTTO_WDT_CTRL_ENABLE BIT(31)
#define OTTO_WDT_CTRL_PRESCALE GENMASK(30, 29)
#define OTTO_WDT_CTRL_PHASE1 GENMASK(26, 22)
#define OTTO_WDT_CTRL_PHASE2 GENMASK(19, 15)
#define OTTO_WDT_CTRL_RST_MODE GENMASK(1, 0)
#define OTTO_WDT_MODE_SOC 0
#define OTTO_WDT_MODE_CPU 1
#define OTTO_WDT_MODE_SOFTWARE 2
#define OTTO_WDT_CTRL_DEFAULT OTTO_WDT_MODE_CPU
#define OTTO_WDT_PRESCALE_MAX 3
/*
* One higher than the max values contained in PHASE{1,2}, since a value of 0
* corresponds to one tick.
*/
#define OTTO_WDT_PHASE_TICKS_MAX 32
/*
* The maximum reset delay is actually 2×32 ticks, but that would require large
* pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout
* to 32 + 1 to ensure small pretimeout values can be configured as expected.
*/
#define OTTO_WDT_TIMEOUT_TICKS_MAX (OTTO_WDT_PHASE_TICKS_MAX + 1)
struct otto_wdt_ctrl {
struct watchdog_device wdev;
struct device *dev;
void __iomem *base;
unsigned int clk_rate_khz;
int irq_phase1;
};
static int otto_wdt_start(struct watchdog_device *wdev)
{
struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
u32 v;
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
v |= OTTO_WDT_CTRL_ENABLE;
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
return 0;
}
static int otto_wdt_stop(struct watchdog_device *wdev)
{
struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
u32 v;
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
v &= ~OTTO_WDT_CTRL_ENABLE;
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
return 0;
}
static int otto_wdt_ping(struct watchdog_device *wdev)
{
struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);
return 0;
}
static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
{
return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);
}
/*
* The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
* the value stored in those fields. This means each phase will run for at least
* one tick, so small values need to be clamped to correctly reflect the timeout.
*/
static inline unsigned int div_round_ticks(unsigned int val, unsigned int tick_duration,
unsigned int min_ticks)
{
return max(min_ticks, DIV_ROUND_UP(val, tick_duration));
}
static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout,
unsigned int pretimeout)
{
struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
unsigned int pretimeout_ms = pretimeout * 1000;
unsigned int timeout_ms = timeout * 1000;
unsigned int prescale_next = 0;
unsigned int phase1_ticks;
unsigned int phase2_ticks;
unsigned int total_ticks;
unsigned int prescale;
unsigned int tick_ms;
u32 v;
do {
prescale = prescale_next;
if (prescale > OTTO_WDT_PRESCALE_MAX)
return -EINVAL;
tick_ms = otto_wdt_tick_ms(ctrl, prescale);
total_ticks = div_round_ticks(timeout_ms, tick_ms, 2);
phase1_ticks = div_round_ticks(timeout_ms - pretimeout_ms, tick_ms, 1);
phase2_ticks = total_ticks - phase1_ticks;
prescale_next++;
} while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX
|| phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX);
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
v &= ~(OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2);
v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);
v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);
v |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale);
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
timeout_ms = total_ticks * tick_ms;
ctrl->wdev.timeout = timeout_ms / 1000;
pretimeout_ms = phase2_ticks * tick_ms;
ctrl->wdev.pretimeout = pretimeout_ms / 1000;
return 0;
}
static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
{
return otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1));
}
static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val)
{
return otto_wdt_determine_timeouts(wdev, wdev->timeout, val);
}
static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
void *data)
{
struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
u32 reset_mode;
u32 v;
disable_irq(ctrl->irq_phase1);
switch (reboot_mode) {
case REBOOT_SOFT:
reset_mode = OTTO_WDT_MODE_SOFTWARE;
break;
case REBOOT_WARM:
reset_mode = OTTO_WDT_MODE_CPU;
break;
default:
reset_mode = OTTO_WDT_MODE_SOC;
break;
}
/* Configure for shortest timeout and wait for reset to occur */
v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
mdelay(3 * otto_wdt_tick_ms(ctrl, 0));
return 0;
}
static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id)
{
struct otto_wdt_ctrl *ctrl = dev_id;
iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);
dev_crit(ctrl->dev, "phase 1 timeout\n");
watchdog_notify_pretimeout(&ctrl->wdev);
return IRQ_HANDLED;
}
static const struct watchdog_ops otto_wdt_ops = {
.owner = THIS_MODULE,
.start = otto_wdt_start,
.stop = otto_wdt_stop,
.ping = otto_wdt_ping,
.set_timeout = otto_wdt_set_timeout,
.set_pretimeout = otto_wdt_set_pretimeout,
.restart = otto_wdt_restart,
};
static const struct watchdog_info otto_wdt_info = {
.identity = "Realtek Otto watchdog timer",
.options = WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE |
WDIOF_SETTIMEOUT |
WDIOF_PRETIMEOUT,
};
static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)
{
struct clk *clk;
clk = devm_clk_get_enabled(ctrl->dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");
ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;
if (ctrl->clk_rate_khz == 0)
return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");
return 0;
}
static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
{
static const char *mode_property = "realtek,reset-mode";
const struct fwnode_handle *node = ctrl->dev->fwnode;
int mode_count;
u32 mode;
u32 v;
if (!node)
return -ENXIO;
mode_count = fwnode_property_string_array_count(node, mode_property);
if (mode_count < 0)
return mode_count;
else if (mode_count == 0)
return 0;
else if (mode_count != 1)
return -EINVAL;
if (fwnode_property_match_string(node, mode_property, "soc") == 0)
mode = OTTO_WDT_MODE_SOC;
else if (fwnode_property_match_string(node, mode_property, "cpu") == 0)
mode = OTTO_WDT_MODE_CPU;
else if (fwnode_property_match_string(node, mode_property, "software") == 0)
mode = OTTO_WDT_MODE_SOFTWARE;
else
return -EINVAL;
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
v &= ~OTTO_WDT_CTRL_RST_MODE;
v |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode);
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
return 0;
}
static int otto_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct otto_wdt_ctrl *ctrl;
unsigned int max_tick_ms;
int ret;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
ctrl->dev = dev;
ctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctrl->base))
return PTR_ERR(ctrl->base);
/* Clear any old interrupts and reset initial state */
iowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2,
ctrl->base + OTTO_WDT_REG_INTR);
iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
ret = otto_wdt_probe_clk(ctrl);
if (ret)
return ret;
ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
if (ctrl->irq_phase1 < 0)
return ctrl->irq_phase1;
ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
"realtek-otto-wdt", ctrl);
if (ret)
return dev_err_probe(dev, ret, "Failed to get IRQ for phase1\n");
ret = otto_wdt_probe_reset_mode(ctrl);
if (ret)
return dev_err_probe(dev, ret, "Invalid reset mode specified\n");
ctrl->wdev.parent = dev;
ctrl->wdev.info = &otto_wdt_info;
ctrl->wdev.ops = &otto_wdt_ops;
/*
* Since pretimeout cannot be disabled, min. timeout is twice the
* subsystem resolution. Max. timeout is ca. 43s at a bus clock of 200MHz.
*/
ctrl->wdev.min_timeout = 2;
max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;
ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);
watchdog_set_drvdata(&ctrl->wdev, ctrl);
watchdog_init_timeout(&ctrl->wdev, 0, dev);
watchdog_stop_on_reboot(&ctrl->wdev);
watchdog_set_restart_priority(&ctrl->wdev, 128);
ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);
if (ret)
return dev_err_probe(dev, ret, "Failed to set timeout\n");
return devm_watchdog_register_device(dev, &ctrl->wdev);
}
static const struct of_device_id otto_wdt_ids[] = {
{ .compatible = "realtek,rtl8380-wdt" },
{ .compatible = "realtek,rtl8390-wdt" },
{ .compatible = "realtek,rtl9300-wdt" },
{ .compatible = "realtek,rtl9310-wdt" },
{ }
};
MODULE_DEVICE_TABLE(of, otto_wdt_ids);
static struct platform_driver otto_wdt_driver = {
.probe = otto_wdt_probe,
.driver = {
.name = "realtek-otto-watchdog",
.of_match_table = otto_wdt_ids,
},
};
module_platform_driver(otto_wdt_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sander Vanheule <[email protected]>");
MODULE_DESCRIPTION("Realtek Otto watchdog timer driver");
| linux-master | drivers/watchdog/realtek_otto_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for watchdog aspect of for Zodiac Inflight Innovations RAVE
* Supervisory Processor(SP) MCU
*
* Copyright (C) 2017 Zodiac Inflight Innovation
*
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/mfd/rave-sp.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/watchdog.h>
enum {
RAVE_SP_RESET_BYTE = 1,
RAVE_SP_RESET_REASON_NORMAL = 0,
RAVE_SP_RESET_DELAY_MS = 500,
};
/**
* struct rave_sp_wdt_variant - RAVE SP watchdog variant
*
* @max_timeout: Largest possible watchdog timeout setting
* @min_timeout: Smallest possible watchdog timeout setting
*
* @configure: Function to send configuration command
* @restart: Function to send "restart" command
*/
struct rave_sp_wdt_variant {
unsigned int max_timeout;
unsigned int min_timeout;
int (*configure)(struct watchdog_device *, bool);
int (*restart)(struct watchdog_device *);
};
/**
* struct rave_sp_wdt - RAVE SP watchdog
*
* @wdd: Underlying watchdog device
* @sp: Pointer to parent RAVE SP device
* @variant: Device specific variant information
* @reboot_notifier: Reboot notifier implementing machine reset
*/
struct rave_sp_wdt {
struct watchdog_device wdd;
struct rave_sp *sp;
const struct rave_sp_wdt_variant *variant;
struct notifier_block reboot_notifier;
};
static struct rave_sp_wdt *to_rave_sp_wdt(struct watchdog_device *wdd)
{
return container_of(wdd, struct rave_sp_wdt, wdd);
}
static int rave_sp_wdt_exec(struct watchdog_device *wdd, void *data,
size_t data_size)
{
return rave_sp_exec(to_rave_sp_wdt(wdd)->sp,
data, data_size, NULL, 0);
}
static int rave_sp_wdt_legacy_configure(struct watchdog_device *wdd, bool on)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_SW_WDT,
[1] = 0,
[2] = 0,
[3] = on,
[4] = on ? wdd->timeout : 0,
};
return rave_sp_wdt_exec(wdd, cmd, sizeof(cmd));
}
static int rave_sp_wdt_rdu_configure(struct watchdog_device *wdd, bool on)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_SW_WDT,
[1] = 0,
[2] = on,
[3] = (u8)wdd->timeout,
[4] = (u8)(wdd->timeout >> 8),
};
return rave_sp_wdt_exec(wdd, cmd, sizeof(cmd));
}
/**
* rave_sp_wdt_configure - Configure watchdog device
*
* @wdd: Device to configure
* @on: Desired state of the watchdog timer (ON/OFF)
*
* This function configures two aspects of the watchdog timer:
*
* - Wheither it is ON or OFF
* - Its timeout duration
*
* with first aspect specified via function argument and second via
* the value of 'wdd->timeout'.
*/
static int rave_sp_wdt_configure(struct watchdog_device *wdd, bool on)
{
return to_rave_sp_wdt(wdd)->variant->configure(wdd, on);
}
static int rave_sp_wdt_legacy_restart(struct watchdog_device *wdd)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_RESET,
[1] = 0,
[2] = RAVE_SP_RESET_BYTE
};
return rave_sp_wdt_exec(wdd, cmd, sizeof(cmd));
}
static int rave_sp_wdt_rdu_restart(struct watchdog_device *wdd)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_RESET,
[1] = 0,
[2] = RAVE_SP_RESET_BYTE,
[3] = RAVE_SP_RESET_REASON_NORMAL
};
return rave_sp_wdt_exec(wdd, cmd, sizeof(cmd));
}
static int rave_sp_wdt_reboot_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
/*
* Restart handler is called in atomic context which means we
* can't communicate to SP via UART. Luckily for use SP will
* wait 500ms before actually resetting us, so we ask it to do
* so here and let the rest of the system go on wrapping
* things up.
*/
if (action == SYS_DOWN || action == SYS_HALT) {
struct rave_sp_wdt *sp_wd =
container_of(nb, struct rave_sp_wdt, reboot_notifier);
const int ret = sp_wd->variant->restart(&sp_wd->wdd);
if (ret < 0)
dev_err(sp_wd->wdd.parent,
"Failed to issue restart command (%d)", ret);
return NOTIFY_OK;
}
return NOTIFY_DONE;
}
static int rave_sp_wdt_restart(struct watchdog_device *wdd,
unsigned long action, void *data)
{
/*
* The actual work was done by reboot notifier above. SP
* firmware waits 500 ms before issuing reset, so let's hang
* here for twice that delay and hopefuly we'd never reach
* the return statement.
*/
mdelay(2 * RAVE_SP_RESET_DELAY_MS);
return -EIO;
}
static int rave_sp_wdt_start(struct watchdog_device *wdd)
{
int ret;
ret = rave_sp_wdt_configure(wdd, true);
if (!ret)
set_bit(WDOG_HW_RUNNING, &wdd->status);
return ret;
}
static int rave_sp_wdt_stop(struct watchdog_device *wdd)
{
return rave_sp_wdt_configure(wdd, false);
}
static int rave_sp_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->timeout = timeout;
return rave_sp_wdt_configure(wdd, watchdog_active(wdd));
}
static int rave_sp_wdt_ping(struct watchdog_device *wdd)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_PET_WDT,
[1] = 0,
};
return rave_sp_wdt_exec(wdd, cmd, sizeof(cmd));
}
static const struct watchdog_info rave_sp_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "RAVE SP Watchdog",
};
static const struct watchdog_ops rave_sp_wdt_ops = {
.owner = THIS_MODULE,
.start = rave_sp_wdt_start,
.stop = rave_sp_wdt_stop,
.ping = rave_sp_wdt_ping,
.set_timeout = rave_sp_wdt_set_timeout,
.restart = rave_sp_wdt_restart,
};
static const struct rave_sp_wdt_variant rave_sp_wdt_legacy = {
.max_timeout = 255,
.min_timeout = 1,
.configure = rave_sp_wdt_legacy_configure,
.restart = rave_sp_wdt_legacy_restart,
};
static const struct rave_sp_wdt_variant rave_sp_wdt_rdu = {
.max_timeout = 180,
.min_timeout = 60,
.configure = rave_sp_wdt_rdu_configure,
.restart = rave_sp_wdt_rdu_restart,
};
static const struct of_device_id rave_sp_wdt_of_match[] = {
{
.compatible = "zii,rave-sp-watchdog-legacy",
.data = &rave_sp_wdt_legacy,
},
{
.compatible = "zii,rave-sp-watchdog",
.data = &rave_sp_wdt_rdu,
},
{ /* sentinel */ }
};
static int rave_sp_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct rave_sp_wdt *sp_wd;
struct nvmem_cell *cell;
__le16 timeout = 0;
int ret;
sp_wd = devm_kzalloc(dev, sizeof(*sp_wd), GFP_KERNEL);
if (!sp_wd)
return -ENOMEM;
sp_wd->variant = of_device_get_match_data(dev);
sp_wd->sp = dev_get_drvdata(dev->parent);
wdd = &sp_wd->wdd;
wdd->parent = dev;
wdd->info = &rave_sp_wdt_info;
wdd->ops = &rave_sp_wdt_ops;
wdd->min_timeout = sp_wd->variant->min_timeout;
wdd->max_timeout = sp_wd->variant->max_timeout;
wdd->status = WATCHDOG_NOWAYOUT_INIT_STATUS;
wdd->timeout = 60;
cell = nvmem_cell_get(dev, "wdt-timeout");
if (!IS_ERR(cell)) {
size_t len;
void *value = nvmem_cell_read(cell, &len);
if (!IS_ERR(value)) {
memcpy(&timeout, value, min(len, sizeof(timeout)));
kfree(value);
}
nvmem_cell_put(cell);
}
watchdog_init_timeout(wdd, le16_to_cpu(timeout), dev);
watchdog_set_restart_priority(wdd, 255);
watchdog_stop_on_unregister(wdd);
sp_wd->reboot_notifier.notifier_call = rave_sp_wdt_reboot_notifier;
ret = devm_register_reboot_notifier(dev, &sp_wd->reboot_notifier);
if (ret) {
dev_err(dev, "Failed to register reboot notifier\n");
return ret;
}
/*
* We don't know if watchdog is running now. To be sure, let's
* start it and depend on watchdog core to ping it
*/
wdd->max_hw_heartbeat_ms = wdd->max_timeout * 1000;
ret = rave_sp_wdt_start(wdd);
if (ret) {
dev_err(dev, "Watchdog didn't start\n");
return ret;
}
ret = devm_watchdog_register_device(dev, wdd);
if (ret) {
rave_sp_wdt_stop(wdd);
return ret;
}
return 0;
}
static struct platform_driver rave_sp_wdt_driver = {
.probe = rave_sp_wdt_probe,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = rave_sp_wdt_of_match,
},
};
module_platform_driver(rave_sp_wdt_driver);
MODULE_DEVICE_TABLE(of, rave_sp_wdt_of_match);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Vostrikov <[email protected]>");
MODULE_AUTHOR("Nikita Yushchenko <[email protected]>");
MODULE_AUTHOR("Andrey Smirnov <[email protected]>");
MODULE_DESCRIPTION("RAVE SP Watchdog driver");
MODULE_ALIAS("platform:rave-sp-watchdog");
| linux-master | drivers/watchdog/rave-sp-wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Meson Watchdog Driver
*
* Copyright (c) 2014 Carlo Caione
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#define DRV_NAME "meson_wdt"
#define MESON_WDT_TC 0x00
#define MESON_WDT_DC_RESET (3 << 24)
#define MESON_WDT_RESET 0x04
#define MESON_WDT_TIMEOUT 30
#define MESON_WDT_MIN_TIMEOUT 1
#define MESON_SEC_TO_TC(s, c) ((s) * (c))
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;
struct meson_wdt_data {
unsigned int enable;
unsigned int terminal_count_mask;
unsigned int count_unit;
};
static struct meson_wdt_data meson6_wdt_data = {
.enable = BIT(22),
.terminal_count_mask = 0x3fffff,
.count_unit = 100000, /* 10 us */
};
static struct meson_wdt_data meson8b_wdt_data = {
.enable = BIT(19),
.terminal_count_mask = 0xffff,
.count_unit = 7812, /* 128 us */
};
struct meson_wdt_dev {
struct watchdog_device wdt_dev;
void __iomem *wdt_base;
const struct meson_wdt_data *data;
};
static int meson_wdt_restart(struct watchdog_device *wdt_dev,
unsigned long action, void *data)
{
struct meson_wdt_dev *meson_wdt = watchdog_get_drvdata(wdt_dev);
u32 tc_reboot = MESON_WDT_DC_RESET;
tc_reboot |= meson_wdt->data->enable;
while (1) {
writel(tc_reboot, meson_wdt->wdt_base + MESON_WDT_TC);
mdelay(5);
}
return 0;
}
static int meson_wdt_ping(struct watchdog_device *wdt_dev)
{
struct meson_wdt_dev *meson_wdt = watchdog_get_drvdata(wdt_dev);
writel(0, meson_wdt->wdt_base + MESON_WDT_RESET);
return 0;
}
static void meson_wdt_change_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
struct meson_wdt_dev *meson_wdt = watchdog_get_drvdata(wdt_dev);
u32 reg;
reg = readl(meson_wdt->wdt_base + MESON_WDT_TC);
reg &= ~meson_wdt->data->terminal_count_mask;
reg |= MESON_SEC_TO_TC(timeout, meson_wdt->data->count_unit);
writel(reg, meson_wdt->wdt_base + MESON_WDT_TC);
}
static int meson_wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int timeout)
{
wdt_dev->timeout = timeout;
meson_wdt_change_timeout(wdt_dev, timeout);
meson_wdt_ping(wdt_dev);
return 0;
}
static int meson_wdt_stop(struct watchdog_device *wdt_dev)
{
struct meson_wdt_dev *meson_wdt = watchdog_get_drvdata(wdt_dev);
u32 reg;
reg = readl(meson_wdt->wdt_base + MESON_WDT_TC);
reg &= ~meson_wdt->data->enable;
writel(reg, meson_wdt->wdt_base + MESON_WDT_TC);
return 0;
}
static int meson_wdt_start(struct watchdog_device *wdt_dev)
{
struct meson_wdt_dev *meson_wdt = watchdog_get_drvdata(wdt_dev);
u32 reg;
meson_wdt_change_timeout(wdt_dev, meson_wdt->wdt_dev.timeout);
meson_wdt_ping(wdt_dev);
reg = readl(meson_wdt->wdt_base + MESON_WDT_TC);
reg |= meson_wdt->data->enable;
writel(reg, meson_wdt->wdt_base + MESON_WDT_TC);
return 0;
}
static const struct watchdog_info meson_wdt_info = {
.identity = DRV_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops meson_wdt_ops = {
.owner = THIS_MODULE,
.start = meson_wdt_start,
.stop = meson_wdt_stop,
.ping = meson_wdt_ping,
.set_timeout = meson_wdt_set_timeout,
.restart = meson_wdt_restart,
};
static const struct of_device_id meson_wdt_dt_ids[] = {
{ .compatible = "amlogic,meson6-wdt", .data = &meson6_wdt_data },
{ .compatible = "amlogic,meson8-wdt", .data = &meson6_wdt_data },
{ .compatible = "amlogic,meson8b-wdt", .data = &meson8b_wdt_data },
{ .compatible = "amlogic,meson8m2-wdt", .data = &meson8b_wdt_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, meson_wdt_dt_ids);
static int meson_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct meson_wdt_dev *meson_wdt;
int err;
meson_wdt = devm_kzalloc(dev, sizeof(*meson_wdt), GFP_KERNEL);
if (!meson_wdt)
return -ENOMEM;
meson_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(meson_wdt->wdt_base))
return PTR_ERR(meson_wdt->wdt_base);
meson_wdt->data = device_get_match_data(dev);
meson_wdt->wdt_dev.parent = dev;
meson_wdt->wdt_dev.info = &meson_wdt_info;
meson_wdt->wdt_dev.ops = &meson_wdt_ops;
meson_wdt->wdt_dev.max_timeout =
meson_wdt->data->terminal_count_mask / meson_wdt->data->count_unit;
meson_wdt->wdt_dev.min_timeout = MESON_WDT_MIN_TIMEOUT;
meson_wdt->wdt_dev.timeout = min_t(unsigned int,
MESON_WDT_TIMEOUT,
meson_wdt->wdt_dev.max_timeout);
watchdog_set_drvdata(&meson_wdt->wdt_dev, meson_wdt);
watchdog_init_timeout(&meson_wdt->wdt_dev, timeout, dev);
watchdog_set_nowayout(&meson_wdt->wdt_dev, nowayout);
watchdog_set_restart_priority(&meson_wdt->wdt_dev, 128);
meson_wdt_stop(&meson_wdt->wdt_dev);
watchdog_stop_on_reboot(&meson_wdt->wdt_dev);
err = devm_watchdog_register_device(dev, &meson_wdt->wdt_dev);
if (err)
return err;
dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
meson_wdt->wdt_dev.timeout, nowayout);
return 0;
}
static struct platform_driver meson_wdt_driver = {
.probe = meson_wdt_probe,
.driver = {
.name = DRV_NAME,
.of_match_table = meson_wdt_dt_ids,
},
};
module_platform_driver(meson_wdt_driver);
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Carlo Caione <[email protected]>");
MODULE_DESCRIPTION("Meson Watchdog Timer Driver");
| linux-master | drivers/watchdog/meson_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* SoftDog: A Software Watchdog Device
*
* (c) Copyright 1996 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>
*
* Software only watchdog driver. Unlike its big brother the WDT501P
* driver this won't always recover a failed machine.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/hrtimer.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/reboot.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/workqueue.h>
#define TIMER_MARGIN 60 /* Default is 60 seconds */
static unsigned int soft_margin = TIMER_MARGIN; /* in seconds */
module_param(soft_margin, uint, 0);
MODULE_PARM_DESC(soft_margin,
"Watchdog soft_margin in seconds. (0 < soft_margin < 65536, default="
__MODULE_STRING(TIMER_MARGIN) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int soft_noboot;
module_param(soft_noboot, int, 0);
MODULE_PARM_DESC(soft_noboot,
"Softdog action, set to 1 to ignore reboots, 0 to reboot (default=0)");
static int soft_panic;
module_param(soft_panic, int, 0);
MODULE_PARM_DESC(soft_panic,
"Softdog action, set to 1 to panic, 0 to reboot (default=0)");
static char *soft_reboot_cmd;
module_param(soft_reboot_cmd, charp, 0000);
MODULE_PARM_DESC(soft_reboot_cmd,
"Set reboot command. Emergency reboot takes place if unset");
static bool soft_active_on_boot;
module_param(soft_active_on_boot, bool, 0000);
MODULE_PARM_DESC(soft_active_on_boot,
"Set to true to active Softdog on boot (default=false)");
static struct hrtimer softdog_ticktock;
static struct hrtimer softdog_preticktock;
static int reboot_kthread_fn(void *data)
{
kernel_restart(soft_reboot_cmd);
return -EPERM; /* Should not reach here */
}
static void reboot_work_fn(struct work_struct *unused)
{
kthread_run(reboot_kthread_fn, NULL, "softdog_reboot");
}
static enum hrtimer_restart softdog_fire(struct hrtimer *timer)
{
static bool soft_reboot_fired;
module_put(THIS_MODULE);
if (soft_noboot) {
pr_crit("Triggered - Reboot ignored\n");
} else if (soft_panic) {
pr_crit("Initiating panic\n");
panic("Software Watchdog Timer expired");
} else {
pr_crit("Initiating system reboot\n");
if (!soft_reboot_fired && soft_reboot_cmd != NULL) {
static DECLARE_WORK(reboot_work, reboot_work_fn);
/*
* The 'kernel_restart' is a 'might-sleep' operation.
* Also, executing it in system-wide workqueues blocks
* any driver from using the same workqueue in its
* shutdown callback function. Thus, we should execute
* the 'kernel_restart' in a standalone kernel thread.
* But since starting a kernel thread is also a
* 'might-sleep' operation, so the 'reboot_work' is
* required as a launcher of the kernel thread.
*
* After request the reboot, restart the timer to
* schedule an 'emergency_restart' reboot after
* 'TIMER_MARGIN' seconds. It's because if the softdog
* hangs, it might be because of scheduling issues. And
* if that is the case, both 'schedule_work' and
* 'kernel_restart' may possibly be malfunctional at the
* same time.
*/
soft_reboot_fired = true;
schedule_work(&reboot_work);
hrtimer_add_expires_ns(timer,
(u64)TIMER_MARGIN * NSEC_PER_SEC);
return HRTIMER_RESTART;
}
emergency_restart();
pr_crit("Reboot didn't ?????\n");
}
return HRTIMER_NORESTART;
}
static struct watchdog_device softdog_dev;
static enum hrtimer_restart softdog_pretimeout(struct hrtimer *timer)
{
watchdog_notify_pretimeout(&softdog_dev);
return HRTIMER_NORESTART;
}
static int softdog_ping(struct watchdog_device *w)
{
if (!hrtimer_active(&softdog_ticktock))
__module_get(THIS_MODULE);
hrtimer_start(&softdog_ticktock, ktime_set(w->timeout, 0),
HRTIMER_MODE_REL);
if (IS_ENABLED(CONFIG_SOFT_WATCHDOG_PRETIMEOUT)) {
if (w->pretimeout)
hrtimer_start(&softdog_preticktock,
ktime_set(w->timeout - w->pretimeout, 0),
HRTIMER_MODE_REL);
else
hrtimer_cancel(&softdog_preticktock);
}
return 0;
}
static int softdog_stop(struct watchdog_device *w)
{
if (hrtimer_cancel(&softdog_ticktock))
module_put(THIS_MODULE);
if (IS_ENABLED(CONFIG_SOFT_WATCHDOG_PRETIMEOUT))
hrtimer_cancel(&softdog_preticktock);
return 0;
}
static struct watchdog_info softdog_info = {
.identity = "Software Watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops softdog_ops = {
.owner = THIS_MODULE,
.start = softdog_ping,
.stop = softdog_stop,
};
static struct watchdog_device softdog_dev = {
.info = &softdog_info,
.ops = &softdog_ops,
.min_timeout = 1,
.max_timeout = 65535,
.timeout = TIMER_MARGIN,
};
static int __init softdog_init(void)
{
int ret;
watchdog_init_timeout(&softdog_dev, soft_margin, NULL);
watchdog_set_nowayout(&softdog_dev, nowayout);
watchdog_stop_on_reboot(&softdog_dev);
hrtimer_init(&softdog_ticktock, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
softdog_ticktock.function = softdog_fire;
if (IS_ENABLED(CONFIG_SOFT_WATCHDOG_PRETIMEOUT)) {
softdog_info.options |= WDIOF_PRETIMEOUT;
hrtimer_init(&softdog_preticktock, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
softdog_preticktock.function = softdog_pretimeout;
}
if (soft_active_on_boot)
softdog_ping(&softdog_dev);
ret = watchdog_register_device(&softdog_dev);
if (ret)
return ret;
pr_info("initialized. soft_noboot=%d soft_margin=%d sec soft_panic=%d (nowayout=%d)\n",
soft_noboot, softdog_dev.timeout, soft_panic, nowayout);
pr_info(" soft_reboot_cmd=%s soft_active_on_boot=%d\n",
soft_reboot_cmd ?: "<not set>", soft_active_on_boot);
return 0;
}
module_init(softdog_init);
static void __exit softdog_exit(void)
{
watchdog_unregister_device(&softdog_dev);
}
module_exit(softdog_exit);
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("Software Watchdog Device Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/softdog.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015-2016 Mentor Graphics
*/
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/watchdog.h>
#include "watchdog_pretimeout.h"
/**
* pretimeout_noop - No operation on watchdog pretimeout event
* @wdd - watchdog_device
*
* This function prints a message about pretimeout to kernel log.
*/
static void pretimeout_noop(struct watchdog_device *wdd)
{
pr_alert("watchdog%d: pretimeout event\n", wdd->id);
}
static struct watchdog_governor watchdog_gov_noop = {
.name = "noop",
.pretimeout = pretimeout_noop,
};
static int __init watchdog_gov_noop_register(void)
{
return watchdog_register_governor(&watchdog_gov_noop);
}
static void __exit watchdog_gov_noop_unregister(void)
{
watchdog_unregister_governor(&watchdog_gov_noop);
}
module_init(watchdog_gov_noop_register);
module_exit(watchdog_gov_noop_unregister);
MODULE_AUTHOR("Vladimir Zapolskiy <[email protected]>");
MODULE_DESCRIPTION("Panic watchdog pretimeout governor");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/pretimeout_noop.c |
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Apple SoC Watchdog driver
*
* Copyright (C) The Asahi Linux Contributors
*/
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/limits.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
/*
* Apple Watchdog MMIO registers
*
* This HW block has three separate watchdogs. WD0 resets the machine
* to recovery mode and is not very useful for us. WD1 and WD2 trigger a normal
* machine reset. WD0 additionally supports a configurable interrupt.
* This information can be used to implement pretimeout support at a later time.
*
* APPLE_WDT_WDx_CUR_TIME is a simple counter incremented for each tick of the
* reference clock. It can also be overwritten to any value.
* Whenever APPLE_WDT_CTRL_RESET_EN is set in APPLE_WDT_WDx_CTRL and
* APPLE_WDT_WDx_CUR_TIME >= APPLE_WDT_WDx_BITE_TIME the entire machine is
* reset.
* Whenever APPLE_WDT_CTRL_IRQ_EN is set and APPLE_WDTx_WD1_CUR_TIME >=
* APPLE_WDTx_WD1_BARK_TIME an interrupt is triggered and
* APPLE_WDT_CTRL_IRQ_STATUS is set. The interrupt can be cleared by writing
* 1 to APPLE_WDT_CTRL_IRQ_STATUS.
*/
#define APPLE_WDT_WD0_CUR_TIME 0x00
#define APPLE_WDT_WD0_BITE_TIME 0x04
#define APPLE_WDT_WD0_BARK_TIME 0x08
#define APPLE_WDT_WD0_CTRL 0x0c
#define APPLE_WDT_WD1_CUR_TIME 0x10
#define APPLE_WDT_WD1_BITE_TIME 0x14
#define APPLE_WDT_WD1_CTRL 0x1c
#define APPLE_WDT_WD2_CUR_TIME 0x20
#define APPLE_WDT_WD2_BITE_TIME 0x24
#define APPLE_WDT_WD2_CTRL 0x2c
#define APPLE_WDT_CTRL_IRQ_EN BIT(0)
#define APPLE_WDT_CTRL_IRQ_STATUS BIT(1)
#define APPLE_WDT_CTRL_RESET_EN BIT(2)
#define APPLE_WDT_TIMEOUT_DEFAULT 30
struct apple_wdt {
struct watchdog_device wdd;
void __iomem *regs;
unsigned long clk_rate;
};
static struct apple_wdt *to_apple_wdt(struct watchdog_device *wdd)
{
return container_of(wdd, struct apple_wdt, wdd);
}
static int apple_wdt_start(struct watchdog_device *wdd)
{
struct apple_wdt *wdt = to_apple_wdt(wdd);
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
return 0;
}
static int apple_wdt_stop(struct watchdog_device *wdd)
{
struct apple_wdt *wdt = to_apple_wdt(wdd);
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL);
return 0;
}
static int apple_wdt_ping(struct watchdog_device *wdd)
{
struct apple_wdt *wdt = to_apple_wdt(wdd);
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
return 0;
}
static int apple_wdt_set_timeout(struct watchdog_device *wdd, unsigned int s)
{
struct apple_wdt *wdt = to_apple_wdt(wdd);
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
wdd->timeout = s;
return 0;
}
static unsigned int apple_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct apple_wdt *wdt = to_apple_wdt(wdd);
u32 cur_time, reset_time;
cur_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
reset_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_BITE_TIME);
return (reset_time - cur_time) / wdt->clk_rate;
}
static int apple_wdt_restart(struct watchdog_device *wdd, unsigned long mode,
void *cmd)
{
struct apple_wdt *wdt = to_apple_wdt(wdd);
writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
/*
* Flush writes and then wait for the SoC to reset. Even though the
* reset is queued almost immediately experiments have shown that it
* can take up to ~20-25ms until the SoC is actually reset. Just wait
* 50ms here to be safe.
*/
(void)readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
mdelay(50);
return 0;
}
static struct watchdog_ops apple_wdt_ops = {
.owner = THIS_MODULE,
.start = apple_wdt_start,
.stop = apple_wdt_stop,
.ping = apple_wdt_ping,
.set_timeout = apple_wdt_set_timeout,
.get_timeleft = apple_wdt_get_timeleft,
.restart = apple_wdt_restart,
};
static struct watchdog_info apple_wdt_info = {
.identity = "Apple SoC Watchdog",
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
};
static int apple_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct apple_wdt *wdt;
struct clk *clk;
u32 wdt_ctrl;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->regs))
return PTR_ERR(wdt->regs);
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
wdt->clk_rate = clk_get_rate(clk);
if (!wdt->clk_rate)
return -EINVAL;
wdt->wdd.ops = &apple_wdt_ops;
wdt->wdd.info = &apple_wdt_info;
wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate;
wdt->wdd.timeout = APPLE_WDT_TIMEOUT_DEFAULT;
wdt_ctrl = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CTRL);
if (wdt_ctrl & APPLE_WDT_CTRL_RESET_EN)
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
watchdog_init_timeout(&wdt->wdd, 0, dev);
apple_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
watchdog_stop_on_unregister(&wdt->wdd);
watchdog_set_restart_priority(&wdt->wdd, 128);
return devm_watchdog_register_device(dev, &wdt->wdd);
}
static const struct of_device_id apple_wdt_of_match[] = {
{ .compatible = "apple,wdt" },
{},
};
MODULE_DEVICE_TABLE(of, apple_wdt_of_match);
static struct platform_driver apple_wdt_driver = {
.driver = {
.name = "apple-watchdog",
.of_match_table = apple_wdt_of_match,
},
.probe = apple_wdt_probe,
};
module_platform_driver(apple_wdt_driver);
MODULE_DESCRIPTION("Apple SoC watchdog driver");
MODULE_AUTHOR("Sven Peter <[email protected]>");
MODULE_LICENSE("Dual MIT/GPL");
| linux-master | drivers/watchdog/apple_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* ST's LPC Watchdog
*
* Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
*
* Author: David Paris <[email protected]> for STMicroelectronics
* Lee Jones <[email protected]> for STMicroelectronics
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
#include <dt-bindings/mfd/st-lpc.h>
/* Low Power Alarm */
#define LPC_LPA_LSB_OFF 0x410
#define LPC_LPA_START_OFF 0x418
/* LPC as WDT */
#define LPC_WDT_OFF 0x510
static struct watchdog_device st_wdog_dev;
struct st_wdog_syscfg {
unsigned int reset_type_reg;
unsigned int reset_type_mask;
unsigned int enable_reg;
unsigned int enable_mask;
};
struct st_wdog {
void __iomem *base;
struct device *dev;
struct regmap *regmap;
struct st_wdog_syscfg *syscfg;
struct clk *clk;
unsigned long clkrate;
bool warm_reset;
};
static struct st_wdog_syscfg stih407_syscfg = {
.enable_reg = 0x204,
.enable_mask = BIT(19),
};
static const struct of_device_id st_wdog_match[] = {
{
.compatible = "st,stih407-lpc",
.data = &stih407_syscfg,
},
{},
};
MODULE_DEVICE_TABLE(of, st_wdog_match);
static void st_wdog_setup(struct st_wdog *st_wdog, bool enable)
{
/* Type of watchdog reset - 0: Cold 1: Warm */
if (st_wdog->syscfg->reset_type_reg)
regmap_update_bits(st_wdog->regmap,
st_wdog->syscfg->reset_type_reg,
st_wdog->syscfg->reset_type_mask,
st_wdog->warm_reset);
/* Mask/unmask watchdog reset */
regmap_update_bits(st_wdog->regmap,
st_wdog->syscfg->enable_reg,
st_wdog->syscfg->enable_mask,
enable ? 0 : st_wdog->syscfg->enable_mask);
}
static void st_wdog_load_timer(struct st_wdog *st_wdog, unsigned int timeout)
{
unsigned long clkrate = st_wdog->clkrate;
writel_relaxed(timeout * clkrate, st_wdog->base + LPC_LPA_LSB_OFF);
writel_relaxed(1, st_wdog->base + LPC_LPA_START_OFF);
}
static int st_wdog_start(struct watchdog_device *wdd)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(wdd);
writel_relaxed(1, st_wdog->base + LPC_WDT_OFF);
return 0;
}
static int st_wdog_stop(struct watchdog_device *wdd)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(wdd);
writel_relaxed(0, st_wdog->base + LPC_WDT_OFF);
return 0;
}
static int st_wdog_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(wdd);
wdd->timeout = timeout;
st_wdog_load_timer(st_wdog, timeout);
return 0;
}
static int st_wdog_keepalive(struct watchdog_device *wdd)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(wdd);
st_wdog_load_timer(st_wdog, wdd->timeout);
return 0;
}
static const struct watchdog_info st_wdog_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "ST LPC WDT",
};
static const struct watchdog_ops st_wdog_ops = {
.owner = THIS_MODULE,
.start = st_wdog_start,
.stop = st_wdog_stop,
.ping = st_wdog_keepalive,
.set_timeout = st_wdog_set_timeout,
};
static struct watchdog_device st_wdog_dev = {
.info = &st_wdog_info,
.ops = &st_wdog_ops,
};
static void st_clk_disable_unprepare(void *data)
{
clk_disable_unprepare(data);
}
static int st_wdog_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *match;
struct device_node *np = dev->of_node;
struct st_wdog *st_wdog;
struct regmap *regmap;
struct clk *clk;
void __iomem *base;
uint32_t mode;
int ret;
ret = of_property_read_u32(np, "st,lpc-mode", &mode);
if (ret) {
dev_err(dev, "An LPC mode must be provided\n");
return -EINVAL;
}
/* LPC can either run as a Clocksource or in RTC or WDT mode */
if (mode != ST_LPC_MODE_WDT)
return -ENODEV;
st_wdog = devm_kzalloc(dev, sizeof(*st_wdog), GFP_KERNEL);
if (!st_wdog)
return -ENOMEM;
match = of_match_device(st_wdog_match, dev);
if (!match) {
dev_err(dev, "Couldn't match device\n");
return -ENODEV;
}
st_wdog->syscfg = (struct st_wdog_syscfg *)match->data;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(regmap)) {
dev_err(dev, "No syscfg phandle specified\n");
return PTR_ERR(regmap);
}
clk = devm_clk_get(dev, NULL);
if (IS_ERR(clk)) {
dev_err(dev, "Unable to request clock\n");
return PTR_ERR(clk);
}
st_wdog->dev = dev;
st_wdog->base = base;
st_wdog->clk = clk;
st_wdog->regmap = regmap;
st_wdog->warm_reset = of_property_read_bool(np, "st,warm_reset");
st_wdog->clkrate = clk_get_rate(st_wdog->clk);
if (!st_wdog->clkrate) {
dev_err(dev, "Unable to fetch clock rate\n");
return -EINVAL;
}
st_wdog_dev.max_timeout = 0xFFFFFFFF / st_wdog->clkrate;
st_wdog_dev.parent = dev;
ret = clk_prepare_enable(clk);
if (ret) {
dev_err(dev, "Unable to enable clock\n");
return ret;
}
ret = devm_add_action_or_reset(dev, st_clk_disable_unprepare, clk);
if (ret)
return ret;
watchdog_set_drvdata(&st_wdog_dev, st_wdog);
watchdog_set_nowayout(&st_wdog_dev, WATCHDOG_NOWAYOUT);
/* Init Watchdog timeout with value in DT */
ret = watchdog_init_timeout(&st_wdog_dev, 0, dev);
if (ret)
return ret;
ret = devm_watchdog_register_device(dev, &st_wdog_dev);
if (ret)
return ret;
st_wdog_setup(st_wdog, true);
dev_info(dev, "LPC Watchdog driver registered, reset type is %s",
st_wdog->warm_reset ? "warm" : "cold");
return ret;
}
static void st_wdog_remove(struct platform_device *pdev)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(&st_wdog_dev);
st_wdog_setup(st_wdog, false);
}
static int st_wdog_suspend(struct device *dev)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(&st_wdog_dev);
if (watchdog_active(&st_wdog_dev))
st_wdog_stop(&st_wdog_dev);
st_wdog_setup(st_wdog, false);
clk_disable(st_wdog->clk);
return 0;
}
static int st_wdog_resume(struct device *dev)
{
struct st_wdog *st_wdog = watchdog_get_drvdata(&st_wdog_dev);
int ret;
ret = clk_enable(st_wdog->clk);
if (ret) {
dev_err(dev, "Unable to re-enable clock\n");
watchdog_unregister_device(&st_wdog_dev);
clk_unprepare(st_wdog->clk);
return ret;
}
st_wdog_setup(st_wdog, true);
if (watchdog_active(&st_wdog_dev)) {
st_wdog_load_timer(st_wdog, st_wdog_dev.timeout);
st_wdog_start(&st_wdog_dev);
}
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(st_wdog_pm_ops,
st_wdog_suspend, st_wdog_resume);
static struct platform_driver st_wdog_driver = {
.driver = {
.name = "st-lpc-wdt",
.pm = pm_sleep_ptr(&st_wdog_pm_ops),
.of_match_table = st_wdog_match,
},
.probe = st_wdog_probe,
.remove_new = st_wdog_remove,
};
module_platform_driver(st_wdog_driver);
MODULE_AUTHOR("David Paris <[email protected]>");
MODULE_DESCRIPTION("ST LPC Watchdog Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/st_lpc_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* txx9wdt: A Hardware Watchdog Driver for TXx9 SoCs
*
* Copyright (C) 2007 Atsushi Nemoto <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/txx9tmr.h>
#define WD_TIMER_CCD 7 /* 1/256 */
#define WD_TIMER_CLK (clk_get_rate(txx9_imclk) / (2 << WD_TIMER_CCD))
#define WD_MAX_TIMEOUT ((0xffffffff >> (32 - TXX9_TIMER_BITS)) / WD_TIMER_CLK)
#define TIMER_MARGIN 60 /* Default is 60 seconds */
static unsigned int timeout = TIMER_MARGIN; /* in seconds */
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. "
"(0<timeout<((2^" __MODULE_STRING(TXX9_TIMER_BITS) ")/(IMCLK/256)), "
"default=" __MODULE_STRING(TIMER_MARGIN) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static struct txx9_tmr_reg __iomem *txx9wdt_reg;
static struct clk *txx9_imclk;
static DEFINE_SPINLOCK(txx9_lock);
static int txx9wdt_ping(struct watchdog_device *wdt_dev)
{
spin_lock(&txx9_lock);
__raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr);
spin_unlock(&txx9_lock);
return 0;
}
static int txx9wdt_start(struct watchdog_device *wdt_dev)
{
spin_lock(&txx9_lock);
__raw_writel(WD_TIMER_CLK * wdt_dev->timeout, &txx9wdt_reg->cpra);
__raw_writel(WD_TIMER_CCD, &txx9wdt_reg->ccdr);
__raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */
__raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
&txx9wdt_reg->tcr);
__raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr);
spin_unlock(&txx9_lock);
return 0;
}
static int txx9wdt_stop(struct watchdog_device *wdt_dev)
{
spin_lock(&txx9_lock);
__raw_writel(TXx9_TMWTMR_WDIS, &txx9wdt_reg->wtmr);
__raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE,
&txx9wdt_reg->tcr);
spin_unlock(&txx9_lock);
return 0;
}
static int txx9wdt_set_timeout(struct watchdog_device *wdt_dev,
unsigned int new_timeout)
{
wdt_dev->timeout = new_timeout;
txx9wdt_stop(wdt_dev);
txx9wdt_start(wdt_dev);
return 0;
}
static const struct watchdog_info txx9wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "Hardware Watchdog for TXx9",
};
static const struct watchdog_ops txx9wdt_ops = {
.owner = THIS_MODULE,
.start = txx9wdt_start,
.stop = txx9wdt_stop,
.ping = txx9wdt_ping,
.set_timeout = txx9wdt_set_timeout,
};
static struct watchdog_device txx9wdt = {
.info = &txx9wdt_info,
.ops = &txx9wdt_ops,
};
static int __init txx9wdt_probe(struct platform_device *dev)
{
int ret;
txx9_imclk = clk_get(NULL, "imbus_clk");
if (IS_ERR(txx9_imclk)) {
ret = PTR_ERR(txx9_imclk);
txx9_imclk = NULL;
goto exit;
}
ret = clk_prepare_enable(txx9_imclk);
if (ret) {
clk_put(txx9_imclk);
txx9_imclk = NULL;
goto exit;
}
txx9wdt_reg = devm_platform_ioremap_resource(dev, 0);
if (IS_ERR(txx9wdt_reg)) {
ret = PTR_ERR(txx9wdt_reg);
goto exit;
}
if (timeout < 1 || timeout > WD_MAX_TIMEOUT)
timeout = TIMER_MARGIN;
txx9wdt.timeout = timeout;
txx9wdt.min_timeout = 1;
txx9wdt.max_timeout = WD_MAX_TIMEOUT;
txx9wdt.parent = &dev->dev;
watchdog_set_nowayout(&txx9wdt, nowayout);
ret = watchdog_register_device(&txx9wdt);
if (ret)
goto exit;
pr_info("Hardware Watchdog Timer: timeout=%d sec (max %ld) (nowayout= %d)\n",
timeout, WD_MAX_TIMEOUT, nowayout);
return 0;
exit:
if (txx9_imclk) {
clk_disable_unprepare(txx9_imclk);
clk_put(txx9_imclk);
}
return ret;
}
static int __exit txx9wdt_remove(struct platform_device *dev)
{
watchdog_unregister_device(&txx9wdt);
clk_disable_unprepare(txx9_imclk);
clk_put(txx9_imclk);
return 0;
}
static void txx9wdt_shutdown(struct platform_device *dev)
{
txx9wdt_stop(&txx9wdt);
}
static struct platform_driver txx9wdt_driver = {
.remove = __exit_p(txx9wdt_remove),
.shutdown = txx9wdt_shutdown,
.driver = {
.name = "txx9wdt",
},
};
module_platform_driver_probe(txx9wdt_driver, txx9wdt_probe);
MODULE_DESCRIPTION("TXx9 Watchdog Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:txx9wdt");
| linux-master | drivers/watchdog/txx9wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SMsC 37B787 Watchdog Timer driver for Linux 2.6.x.x
*
* Based on acquirewdt.c by Alan Cox <[email protected]>
* and some other existing drivers
*
* The authors do NOT admit liability nor provide warranty for
* any of this software. This material is provided "AS-IS" in
* the hope that it may be useful for others.
*
* (C) Copyright 2003-2006 Sven Anders <[email protected]>
*
* History:
* 2003 - Created version 1.0 for Linux 2.4.x.
* 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
* features. Released version 1.1
*
* Theory of operation:
*
* A Watchdog Timer (WDT) is a hardware circuit that can
* reset the computer system in case of a software fault.
* You probably knew that already.
*
* Usually a userspace daemon will notify the kernel WDT driver
* via the /dev/watchdog special device file that userspace is
* still alive, at regular intervals. When such a notification
* occurs, the driver will usually tell the hardware watchdog
* that everything is in order, and that the watchdog should wait
* for yet another little while to reset the system.
* If userspace fails (RAM error, kernel bug, whatever), the
* notifications cease to occur, and the hardware watchdog will
* reset the system (causing a reboot) after the timeout occurs.
*
* Create device with:
* mknod /dev/watchdog c 10 130
*
* For an example userspace keep-alive daemon, see:
* Documentation/watchdog/wdt.rst
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/uaccess.h>
/* enable support for minutes as units? */
/* (does not always work correctly, so disabled by default!) */
#define SMSC_SUPPORT_MINUTES
#undef SMSC_SUPPORT_MINUTES
#define MAX_TIMEOUT 255
#define UNIT_SECOND 0
#define UNIT_MINUTE 1
#define VERSION "1.1"
#define IOPORT 0x3F0
#define IOPORT_SIZE 2
#define IODEV_NO 8
static int unit = UNIT_SECOND; /* timer's unit */
static int timeout = 60; /* timeout value: default is 60 "units" */
static unsigned long timer_enabled; /* is the timer enabled? */
static char expect_close; /* is the close expected? */
static DEFINE_SPINLOCK(io_lock);/* to guard the watchdog from io races */
static bool nowayout = WATCHDOG_NOWAYOUT;
/* -- Low level function ----------------------------------------*/
/* unlock the IO chip */
static inline void open_io_config(void)
{
outb(0x55, IOPORT);
mdelay(1);
outb(0x55, IOPORT);
}
/* lock the IO chip */
static inline void close_io_config(void)
{
outb(0xAA, IOPORT);
}
/* select the IO device */
static inline void select_io_device(unsigned char devno)
{
outb(0x07, IOPORT);
outb(devno, IOPORT+1);
}
/* write to the control register */
static inline void write_io_cr(unsigned char reg, unsigned char data)
{
outb(reg, IOPORT);
outb(data, IOPORT+1);
}
/* read from the control register */
static inline char read_io_cr(unsigned char reg)
{
outb(reg, IOPORT);
return inb(IOPORT+1);
}
/* -- Medium level functions ------------------------------------*/
static inline void gpio_bit12(unsigned char reg)
{
/* -- General Purpose I/O Bit 1.2 --
* Bit 0, In/Out: 0 = Output, 1 = Input
* Bit 1, Polarity: 0 = No Invert, 1 = Invert
* Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable
* Bit 3/4, Function select: 00 = GPI/O, 01 = WDT, 10 = P17,
* 11 = Either Edge Triggered Intr. 2
* Bit 5/6 (Reserved)
* Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain
*/
write_io_cr(0xE2, reg);
}
static inline void gpio_bit13(unsigned char reg)
{
/* -- General Purpose I/O Bit 1.3 --
* Bit 0, In/Out: 0 = Output, 1 = Input
* Bit 1, Polarity: 0 = No Invert, 1 = Invert
* Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable
* Bit 3, Function select: 0 = GPI/O, 1 = LED
* Bit 4-6 (Reserved)
* Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain
*/
write_io_cr(0xE3, reg);
}
static inline void wdt_timer_units(unsigned char new_units)
{
/* -- Watchdog timer units --
* Bit 0-6 (Reserved)
* Bit 7, WDT Time-out Value Units Select
* (0 = Minutes, 1 = Seconds)
*/
write_io_cr(0xF1, new_units);
}
static inline void wdt_timeout_value(unsigned char new_timeout)
{
/* -- Watchdog Timer Time-out Value --
* Bit 0-7 Binary coded units (0=Disabled, 1..255)
*/
write_io_cr(0xF2, new_timeout);
}
static inline void wdt_timer_conf(unsigned char conf)
{
/* -- Watchdog timer configuration --
* Bit 0 Joystick enable: 0* = No Reset, 1 = Reset WDT upon
* Gameport I/O
* Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr.
* Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr
* Bit 3 Reset the timer
* (Wrong in SMsC documentation? Given as: PowerLED Timout
* Enabled)
* Bit 4-7 WDT Interrupt Mapping: (0000* = Disabled,
* 0001=IRQ1, 0010=(Invalid), 0011=IRQ3 to 1111=IRQ15)
*/
write_io_cr(0xF3, conf);
}
static inline void wdt_timer_ctrl(unsigned char reg)
{
/* -- Watchdog timer control --
* Bit 0 Status Bit: 0 = Timer counting, 1 = Timeout occurred
* Bit 1 Power LED Toggle: 0 = Disable Toggle, 1 = Toggle at 1 Hz
* Bit 2 Force Timeout: 1 = Forces WD timeout event (self-cleaning)
* Bit 3 P20 Force Timeout enabled:
* 0 = P20 activity does not generate the WD timeout event
* 1 = P20 Allows rising edge of P20, from the keyboard
* controller, to force the WD timeout event.
* Bit 4 (Reserved)
* -- Soft power management --
* Bit 5 Stop Counter: 1 = Stop software power down counter
* set via register 0xB8, (self-cleaning)
* (Upon read: 0 = Counter running, 1 = Counter stopped)
* Bit 6 Restart Counter: 1 = Restart software power down counter
* set via register 0xB8, (self-cleaning)
* Bit 7 SPOFF: 1 = Force software power down (self-cleaning)
*/
write_io_cr(0xF4, reg);
}
/* -- Higher level functions ------------------------------------*/
/* initialize watchdog */
static void wb_smsc_wdt_initialize(void)
{
unsigned char old;
spin_lock(&io_lock);
open_io_config();
select_io_device(IODEV_NO);
/* enable the watchdog */
gpio_bit13(0x08); /* Select pin 80 = LED not GPIO */
gpio_bit12(0x0A); /* Set pin 79 = WDT not
GPIO/Output/Polarity=Invert */
/* disable the timeout */
wdt_timeout_value(0);
/* reset control register */
wdt_timer_ctrl(0x00);
/* reset configuration register */
wdt_timer_conf(0x00);
/* read old (timer units) register */
old = read_io_cr(0xF1) & 0x7F;
if (unit == UNIT_SECOND)
old |= 0x80; /* set to seconds */
/* set the watchdog timer units */
wdt_timer_units(old);
close_io_config();
spin_unlock(&io_lock);
}
/* shutdown the watchdog */
static void wb_smsc_wdt_shutdown(void)
{
spin_lock(&io_lock);
open_io_config();
select_io_device(IODEV_NO);
/* disable the watchdog */
gpio_bit13(0x09);
gpio_bit12(0x09);
/* reset watchdog config register */
wdt_timer_conf(0x00);
/* reset watchdog control register */
wdt_timer_ctrl(0x00);
/* disable timeout */
wdt_timeout_value(0x00);
close_io_config();
spin_unlock(&io_lock);
}
/* set timeout => enable watchdog */
static void wb_smsc_wdt_set_timeout(unsigned char new_timeout)
{
spin_lock(&io_lock);
open_io_config();
select_io_device(IODEV_NO);
/* set Power LED to blink, if we enable the timeout */
wdt_timer_ctrl((new_timeout == 0) ? 0x00 : 0x02);
/* set timeout value */
wdt_timeout_value(new_timeout);
close_io_config();
spin_unlock(&io_lock);
}
/* get timeout */
static unsigned char wb_smsc_wdt_get_timeout(void)
{
unsigned char set_timeout;
spin_lock(&io_lock);
open_io_config();
select_io_device(IODEV_NO);
set_timeout = read_io_cr(0xF2);
close_io_config();
spin_unlock(&io_lock);
return set_timeout;
}
/* disable watchdog */
static void wb_smsc_wdt_disable(void)
{
/* set the timeout to 0 to disable the watchdog */
wb_smsc_wdt_set_timeout(0);
}
/* enable watchdog by setting the current timeout */
static void wb_smsc_wdt_enable(void)
{
/* set the current timeout... */
wb_smsc_wdt_set_timeout(timeout);
}
/* reset the timer */
static void wb_smsc_wdt_reset_timer(void)
{
spin_lock(&io_lock);
open_io_config();
select_io_device(IODEV_NO);
/* reset the timer */
wdt_timeout_value(timeout);
wdt_timer_conf(0x08);
close_io_config();
spin_unlock(&io_lock);
}
/* return, if the watchdog is enabled (timeout is set...) */
static int wb_smsc_wdt_status(void)
{
return (wb_smsc_wdt_get_timeout() == 0) ? 0 : WDIOF_KEEPALIVEPING;
}
/* -- File operations -------------------------------------------*/
/* open => enable watchdog and set initial timeout */
static int wb_smsc_wdt_open(struct inode *inode, struct file *file)
{
/* /dev/watchdog can only be opened once */
if (test_and_set_bit(0, &timer_enabled))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Reload and activate timer */
wb_smsc_wdt_enable();
pr_info("Watchdog enabled. Timeout set to %d %s\n",
timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)");
return stream_open(inode, file);
}
/* close => shut off the timer */
static int wb_smsc_wdt_release(struct inode *inode, struct file *file)
{
/* Shut off the timer. */
if (expect_close == 42) {
wb_smsc_wdt_disable();
pr_info("Watchdog disabled, sleeping again...\n");
} else {
pr_crit("Unexpected close, not stopping watchdog!\n");
wb_smsc_wdt_reset_timer();
}
clear_bit(0, &timer_enabled);
expect_close = 0;
return 0;
}
/* write => update the timer to keep the machine alive */
static ssize_t wb_smsc_wdt_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
/* See if we got the magic character 'V' and reload the timer */
if (len) {
if (!nowayout) {
size_t i;
/* reset expect flag */
expect_close = 0;
/* scan to see whether or not we got the
magic character */
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
/* someone wrote to us, we should reload the timer */
wb_smsc_wdt_reset_timer();
}
return len;
}
/* ioctl => control interface */
static long wb_smsc_wdt_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
int new_timeout;
union {
struct watchdog_info __user *ident;
int __user *i;
} uarg;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.firmware_version = 0,
.identity = "SMsC 37B787 Watchdog",
};
uarg.i = (int __user *)arg;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(uarg.ident, &ident, sizeof(ident))
? -EFAULT : 0;
case WDIOC_GETSTATUS:
return put_user(wb_smsc_wdt_status(), uarg.i);
case WDIOC_GETBOOTSTATUS:
return put_user(0, uarg.i);
case WDIOC_SETOPTIONS:
{
int options, retval = -EINVAL;
if (get_user(options, uarg.i))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
wb_smsc_wdt_disable();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
wb_smsc_wdt_enable();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
wb_smsc_wdt_reset_timer();
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_timeout, uarg.i))
return -EFAULT;
/* the API states this is given in secs */
if (unit == UNIT_MINUTE)
new_timeout /= 60;
if (new_timeout < 0 || new_timeout > MAX_TIMEOUT)
return -EINVAL;
timeout = new_timeout;
wb_smsc_wdt_set_timeout(timeout);
fallthrough; /* and return the new timeout */
case WDIOC_GETTIMEOUT:
new_timeout = timeout;
if (unit == UNIT_MINUTE)
new_timeout *= 60;
return put_user(new_timeout, uarg.i);
default:
return -ENOTTY;
}
}
/* -- Notifier funtions -----------------------------------------*/
static int wb_smsc_wdt_notify_sys(struct notifier_block *this,
unsigned long code, void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT) {
/* set timeout to 0, to avoid possible race-condition */
timeout = 0;
wb_smsc_wdt_disable();
}
return NOTIFY_DONE;
}
/* -- Module's structures ---------------------------------------*/
static const struct file_operations wb_smsc_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = wb_smsc_wdt_write,
.unlocked_ioctl = wb_smsc_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = wb_smsc_wdt_open,
.release = wb_smsc_wdt_release,
};
static struct notifier_block wb_smsc_wdt_notifier = {
.notifier_call = wb_smsc_wdt_notify_sys,
};
static struct miscdevice wb_smsc_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wb_smsc_wdt_fops,
};
/* -- Module init functions -------------------------------------*/
/* module's "constructor" */
static int __init wb_smsc_wdt_init(void)
{
int ret;
pr_info("SMsC 37B787 watchdog component driver "
VERSION " initialising...\n");
if (!request_region(IOPORT, IOPORT_SIZE, "SMsC 37B787 watchdog")) {
pr_err("Unable to register IO port %#x\n", IOPORT);
ret = -EBUSY;
goto out_pnp;
}
/* set new maximum, if it's too big */
if (timeout > MAX_TIMEOUT)
timeout = MAX_TIMEOUT;
/* init the watchdog timer */
wb_smsc_wdt_initialize();
ret = register_reboot_notifier(&wb_smsc_wdt_notifier);
if (ret) {
pr_err("Unable to register reboot notifier err = %d\n", ret);
goto out_io;
}
ret = misc_register(&wb_smsc_wdt_miscdev);
if (ret) {
pr_err("Unable to register miscdev on minor %d\n",
WATCHDOG_MINOR);
goto out_rbt;
}
/* output info */
pr_info("Timeout set to %d %s\n",
timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)");
pr_info("Watchdog initialized and sleeping (nowayout=%d)...\n",
nowayout);
out_clean:
return ret;
out_rbt:
unregister_reboot_notifier(&wb_smsc_wdt_notifier);
out_io:
release_region(IOPORT, IOPORT_SIZE);
out_pnp:
goto out_clean;
}
/* module's "destructor" */
static void __exit wb_smsc_wdt_exit(void)
{
/* Stop the timer before we leave */
if (!nowayout) {
wb_smsc_wdt_shutdown();
pr_info("Watchdog disabled\n");
}
misc_deregister(&wb_smsc_wdt_miscdev);
unregister_reboot_notifier(&wb_smsc_wdt_notifier);
release_region(IOPORT, IOPORT_SIZE);
pr_info("SMsC 37B787 watchdog component driver removed\n");
}
module_init(wb_smsc_wdt_init);
module_exit(wb_smsc_wdt_exit);
MODULE_AUTHOR("Sven Anders <[email protected]>");
MODULE_DESCRIPTION("Driver for SMsC 37B787 watchdog component (Version "
VERSION ")");
MODULE_LICENSE("GPL");
#ifdef SMSC_SUPPORT_MINUTES
module_param(unit, int, 0);
MODULE_PARM_DESC(unit,
"set unit to use, 0=seconds or 1=minutes, default is 0");
#endif
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "range is 1-255 units, default is 60");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
| linux-master | drivers/watchdog/smsc37b787_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* SBC8360 Watchdog driver
*
* (c) Copyright 2005 Webcon, Inc.
*
* Based on ib700wdt.c, which is based on advantechwdt.c which is based
* on acquirewdt.c which is based on wdt.c.
*
* (c) Copyright 2001 Charles Howes <[email protected]>
*
* Based on advantechwdt.c which is based on acquirewdt.c which
* is based on wdt.c.
*
* (c) Copyright 2000-2001 Marek Michalkiewicz <[email protected]>
*
* Based on acquirewdt.c which is based on wdt.c.
* Original copyright messages:
*
* (c) Copyright 1996 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>
*
* 14-Dec-2001 Matt Domsch <[email protected]>
* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
* Added timeout module option to override default
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/notifier.h>
#include <linux/fs.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/uaccess.h>
static unsigned long sbc8360_is_open;
static char expect_close;
/*
*
* Watchdog Timer Configuration
*
* The function of the watchdog timer is to reset the system automatically
* and is defined at I/O port 0120H and 0121H. To enable the watchdog timer
* and allow the system to reset, write appropriate values from the table
* below to I/O port 0120H and 0121H. To disable the timer, write a zero
* value to I/O port 0121H for the system to stop the watchdog function.
*
* The following describes how the timer should be programmed (according to
* the vendor documentation)
*
* Enabling Watchdog:
* MOV AX,000AH (enable, phase I)
* MOV DX,0120H
* OUT DX,AX
* MOV AX,000BH (enable, phase II)
* MOV DX,0120H
* OUT DX,AX
* MOV AX,000nH (set multiplier n, from 1-4)
* MOV DX,0120H
* OUT DX,AX
* MOV AX,000mH (set base timer m, from 0-F)
* MOV DX,0121H
* OUT DX,AX
*
* Reset timer:
* MOV AX,000mH (same as set base timer, above)
* MOV DX,0121H
* OUT DX,AX
*
* Disabling Watchdog:
* MOV AX,0000H (a zero value)
* MOV DX,0120H
* OUT DX,AX
*
* Watchdog timeout configuration values:
* N
* M | 1 2 3 4
* --|----------------------------------
* 0 | 0.5s 5s 50s 100s
* 1 | 1s 10s 100s 200s
* 2 | 1.5s 15s 150s 300s
* 3 | 2s 20s 200s 400s
* 4 | 2.5s 25s 250s 500s
* 5 | 3s 30s 300s 600s
* 6 | 3.5s 35s 350s 700s
* 7 | 4s 40s 400s 800s
* 8 | 4.5s 45s 450s 900s
* 9 | 5s 50s 500s 1000s
* A | 5.5s 55s 550s 1100s
* B | 6s 60s 600s 1200s
* C | 6.5s 65s 650s 1300s
* D | 7s 70s 700s 1400s
* E | 7.5s 75s 750s 1500s
* F | 8s 80s 800s 1600s
*
* Another way to say the same things is:
* For N=1, Timeout = (M+1) * 0.5s
* For N=2, Timeout = (M+1) * 5s
* For N=3, Timeout = (M+1) * 50s
* For N=4, Timeout = (M+1) * 100s
*
*/
static int wd_times[64][2] = {
{0, 1}, /* 0 = 0.5s */
{1, 1}, /* 1 = 1s */
{2, 1}, /* 2 = 1.5s */
{3, 1}, /* 3 = 2s */
{4, 1}, /* 4 = 2.5s */
{5, 1}, /* 5 = 3s */
{6, 1}, /* 6 = 3.5s */
{7, 1}, /* 7 = 4s */
{8, 1}, /* 8 = 4.5s */
{9, 1}, /* 9 = 5s */
{0xA, 1}, /* 10 = 5.5s */
{0xB, 1}, /* 11 = 6s */
{0xC, 1}, /* 12 = 6.5s */
{0xD, 1}, /* 13 = 7s */
{0xE, 1}, /* 14 = 7.5s */
{0xF, 1}, /* 15 = 8s */
{0, 2}, /* 16 = 5s */
{1, 2}, /* 17 = 10s */
{2, 2}, /* 18 = 15s */
{3, 2}, /* 19 = 20s */
{4, 2}, /* 20 = 25s */
{5, 2}, /* 21 = 30s */
{6, 2}, /* 22 = 35s */
{7, 2}, /* 23 = 40s */
{8, 2}, /* 24 = 45s */
{9, 2}, /* 25 = 50s */
{0xA, 2}, /* 26 = 55s */
{0xB, 2}, /* 27 = 60s */
{0xC, 2}, /* 28 = 65s */
{0xD, 2}, /* 29 = 70s */
{0xE, 2}, /* 30 = 75s */
{0xF, 2}, /* 31 = 80s */
{0, 3}, /* 32 = 50s */
{1, 3}, /* 33 = 100s */
{2, 3}, /* 34 = 150s */
{3, 3}, /* 35 = 200s */
{4, 3}, /* 36 = 250s */
{5, 3}, /* 37 = 300s */
{6, 3}, /* 38 = 350s */
{7, 3}, /* 39 = 400s */
{8, 3}, /* 40 = 450s */
{9, 3}, /* 41 = 500s */
{0xA, 3}, /* 42 = 550s */
{0xB, 3}, /* 43 = 600s */
{0xC, 3}, /* 44 = 650s */
{0xD, 3}, /* 45 = 700s */
{0xE, 3}, /* 46 = 750s */
{0xF, 3}, /* 47 = 800s */
{0, 4}, /* 48 = 100s */
{1, 4}, /* 49 = 200s */
{2, 4}, /* 50 = 300s */
{3, 4}, /* 51 = 400s */
{4, 4}, /* 52 = 500s */
{5, 4}, /* 53 = 600s */
{6, 4}, /* 54 = 700s */
{7, 4}, /* 55 = 800s */
{8, 4}, /* 56 = 900s */
{9, 4}, /* 57 = 1000s */
{0xA, 4}, /* 58 = 1100s */
{0xB, 4}, /* 59 = 1200s */
{0xC, 4}, /* 60 = 1300s */
{0xD, 4}, /* 61 = 1400s */
{0xE, 4}, /* 62 = 1500s */
{0xF, 4} /* 63 = 1600s */
};
#define SBC8360_ENABLE 0x120
#define SBC8360_BASETIME 0x121
static int timeout = 27;
static int wd_margin = 0xB;
static int wd_multiplier = 2;
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Index into timeout table (0-63) (default=27 (60s))");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Kernel methods.
*/
/* Activate and pre-configure watchdog */
static void sbc8360_activate(void)
{
/* Enable the watchdog */
outb(0x0A, SBC8360_ENABLE);
msleep_interruptible(100);
outb(0x0B, SBC8360_ENABLE);
msleep_interruptible(100);
/* Set timeout multiplier */
outb(wd_multiplier, SBC8360_ENABLE);
msleep_interruptible(100);
/* Nothing happens until first sbc8360_ping() */
}
/* Kernel pings watchdog */
static void sbc8360_ping(void)
{
/* Write the base timer register */
outb(wd_margin, SBC8360_BASETIME);
}
/* stop watchdog */
static void sbc8360_stop(void)
{
/* De-activate the watchdog */
outb(0, SBC8360_ENABLE);
}
/* Userspace pings kernel driver, or requests clean close */
static ssize_t sbc8360_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count) {
if (!nowayout) {
size_t i;
/* In case it was set long ago */
expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
sbc8360_ping();
}
return count;
}
static int sbc8360_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &sbc8360_is_open))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Activate and ping once to start the countdown */
sbc8360_activate();
sbc8360_ping();
return stream_open(inode, file);
}
static int sbc8360_close(struct inode *inode, struct file *file)
{
if (expect_close == 42)
sbc8360_stop();
else
pr_crit("SBC8360 device closed unexpectedly. SBC8360 will not stop!\n");
clear_bit(0, &sbc8360_is_open);
expect_close = 0;
return 0;
}
/*
* Notifier for system down
*/
static int sbc8360_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
sbc8360_stop(); /* Disable the SBC8360 Watchdog */
return NOTIFY_DONE;
}
/*
* Kernel Interfaces
*/
static const struct file_operations sbc8360_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = sbc8360_write,
.open = sbc8360_open,
.release = sbc8360_close,
};
static struct miscdevice sbc8360_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &sbc8360_fops,
};
/*
* The SBC8360 needs to learn about soft shutdowns in order to
* turn the timebomb registers off.
*/
static struct notifier_block sbc8360_notifier = {
.notifier_call = sbc8360_notify_sys,
};
static int __init sbc8360_init(void)
{
int res;
unsigned long int mseconds = 60000;
if (timeout < 0 || timeout > 63) {
pr_err("Invalid timeout index (must be 0-63)\n");
res = -EINVAL;
goto out;
}
if (!request_region(SBC8360_ENABLE, 1, "SBC8360")) {
pr_err("ENABLE method I/O %X is not available\n",
SBC8360_ENABLE);
res = -EIO;
goto out;
}
if (!request_region(SBC8360_BASETIME, 1, "SBC8360")) {
pr_err("BASETIME method I/O %X is not available\n",
SBC8360_BASETIME);
res = -EIO;
goto out_nobasetimereg;
}
res = register_reboot_notifier(&sbc8360_notifier);
if (res) {
pr_err("Failed to register reboot notifier\n");
goto out_noreboot;
}
res = misc_register(&sbc8360_miscdev);
if (res) {
pr_err("failed to register misc device\n");
goto out_nomisc;
}
wd_margin = wd_times[timeout][0];
wd_multiplier = wd_times[timeout][1];
if (wd_multiplier == 1)
mseconds = (wd_margin + 1) * 500;
else if (wd_multiplier == 2)
mseconds = (wd_margin + 1) * 5000;
else if (wd_multiplier == 3)
mseconds = (wd_margin + 1) * 50000;
else if (wd_multiplier == 4)
mseconds = (wd_margin + 1) * 100000;
/* My kingdom for the ability to print "0.5 seconds" in the kernel! */
pr_info("Timeout set at %ld ms\n", mseconds);
return 0;
out_nomisc:
unregister_reboot_notifier(&sbc8360_notifier);
out_noreboot:
release_region(SBC8360_BASETIME, 1);
out_nobasetimereg:
release_region(SBC8360_ENABLE, 1);
out:
return res;
}
static void __exit sbc8360_exit(void)
{
misc_deregister(&sbc8360_miscdev);
unregister_reboot_notifier(&sbc8360_notifier);
release_region(SBC8360_ENABLE, 1);
release_region(SBC8360_BASETIME, 1);
}
module_init(sbc8360_init);
module_exit(sbc8360_exit);
MODULE_AUTHOR("Ian E. Morgan <[email protected]>");
MODULE_DESCRIPTION("SBC8360 watchdog driver");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.01");
/* end of sbc8360.c */
| linux-master | drivers/watchdog/sbc8360.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ARM Secure Monitor Call watchdog driver
*
* Copyright 2020 Google LLC.
* Julius Werner <[email protected]>
* Based on mtk_wdt.c
*/
#include <linux/arm-smccc.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <uapi/linux/psci.h>
#define DRV_NAME "arm_smc_wdt"
#define DRV_VERSION "1.0"
enum smcwd_call {
SMCWD_INIT = 0,
SMCWD_SET_TIMEOUT = 1,
SMCWD_ENABLE = 2,
SMCWD_PET = 3,
SMCWD_GET_TIMELEFT = 4,
};
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int timeout;
static int smcwd_call(struct watchdog_device *wdd, enum smcwd_call call,
unsigned long arg, struct arm_smccc_res *res)
{
struct arm_smccc_res local_res;
if (!res)
res = &local_res;
arm_smccc_smc((u32)(uintptr_t)watchdog_get_drvdata(wdd), call, arg, 0,
0, 0, 0, 0, res);
if (res->a0 == PSCI_RET_NOT_SUPPORTED)
return -ENODEV;
if (res->a0 == PSCI_RET_INVALID_PARAMS)
return -EINVAL;
if (res->a0 != PSCI_RET_SUCCESS)
return -EIO;
return 0;
}
static int smcwd_ping(struct watchdog_device *wdd)
{
return smcwd_call(wdd, SMCWD_PET, 0, NULL);
}
static unsigned int smcwd_get_timeleft(struct watchdog_device *wdd)
{
struct arm_smccc_res res;
smcwd_call(wdd, SMCWD_GET_TIMELEFT, 0, &res);
if (res.a0)
return 0;
return res.a1;
}
static int smcwd_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
{
int res;
res = smcwd_call(wdd, SMCWD_SET_TIMEOUT, timeout, NULL);
if (!res)
wdd->timeout = timeout;
return res;
}
static int smcwd_stop(struct watchdog_device *wdd)
{
return smcwd_call(wdd, SMCWD_ENABLE, 0, NULL);
}
static int smcwd_start(struct watchdog_device *wdd)
{
return smcwd_call(wdd, SMCWD_ENABLE, 1, NULL);
}
static const struct watchdog_info smcwd_info = {
.identity = DRV_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops smcwd_ops = {
.start = smcwd_start,
.stop = smcwd_stop,
.ping = smcwd_ping,
.set_timeout = smcwd_set_timeout,
};
static const struct watchdog_ops smcwd_timeleft_ops = {
.start = smcwd_start,
.stop = smcwd_stop,
.ping = smcwd_ping,
.set_timeout = smcwd_set_timeout,
.get_timeleft = smcwd_get_timeleft,
};
static int smcwd_probe(struct platform_device *pdev)
{
struct watchdog_device *wdd;
int err;
struct arm_smccc_res res;
u32 smc_func_id;
wdd = devm_kzalloc(&pdev->dev, sizeof(*wdd), GFP_KERNEL);
if (!wdd)
return -ENOMEM;
platform_set_drvdata(pdev, wdd);
if (of_property_read_u32(pdev->dev.of_node, "arm,smc-id",
&smc_func_id))
smc_func_id = 0x82003D06;
watchdog_set_drvdata(wdd, (void *)(uintptr_t)smc_func_id);
err = smcwd_call(wdd, SMCWD_INIT, 0, &res);
if (err < 0)
return err;
wdd->info = &smcwd_info;
/* get_timeleft is optional */
if (smcwd_call(wdd, SMCWD_GET_TIMELEFT, 0, NULL))
wdd->ops = &smcwd_ops;
else
wdd->ops = &smcwd_timeleft_ops;
wdd->timeout = res.a2;
wdd->max_timeout = res.a2;
wdd->min_timeout = res.a1;
wdd->parent = &pdev->dev;
watchdog_stop_on_reboot(wdd);
watchdog_stop_on_unregister(wdd);
watchdog_set_nowayout(wdd, nowayout);
watchdog_init_timeout(wdd, timeout, &pdev->dev);
err = smcwd_set_timeout(wdd, wdd->timeout);
if (err)
return err;
err = devm_watchdog_register_device(&pdev->dev, wdd);
if (err)
return err;
dev_info(&pdev->dev,
"Watchdog registered (timeout=%d sec, nowayout=%d)\n",
wdd->timeout, nowayout);
return 0;
}
static const struct of_device_id smcwd_dt_ids[] = {
{ .compatible = "arm,smc-wdt" },
{}
};
MODULE_DEVICE_TABLE(of, smcwd_dt_ids);
static struct platform_driver smcwd_driver = {
.probe = smcwd_probe,
.driver = {
.name = DRV_NAME,
.of_match_table = smcwd_dt_ids,
},
};
module_platform_driver(smcwd_driver);
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Julius Werner <[email protected]>");
MODULE_DESCRIPTION("ARM Secure Monitor Call Watchdog Driver");
MODULE_VERSION(DRV_VERSION);
| linux-master | drivers/watchdog/arm_smc_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/char/watchdog/ixp4xx_wdt.c
*
* Watchdog driver for Intel IXP4xx network processors
*
* Author: Deepak Saxena <[email protected]>
* Author: Linus Walleij <[email protected]>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
* Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <[email protected]>
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/bits.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/soc/ixp4xx/cpu.h>
struct ixp4xx_wdt {
struct watchdog_device wdd;
void __iomem *base;
unsigned long rate;
};
/* Fallback if we do not have a clock for this */
#define IXP4XX_TIMER_FREQ 66666000
/* Registers after the timer registers */
#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
#define IXP4XX_WDT_KEY 0x0000482E
#define IXP4XX_WDT_RESET_ENABLE 0x00000001
#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
static inline
struct ixp4xx_wdt *to_ixp4xx_wdt(struct watchdog_device *wdd)
{
return container_of(wdd, struct ixp4xx_wdt, wdd);
}
static int ixp4xx_wdt_start(struct watchdog_device *wdd)
{
struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
__raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
__raw_writel(wdd->timeout * iwdt->rate,
iwdt->base + IXP4XX_OSWT_OFFSET);
__raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
iwdt->base + IXP4XX_OSWE_OFFSET);
__raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
return 0;
}
static int ixp4xx_wdt_stop(struct watchdog_device *wdd)
{
struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
__raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
__raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
return 0;
}
static int ixp4xx_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
wdd->timeout = timeout;
if (watchdog_active(wdd))
ixp4xx_wdt_start(wdd);
return 0;
}
static int ixp4xx_wdt_restart(struct watchdog_device *wdd,
unsigned long action, void *data)
{
struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
__raw_writel(0, iwdt->base + IXP4XX_OSWT_OFFSET);
__raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
iwdt->base + IXP4XX_OSWE_OFFSET);
return 0;
}
static const struct watchdog_ops ixp4xx_wdt_ops = {
.start = ixp4xx_wdt_start,
.stop = ixp4xx_wdt_stop,
.set_timeout = ixp4xx_wdt_set_timeout,
.restart = ixp4xx_wdt_restart,
.owner = THIS_MODULE,
};
static const struct watchdog_info ixp4xx_wdt_info = {
.options = WDIOF_KEEPALIVEPING
| WDIOF_MAGICCLOSE
| WDIOF_SETTIMEOUT,
.identity = KBUILD_MODNAME,
};
static int ixp4xx_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ixp4xx_wdt *iwdt;
struct clk *clk;
int ret;
if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n");
return -ENODEV;
}
iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL);
if (!iwdt)
return -ENOMEM;
iwdt->base = (void __iomem *)dev->platform_data;
/*
* Retrieve rate from a fixed clock from the device tree if
* the parent has that, else use the default clock rate.
*/
clk = devm_clk_get_enabled(dev->parent, NULL);
if (!IS_ERR(clk))
iwdt->rate = clk_get_rate(clk);
if (!iwdt->rate)
iwdt->rate = IXP4XX_TIMER_FREQ;
iwdt->wdd.info = &ixp4xx_wdt_info;
iwdt->wdd.ops = &ixp4xx_wdt_ops;
iwdt->wdd.min_timeout = 1;
iwdt->wdd.max_timeout = U32_MAX / iwdt->rate;
iwdt->wdd.parent = dev;
/* Default to 60 seconds */
iwdt->wdd.timeout = 60U;
watchdog_init_timeout(&iwdt->wdd, 0, dev);
if (__raw_readl(iwdt->base + IXP4XX_OSST_OFFSET) &
IXP4XX_OSST_TIMER_WARM_RESET)
iwdt->wdd.bootstatus = WDIOF_CARDRESET;
ret = devm_watchdog_register_device(dev, &iwdt->wdd);
if (ret)
return ret;
dev_info(dev, "IXP4xx watchdog available\n");
return 0;
}
static struct platform_driver ixp4xx_wdt_driver = {
.probe = ixp4xx_wdt_probe,
.driver = {
.name = "ixp4xx-watchdog",
},
};
module_platform_driver(ixp4xx_wdt_driver);
MODULE_AUTHOR("Deepak Saxena <[email protected]>");
MODULE_DESCRIPTION("IXP4xx Network Processor Watchdog");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/ixp4xx_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Watchdog driver for the UniPhier watchdog timer
*
* (c) Copyright 2014 Panasonic Corporation
* (c) Copyright 2016 Socionext Inc.
* All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
/* WDT timer setting register */
#define WDTTIMSET 0x3004
#define WDTTIMSET_PERIOD_MASK (0xf << 0)
#define WDTTIMSET_PERIOD_1_SEC (0x3 << 0)
/* WDT reset selection register */
#define WDTRSTSEL 0x3008
#define WDTRSTSEL_RSTSEL_MASK (0x3 << 0)
#define WDTRSTSEL_RSTSEL_BOTH (0x0 << 0)
#define WDTRSTSEL_RSTSEL_IRQ_ONLY (0x2 << 0)
/* WDT control register */
#define WDTCTRL 0x300c
#define WDTCTRL_STATUS BIT(8)
#define WDTCTRL_CLEAR BIT(1)
#define WDTCTRL_ENABLE BIT(0)
#define SEC_TO_WDTTIMSET_PRD(sec) \
(ilog2(sec) + WDTTIMSET_PERIOD_1_SEC)
#define WDTST_TIMEOUT 1000 /* usec */
#define WDT_DEFAULT_TIMEOUT 64 /* Default is 64 seconds */
#define WDT_PERIOD_MIN 1
#define WDT_PERIOD_MAX 128
static unsigned int timeout = 0;
static bool nowayout = WATCHDOG_NOWAYOUT;
struct uniphier_wdt_dev {
struct watchdog_device wdt_dev;
struct regmap *regmap;
};
/*
* UniPhier Watchdog operations
*/
static int uniphier_watchdog_ping(struct watchdog_device *w)
{
struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
unsigned int val;
int ret;
/* Clear counter */
ret = regmap_write_bits(wdev->regmap, WDTCTRL,
WDTCTRL_CLEAR, WDTCTRL_CLEAR);
if (!ret)
/*
* As SoC specification, after clear counter,
* it needs to wait until counter status is 1.
*/
ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val,
(val & WDTCTRL_STATUS),
0, WDTST_TIMEOUT);
return ret;
}
static int __uniphier_watchdog_start(struct regmap *regmap, unsigned int sec)
{
unsigned int val;
int ret;
ret = regmap_read_poll_timeout(regmap, WDTCTRL, val,
!(val & WDTCTRL_STATUS),
0, WDTST_TIMEOUT);
if (ret)
return ret;
/* Setup period */
ret = regmap_write(regmap, WDTTIMSET,
SEC_TO_WDTTIMSET_PRD(sec));
if (ret)
return ret;
/* Enable and clear watchdog */
ret = regmap_write(regmap, WDTCTRL, WDTCTRL_ENABLE | WDTCTRL_CLEAR);
if (!ret)
/*
* As SoC specification, after clear counter,
* it needs to wait until counter status is 1.
*/
ret = regmap_read_poll_timeout(regmap, WDTCTRL, val,
(val & WDTCTRL_STATUS),
0, WDTST_TIMEOUT);
return ret;
}
static int __uniphier_watchdog_stop(struct regmap *regmap)
{
/* Disable and stop watchdog */
return regmap_write_bits(regmap, WDTCTRL, WDTCTRL_ENABLE, 0);
}
static int __uniphier_watchdog_restart(struct regmap *regmap, unsigned int sec)
{
int ret;
ret = __uniphier_watchdog_stop(regmap);
if (ret)
return ret;
return __uniphier_watchdog_start(regmap, sec);
}
static int uniphier_watchdog_start(struct watchdog_device *w)
{
struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
unsigned int tmp_timeout;
tmp_timeout = roundup_pow_of_two(w->timeout);
return __uniphier_watchdog_start(wdev->regmap, tmp_timeout);
}
static int uniphier_watchdog_stop(struct watchdog_device *w)
{
struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
return __uniphier_watchdog_stop(wdev->regmap);
}
static int uniphier_watchdog_set_timeout(struct watchdog_device *w,
unsigned int t)
{
struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
unsigned int tmp_timeout;
int ret;
tmp_timeout = roundup_pow_of_two(t);
if (tmp_timeout == w->timeout)
return 0;
if (watchdog_active(w)) {
ret = __uniphier_watchdog_restart(wdev->regmap, tmp_timeout);
if (ret)
return ret;
}
w->timeout = tmp_timeout;
return 0;
}
/*
* Kernel Interfaces
*/
static const struct watchdog_info uniphier_wdt_info = {
.identity = "uniphier-wdt",
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE |
WDIOF_OVERHEAT,
};
static const struct watchdog_ops uniphier_wdt_ops = {
.owner = THIS_MODULE,
.start = uniphier_watchdog_start,
.stop = uniphier_watchdog_stop,
.ping = uniphier_watchdog_ping,
.set_timeout = uniphier_watchdog_set_timeout,
};
static int uniphier_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct uniphier_wdt_dev *wdev;
struct regmap *regmap;
struct device_node *parent;
int ret;
wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
if (!wdev)
return -ENOMEM;
parent = of_get_parent(dev->of_node); /* parent should be syscon node */
regmap = syscon_node_to_regmap(parent);
of_node_put(parent);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
wdev->regmap = regmap;
wdev->wdt_dev.info = &uniphier_wdt_info;
wdev->wdt_dev.ops = &uniphier_wdt_ops;
wdev->wdt_dev.max_timeout = WDT_PERIOD_MAX;
wdev->wdt_dev.min_timeout = WDT_PERIOD_MIN;
wdev->wdt_dev.timeout = WDT_DEFAULT_TIMEOUT;
wdev->wdt_dev.parent = dev;
watchdog_init_timeout(&wdev->wdt_dev, timeout, dev);
watchdog_set_nowayout(&wdev->wdt_dev, nowayout);
watchdog_stop_on_reboot(&wdev->wdt_dev);
watchdog_set_drvdata(&wdev->wdt_dev, wdev);
uniphier_watchdog_stop(&wdev->wdt_dev);
ret = regmap_write(wdev->regmap, WDTRSTSEL, WDTRSTSEL_RSTSEL_BOTH);
if (ret)
return ret;
ret = devm_watchdog_register_device(dev, &wdev->wdt_dev);
if (ret)
return ret;
dev_info(dev, "watchdog driver (timeout=%d sec, nowayout=%d)\n",
wdev->wdt_dev.timeout, nowayout);
return 0;
}
static const struct of_device_id uniphier_wdt_dt_ids[] = {
{ .compatible = "socionext,uniphier-wdt" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_wdt_dt_ids);
static struct platform_driver uniphier_wdt_driver = {
.probe = uniphier_wdt_probe,
.driver = {
.name = "uniphier-wdt",
.of_match_table = uniphier_wdt_dt_ids,
},
};
module_platform_driver(uniphier_wdt_driver);
module_param(timeout, uint, 0000);
MODULE_PARM_DESC(timeout,
"Watchdog timeout seconds in power of 2. (0 < timeout < 128, default="
__MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
module_param(nowayout, bool, 0000);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_AUTHOR("Keiji Hayashibara <[email protected]>");
MODULE_DESCRIPTION("UniPhier Watchdog Device Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/uniphier_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog driver for Broadcom BCM47XX
*
* Copyright (C) 2008 Aleksandar Radovanovic <[email protected]>
* Copyright (C) 2009 Matthieu CASTET <[email protected]>
* Copyright (C) 2012-2013 Hauke Mehrtens <[email protected]>
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bcm47xx_wdt.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/timer.h>
#include <linux/jiffies.h>
#define DRV_NAME "bcm47xx_wdt"
#define WDT_DEFAULT_TIME 30 /* seconds */
#define WDT_SOFTTIMER_MAX 255 /* seconds */
#define WDT_SOFTTIMER_THRESHOLD 60 /* seconds */
static int timeout = WDT_DEFAULT_TIME;
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog time in seconds. (default="
__MODULE_STRING(WDT_DEFAULT_TIME) ")");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static inline struct bcm47xx_wdt *bcm47xx_wdt_get(struct watchdog_device *wdd)
{
return container_of(wdd, struct bcm47xx_wdt, wdd);
}
static int bcm47xx_wdt_hard_keepalive(struct watchdog_device *wdd)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
wdt->timer_set_ms(wdt, wdd->timeout * 1000);
return 0;
}
static int bcm47xx_wdt_hard_start(struct watchdog_device *wdd)
{
return 0;
}
static int bcm47xx_wdt_hard_stop(struct watchdog_device *wdd)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
wdt->timer_set(wdt, 0);
return 0;
}
static int bcm47xx_wdt_hard_set_timeout(struct watchdog_device *wdd,
unsigned int new_time)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
u32 max_timer = wdt->max_timer_ms;
if (new_time < 1 || new_time > max_timer / 1000) {
pr_warn("timeout value must be 1<=x<=%d, using %d\n",
max_timer / 1000, new_time);
return -EINVAL;
}
wdd->timeout = new_time;
return 0;
}
static int bcm47xx_wdt_restart(struct watchdog_device *wdd,
unsigned long action, void *data)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
wdt->timer_set(wdt, 1);
return 0;
}
static const struct watchdog_ops bcm47xx_wdt_hard_ops = {
.owner = THIS_MODULE,
.start = bcm47xx_wdt_hard_start,
.stop = bcm47xx_wdt_hard_stop,
.ping = bcm47xx_wdt_hard_keepalive,
.set_timeout = bcm47xx_wdt_hard_set_timeout,
.restart = bcm47xx_wdt_restart,
};
static void bcm47xx_wdt_soft_timer_tick(struct timer_list *t)
{
struct bcm47xx_wdt *wdt = from_timer(wdt, t, soft_timer);
u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms);
if (!atomic_dec_and_test(&wdt->soft_ticks)) {
wdt->timer_set_ms(wdt, next_tick);
mod_timer(&wdt->soft_timer, jiffies + HZ);
} else {
pr_crit("Watchdog will fire soon!!!\n");
}
}
static int bcm47xx_wdt_soft_keepalive(struct watchdog_device *wdd)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
atomic_set(&wdt->soft_ticks, wdd->timeout);
return 0;
}
static int bcm47xx_wdt_soft_start(struct watchdog_device *wdd)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
bcm47xx_wdt_soft_keepalive(wdd);
bcm47xx_wdt_soft_timer_tick(&wdt->soft_timer);
return 0;
}
static int bcm47xx_wdt_soft_stop(struct watchdog_device *wdd)
{
struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd);
del_timer_sync(&wdt->soft_timer);
wdt->timer_set(wdt, 0);
return 0;
}
static int bcm47xx_wdt_soft_set_timeout(struct watchdog_device *wdd,
unsigned int new_time)
{
if (new_time < 1 || new_time > WDT_SOFTTIMER_MAX) {
pr_warn("timeout value must be 1<=x<=%d, using %d\n",
WDT_SOFTTIMER_MAX, new_time);
return -EINVAL;
}
wdd->timeout = new_time;
return 0;
}
static const struct watchdog_info bcm47xx_wdt_info = {
.identity = DRV_NAME,
.options = WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops bcm47xx_wdt_soft_ops = {
.owner = THIS_MODULE,
.start = bcm47xx_wdt_soft_start,
.stop = bcm47xx_wdt_soft_stop,
.ping = bcm47xx_wdt_soft_keepalive,
.set_timeout = bcm47xx_wdt_soft_set_timeout,
.restart = bcm47xx_wdt_restart,
};
static int bcm47xx_wdt_probe(struct platform_device *pdev)
{
int ret;
bool soft;
struct bcm47xx_wdt *wdt = dev_get_platdata(&pdev->dev);
if (!wdt)
return -ENXIO;
soft = wdt->max_timer_ms < WDT_SOFTTIMER_THRESHOLD * 1000;
if (soft) {
wdt->wdd.ops = &bcm47xx_wdt_soft_ops;
timer_setup(&wdt->soft_timer, bcm47xx_wdt_soft_timer_tick, 0);
} else {
wdt->wdd.ops = &bcm47xx_wdt_hard_ops;
}
wdt->wdd.info = &bcm47xx_wdt_info;
wdt->wdd.timeout = WDT_DEFAULT_TIME;
wdt->wdd.parent = &pdev->dev;
ret = wdt->wdd.ops->set_timeout(&wdt->wdd, timeout);
if (ret)
goto err_timer;
watchdog_set_nowayout(&wdt->wdd, nowayout);
watchdog_set_restart_priority(&wdt->wdd, 64);
watchdog_stop_on_reboot(&wdt->wdd);
ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
if (ret)
goto err_timer;
dev_info(&pdev->dev, "BCM47xx Watchdog Timer enabled (%d seconds%s%s)\n",
timeout, nowayout ? ", nowayout" : "",
soft ? ", Software Timer" : "");
return 0;
err_timer:
if (soft)
del_timer_sync(&wdt->soft_timer);
return ret;
}
static struct platform_driver bcm47xx_wdt_driver = {
.driver = {
.name = "bcm47xx-wdt",
},
.probe = bcm47xx_wdt_probe,
};
module_platform_driver(bcm47xx_wdt_driver);
MODULE_AUTHOR("Aleksandar Radovanovic");
MODULE_AUTHOR("Hauke Mehrtens <[email protected]>");
MODULE_DESCRIPTION("Watchdog driver for Broadcom BCM47xx");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/bcm47xx_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Watchdog driver for SBC-FITPC2 board
*
* Author: Denis Turischev <[email protected]>
*
* Adapted from the IXP2000 watchdog driver by Deepak Saxena.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME " WATCHDOG: " fmt
#include <linux/module.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/moduleparam.h>
#include <linux/dmi.h>
#include <linux/io.h>
#include <linux/uaccess.h>
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int margin = 60; /* (secs) Default is 1 minute */
static unsigned long wdt_status;
static DEFINE_MUTEX(wdt_lock);
#define WDT_IN_USE 0
#define WDT_OK_TO_CLOSE 1
#define COMMAND_PORT 0x4c
#define DATA_PORT 0x48
#define IFACE_ON_COMMAND 1
#define REBOOT_COMMAND 2
#define WATCHDOG_NAME "SBC-FITPC2 Watchdog"
static void wdt_send_data(unsigned char command, unsigned char data)
{
outb(data, DATA_PORT);
msleep(200);
outb(command, COMMAND_PORT);
msleep(100);
}
static void wdt_enable(void)
{
mutex_lock(&wdt_lock);
wdt_send_data(IFACE_ON_COMMAND, 1);
wdt_send_data(REBOOT_COMMAND, margin);
mutex_unlock(&wdt_lock);
}
static void wdt_disable(void)
{
mutex_lock(&wdt_lock);
wdt_send_data(IFACE_ON_COMMAND, 0);
wdt_send_data(REBOOT_COMMAND, 0);
mutex_unlock(&wdt_lock);
}
static int fitpc2_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(WDT_IN_USE, &wdt_status))
return -EBUSY;
clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
wdt_enable();
return stream_open(inode, file);
}
static ssize_t fitpc2_wdt_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
size_t i;
if (!len)
return 0;
if (nowayout) {
len = 0;
goto out;
}
clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
set_bit(WDT_OK_TO_CLOSE, &wdt_status);
}
out:
wdt_enable();
return len;
}
static const struct watchdog_info ident = {
.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING,
.identity = WATCHDOG_NAME,
};
static long fitpc2_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int ret = -ENOTTY;
int time;
switch (cmd) {
case WDIOC_GETSUPPORT:
ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
sizeof(ident)) ? -EFAULT : 0;
break;
case WDIOC_GETSTATUS:
ret = put_user(0, (int __user *)arg);
break;
case WDIOC_GETBOOTSTATUS:
ret = put_user(0, (int __user *)arg);
break;
case WDIOC_KEEPALIVE:
wdt_enable();
ret = 0;
break;
case WDIOC_SETTIMEOUT:
ret = get_user(time, (int __user *)arg);
if (ret)
break;
if (time < 31 || time > 255) {
ret = -EINVAL;
break;
}
margin = time;
wdt_enable();
fallthrough;
case WDIOC_GETTIMEOUT:
ret = put_user(margin, (int __user *)arg);
break;
}
return ret;
}
static int fitpc2_wdt_release(struct inode *inode, struct file *file)
{
if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) {
wdt_disable();
pr_info("Device disabled\n");
} else {
pr_warn("Device closed unexpectedly - timer will not stop\n");
wdt_enable();
}
clear_bit(WDT_IN_USE, &wdt_status);
clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
return 0;
}
static const struct file_operations fitpc2_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = fitpc2_wdt_write,
.unlocked_ioctl = fitpc2_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = fitpc2_wdt_open,
.release = fitpc2_wdt_release,
};
static struct miscdevice fitpc2_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &fitpc2_wdt_fops,
};
static int __init fitpc2_wdt_init(void)
{
int err;
const char *brd_name;
brd_name = dmi_get_system_info(DMI_BOARD_NAME);
if (!brd_name || !strstr(brd_name, "SBC-FITPC2"))
return -ENODEV;
pr_info("%s found\n", brd_name);
if (!request_region(COMMAND_PORT, 1, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n", COMMAND_PORT);
return -EIO;
}
if (!request_region(DATA_PORT, 1, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n", DATA_PORT);
err = -EIO;
goto err_data_port;
}
if (margin < 31 || margin > 255) {
pr_err("margin must be in range 31 - 255 seconds, you tried to set %d\n",
margin);
err = -EINVAL;
goto err_margin;
}
err = misc_register(&fitpc2_wdt_miscdev);
if (err) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, err);
goto err_margin;
}
return 0;
err_margin:
release_region(DATA_PORT, 1);
err_data_port:
release_region(COMMAND_PORT, 1);
return err;
}
static void __exit fitpc2_wdt_exit(void)
{
misc_deregister(&fitpc2_wdt_miscdev);
release_region(DATA_PORT, 1);
release_region(COMMAND_PORT, 1);
}
module_init(fitpc2_wdt_init);
module_exit(fitpc2_wdt_exit);
MODULE_AUTHOR("Denis Turischev <[email protected]>");
MODULE_DESCRIPTION("SBC-FITPC2 Watchdog");
module_param(margin, int, 0);
MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sbc_fitpc2_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for the MTX-1 Watchdog.
*
* (C) Copyright 2005 4G Systems <[email protected]>,
* All Rights Reserved.
* http://www.4g-systems.biz
*
* (C) Copyright 2007 OpenWrt.org, Florian Fainelli <[email protected]>
* (c) Copyright 2005 4G Systems <[email protected]>
*
* Release 0.01.
* Author: Michael Stickel [email protected]
*
* Release 0.02.
* Author: Florian Fainelli [email protected]
* use the Linux watchdog/timer APIs
*
* The Watchdog is configured to reset the MTX-1
* if it is not triggered for 100 seconds.
* It should not be triggered more often than 1.6 seconds.
*
* A timer triggers the watchdog every 5 seconds, until
* it is opened for the first time. After the first open
* it MUST be triggered every 2..95 seconds.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/timer.h>
#include <linux/completion.h>
#include <linux/jiffies.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/gpio/consumer.h>
#define MTX1_WDT_INTERVAL (5 * HZ)
static int ticks = 100 * HZ;
static struct {
struct completion stop;
spinlock_t lock;
int running;
struct timer_list timer;
int queue;
int default_ticks;
unsigned long inuse;
struct gpio_desc *gpiod;
unsigned int gstate;
} mtx1_wdt_device;
static void mtx1_wdt_trigger(struct timer_list *unused)
{
spin_lock(&mtx1_wdt_device.lock);
if (mtx1_wdt_device.running)
ticks--;
/* toggle wdt gpio */
mtx1_wdt_device.gstate = !mtx1_wdt_device.gstate;
gpiod_set_value(mtx1_wdt_device.gpiod, mtx1_wdt_device.gstate);
if (mtx1_wdt_device.queue && ticks)
mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL);
else
complete(&mtx1_wdt_device.stop);
spin_unlock(&mtx1_wdt_device.lock);
}
static void mtx1_wdt_reset(void)
{
ticks = mtx1_wdt_device.default_ticks;
}
static void mtx1_wdt_start(void)
{
unsigned long flags;
spin_lock_irqsave(&mtx1_wdt_device.lock, flags);
if (!mtx1_wdt_device.queue) {
mtx1_wdt_device.queue = 1;
mtx1_wdt_device.gstate = 1;
gpiod_set_value(mtx1_wdt_device.gpiod, 1);
mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL);
}
mtx1_wdt_device.running++;
spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags);
}
static int mtx1_wdt_stop(void)
{
unsigned long flags;
spin_lock_irqsave(&mtx1_wdt_device.lock, flags);
if (mtx1_wdt_device.queue) {
mtx1_wdt_device.queue = 0;
mtx1_wdt_device.gstate = 0;
gpiod_set_value(mtx1_wdt_device.gpiod, 0);
}
ticks = mtx1_wdt_device.default_ticks;
spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags);
return 0;
}
/* Filesystem functions */
static int mtx1_wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &mtx1_wdt_device.inuse))
return -EBUSY;
return stream_open(inode, file);
}
static int mtx1_wdt_release(struct inode *inode, struct file *file)
{
clear_bit(0, &mtx1_wdt_device.inuse);
return 0;
}
static long mtx1_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = (int __user *)argp;
unsigned int value;
static const struct watchdog_info ident = {
.options = WDIOF_CARDRESET,
.identity = "MTX-1 WDT",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident)))
return -EFAULT;
break;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
put_user(0, p);
break;
case WDIOC_SETOPTIONS:
if (get_user(value, p))
return -EFAULT;
if (value & WDIOS_ENABLECARD)
mtx1_wdt_start();
else if (value & WDIOS_DISABLECARD)
mtx1_wdt_stop();
else
return -EINVAL;
return 0;
case WDIOC_KEEPALIVE:
mtx1_wdt_reset();
break;
default:
return -ENOTTY;
}
return 0;
}
static ssize_t mtx1_wdt_write(struct file *file, const char *buf,
size_t count, loff_t *ppos)
{
if (!count)
return -EIO;
mtx1_wdt_reset();
return count;
}
static const struct file_operations mtx1_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.unlocked_ioctl = mtx1_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = mtx1_wdt_open,
.write = mtx1_wdt_write,
.release = mtx1_wdt_release,
};
static struct miscdevice mtx1_wdt_misc = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &mtx1_wdt_fops,
};
static int mtx1_wdt_probe(struct platform_device *pdev)
{
int ret;
mtx1_wdt_device.gpiod = devm_gpiod_get(&pdev->dev,
NULL, GPIOD_OUT_HIGH);
if (IS_ERR(mtx1_wdt_device.gpiod)) {
dev_err(&pdev->dev, "failed to request gpio");
return PTR_ERR(mtx1_wdt_device.gpiod);
}
spin_lock_init(&mtx1_wdt_device.lock);
init_completion(&mtx1_wdt_device.stop);
mtx1_wdt_device.queue = 0;
clear_bit(0, &mtx1_wdt_device.inuse);
timer_setup(&mtx1_wdt_device.timer, mtx1_wdt_trigger, 0);
mtx1_wdt_device.default_ticks = ticks;
ret = misc_register(&mtx1_wdt_misc);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register\n");
return ret;
}
mtx1_wdt_start();
dev_info(&pdev->dev, "MTX-1 Watchdog driver\n");
return 0;
}
static void mtx1_wdt_remove(struct platform_device *pdev)
{
/* FIXME: do we need to lock this test ? */
if (mtx1_wdt_device.queue) {
mtx1_wdt_device.queue = 0;
wait_for_completion(&mtx1_wdt_device.stop);
}
misc_deregister(&mtx1_wdt_misc);
}
static struct platform_driver mtx1_wdt_driver = {
.probe = mtx1_wdt_probe,
.remove_new = mtx1_wdt_remove,
.driver.name = "mtx1-wdt",
.driver.owner = THIS_MODULE,
};
module_platform_driver(mtx1_wdt_driver);
MODULE_AUTHOR("Michael Stickel, Florian Fainelli");
MODULE_DESCRIPTION("Driver for the MTX-1 watchdog");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mtx1-wdt");
| linux-master | drivers/watchdog/mtx-1_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Cadence WDT driver - Used by Xilinx Zynq
*
* Copyright (C) 2010 - 2014 Xilinx, Inc.
*
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define CDNS_WDT_DEFAULT_TIMEOUT 10
/* Supports 1 - 516 sec */
#define CDNS_WDT_MIN_TIMEOUT 1
#define CDNS_WDT_MAX_TIMEOUT 516
/* Restart key */
#define CDNS_WDT_RESTART_KEY 0x00001999
/* Counter register access key */
#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000
/* Counter value divisor */
#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000
/* Clock prescaler value and selection */
#define CDNS_WDT_PRESCALE_64 64
#define CDNS_WDT_PRESCALE_512 512
#define CDNS_WDT_PRESCALE_4096 4096
#define CDNS_WDT_PRESCALE_SELECT_64 1
#define CDNS_WDT_PRESCALE_SELECT_512 2
#define CDNS_WDT_PRESCALE_SELECT_4096 3
/* Input clock frequency */
#define CDNS_WDT_CLK_10MHZ 10000000
#define CDNS_WDT_CLK_75MHZ 75000000
/* Counter maximum value */
#define CDNS_WDT_COUNTER_MAX 0xFFF
static int wdt_timeout;
static int nowayout = WATCHDOG_NOWAYOUT;
module_param(wdt_timeout, int, 0644);
MODULE_PARM_DESC(wdt_timeout,
"Watchdog time in seconds. (default="
__MODULE_STRING(CDNS_WDT_DEFAULT_TIMEOUT) ")");
module_param(nowayout, int, 0644);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/**
* struct cdns_wdt - Watchdog device structure
* @regs: baseaddress of device
* @rst: reset flag
* @clk: struct clk * of a clock source
* @prescaler: for saving prescaler value
* @ctrl_clksel: counter clock prescaler selection
* @io_lock: spinlock for IO register access
* @cdns_wdt_device: watchdog device structure
*
* Structure containing parameters specific to cadence watchdog.
*/
struct cdns_wdt {
void __iomem *regs;
bool rst;
struct clk *clk;
u32 prescaler;
u32 ctrl_clksel;
spinlock_t io_lock;
struct watchdog_device cdns_wdt_device;
};
/* Write access to Registers */
static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val)
{
writel_relaxed(val, wdt->regs + offset);
}
/*************************Register Map**************************************/
/* Register Offsets for the WDT */
#define CDNS_WDT_ZMR_OFFSET 0x0 /* Zero Mode Register */
#define CDNS_WDT_CCR_OFFSET 0x4 /* Counter Control Register */
#define CDNS_WDT_RESTART_OFFSET 0x8 /* Restart Register */
#define CDNS_WDT_SR_OFFSET 0xC /* Status Register */
/*
* Zero Mode Register - This register controls how the time out is indicated
* and also contains the access code to allow writes to the register (0xABC).
*/
#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */
#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */
#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */
/*
* Counter Control register - This register controls how fast the timer runs
* and the reset value and also contains the access code to allow writes to
* the register.
*/
#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */
/**
* cdns_wdt_stop - Stop the watchdog.
*
* @wdd: watchdog device
*
* Read the contents of the ZMR register, clear the WDEN bit
* in the register and set the access key for successful write.
*
* Return: always 0
*/
static int cdns_wdt_stop(struct watchdog_device *wdd)
{
struct cdns_wdt *wdt = watchdog_get_drvdata(wdd);
spin_lock(&wdt->io_lock);
cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET,
CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK));
spin_unlock(&wdt->io_lock);
return 0;
}
/**
* cdns_wdt_reload - Reload the watchdog timer (i.e. pat the watchdog).
*
* @wdd: watchdog device
*
* Write the restart key value (0x00001999) to the restart register.
*
* Return: always 0
*/
static int cdns_wdt_reload(struct watchdog_device *wdd)
{
struct cdns_wdt *wdt = watchdog_get_drvdata(wdd);
spin_lock(&wdt->io_lock);
cdns_wdt_writereg(wdt, CDNS_WDT_RESTART_OFFSET,
CDNS_WDT_RESTART_KEY);
spin_unlock(&wdt->io_lock);
return 0;
}
/**
* cdns_wdt_start - Enable and start the watchdog.
*
* @wdd: watchdog device
*
* The counter value is calculated according to the formula:
* calculated count = (timeout * clock) / prescaler + 1.
* The calculated count is divided by 0x1000 to obtain the field value
* to write to counter control register.
* Clears the contents of prescaler and counter reset value. Sets the
* prescaler to 4096 and the calculated count and access key
* to write to CCR Register.
* Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
* or Interrupt signal(IRQEN) with a specified cycles and the access
* key to write to ZMR Register.
*
* Return: always 0
*/
static int cdns_wdt_start(struct watchdog_device *wdd)
{
struct cdns_wdt *wdt = watchdog_get_drvdata(wdd);
unsigned int data = 0;
unsigned short count;
unsigned long clock_f = clk_get_rate(wdt->clk);
/*
* Counter value divisor to obtain the value of
* counter reset to be written to control register.
*/
count = (wdd->timeout * (clock_f / wdt->prescaler)) /
CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;
if (count > CDNS_WDT_COUNTER_MAX)
count = CDNS_WDT_COUNTER_MAX;
spin_lock(&wdt->io_lock);
cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET,
CDNS_WDT_ZMR_ZKEY_VAL);
count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
/* Write counter access key first to be able write to register */
data = count | CDNS_WDT_REGISTER_ACCESS_KEY | wdt->ctrl_clksel;
cdns_wdt_writereg(wdt, CDNS_WDT_CCR_OFFSET, data);
data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
CDNS_WDT_ZMR_ZKEY_VAL;
/* Reset on timeout if specified in device tree. */
if (wdt->rst) {
data |= CDNS_WDT_ZMR_RSTEN_MASK;
data &= ~CDNS_WDT_ZMR_IRQEN_MASK;
} else {
data &= ~CDNS_WDT_ZMR_RSTEN_MASK;
data |= CDNS_WDT_ZMR_IRQEN_MASK;
}
cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET, data);
cdns_wdt_writereg(wdt, CDNS_WDT_RESTART_OFFSET,
CDNS_WDT_RESTART_KEY);
spin_unlock(&wdt->io_lock);
return 0;
}
/**
* cdns_wdt_settimeout - Set a new timeout value for the watchdog device.
*
* @wdd: watchdog device
* @new_time: new timeout value that needs to be set
* Return: 0 on success
*
* Update the watchdog_device timeout with new value which is used when
* cdns_wdt_start is called.
*/
static int cdns_wdt_settimeout(struct watchdog_device *wdd,
unsigned int new_time)
{
wdd->timeout = new_time;
return cdns_wdt_start(wdd);
}
/**
* cdns_wdt_irq_handler - Notifies of watchdog timeout.
*
* @irq: interrupt number
* @dev_id: pointer to a platform device structure
* Return: IRQ_HANDLED
*
* The handler is invoked when the watchdog times out and a
* reset on timeout has not been enabled.
*/
static irqreturn_t cdns_wdt_irq_handler(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
dev_info(&pdev->dev,
"Watchdog timed out. Internal reset not enabled\n");
return IRQ_HANDLED;
}
/*
* Info structure used to indicate the features supported by the device
* to the upper layers. This is defined in watchdog.h header file.
*/
static const struct watchdog_info cdns_wdt_info = {
.identity = "cdns_wdt watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
/* Watchdog Core Ops */
static const struct watchdog_ops cdns_wdt_ops = {
.owner = THIS_MODULE,
.start = cdns_wdt_start,
.stop = cdns_wdt_stop,
.ping = cdns_wdt_reload,
.set_timeout = cdns_wdt_settimeout,
};
/************************Platform Operations*****************************/
/**
* cdns_wdt_probe - Probe call for the device.
*
* @pdev: handle to the platform device structure.
* Return: 0 on success, negative error otherwise.
*
* It does all the memory allocation and registration for the device.
*/
static int cdns_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret, irq;
unsigned long clock_f;
struct cdns_wdt *wdt;
struct watchdog_device *cdns_wdt_device;
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
cdns_wdt_device = &wdt->cdns_wdt_device;
cdns_wdt_device->info = &cdns_wdt_info;
cdns_wdt_device->ops = &cdns_wdt_ops;
cdns_wdt_device->timeout = CDNS_WDT_DEFAULT_TIMEOUT;
cdns_wdt_device->min_timeout = CDNS_WDT_MIN_TIMEOUT;
cdns_wdt_device->max_timeout = CDNS_WDT_MAX_TIMEOUT;
wdt->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->regs))
return PTR_ERR(wdt->regs);
/* Register the interrupt */
wdt->rst = of_property_read_bool(dev->of_node, "reset-on-timeout");
irq = platform_get_irq(pdev, 0);
if (!wdt->rst && irq >= 0) {
ret = devm_request_irq(dev, irq, cdns_wdt_irq_handler, 0,
pdev->name, pdev);
if (ret) {
dev_err(dev,
"cannot register interrupt handler err=%d\n",
ret);
return ret;
}
}
/* Initialize the members of cdns_wdt structure */
cdns_wdt_device->parent = dev;
watchdog_init_timeout(cdns_wdt_device, wdt_timeout, dev);
watchdog_set_nowayout(cdns_wdt_device, nowayout);
watchdog_stop_on_reboot(cdns_wdt_device);
watchdog_set_drvdata(cdns_wdt_device, wdt);
wdt->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(wdt->clk))
return dev_err_probe(dev, PTR_ERR(wdt->clk),
"input clock not found\n");
clock_f = clk_get_rate(wdt->clk);
if (clock_f <= CDNS_WDT_CLK_75MHZ) {
wdt->prescaler = CDNS_WDT_PRESCALE_512;
wdt->ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;
} else {
wdt->prescaler = CDNS_WDT_PRESCALE_4096;
wdt->ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;
}
spin_lock_init(&wdt->io_lock);
watchdog_stop_on_reboot(cdns_wdt_device);
watchdog_stop_on_unregister(cdns_wdt_device);
ret = devm_watchdog_register_device(dev, cdns_wdt_device);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
dev_info(dev, "Xilinx Watchdog Timer with timeout %ds%s\n",
cdns_wdt_device->timeout, nowayout ? ", nowayout" : "");
return 0;
}
/**
* cdns_wdt_suspend - Stop the device.
*
* @dev: handle to the device structure.
* Return: 0 always.
*/
static int __maybe_unused cdns_wdt_suspend(struct device *dev)
{
struct cdns_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->cdns_wdt_device)) {
cdns_wdt_stop(&wdt->cdns_wdt_device);
clk_disable_unprepare(wdt->clk);
}
return 0;
}
/**
* cdns_wdt_resume - Resume the device.
*
* @dev: handle to the device structure.
* Return: 0 on success, errno otherwise.
*/
static int __maybe_unused cdns_wdt_resume(struct device *dev)
{
int ret;
struct cdns_wdt *wdt = dev_get_drvdata(dev);
if (watchdog_active(&wdt->cdns_wdt_device)) {
ret = clk_prepare_enable(wdt->clk);
if (ret) {
dev_err(dev, "unable to enable clock\n");
return ret;
}
cdns_wdt_start(&wdt->cdns_wdt_device);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(cdns_wdt_pm_ops, cdns_wdt_suspend, cdns_wdt_resume);
static const struct of_device_id cdns_wdt_of_match[] = {
{ .compatible = "cdns,wdt-r1p2", },
{ /* end of table */ }
};
MODULE_DEVICE_TABLE(of, cdns_wdt_of_match);
/* Driver Structure */
static struct platform_driver cdns_wdt_driver = {
.probe = cdns_wdt_probe,
.driver = {
.name = "cdns-wdt",
.of_match_table = cdns_wdt_of_match,
.pm = &cdns_wdt_pm_ops,
},
};
module_platform_driver(cdns_wdt_driver);
MODULE_AUTHOR("Xilinx, Inc.");
MODULE_DESCRIPTION("Watchdog driver for Cadence WDT");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/cadence_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2020 ROHM Semiconductors
*
* ROHM BD9576MUF and BD9573MUF Watchdog driver
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/mfd/rohm-bd957x.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
static bool nowayout;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default=\"false\")");
#define HW_MARGIN_MIN 2
#define HW_MARGIN_MAX 4416
#define BD957X_WDT_DEFAULT_MARGIN 4416
#define WATCHDOG_TIMEOUT 30
struct bd9576_wdt_priv {
struct gpio_desc *gpiod_ping;
struct gpio_desc *gpiod_en;
struct device *dev;
struct regmap *regmap;
bool always_running;
struct watchdog_device wdd;
};
static void bd9576_wdt_disable(struct bd9576_wdt_priv *priv)
{
gpiod_set_value_cansleep(priv->gpiod_en, 0);
}
static int bd9576_wdt_ping(struct watchdog_device *wdd)
{
struct bd9576_wdt_priv *priv = watchdog_get_drvdata(wdd);
/* Pulse */
gpiod_set_value_cansleep(priv->gpiod_ping, 1);
gpiod_set_value_cansleep(priv->gpiod_ping, 0);
return 0;
}
static int bd9576_wdt_start(struct watchdog_device *wdd)
{
struct bd9576_wdt_priv *priv = watchdog_get_drvdata(wdd);
gpiod_set_value_cansleep(priv->gpiod_en, 1);
return bd9576_wdt_ping(wdd);
}
static int bd9576_wdt_stop(struct watchdog_device *wdd)
{
struct bd9576_wdt_priv *priv = watchdog_get_drvdata(wdd);
if (!priv->always_running)
bd9576_wdt_disable(priv);
else
set_bit(WDOG_HW_RUNNING, &wdd->status);
return 0;
}
static const struct watchdog_info bd957x_wdt_ident = {
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT,
.identity = "BD957x Watchdog",
};
static const struct watchdog_ops bd957x_wdt_ops = {
.owner = THIS_MODULE,
.start = bd9576_wdt_start,
.stop = bd9576_wdt_stop,
.ping = bd9576_wdt_ping,
};
/* Unit is hundreds of uS */
#define FASTNG_MIN 23
static int find_closest_fast(int target, int *sel, int *val)
{
int i;
int window = FASTNG_MIN;
for (i = 0; i < 8 && window < target; i++)
window <<= 1;
*val = window;
*sel = i;
if (i == 8)
return -EINVAL;
return 0;
}
static int find_closest_slow_by_fast(int fast_val, int target, int *slowsel)
{
int sel;
static const int multipliers[] = {2, 3, 7, 15};
for (sel = 0; sel < ARRAY_SIZE(multipliers) &&
multipliers[sel] * fast_val < target; sel++)
;
if (sel == ARRAY_SIZE(multipliers))
return -EINVAL;
*slowsel = sel;
return 0;
}
static int find_closest_slow(int target, int *slow_sel, int *fast_sel)
{
static const int multipliers[] = {2, 3, 7, 15};
int i, j;
int val = 0;
int window = FASTNG_MIN;
for (i = 0; i < 8; i++) {
for (j = 0; j < ARRAY_SIZE(multipliers); j++) {
int slow;
slow = window * multipliers[j];
if (slow >= target && (!val || slow < val)) {
val = slow;
*fast_sel = i;
*slow_sel = j;
}
}
window <<= 1;
}
if (!val)
return -EINVAL;
return 0;
}
#define BD957X_WDG_TYPE_WINDOW BIT(5)
#define BD957X_WDG_TYPE_SLOW 0
#define BD957X_WDG_TYPE_MASK BIT(5)
#define BD957X_WDG_NG_RATIO_MASK 0x18
#define BD957X_WDG_FASTNG_MASK 0x7
static int bd957x_set_wdt_mode(struct bd9576_wdt_priv *priv, int hw_margin,
int hw_margin_min)
{
int ret, fastng, slowng, type, reg, mask;
struct device *dev = priv->dev;
/* convert to 100uS */
hw_margin *= 10;
hw_margin_min *= 10;
if (hw_margin_min) {
int min;
type = BD957X_WDG_TYPE_WINDOW;
dev_dbg(dev, "Setting type WINDOW 0x%x\n", type);
ret = find_closest_fast(hw_margin_min, &fastng, &min);
if (ret) {
dev_err(dev, "bad WDT window for fast timeout\n");
return ret;
}
ret = find_closest_slow_by_fast(min, hw_margin, &slowng);
if (ret) {
dev_err(dev, "bad WDT window\n");
return ret;
}
} else {
type = BD957X_WDG_TYPE_SLOW;
dev_dbg(dev, "Setting type SLOW 0x%x\n", type);
ret = find_closest_slow(hw_margin, &slowng, &fastng);
if (ret) {
dev_err(dev, "bad WDT window\n");
return ret;
}
}
slowng <<= ffs(BD957X_WDG_NG_RATIO_MASK) - 1;
reg = type | slowng | fastng;
mask = BD957X_WDG_TYPE_MASK | BD957X_WDG_NG_RATIO_MASK |
BD957X_WDG_FASTNG_MASK;
ret = regmap_update_bits(priv->regmap, BD957X_REG_WDT_CONF,
mask, reg);
return ret;
}
static int bd9576_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct bd9576_wdt_priv *priv;
u32 hw_margin[2];
u32 hw_margin_max = BD957X_WDT_DEFAULT_MARGIN, hw_margin_min = 0;
int count;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->dev = dev;
priv->regmap = dev_get_regmap(dev->parent, NULL);
if (!priv->regmap) {
dev_err(dev, "No regmap found\n");
return -ENODEV;
}
priv->gpiod_en = devm_fwnode_gpiod_get(dev, dev_fwnode(dev->parent),
"rohm,watchdog-enable",
GPIOD_OUT_LOW,
"watchdog-enable");
if (IS_ERR(priv->gpiod_en))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_en),
"getting watchdog-enable GPIO failed\n");
priv->gpiod_ping = devm_fwnode_gpiod_get(dev, dev_fwnode(dev->parent),
"rohm,watchdog-ping",
GPIOD_OUT_LOW,
"watchdog-ping");
if (IS_ERR(priv->gpiod_ping))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_ping),
"getting watchdog-ping GPIO failed\n");
count = device_property_count_u32(dev->parent, "rohm,hw-timeout-ms");
if (count < 0 && count != -EINVAL)
return count;
if (count > 0) {
if (count > ARRAY_SIZE(hw_margin))
return -EINVAL;
ret = device_property_read_u32_array(dev->parent,
"rohm,hw-timeout-ms",
hw_margin, count);
if (ret < 0)
return ret;
if (count == 1)
hw_margin_max = hw_margin[0];
if (count == 2) {
hw_margin_max = hw_margin[1];
hw_margin_min = hw_margin[0];
}
}
ret = bd957x_set_wdt_mode(priv, hw_margin_max, hw_margin_min);
if (ret)
return ret;
priv->always_running = device_property_read_bool(dev->parent,
"always-running");
watchdog_set_drvdata(&priv->wdd, priv);
priv->wdd.info = &bd957x_wdt_ident;
priv->wdd.ops = &bd957x_wdt_ops;
priv->wdd.min_hw_heartbeat_ms = hw_margin_min;
priv->wdd.max_hw_heartbeat_ms = hw_margin_max;
priv->wdd.parent = dev;
priv->wdd.timeout = WATCHDOG_TIMEOUT;
watchdog_init_timeout(&priv->wdd, 0, dev);
watchdog_set_nowayout(&priv->wdd, nowayout);
watchdog_stop_on_reboot(&priv->wdd);
if (priv->always_running)
bd9576_wdt_start(&priv->wdd);
return devm_watchdog_register_device(dev, &priv->wdd);
}
static struct platform_driver bd9576_wdt_driver = {
.driver = {
.name = "bd9576-wdt",
},
.probe = bd9576_wdt_probe,
};
module_platform_driver(bd9576_wdt_driver);
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("ROHM BD9576/BD9573 Watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd9576-wdt");
| linux-master | drivers/watchdog/bd9576_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* drivers/char/watchdog/pnx4008_wdt.c
*
* Watchdog driver for PNX4008 board
*
* Authors: Dmitry Chigirev <[email protected]>,
* Vitaly Wool <[email protected]>
* Based on sa1100 driver,
* Copyright (C) 2000 Oleg Drokin <[email protected]>
*
* 2005-2006 (c) MontaVista Software, Inc.
*
* (C) 2012 Wolfram Sang, Pengutronix
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/reboot.h>
/* WatchDog Timer - Chapter 23 Page 207 */
#define DEFAULT_HEARTBEAT 19
#define MAX_HEARTBEAT 60
/* Watchdog timer register set definition */
#define WDTIM_INT(p) ((p) + 0x0)
#define WDTIM_CTRL(p) ((p) + 0x4)
#define WDTIM_COUNTER(p) ((p) + 0x8)
#define WDTIM_MCTRL(p) ((p) + 0xC)
#define WDTIM_MATCH0(p) ((p) + 0x10)
#define WDTIM_EMR(p) ((p) + 0x14)
#define WDTIM_PULSE(p) ((p) + 0x18)
#define WDTIM_RES(p) ((p) + 0x1C)
/* WDTIM_INT bit definitions */
#define MATCH_INT 1
/* WDTIM_CTRL bit definitions */
#define COUNT_ENAB 1
#define RESET_COUNT (1 << 1)
#define DEBUG_EN (1 << 2)
/* WDTIM_MCTRL bit definitions */
#define MR0_INT 1
#undef RESET_COUNT0
#define RESET_COUNT0 (1 << 2)
#define STOP_COUNT0 (1 << 2)
#define M_RES1 (1 << 3)
#define M_RES2 (1 << 4)
#define RESFRC1 (1 << 5)
#define RESFRC2 (1 << 6)
/* WDTIM_EMR bit definitions */
#define EXT_MATCH0 1
#define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */
/* WDTIM_RES bit definitions */
#define WDOG_RESET 1 /* read only */
#define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned int heartbeat;
static DEFINE_SPINLOCK(io_lock);
static void __iomem *wdt_base;
static struct clk *wdt_clk;
static int pnx4008_wdt_start(struct watchdog_device *wdd)
{
spin_lock(&io_lock);
/* stop counter, initiate counter reset */
writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
/*wait for reset to complete. 100% guarantee event */
while (readl(WDTIM_COUNTER(wdt_base)))
cpu_relax();
/* internal and external reset, stop after that */
writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
/* configure match output */
writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
/* clear interrupt, just in case */
writel(MATCH_INT, WDTIM_INT(wdt_base));
/* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
writel(0xFFFF, WDTIM_PULSE(wdt_base));
writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
/*enable counter, stop when debugger active */
writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
spin_unlock(&io_lock);
return 0;
}
static int pnx4008_wdt_stop(struct watchdog_device *wdd)
{
spin_lock(&io_lock);
writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
spin_unlock(&io_lock);
return 0;
}
static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int new_timeout)
{
wdd->timeout = new_timeout;
return 0;
}
static int pnx4008_restart_handler(struct watchdog_device *wdd,
unsigned long mode, void *cmd)
{
const char *boot_cmd = cmd;
/*
* Verify if a "cmd" passed from the userspace program rebooting
* the system; if available, handle it.
* - For details, see the 'reboot' syscall in kernel/reboot.c
* - If the received "cmd" is not supported, use the default mode.
*/
if (boot_cmd) {
if (boot_cmd[0] == 'h')
mode = REBOOT_HARD;
else if (boot_cmd[0] == 's')
mode = REBOOT_SOFT;
}
if (mode == REBOOT_SOFT) {
/* Force match output active */
writel(EXT_MATCH0, WDTIM_EMR(wdt_base));
/* Internal reset on match output (RESOUT_N not asserted) */
writel(M_RES1, WDTIM_MCTRL(wdt_base));
} else {
/* Instant assert of RESETOUT_N with pulse length 1mS */
writel(13000, WDTIM_PULSE(wdt_base));
writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base));
}
/* Wait for watchdog to reset system */
mdelay(1000);
return NOTIFY_DONE;
}
static const struct watchdog_info pnx4008_wdt_ident = {
.options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "PNX4008 Watchdog",
};
static const struct watchdog_ops pnx4008_wdt_ops = {
.owner = THIS_MODULE,
.start = pnx4008_wdt_start,
.stop = pnx4008_wdt_stop,
.set_timeout = pnx4008_wdt_set_timeout,
.restart = pnx4008_restart_handler,
};
static struct watchdog_device pnx4008_wdd = {
.info = &pnx4008_wdt_ident,
.ops = &pnx4008_wdt_ops,
.timeout = DEFAULT_HEARTBEAT,
.min_timeout = 1,
.max_timeout = MAX_HEARTBEAT,
};
static int pnx4008_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret = 0;
watchdog_init_timeout(&pnx4008_wdd, heartbeat, dev);
wdt_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt_base))
return PTR_ERR(wdt_base);
wdt_clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(wdt_clk))
return PTR_ERR(wdt_clk);
pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
WDIOF_CARDRESET : 0;
pnx4008_wdd.parent = dev;
watchdog_set_nowayout(&pnx4008_wdd, nowayout);
watchdog_set_restart_priority(&pnx4008_wdd, 128);
if (readl(WDTIM_CTRL(wdt_base)) & COUNT_ENAB)
set_bit(WDOG_HW_RUNNING, &pnx4008_wdd.status);
ret = devm_watchdog_register_device(dev, &pnx4008_wdd);
if (ret < 0)
return ret;
dev_info(dev, "heartbeat %d sec\n", pnx4008_wdd.timeout);
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id pnx4008_wdt_match[] = {
{ .compatible = "nxp,pnx4008-wdt" },
{ }
};
MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
#endif
static struct platform_driver platform_wdt_driver = {
.driver = {
.name = "pnx4008-watchdog",
.of_match_table = of_match_ptr(pnx4008_wdt_match),
},
.probe = pnx4008_wdt_probe,
};
module_platform_driver(platform_wdt_driver);
MODULE_AUTHOR("MontaVista Software, Inc. <[email protected]>");
MODULE_AUTHOR("Wolfram Sang <[email protected]>");
MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
module_param(heartbeat, uint, 0);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat period in seconds from 1 to "
__MODULE_STRING(MAX_HEARTBEAT) ", default "
__MODULE_STRING(DEFAULT_HEARTBEAT));
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Set to 1 to keep watchdog running after device release");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pnx4008-watchdog");
| linux-master | drivers/watchdog/pnx4008_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* FIXME: add wdrtas_get_status and wdrtas_get_boot_status as soon as
* RTAS calls are available
*/
/*
* RTAS watchdog driver
*
* (C) Copyright IBM Corp. 2005
* device driver to exploit watchdog RTAS functions
*
* Authors : Utz Bacher <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/uaccess.h>
#include <asm/rtas.h>
#define WDRTAS_MAGIC_CHAR 42
#define WDRTAS_SUPPORTED_MASK (WDIOF_SETTIMEOUT | \
WDIOF_MAGICCLOSE)
MODULE_AUTHOR("Utz Bacher <[email protected]>");
MODULE_DESCRIPTION("RTAS watchdog driver");
MODULE_LICENSE("GPL");
static bool wdrtas_nowayout = WATCHDOG_NOWAYOUT;
static atomic_t wdrtas_miscdev_open = ATOMIC_INIT(0);
static char wdrtas_expect_close;
static int wdrtas_interval;
#define WDRTAS_THERMAL_SENSOR 3
static int wdrtas_token_get_sensor_state;
#define WDRTAS_SURVEILLANCE_IND 9000
static int wdrtas_token_set_indicator;
#define WDRTAS_SP_SPI 28
static int wdrtas_token_get_sp;
static int wdrtas_token_event_scan;
#define WDRTAS_DEFAULT_INTERVAL 300
#define WDRTAS_LOGBUFFER_LEN 128
static char wdrtas_logbuffer[WDRTAS_LOGBUFFER_LEN];
/*** watchdog access functions */
/**
* wdrtas_set_interval - sets the watchdog interval
* @interval: new interval
*
* returns 0 on success, <0 on failures
*
* wdrtas_set_interval sets the watchdog keepalive interval by calling the
* RTAS function set-indicator (surveillance). The unit of interval is
* seconds.
*/
static int wdrtas_set_interval(int interval)
{
long result;
static int print_msg = 10;
/* rtas uses minutes */
interval = (interval + 59) / 60;
result = rtas_call(wdrtas_token_set_indicator, 3, 1, NULL,
WDRTAS_SURVEILLANCE_IND, 0, interval);
if (result < 0 && print_msg) {
pr_err("setting the watchdog to %i timeout failed: %li\n",
interval, result);
print_msg--;
}
return result;
}
#define WDRTAS_SP_SPI_LEN 4
/**
* wdrtas_get_interval - returns the current watchdog interval
* @fallback_value: value (in seconds) to use, if the RTAS call fails
*
* returns the interval
*
* wdrtas_get_interval returns the current watchdog keepalive interval
* as reported by the RTAS function ibm,get-system-parameter. The unit
* of the return value is seconds.
*/
static int wdrtas_get_interval(int fallback_value)
{
long result;
char value[WDRTAS_SP_SPI_LEN];
spin_lock(&rtas_data_buf_lock);
memset(rtas_data_buf, 0, WDRTAS_SP_SPI_LEN);
result = rtas_call(wdrtas_token_get_sp, 3, 1, NULL,
WDRTAS_SP_SPI, __pa(rtas_data_buf),
WDRTAS_SP_SPI_LEN);
memcpy(value, rtas_data_buf, WDRTAS_SP_SPI_LEN);
spin_unlock(&rtas_data_buf_lock);
if (value[0] != 0 || value[1] != 2 || value[3] != 0 || result < 0) {
pr_warn("could not get sp_spi watchdog timeout (%li). Continuing\n",
result);
return fallback_value;
}
/* rtas uses minutes */
return ((int)value[2]) * 60;
}
/**
* wdrtas_timer_start - starts watchdog
*
* wdrtas_timer_start starts the watchdog by calling the RTAS function
* set-interval (surveillance)
*/
static void wdrtas_timer_start(void)
{
wdrtas_set_interval(wdrtas_interval);
}
/**
* wdrtas_timer_stop - stops watchdog
*
* wdrtas_timer_stop stops the watchdog timer by calling the RTAS function
* set-interval (surveillance)
*/
static void wdrtas_timer_stop(void)
{
wdrtas_set_interval(0);
}
/**
* wdrtas_timer_keepalive - resets watchdog timer to keep system alive
*
* wdrtas_timer_keepalive restarts the watchdog timer by calling the
* RTAS function event-scan and repeats these calls as long as there are
* events available. All events will be dumped.
*/
static void wdrtas_timer_keepalive(void)
{
long result;
do {
result = rtas_call(wdrtas_token_event_scan, 4, 1, NULL,
RTAS_EVENT_SCAN_ALL_EVENTS, 0,
(void *)__pa(wdrtas_logbuffer),
WDRTAS_LOGBUFFER_LEN);
if (result < 0)
pr_err("event-scan failed: %li\n", result);
if (result == 0)
print_hex_dump(KERN_INFO, "dumping event, data: ",
DUMP_PREFIX_OFFSET, 16, 1,
wdrtas_logbuffer, WDRTAS_LOGBUFFER_LEN, false);
} while (result == 0);
}
/**
* wdrtas_get_temperature - returns current temperature
*
* returns temperature or <0 on failures
*
* wdrtas_get_temperature returns the current temperature in Fahrenheit. It
* uses the RTAS call get-sensor-state, token 3 to do so
*/
static int wdrtas_get_temperature(void)
{
int result;
int temperature = 0;
result = rtas_get_sensor(WDRTAS_THERMAL_SENSOR, 0, &temperature);
if (result < 0)
pr_warn("reading the thermal sensor failed: %i\n", result);
else
temperature = ((temperature * 9) / 5) + 32; /* fahrenheit */
return temperature;
}
/**
* wdrtas_get_status - returns the status of the watchdog
*
* returns a bitmask of defines WDIOF_... as defined in
* include/linux/watchdog.h
*/
static int wdrtas_get_status(void)
{
return 0; /* TODO */
}
/**
* wdrtas_get_boot_status - returns the reason for the last boot
*
* returns a bitmask of defines WDIOF_... as defined in
* include/linux/watchdog.h, indicating why the watchdog rebooted the system
*/
static int wdrtas_get_boot_status(void)
{
return 0; /* TODO */
}
/*** watchdog API and operations stuff */
/* wdrtas_write - called when watchdog device is written to
* @file: file structure
* @buf: user buffer with data
* @len: amount to data written
* @ppos: position in file
*
* returns the number of successfully processed characters, which is always
* the number of bytes passed to this function
*
* wdrtas_write processes all the data given to it and looks for the magic
* character 'V'. This character allows the watchdog device to be closed
* properly.
*/
static ssize_t wdrtas_write(struct file *file, const char __user *buf,
size_t len, loff_t *ppos)
{
int i;
char c;
if (!len)
goto out;
if (!wdrtas_nowayout) {
wdrtas_expect_close = 0;
/* look for 'V' */
for (i = 0; i < len; i++) {
if (get_user(c, buf + i))
return -EFAULT;
/* allow to close device */
if (c == 'V')
wdrtas_expect_close = WDRTAS_MAGIC_CHAR;
}
}
wdrtas_timer_keepalive();
out:
return len;
}
/**
* wdrtas_ioctl - ioctl function for the watchdog device
* @file: file structure
* @cmd: command for ioctl
* @arg: argument pointer
*
* returns 0 on success, <0 on failure
*
* wdrtas_ioctl implements the watchdog API ioctls
*/
static long wdrtas_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int __user *argp = (void __user *)arg;
int i;
static const struct watchdog_info wdinfo = {
.options = WDRTAS_SUPPORTED_MASK,
.firmware_version = 0,
.identity = "wdrtas",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &wdinfo, sizeof(wdinfo)))
return -EFAULT;
return 0;
case WDIOC_GETSTATUS:
i = wdrtas_get_status();
return put_user(i, argp);
case WDIOC_GETBOOTSTATUS:
i = wdrtas_get_boot_status();
return put_user(i, argp);
case WDIOC_GETTEMP:
if (wdrtas_token_get_sensor_state == RTAS_UNKNOWN_SERVICE)
return -EOPNOTSUPP;
i = wdrtas_get_temperature();
return put_user(i, argp);
case WDIOC_SETOPTIONS:
if (get_user(i, argp))
return -EFAULT;
if (i & WDIOS_DISABLECARD)
wdrtas_timer_stop();
if (i & WDIOS_ENABLECARD) {
wdrtas_timer_keepalive();
wdrtas_timer_start();
}
/* not implemented. Done by H8
if (i & WDIOS_TEMPPANIC) {
} */
return 0;
case WDIOC_KEEPALIVE:
wdrtas_timer_keepalive();
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(i, argp))
return -EFAULT;
if (wdrtas_set_interval(i))
return -EINVAL;
wdrtas_timer_keepalive();
if (wdrtas_token_get_sp == RTAS_UNKNOWN_SERVICE)
wdrtas_interval = i;
else
wdrtas_interval = wdrtas_get_interval(i);
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(wdrtas_interval, argp);
default:
return -ENOTTY;
}
}
/**
* wdrtas_open - open function of watchdog device
* @inode: inode structure
* @file: file structure
*
* returns 0 on success, -EBUSY if the file has been opened already, <0 on
* other failures
*
* function called when watchdog device is opened
*/
static int wdrtas_open(struct inode *inode, struct file *file)
{
/* only open once */
if (atomic_inc_return(&wdrtas_miscdev_open) > 1) {
atomic_dec(&wdrtas_miscdev_open);
return -EBUSY;
}
wdrtas_timer_start();
wdrtas_timer_keepalive();
return stream_open(inode, file);
}
/**
* wdrtas_close - close function of watchdog device
* @inode: inode structure
* @file: file structure
*
* returns 0 on success
*
* close function. Always succeeds
*/
static int wdrtas_close(struct inode *inode, struct file *file)
{
/* only stop watchdog, if this was announced using 'V' before */
if (wdrtas_expect_close == WDRTAS_MAGIC_CHAR)
wdrtas_timer_stop();
else {
pr_warn("got unexpected close. Watchdog not stopped.\n");
wdrtas_timer_keepalive();
}
wdrtas_expect_close = 0;
atomic_dec(&wdrtas_miscdev_open);
return 0;
}
/**
* wdrtas_temp_read - gives back the temperature in fahrenheit
* @file: file structure
* @buf: user buffer
* @count: number of bytes to be read
* @ppos: position in file
*
* returns always 1 or -EFAULT in case of user space copy failures, <0 on
* other failures
*
* wdrtas_temp_read gives the temperature to the users by copying this
* value as one byte into the user space buffer. The unit is Fahrenheit...
*/
static ssize_t wdrtas_temp_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
int temperature = 0;
temperature = wdrtas_get_temperature();
if (temperature < 0)
return temperature;
if (copy_to_user(buf, &temperature, 1))
return -EFAULT;
return 1;
}
/**
* wdrtas_temp_open - open function of temperature device
* @inode: inode structure
* @file: file structure
*
* returns 0 on success, <0 on failure
*
* function called when temperature device is opened
*/
static int wdrtas_temp_open(struct inode *inode, struct file *file)
{
return stream_open(inode, file);
}
/**
* wdrtas_temp_close - close function of temperature device
* @inode: inode structure
* @file: file structure
*
* returns 0 on success
*
* close function. Always succeeds
*/
static int wdrtas_temp_close(struct inode *inode, struct file *file)
{
return 0;
}
/**
* wdrtas_reboot - reboot notifier function
* @nb: notifier block structure
* @code: reboot code
* @ptr: unused
*
* returns NOTIFY_DONE
*
* wdrtas_reboot stops the watchdog in case of a reboot
*/
static int wdrtas_reboot(struct notifier_block *this,
unsigned long code, void *ptr)
{
if (code == SYS_DOWN || code == SYS_HALT)
wdrtas_timer_stop();
return NOTIFY_DONE;
}
/*** initialization stuff */
static const struct file_operations wdrtas_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = wdrtas_write,
.unlocked_ioctl = wdrtas_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = wdrtas_open,
.release = wdrtas_close,
};
static struct miscdevice wdrtas_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wdrtas_fops,
};
static const struct file_operations wdrtas_temp_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.read = wdrtas_temp_read,
.open = wdrtas_temp_open,
.release = wdrtas_temp_close,
};
static struct miscdevice wdrtas_tempdev = {
.minor = TEMP_MINOR,
.name = "temperature",
.fops = &wdrtas_temp_fops,
};
static struct notifier_block wdrtas_notifier = {
.notifier_call = wdrtas_reboot,
};
/**
* wdrtas_get_tokens - reads in RTAS tokens
*
* returns 0 on success, <0 on failure
*
* wdrtas_get_tokens reads in the tokens for the RTAS calls used in
* this watchdog driver. It tolerates, if "get-sensor-state" and
* "ibm,get-system-parameter" are not available.
*/
static int wdrtas_get_tokens(void)
{
wdrtas_token_get_sensor_state = rtas_token("get-sensor-state");
if (wdrtas_token_get_sensor_state == RTAS_UNKNOWN_SERVICE) {
pr_warn("couldn't get token for get-sensor-state. Trying to continue without temperature support.\n");
}
wdrtas_token_get_sp = rtas_token("ibm,get-system-parameter");
if (wdrtas_token_get_sp == RTAS_UNKNOWN_SERVICE) {
pr_warn("couldn't get token for ibm,get-system-parameter. Trying to continue with a default timeout value of %i seconds.\n",
WDRTAS_DEFAULT_INTERVAL);
}
wdrtas_token_set_indicator = rtas_token("set-indicator");
if (wdrtas_token_set_indicator == RTAS_UNKNOWN_SERVICE) {
pr_err("couldn't get token for set-indicator. Terminating watchdog code.\n");
return -EIO;
}
wdrtas_token_event_scan = rtas_token("event-scan");
if (wdrtas_token_event_scan == RTAS_UNKNOWN_SERVICE) {
pr_err("couldn't get token for event-scan. Terminating watchdog code.\n");
return -EIO;
}
return 0;
}
/**
* wdrtas_unregister_devs - unregisters the misc dev handlers
*
* wdrtas_register_devs unregisters the watchdog and temperature watchdog
* misc devs
*/
static void wdrtas_unregister_devs(void)
{
misc_deregister(&wdrtas_miscdev);
if (wdrtas_token_get_sensor_state != RTAS_UNKNOWN_SERVICE)
misc_deregister(&wdrtas_tempdev);
}
/**
* wdrtas_register_devs - registers the misc dev handlers
*
* returns 0 on success, <0 on failure
*
* wdrtas_register_devs registers the watchdog and temperature watchdog
* misc devs
*/
static int wdrtas_register_devs(void)
{
int result;
result = misc_register(&wdrtas_miscdev);
if (result) {
pr_err("couldn't register watchdog misc device. Terminating watchdog code.\n");
return result;
}
if (wdrtas_token_get_sensor_state != RTAS_UNKNOWN_SERVICE) {
result = misc_register(&wdrtas_tempdev);
if (result) {
pr_warn("couldn't register watchdog temperature misc device. Continuing without temperature support.\n");
wdrtas_token_get_sensor_state = RTAS_UNKNOWN_SERVICE;
}
}
return 0;
}
/**
* wdrtas_init - init function of the watchdog driver
*
* returns 0 on success, <0 on failure
*
* registers the file handlers and the reboot notifier
*/
static int __init wdrtas_init(void)
{
if (wdrtas_get_tokens())
return -ENODEV;
if (wdrtas_register_devs())
return -ENODEV;
if (register_reboot_notifier(&wdrtas_notifier)) {
pr_err("could not register reboot notifier. Terminating watchdog code.\n");
wdrtas_unregister_devs();
return -ENODEV;
}
if (wdrtas_token_get_sp == RTAS_UNKNOWN_SERVICE)
wdrtas_interval = WDRTAS_DEFAULT_INTERVAL;
else
wdrtas_interval = wdrtas_get_interval(WDRTAS_DEFAULT_INTERVAL);
return 0;
}
/**
* wdrtas_exit - exit function of the watchdog driver
*
* unregisters the file handlers and the reboot notifier
*/
static void __exit wdrtas_exit(void)
{
if (!wdrtas_nowayout)
wdrtas_timer_stop();
wdrtas_unregister_devs();
unregister_reboot_notifier(&wdrtas_notifier);
}
module_init(wdrtas_init);
module_exit(wdrtas_exit);
| linux-master | drivers/watchdog/wdrtas.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* National Semiconductor PC87307/PC97307 (ala SC1200) WDT driver
* (c) Copyright 2002 Zwane Mwaikambo <[email protected]>,
* All Rights Reserved.
* Based on wdt.c and wdt977.c by Alan Cox and Woody Suwalski respectively.
*
* The author(s) of this software shall not be held liable for damages
* of any nature resulting due to the use of this software. This
* software is provided AS-IS with no warranties.
*
* Changelog:
* 20020220 Zwane Mwaikambo Code based on datasheet, no hardware.
* 20020221 Zwane Mwaikambo Cleanups as suggested by Jeff Garzik
* and Alan Cox.
* 20020222 Zwane Mwaikambo Added probing.
* 20020225 Zwane Mwaikambo Added ISAPNP support.
* 20020412 Rob Radez Broke out start/stop functions
* <[email protected]> Return proper status instead of
* temperature warning
* Add WDIOC_GETBOOTSTATUS and
* WDIOC_SETOPTIONS ioctls
* Fix CONFIG_WATCHDOG_NOWAYOUT
* 20020530 Joel Becker Add Matt Domsch's nowayout module
* option
* 20030116 Adam Belay Updated to the latest pnp code
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/pnp.h>
#include <linux/fs.h>
#include <linux/semaphore.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#define SC1200_MODULE_VER "build 20020303"
#define SC1200_MODULE_NAME "sc1200wdt"
#define MAX_TIMEOUT 255 /* 255 minutes */
#define PMIR (io) /* Power Management Index Register */
#define PMDR (io+1) /* Power Management Data Register */
/* Data Register indexes */
#define FER1 0x00 /* Function enable register 1 */
#define FER2 0x01 /* Function enable register 2 */
#define PMC1 0x02 /* Power Management Ctrl 1 */
#define PMC2 0x03 /* Power Management Ctrl 2 */
#define PMC3 0x04 /* Power Management Ctrl 3 */
#define WDTO 0x05 /* Watchdog timeout register */
#define WDCF 0x06 /* Watchdog config register */
#define WDST 0x07 /* Watchdog status register */
/* WDCF bitfields - which devices assert WDO */
#define KBC_IRQ 0x01 /* Keyboard Controller */
#define MSE_IRQ 0x02 /* Mouse */
#define UART1_IRQ 0x03 /* Serial0 */
#define UART2_IRQ 0x04 /* Serial1 */
/* 5 -7 are reserved */
static int timeout = 1;
static int io = -1;
static int io_len = 2; /* for non plug and play */
static unsigned long open_flag;
static char expect_close;
static DEFINE_SPINLOCK(sc1200wdt_lock); /* io port access serialisation */
#if defined CONFIG_PNP
static int isapnp = 1;
static struct pnp_dev *wdt_dev;
module_param(isapnp, int, 0);
MODULE_PARM_DESC(isapnp,
"When set to 0 driver ISA PnP support will be disabled");
#endif
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, "io port");
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "range is 0-255 minutes, default is 1");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/* Read from Data Register */
static inline void __sc1200wdt_read_data(unsigned char index,
unsigned char *data)
{
outb_p(index, PMIR);
*data = inb(PMDR);
}
static void sc1200wdt_read_data(unsigned char index, unsigned char *data)
{
spin_lock(&sc1200wdt_lock);
__sc1200wdt_read_data(index, data);
spin_unlock(&sc1200wdt_lock);
}
/* Write to Data Register */
static inline void __sc1200wdt_write_data(unsigned char index,
unsigned char data)
{
outb_p(index, PMIR);
outb(data, PMDR);
}
static inline void sc1200wdt_write_data(unsigned char index,
unsigned char data)
{
spin_lock(&sc1200wdt_lock);
__sc1200wdt_write_data(index, data);
spin_unlock(&sc1200wdt_lock);
}
static void sc1200wdt_start(void)
{
unsigned char reg;
spin_lock(&sc1200wdt_lock);
__sc1200wdt_read_data(WDCF, ®);
/* assert WDO when any of the following interrupts are triggered too */
reg |= (KBC_IRQ | MSE_IRQ | UART1_IRQ | UART2_IRQ);
__sc1200wdt_write_data(WDCF, reg);
/* set the timeout and get the ball rolling */
__sc1200wdt_write_data(WDTO, timeout);
spin_unlock(&sc1200wdt_lock);
}
static void sc1200wdt_stop(void)
{
sc1200wdt_write_data(WDTO, 0);
}
/* This returns the status of the WDO signal, inactive high. */
static inline int sc1200wdt_status(void)
{
unsigned char ret;
sc1200wdt_read_data(WDST, &ret);
/* If the bit is inactive, the watchdog is enabled, so return
* KEEPALIVEPING which is a bit of a kludge because there's nothing
* else for enabled/disabled status
*/
return (ret & 0x01) ? 0 : WDIOF_KEEPALIVEPING;
}
static int sc1200wdt_open(struct inode *inode, struct file *file)
{
/* allow one at a time */
if (test_and_set_bit(0, &open_flag))
return -EBUSY;
if (timeout > MAX_TIMEOUT)
timeout = MAX_TIMEOUT;
sc1200wdt_start();
pr_info("Watchdog enabled, timeout = %d min(s)", timeout);
return stream_open(inode, file);
}
static long sc1200wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int new_timeout;
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE,
.firmware_version = 0,
.identity = "PC87307/PC97307",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user(argp, &ident, sizeof(ident)))
return -EFAULT;
return 0;
case WDIOC_GETSTATUS:
return put_user(sc1200wdt_status(), p);
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
int options, retval = -EINVAL;
if (get_user(options, p))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
sc1200wdt_stop();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
sc1200wdt_start();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
sc1200wdt_write_data(WDTO, timeout);
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_timeout, p))
return -EFAULT;
/* the API states this is given in secs */
new_timeout /= 60;
if (new_timeout < 0 || new_timeout > MAX_TIMEOUT)
return -EINVAL;
timeout = new_timeout;
sc1200wdt_write_data(WDTO, timeout);
fallthrough; /* and return the new timeout */
case WDIOC_GETTIMEOUT:
return put_user(timeout * 60, p);
default:
return -ENOTTY;
}
}
static int sc1200wdt_release(struct inode *inode, struct file *file)
{
if (expect_close == 42) {
sc1200wdt_stop();
pr_info("Watchdog disabled\n");
} else {
sc1200wdt_write_data(WDTO, timeout);
pr_crit("Unexpected close!, timeout = %d min(s)\n", timeout);
}
clear_bit(0, &open_flag);
expect_close = 0;
return 0;
}
static ssize_t sc1200wdt_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
if (len) {
if (!nowayout) {
size_t i;
expect_close = 0;
for (i = 0; i != len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
sc1200wdt_write_data(WDTO, timeout);
return len;
}
return 0;
}
static int sc1200wdt_notify_sys(struct notifier_block *this,
unsigned long code, void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
sc1200wdt_stop();
return NOTIFY_DONE;
}
static struct notifier_block sc1200wdt_notifier = {
.notifier_call = sc1200wdt_notify_sys,
};
static const struct file_operations sc1200wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = sc1200wdt_write,
.unlocked_ioctl = sc1200wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = sc1200wdt_open,
.release = sc1200wdt_release,
};
static struct miscdevice sc1200wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &sc1200wdt_fops,
};
static int __init sc1200wdt_probe(void)
{
/* The probe works by reading the PMC3 register's default value of 0x0e
* there is one caveat, if the device disables the parallel port or any
* of the UARTs we won't be able to detect it.
* NB. This could be done with accuracy by reading the SID registers,
* but we don't have access to those io regions.
*/
unsigned char reg;
sc1200wdt_read_data(PMC3, ®);
reg &= 0x0f; /* we don't want the UART busy bits */
return (reg == 0x0e) ? 0 : -ENODEV;
}
#if defined CONFIG_PNP
static const struct pnp_device_id scl200wdt_pnp_devices[] = {
/* National Semiconductor PC87307/PC97307 watchdog component */
{.id = "NSC0800", .driver_data = 0},
{.id = ""},
};
static int scl200wdt_pnp_probe(struct pnp_dev *dev,
const struct pnp_device_id *dev_id)
{
/* this driver only supports one card at a time */
if (wdt_dev || !isapnp)
return -EBUSY;
wdt_dev = dev;
io = pnp_port_start(wdt_dev, 0);
io_len = pnp_port_len(wdt_dev, 0);
if (!request_region(io, io_len, SC1200_MODULE_NAME)) {
pr_err("Unable to register IO port %#x\n", io);
return -EBUSY;
}
pr_info("PnP device found at io port %#x/%d\n", io, io_len);
return 0;
}
static void scl200wdt_pnp_remove(struct pnp_dev *dev)
{
if (wdt_dev) {
release_region(io, io_len);
wdt_dev = NULL;
}
}
static struct pnp_driver scl200wdt_pnp_driver = {
.name = "scl200wdt",
.id_table = scl200wdt_pnp_devices,
.probe = scl200wdt_pnp_probe,
.remove = scl200wdt_pnp_remove,
};
#endif /* CONFIG_PNP */
static int __init sc1200wdt_init(void)
{
int ret;
pr_info("%s\n", SC1200_MODULE_VER);
#if defined CONFIG_PNP
if (isapnp) {
ret = pnp_register_driver(&scl200wdt_pnp_driver);
if (ret)
goto out_clean;
}
#endif
if (io == -1) {
pr_err("io parameter must be specified\n");
ret = -EINVAL;
goto out_pnp;
}
#if defined CONFIG_PNP
/* now that the user has specified an IO port and we haven't detected
* any devices, disable pnp support */
if (isapnp)
pnp_unregister_driver(&scl200wdt_pnp_driver);
isapnp = 0;
#endif
if (!request_region(io, io_len, SC1200_MODULE_NAME)) {
pr_err("Unable to register IO port %#x\n", io);
ret = -EBUSY;
goto out_pnp;
}
ret = sc1200wdt_probe();
if (ret)
goto out_io;
ret = register_reboot_notifier(&sc1200wdt_notifier);
if (ret) {
pr_err("Unable to register reboot notifier err = %d\n", ret);
goto out_io;
}
ret = misc_register(&sc1200wdt_miscdev);
if (ret) {
pr_err("Unable to register miscdev on minor %d\n",
WATCHDOG_MINOR);
goto out_rbt;
}
/* ret = 0 */
out_clean:
return ret;
out_rbt:
unregister_reboot_notifier(&sc1200wdt_notifier);
out_io:
release_region(io, io_len);
out_pnp:
#if defined CONFIG_PNP
if (isapnp)
pnp_unregister_driver(&scl200wdt_pnp_driver);
#endif
goto out_clean;
}
static void __exit sc1200wdt_exit(void)
{
misc_deregister(&sc1200wdt_miscdev);
unregister_reboot_notifier(&sc1200wdt_notifier);
#if defined CONFIG_PNP
if (isapnp)
pnp_unregister_driver(&scl200wdt_pnp_driver);
else
#endif
release_region(io, io_len);
}
module_init(sc1200wdt_init);
module_exit(sc1200wdt_exit);
MODULE_AUTHOR("Zwane Mwaikambo <[email protected]>");
MODULE_DESCRIPTION(
"Driver for National Semiconductor PC87307/PC97307 watchdog component");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sc1200wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Wdt977 0.04: A Watchdog Device for Netwinder W83977AF chip
*
* (c) Copyright 1998 Rebel.com (Woody Suwalski <[email protected]>)
*
* -----------------------
*
* -----------------------
* 14-Dec-2001 Matt Domsch <[email protected]>
* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
* 19-Dec-2001 Woody Suwalski: Netwinder fixes, ioctl interface
* 06-Jan-2002 Woody Suwalski: For compatibility, convert all timeouts
* from minutes to seconds.
* 07-Jul-2003 Daniele Bellucci: Audit return code of misc_register in
* nwwatchdog_init.
* 25-Oct-2005 Woody Suwalski: Convert addresses to #defs, add spinlocks
* remove limitiation to be used on
* Netwinders only
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/watchdog.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <asm/mach-types.h>
#define WATCHDOG_VERSION "0.04"
#define WATCHDOG_NAME "Wdt977"
#define IO_INDEX_PORT 0x370 /* on some systems it can be 0x3F0 */
#define IO_DATA_PORT (IO_INDEX_PORT + 1)
#define UNLOCK_DATA 0x87
#define LOCK_DATA 0xAA
#define DEVICE_REGISTER 0x07
#define DEFAULT_TIMEOUT 60 /* default timeout in seconds */
static int timeout = DEFAULT_TIMEOUT;
static int timeoutM; /* timeout in minutes */
static unsigned long timer_alive;
static int testmode;
static char expect_close;
static DEFINE_SPINLOCK(spinlock);
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (60..15300, default="
__MODULE_STRING(DEFAULT_TIMEOUT) ")");
module_param(testmode, int, 0);
MODULE_PARM_DESC(testmode, "Watchdog testmode (1 = no reboot), default=0");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Start the watchdog
*/
static int wdt977_start(void)
{
unsigned long flags;
spin_lock_irqsave(&spinlock, flags);
/* unlock the SuperIO chip */
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
/* select device Aux2 (device=8) and set watchdog regs F2, F3 and F4
* F2 has the timeout in minutes
* F3 could be set to the POWER LED blink (with GP17 set to PowerLed)
* at timeout, and to reset timer on kbd/mouse activity (not impl.)
* F4 is used to just clear the TIMEOUT'ed state (bit 0)
*/
outb_p(DEVICE_REGISTER, IO_INDEX_PORT);
outb_p(0x08, IO_DATA_PORT);
outb_p(0xF2, IO_INDEX_PORT);
outb_p(timeoutM, IO_DATA_PORT);
outb_p(0xF3, IO_INDEX_PORT);
outb_p(0x00, IO_DATA_PORT); /* another setting is 0E for
kbd/mouse/LED */
outb_p(0xF4, IO_INDEX_PORT);
outb_p(0x00, IO_DATA_PORT);
/* At last select device Aux1 (dev=7) and set GP16 as a
* watchdog output. In test mode watch the bit 1 on F4 to
* indicate "triggered"
*/
if (!testmode) {
outb_p(DEVICE_REGISTER, IO_INDEX_PORT);
outb_p(0x07, IO_DATA_PORT);
outb_p(0xE6, IO_INDEX_PORT);
outb_p(0x08, IO_DATA_PORT);
}
/* lock the SuperIO chip */
outb_p(LOCK_DATA, IO_INDEX_PORT);
spin_unlock_irqrestore(&spinlock, flags);
pr_info("activated\n");
return 0;
}
/*
* Stop the watchdog
*/
static int wdt977_stop(void)
{
unsigned long flags;
spin_lock_irqsave(&spinlock, flags);
/* unlock the SuperIO chip */
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
/* select device Aux2 (device=8) and set watchdog regs F2,F3 and F4
* F3 is reset to its default state
* F4 can clear the TIMEOUT'ed state (bit 0) - back to default
* We can not use GP17 as a PowerLed, as we use its usage as a RedLed
*/
outb_p(DEVICE_REGISTER, IO_INDEX_PORT);
outb_p(0x08, IO_DATA_PORT);
outb_p(0xF2, IO_INDEX_PORT);
outb_p(0xFF, IO_DATA_PORT);
outb_p(0xF3, IO_INDEX_PORT);
outb_p(0x00, IO_DATA_PORT);
outb_p(0xF4, IO_INDEX_PORT);
outb_p(0x00, IO_DATA_PORT);
outb_p(0xF2, IO_INDEX_PORT);
outb_p(0x00, IO_DATA_PORT);
/* at last select device Aux1 (dev=7) and set
GP16 as a watchdog output */
outb_p(DEVICE_REGISTER, IO_INDEX_PORT);
outb_p(0x07, IO_DATA_PORT);
outb_p(0xE6, IO_INDEX_PORT);
outb_p(0x08, IO_DATA_PORT);
/* lock the SuperIO chip */
outb_p(LOCK_DATA, IO_INDEX_PORT);
spin_unlock_irqrestore(&spinlock, flags);
pr_info("shutdown\n");
return 0;
}
/*
* Send a keepalive ping to the watchdog
* This is done by simply re-writing the timeout to reg. 0xF2
*/
static int wdt977_keepalive(void)
{
unsigned long flags;
spin_lock_irqsave(&spinlock, flags);
/* unlock the SuperIO chip */
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
/* select device Aux2 (device=8) and kicks watchdog reg F2 */
/* F2 has the timeout in minutes */
outb_p(DEVICE_REGISTER, IO_INDEX_PORT);
outb_p(0x08, IO_DATA_PORT);
outb_p(0xF2, IO_INDEX_PORT);
outb_p(timeoutM, IO_DATA_PORT);
/* lock the SuperIO chip */
outb_p(LOCK_DATA, IO_INDEX_PORT);
spin_unlock_irqrestore(&spinlock, flags);
return 0;
}
/*
* Set the watchdog timeout value
*/
static int wdt977_set_timeout(int t)
{
int tmrval;
/* convert seconds to minutes, rounding up */
tmrval = (t + 59) / 60;
if (machine_is_netwinder()) {
/* we have a hw bug somewhere, so each 977 minute is actually
* only 30sec. This limits the max timeout to half of device
* max of 255 minutes...
*/
tmrval += tmrval;
}
if (tmrval < 1 || tmrval > 255)
return -EINVAL;
/* timeout is the timeout in seconds, timeoutM is
the timeout in minutes) */
timeout = t;
timeoutM = tmrval;
return 0;
}
/*
* Get the watchdog status
*/
static int wdt977_get_status(int *status)
{
int new_status;
unsigned long flags;
spin_lock_irqsave(&spinlock, flags);
/* unlock the SuperIO chip */
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
outb_p(UNLOCK_DATA, IO_INDEX_PORT);
/* select device Aux2 (device=8) and read watchdog reg F4 */
outb_p(DEVICE_REGISTER, IO_INDEX_PORT);
outb_p(0x08, IO_DATA_PORT);
outb_p(0xF4, IO_INDEX_PORT);
new_status = inb_p(IO_DATA_PORT);
/* lock the SuperIO chip */
outb_p(LOCK_DATA, IO_INDEX_PORT);
spin_unlock_irqrestore(&spinlock, flags);
*status = 0;
if (new_status & 1)
*status |= WDIOF_CARDRESET;
return 0;
}
/*
* /dev/watchdog handling
*/
static int wdt977_open(struct inode *inode, struct file *file)
{
/* If the watchdog is alive we don't need to start it again */
if (test_and_set_bit(0, &timer_alive))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
wdt977_start();
return stream_open(inode, file);
}
static int wdt977_release(struct inode *inode, struct file *file)
{
/*
* Shut off the timer.
* Lock it in if it's a module and we set nowayout
*/
if (expect_close == 42) {
wdt977_stop();
clear_bit(0, &timer_alive);
} else {
wdt977_keepalive();
pr_crit("Unexpected close, not stopping watchdog!\n");
}
expect_close = 0;
return 0;
}
/*
* wdt977_write:
* @file: file handle to the watchdog
* @buf: buffer to write (unused as data does not matter here
* @count: count of bytes
* @ppos: pointer to the position to write. No seeks allowed
*
* A write to a watchdog device is defined as a keepalive signal. Any
* write of data will do, as we we don't define content meaning.
*/
static ssize_t wdt977_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count) {
if (!nowayout) {
size_t i;
/* In case it was set long ago */
expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
expect_close = 42;
}
}
/* someone wrote to us, we should restart timer */
wdt977_keepalive();
}
return count;
}
static const struct watchdog_info ident = {
.options = WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.firmware_version = 1,
.identity = WATCHDOG_NAME,
};
/*
* wdt977_ioctl:
* @inode: inode of the device
* @file: file handle to the device
* @cmd: watchdog command
* @arg: argument pointer
*
* The watchdog API defines a common set of functions for all watchdogs
* according to their available features.
*/
static long wdt977_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int status;
int new_options, retval = -EINVAL;
int new_timeout;
union {
struct watchdog_info __user *ident;
int __user *i;
} uarg;
uarg.i = (int __user *)arg;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(uarg.ident, &ident,
sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
wdt977_get_status(&status);
return put_user(status, uarg.i);
case WDIOC_GETBOOTSTATUS:
return put_user(0, uarg.i);
case WDIOC_SETOPTIONS:
if (get_user(new_options, uarg.i))
return -EFAULT;
if (new_options & WDIOS_DISABLECARD) {
wdt977_stop();
retval = 0;
}
if (new_options & WDIOS_ENABLECARD) {
wdt977_start();
retval = 0;
}
return retval;
case WDIOC_KEEPALIVE:
wdt977_keepalive();
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_timeout, uarg.i))
return -EFAULT;
if (wdt977_set_timeout(new_timeout))
return -EINVAL;
wdt977_keepalive();
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(timeout, uarg.i);
default:
return -ENOTTY;
}
}
static int wdt977_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
wdt977_stop();
return NOTIFY_DONE;
}
static const struct file_operations wdt977_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = wdt977_write,
.unlocked_ioctl = wdt977_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = wdt977_open,
.release = wdt977_release,
};
static struct miscdevice wdt977_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wdt977_fops,
};
static struct notifier_block wdt977_notifier = {
.notifier_call = wdt977_notify_sys,
};
static int __init wd977_init(void)
{
int rc;
pr_info("driver v%s\n", WATCHDOG_VERSION);
/* Check that the timeout value is within its range;
if not reset to the default */
if (wdt977_set_timeout(timeout)) {
wdt977_set_timeout(DEFAULT_TIMEOUT);
pr_info("timeout value must be 60 < timeout < 15300, using %d\n",
DEFAULT_TIMEOUT);
}
/* on Netwinder the IOports are already reserved by
* arch/arm/mach-footbridge/netwinder-hw.c
*/
if (!machine_is_netwinder()) {
if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) {
pr_err("I/O address 0x%04x already in use\n",
IO_INDEX_PORT);
rc = -EIO;
goto err_out;
}
}
rc = register_reboot_notifier(&wdt977_notifier);
if (rc) {
pr_err("cannot register reboot notifier (err=%d)\n", rc);
goto err_out_region;
}
rc = misc_register(&wdt977_miscdev);
if (rc) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
wdt977_miscdev.minor, rc);
goto err_out_reboot;
}
pr_info("initialized. timeout=%d sec (nowayout=%d, testmode=%i)\n",
timeout, nowayout, testmode);
return 0;
err_out_reboot:
unregister_reboot_notifier(&wdt977_notifier);
err_out_region:
if (!machine_is_netwinder())
release_region(IO_INDEX_PORT, 2);
err_out:
return rc;
}
static void __exit wd977_exit(void)
{
wdt977_stop();
misc_deregister(&wdt977_miscdev);
unregister_reboot_notifier(&wdt977_notifier);
release_region(IO_INDEX_PORT, 2);
}
module_init(wd977_init);
module_exit(wd977_exit);
MODULE_AUTHOR("Woody Suwalski <[email protected]>");
MODULE_DESCRIPTION("W83977AF Watchdog driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/wdt977.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* PIKA FPGA based Watchdog Timer
*
* Copyright (c) 2008 PIKA Technologies
* Sean MacLennan <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
#include <linux/bitops.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#define DRV_NAME "PIKA-WDT"
/* Hardware timeout in seconds */
#define WDT_HW_TIMEOUT 2
/* Timer heartbeat (500ms) */
#define WDT_TIMEOUT (HZ/2)
/* User land timeout */
#define WDT_HEARTBEAT 15
static int heartbeat = WDT_HEARTBEAT;
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
"(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static struct {
void __iomem *fpga;
unsigned long next_heartbeat; /* the next_heartbeat for the timer */
unsigned long open;
char expect_close;
int bootstatus;
struct timer_list timer; /* The timer that pings the watchdog */
} pikawdt_private;
static struct watchdog_info ident __ro_after_init = {
.identity = DRV_NAME,
.options = WDIOF_CARDRESET |
WDIOF_SETTIMEOUT |
WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
/*
* Reload the watchdog timer. (ie, pat the watchdog)
*/
static inline void pikawdt_reset(void)
{
/* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) --
* Bit 7, WTCHDG_EN: When set to 1, the watchdog timer is enabled.
* Once enabled, it cannot be disabled. The watchdog can be
* kicked by performing any write access to the reset
* control register (this register).
* Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in
* seconds. Valid ranges are 1 to 15 seconds. The value can
* be modified dynamically.
*/
unsigned reset = in_be32(pikawdt_private.fpga + 0x14);
/* enable with max timeout - 15 seconds */
reset |= (1 << 7) + (WDT_HW_TIMEOUT << 8);
out_be32(pikawdt_private.fpga + 0x14, reset);
}
/*
* Timer tick
*/
static void pikawdt_ping(struct timer_list *unused)
{
if (time_before(jiffies, pikawdt_private.next_heartbeat) ||
(!nowayout && !pikawdt_private.open)) {
pikawdt_reset();
mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT);
} else
pr_crit("I will reset your machine !\n");
}
static void pikawdt_keepalive(void)
{
pikawdt_private.next_heartbeat = jiffies + heartbeat * HZ;
}
static void pikawdt_start(void)
{
pikawdt_keepalive();
mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT);
}
/*
* Watchdog device is opened, and watchdog starts running.
*/
static int pikawdt_open(struct inode *inode, struct file *file)
{
/* /dev/watchdog can only be opened once */
if (test_and_set_bit(0, &pikawdt_private.open))
return -EBUSY;
pikawdt_start();
return stream_open(inode, file);
}
/*
* Close the watchdog device.
*/
static int pikawdt_release(struct inode *inode, struct file *file)
{
/* stop internal ping */
if (!pikawdt_private.expect_close)
del_timer(&pikawdt_private.timer);
clear_bit(0, &pikawdt_private.open);
pikawdt_private.expect_close = 0;
return 0;
}
/*
* Pat the watchdog whenever device is written to.
*/
static ssize_t pikawdt_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
if (!len)
return 0;
/* Scan for magic character */
if (!nowayout) {
size_t i;
pikawdt_private.expect_close = 0;
for (i = 0; i < len; i++) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V') {
pikawdt_private.expect_close = 42;
break;
}
}
}
pikawdt_keepalive();
return len;
}
/*
* Handle commands from user-space.
*/
static long pikawdt_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
int new_value;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
return put_user(0, p);
case WDIOC_GETBOOTSTATUS:
return put_user(pikawdt_private.bootstatus, p);
case WDIOC_KEEPALIVE:
pikawdt_keepalive();
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_value, p))
return -EFAULT;
heartbeat = new_value;
pikawdt_keepalive();
return put_user(new_value, p); /* return current value */
case WDIOC_GETTIMEOUT:
return put_user(heartbeat, p);
}
return -ENOTTY;
}
static const struct file_operations pikawdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.open = pikawdt_open,
.release = pikawdt_release,
.write = pikawdt_write,
.unlocked_ioctl = pikawdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
};
static struct miscdevice pikawdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &pikawdt_fops,
};
static int __init pikawdt_init(void)
{
struct device_node *np;
void __iomem *fpga;
u32 post1;
int ret;
np = of_find_compatible_node(NULL, NULL, "pika,fpga");
if (np == NULL) {
pr_err("Unable to find fpga\n");
return -ENOENT;
}
pikawdt_private.fpga = of_iomap(np, 0);
of_node_put(np);
if (pikawdt_private.fpga == NULL) {
pr_err("Unable to map fpga\n");
return -ENOMEM;
}
ident.firmware_version = in_be32(pikawdt_private.fpga + 0x1c) & 0xffff;
/* POST information is in the sd area. */
np = of_find_compatible_node(NULL, NULL, "pika,fpga-sd");
if (np == NULL) {
pr_err("Unable to find fpga-sd\n");
ret = -ENOENT;
goto out;
}
fpga = of_iomap(np, 0);
of_node_put(np);
if (fpga == NULL) {
pr_err("Unable to map fpga-sd\n");
ret = -ENOMEM;
goto out;
}
/* -- FPGA: POST Test Results Register 1 (32bit R/W) (Offset: 0x4040) --
* Bit 31, WDOG: Set to 1 when the last reset was caused by a watchdog
* timeout.
*/
post1 = in_be32(fpga + 0x40);
if (post1 & 0x80000000)
pikawdt_private.bootstatus = WDIOF_CARDRESET;
iounmap(fpga);
timer_setup(&pikawdt_private.timer, pikawdt_ping, 0);
ret = misc_register(&pikawdt_miscdev);
if (ret) {
pr_err("Unable to register miscdev\n");
goto out;
}
pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
heartbeat, nowayout);
return 0;
out:
iounmap(pikawdt_private.fpga);
return ret;
}
static void __exit pikawdt_exit(void)
{
misc_deregister(&pikawdt_miscdev);
iounmap(pikawdt_private.fpga);
}
module_init(pikawdt_init);
module_exit(pikawdt_exit);
MODULE_AUTHOR("Sean MacLennan <[email protected]>");
MODULE_DESCRIPTION("PIKA FPGA based Watchdog Timer");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/pika_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2011-2013
*
* Author: Mathieu Poirier <[email protected]> for ST-Ericsson
* Author: Jonas Aaberg <[email protected]> for ST-Ericsson
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/err.h>
#include <linux/uaccess.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/mfd/dbx500-prcmu.h>
#define WATCHDOG_TIMEOUT 600 /* 10 minutes */
#define WATCHDOG_MIN 0
#define WATCHDOG_MAX28 268435 /* 28 bit resolution in ms == 268435.455 s */
static unsigned int timeout = WATCHDOG_TIMEOUT;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static int db8500_wdt_start(struct watchdog_device *wdd)
{
return prcmu_enable_a9wdog(PRCMU_WDOG_ALL);
}
static int db8500_wdt_stop(struct watchdog_device *wdd)
{
return prcmu_disable_a9wdog(PRCMU_WDOG_ALL);
}
static int db8500_wdt_keepalive(struct watchdog_device *wdd)
{
return prcmu_kick_a9wdog(PRCMU_WDOG_ALL);
}
static int db8500_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
db8500_wdt_stop(wdd);
prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
db8500_wdt_start(wdd);
return 0;
}
static const struct watchdog_info db8500_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.identity = "DB8500 WDT",
.firmware_version = 1,
};
static const struct watchdog_ops db8500_wdt_ops = {
.owner = THIS_MODULE,
.start = db8500_wdt_start,
.stop = db8500_wdt_stop,
.ping = db8500_wdt_keepalive,
.set_timeout = db8500_wdt_set_timeout,
};
static struct watchdog_device db8500_wdt = {
.info = &db8500_wdt_info,
.ops = &db8500_wdt_ops,
.min_timeout = WATCHDOG_MIN,
.max_timeout = WATCHDOG_MAX28,
};
static int db8500_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret;
timeout = 600; /* Default to 10 minutes */
db8500_wdt.parent = dev;
watchdog_set_nowayout(&db8500_wdt, nowayout);
/* disable auto off on sleep */
prcmu_config_a9wdog(PRCMU_WDOG_CPU1, false);
/* set HW initial value */
prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
ret = devm_watchdog_register_device(dev, &db8500_wdt);
if (ret)
return ret;
dev_info(dev, "initialized\n");
return 0;
}
static int db8500_wdt_suspend(struct platform_device *pdev,
pm_message_t state)
{
if (watchdog_active(&db8500_wdt)) {
db8500_wdt_stop(&db8500_wdt);
prcmu_config_a9wdog(PRCMU_WDOG_CPU1, true);
prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
db8500_wdt_start(&db8500_wdt);
}
return 0;
}
static int db8500_wdt_resume(struct platform_device *pdev)
{
if (watchdog_active(&db8500_wdt)) {
db8500_wdt_stop(&db8500_wdt);
prcmu_config_a9wdog(PRCMU_WDOG_CPU1, false);
prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
db8500_wdt_start(&db8500_wdt);
}
return 0;
}
static struct platform_driver db8500_wdt_driver = {
.probe = db8500_wdt_probe,
.suspend = pm_ptr(db8500_wdt_suspend),
.resume = pm_ptr(db8500_wdt_resume),
.driver = {
.name = "db8500_wdt",
},
};
module_platform_driver(db8500_wdt_driver);
MODULE_AUTHOR("Jonas Aaberg <[email protected]>");
MODULE_DESCRIPTION("DB8500 Watchdog Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:db8500_wdt");
| linux-master | drivers/watchdog/db8500_wdt.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Eurotech CPU-1220/1410/1420 on board WDT driver
*
* (c) Copyright 2001 Ascensit <[email protected]>
* (c) Copyright 2001 Rodolfo Giometti <[email protected]>
* (c) Copyright 2002 Rob Radez <[email protected]>
*
* Based on wdt.c.
* Original copyright messages:
*
* (c) Copyright 1996-1997 Alan Cox <[email protected]>,
* All Rights Reserved.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <[email protected]>*
*/
/* Changelog:
*
* 2001 - Rodolfo Giometti
* Initial release
*
* 2002/04/25 - Rob Radez
* clean up #includes
* clean up locking
* make __setup param unique
* proper options in watchdog_info
* add WDIOC_GETSTATUS and WDIOC_SETOPTIONS ioctls
* add expect_close support
*
* 2002.05.30 - Joel Becker <[email protected]>
* Added Matt Domsch's nowayout module option.
*/
/*
* The eurotech CPU-1220/1410/1420's watchdog is a part
* of the on-board SUPER I/O device SMSC FDC 37B782.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/uaccess.h>
static unsigned long eurwdt_is_open;
static int eurwdt_timeout;
static char eur_expect_close;
static DEFINE_SPINLOCK(eurwdt_lock);
/*
* You must set these - there is no sane way to probe for this board.
*/
static int io = 0x3f0;
static int irq = 10;
static char *ev = "int";
#define WDT_TIMEOUT 60 /* 1 minute */
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* Some symbolic names
*/
#define WDT_CTRL_REG 0x30
#define WDT_OUTPIN_CFG 0xe2
#define WDT_EVENT_INT 0x00
#define WDT_EVENT_REBOOT 0x08
#define WDT_UNIT_SEL 0xf1
#define WDT_UNIT_SECS 0x80
#define WDT_TIMEOUT_VAL 0xf2
#define WDT_TIMER_CFG 0xf3
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, "Eurotech WDT io port (default=0x3f0)");
module_param_hw(irq, int, irq, 0);
MODULE_PARM_DESC(irq, "Eurotech WDT irq (default=10)");
module_param(ev, charp, 0);
MODULE_PARM_DESC(ev, "Eurotech WDT event type (default is `int')");
/*
* Programming support
*/
static inline void eurwdt_write_reg(u8 index, u8 data)
{
outb(index, io);
outb(data, io+1);
}
static inline void eurwdt_lock_chip(void)
{
outb(0xaa, io);
}
static inline void eurwdt_unlock_chip(void)
{
outb(0x55, io);
eurwdt_write_reg(0x07, 0x08); /* set the logical device */
}
static inline void eurwdt_set_timeout(int timeout)
{
eurwdt_write_reg(WDT_TIMEOUT_VAL, (u8) timeout);
}
static inline void eurwdt_disable_timer(void)
{
eurwdt_set_timeout(0);
}
static void eurwdt_activate_timer(void)
{
eurwdt_disable_timer();
eurwdt_write_reg(WDT_CTRL_REG, 0x01); /* activate the WDT */
eurwdt_write_reg(WDT_OUTPIN_CFG,
!strcmp("int", ev) ? WDT_EVENT_INT : WDT_EVENT_REBOOT);
/* Setting interrupt line */
if (irq == 2 || irq > 15 || irq < 0) {
pr_err("invalid irq number\n");
irq = 0; /* if invalid we disable interrupt */
}
if (irq == 0)
pr_info("interrupt disabled\n");
eurwdt_write_reg(WDT_TIMER_CFG, irq << 4);
eurwdt_write_reg(WDT_UNIT_SEL, WDT_UNIT_SECS); /* we use seconds */
eurwdt_set_timeout(0); /* the default timeout */
}
/*
* Kernel methods.
*/
static irqreturn_t eurwdt_interrupt(int irq, void *dev_id)
{
pr_crit("timeout WDT timeout\n");
#ifdef ONLY_TESTING
pr_crit("Would Reboot\n");
#else
pr_crit("Initiating system reboot\n");
emergency_restart();
#endif
return IRQ_HANDLED;
}
/**
* eurwdt_ping:
*
* Reload counter one with the watchdog timeout.
*/
static void eurwdt_ping(void)
{
/* Write the watchdog default value */
eurwdt_set_timeout(eurwdt_timeout);
}
/**
* eurwdt_write:
* @file: file handle to the watchdog
* @buf: buffer to write (unused as data does not matter here
* @count: count of bytes
* @ppos: pointer to the position to write. No seeks allowed
*
* A write to a watchdog device is defined as a keepalive signal. Any
* write of data will do, as we don't define content meaning.
*/
static ssize_t eurwdt_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count) {
if (!nowayout) {
size_t i;
eur_expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
eur_expect_close = 42;
}
}
spin_lock(&eurwdt_lock);
eurwdt_ping(); /* the default timeout */
spin_unlock(&eurwdt_lock);
}
return count;
}
/**
* eurwdt_ioctl:
* @file: file handle to the device
* @cmd: watchdog command
* @arg: argument pointer
*
* The watchdog API defines a common set of functions for all watchdogs
* according to their available features.
*/
static long eurwdt_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT
| WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = "WDT Eurotech CPU-1220/1410",
};
int time;
int options, retval = -EINVAL;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
if (get_user(options, p))
return -EFAULT;
spin_lock(&eurwdt_lock);
if (options & WDIOS_DISABLECARD) {
eurwdt_disable_timer();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
eurwdt_activate_timer();
eurwdt_ping();
retval = 0;
}
spin_unlock(&eurwdt_lock);
return retval;
case WDIOC_KEEPALIVE:
spin_lock(&eurwdt_lock);
eurwdt_ping();
spin_unlock(&eurwdt_lock);
return 0;
case WDIOC_SETTIMEOUT:
if (copy_from_user(&time, p, sizeof(int)))
return -EFAULT;
/* Sanity check */
if (time < 0 || time > 255)
return -EINVAL;
spin_lock(&eurwdt_lock);
eurwdt_timeout = time;
eurwdt_set_timeout(time);
spin_unlock(&eurwdt_lock);
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(eurwdt_timeout, p);
default:
return -ENOTTY;
}
}
/**
* eurwdt_open:
* @inode: inode of device
* @file: file handle to device
*
* The misc device has been opened. The watchdog device is single
* open and on opening we load the counter.
*/
static int eurwdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &eurwdt_is_open))
return -EBUSY;
eurwdt_timeout = WDT_TIMEOUT; /* initial timeout */
/* Activate the WDT */
eurwdt_activate_timer();
return stream_open(inode, file);
}
/**
* eurwdt_release:
* @inode: inode to board
* @file: file handle to board
*
* The watchdog has a configurable API. There is a religious dispute
* between people who want their watchdog to be able to shut down and
* those who want to be sure if the watchdog manager dies the machine
* reboots. In the former case we disable the counters, in the latter
* case you have to open it again very soon.
*/
static int eurwdt_release(struct inode *inode, struct file *file)
{
if (eur_expect_close == 42)
eurwdt_disable_timer();
else {
pr_crit("Unexpected close, not stopping watchdog!\n");
eurwdt_ping();
}
clear_bit(0, &eurwdt_is_open);
eur_expect_close = 0;
return 0;
}
/**
* eurwdt_notify_sys:
* @this: our notifier block
* @code: the event being reported
* @unused: unused
*
* Our notifier is called on system shutdowns. We want to turn the card
* off at reboot otherwise the machine will reboot again during memory
* test or worse yet during the following fsck. This would suck, in fact
* trust me - if it happens it does suck.
*/
static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
eurwdt_disable_timer(); /* Turn the card off */
return NOTIFY_DONE;
}
/*
* Kernel Interfaces
*/
static const struct file_operations eurwdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = eurwdt_write,
.unlocked_ioctl = eurwdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = eurwdt_open,
.release = eurwdt_release,
};
static struct miscdevice eurwdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &eurwdt_fops,
};
/*
* The WDT card needs to learn about soft shutdowns in order to
* turn the timebomb registers off.
*/
static struct notifier_block eurwdt_notifier = {
.notifier_call = eurwdt_notify_sys,
};
/**
* eurwdt_exit:
*
* Unload the watchdog. You cannot do this with any file handles open.
* If your watchdog is set to continue ticking on close and you unload
* it, well it keeps ticking. We won't get the interrupt but the board
* will not touch PC memory so all is fine. You just have to load a new
* module in 60 seconds or reboot.
*/
static void __exit eurwdt_exit(void)
{
eurwdt_lock_chip();
misc_deregister(&eurwdt_miscdev);
unregister_reboot_notifier(&eurwdt_notifier);
release_region(io, 2);
free_irq(irq, NULL);
}
/**
* eurwdt_init:
*
* Set up the WDT watchdog board. After grabbing the resources
* we require we need also to unlock the device.
* The open() function will actually kick the board off.
*/
static int __init eurwdt_init(void)
{
int ret;
ret = request_irq(irq, eurwdt_interrupt, 0, "eurwdt", NULL);
if (ret) {
pr_err("IRQ %d is not free\n", irq);
goto out;
}
if (!request_region(io, 2, "eurwdt")) {
pr_err("IO %X is not free\n", io);
ret = -EBUSY;
goto outirq;
}
ret = register_reboot_notifier(&eurwdt_notifier);
if (ret) {
pr_err("can't register reboot notifier (err=%d)\n", ret);
goto outreg;
}
ret = misc_register(&eurwdt_miscdev);
if (ret) {
pr_err("can't misc_register on minor=%d\n", WATCHDOG_MINOR);
goto outreboot;
}
eurwdt_unlock_chip();
ret = 0;
pr_info("Eurotech WDT driver 0.01 at %X (Interrupt %d) - timeout event: %s\n",
io, irq, (!strcmp("int", ev) ? "int" : "reboot"));
out:
return ret;
outreboot:
unregister_reboot_notifier(&eurwdt_notifier);
outreg:
release_region(io, 2);
outirq:
free_irq(irq, NULL);
goto out;
}
module_init(eurwdt_init);
module_exit(eurwdt_exit);
MODULE_AUTHOR("Rodolfo Giometti");
MODULE_DESCRIPTION("Driver for Eurotech CPU-1220/1410 on board watchdog");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/eurotechwdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ACPI Hardware Watchdog (WDAT) driver.
*
* Copyright (C) 2016, Intel Corporation
* Author: Mika Westerberg <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/watchdog.h>
#define MAX_WDAT_ACTIONS ACPI_WDAT_ACTION_RESERVED
/**
* struct wdat_instruction - Single ACPI WDAT instruction
* @entry: Copy of the ACPI table instruction
* @reg: Register the instruction is accessing
* @node: Next instruction in action sequence
*/
struct wdat_instruction {
struct acpi_wdat_entry entry;
void __iomem *reg;
struct list_head node;
};
/**
* struct wdat_wdt - ACPI WDAT watchdog device
* @pdev: Parent platform device
* @wdd: Watchdog core device
* @period: How long is one watchdog period in ms
* @stopped_in_sleep: Is this watchdog stopped by the firmware in S1-S5
* @stopped: Was the watchdog stopped by the driver in suspend
* @instructions: An array of instruction lists indexed by an action number from
* the WDAT table. There can be %NULL entries for not implemented
* actions.
*/
struct wdat_wdt {
struct platform_device *pdev;
struct watchdog_device wdd;
unsigned int period;
bool stopped_in_sleep;
bool stopped;
struct list_head *instructions[MAX_WDAT_ACTIONS];
};
#define to_wdat_wdt(wdd) container_of(wdd, struct wdat_wdt, wdd)
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#define WDAT_DEFAULT_TIMEOUT 30
static int timeout = WDAT_DEFAULT_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
__MODULE_STRING(WDAT_DEFAULT_TIMEOUT) ")");
static int wdat_wdt_read(struct wdat_wdt *wdat,
const struct wdat_instruction *instr, u32 *value)
{
const struct acpi_generic_address *gas = &instr->entry.register_region;
switch (gas->access_width) {
case 1:
*value = ioread8(instr->reg);
break;
case 2:
*value = ioread16(instr->reg);
break;
case 3:
*value = ioread32(instr->reg);
break;
default:
return -EINVAL;
}
dev_dbg(&wdat->pdev->dev, "Read %#x from 0x%08llx\n", *value,
gas->address);
return 0;
}
static int wdat_wdt_write(struct wdat_wdt *wdat,
const struct wdat_instruction *instr, u32 value)
{
const struct acpi_generic_address *gas = &instr->entry.register_region;
switch (gas->access_width) {
case 1:
iowrite8((u8)value, instr->reg);
break;
case 2:
iowrite16((u16)value, instr->reg);
break;
case 3:
iowrite32(value, instr->reg);
break;
default:
return -EINVAL;
}
dev_dbg(&wdat->pdev->dev, "Wrote %#x to 0x%08llx\n", value,
gas->address);
return 0;
}
static int wdat_wdt_run_action(struct wdat_wdt *wdat, unsigned int action,
u32 param, u32 *retval)
{
struct wdat_instruction *instr;
if (action >= ARRAY_SIZE(wdat->instructions))
return -EINVAL;
if (!wdat->instructions[action])
return -EOPNOTSUPP;
dev_dbg(&wdat->pdev->dev, "Running action %#x\n", action);
/* Run each instruction sequentially */
list_for_each_entry(instr, wdat->instructions[action], node) {
const struct acpi_wdat_entry *entry = &instr->entry;
const struct acpi_generic_address *gas;
u32 flags, value, mask, x, y;
bool preserve;
int ret;
gas = &entry->register_region;
preserve = entry->instruction & ACPI_WDAT_PRESERVE_REGISTER;
flags = entry->instruction & ~ACPI_WDAT_PRESERVE_REGISTER;
value = entry->value;
mask = entry->mask;
switch (flags) {
case ACPI_WDAT_READ_VALUE:
ret = wdat_wdt_read(wdat, instr, &x);
if (ret)
return ret;
x >>= gas->bit_offset;
x &= mask;
if (retval)
*retval = x == value;
break;
case ACPI_WDAT_READ_COUNTDOWN:
ret = wdat_wdt_read(wdat, instr, &x);
if (ret)
return ret;
x >>= gas->bit_offset;
x &= mask;
if (retval)
*retval = x;
break;
case ACPI_WDAT_WRITE_VALUE:
x = value & mask;
x <<= gas->bit_offset;
if (preserve) {
ret = wdat_wdt_read(wdat, instr, &y);
if (ret)
return ret;
y = y & ~(mask << gas->bit_offset);
x |= y;
}
ret = wdat_wdt_write(wdat, instr, x);
if (ret)
return ret;
break;
case ACPI_WDAT_WRITE_COUNTDOWN:
x = param;
x &= mask;
x <<= gas->bit_offset;
if (preserve) {
ret = wdat_wdt_read(wdat, instr, &y);
if (ret)
return ret;
y = y & ~(mask << gas->bit_offset);
x |= y;
}
ret = wdat_wdt_write(wdat, instr, x);
if (ret)
return ret;
break;
default:
dev_err(&wdat->pdev->dev, "Unknown instruction: %u\n",
flags);
return -EINVAL;
}
}
return 0;
}
static int wdat_wdt_enable_reboot(struct wdat_wdt *wdat)
{
int ret;
/*
* WDAT specification says that the watchdog is required to reboot
* the system when it fires. However, it also states that it is
* recommended to make it configurable through hardware register. We
* enable reboot now if it is configurable, just in case.
*/
ret = wdat_wdt_run_action(wdat, ACPI_WDAT_SET_REBOOT, 0, NULL);
if (ret && ret != -EOPNOTSUPP) {
dev_err(&wdat->pdev->dev,
"Failed to enable reboot when watchdog triggers\n");
return ret;
}
return 0;
}
static void wdat_wdt_boot_status(struct wdat_wdt *wdat)
{
u32 boot_status = 0;
int ret;
ret = wdat_wdt_run_action(wdat, ACPI_WDAT_GET_STATUS, 0, &boot_status);
if (ret && ret != -EOPNOTSUPP) {
dev_err(&wdat->pdev->dev, "Failed to read boot status\n");
return;
}
if (boot_status)
wdat->wdd.bootstatus = WDIOF_CARDRESET;
/* Clear the boot status in case BIOS did not do it */
ret = wdat_wdt_run_action(wdat, ACPI_WDAT_SET_STATUS, 0, NULL);
if (ret && ret != -EOPNOTSUPP)
dev_err(&wdat->pdev->dev, "Failed to clear boot status\n");
}
static void wdat_wdt_set_running(struct wdat_wdt *wdat)
{
u32 running = 0;
int ret;
ret = wdat_wdt_run_action(wdat, ACPI_WDAT_GET_RUNNING_STATE, 0,
&running);
if (ret && ret != -EOPNOTSUPP)
dev_err(&wdat->pdev->dev, "Failed to read running state\n");
if (running)
set_bit(WDOG_HW_RUNNING, &wdat->wdd.status);
}
static int wdat_wdt_start(struct watchdog_device *wdd)
{
return wdat_wdt_run_action(to_wdat_wdt(wdd),
ACPI_WDAT_SET_RUNNING_STATE, 0, NULL);
}
static int wdat_wdt_stop(struct watchdog_device *wdd)
{
return wdat_wdt_run_action(to_wdat_wdt(wdd),
ACPI_WDAT_SET_STOPPED_STATE, 0, NULL);
}
static int wdat_wdt_ping(struct watchdog_device *wdd)
{
return wdat_wdt_run_action(to_wdat_wdt(wdd), ACPI_WDAT_RESET, 0, NULL);
}
static int wdat_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct wdat_wdt *wdat = to_wdat_wdt(wdd);
unsigned int periods;
int ret;
periods = timeout * 1000 / wdat->period;
ret = wdat_wdt_run_action(wdat, ACPI_WDAT_SET_COUNTDOWN, periods, NULL);
if (!ret)
wdd->timeout = timeout;
return ret;
}
static unsigned int wdat_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct wdat_wdt *wdat = to_wdat_wdt(wdd);
u32 periods = 0;
wdat_wdt_run_action(wdat, ACPI_WDAT_GET_CURRENT_COUNTDOWN, 0, &periods);
return periods * wdat->period / 1000;
}
static const struct watchdog_info wdat_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
.firmware_version = 0,
.identity = "wdat_wdt",
};
static struct watchdog_ops wdat_wdt_ops = {
.owner = THIS_MODULE,
.start = wdat_wdt_start,
.stop = wdat_wdt_stop,
.ping = wdat_wdt_ping,
.set_timeout = wdat_wdt_set_timeout,
};
static int wdat_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct acpi_wdat_entry *entries;
const struct acpi_table_wdat *tbl;
struct wdat_wdt *wdat;
struct resource *res;
void __iomem **regs;
acpi_status status;
int i, ret;
status = acpi_get_table(ACPI_SIG_WDAT, 0,
(struct acpi_table_header **)&tbl);
if (ACPI_FAILURE(status))
return -ENODEV;
wdat = devm_kzalloc(dev, sizeof(*wdat), GFP_KERNEL);
if (!wdat)
return -ENOMEM;
regs = devm_kcalloc(dev, pdev->num_resources, sizeof(*regs),
GFP_KERNEL);
if (!regs)
return -ENOMEM;
/* WDAT specification wants to have >= 1ms period */
if (tbl->timer_period < 1)
return -EINVAL;
if (tbl->min_count > tbl->max_count)
return -EINVAL;
wdat->period = tbl->timer_period;
wdat->wdd.min_timeout = DIV_ROUND_UP(wdat->period * tbl->min_count, 1000);
wdat->wdd.max_timeout = wdat->period * tbl->max_count / 1000;
wdat->stopped_in_sleep = tbl->flags & ACPI_WDAT_STOPPED;
wdat->wdd.info = &wdat_wdt_info;
wdat->wdd.ops = &wdat_wdt_ops;
wdat->pdev = pdev;
/* Request and map all resources */
for (i = 0; i < pdev->num_resources; i++) {
void __iomem *reg;
res = &pdev->resource[i];
if (resource_type(res) == IORESOURCE_MEM) {
reg = devm_ioremap_resource(dev, res);
if (IS_ERR(reg))
return PTR_ERR(reg);
} else if (resource_type(res) == IORESOURCE_IO) {
reg = devm_ioport_map(dev, res->start, 1);
if (!reg)
return -ENOMEM;
} else {
dev_err(dev, "Unsupported resource\n");
return -EINVAL;
}
regs[i] = reg;
}
entries = (struct acpi_wdat_entry *)(tbl + 1);
for (i = 0; i < tbl->entries; i++) {
const struct acpi_generic_address *gas;
struct wdat_instruction *instr;
struct list_head *instructions;
unsigned int action;
struct resource r;
int j;
action = entries[i].action;
if (action >= MAX_WDAT_ACTIONS) {
dev_dbg(dev, "Skipping unknown action: %u\n", action);
continue;
}
instr = devm_kzalloc(dev, sizeof(*instr), GFP_KERNEL);
if (!instr)
return -ENOMEM;
INIT_LIST_HEAD(&instr->node);
instr->entry = entries[i];
gas = &entries[i].register_region;
memset(&r, 0, sizeof(r));
r.start = gas->address;
r.end = r.start + ACPI_ACCESS_BYTE_WIDTH(gas->access_width) - 1;
if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
r.flags = IORESOURCE_MEM;
} else if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
r.flags = IORESOURCE_IO;
} else {
dev_dbg(dev, "Unsupported address space: %d\n",
gas->space_id);
continue;
}
/* Find the matching resource */
for (j = 0; j < pdev->num_resources; j++) {
res = &pdev->resource[j];
if (resource_contains(res, &r)) {
instr->reg = regs[j] + r.start - res->start;
break;
}
}
if (!instr->reg) {
dev_err(dev, "I/O resource not found\n");
return -EINVAL;
}
instructions = wdat->instructions[action];
if (!instructions) {
instructions = devm_kzalloc(dev,
sizeof(*instructions),
GFP_KERNEL);
if (!instructions)
return -ENOMEM;
INIT_LIST_HEAD(instructions);
wdat->instructions[action] = instructions;
}
list_add_tail(&instr->node, instructions);
}
if (wdat->instructions[ACPI_WDAT_GET_CURRENT_COUNTDOWN])
wdat_wdt_ops.get_timeleft = wdat_wdt_get_timeleft;
wdat_wdt_boot_status(wdat);
wdat_wdt_set_running(wdat);
ret = wdat_wdt_enable_reboot(wdat);
if (ret)
return ret;
platform_set_drvdata(pdev, wdat);
/*
* Set initial timeout so that userspace has time to configure the
* watchdog properly after it has opened the device. In some cases
* the BIOS default is too short and causes immediate reboot.
*/
if (watchdog_timeout_invalid(&wdat->wdd, timeout)) {
dev_warn(dev, "Invalid timeout %d given, using %d\n",
timeout, WDAT_DEFAULT_TIMEOUT);
timeout = WDAT_DEFAULT_TIMEOUT;
}
ret = wdat_wdt_set_timeout(&wdat->wdd, timeout);
if (ret)
return ret;
watchdog_set_nowayout(&wdat->wdd, nowayout);
watchdog_stop_on_reboot(&wdat->wdd);
watchdog_stop_on_unregister(&wdat->wdd);
return devm_watchdog_register_device(dev, &wdat->wdd);
}
static int wdat_wdt_suspend_noirq(struct device *dev)
{
struct wdat_wdt *wdat = dev_get_drvdata(dev);
int ret;
if (!watchdog_active(&wdat->wdd))
return 0;
/*
* We need to stop the watchdog if firmware is not doing it or if we
* are going suspend to idle (where firmware is not involved). If
* firmware is stopping the watchdog we kick it here one more time
* to give it some time.
*/
wdat->stopped = false;
if (acpi_target_system_state() == ACPI_STATE_S0 ||
!wdat->stopped_in_sleep) {
ret = wdat_wdt_stop(&wdat->wdd);
if (!ret)
wdat->stopped = true;
} else {
ret = wdat_wdt_ping(&wdat->wdd);
}
return ret;
}
static int wdat_wdt_resume_noirq(struct device *dev)
{
struct wdat_wdt *wdat = dev_get_drvdata(dev);
int ret;
if (!watchdog_active(&wdat->wdd))
return 0;
if (!wdat->stopped) {
/*
* Looks like the boot firmware reinitializes the watchdog
* before it hands off to the OS on resume from sleep so we
* stop and reprogram the watchdog here.
*/
ret = wdat_wdt_stop(&wdat->wdd);
if (ret)
return ret;
ret = wdat_wdt_set_timeout(&wdat->wdd, wdat->wdd.timeout);
if (ret)
return ret;
ret = wdat_wdt_enable_reboot(wdat);
if (ret)
return ret;
ret = wdat_wdt_ping(&wdat->wdd);
if (ret)
return ret;
}
return wdat_wdt_start(&wdat->wdd);
}
static const struct dev_pm_ops wdat_wdt_pm_ops = {
NOIRQ_SYSTEM_SLEEP_PM_OPS(wdat_wdt_suspend_noirq, wdat_wdt_resume_noirq)
};
static struct platform_driver wdat_wdt_driver = {
.probe = wdat_wdt_probe,
.driver = {
.name = "wdat_wdt",
.pm = pm_sleep_ptr(&wdat_wdt_pm_ops),
},
};
module_platform_driver(wdat_wdt_driver);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("ACPI Hardware Watchdog (WDAT) driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:wdat_wdt");
| linux-master | drivers/watchdog/wdat_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Starfive Watchdog driver
*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/watchdog.h>
/* JH7100 Watchdog register define */
#define STARFIVE_WDT_JH7100_INTSTAUS 0x000
#define STARFIVE_WDT_JH7100_CONTROL 0x104
#define STARFIVE_WDT_JH7100_LOAD 0x108
#define STARFIVE_WDT_JH7100_EN 0x110
#define STARFIVE_WDT_JH7100_RELOAD 0x114 /* Write 0 or 1 to reload preset value */
#define STARFIVE_WDT_JH7100_VALUE 0x118
#define STARFIVE_WDT_JH7100_INTCLR 0x120 /*
* [0]: Write 1 to clear interrupt
* [1]: 1 mean clearing and 0 mean complete
* [31:2]: reserved.
*/
#define STARFIVE_WDT_JH7100_LOCK 0x13c /* write 0x378f0765 to unlock */
/* JH7110 Watchdog register define */
#define STARFIVE_WDT_JH7110_LOAD 0x000
#define STARFIVE_WDT_JH7110_VALUE 0x004
#define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
* [0]: reset enable;
* [1]: interrupt enable && watchdog enable
* [31:2]: reserved.
*/
#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
#define STARFIVE_WDT_JH7110_IMS 0x014
#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
/* WDOGCONTROL */
#define STARFIVE_WDT_ENABLE 0x1
#define STARFIVE_WDT_EN_SHIFT 0
#define STARFIVE_WDT_RESET_EN 0x1
#define STARFIVE_WDT_JH7100_RST_EN_SHIFT 0
#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
/* WDOGLOCK */
#define STARFIVE_WDT_JH7100_UNLOCK_KEY 0x378f0765
#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
/* WDOGINTCLR */
#define STARFIVE_WDT_INTCLR 0x1
#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
#define STARFIVE_WDT_MAXCNT 0xffffffff
#define STARFIVE_WDT_DEFAULT_TIME (15)
#define STARFIVE_WDT_DELAY_US 0
#define STARFIVE_WDT_TIMEOUT_US 10000
/* module parameter */
#define STARFIVE_WDT_EARLY_ENA 0
static bool nowayout = WATCHDOG_NOWAYOUT;
static int heartbeat;
static bool early_enable = STARFIVE_WDT_EARLY_ENA;
module_param(heartbeat, int, 0);
module_param(early_enable, bool, 0);
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
__MODULE_STRING(STARFIVE_WDT_DEFAULT_TIME) ")");
MODULE_PARM_DESC(early_enable,
"Watchdog is started at boot time if set to 1, default="
__MODULE_STRING(STARFIVE_WDT_EARLY_ENA));
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
struct starfive_wdt_variant {
unsigned int control; /* Watchdog Control Resgister for reset enable */
unsigned int load; /* Watchdog Load register */
unsigned int reload; /* Watchdog Reload Control register */
unsigned int enable; /* Watchdog Enable Register */
unsigned int value; /* Watchdog Counter Value Register */
unsigned int int_clr; /* Watchdog Interrupt Clear Register */
unsigned int unlock; /* Watchdog Lock Register */
unsigned int int_status; /* Watchdog Interrupt Status Register */
u32 unlock_key;
char enrst_shift;
char en_shift;
bool intclr_check; /* whether need to check it before clearing interrupt */
char intclr_ava_shift;
bool double_timeout; /* The watchdog need twice timeout to reboot */
};
struct starfive_wdt {
struct watchdog_device wdd;
spinlock_t lock; /* spinlock for register handling */
void __iomem *base;
struct clk *core_clk;
struct clk *apb_clk;
const struct starfive_wdt_variant *variant;
unsigned long freq;
u32 count; /* count of timeout */
u32 reload; /* restore the count */
};
/* Register layout and configuration for the JH7100 */
static const struct starfive_wdt_variant starfive_wdt_jh7100_variant = {
.control = STARFIVE_WDT_JH7100_CONTROL,
.load = STARFIVE_WDT_JH7100_LOAD,
.reload = STARFIVE_WDT_JH7100_RELOAD,
.enable = STARFIVE_WDT_JH7100_EN,
.value = STARFIVE_WDT_JH7100_VALUE,
.int_clr = STARFIVE_WDT_JH7100_INTCLR,
.unlock = STARFIVE_WDT_JH7100_LOCK,
.unlock_key = STARFIVE_WDT_JH7100_UNLOCK_KEY,
.int_status = STARFIVE_WDT_JH7100_INTSTAUS,
.enrst_shift = STARFIVE_WDT_JH7100_RST_EN_SHIFT,
.en_shift = STARFIVE_WDT_EN_SHIFT,
.intclr_check = true,
.intclr_ava_shift = STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT,
.double_timeout = false,
};
/* Register layout and configuration for the JH7110 */
static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
.control = STARFIVE_WDT_JH7110_CONTROL,
.load = STARFIVE_WDT_JH7110_LOAD,
.enable = STARFIVE_WDT_JH7110_CONTROL,
.value = STARFIVE_WDT_JH7110_VALUE,
.int_clr = STARFIVE_WDT_JH7110_INTCLR,
.unlock = STARFIVE_WDT_JH7110_LOCK,
.unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
.int_status = STARFIVE_WDT_JH7110_IMS,
.enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
.en_shift = STARFIVE_WDT_EN_SHIFT,
.intclr_check = false,
.double_timeout = true,
};
static int starfive_wdt_enable_clock(struct starfive_wdt *wdt)
{
int ret;
ret = clk_prepare_enable(wdt->apb_clk);
if (ret)
return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n");
ret = clk_prepare_enable(wdt->core_clk);
if (ret)
return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n");
return 0;
}
static void starfive_wdt_disable_clock(struct starfive_wdt *wdt)
{
clk_disable_unprepare(wdt->core_clk);
clk_disable_unprepare(wdt->apb_clk);
}
static inline int starfive_wdt_get_clock(struct starfive_wdt *wdt)
{
struct device *dev = wdt->wdd.parent;
wdt->apb_clk = devm_clk_get(dev, "apb");
if (IS_ERR(wdt->apb_clk))
return dev_err_probe(dev, PTR_ERR(wdt->apb_clk), "failed to get apb clock\n");
wdt->core_clk = devm_clk_get(dev, "core");
if (IS_ERR(wdt->core_clk))
return dev_err_probe(dev, PTR_ERR(wdt->core_clk), "failed to get core clock\n");
return 0;
}
static inline int starfive_wdt_reset_init(struct device *dev)
{
struct reset_control *rsts;
int ret;
rsts = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(rsts))
return dev_err_probe(dev, PTR_ERR(rsts), "failed to get resets\n");
ret = reset_control_deassert(rsts);
if (ret)
return dev_err_probe(dev, ret, "failed to deassert resets\n");
return 0;
}
static u32 starfive_wdt_ticks_to_sec(struct starfive_wdt *wdt, u32 ticks)
{
return DIV_ROUND_CLOSEST(ticks, wdt->freq);
}
/* Write unlock-key to unlock. Write other value to lock. */
static void starfive_wdt_unlock(struct starfive_wdt *wdt)
{
spin_lock(&wdt->lock);
writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
}
static void starfive_wdt_lock(struct starfive_wdt *wdt)
{
writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
spin_unlock(&wdt->lock);
}
/* enable watchdog interrupt to reset/reboot */
static void starfive_wdt_enable_reset(struct starfive_wdt *wdt)
{
u32 val;
val = readl(wdt->base + wdt->variant->control);
val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
writel(val, wdt->base + wdt->variant->control);
}
/* interrupt status whether has been raised from the counter */
static bool starfive_wdt_raise_irq_status(struct starfive_wdt *wdt)
{
return !!readl(wdt->base + wdt->variant->int_status);
}
/* waiting interrupt can be free to clear */
static int starfive_wdt_wait_int_free(struct starfive_wdt *wdt)
{
u32 value;
return readl_poll_timeout_atomic(wdt->base + wdt->variant->int_clr, value,
!(value & BIT(wdt->variant->intclr_ava_shift)),
STARFIVE_WDT_DELAY_US, STARFIVE_WDT_TIMEOUT_US);
}
/* clear interrupt signal before initialization or reload */
static int starfive_wdt_int_clr(struct starfive_wdt *wdt)
{
int ret;
if (wdt->variant->intclr_check) {
ret = starfive_wdt_wait_int_free(wdt);
if (ret)
return dev_err_probe(wdt->wdd.parent, ret,
"watchdog is not ready to clear interrupt.\n");
}
writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
return 0;
}
static inline void starfive_wdt_set_count(struct starfive_wdt *wdt, u32 val)
{
writel(val, wdt->base + wdt->variant->load);
}
static inline u32 starfive_wdt_get_count(struct starfive_wdt *wdt)
{
return readl(wdt->base + wdt->variant->value);
}
/* enable watchdog */
static inline void starfive_wdt_enable(struct starfive_wdt *wdt)
{
u32 val;
val = readl(wdt->base + wdt->variant->enable);
val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
writel(val, wdt->base + wdt->variant->enable);
}
/* disable watchdog */
static inline void starfive_wdt_disable(struct starfive_wdt *wdt)
{
u32 val;
val = readl(wdt->base + wdt->variant->enable);
val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
writel(val, wdt->base + wdt->variant->enable);
}
static inline void starfive_wdt_set_reload_count(struct starfive_wdt *wdt, u32 count)
{
starfive_wdt_set_count(wdt, count);
/* 7100 need set any value to reload register and could reload value to counter */
if (wdt->variant->reload)
writel(0x1, wdt->base + wdt->variant->reload);
}
static unsigned int starfive_wdt_max_timeout(struct starfive_wdt *wdt)
{
if (wdt->variant->double_timeout)
return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, (wdt->freq / 2)) - 1;
return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, wdt->freq) - 1;
}
static unsigned int starfive_wdt_get_timeleft(struct watchdog_device *wdd)
{
struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
u32 count;
/*
* If the watchdog takes twice timeout and set half count value,
* timeleft value should add the count value before first timeout.
*/
count = starfive_wdt_get_count(wdt);
if (wdt->variant->double_timeout && !starfive_wdt_raise_irq_status(wdt))
count += wdt->count;
return starfive_wdt_ticks_to_sec(wdt, count);
}
static int starfive_wdt_keepalive(struct watchdog_device *wdd)
{
struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
int ret;
starfive_wdt_unlock(wdt);
ret = starfive_wdt_int_clr(wdt);
if (ret)
goto exit;
starfive_wdt_set_reload_count(wdt, wdt->count);
exit:
/* exit with releasing spinlock and locking registers */
starfive_wdt_lock(wdt);
return ret;
}
static int starfive_wdt_start(struct starfive_wdt *wdt)
{
int ret;
starfive_wdt_unlock(wdt);
/* disable watchdog, to be safe */
starfive_wdt_disable(wdt);
starfive_wdt_enable_reset(wdt);
ret = starfive_wdt_int_clr(wdt);
if (ret)
goto exit;
starfive_wdt_set_count(wdt, wdt->count);
starfive_wdt_enable(wdt);
exit:
starfive_wdt_lock(wdt);
return ret;
}
static void starfive_wdt_stop(struct starfive_wdt *wdt)
{
starfive_wdt_unlock(wdt);
starfive_wdt_disable(wdt);
starfive_wdt_lock(wdt);
}
static int starfive_wdt_pm_start(struct watchdog_device *wdd)
{
struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
int ret = pm_runtime_get_sync(wdd->parent);
if (ret < 0)
return ret;
return starfive_wdt_start(wdt);
}
static int starfive_wdt_pm_stop(struct watchdog_device *wdd)
{
struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
starfive_wdt_stop(wdt);
return pm_runtime_put_sync(wdd->parent);
}
static int starfive_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
unsigned long count = timeout * wdt->freq;
/* some watchdogs take two timeouts to reset */
if (wdt->variant->double_timeout)
count /= 2;
wdt->count = count;
wdd->timeout = timeout;
starfive_wdt_unlock(wdt);
starfive_wdt_disable(wdt);
starfive_wdt_set_reload_count(wdt, wdt->count);
starfive_wdt_enable(wdt);
starfive_wdt_lock(wdt);
return 0;
}
#define STARFIVE_WDT_OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
static const struct watchdog_info starfive_wdt_info = {
.options = STARFIVE_WDT_OPTIONS,
.identity = "StarFive Watchdog",
};
static const struct watchdog_ops starfive_wdt_ops = {
.owner = THIS_MODULE,
.start = starfive_wdt_pm_start,
.stop = starfive_wdt_pm_stop,
.ping = starfive_wdt_keepalive,
.set_timeout = starfive_wdt_set_timeout,
.get_timeleft = starfive_wdt_get_timeleft,
};
static int starfive_wdt_probe(struct platform_device *pdev)
{
struct starfive_wdt *wdt;
int ret;
wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
if (!wdt)
return -ENOMEM;
wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wdt->base))
return dev_err_probe(&pdev->dev, PTR_ERR(wdt->base), "error mapping registers\n");
wdt->wdd.parent = &pdev->dev;
ret = starfive_wdt_get_clock(wdt);
if (ret)
return ret;
platform_set_drvdata(pdev, wdt);
pm_runtime_enable(&pdev->dev);
if (pm_runtime_enabled(&pdev->dev)) {
ret = pm_runtime_get_sync(&pdev->dev);
if (ret < 0)
return ret;
} else {
/* runtime PM is disabled but clocks need to be enabled */
ret = starfive_wdt_enable_clock(wdt);
if (ret)
return ret;
}
ret = starfive_wdt_reset_init(&pdev->dev);
if (ret)
goto err_exit;
watchdog_set_drvdata(&wdt->wdd, wdt);
wdt->wdd.info = &starfive_wdt_info;
wdt->wdd.ops = &starfive_wdt_ops;
wdt->variant = of_device_get_match_data(&pdev->dev);
spin_lock_init(&wdt->lock);
wdt->freq = clk_get_rate(wdt->core_clk);
if (!wdt->freq) {
dev_err(&pdev->dev, "get clock rate failed.\n");
ret = -EINVAL;
goto err_exit;
}
wdt->wdd.min_timeout = 1;
wdt->wdd.max_timeout = starfive_wdt_max_timeout(wdt);
wdt->wdd.timeout = STARFIVE_WDT_DEFAULT_TIME;
watchdog_init_timeout(&wdt->wdd, heartbeat, &pdev->dev);
starfive_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
watchdog_set_nowayout(&wdt->wdd, nowayout);
watchdog_stop_on_reboot(&wdt->wdd);
watchdog_stop_on_unregister(&wdt->wdd);
if (early_enable) {
ret = starfive_wdt_start(wdt);
if (ret)
goto err_exit;
set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
} else {
starfive_wdt_stop(wdt);
}
ret = watchdog_register_device(&wdt->wdd);
if (ret)
goto err_exit;
if (!early_enable)
pm_runtime_put_sync(&pdev->dev);
return 0;
err_exit:
starfive_wdt_disable_clock(wdt);
pm_runtime_disable(&pdev->dev);
return ret;
}
static int starfive_wdt_remove(struct platform_device *pdev)
{
struct starfive_wdt *wdt = platform_get_drvdata(pdev);
starfive_wdt_stop(wdt);
watchdog_unregister_device(&wdt->wdd);
if (pm_runtime_enabled(&pdev->dev))
pm_runtime_disable(&pdev->dev);
else
/* disable clock without PM */
starfive_wdt_disable_clock(wdt);
return 0;
}
static void starfive_wdt_shutdown(struct platform_device *pdev)
{
struct starfive_wdt *wdt = platform_get_drvdata(pdev);
starfive_wdt_pm_stop(&wdt->wdd);
}
static int starfive_wdt_suspend(struct device *dev)
{
struct starfive_wdt *wdt = dev_get_drvdata(dev);
/* Save watchdog state, and turn it off. */
wdt->reload = starfive_wdt_get_count(wdt);
/* Note that WTCNT doesn't need to be saved. */
starfive_wdt_stop(wdt);
return pm_runtime_force_suspend(dev);
}
static int starfive_wdt_resume(struct device *dev)
{
struct starfive_wdt *wdt = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_force_resume(dev);
if (ret)
return ret;
starfive_wdt_unlock(wdt);
/* Restore watchdog state. */
starfive_wdt_set_reload_count(wdt, wdt->reload);
starfive_wdt_lock(wdt);
return starfive_wdt_start(wdt);
}
static int starfive_wdt_runtime_suspend(struct device *dev)
{
struct starfive_wdt *wdt = dev_get_drvdata(dev);
starfive_wdt_disable_clock(wdt);
return 0;
}
static int starfive_wdt_runtime_resume(struct device *dev)
{
struct starfive_wdt *wdt = dev_get_drvdata(dev);
return starfive_wdt_enable_clock(wdt);
}
static const struct dev_pm_ops starfive_wdt_pm_ops = {
RUNTIME_PM_OPS(starfive_wdt_runtime_suspend, starfive_wdt_runtime_resume, NULL)
SYSTEM_SLEEP_PM_OPS(starfive_wdt_suspend, starfive_wdt_resume)
};
static const struct of_device_id starfive_wdt_match[] = {
{ .compatible = "starfive,jh7100-wdt", .data = &starfive_wdt_jh7100_variant },
{ .compatible = "starfive,jh7110-wdt", .data = &starfive_wdt_jh7110_variant },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, starfive_wdt_match);
static struct platform_driver starfive_wdt_driver = {
.probe = starfive_wdt_probe,
.remove = starfive_wdt_remove,
.shutdown = starfive_wdt_shutdown,
.driver = {
.name = "starfive-wdt",
.pm = pm_ptr(&starfive_wdt_pm_ops),
.of_match_table = starfive_wdt_match,
},
};
module_platform_driver(starfive_wdt_driver);
MODULE_AUTHOR("Xingyu Wu <[email protected]>");
MODULE_AUTHOR("Samin Guo <[email protected]>");
MODULE_DESCRIPTION("StarFive Watchdog Device Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/starfive-wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MStar WDT driver
*
* Copyright (C) 2019 - 2021 Daniel Palmer
* Copyright (C) 2021 Romain Perier
*
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define REG_WDT_CLR 0x0
#define REG_WDT_MAX_PRD_L 0x10
#define REG_WDT_MAX_PRD_H 0x14
#define MSC313E_WDT_MIN_TIMEOUT 1
#define MSC313E_WDT_DEFAULT_TIMEOUT 30
static unsigned int timeout;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
struct msc313e_wdt_priv {
void __iomem *base;
struct watchdog_device wdev;
struct clk *clk;
};
static int msc313e_wdt_start(struct watchdog_device *wdev)
{
struct msc313e_wdt_priv *priv = watchdog_get_drvdata(wdev);
u32 timeout;
int err;
err = clk_prepare_enable(priv->clk);
if (err)
return err;
timeout = wdev->timeout * clk_get_rate(priv->clk);
writew(timeout & 0xffff, priv->base + REG_WDT_MAX_PRD_L);
writew((timeout >> 16) & 0xffff, priv->base + REG_WDT_MAX_PRD_H);
writew(1, priv->base + REG_WDT_CLR);
return 0;
}
static int msc313e_wdt_ping(struct watchdog_device *wdev)
{
struct msc313e_wdt_priv *priv = watchdog_get_drvdata(wdev);
writew(1, priv->base + REG_WDT_CLR);
return 0;
}
static int msc313e_wdt_stop(struct watchdog_device *wdev)
{
struct msc313e_wdt_priv *priv = watchdog_get_drvdata(wdev);
writew(0, priv->base + REG_WDT_MAX_PRD_L);
writew(0, priv->base + REG_WDT_MAX_PRD_H);
writew(0, priv->base + REG_WDT_CLR);
clk_disable_unprepare(priv->clk);
return 0;
}
static int msc313e_wdt_settimeout(struct watchdog_device *wdev, unsigned int new_time)
{
wdev->timeout = new_time;
return msc313e_wdt_start(wdev);
}
static const struct watchdog_info msc313e_wdt_ident = {
.identity = "MSC313e watchdog",
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
};
static const struct watchdog_ops msc313e_wdt_ops = {
.owner = THIS_MODULE,
.start = msc313e_wdt_start,
.stop = msc313e_wdt_stop,
.ping = msc313e_wdt_ping,
.set_timeout = msc313e_wdt_settimeout,
};
static const struct of_device_id msc313e_wdt_of_match[] = {
{ .compatible = "mstar,msc313e-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, msc313e_wdt_of_match);
static int msc313e_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct msc313e_wdt_priv *priv;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk)) {
dev_err(dev, "No input clock\n");
return PTR_ERR(priv->clk);
}
priv->wdev.info = &msc313e_wdt_ident,
priv->wdev.ops = &msc313e_wdt_ops,
priv->wdev.parent = dev;
priv->wdev.min_timeout = MSC313E_WDT_MIN_TIMEOUT;
priv->wdev.max_timeout = U32_MAX / clk_get_rate(priv->clk);
priv->wdev.timeout = MSC313E_WDT_DEFAULT_TIMEOUT;
/* If the period is non-zero the WDT is running */
if (readw(priv->base + REG_WDT_MAX_PRD_L) | (readw(priv->base + REG_WDT_MAX_PRD_H) << 16))
set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
watchdog_set_drvdata(&priv->wdev, priv);
watchdog_init_timeout(&priv->wdev, timeout, dev);
watchdog_stop_on_reboot(&priv->wdev);
watchdog_stop_on_unregister(&priv->wdev);
return devm_watchdog_register_device(dev, &priv->wdev);
}
static int __maybe_unused msc313e_wdt_suspend(struct device *dev)
{
struct msc313e_wdt_priv *priv = dev_get_drvdata(dev);
if (watchdog_active(&priv->wdev))
msc313e_wdt_stop(&priv->wdev);
return 0;
}
static int __maybe_unused msc313e_wdt_resume(struct device *dev)
{
struct msc313e_wdt_priv *priv = dev_get_drvdata(dev);
if (watchdog_active(&priv->wdev))
msc313e_wdt_start(&priv->wdev);
return 0;
}
static SIMPLE_DEV_PM_OPS(msc313e_wdt_pm_ops, msc313e_wdt_suspend, msc313e_wdt_resume);
static struct platform_driver msc313e_wdt_driver = {
.driver = {
.name = "msc313e-wdt",
.of_match_table = msc313e_wdt_of_match,
.pm = &msc313e_wdt_pm_ops,
},
.probe = msc313e_wdt_probe,
};
module_platform_driver(msc313e_wdt_driver);
MODULE_AUTHOR("Daniel Palmer <[email protected]>");
MODULE_DESCRIPTION("Watchdog driver for MStar MSC313e");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/msc313e_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/A Series WDT Driver
*
* Copyright (C) 2017 Renesas Electronics America, Inc.
* Copyright (C) 2017 Chris Brandt
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#define DEFAULT_TIMEOUT 30
/* Watchdog Timer Registers */
#define WTCSR 0
#define WTCSR_MAGIC 0xA500
#define WTSCR_WT BIT(6)
#define WTSCR_TME BIT(5)
#define WTSCR_CKS(i) (i)
#define WTCNT 2
#define WTCNT_MAGIC 0x5A00
#define WRCSR 4
#define WRCSR_MAGIC 0x5A00
#define WRCSR_RSTE BIT(6)
#define WRCSR_CLEAR_WOVF 0xA500 /* special value */
/* The maximum CKS register setting value to get the longest timeout */
#define CKS_3BIT 0x7
#define CKS_4BIT 0xF
#define DIVIDER_3BIT 16384 /* Clock divider when CKS = 0x7 */
#define DIVIDER_4BIT 4194304 /* Clock divider when CKS = 0xF */
struct rza_wdt {
struct watchdog_device wdev;
void __iomem *base;
struct clk *clk;
u8 count;
u8 cks;
};
static void rza_wdt_calc_timeout(struct rza_wdt *priv, int timeout)
{
unsigned long rate = clk_get_rate(priv->clk);
unsigned int ticks;
if (priv->cks == CKS_4BIT) {
ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT);
/*
* Since max_timeout was set in probe, we know that the timeout
* value passed will never calculate to a tick value greater
* than 256.
*/
priv->count = 256 - ticks;
} else {
/* Start timer with longest timeout */
priv->count = 0;
}
pr_debug("%s: timeout set to %u (WTCNT=%d)\n", __func__,
timeout, priv->count);
}
static int rza_wdt_start(struct watchdog_device *wdev)
{
struct rza_wdt *priv = watchdog_get_drvdata(wdev);
/* Stop timer */
writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
/* Must dummy read WRCSR:WOVF at least once before clearing */
readb(priv->base + WRCSR);
writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
rza_wdt_calc_timeout(priv, wdev->timeout);
writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME |
WTSCR_CKS(priv->cks), priv->base + WTCSR);
return 0;
}
static int rza_wdt_stop(struct watchdog_device *wdev)
{
struct rza_wdt *priv = watchdog_get_drvdata(wdev);
writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
return 0;
}
static int rza_wdt_ping(struct watchdog_device *wdev)
{
struct rza_wdt *priv = watchdog_get_drvdata(wdev);
writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
pr_debug("%s: timeout = %u\n", __func__, wdev->timeout);
return 0;
}
static int rza_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
{
wdev->timeout = timeout;
rza_wdt_start(wdev);
return 0;
}
static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action,
void *data)
{
struct rza_wdt *priv = watchdog_get_drvdata(wdev);
/* Stop timer */
writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
/* Must dummy read WRCSR:WOVF at least once before clearing */
readb(priv->base + WRCSR);
writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
/*
* Start timer with fastest clock source and only 1 clock left before
* overflow with reset option enabled.
*/
writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
writew(WTCNT_MAGIC | 255, priv->base + WTCNT);
writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR);
/*
* Actually make sure the above sequence hits hardware before sleeping.
*/
wmb();
/* Wait for WDT overflow (reset) */
udelay(20);
return 0;
}
static const struct watchdog_info rza_wdt_ident = {
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
.identity = "Renesas RZ/A WDT Watchdog",
};
static const struct watchdog_ops rza_wdt_ops = {
.owner = THIS_MODULE,
.start = rza_wdt_start,
.stop = rza_wdt_stop,
.ping = rza_wdt_ping,
.set_timeout = rza_set_timeout,
.restart = rza_wdt_restart,
};
static int rza_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rza_wdt *priv;
unsigned long rate;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
rate = clk_get_rate(priv->clk);
if (rate < 16384) {
dev_err(dev, "invalid clock rate (%ld)\n", rate);
return -ENOENT;
}
priv->wdev.info = &rza_wdt_ident;
priv->wdev.ops = &rza_wdt_ops;
priv->wdev.parent = dev;
priv->cks = (u8)(uintptr_t) of_device_get_match_data(dev);
if (priv->cks == CKS_4BIT) {
/* Assume slowest clock rate possible (CKS=0xF) */
priv->wdev.max_timeout = (DIVIDER_4BIT * U8_MAX) / rate;
} else if (priv->cks == CKS_3BIT) {
/* Assume slowest clock rate possible (CKS=7) */
rate /= DIVIDER_3BIT;
/*
* Since the max possible timeout of our 8-bit count
* register is less than a second, we must use
* max_hw_heartbeat_ms.
*/
priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
dev_dbg(dev, "max hw timeout of %dms\n",
priv->wdev.max_hw_heartbeat_ms);
}
priv->wdev.min_timeout = 1;
priv->wdev.timeout = DEFAULT_TIMEOUT;
watchdog_init_timeout(&priv->wdev, 0, dev);
watchdog_set_drvdata(&priv->wdev, priv);
ret = devm_watchdog_register_device(dev, &priv->wdev);
if (ret)
dev_err(dev, "Cannot register watchdog device\n");
return ret;
}
static const struct of_device_id rza_wdt_of_match[] = {
{ .compatible = "renesas,r7s9210-wdt", .data = (void *)CKS_4BIT, },
{ .compatible = "renesas,rza-wdt", .data = (void *)CKS_3BIT, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rza_wdt_of_match);
static struct platform_driver rza_wdt_driver = {
.probe = rza_wdt_probe,
.driver = {
.name = "rza_wdt",
.of_match_table = rza_wdt_of_match,
},
};
module_platform_driver(rza_wdt_driver);
MODULE_DESCRIPTION("Renesas RZ/A WDT Driver");
MODULE_AUTHOR("Chris Brandt <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/watchdog/rza_wdt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* VIA Chipset Watchdog Driver
*
* Copyright (C) 2011 Sigfox
* Author: Marc Vertes <[email protected]>
* Based on a preliminary version from Harald Welte <[email protected]>
* Timer code by Wim Van Sebroeck <[email protected]>
*
* Caveat: PnP must be enabled in BIOS to allow full access to watchdog
* control registers. If not, the watchdog must be configured in BIOS manually.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/device.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/timer.h>
#include <linux/watchdog.h>
/* Configuration registers relative to the pci device */
#define VIA_WDT_MMIO_BASE 0xe8 /* MMIO region base address */
#define VIA_WDT_CONF 0xec /* watchdog enable state */
/* Relevant bits for the VIA_WDT_CONF register */
#define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
#define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
/*
* The MMIO region contains the watchdog control register and the
* hardware timer counter.
*/
#define VIA_WDT_MMIO_LEN 8 /* MMIO region length in bytes */
#define VIA_WDT_CTL 0 /* MMIO addr+0: state/control reg. */
#define VIA_WDT_COUNT 4 /* MMIO addr+4: timer counter reg. */
/* Bits for the VIA_WDT_CTL register */
#define VIA_WDT_RUNNING 0x01 /* 0: stop, 1: running */
#define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
#define VIA_WDT_PWROFF 0x04 /* 0: reset, 1: poweroff */
#define VIA_WDT_DISABLED 0x08 /* 1: timer is disabled */
#define VIA_WDT_TRIGGER 0x80 /* 1: start a new countdown */
/* Hardware heartbeat in seconds */
#define WDT_HW_HEARTBEAT 1
/* Timer heartbeat (500ms) */
#define WDT_HEARTBEAT (HZ/2) /* should be <= ((WDT_HW_HEARTBEAT*HZ)/2) */
/* User space timeout in seconds */
#define WDT_TIMEOUT_MAX 1023 /* approx. 17 min. */
#define WDT_TIMEOUT 60
static int timeout = WDT_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, between 1 and 1023 "
"(default = " __MODULE_STRING(WDT_TIMEOUT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
"(default = " __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static struct watchdog_device wdt_dev;
static struct resource wdt_res;
static void __iomem *wdt_mem;
static unsigned int mmio;
static void wdt_timer_tick(struct timer_list *unused);
static DEFINE_TIMER(timer, wdt_timer_tick);
/* The timer that pings the watchdog */
static unsigned long next_heartbeat; /* the next_heartbeat for the timer */
static inline void wdt_reset(void)
{
unsigned int ctl = readl(wdt_mem);
writel(ctl | VIA_WDT_TRIGGER, wdt_mem);
}
/*
* Timer tick: the timer will make sure that the watchdog timer hardware
* is being reset in time. The conditions to do this are:
* 1) the watchdog timer has been started and /dev/watchdog is open
* and there is still time left before userspace should send the
* next heartbeat/ping. (note: the internal heartbeat is much smaller
* then the external/userspace heartbeat).
* 2) the watchdog timer has been stopped by userspace.
*/
static void wdt_timer_tick(struct timer_list *unused)
{
if (time_before(jiffies, next_heartbeat) ||
(!watchdog_active(&wdt_dev))) {
wdt_reset();
mod_timer(&timer, jiffies + WDT_HEARTBEAT);
} else
pr_crit("I will reboot your machine !\n");
}
static int wdt_ping(struct watchdog_device *wdd)
{
/* calculate when the next userspace timeout will be */
next_heartbeat = jiffies + wdd->timeout * HZ;
return 0;
}
static int wdt_start(struct watchdog_device *wdd)
{
unsigned int ctl = readl(wdt_mem);
writel(wdd->timeout, wdt_mem + VIA_WDT_COUNT);
writel(ctl | VIA_WDT_RUNNING | VIA_WDT_TRIGGER, wdt_mem);
wdt_ping(wdd);
mod_timer(&timer, jiffies + WDT_HEARTBEAT);
return 0;
}
static int wdt_stop(struct watchdog_device *wdd)
{
unsigned int ctl = readl(wdt_mem);
writel(ctl & ~VIA_WDT_RUNNING, wdt_mem);
return 0;
}
static int wdt_set_timeout(struct watchdog_device *wdd,
unsigned int new_timeout)
{
writel(new_timeout, wdt_mem + VIA_WDT_COUNT);
wdd->timeout = new_timeout;
return 0;
}
static const struct watchdog_info wdt_info = {
.identity = "VIA watchdog",
.options = WDIOF_CARDRESET |
WDIOF_SETTIMEOUT |
WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
};
static const struct watchdog_ops wdt_ops = {
.owner = THIS_MODULE,
.start = wdt_start,
.stop = wdt_stop,
.ping = wdt_ping,
.set_timeout = wdt_set_timeout,
};
static struct watchdog_device wdt_dev = {
.info = &wdt_info,
.ops = &wdt_ops,
.min_timeout = 1,
.max_timeout = WDT_TIMEOUT_MAX,
};
static int wdt_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
unsigned char conf;
int ret = -ENODEV;
if (pci_enable_device(pdev)) {
dev_err(&pdev->dev, "cannot enable PCI device\n");
return -ENODEV;
}
/*
* Allocate a MMIO region which contains watchdog control register
* and counter, then configure the watchdog to use this region.
* This is possible only if PnP is properly enabled in BIOS.
* If not, the watchdog must be configured in BIOS manually.
*/
if (allocate_resource(&iomem_resource, &wdt_res, VIA_WDT_MMIO_LEN,
0xf0000000, 0xffffff00, 0xff, NULL, NULL)) {
dev_err(&pdev->dev, "MMIO allocation failed\n");
goto err_out_disable_device;
}
pci_write_config_dword(pdev, VIA_WDT_MMIO_BASE, wdt_res.start);
pci_read_config_byte(pdev, VIA_WDT_CONF, &conf);
conf |= VIA_WDT_CONF_ENABLE | VIA_WDT_CONF_MMIO;
pci_write_config_byte(pdev, VIA_WDT_CONF, conf);
pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio);
if (mmio) {
dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio);
} else {
dev_err(&pdev->dev, "MMIO setting failed. Check BIOS.\n");
goto err_out_resource;
}
if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) {
dev_err(&pdev->dev, "MMIO region busy\n");
goto err_out_resource;
}
wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN);
if (wdt_mem == NULL) {
dev_err(&pdev->dev, "cannot remap VIA wdt MMIO registers\n");
goto err_out_release;
}
if (timeout < 1 || timeout > WDT_TIMEOUT_MAX)
timeout = WDT_TIMEOUT;
wdt_dev.timeout = timeout;
wdt_dev.parent = &pdev->dev;
watchdog_set_nowayout(&wdt_dev, nowayout);
if (readl(wdt_mem) & VIA_WDT_FIRED)
wdt_dev.bootstatus |= WDIOF_CARDRESET;
ret = watchdog_register_device(&wdt_dev);
if (ret)
goto err_out_iounmap;
/* start triggering, in case of watchdog already enabled by BIOS */
mod_timer(&timer, jiffies + WDT_HEARTBEAT);
return 0;
err_out_iounmap:
iounmap(wdt_mem);
err_out_release:
release_mem_region(mmio, VIA_WDT_MMIO_LEN);
err_out_resource:
release_resource(&wdt_res);
err_out_disable_device:
pci_disable_device(pdev);
return ret;
}
static void wdt_remove(struct pci_dev *pdev)
{
watchdog_unregister_device(&wdt_dev);
del_timer_sync(&timer);
iounmap(wdt_mem);
release_mem_region(mmio, VIA_WDT_MMIO_LEN);
release_resource(&wdt_res);
pci_disable_device(pdev);
}
static const struct pci_device_id wdt_pci_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700) },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800) },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) },
{ 0 }
};
static struct pci_driver wdt_driver = {
.name = "via_wdt",
.id_table = wdt_pci_table,
.probe = wdt_probe,
.remove = wdt_remove,
};
module_pci_driver(wdt_driver);
MODULE_AUTHOR("Marc Vertes");
MODULE_DESCRIPTION("Driver for watchdog timer on VIA chipset");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/via_wdt.c |
// SPDX-License-Identifier: GPL-2.0
/*
* drivers/char/watchdog/davinci_wdt.c
*
* Watchdog driver for DaVinci DM644x/DM646x processors
*
* Copyright (C) 2006-2013 Texas Instruments.
*
* 2007 (c) MontaVista Software, Inc.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/err.h>
#define MODULE_NAME "DAVINCI-WDT: "
#define DEFAULT_HEARTBEAT 60
#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
/* Timer register set definition */
#define PID12 (0x0)
#define EMUMGT (0x4)
#define TIM12 (0x10)
#define TIM34 (0x14)
#define PRD12 (0x18)
#define PRD34 (0x1C)
#define TCR (0x20)
#define TGCR (0x24)
#define WDTCR (0x28)
/* TCR bit definitions */
#define ENAMODE12_DISABLED (0 << 6)
#define ENAMODE12_ONESHOT (1 << 6)
#define ENAMODE12_PERIODIC (2 << 6)
/* TGCR bit definitions */
#define TIM12RS_UNRESET (1 << 0)
#define TIM34RS_UNRESET (1 << 1)
#define TIMMODE_64BIT_WDOG (2 << 2)
/* WDTCR bit definitions */
#define WDEN (1 << 14)
#define WDFLAG (1 << 15)
#define WDKEY_SEQ0 (0xa5c6 << 16)
#define WDKEY_SEQ1 (0xda7e << 16)
static int heartbeat;
/*
* struct to hold data for each WDT device
* @base - base io address of WD device
* @clk - source clock of WDT
* @wdd - hold watchdog device as is in WDT core
*/
struct davinci_wdt_device {
void __iomem *base;
struct clk *clk;
struct watchdog_device wdd;
};
static int davinci_wdt_start(struct watchdog_device *wdd)
{
u32 tgcr;
u32 timer_margin;
unsigned long wdt_freq;
struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
wdt_freq = clk_get_rate(davinci_wdt->clk);
/* disable, internal clock source */
iowrite32(0, davinci_wdt->base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
iowrite32(0, davinci_wdt->base + TGCR);
tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
iowrite32(tgcr, davinci_wdt->base + TGCR);
/* clear counter regs */
iowrite32(0, davinci_wdt->base + TIM12);
iowrite32(0, davinci_wdt->base + TIM34);
/* set timeout period */
timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
iowrite32(timer_margin, davinci_wdt->base + PRD12);
timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
iowrite32(timer_margin, davinci_wdt->base + PRD34);
/* enable run continuously */
iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
/* Once the WDT is in pre-active state write to
* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
* write protected (except for the WDKEY field)
*/
/* put watchdog in pre-active state */
iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
/* put watchdog in active state */
iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
return 0;
}
static int davinci_wdt_ping(struct watchdog_device *wdd)
{
struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
/* put watchdog in service state */
iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
/* put watchdog in active state */
iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
return 0;
}
static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
{
u64 timer_counter;
unsigned long freq;
u32 val;
struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
/* if timeout has occured then return 0 */
val = ioread32(davinci_wdt->base + WDTCR);
if (val & WDFLAG)
return 0;
freq = clk_get_rate(davinci_wdt->clk);
if (!freq)
return 0;
timer_counter = ioread32(davinci_wdt->base + TIM12);
timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
timer_counter = div64_ul(timer_counter, freq);
return wdd->timeout - timer_counter;
}
static int davinci_wdt_restart(struct watchdog_device *wdd,
unsigned long action, void *data)
{
struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
u32 tgcr, wdtcr;
/* disable, internal clock source */
iowrite32(0, davinci_wdt->base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
tgcr = 0;
iowrite32(tgcr, davinci_wdt->base + TGCR);
tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
iowrite32(tgcr, davinci_wdt->base + TGCR);
/* clear counter and period regs */
iowrite32(0, davinci_wdt->base + TIM12);
iowrite32(0, davinci_wdt->base + TIM34);
iowrite32(0, davinci_wdt->base + PRD12);
iowrite32(0, davinci_wdt->base + PRD34);
/* put watchdog in pre-active state */
wdtcr = WDKEY_SEQ0 | WDEN;
iowrite32(wdtcr, davinci_wdt->base + WDTCR);
/* put watchdog in active state */
wdtcr = WDKEY_SEQ1 | WDEN;
iowrite32(wdtcr, davinci_wdt->base + WDTCR);
/* write an invalid value to the WDKEY field to trigger a restart */
wdtcr = 0x00004000;
iowrite32(wdtcr, davinci_wdt->base + WDTCR);
return 0;
}
static const struct watchdog_info davinci_wdt_info = {
.options = WDIOF_KEEPALIVEPING,
.identity = "DaVinci/Keystone Watchdog",
};
static const struct watchdog_ops davinci_wdt_ops = {
.owner = THIS_MODULE,
.start = davinci_wdt_start,
.stop = davinci_wdt_ping,
.ping = davinci_wdt_ping,
.get_timeleft = davinci_wdt_get_timeleft,
.restart = davinci_wdt_restart,
};
static int davinci_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct watchdog_device *wdd;
struct davinci_wdt_device *davinci_wdt;
davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
if (!davinci_wdt)
return -ENOMEM;
davinci_wdt->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(davinci_wdt->clk))
return dev_err_probe(dev, PTR_ERR(davinci_wdt->clk),
"failed to get clock node\n");
platform_set_drvdata(pdev, davinci_wdt);
wdd = &davinci_wdt->wdd;
wdd->info = &davinci_wdt_info;
wdd->ops = &davinci_wdt_ops;
wdd->min_timeout = 1;
wdd->max_timeout = MAX_HEARTBEAT;
wdd->timeout = DEFAULT_HEARTBEAT;
wdd->parent = dev;
watchdog_init_timeout(wdd, heartbeat, dev);
dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
watchdog_set_drvdata(wdd, davinci_wdt);
watchdog_set_nowayout(wdd, 1);
watchdog_set_restart_priority(wdd, 128);
davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(davinci_wdt->base))
return PTR_ERR(davinci_wdt->base);
return devm_watchdog_register_device(dev, wdd);
}
static const struct of_device_id davinci_wdt_of_match[] = {
{ .compatible = "ti,davinci-wdt", },
{},
};
MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
static struct platform_driver platform_wdt_driver = {
.driver = {
.name = "davinci-wdt",
.of_match_table = davinci_wdt_of_match,
},
.probe = davinci_wdt_probe,
};
module_platform_driver(platform_wdt_driver);
MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("DaVinci Watchdog Driver");
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat period in seconds from 1 to "
__MODULE_STRING(MAX_HEARTBEAT) ", default "
__MODULE_STRING(DEFAULT_HEARTBEAT));
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:davinci-wdt");
| linux-master | drivers/watchdog/davinci_wdt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AMD Elan SC520 processor Watchdog Timer driver
*
* Based on acquirewdt.c by Alan Cox,
* and sbc60xxwdt.c by Jakob Oestergaard <[email protected]>
*
* The authors do NOT admit liability nor provide warranty for
* any of this software. This material is provided "AS-IS" in
* the hope that it may be useful for others.
*
* (c) Copyright 2001 Scott Jennings <[email protected]>
* 9/27 - 2001 [Initial release]
*
* Additional fixes Alan Cox
* - Fixed formatting
* - Removed debug printks
* - Fixed SMP built kernel deadlock
* - Switched to private locks not lock_kernel
* - Used ioremap/writew/readw
* - Added NOWAYOUT support
* 4/12 - 2002 Changes by Rob Radez <[email protected]>
* - Change comments
* - Eliminate fop_llseek
* - Change CONFIG_WATCHDOG_NOWAYOUT semantics
* - Add KERN_* tags to printks
* - fix possible wdt_is_open race
* - Report proper capabilities in watchdog_info
* - Add WDIOC_{GETSTATUS, GETBOOTSTATUS, SETTIMEOUT,
* GETTIMEOUT, SETOPTIONS} ioctls
* 09/8 - 2003 Changes by Wim Van Sebroeck <[email protected]>
* - cleanup of trailing spaces
* - added extra printk's for startup problems
* - use module_param
* - made timeout (the emulated heartbeat) a module_param
* - made the keepalive ping an internal subroutine
* 3/27 - 2004 Changes by Sean Young <[email protected]>
* - set MMCR_BASE to 0xfffef000
* - CBAR does not need to be read
* - removed debugging printks
*
* This WDT driver is different from most other Linux WDT
* drivers in that the driver will ping the watchdog by itself,
* because this particular WDT has a very short timeout (1.6
* seconds) and it would be insane to count on any userspace
* daemon always getting scheduled within that time frame.
*
* This driver uses memory mapped IO, and spinlock.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/uaccess.h>
/*
* The AMD Elan SC520 timeout value is 492us times a power of 2 (0-7)
*
* 0: 492us 2: 1.01s 4: 4.03s 6: 16.22s
* 1: 503ms 3: 2.01s 5: 8.05s 7: 32.21s
*
* We will program the SC520 watchdog for a timeout of 2.01s.
* If we reset the watchdog every ~250ms we should be safe.
*/
#define WDT_INTERVAL (HZ/4+1)
/*
* We must not require too good response from the userspace daemon.
* Here we require the userspace daemon to send us a heartbeat
* char to /dev/watchdog every 30 seconds.
*/
#define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
/* in seconds, will be multiplied by HZ to get seconds to wait for a ping */
static int timeout = WATCHDOG_TIMEOUT;
module_param(timeout, int, 0);
MODULE_PARM_DESC(timeout,
"Watchdog timeout in seconds. (1 <= timeout <= 3600, default="
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
/*
* AMD Elan SC520 - Watchdog Timer Registers
*/
#define MMCR_BASE 0xfffef000 /* The default base address */
#define OFFS_WDTMRCTL 0xCB0 /* Watchdog Timer Control Register */
/* WDT Control Register bit definitions */
#define WDT_EXP_SEL_01 0x0001 /* [01] Time-out = 496 us (with 33 Mhz clk). */
#define WDT_EXP_SEL_02 0x0002 /* [02] Time-out = 508 ms (with 33 Mhz clk). */
#define WDT_EXP_SEL_03 0x0004 /* [03] Time-out = 1.02 s (with 33 Mhz clk). */
#define WDT_EXP_SEL_04 0x0008 /* [04] Time-out = 2.03 s (with 33 Mhz clk). */
#define WDT_EXP_SEL_05 0x0010 /* [05] Time-out = 4.07 s (with 33 Mhz clk). */
#define WDT_EXP_SEL_06 0x0020 /* [06] Time-out = 8.13 s (with 33 Mhz clk). */
#define WDT_EXP_SEL_07 0x0040 /* [07] Time-out = 16.27s (with 33 Mhz clk). */
#define WDT_EXP_SEL_08 0x0080 /* [08] Time-out = 32.54s (with 33 Mhz clk). */
#define WDT_IRQ_FLG 0x1000 /* [12] Interrupt Request Flag */
#define WDT_WRST_ENB 0x4000 /* [14] Watchdog Timer Reset Enable */
#define WDT_ENB 0x8000 /* [15] Watchdog Timer Enable */
static __u16 __iomem *wdtmrctl;
static void wdt_timer_ping(struct timer_list *);
static DEFINE_TIMER(timer, wdt_timer_ping);
static unsigned long next_heartbeat;
static unsigned long wdt_is_open;
static char wdt_expect_close;
static DEFINE_SPINLOCK(wdt_spinlock);
/*
* Whack the dog
*/
static void wdt_timer_ping(struct timer_list *unused)
{
/* If we got a heartbeat pulse within the WDT_US_INTERVAL
* we agree to ping the WDT
*/
if (time_before(jiffies, next_heartbeat)) {
/* Ping the WDT */
spin_lock(&wdt_spinlock);
writew(0xAAAA, wdtmrctl);
writew(0x5555, wdtmrctl);
spin_unlock(&wdt_spinlock);
/* Re-set the timer interval */
mod_timer(&timer, jiffies + WDT_INTERVAL);
} else
pr_warn("Heartbeat lost! Will not ping the watchdog\n");
}
/*
* Utility routines
*/
static void wdt_config(int writeval)
{
unsigned long flags;
/* buy some time (ping) */
spin_lock_irqsave(&wdt_spinlock, flags);
readw(wdtmrctl); /* ensure write synchronization */
writew(0xAAAA, wdtmrctl);
writew(0x5555, wdtmrctl);
/* unlock WDT = make WDT configuration register writable one time */
writew(0x3333, wdtmrctl);
writew(0xCCCC, wdtmrctl);
/* write WDT configuration register */
writew(writeval, wdtmrctl);
spin_unlock_irqrestore(&wdt_spinlock, flags);
}
static int wdt_startup(void)
{
next_heartbeat = jiffies + (timeout * HZ);
/* Start the timer */
mod_timer(&timer, jiffies + WDT_INTERVAL);
/* Start the watchdog */
wdt_config(WDT_ENB | WDT_WRST_ENB | WDT_EXP_SEL_04);
pr_info("Watchdog timer is now enabled\n");
return 0;
}
static int wdt_turnoff(void)
{
/* Stop the timer */
del_timer_sync(&timer);
/* Stop the watchdog */
wdt_config(0);
pr_info("Watchdog timer is now disabled...\n");
return 0;
}
static int wdt_keepalive(void)
{
/* user land ping */
next_heartbeat = jiffies + (timeout * HZ);
return 0;
}
static int wdt_set_heartbeat(int t)
{
if ((t < 1) || (t > 3600)) /* arbitrary upper limit */
return -EINVAL;
timeout = t;
return 0;
}
/*
* /dev/watchdog handling
*/
static ssize_t fop_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
/* See if we got the magic character 'V' and reload the timer */
if (count) {
if (!nowayout) {
size_t ofs;
/* note: just in case someone wrote the magic character
* five months ago... */
wdt_expect_close = 0;
/* now scan */
for (ofs = 0; ofs != count; ofs++) {
char c;
if (get_user(c, buf + ofs))
return -EFAULT;
if (c == 'V')
wdt_expect_close = 42;
}
}
/* Well, anyhow someone wrote to us, we should
return that favour */
wdt_keepalive();
}
return count;
}
static int fop_open(struct inode *inode, struct file *file)
{
/* Just in case we're already talking to someone... */
if (test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Good, fire up the show */
wdt_startup();
return stream_open(inode, file);
}
static int fop_close(struct inode *inode, struct file *file)
{
if (wdt_expect_close == 42)
wdt_turnoff();
else {
pr_crit("Unexpected close, not stopping watchdog!\n");
wdt_keepalive();
}
clear_bit(0, &wdt_is_open);
wdt_expect_close = 0;
return 0;
}
static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int __user *p = argp;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT
| WDIOF_MAGICCLOSE,
.firmware_version = 1,
.identity = "SC520",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_SETOPTIONS:
{
int new_options, retval = -EINVAL;
if (get_user(new_options, p))
return -EFAULT;
if (new_options & WDIOS_DISABLECARD) {
wdt_turnoff();
retval = 0;
}
if (new_options & WDIOS_ENABLECARD) {
wdt_startup();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
wdt_keepalive();
return 0;
case WDIOC_SETTIMEOUT:
{
int new_timeout;
if (get_user(new_timeout, p))
return -EFAULT;
if (wdt_set_heartbeat(new_timeout))
return -EINVAL;
wdt_keepalive();
}
fallthrough;
case WDIOC_GETTIMEOUT:
return put_user(timeout, p);
default:
return -ENOTTY;
}
}
static const struct file_operations wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = fop_write,
.open = fop_open,
.release = fop_close,
.unlocked_ioctl = fop_ioctl,
.compat_ioctl = compat_ptr_ioctl,
};
static struct miscdevice wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wdt_fops,
};
/*
* Notifier for system down
*/
static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
wdt_turnoff();
return NOTIFY_DONE;
}
/*
* The WDT needs to learn about soft shutdowns in order to
* turn the timebomb registers off.
*/
static struct notifier_block wdt_notifier = {
.notifier_call = wdt_notify_sys,
};
static void __exit sc520_wdt_unload(void)
{
if (!nowayout)
wdt_turnoff();
/* Deregister */
misc_deregister(&wdt_miscdev);
unregister_reboot_notifier(&wdt_notifier);
iounmap(wdtmrctl);
}
static int __init sc520_wdt_init(void)
{
int rc = -EBUSY;
/* Check that the timeout value is within it's range ;
if not reset to the default */
if (wdt_set_heartbeat(timeout)) {
wdt_set_heartbeat(WATCHDOG_TIMEOUT);
pr_info("timeout value must be 1 <= timeout <= 3600, using %d\n",
WATCHDOG_TIMEOUT);
}
wdtmrctl = ioremap(MMCR_BASE + OFFS_WDTMRCTL, 2);
if (!wdtmrctl) {
pr_err("Unable to remap memory\n");
rc = -ENOMEM;
goto err_out_region2;
}
rc = register_reboot_notifier(&wdt_notifier);
if (rc) {
pr_err("cannot register reboot notifier (err=%d)\n", rc);
goto err_out_ioremap;
}
rc = misc_register(&wdt_miscdev);
if (rc) {
pr_err("cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, rc);
goto err_out_notifier;
}
pr_info("WDT driver for SC520 initialised. timeout=%d sec (nowayout=%d)\n",
timeout, nowayout);
return 0;
err_out_notifier:
unregister_reboot_notifier(&wdt_notifier);
err_out_ioremap:
iounmap(wdtmrctl);
err_out_region2:
return rc;
}
module_init(sc520_wdt_init);
module_exit(sc520_wdt_unload);
MODULE_AUTHOR("Scott and Bill Jennings");
MODULE_DESCRIPTION(
"Driver for watchdog timer in AMD \"Elan\" SC520 uProcessor");
MODULE_LICENSE("GPL");
| linux-master | drivers/watchdog/sc520_wdt.c |
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