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oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/board_test.hpp | #include <sycl/sycl.hpp>
#include <vector>
#include "host_speed.hpp"
#if defined(SUPPORTS_USM)
#include "usm_speed.hpp"
#endif
// Pre-declare kernel name to prevent name mangling
// This is an FPGA best practice that makes it easier to identify the kernel in
// the optimization reports.
class NopNDRange;
class NopSingleTask;
class KernelSender;
class KernelReceiver;
class MemReadWriteStream;
class MemReadWriteStreamNDRange;
class MemWriteStream;
class MemReadStream;
// Pipe used between KernelSender and KernelReceiver -
// ShimMetrics::KernelLaunchTest(queue &q) function
using SendertoReceiverPipe =
sycl::ext::intel::pipe< // Defined in the SYCL headers
class SenderReceiverPipe, // An identifier for the pipe
unsigned int, // The type of data in the pipe
1>; // The capacity of the pipe
/////////////////////////////////
// **** class ShimMetrics **** //
/////////////////////////////////
// Object stores oneAPI shim metrics
// Member Functions (details closer to function definition):
// ShimMetrics - Constructor; initializes all metrics and obtains maximum device
// allocation and maximum device global memory TestGlobalMem - Host to device
// global memory interface check HostSpeed - Host to device global memory
// bandwidth measurement HostRWTest - Unaligned read & writes from host to
// device global memory KernelClkFreq - Kernel clock frequency measurement
// KernelLatency - Kernel latency measurement
// KernelLaunchTest - Host to kernel interface check
// KernelMemRW - Kernel to device global memory interface check
// KernelMemBW - Kernel to device global memory bandwidth measurement
class ShimMetrics {
public:
ShimMetrics(sycl::queue &q)
: h2d_rd_bw_{0},
h2d_wr_bw_{0},
h2d_rd_wr_bw_{0},
h2d_rw_test_{false},
kernel_freq_{0},
kernel_latency_{0},
kernel_thruput_{0},
kernel_mem_bw_{0},
kernel_mem_rw_test_{false} {
max_buffer_size_ =
q.get_device().get_info<sycl::info::device::global_mem_size>();
#if defined(FPGA_EMULATOR)
max_alloc_size_ =
512 * kMB; // Limiting size of all buffers used in test for emulation
#else
max_alloc_size_ =
q.get_device().get_info<sycl::info::device::max_mem_alloc_size>();
#endif
std::cout << "\nclGetDeviceInfo CL_DEVICE_GLOBAL_MEM_SIZE = "
<< max_buffer_size_ << "\n";
std::cout << "clGetDeviceInfo CL_DEVICE_MAX_MEM_ALLOC_SIZE = "
<< max_alloc_size_ << "\n";
std::cout << "Device buffer size available for allocation = "
<< max_alloc_size_ << " bytes\n";
board_info_.fmax_info_ = false;
board_info_.quartus_fmax_ = 0.0;
}
~ShimMetrics() {}
size_t TestGlobalMem(sycl::queue &q);
int HostSpeed(sycl::queue &q);
int HostRWTest(sycl::queue &q, size_t dev_offset = 0);
int KernelClkFreq(sycl::queue &q, bool report_chk = true);
int KernelLaunchTest(sycl::queue &q);
int KernelLatency(sycl::queue &q);
int KernelMemRW(sycl::queue &q);
int KernelMemBW(sycl::queue &q);
#if defined(SUPPORTS_USM)
int USMBWTest(sycl::queue &q);
#endif
void ReadBinary();
private:
float h2d_rd_bw_;
float h2d_wr_bw_;
float h2d_rd_wr_bw_;
bool h2d_rw_test_;
float kernel_freq_;
float kernel_latency_;
float kernel_thruput_;
float kernel_mem_bw_;
bool kernel_mem_rw_test_;
cl_ulong max_buffer_size_;
cl_ulong max_alloc_size_;
struct BoardSpec {
bool fmax_info_;
float quartus_fmax_;
} board_info_;
};
//////////////////////////////////////
// **** TestGlobalMem function **** //
//////////////////////////////////////
// Input:
// queue &q - queue to submit operation
// Returns:
// Number of errors in transfer OR 1 if device memory allocation is 0 or test
// fails (return 0 means test passed)
// The function does the following tasks:
// 1. Get maximum device global memory allocation size
// 2. Allocate host memory to use to store data to be written to and read from
// device
// 3. Write to device global memory
// 4. Read from device global memory
// 5. Verify data read back matches value written
// 6. Report read, write bandwidth
// If this test passes (returns 0), the host to device global memory interface
// is working fine
size_t ShimMetrics::TestGlobalMem(sycl::queue &q) {
// Data is transferred from host to device in kMaxHostChunk size transfers
// (size in bytes)
constexpr size_t kMaxHostChunk = 512 * kMB;
// Test fails if max alloc size is 0
if (max_alloc_size_ == 0) {
std::cerr << "Maximum global memory allocation supported by Sycl device is "
<< "0! Cannot run host speed test\n\n";
return 1;
}
// **** Create device buffer ****//
// Creating device buffer to span all usable global memory space on device
sycl::buffer<unsigned long, 1> dev_buf{
sycl::range<1>{(max_alloc_size_ / sizeof(unsigned long))}};
std::cout << "Size of buffer created = " << dev_buf.byte_size() << " bytes\n";
// **** Host memory allocation **** //
/*<hostbuf> is used to store data
to be written to device buffer as well as data that is read back
While loop retries allocation for smaller chunk if kMaxHostChunk allocation
fails, minimum size is 512 bytes*/
// Size of allocated host memory (in bytes)
size_t host_size = kMaxHostChunk;
unsigned long *hostbuf = new (std::nothrow) unsigned long[host_size];
while ((host_size >= (kKB / 2)) && hostbuf == NULL) {
host_size = host_size / 2;
hostbuf = new (std::nothrow) unsigned long[host_size];
}
if (hostbuf == NULL) {
std::cerr << "Error: Allocation of host buffers for the test failed."
<< "Cannot run host speed test\n\n";
return 1;
}
// **** Writing data from host memory to device global memory **** //
// Number of bytes remaining to transfer to device memory
unsigned long bytes_rem = max_alloc_size_;
// offset at which write should begin in device global memory
unsigned long offset = 0;
// Total time to write
double sum_time_ns = 0.0;
// Copying host memory to device buffer in chunks
std::cout << "Writing " << (max_alloc_size_ / kMB)
<< " MB to device global memory ... ";
// Device global memory larger (i.e. max_alloc_size_) than host memory size
// (i.e. host_size) Chunks of host memory size written to device memory in
// iterations
while (bytes_rem > 0) {
unsigned long chunk = bytes_rem;
if (chunk > host_size) chunk = host_size;
// Initializing host buffer
for (unsigned long i = 0; i < chunk / sizeof(unsigned long); ++i) {
hostbuf[i] = offset + i;
}
// Submit command to copy (explicit copy from host to device)
auto h2d_copy_e = q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed
auto buf_range = chunk / sizeof(unsigned long);
// offset starts at 0 - incremented by chunk size each iteration
auto buf_offset = offset / sizeof(unsigned long);
// Access host_size range of buffer starting at buf_offset
sycl::accessor mem(dev_buf, h, buf_range, buf_offset);
// Writing from host memory to device buffer
h.copy(hostbuf, mem);
});
// Wait for explicit copy from host memory to device buffer to complete
h2d_copy_e.wait();
// Get time for copy operation using Sycl event information (return in
// nanoseconds)
sum_time_ns += SyclGetQStExecTimeNs(h2d_copy_e);
// Increment offset and decrement remaining bytes by size of transfer
offset += chunk;
bytes_rem -= chunk;
} // End of write-to-device while loop
// Report write bandwidth
std::cout << (((float)max_alloc_size_ / kMB) / ((float)sum_time_ns * 1e-9))
<< " MB/s\n";
// **** Reading data from device global memory to host memory **** //
// Read back all of memory and verify
std::cout << "Reading " << (max_alloc_size_ / kMB)
<< " MB from device global memory ... ";
// Reset variables for read loop
bytes_rem = max_alloc_size_;
// Start reading at offset 0
offset = 0;
// Total time to read
sum_time_ns = 0.0;
// The same host memory is used to read back values, resetting it to 0
for (unsigned long i = 0; i < host_size / sizeof(unsigned long); ++i) {
hostbuf[i] = 0;
}
// Variables for error calculation (verify value read back matches written
// value)
unsigned long errors = 0;
unsigned long compare_count = 0;
unsigned long chunk_errors = 0;
unsigned long chunk_cnt_rd = 0;
// Device global memory larger (i.e. max_alloc_size_) than host memory size
// (i.e. host_size) Read back chunks of host memory size from device memory in
// iterations
while (bytes_rem > 0) {
unsigned long chunk = bytes_rem;
if (chunk > host_size) chunk = host_size;
// Submit copy operation (explicit copy from device to host)
auto d2h_copy_e = q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed
auto buf_range = chunk / sizeof(unsigned long);
// offset starts at 0 - incremented by chunk size each iteration
auto buf_offset = offset / sizeof(unsigned long);
// Access host_size range of buffer starting at buf_offset
sycl::accessor mem(dev_buf, h, buf_range, buf_offset);
// Reading from device buffer into host memory
h.copy(mem, hostbuf);
});
// Wait for explicit copy from host memory to device buffer to complete
d2h_copy_e.wait();
// Get time for copy operation using Sycl event information (return in
// nanoseconds)
sum_time_ns += SyclGetQStExecTimeNs(d2h_copy_e); // Nanoseconds
// **** Verification **** //
// Verify data read back matches data that was written, if not increment
// error count
for (unsigned long i = 0; i < chunk / sizeof(unsigned long); ++i) {
compare_count++;
if (hostbuf[i] != (i + offset)) {
++errors;
if (errors <= 32) { // only print 32 errors
std::cerr << "Verification failure at element " << i << ", expected "
<< i << " but read back " << hostbuf[i] << "\n";
}
chunk_errors++;
if (chunk_errors <= 32) { // only print 32 errors
std::cerr << "Verification failure at element " << i << "; chunk_cnt "
<< chunk_cnt_rd << ";, expected 0x" << std::hex << i
<< " \\ " << std::dec << i << " but read back 0x"
<< std::hex << hostbuf[i] << " \\ " << std::dec
<< hostbuf[i] << "\n";
}
}
} // End of for loop
if (chunk_errors > 0) {
std::cerr << "chunk_errors for chunk " << chunk_cnt_rd << " was "
<< chunk_errors << " \\ 0x" << std::hex << chunk_errors
<< std::dec
<< "\n"; // Restoring manipulator to decimal in the end of cout
chunk_errors = 0; // reset for next chunk
}
// Increment offset and decrement remaining bytes by size of transfer
offset += chunk;
bytes_rem -= chunk;
chunk_cnt_rd++;
} // End of read-from-device while loop
// Report read bandwidth
std::cout << (((float)max_alloc_size_ / kMB) / ((float)sum_time_ns * 1e-9))
<< " MB/s\n";
// **** Report results from global memory test **** //
std::cout << "Verifying data ...\n";
if (errors == 0) {
std::cout << "Successfully wrote and readback " << (max_alloc_size_ / kMB)
<< " MB buffer\n\n";
} else {
std::cout << "Wrote and readback " << (max_alloc_size_ / kMB)
<< " MB buffer\n";
std::cerr
<< "Failed write/readback test with " << errors << " errors out of "
<< compare_count << " \\ 0x" << std::hex << compare_count
<< std::dec // Restoring manipulator to decimal at the end of cout
<< " comparisons\n\n";
}
// Free allocated host memory
delete[] hostbuf;
return errors;
}
//////////////////////////////////
// **** HostSpeed function **** //
//////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// Returns:
// 0 is test passes, 1 if test fails
// The function does the following tasks:
// 1. Test entire device global memory by writing and reading to it
// 2. Write to device global memory in smaller chunks and measure transfer time
// for each chunk
// 3. Read back data from device global memory and measure transfer time for
// each chunk
// 4. Verify data read back from device matches data written to device
// 5. Calculate write bandwidth, read bandwidth and read-write bandwidth from
// results of above transfers
// Following additional functions are used for the above tasks:
// More details about these funtions can be found with the corresponsing
// definitions
// 1. size_t TestGlobalMem(queue &q)
// 2. struct Speed WriteSpeed(queue &q, buffer<char,1> &device_buffer, char
// *hostbuf_wr, size_t block_bytes, size_t total_bytes)
// 3. struct Speed ReadSpeed(queue &q, buffer<char,1> &device_buffer, char
// *hostbuf_rd, size_t block_bytes, size_t total_bytes)
// 4. bool CheckResults
// 4. unsigned long SyclGetQStExecTimeNs(event e)
// 5. unsigned long SyclGetTotalTimeNs(event first_evt, event last_evt)
int ShimMetrics::HostSpeed(sycl::queue &q) {
// Total bytes to transfer
constexpr size_t kMaxBytes = 8 * kMB; // 8 MB;
constexpr size_t kMaxChars = kMaxBytes / sizeof(char);
// Block size of each transfer in bytes
constexpr size_t kMinBytes = 32 * kKB; // 32 KB
size_t block_bytes = kMinBytes;
// Call function to verify write to and read from the entire device global
// memory
if (ShimMetrics::TestGlobalMem(q) != 0) {
std::cerr << "Error: Global memory test failed\n";
return 1;
}
// **** Device buffer **** //
// Creating device buffer to span kMaxBytes size
// Buffer that WriteSpeed and ReadSpeed functions write to & read from
sycl::buffer<char, 1> device_buffer{sycl::range<1>{kMaxChars}};
// **** Host memory allocation and initialization **** //
// hostbuf_wr is used by WriteSpeed function to get input data to device
// buffer hostbuf_rd is used by ReadSpeed function to store data read from
// device buffer
char *hostbuf_rd = new char[kMaxBytes];
char *hostbuf_wr = new char[kMaxBytes];
// Initializing input on host to be written to device buffer
srand(kRandomSeed);
// Create sequence: 0 rand1 ~2 rand2 4 ...
for (size_t j = 0; j < kMaxChars; j++) {
if (j % 2 == 0)
hostbuf_wr[j] = (j & 2) ? ~j : j;
else
hostbuf_wr[j] = rand() * rand();
}
// *** Warm-up link before measuring bandwidth *** //
// Writing to device buffer from initialized host memory
WriteSpeed(q, device_buffer, hostbuf_wr, block_bytes, kMaxBytes);
// Reading from device buffer into allocated host memory
ReadSpeed(q, device_buffer, hostbuf_rd, block_bytes, kMaxBytes);
// **** Block transfers to measure bandwidth **** //
// Total number of iterations to write total bytes (i.e. kMaxBytes) in blocks
// of block_bytes size
size_t iterations = 1;
for (size_t i = kMaxBytes / block_bytes; i >> 1; i = i >> 1) iterations++;
// struct Speed in defined in hostspeed.hpp and is used to store transfer
// times Creating array of struct to store output from each iteration The
// values from each iteration are analyzed to report bandwidth
struct Speed rd_bw[iterations];
struct Speed wr_bw[iterations];
// std::cout is manipulated to format output
// Storing old state of std::cout to restore
std::ios old_state(nullptr);
old_state.copyfmt(std::cout);
// Variable accumulate store result of each iteration
bool result = true;
// Iterate till total bytes (i.e. kMaxBytes) have been transferred
// and accumulate results in rd_bw and wr_bw structs
for (size_t i = 0; i < iterations; i++, block_bytes *= 2) {
std::cout << "Transferring " << (kMaxBytes / kKB) << " KBs in "
<< (kMaxBytes / block_bytes) << " " << (block_bytes / kKB)
<< " KB blocks ...\n";
wr_bw[i] = WriteSpeed(q, device_buffer, hostbuf_wr, block_bytes, kMaxBytes);
rd_bw[i] = ReadSpeed(q, device_buffer, hostbuf_rd, block_bytes, kMaxBytes);
// Verify value read back matches value that was written to device
result &= CheckResults(hostbuf_wr, hostbuf_rd, kMaxChars);
// Restoring old format after each CheckResults function call to print
// correct format in current loop
std::cout.copyfmt(old_state);
}
// **** Report results **** //
// The write and read have already completed in the for loop with calls to
// ReadSpeed, WriteSpeed functions The two for loops below simply format and
// print the output for these tests
// **** Report results from writes to device **** //
// Restoring value of block_bytes as it changed in for loop above
block_bytes = kMinBytes;
// Fastest transfer value used in read-write bandwidth calculation
float write_topspeed = 0;
std::cout << "\nWriting " << (kMaxBytes / kKB)
<< " KBs with block size (in bytes) below:\n";
std::cout << "\nBlock_Size Avg Max Min End-End (MB/s)\n";
for (size_t i = 0; i < iterations; i++, block_bytes *= 2) {
std::cout << std::setw(8) << block_bytes << " " << std::setprecision(2)
<< std::fixed << wr_bw[i].average << " " << wr_bw[i].fastest
<< " " << wr_bw[i].slowest << " " << wr_bw[i].total << " \n";
if (wr_bw[i].fastest > write_topspeed) write_topspeed = wr_bw[i].fastest;
if (wr_bw[i].total > write_topspeed) write_topspeed = wr_bw[i].total;
// Restoring old format after each CheckResults function call to print
// correct format in current loop
std::cout.copyfmt(old_state);
}
// **** Report results from read from device **** //
// Restoring value of block_bytes as it changed in for loop above
block_bytes = kMinBytes;
// Fastest transfer value used in read-write bandwidth calculation
float read_topspeed = 0;
std::cout << "\nReading " << (kMaxBytes / kKB)
<< " KBs with block size (in bytes) below:\n";
std::cout << "\nBlock_Size Avg Max Min End-End (MB/s)\n";
for (size_t i = 0; i < iterations; i++, block_bytes *= 2) {
std::cout << std::setw(8) << block_bytes << " " << std::setprecision(2)
<< std::fixed << rd_bw[i].average << " " << rd_bw[i].fastest
<< " " << rd_bw[i].slowest << " " << rd_bw[i].total << " \n";
if (rd_bw[i].fastest > read_topspeed) read_topspeed = rd_bw[i].fastest;
if (rd_bw[i].total > read_topspeed) read_topspeed = rd_bw[i].total;
// Restoring old format after each CheckResults function call to print
// correct format in current loop
std::cout.copyfmt(old_state);
}
h2d_rd_bw_ = read_topspeed;
h2d_wr_bw_ = write_topspeed;
h2d_rd_wr_bw_ = ((read_topspeed + write_topspeed) / 2);
std::cout << "\nHost write top speed = " << std::setprecision(2) << std::fixed
<< write_topspeed << " MB/s\n";
std::cout << "Host read top speed = " << read_topspeed << " MB/s\n\n";
std::cout << "\nHOST-TO-MEMORY BANDWIDTH = " << std::setprecision(0)
<< ((read_topspeed + write_topspeed) / 2) << " MB/s\n\n";
// Restoring old format after each CheckResults function call to print correct
// format in current loop
std::cout.copyfmt(old_state);
// Fail if any iteration of the transfer failed
if (!result) std::cerr << "\nFAILURE!\n";
// Free allocated host memory
delete[] hostbuf_rd;
delete[] hostbuf_wr;
return (result) ? 0 : 1;
}
///////////////////////////////////
// **** HostRWTest function **** //
///////////////////////////////////
// Inputs:
// 1. queue &q - queue to submit operation
// 2. size_t dev_offset - device buffer offset (for transfer from aligned memory
// in device, the default value of this is 0) Returns: 0 is test passes,
// terminates program if test fails
// The function does the following tasks:
// 1. Creates a device buffer sized an odd number of bytes
// 2. Host memory allocation for both read and write with padding to prenent
// overflow during unaligned transfer
// 3. Increments pointer to host memory to make it an unaligned address
// 4. Writes data from this unaligned address to device global memory
// 5. Reads back data from device global memory to aligned host memory pointer
// 6. Verifies data read back matches data written
// Program terminates if verification fails
int ShimMetrics::HostRWTest(sycl::queue &q, size_t dev_offset) {
// Bytes to transfer (1KB)
constexpr size_t kMaxBytes_rw = kKB;
// **** Device and host memory offsets to make them unaligned **** //
// Device offset is passed from calling function
// Selected host memory (for input to device) offset for unaligned transfer =
// 5
constexpr signed int kHostInOffset = 5;
// Selected host memory (to read back from device) offset for read back = 8
constexpr signed int kHostRdOffset = 8;
std::cout << "--- Running host read write test with device offset "
<< dev_offset << "\n";
// **** Device buffer creation **** //
// Expanding device buffer size; odd number of bytes (i.e. +3) makes sure that
// DMA is not aligned
constexpr size_t kOddMaxBytes = kMaxBytes_rw + 3;
// Device buffer of kOddMaxbytes
sycl::buffer<char, 1> dev_buf(sycl::range<1>{kOddMaxBytes});
// **** Host memory allocation and initialization **** //
// Padding both host memory blocks with extra space to avoid overflow during
// unaligned transfers
// Allocating host memory for input to device buffer
char *host_in_buf =
new char[kMaxBytes_rw +
(2 * kHostInOffset)]; // Padding on both sides of memory, hence
// increment size by 2 * host_in_offset
// Save original memory address before offset
char *host_in_buf_ptr = host_in_buf;
// Initialize host memory with some invalid data
char invalid_host_input = -6;
for (size_t j = 0; j < ((kMaxBytes_rw + (2 * kHostInOffset)) / sizeof(char));
j++) {
host_in_buf[j] = invalid_host_input;
}
// Increment pointer to make input host memory pointer non-aligned to test
// un-aligned host ptr to un-aligned device ptr transfer
host_in_buf += kHostInOffset;
// Allocating host memory to read back into from device buffer
char *host_rd_buf =
new char[kMaxBytes_rw +
(2 * kHostRdOffset)]; // Padding on both sides of memory, hence
// increment size by 2 * host_rd_offset
// Save original memory address before offset
char *host_rd_buf_ptr = host_rd_buf;
// Initialize host memory with some invalid data
char invalid_read_back = -3;
for (size_t j = 0; j < ((kMaxBytes_rw + (2 * kHostRdOffset)) / sizeof(char));
j++) {
host_rd_buf[j] = invalid_read_back;
}
// Increment pointer to make read back memory pointer aligned to test reading
// from un-aligned device ptr to aligned host ptr
host_rd_buf += kHostRdOffset;
#ifdef DEBUG
std::cout << "host input buf = " << host_in_buf << " , "
<< "host read back buf = " << host_rd_buf << "\n";
#endif
srand(kRandomSeed);
// **** Write to and read from device global memory **** //
// Non-DMA read/writes of all sizes upto 1024
for (size_t i = 1; i <= kMaxBytes_rw; i++) {
#ifdef DEBUG
std::cout << "Read/write of " << i << " bytes\n";
#endif
// host will have unique values for every write
for (size_t j = 0; j < i; j++) {
host_in_buf[j] = (char)rand();
}
// **** Write to device global memory **** //
// Submit copy operation (explicit copy from host to device)
q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed = i bytes (chars)
// Device buffer is accessed at dev_offset
// Using +3 offset on aligned device pointer ensures that DMA is never
// used (because the host ptr is not aligned)
sycl::accessor mem(dev_buf, h, i, dev_offset);
// Writing from host memory to device buffer
h.copy(host_in_buf, mem);
}).wait(); // Wait for copy to complete
// **** Read from device global memory **** //
// Submit copy operation (explicit copy from device to host)
q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed = i bytes (chars)
// Device buffer is accessed at dev_offset
sycl::accessor mem(dev_buf, h, i, dev_offset);
// Reading from device buffer into host memory
h.copy(mem, host_rd_buf);
}).wait(); // Wait for copy to complete
// Verify values read back match the input
#ifdef DEBUG
std::cout << host_rd_buf[0] << " , " << host_in_buf[0] << "\n";
#endif
if (memcmp(host_in_buf, host_rd_buf, i) != 0) {
std::cerr << i << " bytes read/write FAILED!\n";
for (size_t m = 0; m < i; m++) {
if (host_in_buf[m] != host_rd_buf[m]) {
std::cerr << "char #" << m
<< " , host input buffer = " << host_in_buf[m]
<< " , host read back buffer = " << host_rd_buf[m] << "\n";
}
}
assert(0);
}
// make sure bounds on both ends of buffer are ok
for (signed int k = (-1 * kHostRdOffset); k < kHostRdOffset; k++) {
if (k < 0)
assert(host_rd_buf[k] == invalid_read_back);
else
assert(host_rd_buf[i + k] == invalid_read_back);
}
} // End of for loop for writing/reading all bytes
// Free allocated host memory
delete[] host_in_buf_ptr;
delete[] host_rd_buf_ptr;
// Unaligned transfers completed successfully, test passed
h2d_rw_test_ = true;
return 0;
}
//////////////////////////////////////
// **** KernelClkFreq function **** //
//////////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// bool report_chk - control if Quartus compiled frequency should be read
// Returns:
// 0 is test passes, 1 if test fails
// The function does the following tasks:
// 1. Launches an no-operation NDRange kernel with global size 128 MB
// 2. Measures time taken for the above NDRange kernel using Sycl event
// profiling information
// 3. Obtain kernel clock frequency based on time take for 128 Mglobal
// operations (NDRange)
// 4. If the <report_chk> is true, compare the above hardware frequency with
// Quartus compiled frequency
// 5. Return 0 (test pass) if measured frequency is within 2 of Quartus compiled
// frequency, else report error and terminate test
// NOTE: If <report_chk> is set to false, comparison with Quartus compiled
// frequency is not done and remaining tests in board_test continue without
// this frequency check of 2% error tolerance
int ShimMetrics::KernelClkFreq(sycl::queue &q, bool report_chk) {
// **** Launching an empty kernel (no op) **** //
// ND Range of kernel to launch
constexpr size_t kTotalBytes =
128 * kMB; // 128 MB - this is the min amount known to be available on
// device memory (minimum on device - e.g. Cyclone V)
constexpr size_t kGlobalSize = kTotalBytes / (sizeof(unsigned));
auto e = q.submit([&](sycl::handler &h) {
// Global range (1 dimension)
constexpr size_t kN = kGlobalSize;
// Work group Size (1 dimension)
constexpr size_t kReqdWgSize = 32 * kKB; // 32 KB
h.parallel_for<NopNDRange>(
sycl::nd_range<1>(sycl::range<1>(kN), sycl::range<1>(kReqdWgSize)), [=
](auto id) [[sycl::reqd_work_group_size(1, 1, kReqdWgSize)]]{});
});
// Wait for operation to complete
e.wait();
// **** Get time for kernel event **** //
float time = SyclGetQStExecTimeNs(e);
kernel_freq_ =
((float)kGlobalSize) /
(time / 1000.0f); // Time is returned in nanoseconds,
// converting global size to Mega and ns to s
// **** Compare measured clock frequency with Quartus Prime compiled fmax **** //
// Check Quartus reports if user has selected this (true by default)
if (report_chk) {
ShimMetrics::ReadBinary();
if (!board_info_.fmax_info_) {
std::cerr
<< "Failed to read Quartus compiled fmax from " << kBinaryName
<< "please ensure full kernel compile has run and "
<< "hardware generation completed successfully.\n"
<< "Reporting measured frequency and terminating test, "
<< "none of the other tests will run as hardware frequency "
<< "may not be the expected value and may lead to functional "
<< "errors.\n\n"
<< "Measured Frequency = " << kernel_freq_ << "\n\n"
<< "If you wish to override this failure, please set "
<< "\"report_chk\" variable to \"false\" in <board_test.cpp> and "
<< "recompile host code using \"-reuse-exe=board_test.fpga\" "
<< "option in compile command.\n"
<< " *** NOTE ***: Please run complete board_test at least once and "
<< "ensure the hardware frequency matches expected frequency, "
<< "mismatch may lead to functional errors.\n\n";
return 1;
} else {
// Quartus compiled frequency found, report it
std::cout << "Measured Frequency = " << kernel_freq_ << " MHz \n";
std::cout << "Quartus Compiled Frequency = "
<< board_info_.quartus_fmax_ << " MHz \n\n";
// Check that hardware frequency is within 2% of Quartus compiled
// frequency, terminate test if its not
float PercentError = (fabs(board_info_.quartus_fmax_ - kernel_freq_) /
(board_info_.quartus_fmax_)) *
100;
if (PercentError < 2)
std::cout << "Measured Clock frequency is within 2 percent of "
<< "Quartus compiled frequency. \n";
else {
std::cerr
<< "\nError: measured clock frequency not within 2 "
<< "percent of Quartus compiled frequency. \n"
<< "Terminating test.\n"
<< "If you wish to override this failure, please set "
<< "\"report_chk\" variable to \"false\" in <board_test.cpp> and "
<< "recompile host code using \"-reuse-exe=board_test.fpga\" "
<< "option in compile command.\n"
<< " *** NOTE ***: Please run complete board_test at least once "
<< "and ensure the hardware frequency matches expected frequency, "
<< "mismatch may lead to functional errors.\n\n";
return 1;
}
}
} else {
// User has selected to not to compare measured frequency with Quartus
// compiled frequency, report and continue other tests
std::cout
<< "*** NOTE ***: User has selected to turn off the comparison of "
<< "measured frequency with Quartus compiled frequency by setting the "
<< "\"report_chk\" variable to \"false\" in <board_test.cpp>\n"
<< "The Quartus compiled frequency will not be reported and the "
<< "remaining tests will run without this check\n\n"
<< " *** NOTE ***: Please run complete board_test at least once and "
<< "ensure the hardware frequency matches expected frequency, "
<< "mismatch may lead to functional errors.\n\n"
<< "Reporting measured frequency and continuing remaining tests.\n"
<< "Measured Frequency = " << kernel_freq_ << "\n";
} // End of if - else to check for reports
return 0;
}
/////////////////////////////////////////
// **** KernelLaunchTest function **** //
/////////////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// Returns:
// 0 is test passes, 1 if test fails
// The function does the following tasks:
// 1. Create a pipe between 2 kernels (sender kernel and receiver kernel)
// 2. Launch sender kernel
// 3. Sender kernel writes a known value (kTestValue) to the pipe
// 4. Launch receiver kernel
// 5. Receiver kernel reads the value from pipe and writes to memory
// 6. Host reads data back from memory and checks if the value read is equal to
// the known value (kTestVakue) Test fails if there is a data mismatch
int ShimMetrics::KernelLaunchTest(sycl::queue &q) {
// Value to be written to pipe from KernelSender
constexpr unsigned int kTestValue = 0xdead1234;
// Create device buffer to read back data
std::array<unsigned int, 1> init_val = {0};
sycl::buffer dev_buf(init_val);
// **** Launch sender kernel (writes to pipe) **** //
std::cout << "Launching kernel KernelSender ...\n";
auto e_send = q.submit([&](sycl::handler &h) {
// Global range (1 dimension)
constexpr size_t kN = 1;
// Work group size (1 dimension)
constexpr size_t kReqdWgSize = 1;
h.parallel_for<KernelSender>(
sycl::nd_range<1>(sycl::range<1>(kN), sycl::range<1>(kReqdWgSize)),
[=](auto id) {
SendertoReceiverPipe::write(kTestValue); // Blocking write
});
});
// **** Launch receiver kernel (reads from pipe) **** //
std::cout << "Launching kernel KernelReceiver ...\n";
auto e_receive = q.submit([&](sycl::handler &h) {
// Global range (1 dimension)
constexpr size_t kN = 1;
// Work group size (1 dimension)
constexpr size_t kReqdWgSize = 1;
sycl::accessor mem(dev_buf, h);
h.parallel_for<KernelReceiver>(
sycl::nd_range<1>(sycl::range<1>(kN), sycl::range<1>(kReqdWgSize)),
[=](sycl::nd_item<1> it) {
// Initialize to 0
unsigned int pipe_value = 0;
// Blocking read from pipe
pipe_value = SendertoReceiverPipe::read();
auto gid = it.get_global_id(0);
mem[gid] = pipe_value;
});
});
// **** Wait for sender and receiver kernels to finish **** //
std::cout << " ... Waiting for sender\n";
e_send.wait();
std::cout << "Sender sent the token to receiver\n";
std::cout << " ... Waiting for receiver\n";
e_receive.wait();
// Read back data written by pipe to device memory
sycl::host_accessor h_buf_access{dev_buf};
if (h_buf_access[0] != kTestValue) {
std::cerr << "Kernel Launch Test failed, incorrect value read back from "
<< "pipe between sender and receiver kernel:\n"
<< "Value written to pipe : " << kTestValue
<< " Value read back : " << h_buf_access[0] << "\n";
return 1;
}
return 0;
}
//////////////////////////////////////
// **** KernelLatency function **** //
//////////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// Returns:
// 0 indicating successful completion (no error checks)
// The function does the following tasks:
// 1. Launch large number of no operation kernels
// 2. Measure total time for the above kernels to launch and finish
// 3. Calculate kernel latency and kernel throughput based on total time and
// number of kernels
// 4. Report the latency and throughput and return
int ShimMetrics::KernelLatency(sycl::queue &q) {
// **** Launch no-op kernel multiple times **** //
auto start = std::chrono::system_clock::now();
constexpr size_t kNumKernels = 10000;
for (size_t l = 0; l < kNumKernels; l++) {
auto e = q.single_task<NopSingleTask>([=]() {}); // no operation kernel
}
// Wait for all queued tasks to finish
q.wait();
auto stop = std::chrono::system_clock::now();
// Time taken for kNumKernels to launch and finish
std::chrono::duration<float> time = (stop - start); // in seconds
// **** Report kernel latency **** //
// Storing old state of std::cout to restore after output printed
std::ios old_state(nullptr);
old_state.copyfmt(std::cout);
// Calculating throughput in kernels/ms, averaged over kNumKernels launches
kernel_thruput_ = kNumKernels * 1 / (time.count() * 1000.0f);
kernel_latency_ = (time.count() * 1.0e6f / kNumKernels);
std::cout << "Processed " << kNumKernels << " kernels in "
<< std::setprecision(4) << std::fixed << (time.count() * 1000.0f)
<< " ms\n";
std::cout << "Single kernel round trip time = " << kernel_latency_ << " us\n";
std::cout << "Throughput = " << kernel_thruput_ << " kernels/ms\n";
// Restoring old format after each check_results function call to print
// correct format in current loop
std::cout.copyfmt(old_state);
std::cout << "Kernel execution is complete\n";
// Test complete
return 0;
}
////////////////////////////////////
// **** KernelMemRW function **** //
////////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// Returns:
// 0 is test passes, 1 if device memory allocation is 0 or if test fails
// The function does the following tasks:
// 1. Gets maximum allocation size for device global memory
// 2. Calculates number of unsigned type elements that can be written to device
// and allocates device buffer to span this size
// 3. Allocates host memory for input & output to & from device global memory
// 4. Write initial data to entire device global memory
// 5. Launches kernel to modify the values written to device global memory
// 6. Reads the modified data from device global memory into host memory
// 7. Verifies data matches expected value
// Following additional function is used in this test:
// This is defined in this file and declared in corresponding header
// (kernel_mem_rw.hpp) More details can be found with the corresponsing
// definition
// 1. void InitializeVector(unsigned *vector, size_t size, size_t offset)
int ShimMetrics::KernelMemRW(sycl::queue &q) {
// Test fails if max alloc size is 0
if (max_alloc_size_ == 0) {
std::cerr << "Maximum global memory allocation supported by Sycl device is "
<< "0! Cannot run kernel-to-memory read wite test\n\n";
return 1;
}
std::cout << "Maximum device global memory allocation size is "
<< max_alloc_size_ << " bytes \n";
// Number of integer type vectors supported on the device
size_t max_dev_vectors = max_alloc_size_ / sizeof(unsigned);
// **** Host memory Allocation **** //
// Allocate host vectors
// ND Range kernel uses max_dev_vectors to calculate the global range...
// ...SYCL ID queries are expected to fit within MAX_INT,...
// ...limit the range to prevent truncating data and errors
size_t num_host_vectors =
(max_dev_vectors > (std::numeric_limits<int>::max())) ? kGB
: max_dev_vectors;
size_t host_vector_size_bytes = num_host_vectors * sizeof(unsigned);
// Host memory used for storing input data to device
unsigned *host_data_in = new (std::nothrow) unsigned[host_vector_size_bytes];
// Host memory used to store data read back from device
unsigned *host_data_out = new (std::nothrow) unsigned[host_vector_size_bytes];
// The below while loop checks if host memory allocation failed and tries to
// allocate a smaller chunk if above allocation fails, minimum size of 512
// bytes
while ((host_vector_size_bytes >= (kKB / 2)) &&
(host_data_in == NULL || host_data_out == NULL)) {
num_host_vectors = num_host_vectors / 2;
host_vector_size_bytes = num_host_vectors * sizeof(unsigned);
host_data_in = new (std::nothrow) unsigned[host_vector_size_bytes];
host_data_out = new (std::nothrow) unsigned[host_vector_size_bytes];
}
if (host_data_in == NULL || host_data_out == NULL) {
std::cerr << "Error: Allocation of host buffers for the test failed."
<< "Cannot run kernel-to-memory read wite test\n\n";
if (host_data_in) delete[] host_data_in;
if (host_data_out) delete[] host_data_out;
return 1;
}
std::cout << "Finished host memory allocation for input and output data\n";
// **** Device buffer creation **** //
std::cout << "Creating device buffer\n";
sycl::buffer<unsigned, 1> dev_buf(sycl::range<1>{max_dev_vectors});
// **** Writing to device global memory **** //
// If max_dev_vectors (i.e. device global memory allocation size) >
// MAX_INT,...
// ... multiple iterations/writes to device memory are needed to fill entire
// global memory with preset data ...
// ... To ensure full device global memory is written to (even if it is evenly
// distributable by kGB) - ...
// ... Pad with (kGB - 1) before dividing by kGB.
size_t num_dev_writes =
(max_dev_vectors + kGB - 1) /
kGB; // Calculating number of writes needed (adding kGB - 1 to prevent
// missing out few bytes of global address space due to rounding
// Access device memory in chunks and initialize it
for (size_t vecID = 0; vecID < num_dev_writes; vecID++) {
// Each iteration writes kGB size chunks, so offset increments by lGB
size_t global_offset = vecID * kGB;
size_t current_write_size = kGB;
// Remaining vectors for last set (calculated this way as the padding may
// make the last write bigger than actual global memory size on buffer)
if (vecID == (num_dev_writes - 1)) {
current_write_size = max_dev_vectors - global_offset;
}
// If host buffer - host_data_in is smaller than max_dev_vectors, transfer
// data in multiple writes
size_t offset_bytes = 0;
size_t bytes_rem = current_write_size * sizeof(unsigned);
while (bytes_rem > 0) {
size_t chunk = bytes_rem;
// chunk is greater than host buffer size, break into smaller chunks
if (chunk > host_vector_size_bytes) chunk = host_vector_size_bytes;
// Number of elements written in 1 transfer (copy operation)
num_host_vectors = chunk / sizeof(unsigned);
// Offset if max_dev_vectors chunk is broken into smaller portions
size_t offset = offset_bytes / sizeof(unsigned);
// Initialize input data on host with the total offset value
InitializeVector(host_data_in, num_host_vectors,
(global_offset + offset));
// Submit copy operation (explicit copy from host to device)
q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed is num_host_vectors
// offset starts at 0 - incremented by chunk size each iteration
auto buf_offset = global_offset + offset;
sycl::accessor mem(dev_buf, h, num_host_vectors, buf_offset);
// Writing from host memory to device buffer
h.copy(host_data_in, mem);
}).wait(); // Wait for copy operation to complete
// Increment offset and decrement remaining bytes by chunk size each
// interation
offset_bytes += chunk;
bytes_rem -= chunk;
} // End of write while loop
} // End of write for loop
std::cout << "Finished writing to device buffers \n";
// **** Submitting kernel operation **** //
std::cout << "Launching kernel MemReadWriteStream ... \n";
// Enqueue kernel to access all of global memory
// Multiple enqueues are needed to access the whole ...
// ... global memory address space from the kernel ...
// ... if max_dev_vectors > kGB
for (size_t vecID = 0; vecID < num_dev_writes; vecID++) {
// Each iteration writes kGB size chunks, so offset increments by kGB
size_t global_offset = vecID * kGB;
size_t current_write_size = kGB;
// Remaining vectors for last set (calculated this way as the padding may
// make the last read bigger than actual global memory size on buffer)
if (vecID == (num_dev_writes - 1)) {
current_write_size = max_dev_vectors - global_offset;
}
std::cout << "Launching kernel with global offset : " << global_offset
<< "\n";
// launch kernel
auto e = q.submit([&](sycl::handler &h) {
// Global range (1 dimension)
size_t N = current_write_size;
sycl::accessor mem(dev_buf, h, N, global_offset);
h.parallel_for<MemReadWriteStream>(sycl::range<1>{N},
[=](sycl::item<1> it) {
// Add 2 to all data read from global
// memory (meaning adding 2 to all
// the offsets calculated in write
// loops above)
auto gid = it.get_id(0);
mem[gid] = mem[gid] + 2;
});
});
} // End of kernel launch for loop
// Wait for operation to complete
q.wait();
std::cout << "... kernel finished execution. \n";
// **** Read back data from device global memory & verify **** //
for (size_t vecID = 0; vecID < num_dev_writes; vecID++) {
// Each iteration writes kGB size chunks, so offset increments by kGB
size_t global_offset = vecID * kGB;
size_t current_read_size = kGB;
// Remaining vectors for last set (calculated this way as the padding may
// make the last read bigger than actual global memory size on buffer)
if (vecID == (num_dev_writes - 1)) {
current_read_size = max_dev_vectors - global_offset;
}
// If host buffer - host_data_out is smaller than max_dev_vectors, transfer
// data in multiple reads
size_t bytes_rem = current_read_size * sizeof(unsigned);
size_t offset_bytes = 0;
while (bytes_rem > 0) {
size_t chunk = bytes_rem;
// chunk is greater than host buffer size, break into smaller chunks
if (chunk > host_vector_size_bytes) chunk = host_vector_size_bytes;
// Number of elements read in 1 transfer (copy operation)
num_host_vectors = chunk / sizeof(unsigned);
// Offset if max_dev_vectors chunk is broken into smaller portions
size_t offset = offset_bytes / sizeof(unsigned);
// Submit copy operation (explicit copy from device to host)
q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed is num_host_vectors
// offset starts at 0 - incremented by chunk size each iteration
auto buf_offset = global_offset + offset;
sycl::accessor mem(dev_buf, h, num_host_vectors, buf_offset);
// Reading from device buffer into host memory
h.copy(mem, host_data_out);
}).wait(); // Wait for copy operation to complete
// **** Verify output **** //
// Compare value read back is offset + 2
// initial value written was offset, incremented by 2 in kernel
for (size_t i = 0; i < num_host_vectors; i++) {
if (host_data_out[i] != (unsigned)(global_offset + offset + i + 2)) {
std::cerr << "Verification failed " << i << " : " << host_data_out[i]
<< " != " << ((unsigned)(global_offset + offset + i + 2))
<< "\n";
// Free host memory and return if verification fails
if (host_data_in) delete[] host_data_in;
if (host_data_out) delete[] host_data_out;
return 1;
}
}
// Increment offset and decrement remaining bytes by chunk size each
// interation
offset_bytes += chunk;
bytes_rem -= chunk;
}
} // End of read for loop
// All values verified successfully - test passed
std::cout << "Finished Verification\n";
// Free allocated host memory
if (host_data_in) delete[] host_data_in;
if (host_data_out) delete[] host_data_out;
std::cout << "KERNEL TO MEMORY READ WRITE TEST PASSED \n";
kernel_mem_rw_test_ = true;
return 0;
}
////////////////////////////////////
// **** KernelMemBW function **** //
////////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// Returns:
// 0 if test passes, 1 if device max allocation size is 0 or verification fails
// The function does the following tasks:
// 1. Get max allocation size for device global memory, limit device buffer size
// to 4 GB if the max alloc is greater
// 2. Read board_spec.xml to get number of
// memory interfaces/banks
// 3. Allocate host memory and initialize with random values
// 4. Write the data from host memory to device global memory (initializing
// device global memory with random values)
// 4. Launch 3 kernels for each dimm/memory bank:
// a. MemWriteStream - Write to device global memory
// b. MemReadStream - Read from device global memory
// c. MemReadWriteStream - Read, modify and write to device global memory
// Each of the kernel does this for each dimm (test assumes max of 8 dimms), if
// number of dimms is less, the kernel read/write defaults to lowest memory bank
// (1)
// 5. Calculate bandwidth for read, write and read-write based on time taken for
// each of the operation above
// 6. Read the theoretical bandwidth from board_spec.xml, calculate utilization
// and report results
int ShimMetrics::KernelMemBW(sycl::queue &q) {
std::cout << "Note: This test assumes that design was compiled with "
<< "-Xsno-interleaving option\n\n";
// Test fails if max alloc size is 0
if (max_alloc_size_ == 0) {
std::cerr << "Maximum global memory allocation supported by Sycl device is "
<< "0! Cannot run kernel-to-memory bandwidth test\n\n";
return 1;
}
// Default number of memory banks/DIMMs in the oneAPI shim (assumed to
// prevent test from failing if board_spec.xml data cannot be read)
constexpr size_t kDefaultNumBanks = 8;
size_t num_banks = kDefaultNumBanks;
// If device global memory > 4 GB , limit the transfer size to 4 GB for this
// test
size_t total_bytes_used =
(max_alloc_size_ > (4 * kGB)) ? (4 * kGB) : max_alloc_size_;
// Transfer size in number of unsigned elements
size_t vector_size = total_bytes_used / sizeof(unsigned);
// **** Host memory allocation & initialization **** //
// Host memory used to store input data to device buffer
unsigned *host_data_in = new (std::nothrow) unsigned[total_bytes_used];
// Host memory used to store data read back from device
unsigned *host_data_out = new (std::nothrow) unsigned[total_bytes_used];
// The below while loop checks if hostbuf allocation failed and tries to
// allocate a smaller chunk if above allocation fails, minimum buffer size
// of 512 bytes
while ((total_bytes_used > (kKB / 2)) &&
(host_data_in == NULL || host_data_out == NULL)) {
vector_size = vector_size / 2;
total_bytes_used = vector_size * sizeof(unsigned);
host_data_in = new (std::nothrow) unsigned[total_bytes_used];
host_data_out = new (std::nothrow) unsigned[total_bytes_used];
}
if (host_data_in == NULL || host_data_out == NULL) {
std::cerr << "Error: Allocation of host buffer for the test failed."
<< "Cannot run kernel-to-memory bandwidth test\n\n";
if (host_data_in) delete[] host_data_in;
if (host_data_out) delete[] host_data_out;
return 1;
}
// Initialize host memory
InitializeVector(host_data_in, vector_size);
InitializeVector(host_data_out, vector_size);
// **** Write data to device & launch kernels **** //
std::cout << "\nPerforming kernel transfers of " << (total_bytes_used / kMB)
<< " MBs on the default global memory (address starting at 0)\n";
// The loop launches 3 different kernels to measure:
// kernel to memory write bandwidth using "MemWriteStream" kernel
// kernel to memory read bandwidth using "MemReadStream" kernel
// kernel to memory read-write bandwidth using "MemReadWriteStream" kernel
constexpr size_t kNumKernels = 3;
std::string kernel_name[kNumKernels] = {"MemWriteStream", "MemReadStream",
"MemReadWriteStream"};
// Array used to store the bandwidth measurement for each kernel for each
// memory bank
std::vector<std::vector<float> > bw_kern;
// k = 0 launches kernel_name[0] i.e. MemWriteStream kernel
// k = 1 launches kernel_name[1] i.e. MemReadStream kernel
// k = 2 launches kernel_name[2] i.e. MemReadWriteStream kernel
for (unsigned k = 0; k < kNumKernels; k++) {
std::cout << "Launching kernel " << kernel_name[k] << " ... \n";
std::vector<float> bw_bank;
// Launch each kernel once for each memory bank
for (unsigned b = 0; b < num_banks; b++) {
// Assign a memory channel for each transfer (needed for multi-bank
// oneAPI shims/BSP) default memory channel is 1 (lowest)
sycl::property_list buf_prop_list{sycl::property::buffer::mem_channel{1}};
switch (b) {
// if the board_spec.xml has fewer banks than the dimms, mem_channel
// defaults to 1
case 0:
buf_prop_list = {sycl::property::buffer::mem_channel{1}};
break;
case 1:
buf_prop_list = {sycl::property::buffer::mem_channel{2}};
break;
case 2:
buf_prop_list = {sycl::property::buffer::mem_channel{3}};
break;
case 3:
buf_prop_list = {sycl::property::buffer::mem_channel{4}};
break;
case 4:
buf_prop_list = {sycl::property::buffer::mem_channel{5}};
break;
case 5:
buf_prop_list = {sycl::property::buffer::mem_channel{6}};
break;
case 6:
buf_prop_list = {sycl::property::buffer::mem_channel{7}};
break;
default:
buf_prop_list = {sycl::property::buffer::mem_channel{1}};
break;
} // End of switch for setting buffer property
// **** Create device buffer **** //
// Create kernel input buffer on device (memory bank selected by
// mem_channel property)
sycl::buffer<unsigned, 1> dev_buf(sycl::range<1>{vector_size},
buf_prop_list);
// **** Write random values to device global memory **** ///
// Submit copy operation (explicit copy from host to device)
q.submit([&](sycl::handler &h) {
sycl::accessor mem(dev_buf, h);
// Writing from host memory to device buffer
h.copy(host_data_in, mem);
}).wait(); // Wait for copy operation to complete
// **** Submit kernel tasks **** //
auto e = q.submit([&](sycl::handler &h) {
sycl::accessor mem(dev_buf, h);
// Work group Size (1 dimension)
constexpr size_t kWGSize = 1024 * 32;
constexpr size_t kSimdItems = 16;
// Global range (1 dimension)
// Global range should be evenly distributable by work group size ...
// ... Pad with (kWGSize - 1) before dividing by kWGSize and rounding to
// closest multiple
size_t N = ((vector_size + kWGSize - 1) / kWGSize) * kWGSize;
// Dummy variable used in MemReadStream kernel to prevent memory access
// from being optimized away
unsigned dummy_var = 0;
// Kernel to launch selected based on outer for loop control variable k
switch (k) {
case 0: // kernel MemWriteStream
h.parallel_for<MemWriteStream>(
sycl::nd_range<1>(sycl::range<1>(N), sycl::range<1>(kWGSize)),
[=](sycl::nd_item<1> it)
[[intel::num_simd_work_items(kSimdItems),
sycl::reqd_work_group_size(1, 1, kWGSize)]] {
// Write global ID to memory
auto gid = it.get_global_id(0);
// As global range is larger than max_alloc_size_, limit
// access from kernel to memory to size of global memory
if (gid < vector_size) mem[gid] = gid;
});
break;
case 1: // kernel MemReadStream
h.parallel_for<MemReadStream>(
sycl::nd_range<1>(sycl::range<1>(N), sycl::range<1>(kWGSize)),
[=](sycl::nd_item<1> it)
[[intel::num_simd_work_items(kSimdItems),
sycl::reqd_work_group_size(1, 1, kWGSize)]] {
// Read memory
auto gid = it.get_global_id(0);
// As global range is larger than max_alloc_size_, limit
// access from kernel to memory to size of global memory
if (gid < vector_size) {
unsigned val = mem[gid];
// Use val to prevent compiler from optimizing away this
// variable & read from memory
if (val && (dummy_var == 3))
mem[gid] = 2; // Randomly selected value
}
});
break;
case 2: // MemReadWriteStream (also the default)
default:
h.parallel_for<MemReadWriteStreamNDRange>(
sycl::nd_range<1>(sycl::range<1>(N), sycl::range<1>(kWGSize)),
[=](sycl::nd_item<1> it)
[[intel::num_simd_work_items(kSimdItems),
sycl::reqd_work_group_size(1, 1, kWGSize)]] {
// Read, modify and write to memory
auto gid = it.get_global_id(0);
if (gid < vector_size) mem[gid] = mem[gid] + 2;
});
break;
} // End of switch in q.submit
});
// Wait for kernel tasks to complete
e.wait();
// **** Calculate bandwidth for each memory bank for each kernel **** //
if (k == 0 ||
k == 1) { // Unidirectional (MemReadStream or MemWriteStream kernel)
bw_bank.push_back(((vector_size * sizeof(unsigned) / kMB) /
(SyclGetQStExecTimeNs(e) * 1.0e-9f)));
} else { // bidirectional (MemReadWriteStream kernel)
bw_bank.push_back(((vector_size * sizeof(unsigned) * 2 / kMB) /
(SyclGetQStExecTimeNs(e) * 1.0e-9f)));
}
// **** Read data back from device **** //
// Submit copy operation (copy from device to host)
q.submit([&](sycl::handler &h) {
sycl::accessor mem(dev_buf, h);
// Reading from device buffer into host memory
h.copy(mem, host_data_out);
}).wait();
// **** Verification **** //
// kernel MemReadWriteStream adds 2 to the globaloffset (where global
// range is vector_size)
if ((k == 0) || (k == 2)) {
unsigned val_to_add = (k == 2) ? 2 : 0;
bool result = true;
int prints = 0;
for (size_t j = 0; j < vector_size; j++) {
unsigned input_data = (k == 2) ? (host_data_in[j]) : j;
if (host_data_out[j] != (input_data + val_to_add)) {
if (prints++ < 512) { // only print 512 errors
std::cerr << "Error! Mismatch at element " << j << ":" << std::hex
<< std::showbase << host_data_out[j]
<< " != " << (input_data + val_to_add)
<< std::noshowbase << std::dec
<< "\n"; // Restoring std::cout format
}
result = false;
}
}
if (!result) {
std::cerr << "Verification failed, terminating test\n";
return 1;
}
}
} // End of for loop controlled by num_banks
bw_kern.push_back(bw_bank);
} // End of for loop controlled by kNumKernels
// **** Report bandwidth calculation results **** //
std::cout << "\nSummarizing bandwidth in MB/s/bank for banks 1 to "
<< num_banks << "\n";
kernel_mem_bw_ = 0.0;
for (unsigned k = 0; k < kNumKernels; k++) {
for (unsigned b = 0; b < num_banks; b++) {
std::cout << " " << bw_kern[k][b] << " ";
// Accumulate data from each kernel task to calculate average bandwidth
kernel_mem_bw_ += bw_kern[k][b];
}
std::cout << " " << kernel_name[k] << "\n";
}
// Average bandwidth
kernel_mem_bw_ /= num_banks * kNumKernels;
// Report average kernel memory bandwidth
std::cout << "\nKERNEL-TO-MEMORY BANDWIDTH = " << kernel_mem_bw_
<< " MB/s/bank\n";
delete[] host_data_in;
delete[] host_data_out;
return 0;
}
#if defined(SUPPORTS_USM)
////////////////////////////////////
// ****** USMMemBW function ***** //
////////////////////////////////////
// Inputs:
// queue &q - queue to submit operation
// Returns:
// 0 if test passes, 1 if memory allocation or verification fails
// The function does the following tasks, for each test (memcopy, read, write):
// 1. Allocate host USM for input and output. Initialize input with random
// values and initialize output with zero.
// 2. Launch a kernel to perform one of the following tests:
// - Memcopy: copy data from input USM pointer to output USM pointer
// - Read: read data from input USM pointer
// - Write: write data to output USM pointer
// 3. Host verifies the output data is correct
// 4. Rerun the kernel from several more times to measure bandwidth (the first
// iteration is slow due to one time tasks).
// 5. Calculate and report bandwidth.
int ShimMetrics::USMBWTest(sycl::queue &q) {
return run_test(q, MEMCOPY) | run_test(q, READ) | run_test(q, WRITE);
}
#endif
///////////////////////////////////
// **** ReadBinary function **** //
///////////////////////////////////
// Inputs: None
// Returns: void
// The function does the following task:
// Reads Quartus report data from FPGA hardware binary,
// extracts the Quartus compiled kernel clock frequency(actual)
// The FPGA hardware binary has the "acl_quartus_report.txt" embedded in it
void ShimMetrics::ReadBinary() {
std::string temp_cmd =
"aocl binedit " + kBinaryName + " print .acl.quartus_report";
const char *open_cmd_rep = temp_cmd.c_str();
FILE *bin_content_report = _popen(open_cmd_rep, "r");
if (bin_content_report != NULL) {
char *temp_word = new char[50 * sizeof(char)];
std::string lookup_tag = "Actual clock freq: ";
while ((std::feof(bin_content_report) == 0) && !board_info_.fmax_info_) {
std::string rd_line(fgets(temp_word, 50, bin_content_report));
// Look for the fmax tag
if (rd_line.find(lookup_tag) != std::string::npos) {
board_info_.fmax_info_ = true;
// The look-up tag format is "Actual clock freq: "
size_t st_pos = rd_line.find(lookup_tag) + lookup_tag.size();
// Extract frequency starting at st_pos
board_info_.quartus_fmax_ = std::stof(rd_line.substr(st_pos));
// No need to iterate through rest of the file if fmax tag is
// found
break;
} // End of if extracting fmax from rd_line
} // End of while loop reading file
delete[] temp_word;
}
}
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/host_speed.hpp | // Header file to accompany hostspeed tests
#include <sycl/sycl.hpp>
#include <iomanip>
#include <iostream>
#include "helper.hpp"
// struct used in ReadSpeed & WriteSpeed functions to store transfer speeds
struct Speed {
float fastest;
float slowest;
float average;
float total;
};
///////////////////////////////////
// **** WriteSpeed function **** //
///////////////////////////////////
// Inputs:
// 1. queue &q - queue to submit operation
// 2. buffer<char,1> &device_buffer - device buffer to write to (created in
// calling function)
// 3. char *hostbuf_wr - host memory that contains input data to be written to
// device (allocated in calling function)
// 4. size_t block_bytes - size of 1 transfer to device (in bytes)
// 5. size_t total_bytes - total number of bytes to transfer
// Returns:
// struct Speed with the transfer times
// The function does the following tasks:
// 1. Write data to device in multiple transfers as total_bytes > block_bytes
// (i.e. size of 1 transfer)
// 2. Calculate bandwidth based on measured time for each transfer
struct Speed WriteSpeed(sycl::queue &q, sycl::buffer<char, 1> &device_buffer,
char *hostbuf_wr, size_t block_bytes,
size_t total_bytes) {
// Total number of iterations to transfer all bytes in block_bytes sizes
size_t num_xfers = total_bytes / block_bytes;
assert(num_xfers > 0);
// Sycl event for each transfer
sycl::event evt[num_xfers];
// **** Write to device **** //
for (size_t i = 0; i < num_xfers; i++) {
// Submit copy operation (explicit copy from host to device)
evt[i] = q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed
auto buf_range = block_bytes / sizeof(char);
// offset starts at 0 - incremented by transfer size each iteration (i.e.
// block_bytes)
auto buf_offset = (i * block_bytes) / sizeof(char);
// Accessor to access range of device buffer at buf_offset
sycl::accessor<char, 1, sycl::access::mode::write> mem(
device_buffer, h, buf_range, buf_offset);
h.copy(&hostbuf_wr[buf_offset], mem);
});
}
// Wait for copy to complete
q.wait();
// **** Get the time for each transfer from Sycl event array **** //
struct Speed speed_wr;
speed_wr.average = 0.0f;
speed_wr.fastest = 0.0f;
speed_wr.slowest = 1.0e7f;
for (size_t i = 0; i < num_xfers; i++) {
float time_ns = SyclGetQStExecTimeNs(evt[i]);
float speed_MBps = ((float)block_bytes / kMB) / ((float)time_ns * 1e-9);
if (speed_MBps > speed_wr.fastest) speed_wr.fastest = speed_MBps;
if (speed_MBps < speed_wr.slowest) speed_wr.slowest = speed_MBps;
speed_wr.average += time_ns;
}
// Average write bandwidth
speed_wr.average =
((float)total_bytes / kMB) / ((float)speed_wr.average * 1e-9);
speed_wr.total =
((float)total_bytes / kMB) /
((float)SyclGetTotalTimeNs(evt[0], evt[num_xfers - 1]) * 1e-9);
return speed_wr;
} // End of WriteSpeed
//////////////////////////////////
// **** ReadSpeed function **** //
//////////////////////////////////
// Inputs:
// 1. queue &q - queue to submit operation
// 2. buffer<char,1> &device_buffer - device buffer to read from (created in
// calling function)
// 3. char *hostbuf_rd - pointer to host memory to store data that is read from
// device (allocated in calling function)
// 4. size_t block_bytes - size of 1 transfer to device (in bytes)
// 5. size_t total_bytes - total number of bytes to transfer
// Returns:
// struct Speed with the transfer times
// The function does the following tasks:
// 1. Read data from device in multiple transfers as total_bytes > block_bytes
// (i.e. size of 1 transfer)
// 2. Calculate bandwidth based on measured time for each transfer
struct Speed ReadSpeed(sycl::queue &q, sycl::buffer<char, 1> &device_buffer,
char *hostbuf_rd, size_t block_bytes,
size_t total_bytes) {
// Total number of iterations to transfer all bytes in block_bytes sizes
size_t num_xfers = total_bytes / block_bytes;
assert(num_xfers > 0);
// Sycl event for each transfer
sycl::event evt[num_xfers];
// **** Read from device **** //
for (size_t i = 0; i < num_xfers; i++) {
// Submit copy operation (explicit copy from device to host)
evt[i] = q.submit([&](sycl::handler &h) {
// Range of buffer that needs to accessed
auto buf_range = block_bytes / sizeof(char);
// offset starts at 0 - incremented by transfer size each iteration (i.e
// block_bytes)
auto buf_offset = (i * block_bytes) / sizeof(char);
// Accessor to access range of device buffer at buf_offset
sycl::accessor<char, 1, sycl::access::mode::read> mem(
device_buffer, h, buf_range, buf_offset);
h.copy(mem, &hostbuf_rd[buf_offset]);
});
}
// Wait for copy to complete
q.wait();
// **** Get the time for each transfer from Sycl event array **** //
struct Speed speed_rd;
speed_rd.average = 0.0f;
speed_rd.fastest = 0.0f;
speed_rd.slowest = 1.0e7f;
for (size_t i = 0; i < num_xfers; i++) {
float time_ns = SyclGetQStExecTimeNs(evt[i]);
float speed_MBps = ((float)block_bytes / kMB) / ((float)time_ns * 1e-9);
if (speed_MBps > speed_rd.fastest) speed_rd.fastest = speed_MBps;
if (speed_MBps < speed_rd.slowest) speed_rd.slowest = speed_MBps;
speed_rd.average += time_ns;
}
// Average read bandwidth
speed_rd.average =
((float)total_bytes / kMB) / ((float)speed_rd.average * 1e-9);
speed_rd.total =
((float)total_bytes / kMB) /
((float)SyclGetTotalTimeNs(evt[0], evt[num_xfers - 1]) * 1e-9);
return speed_rd;
} // End of ReadSpeed
/////////////////////////////////////
// **** CheckResults function **** //
/////////////////////////////////////
// Inputs:
// 1. char *hostbuf_rd - pointer to host memory with data read back from device
// (allocated in calling function)
// 2. char *hostbuf_wr - pointer to host memory with input data written to
// device (allocated in calling function)
// 3. maxchars - size of comparison
// Returns:
// true if verification is successfull
// The function does the following tasks:
// 1. Compare maxchars elements of hostbuf_rd to hostbuf_wr
// 2. Return false if a mismatch is found
// 3. Return true if all values read back from device match the values that were
// written
bool CheckResults(char *hostbuf_rd, char *hostbuf_wr, size_t maxchars) {
bool result = true;
int prints = 0;
for (auto j = 0; j < maxchars; j++) {
if (hostbuf_rd[j] != hostbuf_wr[j]) {
if (prints++ < 512) { // only print 512 errors
std::cerr << "Error! Mismatch at element " << j << ":" << std::setw(8)
<< std::hex << std::showbase << hostbuf_rd[j]
<< " != " << hostbuf_wr[j] << ", xor = " << std::setfill('0')
<< (hostbuf_rd[j] ^ hostbuf_wr[j]) << "\n";
}
result = false;
}
}
return result;
} // End of CheckResults
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/board_test.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iostream>
#include "exception_handler.hpp"
// Test related header files
#include "board_test.hpp"
int main(int argc, char* argv[]) {
// Always print small help at the beginning of board test
PrintHelp(0);
// Default is to run all tests
int test_to_run = 0;
// test_to_run value changed according to user selection if user has provided
// an input using "-test=<test_number>" option (see PrintHelp function for
// test details)
if (argc == 2) {
std::string tmp_test(argv[1]);
if ((tmp_test.compare(0, 6, "-test=")) == 0) {
test_to_run = std::stoi(tmp_test.substr(6));
if (test_to_run < 0 || test_to_run > 7) {
std::cerr
<< "Not a valid test number, please select the correct test from "
<< "list above and re-run binary with updated value.\n\n";
return 1;
}
} else if ((tmp_test.compare(0, 5, "-help")) == 0) {
PrintHelp(1);
return 0;
} else {
std::cerr << "Incorrect argument passed to ./board_test.fpga! Cannot run "
<< "test\n, please refer to usage information above for "
<< "correct command.\nTerminating test!\n";
return 1;
}
}
if (test_to_run > 0)
std::cout << "User has selected to run only test number " << test_to_run
<< " from test list above\n";
else
std::cout << "Running all tests \n";
// Device Selection
// Select either:
// - the FPGA emulator device (CPU emulation of the FPGA) using FPGA_EMULATOR
// macro
// - the FPGA device (a real FPGA)
#if FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Variable ORed with result of each test
// Value of 0 at the end indicates all tests completed successfully
int ret = 0;
// Queue creation
try {
// queue properties to enable profiling
sycl::property_list q_prop_list{sycl::property::queue::enable_profiling()};
// Create a queue bound to the chosen device
// If the device is unavailable, a SYCL runtime exception is thrown
sycl::queue q(selector, fpga_tools::exception_handler, q_prop_list);
auto device = q.get_device();
// Print out the device information.
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>()
<< std::endl;
// Create a oneAPI Shim object
ShimMetrics hldshim(q);
// Test 1 - Host speed and host read write test
if (test_to_run == 0 || test_to_run == 1) {
std::cout << "\n*****************************************************************\n"
<< "*********************** Host Speed Test *************************\n"
<< "*****************************************************************\n\n";
ret |= hldshim.HostSpeed(q);
std::cout << "\n*****************************************************************\n"
<< "********************* Host Read Write Test **********************\n"
<< "*****************************************************************\n\n";
// Tasks run in Host read write with dev_offset=0 (aligned dev addr):
// 1. write from unaligned host memory to aligned device memory address
// 2. read from aligned device memory to aligned host memory
size_t dev_offset = 0;
int ret_hostrw = hldshim.HostRWTest(q, dev_offset);
if (ret_hostrw != 0) {
std::cerr << "Error: Host read write test failed with aligned dev "
<< "address (dev_offset = " << dev_offset << ")\n"
<< "\nBOARD TEST FAILED\n";
return 1;
}
// Do not run on SoC boards. ARM processor does not support unaligned memory
// access
#ifndef __arm__
// unaligned device addr
dev_offset = 3;
ret_hostrw = hldshim.HostRWTest(q, dev_offset);
if (ret_hostrw != 0) {
std::cerr << "Error: Host read write test failed with unaligned dev "
<< "address (dev_offset = " << dev_offset << ")\n"
<< "\nBOARD TEST FAILED\n";
return 1;
}
#endif
if (!ret_hostrw) std::cout << "\nHOST READ-WRITE TEST PASSED!\n";
ret |= ret_hostrw;
}
// Test 2 - Kernel clock frequency (this is measured before all tests except
// 1)
if (test_to_run == 0 || test_to_run == 5 || test_to_run == 2 ||
test_to_run == 3 || test_to_run == 4 || test_to_run == 6 ||
test_to_run == 7) {
std::cout << "\n*****************************************************************\n"
<< "******************* Kernel Clock Frequency Test ***************\n"
<< "*****************************************************************\n\n";
#if defined(FPGA_EMULATOR)
std::cout << "Kernel clock frequency test is not run in emulation, "
<< "skipping this test \n";
#else
// This test offers the option to skip reading compiled kernel frequency
// from reports using report_chk variable (either user does not have
// reports or purposely wants to skip when there is a bigger mismatch in
// measured vs compiled value) Ideally should be true as skipping this
// check can lead to erroneous behavior due to kernel clock frequency
// issues on hardware
bool report_chk = true;
int ret_kernel_clk = hldshim.KernelClkFreq(q, report_chk);
// If test failed and user has selected to check the Quartus compiled
// frequency, then terminate test
if (ret_kernel_clk && report_chk) {
std::cerr << "\nBOARD TEST FAILED\n";
return 1;
}
ret |= ret_kernel_clk;
#endif
}
// Test 3 - Kernel Launch Test
if (test_to_run == 0 || test_to_run == 3) {
std::cout << "\n*****************************************************************\n"
<< "********************* Kernel Launch Test ************************\n"
<< "*****************************************************************\n\n";
int ret_kernel_launch_test = hldshim.KernelLaunchTest(q);
if (ret_kernel_launch_test == 0) {
std::cout << "\nKERNEL_LAUNCH_TEST PASSED\n";
} else {
std::cerr << "Error: Kernel Launch Test Failed\n"
<< "\nBOARD TEST FAILED\n";
return 1;
}
ret |= ret_kernel_launch_test;
}
// Test 4 - Kernel Latency Measurement
if (test_to_run == 0 || test_to_run == 4) {
std::cout << "\n*****************************************************************\n"
<< "******************** Kernel Latency **************************\n"
<< "*****************************************************************\n\n";
ret |= hldshim.KernelLatency(q);
}
// Test 5 - Kernel-to-Memory Read Write Test
if (test_to_run == 0 || test_to_run == 5) {
std::cout << "\n*****************************************************************\n"
<< "************* Kernel-to-Memory Read Write Test ***************\n"
<< "*****************************************************************\n\n";
int ret_kernel_mem_rw = hldshim.KernelMemRW(q);
if (ret_kernel_mem_rw != 0) {
std::cerr << "Error: kernel-memory read write test failed. \n"
<< "\nBOARD TEST FAILED\n";
return 1;
}
ret |= ret_kernel_mem_rw;
}
// Test 6 - Kernel-to-Memory Bandwidth Measurement
if (test_to_run == 0 || test_to_run == 6) {
std::cout << "\n*****************************************************************\n"
<< "***************** Kernel-to-Memory Bandwidth *****************\n"
<< "*****************************************************************\n\n";
ret |= hldshim.KernelMemBW(q);
}
// Test 7 - USM
if (test_to_run == 0 || test_to_run == 7) {
std::cout << "\n*****************************************************************\n"
<< "*********************** USM Bandwidth *************************\n"
<< "*****************************************************************\n\n";
#if defined(SUPPORTS_USM)
ret |= hldshim.USMBWTest(q);
#else
if (q.get_device().has(sycl::aspect::usm_host_allocations)) {
std::cout << "USM support was detected but the SUPPORTS_USM macro was "
<< "not defined; USM-related tests will not run.\nTo enable "
<< "these tests, please compile with the SUPPORTS_USM macro "
<< "defined.\n";
} else {
std::cout << "Board does not support USM, skipping this test.\n";
}
#endif
}
} // End of try block
catch (sycl::exception const& e) {
// Catches exceptions in the host code
std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";
// Most likely the runtime couldn't find FPGA hardware!
if (e.code().value() == CL_DEVICE_NOT_FOUND) {
std::cerr << "If you are targeting an FPGA, please ensure that your "
<< "system has a correctly configured FPGA board.\n"
<< "Run sys_check in the oneAPI root directory to verify.\n"
<< "If you are targeting the FPGA emulator, compile with "
<< "-DFPGA_EMULATOR.\n";
}
// Caught exception, terminate program
std::terminate();
} // End of catch block
// If value of returns from all tests is 0 (i.e. without
// errors) - Board test passed
if (ret == 0)
std::cout << "\nBOARD TEST PASSED\n";
else
std::cerr << "\nBOARD TEST FAILED\n";
return ret;
} // End of main
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/src/helper.hpp | // Header file to accompany board_test
#include <sycl/sycl.hpp>
constexpr size_t kKB = 1024;
constexpr size_t kMB = 1024 * 1024;
constexpr size_t kGB = 1024 * 1024 * 1024;
constexpr size_t kRandomSeed = 1009;
#if defined(_WIN32) || defined(_WIN64)
std::string kBinaryName = "board_test.fpga.exe";
#elif __linux__
std::string kBinaryName = "board_test.fpga";
#define _popen popen
#define _pclose pclose
#endif
//////////////////////////////////
// **** PrintHelp function **** //
//////////////////////////////////
// Input:
// int details - Selection between long help or short help
// Returns:
// None
// The function does the following task:
// Prints short help with usage infomation and a longer help with details about
// each test
void PrintHelp(int details) {
if (!details) {
std::cout << "\n*** Board_test usage information ***\n"
<< "Command to run board_test using generated binary:\n"
<< " > To run all tests (default): run " << kBinaryName << "\n"
<< " > To run a specific test (see list below); pass the test "
<< "number as argument to \"-test\" option: \n"
<< " Linux: ./board_test.fpga -test=<test_number>\n"
<< " Windows: board_test.exe -test=<test_number>\n"
<< " > To see more details on what each test does use"
<< " -help option\n"
<< "The tests are:\n"
<< " 1. Host Speed and Host Read Write Test\n"
<< " 2. Kernel Clock Frequency Test\n"
<< " 3. Kernel Launch Test\n"
<< " 4. Kernel Latency Measurement\n"
<< " 5. Kernel-to-Memory Read Write Test\n"
<< " 6. Kernel-to-Memory Bandwidth Test\n"
<< " 7. Unified Shared Memory Bandwidth Test\n"
<< "Note: Kernel Clock Frequency is run along with all tests "
<< "except 1 (Host Speed and Host Read Write test)\n\n";
} else {
std::cout
<< "*** Board_test test details ***\n"
<< "The tests are:\n\n"
<< " * 1. Host Speed and Host Read Write Test *\n"
<< " Host Speed and Host Read Write test check the host to device "
<< "interface\n"
<< " Host Speed test measures the host to device global memory "
<< "read, write as well as read-write bandwidth and reports it\n"
<< " Host Read Write Test writes does unaligned memory to unaligned "
<< "device memory writes as well as reads from device to unaligned "
<< "host memory\n\n"
<< " * 2. Kernel Clock Frequency Test *\n"
<< " Kernel Clock Frequency Test measures the kernel clock "
<< "frequency of the bitstream running on the FPGA and compares this "
<< "to the Quartus compiled frequency for the kernel.\n\n"
<< " * 3. Kernel Launch Test *\n"
<< " Kernel Launch test checks if the kernel launched and executed "
<< "successfully. This is done by launching a sender kernel that "
<< "writes a value to a pipe, this pipe is read by the receiver "
<< "kernel, which completes if the correct value is read.\n"
<< " This test will hang if the receiver kernel does not receive "
<< "the correct value\n\n"
<< " * 4. Kernel Latency Measurement *\n"
<< " This test measures the round trip kernel latency by launching "
<< "a no-operation kernel\n\n"
<< " * 5. Kernel-to-Memory Read Write Test *\n"
<< " Kernel-to-Memory Read Write test checks kernel to device "
<< "global memory interface. The test writes data to the entire device "
<< "global memory from host; the kernel then reads -> modifies and "
<< "writes the data back to the device global memory."
<< " The host reads the modified data back and verifies the read "
<< "back values match expected value\n"
<< " * 6. Kernel-to-Memory Bandwidth Test *\n"
<< " Kernel-to-Memory Bandwidth test measures the kernel to device "
<< "global memory bandwidth and compares this with the theoretical "
<< "bandwidth defined in board_spec.xml file in the oneAPI shim/BSP.\n"
<< " * 7. Unified Shared Memory (USM) Bandwidth Test *\n"
<< " Unified Shared Memory Bandwidth test measures and reports the "
<< "average throughput of copying data between, reading data from, and "
<< "writing data to host USM. The SUPPORTS_USM macro must be specified "
<< "at compile-time in order to run this test. \n\n"
<< " Note: This test assumes that design was compiled with "
<< "-Xsno-interleaving option\n\n"
<< "Please use the commands shown at the beginning of this help to run "
<< "all or one of the above tests\n\n";
}
} // End of PrintHelp
/////////////////////////////////////////////
// **** SyclGetQStExecTimeNs function **** //
/////////////////////////////////////////////
// Input:
// event e - Sycl event with profiling information
// Returns:
// Difference in time from command start to command end (in nanoseconds)
// The function does the following task:
// Gets profiling information from a Sycl event and
// returns execution time for a given SYCL event from a queue
unsigned long SyclGetQStExecTimeNs(sycl::event e) {
unsigned long start_time =
e.get_profiling_info<sycl::info::event_profiling::command_start>();
unsigned long end_time =
e.get_profiling_info<sycl::info::event_profiling::command_end>();
return (end_time - start_time);
} // End of SyclGetQStExecTimeNs
///////////////////////////////////////////
// **** SyclGetTotalTimeNs function **** //
///////////////////////////////////////////
// Input:
// event first_evt - Sycl event with profiling information
// event last_evt - another Sycl event with profiling information
// Returns:
// Difference in time from command submission of first event to command end of
// last event (in nanoseconds)
// The function does the following task:
// Gets profiling information from two different Sycl events and
// returns the total execution time for all events between first and last
unsigned long SyclGetTotalTimeNs(sycl::event first_evt, sycl::event last_evt) {
unsigned long first_evt_start =
first_evt.get_profiling_info<sycl::info::event_profiling::command_start>();
unsigned long last_evt_end =
last_evt.get_profiling_info<sycl::info::event_profiling::command_end>();
return (last_evt_end - first_evt_start);
} // End of SyclGetTotalTimeNs
/////////////////////////////////////////
// **** InitializeVector function **** //
/////////////////////////////////////////
// Inputs:
// 1. unsigned *vector - pointer to host memory that has to be initialized
// (allocated in calling function)
// 2. size_t size - number of elements to initialize
// 3. size_t offset - value to use for initialization
// Returns:
// None
// The function does the following task:
// Initializes "size" number of elements in memory pointed
// to with "offset + i", where i is incremented by loop controlled by "size"
void InitializeVector(unsigned *vector, size_t size, size_t offset) {
for (size_t i = 0; i < size; ++i) {
vector[i] = offset + i;
}
}
/////////////////////////////////////////
// **** InitializeVector function **** //
/////////////////////////////////////////
// Inputs:
// 1. unsigned *vector - pointer to host memory that has to be initialized
// (allocated in calling function)
// 2. size_t size - number of elements to initialize
// Returns:
// None
// The function does the following task:
// Initializes "size" number of elements in memory pointed
// to with random values (output of rand() function)
void InitializeVector(unsigned *vector, size_t size) {
for (size_t i = 0; i < size; ++i) {
vector[i] = rand();
}
} | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <list>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "cholesky.hpp"
#include "exception_handler.hpp"
// Use "#define DEBUG" to print debugging information such as matrices content
/*
COMPLEX, MATRIX_DIMENSION and FIXED_ITERATIONS are defined
by the build system.
Depending on the value of COMPLEX, the real or complex Cholesky decomposition
is defined (A = LL*)
Function arguments:
- a_matrix: The input matrix.
- l_matrix The L matrix. The function will overwrite this matrix.
The vector will only contain the lower triangular elements
of the matrix, in a row by row fashion.
- q: The device queue.
- matrix_count: Number of matrices to decompose.
- repetitions: The number of repetitions of the computation to execute.
(for performance evaluation)
*/
template <typename T, bool is_complex>
void CholeskyDecomposition(std::vector<T> &a_matrix, std::vector<T> &l_matrix,
sycl::queue &q, int matrix_count, int repetitions) {
CholeskyDecompositionImpl<MATRIX_DIMENSION, FIXED_ITERATIONS, is_complex,
float>(a_matrix, l_matrix, q, matrix_count,
repetitions);
}
/*
Returns true if both the real and complex parts of the given ac_complex
value are finite
*/
bool IsFinite(ac_complex<float> val) {
return std::isfinite(val.r()) && std::isfinite(val.i());
}
/*
Returns true if the given value is finite
*/
bool IsFinite(float val) { return std::isfinite(val); }
/*
Returns a random floating-point value between min and max
*/
float RandomValueInInterval(float min, float max) {
return min + static_cast<float>(rand()) /
(static_cast<float>(RAND_MAX) / (max - min));
}
int main(int argc, char *argv[]) {
constexpr size_t kRandomSeed = 1138;
constexpr size_t kRows = MATRIX_DIMENSION;
constexpr size_t kColumns = MATRIX_DIMENSION;
constexpr size_t kAMatrixSize = kRows * kColumns;
constexpr size_t kLMatrixSize = (kColumns * (kColumns + 1)) / 2;
constexpr bool kComplex = COMPLEX != 0;
#if defined(FPGA_SIMULATOR)
constexpr size_t kMatricesToDecompose = 1;
#else
constexpr size_t kMatricesToDecompose = 8;
#endif
// Get the number of times we want to repeat the decomposition
// from the command line.
#if defined(FPGA_EMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 16;
#elif defined(FPGA_SIMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 1;
#else
int repetitions = argc > 1 ? atoi(argv[1]) : 819200;
#endif
if (repetitions < 1) {
std::cerr << "Number of repetitions given is lower than 1." << std::endl;
std::cerr << "The decomposition must occur at least 1 time." << std::endl;
std::cerr << "Increase the number of repetitions (e.g. 16)." << std::endl;
return 1;
}
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::queue q = sycl::queue(
selector, fpga_tools::exception_handler,
sycl::property_list{sycl::property::queue::enable_profiling()});
sycl::device device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>().c_str()
<< std::endl;
// Select a type for this compile depending on the value of COMPLEX
using T = std::conditional_t<kComplex, ac_complex<float>, float>;
// Create vectors to hold all the input and output matrices
std::vector<T> a_matrix;
std::vector<T> l_matrix;
a_matrix.resize(kAMatrixSize * kMatricesToDecompose);
l_matrix.resize(kLMatrixSize * kMatricesToDecompose);
std::cout << "Generating " << kMatricesToDecompose << " random ";
if constexpr (kComplex) {
std::cout << "complex ";
} else {
std::cout << "real ";
}
std::cout << "matri" << (kMatricesToDecompose > 1 ? "ces" : "x")
<< " of size " << kRows << "x" << kColumns << " " << std::endl;
// Generate the random (hermitian and positive-definite) input matrices
srand(kRandomSeed);
for (int mat_idx = 0; mat_idx < kMatricesToDecompose; mat_idx++) {
// Construct a single random hermitian and positive-definite matrix
// To do so we, we generate a hermitian matrix A where each element
// is between 0 and 1.
// Since A(i,j) < 1 by construction and a symmetric diagonally dominant
// matrix is symmetric positive definite we can be sure to have a
// symmetric diagonally dominant matrix by adding nI to A
// A = A + n*eye(n);
// For complex matrices, the diagonal elements must be real.
// Random min and max values for the random floating-point value
// generation
constexpr float kRandomMin = 0;
constexpr float kRandomMax = 1;
int current_matrix = mat_idx * kAMatrixSize;
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
float diag_scaling = (row == col) ? float{kRows} : 0;
int index = current_matrix + (col * kRows) + row;
int transpose_index = current_matrix + (row * kRows) + col;
if (col >= row) {
float random_real = RandomValueInInterval(kRandomMin, kRandomMax);
#if COMPLEX == 0
a_matrix[index] = random_real + diag_scaling;
#else
float random_imag =
row == col ? float{0}
: RandomValueInInterval(kRandomMin, kRandomMax);
ac_complex<float> random_complex{random_real + diag_scaling,
random_imag};
a_matrix[index] = random_complex;
#endif
} else {
// conjugate transpose
#if COMPLEX == 0
a_matrix[index] = a_matrix[transpose_index];
#else
a_matrix[index] = a_matrix[transpose_index].conj();
#endif
}
} // end of col
} // end of row
#ifdef DEBUG
std::cout << "A MATRIX " << mat_idx << std::endl;
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
std::cout << a_matrix[current_matrix + (col * kRows) + row] << " ";
} // end of col
std::cout << std::endl;
} // end of row
#endif
} // end of mat_idx
std::cout << "Computing the Cholesky decomposition of "
<< kMatricesToDecompose << " matri"
<< (kMatricesToDecompose > 1 ? "ces " : "x ") << repetitions
<< " times" << std::endl;
CholeskyDecomposition<T, kComplex>(a_matrix, l_matrix, q,
kMatricesToDecompose, repetitions);
// For output post-processing (op)
T l_matrix_op[kRows][kColumns];
// Floating-point error threshold value at which we decide that the design
// computed an incorrect value
constexpr float kErrorThreshold = 1e-4;
// Check L matrices
std::cout << "Verifying results..." << std::endl;
for (int mat_idx = 0; mat_idx < kMatricesToDecompose; mat_idx++) {
// Keep track of L element index
size_t l_idx = 0;
// Read the L matrix from the output vector to the l_matrix_op matrix
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
if (j > i)
l_matrix_op[i][j] = 0;
else {
l_matrix_op[i][j] = l_matrix[(mat_idx * kLMatrixSize) + l_idx];
l_idx++;
}
}
}
#ifdef DEBUG
std::cout << "L MATRIX" << std::endl;
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
std::cout << l_matrix_op[i][j] << " ";
}
std::cout << std::endl;
}
#endif
// Count the number of errors found for this matrix
size_t error_count = 0;
bool error = false;
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
// Compute LL* at index i,j
T l_l_star_ij{0};
for (size_t k = 0; k < kColumns; k++) {
#if COMPLEX == 0
l_l_star_ij += (l_matrix_op[i][k] * l_matrix_op[j][k]);
#else
l_l_star_ij += (l_matrix_op[i][k] * l_matrix_op[j][k].conj());
#endif
}
// Verify that all the results are OK:
// LL* = A at index i,j
bool ll_star_eq_a;
// L is finite at index i,j
bool l_is_finite;
int current_matrix = mat_idx * kAMatrixSize;
int current_element = (j * kRows) + i;
#if COMPLEX == 0
ll_star_eq_a = abs(a_matrix[current_matrix + current_element] -
l_l_star_ij) < kErrorThreshold;
#else
ll_star_eq_a = (abs(a_matrix[current_matrix + current_element].r() -
l_l_star_ij.r()) < kErrorThreshold) &&
(abs(a_matrix[current_matrix + current_element].i() -
l_l_star_ij.i()) < kErrorThreshold);
#endif
l_is_finite = ((i < kColumns) && IsFinite(l_matrix_op[i][j])) ||
(i >= kColumns);
// If any of the checks failed
if (!ll_star_eq_a || !l_is_finite) {
// Increase the error count for this matrix
error_count++;
// Continue counting the errors even if we are going to
// produce an error
if (error) {
continue;
}
std::cerr << "Error in matrix " << mat_idx << std::endl;
if (!ll_star_eq_a) {
std::cerr
<< "Error: A[" << i << "][" << j << "] = "
<< a_matrix[(current_matrix * kAMatrixSize) + (j * kRows) + i]
<< " but LL*[" << i << "][" << j << "] = " << l_l_star_ij
<< std::endl;
}
if (!l_is_finite) {
std::cerr << "L[" << i << "][" << j << "] = " << l_matrix_op[i][j]
<< " is not finite" << std::endl;
}
error = true;
}
} // end of j
} // end of i
if (error_count > 0) {
std::cerr << std::endl << "FAILED" << std::endl;
std::cerr << std::endl
<< "!!!!!!!!!!!!!! " << error_count << " errors" << std::endl;
return 1;
}
} // end of mat_idx
std::cout << std::endl << "PASSED" << std::endl;
return 0;
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::cerr << " If you are targeting FPGA hardware, "
"ensure that your system is connected to an FPGA board that "
"is set up correctly"
<< std::endl;
std::cerr << " If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR"
<< std::endl;
std::terminate();
} catch (std::bad_alloc const &e) {
std::cerr << "Caught a memory allocation exception on the host: "
<< e.what() << std::endl;
std::cerr << " You can reduce the memory requirement by reducing the "
"number of matrices generated. Specify a smaller number when "
"running the executable."
<< std::endl;
std::cerr << " In this run, more than "
<< ((kAMatrixSize + kLMatrixSize) * 2 * kMatricesToDecompose *
sizeof(float)) /
pow(2, 30)
<< " GBs of memory was requested for the decomposition of a "
<< "matrix of size " << kRows << " x " << kColumns << std::endl;
std::terminate();
}
} // end of main
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_elem_per_bank elements.
Repeat these operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Output matrix pipe
>
void MatrixReadFromDDRToPipe(
TT* matrix_ptr, // Input matrix pointer
int matrix_count, // Number of matrices to read from DDR
int repetitions // Number of times to write the same matrix to the pipe
) {
// We may perform an incomplete memory read if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = (rows % num_elem_per_bank) != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst reads of num_elem_per_bank elements required to read a
// full column
constexpr int kLoopIterPerColumn =
(rows / num_elem_per_bank) + kExtraIteration;
// Number of DDR burst reads of num_elem_per_bank to read all the matrices
constexpr int kLoopIter = kLoopIterPerColumn * columns;
// Size in bits of the loop iterator over kLoopIter iterations
constexpr int kLoopIterBitSize = fpga_tools::BitsForMaxValue<kLoopIter + 1>();
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
// Repeatedly read matrix_count matrices from DDR and send them to the pipe
for (int repetition = 0; repetition < repetitions; repetition++) {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
// Keep track of the current element index in the matrix
// Only useful in the case of kIncompleteBurst
int load_index = 0;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> matrix_ptr_located(matrix_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* matrix_ptr_located(matrix_ptr);
#endif
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kLoopIterBitSize, false> li = 0; li < kLoopIter; li++) {
bool last_burst_of_col;
if constexpr (kIncompleteBurst) {
// Check if we are reading the last DDR burst of the current column
last_burst_of_col =
(li % kLoopIterPerColumn) == kLoopIterPerColumn - 1;
}
fpga_tools::NTuple<TT, num_elem_per_bank> ddr_read;
// Perform the DDR burst read of num_elem_per_bank elements
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst) {
// Check if the current read index is beyond the end of the current
// matrix column
bool out_of_bounds =
last_burst_of_col &&
((k % num_elem_per_bank) > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR reads that are relevant (and don't access a
// memory address that may be beyond the matrix last address)
if (!out_of_bounds) {
ddr_read.template get<k>() =
matrix_ptr_located[matrix_index * kMatrixSize + load_index +
k];
}
} else {
ddr_read.template get<k>() =
matrix_ptr_located[matrix_index * kMatrixSize +
(int)(li)*num_elem_per_bank + k];
}
});
if constexpr (kIncompleteBurst) {
// Update the current element index in the input matrix according
// to the read size of the current iteration
load_index +=
last_burst_of_col ? rows % num_elem_per_bank : num_elem_per_bank;
}
MatrixPipe::write(ddr_read);
} // end of li
} // end of matrix_index
} // end of repetition
}
#endif /* __MEMORY_TRANSFERS_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/src/cholesky.hpp | #ifndef __CHOLESKY_HPP__
#define __CHOLESKY_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "streaming_cholesky.hpp"
#include "tuple.hpp"
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class CholeskyDDRToLocalMem;
class Cholesky;
class CholeskyLocalMemToDDR;
class APipe;
class LPipe;
/*
Implementation of the Cholesky decomposition using multiple streaming kernels
Can be configured by datatype, matrix size (must use square matrices), real
and complex.
*/
template <unsigned dimension, // Number of columns/rows in the input matrix
unsigned raw_latency, // RAW latency for triangular loop optimization
bool is_complex, // Selects between ac_complex<T> and T datatype
typename T, // The datatype for the computation
typename TT = std::conditional_t<is_complex, ac_complex<T>, T>
// TT will be ac_complex<T> or T depending on is_complex
>
void CholeskyDecompositionImpl(
std::vector<TT> &a_matrix, // Input matrix A to decompose
std::vector<TT> &l_matrix, // Output matrix L
sycl::queue &q, // Device queue
int matrix_count, // Number of matrices to decompose
int repetitions // Number of repetitions, for performance
// evaluation
) {
constexpr int kAMatrixSize = dimension * dimension;
constexpr int kLMatrixSize = dimension * (dimension + 1) / 2;
constexpr int kNumElementsPerDDRBurst = is_complex ? 4 : 8;
using PipeType = fpga_tools::NTuple<TT, kNumElementsPerDDRBurst>;
// Pipes to communicate the A and L matrices between kernels
using AMatrixPipe = sycl::ext::intel::pipe<APipe, PipeType, 3>;
using LMatrixPipe =
sycl::ext::intel::pipe<LPipe, TT, kNumElementsPerDDRBurst * 4>;
// Allocate FPGA DDR memory.
#if defined (IS_BSP)
TT *a_device = sycl::malloc_device<TT>(kAMatrixSize * matrix_count, q);
TT *l_device = sycl::malloc_device<TT>(kLMatrixSize * matrix_count, q);
#else
// malloc_device are not supported when targetting an FPGA part/family
TT *a_device = sycl::malloc_shared<TT>(kAMatrixSize * matrix_count, q);
TT *l_device = sycl::malloc_shared<TT>(kLMatrixSize * matrix_count, q);
#endif
if ((a_device == nullptr) || (l_device == nullptr)) {
std::cerr << "Error when allocating FPGA DDR" << std::endl;
std::cerr << "The FPGA DDR may be full" << std::endl;
std::cerr << "Try reducing the matrix sizes/count" << std::endl;
return;
}
// Copy the matrices to decompose to the FPGA DDR
q.memcpy(a_device, a_matrix.data(), kAMatrixSize * matrix_count * sizeof(TT))
.wait();
// Launch a kernel that will repeatedly read the matrices on the FPGA DDR
// and write their content to the AMatrixPipe pipe.
auto ddr_read_event = q.single_task<CholeskyDDRToLocalMem>([=] {
MatrixReadFromDDRToPipe<TT, dimension, dimension, kNumElementsPerDDRBurst,
AMatrixPipe>(a_device, matrix_count, repetitions);
});
// Read the A matrix from the AMatrixPipe pipe and compute the Cholesky
// decomposition. Write the L output matrix to the LMatrixPipe pipe.
q.single_task<Cholesky>(
fpga_linalg::StreamingCholesky<T, is_complex, dimension, raw_latency,
kNumElementsPerDDRBurst, AMatrixPipe,
LMatrixPipe>());
auto ddr_write_event = q.single_task<CholeskyLocalMemToDDR>([=
]() [[intel::kernel_args_restrict]] {
// Read the L matrix from the LMatrixPipe pipe and copy it to the FPGA DDR
// Number of DDR bursts of kNumElementsPerDDRBurst required to write
// one vector
constexpr bool kIncompleteBurst =
(kLMatrixSize % kNumElementsPerDDRBurst) != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
constexpr int kLoopIter =
(kLMatrixSize / kNumElementsPerDDRBurst) + kExtraIteration;
// Repeat matrix_count complete L matrix pipe reads
// for as many repetitions as needed
// The loop coalescing directive merges the two outer loops together
// automatically
[[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute
for (int rep_idx = 0; rep_idx < repetitions; rep_idx++) {
for (int matrix_idx = 0; matrix_idx < matrix_count; matrix_idx++) {
for (int li = 0; li < kLoopIter; li++) {
TT bank[kNumElementsPerDDRBurst];
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> vector_ptr(l_device);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* vector_ptr(l_device);
#endif
for (int k = 0; k < kNumElementsPerDDRBurst; k++) {
if (((li * kNumElementsPerDDRBurst) + k) < kLMatrixSize) {
bank[k] = LMatrixPipe::read();
}
}
// Copy the L matrix result to DDR
if constexpr (kIncompleteBurst) {
// Write a burst of kNumElementsPerDDRBurst elements to DDR
#pragma unroll
for (int k = 0; k < kNumElementsPerDDRBurst; k++) {
if (((li * kNumElementsPerDDRBurst) + k) < kLMatrixSize) {
vector_ptr[(matrix_idx * kLMatrixSize) +
(li * kNumElementsPerDDRBurst) + k] = bank[k];
}
}
} else {
// Write a burst of kNumElementsPerDDRBurst elements to DDR
#pragma unroll
for (int k = 0; k < kNumElementsPerDDRBurst; k++) {
vector_ptr[(matrix_idx * kLMatrixSize) +
(li * kNumElementsPerDDRBurst) + k] = bank[k];
}
}
} // end of li
} // end of matrix_idx
} // end of rep_idx
});
ddr_write_event.wait();
// Compute the total time the execution lasted
auto start_time = ddr_read_event.template get_profiling_info<
sycl::info::event_profiling::command_start>();
auto end_time = ddr_write_event.template get_profiling_info<
sycl::info::event_profiling::command_end>();
double diff = (end_time - start_time) / 1.0e9;
// Make sure we throw any asynchronous errors if they have occurred during
// the computation
q.throw_asynchronous();
std::cout << " Total duration: " << diff << " s" << std::endl;
std::cout << "Throughput: " << ((repetitions * matrix_count) / diff) * 1e-3
<< "k matrices/s" << std::endl;
// Copy the L matrices result from the FPGA DDR to the host memory
q.memcpy(l_matrix.data(), l_device, kLMatrixSize * matrix_count * sizeof(TT))
.wait();
// Clean allocated FPGA memory
free(a_device, q);
free(l_device, q);
}
#endif /* __CHOLESKY_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/fft2d/src/fft2d_demo.cpp | #include <math.h>
#define _USE_MATH_DEFINES
#include <cmath>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
#include "fft2d.hpp"
// Forward declarations
void TestFFT(bool mangle, bool inverse);
template <int n>
int Coordinates(int iteration, int i);
template <int lognr_points>
void FourierTransformGold(ac_complex<double> *data, bool inverse);
template <int lognr_points>
void FourierStage(ac_complex<double> *data);
int main(int argc, char **argv) {
if (argc == 1) {
std::cout << "No program argument was passed, running all fft2d variants"
<< std::endl;
// test FFT transform with ordered memory layout
TestFFT(false, false);
// test inverse FFT transform with ordered memory layout
TestFFT(false, true);
// test FFT transform with alternative memory layout
TestFFT(true, false);
// test inverse FFT transform with alternative memory layout
TestFFT(true, true);
} else {
std::string mode = argv[1];
bool mangle{};
bool inverse{};
if (mode == "normal") {
mangle = false;
inverse = false;
} else if (mode == "inverse") {
mangle = false;
inverse = true;
} else if (mode == "mangle") {
mangle = true;
inverse = false;
} else if (mode == "inverse-mangle") {
mangle = true;
inverse = true;
} else {
std::cerr << "Usage: fft2d <mode>" << std::endl;
std::cerr << "Where mode can be normal|inverse|mangle|inverse-mangle|all"
<< std::endl;
std::terminate();
}
TestFFT(mangle, inverse);
}
return 0;
}
void TestFFT(bool mangle, bool inverse) {
try {
// Device selector selection
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::property_list queue_properties{
sycl::property::queue::enable_profiling()};
sycl::queue q =
sycl::queue(selector, fpga_tools::exception_handler, queue_properties);
sycl::device device = q.get_device();
// Print out the device information.
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>() << std::endl;
// Define the log of the FFT size on each dimension and the level of
// parallelism to implement
#if FPGA_SIMULATOR
// Force small sizes in simulation mode to reduce simulation time
constexpr int kLogN = 4;
constexpr int kParallelism = 4;
#else
constexpr int kLogN = LOGN;
constexpr int kParallelism = PARALLELISM;
#endif
static_assert(kParallelism == 4 || kParallelism == 8,
"The FFT kernel implementation only supports 4-parallel and "
"8-parallel FFTs.");
constexpr int kN = 1 << kLogN;
constexpr int kLogParallelism = kParallelism == 8 ? 3 : 2;
// Host memory
ac_complex<float> *host_input_data =
(ac_complex<float> *)std::malloc(sizeof(ac_complex<float>) * kN * kN);
ac_complex<float> *host_output_data =
(ac_complex<float> *)std::malloc(sizeof(ac_complex<float>) * kN * kN);
ac_complex<double> *host_verify =
(ac_complex<double> *)std::malloc(sizeof(ac_complex<double>) * kN * kN);
ac_complex<double> *host_verify_tmp =
(ac_complex<double> *)std::malloc(sizeof(ac_complex<double>) * kN * kN);
if ((host_input_data == nullptr) || (host_output_data == nullptr) ||
(host_verify == nullptr) || (host_verify_tmp == nullptr)) {
std::cerr << "Failed to allocate host memory with malloc." << std::endl;
std::terminate();
}
// Initialize input and produce verification data
for (int i = 0; i < kN; i++) {
for (int j = 0; j < kN; j++) {
int where = mangle ? MangleBits<kLogN>(Coordinates<kN>(i, j))
: Coordinates<kN>(i, j);
host_verify[Coordinates<kN>(i, j)].r() = host_input_data[where].r() =
(float)((double)rand() / (double)RAND_MAX);
host_verify[Coordinates<kN>(i, j)].i() = host_input_data[where].i() =
(float)((double)rand() / (double)RAND_MAX);
}
}
// Device memory
ac_complex<float> *input_data;
ac_complex<float> *output_data;
ac_complex<float> *temp_data;
if (q.get_device().has(sycl::aspect::usm_device_allocations)) {
std::cout << "Using USM device allocations" << std::endl;
// Allocate FPGA DDR memory.
input_data = sycl::malloc_device<ac_complex<float>>(kN * kN, q);
output_data = sycl::malloc_device<ac_complex<float>>(kN * kN, q);
temp_data = sycl::malloc_device<ac_complex<float>>(kN * kN, q);
} else if (q.get_device().has(sycl::aspect::usm_host_allocations)) {
std::cout << "Using USM host allocations" << std::endl;
// No device allocations means that we are probably in an IP authoring
// flow
#if defined IS_BSP
auto prop_list = sycl::property_list{};
#else
// In the IP Authoring flow, we need to define the memory interface.
// For, that we need to assign a location to the memory being accessed.
auto prop_list = sycl::property_list{
sycl::ext::intel::experimental::property::usm::buffer_location(1)};
#endif
input_data = sycl::malloc_host<ac_complex<float>>(kN * kN, q);
output_data = sycl::malloc_host<ac_complex<float>>(kN * kN, q, prop_list);
temp_data = sycl::malloc_host<ac_complex<float>>(kN * kN, q, prop_list);
} else {
std::cerr << "USM device allocations or USM host allocations must be "
"supported to run this sample."
<< std::endl;
std::terminate();
}
if (input_data == nullptr || output_data == nullptr ||
temp_data == nullptr) {
std::cerr << "Failed to allocate USM memory." << std::endl;
std::terminate();
}
// Copy the input data from host DDR to USM memory
q.memcpy(input_data, host_input_data, sizeof(ac_complex<float>) * kN * kN)
.wait();
std::cout << "Launching a " << kN * kN << " points " << kParallelism
<< "-parallel " << (inverse ? "inverse " : "")
<< "FFT transform (" << (mangle ? "alternative" : "ordered")
<< " data layout)" << std::endl;
/*
* A 2D FFT transform requires applying a 1D FFT transform to each matrix
* row followed by a 1D FFT transform to each column of the intermediate
* result.
* A single FFT engine can process rows and columns back-to-back. However,
* as matrix data is stored in global memory, the efficiency of memory
* accesses will impact the overall performance. Accessing consecutive
* memory locations leads to efficient access patterns. However, this is
* obviously not possible when accessing both rows and columns.
*
* The implementation is divided between three concurrent SYCL kernels, as
* depicted below:
*
* -------------------- -------------- --------------------------
* | read matrix rows | ---> | FFT engine | ---> | bit-reverse, transpose |
* | | | | | and write matrix |
* -------------------- -------------- --------------------------
*
* This sequence of kernels does back-to-back row processing followed by a
* data transposition and writes the results back to memory. The host code
* runs these kernels twice to produce the overall 2D FFT transform
*
*
* These kernels transfer data through pipes.
* This avoids the need to read and write intermediate data using global
* memory.
*
* In many cases the FFT engine is a building block in a large application.
* In this case, the memory layout of the matrix can be altered to achieve
* higher memory transfer efficiency. This implementation demonstrates how
* an alternative memory layout can improve performance. The host switches
* between the two memory layouts using a kernel argument. See the
* 'MangleBits' function for additional details.
*/
double start_time;
double end_time;
// This is a limitation of the design
static_assert(kN / kParallelism >= kParallelism);
// Kernel to kernel pipes
using FetchToFFT =
sycl::ext::intel::pipe<class FetchToFFTPipe,
std::array<ac_complex<float>, kParallelism>, 0>;
using FFTToTranspose =
sycl::ext::intel::pipe<class FFTToTransposePipe,
std::array<ac_complex<float>, kParallelism>, 0>;
for (int i = 0; i < 2; i++) {
ac_complex<float> *to_read = i == 0 ? input_data : temp_data;
ac_complex<float> *to_write = i == 0 ? temp_data : output_data;
// Start a 1D FFT on the matrix rows/columns
auto fetch_event = q.single_task<class FetchKernel>(
Fetch<kLogN, kLogParallelism, FetchToFFT, float>{to_read, mangle});
auto fft_event = q.single_task<class FFTKernel>(
FFT<kLogN, kLogParallelism, FetchToFFT, FFTToTranspose, float>{
inverse});
auto transpose_event = q.single_task<class TransposeKernel>(
Transpose<kLogN, kLogParallelism, FFTToTranspose, float>{to_write,
mangle});
fft_event.wait();
transpose_event.wait();
if (i == 0) {
start_time = fetch_event.template get_profiling_info<
sycl::info::event_profiling::command_start>();
} else {
end_time = transpose_event.template get_profiling_info<
sycl::info::event_profiling::command_end>();
}
}
double kernel_runtime = (end_time - start_time) / 1.0e9;
// Copy the output data from the USM memory to the host DDR
q.memcpy(host_output_data, output_data, sizeof(ac_complex<float>) * kN * kN)
.wait();
std::cout << "Processing time = " << kernel_runtime << "s" << std::endl;
double gpoints_per_sec = ((double)kN * kN / kernel_runtime) * 1e-9;
double gflops = 2 * 5 * kN * kN * (log((float)kN) / log((float)2)) /
(kernel_runtime * 1e9);
std::cout << "Throughput = " << gpoints_per_sec << " Gpoints / sec ("
<< gflops << " Gflops)" << std::endl;
// Check signal to noise ratio
// Run reference code
for (int i = 0; i < kN; i++) {
FourierTransformGold<kLogN>(host_verify + Coordinates<kN>(i, 0), inverse);
}
for (int i = 0; i < kN; i++) {
for (int j = 0; j < kN; j++) {
host_verify_tmp[Coordinates<kN>(j, i)] =
host_verify[Coordinates<kN>(i, j)];
}
}
for (int i = 0; i < kN; i++) {
FourierTransformGold<kLogN>(host_verify_tmp + Coordinates<kN>(i, 0),
inverse);
}
for (int i = 0; i < kN; i++) {
for (int j = 0; j < kN; j++) {
host_verify[Coordinates<kN>(j, i)] =
host_verify_tmp[Coordinates<kN>(i, j)];
}
}
double magnitude_sum = 0;
double noise_sum = 0;
for (int i = 0; i < kN; i++) {
for (int j = 0; j < kN; j++) {
int where = mangle ? MangleBits<kLogN>(Coordinates<kN>(i, j))
: Coordinates<kN>(i, j);
double magnitude = (double)host_verify[Coordinates<kN>(i, j)].r() *
(double)host_verify[Coordinates<kN>(i, j)].r() +
(double)host_verify[Coordinates<kN>(i, j)].i() *
(double)host_verify[Coordinates<kN>(i, j)].i();
double noise = (host_verify[Coordinates<kN>(i, j)].r() -
(double)host_output_data[where].r()) *
(host_verify[Coordinates<kN>(i, j)].r() -
(double)host_output_data[where].r()) +
(host_verify[Coordinates<kN>(i, j)].i() -
(double)host_output_data[where].i()) *
(host_verify[Coordinates<kN>(i, j)].i() -
(double)host_output_data[where].i());
magnitude_sum += magnitude;
noise_sum += noise;
}
}
double db = 10 * log(magnitude_sum / noise_sum) / log(10.0);
std::cout << "Signal to noise ratio on output sample: " << db << std::endl;
std::cout << " --> " << (db > 120 ? "PASSED" : "FAILED") << std::endl;
sycl::free(input_data, q);
free(output_data, q);
free(temp_data, q);
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::terminate();
}
}
/////// HELPER FUNCTIONS ///////
// provides a linear offset in the input array
template <int n>
int Coordinates(int iteration, int i) {
return iteration * n + i;
}
// Reference Fourier transform
template <int lognr_points>
void FourierTransformGold(ac_complex<double> *data, bool inverse) {
constexpr int kNrPoints = 1 << lognr_points;
// The inverse requires swapping the real and imaginary component
if (inverse) {
for (int i = 0; i < kNrPoints; i++) {
double tmp = data[i].r();
data[i].r() = data[i].i();
data[i].i() = tmp;
}
}
// Do a FT recursively
FourierStage<lognr_points>(data);
// The inverse requires swapping the real and imaginary component
if (inverse) {
for (int i = 0; i < kNrPoints; i++) {
double tmp = data[i].r();
data[i].r() = data[i].i();
data[i].i() = tmp;
}
}
}
template <int lognr_points>
void FourierStage(ac_complex<double> *data) {
if constexpr (lognr_points > 0) {
constexpr int kNrPoints = 1 << lognr_points;
ac_complex<double> *half1 = (ac_complex<double> *)malloc(
sizeof(ac_complex<double>) * kNrPoints / 2);
ac_complex<double> *half2 = (ac_complex<double> *)malloc(
sizeof(ac_complex<double>) * kNrPoints / 2);
if (half1 == nullptr || half2 == nullptr) {
std::cerr << "Failed to allocate memory in validation function."
<< std::endl;
std::terminate();
}
for (int i = 0; i < kNrPoints / 2; i++) {
half1[i] = data[2 * i];
half2[i] = data[2 * i + 1];
}
FourierStage<lognr_points - 1>(half1);
FourierStage<lognr_points - 1>(half2);
for (int i = 0; i < kNrPoints / 2; i++) {
data[i].r() = half1[i].r() +
cos(2 * M_PI * i / kNrPoints) * half2[i].r() +
sin(2 * M_PI * i / kNrPoints) * half2[i].i();
data[i].i() = half1[i].i() -
sin(2 * M_PI * i / kNrPoints) * half2[i].r() +
cos(2 * M_PI * i / kNrPoints) * half2[i].i();
data[i + kNrPoints / 2].r() =
half1[i].r() - cos(2 * M_PI * i / kNrPoints) * half2[i].r() -
sin(2 * M_PI * i / kNrPoints) * half2[i].i();
data[i + kNrPoints / 2].i() =
half1[i].i() + sin(2 * M_PI * i / kNrPoints) * half2[i].r() -
cos(2 * M_PI * i / kNrPoints) * half2[i].i();
}
free(half1);
free(half2);
}
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/fft2d/src/twiddle_factors.hpp | #define COS8 { \
{ \
{1.0f, 0.9999952912f, 0.9999811649f, 0.9999576211f, 0.9999247193f, 0.9998823404f, 0.9998306036f, 0.9997693896f, 0.9996988177f, 0.9996188283f, 0.9995294213f, 0.9994305968f, 0.9993223548f, 0.9992047548f, 0.9990777373f, 0.9989413023f, 0.9987954497f, 0.9986402392f, 0.9984755516f, 0.9983015656f, 0.9981181026f, 0.9979252815f, 0.997723043f, 0.9975114465f, 0.9972904325f, 0.9970600605f, 0.996820271f, 0.9965711236f, 0.9963126183f, 0.9960446954f, 0.9957674146f, 0.9954807758f, 0.9951847196f, 0.9948793054f, 0.9945645928f, 0.9942404628f, 0.9939069748f, 0.9935641289f, 0.993211925f, 0.9928504229f, 0.9924795628f, 0.9920992851f, 0.9917097688f, 0.9913108349f, 0.9909026623f, 0.9904850721f, 0.9900581837f, 0.9896219969f, 0.9891765118f, 0.9887216687f, 0.988257587f, 0.9877841473f, 0.9873014092f, 0.9868093729f, 0.9863080978f, 0.9857975245f, 0.9852776527f, 0.9847484827f, 0.9842100739f, 0.9836624265f, 0.9831054807f, 0.9825392962f, 0.9819638729f, 0.9813792109f, 0.9807852507f, 0.9801821113f, 0.9795697927f, 0.9789481759f, 0.97831738f, 0.9776773453f, 0.9770281315f, 0.9763697386f, 0.975702107f, 0.9750253558f, 0.974339366f, 0.9736442566f, 0.9729399681f, 0.9722265005f, 0.9715039134f, 0.9707721472f, 0.9700312614f, 0.9692812562f, 0.9685220718f, 0.9677538276f, 0.9669764638f, 0.9661899805f, 0.9653944373f, 0.9645897746f, 0.963776052f, 0.9629532695f, 0.9621214271f, 0.9612804651f, 0.9604305029f, 0.9595715404f, 0.9587034583f, 0.9578264356f, 0.9569403529f, 0.95604527f, 0.9551411867f, 0.9542281032f, 0.9533060193f, 0.9523749948f, 0.9514350295f, 0.950486064f, 0.9495281577f, 0.9485613704f, 0.9475855827f, 0.946600914f, 0.9456073046f, 0.9446048141f, 0.9435934424f, 0.9425731897f, 0.9415440559f, 0.940506041f, 0.9394592047f, 0.9384035468f, 0.9373390079f, 0.9362656474f, 0.9351835251f, 0.9340925217f, 0.932992816f, 0.9318842888f, 0.9307669401f, 0.9296408892f, 0.9285060763f, 0.9273625016f, 0.9262102246f, 0.9250492454f, 0.9238795042f, 0.9227011204f, 0.9215140343f, 0.9203183055f, 0.9191138744f, 0.9179008007f, 0.9166790843f, 0.9154487252f, 0.9142097831f, 0.9129621983f, 0.9117060304f, 0.9104412794f, 0.909168005f, 0.9078860879f, 0.9065957069f, 0.9052967429f, 0.903989315f, 0.9026733041f, 0.9013488293f, 0.9000158906f, 0.8986744881f, 0.8973245621f, 0.8959662318f, 0.8945994973f, 0.893224299f, 0.8918406963f, 0.8904487491f, 0.8890483379f, 0.8876396418f, 0.8862225413f, 0.8847970963f, 0.8833633661f, 0.8819212914f, 0.8804708719f, 0.8790122271f, 0.8775452971f, 0.8760700822f, 0.8745866418f, 0.8730949759f, 0.8715950847f, 0.8700869679f, 0.8685706854f, 0.867046237f, 0.8655136228f, 0.8639728427f, 0.8624239564f, 0.8608669639f, 0.8593018055f, 0.8577286005f, 0.8561473489f, 0.854557991f, 0.8529605865f, 0.851355195f, 0.8497417569f, 0.8481203318f, 0.8464909196f, 0.84485358f, 0.8432082534f, 0.8415549994f, 0.8398938179f, 0.838224709f, 0.8365477324f, 0.8348628879f, 0.8331701756f, 0.8314695954f, 0.8297612071f, 0.8280450702f, 0.8263210654f, 0.8245893121f, 0.8228498101f, 0.8211025f, 0.8193475008f, 0.8175848126f, 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}\
}
#define SIN8 {\
{\
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}\
}
#define SIN4 {\
{\
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}\
} | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/fft2d/src/fft2d.hpp | #ifndef __FFT2D_HPP__
#define __FFT2D_HPP__
#define _USE_MATH_DEFINES
#include <cmath>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
// Large twiddle factors tables
#include "twiddle_factors.hpp"
// Complex single-precision floating-point feedforward FFT / iFFT engine
// Configurable in 4 or 8-parallel versions.
//
// See Mario Garrido, Jesús Grajal, M. A. Sanchez, Oscar Gustafsson:
// Pipeline Radix-2k Feedforward FFT Architectures.
// IEEE Trans. VLSI Syst. 21(1): 23-32 (2013))
//
// The log(points) of the transform must be a compile-time constant argument.
// This FFT engine processes 4 or 8 points for each invocation.
//
// The entry point of the engine is the 'FFTStep' function. This function
// passes 4 or 8 data points through a fixed sequence of processing blocks
// (butterfly, rotation, swap, reorder, multiplications, etc.) and produces
// 4 or 8 output points towards the overall FFT transform.
//
// The engine is designed to be invoked from a loop in a single work-item task.
// When compiling a single work-item task, the compiler leverages pipeline
// parallelism and overlaps the execution of multiple invocations of this
// function. A new instance can start processing every clock cycle
// FFT butterfly building block
template <size_t points, typename T>
std::array<ac_complex<T>, points> Butterfly(
std::array<ac_complex<T>, points> data) {
std::array<ac_complex<T>, points> res;
#pragma unroll
for (int k = 0; k < points; k++) {
if (k % 2 == 0) {
res[k] = data[k] + data[k + 1];
} else {
res[k] = data[k - 1] - data[k];
}
}
return res;
}
// Swap real and imaginary components in preparation for inverse transform
template <size_t points, typename T>
std::array<ac_complex<T>, points> SwapComplex(
std::array<ac_complex<T>, points> data) {
std::array<ac_complex<T>, points> res;
#pragma unroll
for (int k = 0; k < points; k++) {
res[k].r() = data[k].i();
res[k].i() = data[k].r();
}
return res;
}
// FFT trivial rotation building block
template <size_t points, typename T>
std::array<ac_complex<T>, points> TrivialRotate(
std::array<ac_complex<T>, points> data) {
#pragma unroll
for (int k = 0; k < (points / 4); k++) {
ac_complex<T> tmp = data[k * 4 + 3];
data[k * 4 + 3].r() = tmp.i();
data[k * 4 + 3].i() = -tmp.r();
}
return data;
}
// FFT data swap building block associated with trivial rotations
template <size_t points, typename T>
std::array<ac_complex<T>, points> TrivialSwap(
std::array<ac_complex<T>, points> data) {
#pragma unroll
for (int k = 0; k < (points / 4); k++) {
ac_complex<T> tmp = data[k * 4 + 1];
data[k * 4 + 1] = data[k * 4 + 2];
data[k * 4 + 2] = tmp;
}
return data;
}
// FFT data swap building block associated with complex rotations
template <size_t points, typename T>
std::array<ac_complex<T>, points> Swap(std::array<ac_complex<T>, points> data) {
std::array<ac_complex<T>, points> tmp;
#pragma unroll
for (int k = 0; k < (points / 2); k++) {
tmp[k + k] = data[k];
tmp[points - 1 - k - k] = data[points - 1 - k];
}
return tmp;
}
// This function "delays" the input by 'depth' steps
// Input 'data' from invocation N would be returned in invocation N + depth
// The 'shift_reg' sliding window is shifted by 1 element at every invocation
template <typename T>
ac_complex<T> Delay(ac_complex<T> data, int depth, ac_complex<T> *shift_reg) {
shift_reg[depth] = data;
return shift_reg[0];
}
// FFT data reordering building block. Implements the reordering depicted below
// (for depth = 2). The first valid outputs are in invocation 4
// Invocation count: 0123... 01234567...
// data[0] : GECA... ----> DBCA...
// data[1] : HFDB... ----> HFGE...
template <size_t points, typename T>
std::array<ac_complex<T>, points> ReorderData(
std::array<ac_complex<T>, points> data, int depth, ac_complex<T> *shift_reg,
bool toggle) {
// Use disconnected segments of length 'depth + 1' elements starting at
// 'shift_reg' to implement the delay elements. At the end of each FFT step,
// the contents of the entire buffer is shifted by 1 element
#pragma unroll
for (int k = 0; k < points; k++) {
data[k * 2 + 1] = Delay(data[k * 2 + 1], depth,
shift_reg + (k * 2 + 1 - 1) / 2 * (depth + 1));
}
if (toggle) {
#pragma unroll
for (int k = 0; k < points; k += 2) {
ac_complex<T> tmp = data[k];
data[k] = data[k + 1];
data[k + 1] = tmp;
}
}
#pragma unroll
for (int k = 0; k < points; k += 2) {
data[k] = Delay(data[k], depth, shift_reg + (points + k) / 2 * (depth + 1));
}
return data;
}
// Produces the twiddle factor associated with a processing stream 'stream',
// at a specified 'stage' during a step 'index' of the computation
//
// If there are precomputed twiddle factors for the given FFT size, uses them
// This saves hardware resources, because it avoids evaluating 'cos' and 'sin'
// functions
template <int size, size_t points, typename T>
ac_complex<T> Twiddle(int index, int stage, int stream) {
ac_complex<T> twid;
constexpr int kTwiddleStages = 5;
// Coalesces the twiddle tables for indexed access
// Macros defined in twiddle_factors.hpp
constexpr T twiddles_cos_8_points[kTwiddleStages][6][512] = COS8;
constexpr T twiddles_sin_8_points[kTwiddleStages][6][512] = SIN8;
constexpr T twiddles_cos_4_points[kTwiddleStages][3][1024] = COS4;
constexpr T twiddles_sin_4_points[kTwiddleStages][3][1024] = SIN4;
// Use the precomputed twiddle factors, if available - otherwise, compute them
int twid_stage = stage >> 1;
if constexpr (size <= (1 << (kTwiddleStages * 2 + 2))) {
if constexpr (points == 8) {
twid.r() =
twiddles_cos_8_points[twid_stage][stream]
[index *
((1 << (kTwiddleStages * 2 + 2)) / size)];
twid.i() =
twiddles_sin_8_points[twid_stage][stream]
[index *
((1 << (kTwiddleStages * 2 + 2)) / size)];
} else {
twid.r() =
twiddles_cos_4_points[twid_stage][stream]
[index *
((1 << (kTwiddleStages * 2 + 2)) / size)];
twid.i() =
twiddles_sin_4_points[twid_stage][stream]
[index *
((1 << (kTwiddleStages * 2 + 2)) / size)];
}
} else {
// This would generate hardware consuming a large number of resources
// Instantiated only if precomputed twiddle factors are unavailable
constexpr double kTwoPi = 2.0f * M_PI;
int multiplier;
// The latter 3 streams will generate the second half of the elements
// In that case phase = 1
int phase = 0;
if (stream >= 3) {
stream -= 3;
phase = 1;
}
switch (stream) {
case 0:
multiplier = 2;
break;
case 1:
multiplier = 1;
break;
case 2:
multiplier = 3;
break;
default:
multiplier = 0;
}
int pos =
(1 << (stage - 1)) * multiplier *
((index + (size / 8) * phase) & (size / 4 / (1 << (stage - 1)) - 1));
double theta = -1.0f * kTwoPi / size * (pos & (size - 1));
twid.r() = cos(theta);
twid.i() = sin(theta);
}
return twid;
}
// FFT complex rotation building block
template <int size, size_t points, typename T>
std::array<ac_complex<T>, points> ComplexRotate(
std::array<ac_complex<T>, points> data, int index, int stage) {
#pragma unroll
for (int group = 0; group < points / 4; group++) {
#pragma unroll
for (int k = 1; k < 4; k++) {
int stream = group * 3 + k - 1;
data[k + group * 4] *= Twiddle<size, points, T>(index, stage, stream);
}
}
return data;
}
// Process "points" input points towards and a FFT/iFFT of size N, N >= points
// (in order input, bit reversed output). Apply all input points in N / points
// consecutive invocations. Obtain all outputs in N /8 consecutive invocations
// starting with invocation N /points - 1 (outputs are delayed). Multiple
// back-to-back transforms can be executed
//
// 'data' encapsulates points complex single-precision floating-point input
// points 'step' specifies the index of the current invocation
// 'fft_delay_elements' is an array representing a sliding window of size
// N+points*(log(N)-2) 'inverse' toggles between the direct and inverse
// transform
template <int logn, size_t points, typename T>
std::array<ac_complex<T>, points> FFTStep(
std::array<ac_complex<T>, points> data, int step,
ac_complex<T> *fft_delay_elements, bool inverse) {
constexpr int size = 1 << logn;
// Swap real and imaginary components if doing an inverse transform
if (inverse) {
data = SwapComplex(data);
}
// Stage 0 of feed-forward FFT
data = Butterfly(data);
data = TrivialRotate(data);
data = TrivialSwap(data);
int stage;
constexpr int kInitStages = points == 8 ? 2 : 1;
if constexpr (points == 8) {
// Stage 1
data = Butterfly(data);
data = ComplexRotate<size>(data, step & (size / points - 1), 1);
data = Swap(data);
stage = 2;
} else {
stage = 1;
}
// Next stages alternate two computation patterns - represented as
// a loop to avoid code duplication. Instruct the compiler to fully unroll
// the loop to increase the amount of pipeline parallelism and allow feed
// forward execution
#pragma unroll
for (; stage < logn - 1; stage++) {
bool complex_stage = stage & 1; // stages 3, 5, ...
// Figure out the index of the element processed at this stage
// Subtract (add modulo size / 8) the delay incurred as data travels
// from one stage to the next
int data_index = (step + (1 << (logn - 1 - stage))) & (size / points - 1);
data = Butterfly(data);
if (complex_stage) {
data = ComplexRotate<size>(data, data_index, stage);
}
data = Swap(data);
// Compute the delay of this stage
int delay = 1 << (logn - 2 - stage);
// Reordering multiplexers must toggle every 'delay' steps
bool toggle = data_index & delay;
// Assign unique sections of the buffer for the set of delay elements at
// each stage
ac_complex<T> *head_buffer = fft_delay_elements + size -
(1 << (logn - stage + kInitStages)) +
points * (stage - kInitStages);
data = ReorderData(data, delay, head_buffer, toggle);
if (!complex_stage) {
data = TrivialRotate(data);
}
}
// Stage logn - 1
data = Butterfly(data);
// Shift the contents of the sliding window. The hardware is capable of
// shifting the entire contents in parallel if the loop is unrolled. More
// important, when unrolling this loop each transfer maps to a trivial
// loop-carried dependency
#pragma unroll
for (int ii = 0; ii < size + points * (logn - 2) - 1; ii++) {
fft_delay_elements[ii] = fft_delay_elements[ii + 1];
}
if (inverse) {
data = SwapComplex(data);
}
return data;
}
// This utility function bit-reverses an integer 'x' of width 'bits'.
template <int bits>
int BitReversed(int x) {
int y = 0;
#pragma unroll
for (int i = 0; i < bits; i++) {
y <<= 1;
y |= x & 1;
x >>= 1;
}
return y;
}
/* Accesses to DDR memory are efficient if the memory locations are accessed
* in order. There is significant overhead when accesses are not in order.
* The penalty is higher if the accesses stride a large number of locations.
*
* This function provides the mapping for an alternative memory layout. This
* layout preserves some amount of linearity when accessing elements from the
* same matrix row, while bringing closer locations from the same matrix
* column. The matrix offsets are represented using 2 * log(N) bits. This
* function swaps bits log(N) - 1 ... log(N) / 2 with bits
* log(N) + log(N) / 2 - 1 ... log(N).
*
* The end result is that 2^(N/2) locations from the same row would still be
* consecutive in memory, while the distance between locations from the same
* column would be only 2^(N/2)
*/
template <int logn>
int MangleBits(int x) {
constexpr int kNB = logn / 2;
int a95 = x & (((1 << kNB) - 1) << kNB);
int a1410 = x & (((1 << kNB) - 1) << (2 * kNB));
constexpr int mask = ((1 << (2 * kNB)) - 1) << kNB;
a95 = a95 << kNB;
a1410 = a1410 >> kNB;
return (x & ~mask) | a95 | a1410;
}
/* This kernel reads the matrix data and provides "1<<log_points" data to the
* FFT engine.
*/
template <int logn, size_t log_points, typename PipeOut, typename T>
struct Fetch {
ac_complex<T> *src;
int mangle;
Fetch(ac_complex<T> *src_, int mangle_) : src(src_), mangle(mangle_) {}
[[intel::kernel_args_restrict]] // NO-FORMAT: Attribute
void operator()() const {
constexpr int kN = (1 << logn);
constexpr int kPoints = (1 << log_points);
constexpr int kWorkGroupSize = kN;
constexpr int kIterations = kN * kN / kPoints / kWorkGroupSize;
for (int i = 0; i < kIterations; i++) {
// Local memory for storing 8 rows
ac_complex<T> buf[kPoints * kN];
for (int work_item = 0; work_item < kWorkGroupSize; work_item++) {
// Each read fetches 8 matrix points
int x = (i * kN + work_item) << log_points;
/* When using the alternative memory layout, each row consists of a set
* of segments placed far apart in memory. Instead of reading all
* segments from one row in order, read one segment from each row before
* switching to the next segment. This requires swapping bits log(N) + 2
* ... log(N) with bits log(N) / 2 + 2 ... log(N) / 2 in the offset.
*/
int where, where_global;
if (mangle) {
constexpr int kNB = logn / 2;
int a1210 = x & ((kPoints - 1) << (2 * kNB));
int a75 = x & ((kPoints - 1) << kNB);
int mask = ((kPoints - 1) << kNB) | ((kPoints - 1) << (2 * kNB));
a1210 >>= kNB;
a75 <<= kNB;
where = (x & ~mask) | a1210 | a75;
where_global = MangleBits<logn>(where);
} else {
where = x;
where_global = where;
}
#pragma unroll
for (int k = 0; k < kPoints; k++) {
buf[(where & ((1 << (logn + log_points)) - 1)) + k] =
src[where_global + k];
}
}
for (int work_item = 0; work_item < kWorkGroupSize; work_item++) {
int row = work_item >> (logn - log_points);
int col = work_item & (kN / kPoints - 1);
// Stream fetched data over 8 channels to the FFT engine
std::array<ac_complex<T>, kPoints> to_pipe;
#pragma unroll
for (int k = 0; k < kPoints; k++) {
to_pipe[k] =
buf[row * kN + BitReversed<log_points>(k) * kN / kPoints + col];
}
PipeOut::write(to_pipe);
}
}
}
};
/* The FFT engine
* 'inverse' toggles between the direct and the inverse transform
*/
template <int logn, size_t log_points, typename PipeIn, typename PipeOut,
typename T>
struct FFT {
int inverse;
FFT(int inverse_) : inverse(inverse_) {}
void operator()() const {
constexpr int kN = (1 << logn);
constexpr int kPoints = (1 << log_points);
/* The FFT engine requires a sliding window for data reordering; data stored
* in this array is carried across loop iterations and shifted by 1 element
* every iteration; all loop dependencies derived from the uses of this
* array are simple transfers between adjacent array elements
*/
ac_complex<T> fft_delay_elements[kN + kPoints * (logn - 2)];
// needs to run "kN / kPoints - 1" additional iterations to drain the last
// outputs
for (unsigned i = 0; i < kN * (kN / kPoints) + kN / kPoints - 1; i++) {
std::array<ac_complex<T>, kPoints> data;
// Read data from channels
if (i < kN * (kN / kPoints)) {
data = PipeIn::read();
} else {
data = std::array<ac_complex<T>, kPoints>{0};
}
// Perform one FFT step
data =
FFTStep<logn>(data, i % (kN / kPoints), fft_delay_elements, inverse);
// Write result to channels
if (i >= kN / kPoints - 1) {
PipeOut::write(data);
}
}
}
};
/* This kernel receives the FFT results, buffers "1<<log_points" rows and then
* writes the results transposed in memory. Because "1<<log_points" rows are
* buffered, "1<<log_points" consecutive columns can be written at a time on
* each transposed row. This provides some degree of locality. In addition, when
* using the alternative matrix format, consecutive rows are closer in memory,
* and this is also beneficial for higher memory access efficiency
*/
template <int logn, size_t log_points, typename PipeIn, typename T>
struct Transpose {
#if defined IS_BSP
ac_complex<T> *dest;
#else
// Specify the memory interface when in the IP Authoring flow
// The buffer location is set to 1 (identical as the malloc performed in
// fft2d_demo.cpp)
// The data width is equal to width of the DDR burst performed by the function
sycl::ext::oneapi::experimental::annotated_arg<
ac_complex<T> *, decltype(sycl::ext::oneapi::experimental::properties{
sycl::ext::intel::experimental::buffer_location<1>,
sycl::ext::intel::experimental::dwidth<
sizeof(ac_complex<T>) * 8 * (1 << log_points)>,
sycl::ext::intel::experimental::latency<0>})>
dest;
#endif
int mangle;
Transpose(ac_complex<T> *dest_, int mangle_) : dest(dest_), mangle(mangle_) {}
[[intel::kernel_args_restrict]] // NO-FORMAT: Attribute
void operator()() const {
constexpr int kN = (1 << logn);
constexpr int kWorkGroupSize = kN;
constexpr int kPoints = (1 << log_points);
constexpr int kIterations = kN * kN / kPoints / kWorkGroupSize;
for (int t = 0; t < kIterations; t++) {
ac_complex<T> buf[kPoints * kN];
for (int work_item = 0; work_item < kWorkGroupSize; work_item++) {
std::array<ac_complex<T>, kPoints> from_pipe = PipeIn::read();
#pragma unroll
for (int k = 0; k < kPoints; k++) {
buf[kPoints * work_item + k] = from_pipe[k];
}
}
for (int work_item = 0; work_item < kWorkGroupSize; work_item++) {
int colt = work_item;
int revcolt = BitReversed<logn>(colt);
int i = (t * kN + work_item) >> logn;
int where = colt * kN + i * kPoints;
if (mangle) where = MangleBits<logn>(where);
#pragma unroll
for (int k = 0; k < kPoints; k++) {
dest[where + k] = buf[k * kN + revcolt];
}
}
}
}
};
#endif /* __FFT2D_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/src/simple_dma.cpp | // Copyright (c) 2022 Intel Corporation
// SPDX-License-Identifier: MIT
#include <stdlib.h>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
// define buffer locations so the IP can have two unique Avalon memory-mapped
// host interfaces
static constexpr int kBL1 = 1;
static constexpr int kBL2 = 2;
// define alignment of Avalon memory-mapped host interfaces to be 4 bytes per
// read
static constexpr int kAlignment = 4;
struct SimpleDMA {
using params1 = decltype(sycl::ext::oneapi::experimental::properties(
// give this a unique Avalon memory-mapped host interface
sycl::ext::intel::experimental::buffer_location<kBL1>,
sycl::ext::intel::experimental::dwidth<32>,
sycl::ext::intel::experimental::awidth<32>,
sycl::ext::intel::experimental::maxburst<15>,
sycl::ext::oneapi::experimental::alignment<kAlignment>,
// latency (choose 0-latency so that waitrequest will work)
sycl::ext::intel::experimental::latency<0>,
sycl::ext::intel::experimental::read_write_mode_read));
using params2 = decltype(sycl::ext::oneapi::experimental::properties(
// give this a unique Avalon memory-mapped host interface
sycl::ext::intel::experimental::buffer_location<kBL2>,
sycl::ext::intel::experimental::dwidth<32>,
sycl::ext::intel::experimental::awidth<32>,
sycl::ext::intel::experimental::maxburst<15>,
sycl::ext::oneapi::experimental::alignment<kAlignment>,
// latency (choose 0-latency so that waitrequest will work)
sycl::ext::intel::experimental::latency<0>,
sycl::ext::intel::experimental::read_write_mode_write));
// Struct members will be interpreted as kernel arguments. The pointers are
// declared first since they are 64-bit types and won't get split up
sycl::ext::oneapi::experimental::annotated_arg<unsigned int *, params1>
source;
sycl::ext::oneapi::experimental::annotated_arg<unsigned int *, params2> dest;
// measured in bytes, must be a multiple of 4. This is only 32 bits wide so if
// it was declared first it would result in the pointers getting split across
// multiple CSR lines.
unsigned int length_bytes;
// This accelerator will be controlled via its Avalon-MM agent interface, so
// no kernel properties are set.
// Implementation of the DMA kernel.
void operator()() const {
// This loop does not handle partial accesses (less than 4 bytes) at the
// start and end of the source/destination so ensure they are at least
// 4-byte aligned
for (unsigned int i = 0; i < (length_bytes / 4); i++) {
dest[i] = source[i];
}
}
};
constexpr int kLen = 128; // bytes
int main() {
// Use compile-time macros to select either:
// - the FPGA emulator device (CPU emulation of the FPGA)
// - the FPGA device (a real FPGA)
// - the simulator device
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// create the device queue
sycl::queue q(selector, fpga_tools::exception_handler);
// make sure the device supports USM host allocations
auto device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>().c_str() << std::endl;
unsigned int *src = sycl::aligned_alloc_shared<unsigned int>(
kAlignment, kLen, q,
sycl::ext::intel::experimental::property::usm::buffer_location(kBL1));
unsigned int *dest = sycl::aligned_alloc_shared<unsigned int>(
kAlignment, kLen, q,
sycl::ext::intel::experimental::property::usm::buffer_location(kBL2));
unsigned int len = kLen;
// ensure that shared pointers are successfully allocated
if (nullptr == src) {
std::cerr << "failed to allocate pointer src: make sure that awidth is "
"sufficient for the allocation size."
<< std::endl;
return EXIT_FAILURE;
}
if (nullptr == dest) {
std::cerr << "failed to allocate pointer dest: make sure that awidth is "
"sufficient for the allocation size."
<< std::endl;
return EXIT_FAILURE;
}
// pre-load
for (int i = 0; i < len; i++) {
src[i] = len - i;
dest[i] = 0;
}
// line below is what associates the name "SimpleDMA" to the kernel
q.single_task(SimpleDMA{src, dest, len}).wait();
// check results
bool passed = true;
for (int i = 0; i < (len / 4); i++) {
bool ok = (src[i] == dest[i]);
passed &= ok;
if (!passed) {
std::cerr << "ERROR: [" << i << "] expected " << src[i] << " saw "
<< dest[i] << ". " << std::endl;
}
}
std::cout << (passed ? "PASSED" : "FAILED") << std::endl;
sycl::free(src, q);
sycl::free(dest, q);
return EXIT_SUCCESS;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/software/simple_dma_test/src/simple_dma_test.c | // Copyright (c) 2022 Intel Corporation
// SPDX-License-Identifier: MIT
//
// This design leverages a simple DMA oneAPI kernel that has had its RTL
// generated and integrated into the Nios V test system that will be used to
// control the accelerator. The DMA kernel has been configured to read from
// memory in memory location 0 (Buffer Location 0) and write to memory in memory
// location 1 (Buffer Location 1).
//
// The CPU is configured to have a single peripheral space located at
// 0x0010_0000 and it is 1MB in size. So if you want to connect a different
// kernel/IP make sure to place it between data master address
// 0x0010_0000-0x001F_FFFF.
#include <stdio.h>
#include <stdlib.h>
// This comes from the BSP and contains Nios V data cache flushing APIs
#include <sys/alt_cache.h>
// This comes from the BSP that was generated by software_build.h, it includes
// the macros used to access the control/status registers of peripherals
#include "io.h"
// This comes from the BSP that was generated by software_build.h, it contains
// information like address map, IRQ mapping, etc...
#include "system.h"
// including the kernel register map directly from the kernel build directory
#include "../../../kernels/simple_dma/build/simple_dma.report.prj/include/register_map_offsets.hpp"
// In bytes, must be a multiple of 4. Keep it a small number to shorten the
// simulation time and do not exceed the 1MB memory size (remember this code is
// in there too). Once the DMA gets going this buffer will fly by fast so
// setting it too high mostly affects the memory initialization and the
// correctness check at the end once the DMA gets going this buffer will fly by
// fast so setting it too high mostly affects the memory initialization and the
// correctness check at the end.
#define BUFFER_LENGTH 1024
// Error numbers
#define TEST_PASS 0
#define TEST_FAIL 1
/// Calculate DMA kernel register offsets from system.h, and the kernel register
/// offsets from register_map_offsets.hpp
#define REG_ARG_SOURCE_BASE \
(SIMPLE_DMA_ACCELERATOR_BASE + ZTS9SIMPLEDMA_REGISTER_MAP_ARG_ARG_SOURCE_REG)
#define REG_ARG_DEST_BASE \
(SIMPLE_DMA_ACCELERATOR_BASE + ZTS9SIMPLEDMA_REGISTER_MAP_ARG_ARG_DEST_REG)
#define REG_ARG_LENGTH_BASE \
(SIMPLE_DMA_ACCELERATOR_BASE + \
ZTS9SIMPLEDMA_REGISTER_MAP_ARG_ARG_LENGTH_BYTES_REG)
#define REG_START_BASE \
(SIMPLE_DMA_ACCELERATOR_BASE + ZTS9SIMPLEDMA_REGISTER_MAP_START_REG)
#define REG_STATUS \
(SIMPLE_DMA_ACCELERATOR_BASE + ZTS9SIMPLEDMA_REGISTER_MAP_STATUS_REG)
/// @brief configure and start the Simple DMA Accelerator IP
///
/// @details `configure_and_start_dma` will accept the source, destination, and
/// transfer length and write them into the kernel CSRs using the old Nios
/// IORW/IORD_32DIRECT macros, since those also work for Nios II.
///
/// @note Since the kernel is located in the I/O space of the Nios V processor,
/// you may choose to simply dereference a pointer to bypass the data cache but
/// that doesn't port to Nios II directly so that has been avoided here.
///
/// @param[in] source Pointer to source memory to copy from
///
/// @param[in] destination Pointer to which to copy data
///
/// @param[in] length_bytes Number of bytes of data to copy
void configure_and_start_dma(unsigned int* source, unsigned int* destination,
unsigned int length_bytes) {
// Nios V/g is 32-bit, but FPGA IP produced with the Intel® oneAPI DPC++/C++
// Compiler uses 64-bit pointers, so we have to write the source pointer 32
// bits at a time. The source pointer needs to be cast to unsigned int since
// the Nios macros do not expect a pointer.
// According to io.h there is an upper limitation of 12-bits of the offset
// field, so this code instead adds the offset to the base (first argument of
// macro) and hardcodes the offset field to 0 (second argument of macro).
// DMA source
IOWR_32DIRECT(REG_ARG_SOURCE_BASE, 0, (unsigned int)source);
// padding upper 32 bits to all zeros
IOWR_32DIRECT(REG_ARG_SOURCE_BASE + 4, 0, 0);
// DMA destination
IOWR_32DIRECT(REG_ARG_DEST_BASE, 0, (unsigned int)destination);
// padding upper 32 bits to all zeros
IOWR_32DIRECT(REG_ARG_DEST_BASE + 4, 0, 0);
// DMA length
IOWR_32DIRECT(REG_ARG_LENGTH_BASE, 0, BUFFER_LENGTH);
// DMA start
IOWR_32DIRECT(REG_START_BASE, 0, 1);
// The DMA kernel should immediately start at this point
}
/// @brief Exercise the DMA kernel.
///
/// The test has the following phases: \n
///
/// 1. populate a source buffer with an incrementing pattern of 'BUFFER_LENGTH'
/// bytes \n
///
/// 2. clear out the destination buffer \n
///
/// 3. instruct the DMA kernel to perform the source --> destination transfer \n
///
/// 4. check that the destination contents match the source
///
/// @return 0 if the test passes.
int test_simple_dma() {
// allocating source and destination buffers at compile time so that if too
// large a value is set for BUFFER_LENGTH then we'll find out early at compile
// time
unsigned int source[BUFFER_LENGTH / 4];
unsigned int destination[BUFFER_LENGTH / 4];
int i;
// initialize the source buffer with an incrementing pattern and clear out the
// destination before the accelerator clobbers it
for (i = 0; i < (BUFFER_LENGTH / 4); i++) {
source[i] = i;
destination[i] = 0;
}
// main memory (code_data_ram) is *not* in a peripheral region, so all the
// writes to the source and destination need to be flushed from the data cache
// to avoid cache coherency issues when the accelerator attempts to access
// memory.
// make sure all that source data that was set gets flushed out to main memory
alt_dcache_flush(source, BUFFER_LENGTH);
// make sure all that destination data that was zeroed out gets flushed out to
// main memory
alt_dcache_flush(destination, BUFFER_LENGTH);
// Configure and start the DMA kernel
configure_and_start_dma(source, destination, BUFFER_LENGTH);
// Busy-waiting for the accelerator to complete (kernel will fire off
// interrupt as well but there is no register as of 2024.0 to clear it)
while ((IORD_32DIRECT(REG_STATUS, 0) & KERNEL_REGISTER_MAP_DONE_MASK) !=
KERNEL_REGISTER_MAP_DONE_MASK) {
}
// Now that the accelerator is done, test the destination buffer for
// correctness. Since the destination buffer was already flushed from the data
// cache, software can safely read the destination without additional data
// flushes. Since the source was previously flushed as well, it will get
// fetched from main memory and warm up the data cache just like the
// destination buffer in the correctness loop.
// test the results at the destination buffer, if a failure is detected set
// pass to 0 and stop testing
for (i = 0; i < (BUFFER_LENGTH / 4); i++) {
if (source[i] != destination[i]) {
printf(
"Test Fail: Source address = 0x%x, Destination address = 0x%x, byte "
"offset 0x%x. Read value 0x%x instead of expected value 0x%x.\n",
(unsigned int)source, (unsigned int)destination, (i * 4),
destination[i], source[i]);
return TEST_FAIL;
}
}
// If we reach this point then all the data must have passed so we can issue a
// blanket statement that the entire test passed
printf("Test Pass: All the data at the destination matches the source.\n");
return TEST_PASS;
}
/// @brief main function
///
/// @return 0 on a test pass and non-zero on failures, see error numbers near
/// top of this file.
int main() {
int return_val;
printf("Test design for the simple DMA kernel\n\n");
printf(
"Test will initialize %d incrementing four byte unsigned integers, have "
"the accelerator DMA copy the data to a destination and then check the "
"destination for correctness.\n",
(BUFFER_LENGTH / 4));
return_val = test_simple_dma();
printf("Software will now exit.\n");
return return_val;
}
| c |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd.hpp | #ifndef __QRD_HPP__
#define __QRD_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <chrono>
#include <cstring>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
#include "streaming_qrd.hpp"
#include "tuple.hpp"
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class QRDDDRToLocalMem;
class QRD;
class QRDLocalMemToDDRQ;
class QRDLocalMemToDDRR;
class APipe;
class QPipe;
class RPipe;
/*
Implementation of the QR decomposition using multiple streaming kernels
Can be configured by datatype, matrix size and works with square or
rectangular matrices, real and complex.
*/
template <unsigned columns, // Number of columns in the input matrix
unsigned rows, // Number of rows in the input matrix
unsigned raw_latency, // RAW latency for triangular loop optimization
bool is_complex, // Selects between ac_complex<T> and T datatype
typename T, // The datatype for the computation
typename TT = std::conditional_t<is_complex, ac_complex<T>, T>
// TT will be ac_complex<T> or T depending on is_complex
>
void QRDecompositionImpl(
std::vector<TT> &a_matrix, // Input matrix to decompose
std::vector<TT> &q_matrix, // Output matrix Q
std::vector<TT> &r_matrix, // Output matrix R
sycl::queue &q, // Device queue
int matrix_count, // Number of matrices to decompose
int repetitions // Number of repetitions, for performance evaluation
) {
constexpr int kAMatrixSize = columns * rows;
constexpr int kQMatrixSize = columns * rows;
constexpr int kRMatrixSize = columns * (columns + 1) / 2;
constexpr int kNumElementsPerDDRBurst = is_complex ? 4 : 8;
using PipeType = fpga_tools::NTuple<TT, kNumElementsPerDDRBurst>;
// Pipes to communicate the A, Q and R matrices between kernels
using AMatrixPipe = sycl::ext::intel::pipe<APipe, PipeType, 3>;
using QMatrixPipe = sycl::ext::intel::pipe<QPipe, PipeType, 3>;
using RMatrixPipe = sycl::ext::intel::pipe<RPipe, TT,
kNumElementsPerDDRBurst * 4>;
// Allocate FPGA DDR memory.
#if defined (IS_BSP)
TT *a_device = sycl::malloc_device<TT>(kAMatrixSize * matrix_count, q);
TT *q_device = sycl::malloc_device<TT>(kQMatrixSize * matrix_count, q);
TT *r_device = sycl::malloc_device<TT>(kRMatrixSize * matrix_count, q);
#else
// malloc_device are not supported when targetting an FPGA part/family
TT *a_device = sycl::malloc_shared<TT>(kAMatrixSize * matrix_count, q);
TT *q_device = sycl::malloc_shared<TT>(kQMatrixSize * matrix_count, q);
TT *r_device = sycl::malloc_shared<TT>(kRMatrixSize * matrix_count, q);
#endif
q.memcpy(a_device, a_matrix.data(), kAMatrixSize * matrix_count
* sizeof(TT)).wait();
auto ddr_write_event =
q.submit([&](sycl::handler &h) {
h.single_task<QRDDDRToLocalMem>([=]() [[intel::kernel_args_restrict]] {
MatrixReadFromDDRToPipe<TT, rows, columns, kNumElementsPerDDRBurst,
AMatrixPipe>(a_device, matrix_count, repetitions);
});
});
// Read the A matrix from the AMatrixPipe pipe and compute the QR
// decomposition. Write the Q and R output matrices to the QMatrixPipe
// and RMatrixPipe pipes.
q.single_task<QRD>(
fpga_linalg::StreamingQRD<T, is_complex, rows, columns, raw_latency,
kNumElementsPerDDRBurst,
AMatrixPipe, QMatrixPipe, RMatrixPipe>());
auto q_event = q.single_task<QRDLocalMemToDDRQ>([=
]() [[intel::kernel_args_restrict]] {
// Read the Q matrix from the QMatrixPipe pipe and copy it to the
// FPGA DDR
MatrixReadPipeToDDR<TT, rows, columns, kNumElementsPerDDRBurst,
QMatrixPipe>(q_device, matrix_count, repetitions);
});
auto r_event = q.single_task<QRDLocalMemToDDRR>([=
]() [[intel::kernel_args_restrict]] {
// Read the R matrix from the RMatrixPipe pipe and copy it to the
// FPGA DDR
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> vector_ptr_located(r_device);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* vector_ptr_located(r_device);
#endif
// Repeat matrix_count complete R matrix pipe reads
// for as many repetitions as needed
for (int repetition_index = 0; repetition_index < repetitions;
repetition_index++) {
[[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
for (int r_idx = 0; r_idx < kRMatrixSize; r_idx++) {
vector_ptr_located[matrix_index * kRMatrixSize + r_idx] =
RMatrixPipe::read();
} // end of r_idx
} // end of repetition_index
} // end of li
});
q_event.wait();
r_event.wait();
// Compute the total time the execution lasted
auto start_time = ddr_write_event.template
get_profiling_info<sycl::info::event_profiling::command_start>();
auto end_time = q_event.template
get_profiling_info<sycl::info::event_profiling::command_end>();
double diff = (end_time - start_time) / 1.0e9;
q.throw_asynchronous();
std::cout << " Total duration: " << diff << " s" << std::endl;
std::cout << "Throughput: "
<< repetitions * matrix_count / diff * 1e-3
<< "k matrices/s" << std::endl;
// Copy the Q and R matrices result from the FPGA DDR to the host memory
q.memcpy(q_matrix.data(), q_device, kQMatrixSize * matrix_count
* sizeof(TT)).wait();
q.memcpy(r_matrix.data(), r_device, kRMatrixSize * matrix_count
* sizeof(TT)).wait();
// Clean allocated FPGA memory
free(a_device, q);
free(q_device, q);
free(r_device, q);
}
#endif /* __QRD_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/qrd_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <list>
#include "exception_handler.hpp"
#include "qrd.hpp"
#ifdef FPGA_SIMULATOR
#define ROWS_COMPONENT_V 8
#define COLS_COMPONENT_V 8
#else
#define ROWS_COMPONENT_V ROWS_COMPONENT
#define COLS_COMPONENT_V COLS_COMPONENT
#endif
/*
COMPLEX, COLS_COMPONENT, ROWS_COMPONENT and FIXED_ITERATIONS are defined
by the build system.
Depending on the value of COMPLEX, the real or complex QRDecomposition is
defined
Function arguments:
- a_matrix: The input matrix. Interpreted as a transposed matrix.
- q_matrix: The Q matrix. The function will overwrite this matrix.
- r_matrix The R matrix. The function will overwrite this matrix.
The vector will only contain the upper triangular elements
of the matrix, in a row by row fashion.
- q: The device queue.
- matrix_count: Number of matrices to decompose.
- repetitions: The number of repetitions of the computation to execute.
(for performance evaluation)
*/
#if COMPLEX == 0
// Real single precision floating-point QR Decomposition
void QRDecomposition(std::vector<float> &a_matrix, std::vector<float> &q_matrix,
std::vector<float> &r_matrix, sycl::queue &q,
int matrix_count,
int repetitions) {
constexpr bool is_complex = false;
QRDecompositionImpl<COLS_COMPONENT_V, ROWS_COMPONENT_V, FIXED_ITERATIONS,
is_complex, float>(a_matrix, q_matrix, r_matrix, q,
matrix_count, repetitions);
}
#else
// Complex single precision floating-point QR Decomposition
void QRDecomposition(std::vector<ac_complex<float> > &a_matrix,
std::vector<ac_complex<float> > &q_matrix,
std::vector<ac_complex<float> > &r_matrix, sycl::queue &q,
int matrix_count,
int repetitions) {
constexpr bool is_complex = true;
QRDecompositionImpl<COLS_COMPONENT_V, ROWS_COMPONENT_V, FIXED_ITERATIONS,
is_complex, float>(a_matrix, q_matrix, r_matrix, q,
matrix_count, repetitions);
}
#endif
/*
returns if both the real and complex parts of the given ac_complex
value are finite
*/
bool IsFinite(ac_complex<float> val) {
return std::isfinite(val.r()) && std::isfinite(val.i());
}
/*
returns if the given value is finite
*/
bool IsFinite(float val) { return std::isfinite(val); }
int main(int argc, char *argv[]) {
constexpr size_t kRandomSeed = 1138;
constexpr size_t kRandomMin = 1;
constexpr size_t kRandomMax = 10;
constexpr size_t kRows = ROWS_COMPONENT_V;
constexpr size_t kColumns = COLS_COMPONENT_V;
constexpr size_t kAMatrixSize = kRows * kColumns;
constexpr size_t kQMatrixSize = kRows * kColumns;
constexpr size_t kRMatrixSize = kColumns * (kColumns + 1) / 2;
constexpr size_t kQRMatrixSize = kQMatrixSize + kRMatrixSize;
constexpr bool kComplex = COMPLEX != 0;
#if defined(FPGA_SIMULATOR)
std::cout << "Using 32x32 matrices for simulation to reduce runtime" << std::endl;
#endif
// Get the number of times we want to repeat the decomposition
// from the command line.
#if defined(FPGA_EMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 16;
#elif defined(FPGA_SIMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 1;
#else
int repetitions = argc > 1 ? atoi(argv[1]) : 819200;
#endif
if (repetitions < 1) {
std::cout << "Number of repetitions given is lower that 1." << std::endl;
std::cout << "The decomposition must occur at least 1 time." << std::endl;
std::cout << "Increase the number of repetitions (e.g. 16)." << std::endl;
return 1;
}
#if defined(FPGA_SIMULATOR)
constexpr size_t kMatricesToDecompose = 1;
#else
constexpr size_t kMatricesToDecompose = 8;
#endif
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::property_list
queue_properties{sycl::property::queue::enable_profiling()};
sycl::queue q = sycl::queue(selector,
fpga_tools::exception_handler,
queue_properties);
sycl::device device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>().c_str()
<< std::endl;
// Select a type for this compile depending on the value of COMPLEX
using T = std::conditional_t<kComplex, ac_complex<float>, float>;
// Create vectors to hold all the input and output matrices
std::vector<T> a_matrix;
std::vector<T> q_matrix;
std::vector<T> r_matrix;
a_matrix.resize(kAMatrixSize * kMatricesToDecompose);
q_matrix.resize(kQMatrixSize * kMatricesToDecompose);
r_matrix.resize(kRMatrixSize * kMatricesToDecompose);
std::cout << "Generating " << kMatricesToDecompose << " random ";
if constexpr (kComplex) {
std::cout << "complex ";
} else {
std::cout << "real ";
}
std::cout << "matri" << (kMatricesToDecompose > 1 ? "ces" : "x")
<< " of size "
<< kRows << "x" << kColumns << " " << std::endl;
// Generate the random input matrices
srand(kRandomSeed);
for(int matrix_index = 0; matrix_index < kMatricesToDecompose;
matrix_index++){
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
float random_real = rand() % (kRandomMax - kRandomMin) + kRandomMin;
#if COMPLEX == 0
a_matrix[matrix_index * kAMatrixSize
+ col * kRows + row] = random_real;
#else
float random_imag = rand() % (kRandomMax - kRandomMin) + kRandomMin;
ac_complex<float> random_complex{random_real, random_imag};
a_matrix[matrix_index * kAMatrixSize
+ col * kRows + row] = random_complex;
#endif
} // end of col
} // end of row
#ifdef DEBUG
std::cout << "A MATRIX " << matrix_index << std::endl;
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
std::cout << a_matrix[matrix_index * kAMatrixSize
+ col * kRows + row] << " ";
} // end of col
std::cout << std::endl;
} // end of row
#endif
} // end of matrix_index
std::cout << "Running QR decomposition of " << kMatricesToDecompose
<< " matri" << (kMatricesToDecompose > 1 ? "ces " : "x ")
<< repetitions << " times" << std::endl;
QRDecomposition(a_matrix, q_matrix, r_matrix, q, kMatricesToDecompose,
repetitions);
// For output post-processing (op)
T q_matrix_op[kRows][kColumns];
T r_matrix_op[kRows][kColumns];
// For rectangular matrices, Q is only going to have orthogonal columns
// so we won't check if the rows are orthogonal
bool square_matrices = kRows == kColumns;
// Floating-point error threshold value at which we decide that the design
// computed an incorrect value
constexpr float kErrorThreshold = 1e-4;
// The orthogonality check is more sensible to numerical error, the
// threshold is then set a bit higher
float q_ortho_error_threshold = pow(2.0, -9);
// Check Q and R matrices
std::cout << "Verifying results...";
for(int matrix_index = 0; matrix_index < kMatricesToDecompose;
matrix_index++){
// keep track of Q and R element indexes
size_t r_idx = 0;
size_t q_idx = 0;
// Read the R matrix from the output vector to the RMatrixOP matrix
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
if (j < i)
r_matrix_op[i][j] = 0;
else {
r_matrix_op[i][j] = r_matrix[matrix_index*kRMatrixSize
+ r_idx];
r_idx++;
}
}
}
// Read the Q matrix from the output vector to the QMatrixOP matrix
for (size_t j = 0; j < kColumns; j++) {
for (size_t i = 0; i < kRows; i++) {
q_matrix_op[i][j] = q_matrix[matrix_index*kQMatrixSize
+ q_idx];
q_idx++;
}
}
#ifdef DEBUG
std::cout << "R MATRIX" << std::endl;
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
std::cout << r_matrix_op[i][j] << " ";
}
std::cout << std::endl;
}
std::cout << "Q MATRIX" << std::endl;
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
std::cout << q_matrix_op[i][j] << " ";
}
std::cout << std::endl;
}
#endif
// Count the number of errors found for this matrix
size_t error_count = 0;
bool error = false;
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
// Compute Q * R at index i,j
T q_r_ij{0};
for (size_t k = 0; k < kColumns; k++) {
q_r_ij += q_matrix_op[i][k] * r_matrix_op[k][j];
}
// Compute transpose(Q) * Q at index i,j
T qt_q_ij{0};
if (i < kColumns) {
for (size_t k = 0; k < kRows; k++) {
#if COMPLEX == 0
qt_q_ij += q_matrix_op[k][i] * q_matrix_op[k][j];
#else
qt_q_ij += q_matrix_op[k][i] * q_matrix_op[k][j].conj();
#endif
}
}
// Compute Q * transpose(Q) at index i,j
T q_qt_ij{0};
if (square_matrices) {
if (i < kColumns) {
for (size_t k = 0; k < kRows; k++) {
#if COMPLEX == 0
q_qt_ij += q_matrix_op[i][k] * q_matrix_op[j][k];
#else
q_qt_ij += q_matrix_op[i][k] * q_matrix_op[j][k].conj();
#endif
}
}
}
// Verify that all the results are OK:
// Q * R = A at index i,j
bool q_r_eq_a;
// transpose(Q) * Q = Id at index i,j
bool qt_q_eq_id;
// Q * transpose(Q) = Id at index i,j
bool q_qt_eq_id;
// R is upped triangular
bool r_is_upper_triang;
// R is finite at index i,j
bool r_is_finite;
#if COMPLEX == 0
q_r_eq_a = abs(a_matrix[matrix_index * kAMatrixSize
+ j * kRows + i]
- q_r_ij) < kErrorThreshold;
qt_q_eq_id =
((i == j) && (abs(qt_q_ij - 1) < q_ortho_error_threshold)) ||
((i != j) && (abs(qt_q_ij) < q_ortho_error_threshold));
q_qt_eq_id = !square_matrices ||
(((i == j) && (abs(q_qt_ij - 1) < q_ortho_error_threshold)) ||
((i != j) && (abs(q_qt_ij) < q_ortho_error_threshold)));
r_is_upper_triang =
(i >= kColumns) ||
((i > j) && ((abs(r_matrix_op[i][j]) < kErrorThreshold))) ||
((i <= j));
#else
q_r_eq_a = (abs(a_matrix[matrix_index * kAMatrixSize
+ j * kRows + i].r() -
q_r_ij.r()) < kErrorThreshold) &&
(abs(a_matrix[matrix_index * kAMatrixSize
+ j * kRows + i].i() -
q_r_ij.i()) < kErrorThreshold);
qt_q_eq_id =
(((i == j) && (abs(qt_q_ij.r() - 1) < q_ortho_error_threshold)) ||
(((i != j) || (j >= kRows)) && (abs(qt_q_ij.r()) < q_ortho_error_threshold))) &&
(abs(qt_q_ij.i()) < q_ortho_error_threshold);
q_qt_eq_id =
!square_matrices ||
((((i == j) && (abs(q_qt_ij.r() - 1) < q_ortho_error_threshold)) ||
(((i != j) || (j >= kRows)) &&
(abs(q_qt_ij.r()) < q_ortho_error_threshold))) &&
(abs(q_qt_ij.i()) < q_ortho_error_threshold));
r_is_upper_triang =
(i >= kColumns) ||
((i > j) && ((abs(r_matrix_op[i][j].r()) < kErrorThreshold) &&
(abs(r_matrix_op[i][j].i()) < kErrorThreshold))) ||
(i <= j);
#endif
r_is_finite =
((i < kColumns) && IsFinite(r_matrix_op[i][j])) || (i >= kColumns);
// If any of the checks failed
if (!q_r_eq_a || !qt_q_eq_id || !q_qt_eq_id || !r_is_upper_triang ||
!IsFinite(q_r_ij) || !IsFinite(qt_q_ij) || !IsFinite(q_qt_ij) ||
!r_is_finite) {
// Increase the error count for this matrix
error_count++;
// Continue counting the errors even if we now we are going to
// produce an error
if (error) {
continue;
}
if (!q_r_eq_a) {
std::cout << "Error: A[" << i << "][" << j << "] = "
<< a_matrix[matrix_index * kAMatrixSize
+ j * kRows + i]
<< " but QR[" << i << "][" << j << "] = " << q_r_ij
<< std::endl;
}
if (!q_r_eq_a) {
std::cout << "The difference is greater than tolerated ("
<< kErrorThreshold << ")" << std::endl;
}
if (!qt_q_eq_id || !q_qt_eq_id) {
std::cout << "Q is not orthogonal at i " << i << " j " << j << ":"
<< std::endl
<< " transpose(Q) * Q = " << qt_q_ij << std::endl
<< " Q * transpose(Q) =" << q_qt_ij << std::endl;
std::cout << "q_ortho_error_threshold = "
<< q_ortho_error_threshold
<< std::endl;
}
if (!r_is_upper_triang) {
std::cout << "R is not upper triangular at i " << i << " j " << j
<< ":" << std::endl
<< " R = " << r_matrix_op[i][j] << std::endl;
}
if (!IsFinite(q_r_ij)) {
std::cout << "QR[" << i << "][" << j << "] = " << q_r_ij
<< " is not finite" << std::endl;
}
if (!IsFinite(qt_q_ij)) {
std::cout << "transpose(Q) * Q at i " << i << " j " << j << " = "
<< qt_q_ij << " is not finite" << std::endl;
}
if (!IsFinite(q_qt_ij)) {
std::cout << "Q * transpose(Q) at i " << i << " j " << j << " = "
<< q_qt_ij << " is not finite" << std::endl;
}
if (!r_is_finite) {
std::cout << "R[" << i << "][" << j << "] = " << r_matrix_op[i][j]
<< " is not finite" << std::endl;
}
error = true;
}
} // end of j
} // end of i
if (error_count > 0) {
std::cout << std::endl << "FAILED" << std::endl;
std::cout << std::endl
<< "!!!!!!!!!!!!!! " << error_count << " errors" << std::endl;
return 1;
}
} // end of matrix_index
std::cout << std::endl << "PASSED" << std::endl;
return 0;
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::cerr << " If you are targeting an FPGA hardware, "
"ensure that your system is plugged to an FPGA board that is "
"set up correctly"
<< std::endl;
std::cerr << " If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR"
<< std::endl;
std::terminate();
} catch (std::bad_alloc const &e) {
std::cerr << "Caught a memory allocation exception on the host: "
<< e.what() << std::endl;
std::cerr << " You can reduce the memory requirement by reducing the "
"number of matrices generated. Specify a smaller number when "
"running the executable."
<< std::endl;
std::cerr << " In this run, more than "
<< ((kAMatrixSize + kQRMatrixSize) * 2 * kMatricesToDecompose
* sizeof(float)) / pow(2, 30)
<< " GBs of memory was requested for the decomposition of a "
<< "matrix of size " << kRows << " x " << kColumns
<< std::endl;
std::terminate();
}
} // end of main
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "tuple.hpp"
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_elem_per_bank elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Output matrix pipe
>
void MatrixReadFromDDRToPipe(
TT* matrix_ptr, // Input matrix pointer
int matrix_count,// Number of matrix to read from DDR
int repetitions // Number of time to write the same matrix to the pipe
) {
// We may perform an incomplete memory read if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = rows%num_elem_per_bank != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst reads of num_elem_per_bank elements required to read a
// full column
constexpr int kLoopIterPerColumn = rows / num_elem_per_bank + kExtraIteration;
// Number of DDR burst reads of num_elem_per_bank to read all the matrices
constexpr int kLoopIter = kLoopIterPerColumn * columns;
// Size in bits of the loop iterator over kLoopIter iterations
constexpr int kLoopIterBitSize = fpga_tools::BitsForMaxValue<kLoopIter + 1>();
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> matrix_ptr_located(matrix_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* matrix_ptr_located(matrix_ptr);
#endif
// Repeatedly read matrix_count matrices from DDR and sends them to the pipe
for (int repetition = 0; repetition < repetitions; repetition++){
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++){
// Keep track of the current element index in the matrix
// Only useful in the case of kIncompleteBurst
int load_index = 0;
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kLoopIterBitSize, false> li = 0; li < kLoopIter; li++) {
bool last_burst_of_col;
if constexpr (kIncompleteBurst){
// Check if we are reading the last DDR burst of the current column
last_burst_of_col = (li % kLoopIterPerColumn)
== kLoopIterPerColumn - 1;
}
fpga_tools::NTuple<TT, num_elem_per_bank> ddr_read;
// Perform the DDR burst read of num_elem_per_bank elements
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst){
// Check if the current read index is beyond the end of the current
// matrix column
bool out_of_bounds = last_burst_of_col &&
((k % num_elem_per_bank) > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR reads that are relevant (and don't access a
// memory address that may be beyond the matrix last address)
if (!out_of_bounds) {
ddr_read.template get<k>() = matrix_ptr_located
[matrix_index * kMatrixSize + load_index + k];
}
}
else{
ddr_read.template get<k>() = matrix_ptr_located
[matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k];
}
});
if constexpr (kIncompleteBurst){
// Update the current element index in the input matrix according
// to the read size of the current iteration
load_index += last_burst_of_col ? rows % num_elem_per_bank :
num_elem_per_bank;
}
MatrixPipe::write(ddr_read);
} // end of li
} // end of matrix_index
} // end of repetition
}
/*
Write matrix_count matrices of type TT from a pipe, num_elem_per_bank by
num_elem_per_bank and write them to DDR by bursts of num_elem_per_bank
elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Input matrix
>
void MatrixReadPipeToDDR(
TT* matrix_ptr, // Output matrix pointer
int matrix_count,// Number of matrix to write to DDR
int repetitions // Number of time to read the same matrix to the pipe
) {
// We may perform an incomplete memory write if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = rows%num_elem_per_bank != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst of num_elem_per_bank required to write a full column
constexpr int kLoopIterPerColumn = rows / num_elem_per_bank + kExtraIteration;
// Number of DDR burst of num_elem_per_bank to write all the matrices
constexpr int kLoopIter = kLoopIterPerColumn * columns;
// Size in bits of the loop iterator over kLoopIter iterations
constexpr int kLoopIterBitSize = fpga_tools::BitsForMaxValue<kLoopIter + 1>();
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> matrix_ptr_located(matrix_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* matrix_ptr_located(matrix_ptr);
#endif
// Repeatedly read matrix_count matrices from the pipe and write them to DDR
for (int repetition = 0; repetition < repetitions; repetition++){
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++){
// Keep track of the current element index in the output matrix
// Only useful in the case of kIncompleteBurst
int write_idx = 0;
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
[[intel::ivdep]] // NO-FORMAT: Attribute
for (ac_int<kLoopIterBitSize, false> li = 0; li < kLoopIter; li++) {
fpga_tools::NTuple<TT, num_elem_per_bank> pipe_read =
MatrixPipe::read();
bool last_burst_of_col;
if constexpr (kIncompleteBurst){
// Check if we are writing the last DDR burst of the current column
last_burst_of_col =
(li % kLoopIterPerColumn) == kLoopIterPerColumn - 1;
}
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst){
// Check if the current write index is beyond the end of the current
// matrix column
bool out_of_bounds = last_burst_of_col &&
(k > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR writes that are relevant (and don't access a
// memory address that may be beyond the buffer last address)
if (!out_of_bounds) {
matrix_ptr_located[matrix_index * kMatrixSize + write_idx + k] =
pipe_read.template get<k>();
}
}
else{
matrix_ptr_located[matrix_index * kMatrixSize
+ int(li) * num_elem_per_bank + k] = pipe_read.template get<k>();
}
});
if constexpr (kIncompleteBurst){
// Update the current element index in the write buffer according
// to the write size of the current iteration
write_idx += last_burst_of_col ? rows % num_elem_per_bank :
num_elem_per_bank;
}
} // end of li
} // end of matrix_index
} // end of repetition
}
#endif /* __MEMORY_TRANSFERS_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/main.cpp | #include <algorithm>
#include <array>
#include <chrono>
#include <limits>
#include <numeric>
#include <type_traits>
#include <utility>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "merge_sort.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
using namespace sycl;
using namespace std::chrono;
// Determines whether we will use USM host or device allocations to move data
// between host and the device.
// This can be set on the command line by defining the preprocessor macro
// 'USM_HOST_ALLOCATIONS' using the flag: '-DUSM_HOST_ALLOCATIONS'
#if defined(USM_HOST_ALLOCATIONS)
constexpr bool kUseUSMHostAllocation = true;
#else
constexpr bool kUseUSMHostAllocation = false;
#endif
// The number of merge units, which must be a power of 2.
// This can be set by defining the preprocessor macro 'MERGE_UNITS'
// otherwise the default value below is used.
#ifndef MERGE_UNITS
#if defined(FPGA_SIMULATOR)
#define MERGE_UNITS 2
#else
#define MERGE_UNITS 8
#endif
#endif
constexpr size_t kMergeUnits = MERGE_UNITS;
static_assert(kMergeUnits > 0);
static_assert(fpga_tools::IsPow2(kMergeUnits));
// The width of the sort, which must be a power of 2
// This can be set by defining the preprocessor macro 'SORT_WIDTH'
// otherwise the default value below is used.
#ifndef SORT_WIDTH
#define SORT_WIDTH 4
#endif
constexpr size_t kSortWidth = SORT_WIDTH;
static_assert(kSortWidth >= 1);
static_assert(fpga_tools::IsPow2(kSortWidth));
////////////////////////////////////////////////////////////////////////////////
// Forward declare functions used in this file by main()
template <typename ValueT, typename IndexT, typename KernelPtrType>
double FPGASort(queue &q, ValueT *in_vec, ValueT *out_vec, IndexT count);
template <typename T>
bool Validate(T *val, T *ref, unsigned int count);
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[]) {
// the type to sort, needs a compare function!
using ValueT = int;
// the type used to index in the sorter
// below we do a runtime check to make sure this type has enough bits to
// count all the elements to be sorted.
using IndexT = unsigned int;
/////////////////////////////////////////////////////////////
// reading and validating the command line arguments
// defaults
bool passed = true;
#if defined(FPGA_EMULATOR)
IndexT count = 128;
int runs = 2;
#elif defined(FPGA_SIMULATOR)
IndexT count = 16;
int runs = 2;
#else
IndexT count = 1 << 24;
int runs = 17;
#endif
int seed = 777;
// get the size of the input as the first command line argument
if (argc > 1) {
count = atoi(argv[1]);
}
// get the number of runs as the second command line argument
if (argc > 2) {
runs = atoi(argv[2]);
}
// get the random number generator seed as the third command line argument
if (argc > 3) {
seed = atoi(argv[3]);
}
// enforce at least two runs
if (runs < 2) {
std::cerr << "ERROR: 'runs' must be 2 or more\n";
std::terminate();
}
// check args
if (count <= kMergeUnits) {
std::cerr << "ERROR: 'count' must be greater than number of merge units\n";
std::terminate();
} else if (count > std::numeric_limits<IndexT>::max()) {
std::cerr << "ERROR: the index type (IndexT) does not have enough bits to "
<< "count to 'count'\n";
std::terminate();
} else if ((count % kSortWidth) != 0) {
std::cerr << "ERROR: 'count' must be a multiple of the sorter width\n";
std::terminate();
}
/////////////////////////////////////////////////////////////
// the device selector
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// create the device queue
queue q(selector, fpga_tools::exception_handler);
auto device = q.get_device();
// make sure the device supports USM device allocations in BSP mode
#if defined(IS_BSP)
if (!device.has(aspect::usm_device_allocations)) {
std::cerr << "ERROR: The selected device does not support USM device"
<< " allocations\n";
std::terminate();
}
#endif
// make sure the device support USM host allocations if we chose to use them
if (!device.has(aspect::usm_host_allocations) &&
kUseUSMHostAllocation) {
std::cerr << "ERROR: The selected device does not support USM host"
<< " allocations\n";
std::terminate();
}
std::cout << "Running on device: "
<< device.get_info<info::device::name>().c_str()
<< std::endl;
// the input, output, and reference data
std::vector<ValueT> in_vec(count), out_vec(count), ref(count);
// generate some random input data
srand(seed);
std::generate(in_vec.begin(), in_vec.end(), [] { return rand() % 100; });
// copy the input to the output reference and compute the expected result
std::copy(in_vec.begin(), in_vec.end(), ref.begin());
std::sort(ref.begin(), ref.end());
// allocate the input and output data either in USM host or device allocations
ValueT *in, *out;
if constexpr (kUseUSMHostAllocation) {
// using USM host allocations
if ((in = malloc_host<ValueT>(count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'in' using "
<< "malloc_host\n";
std::terminate();
}
if ((out = malloc_host<ValueT>(count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'out' using "
<< "malloc_host\n";
std::terminate();
}
// Copy the input to USM memory and reset the output.
// This is NOT efficient since, in the case of USM host allocations,
// we could have simply generated the input data into the host allocation
// and avoided this copy. However, it makes the code cleaner to assume the
// input is always in 'in_vec' and this portion of the code is not part of
// the performance timing.
std::copy(in_vec.begin(), in_vec.end(), in);
std::fill(out, out + count, ValueT(0));
} else {
// using device allocations
if ((in = malloc_device<ValueT>(count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'in' using "
<< "malloc_device\n";
std::terminate();
}
if ((out = malloc_device<ValueT>(count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'out' using "
<< "malloc_device\n";
std::terminate();
}
// copy the input to the device memory and wait for the copy to finish
q.memcpy(in, in_vec.data(), count * sizeof(ValueT)).wait();
}
// track timing information, in ms
std::vector<double> time(runs);
try {
std::cout << "Running sort " << runs << " times for an "
<< "input size of " << count << " using " << kMergeUnits
<< " " << kSortWidth << "-way merge units\n";
std::cout << "Streaming data from "
<< (kUseUSMHostAllocation ? "host" : "device") << " memory\n";
// the pointer type for the kernel depends on whether data is coming from
// USM host or device allocations
using KernelPtrType =
typename std::conditional_t<kUseUSMHostAllocation, host_ptr<ValueT>,
device_ptr<ValueT>>;
// run the sort multiple times to increase the accuracy of the timing
for (int i = 0; i < runs; i++) {
// run the sort
time[i] = FPGASort<ValueT, IndexT, KernelPtrType>(q, in, out, count);
// Copy the output to 'out_vec'. In the case where we are using USM host
// allocations this is unnecessary since we could simply deference
// 'out'. However, it makes the following code cleaner since the output
// is always in 'out_vec' and this copy is not part of the performance
// timing.
q.memcpy(out_vec.data(), out, count * sizeof(ValueT)).wait();
// validate the output
passed &= Validate(out_vec.data(), ref.data(), count);
}
} catch (exception const &e) {
std::cout << "Caught a synchronous SYCL exception: " << e.what() << "\n";
std::terminate();
}
// free the memory allocated with malloc_host or malloc_device
sycl::free(in, q);
sycl::free(out, q);
// print the performance results
if (passed) {
// NOTE: when run in emulation, these results do not accurately represent
// the performance of the kernels in actual FPGA hardware
double avg_time_ms =
std::accumulate(time.begin() + 1, time.end(), 0.0) / (runs - 1);
IndexT input_count_mega = count * 1e-6;
std::cout << "Execution time: " << avg_time_ms << " ms\n";
std::cout << "Throughput: " << (input_count_mega / (avg_time_ms * 1e-3))
<< " Melements/s\n";
std::cout << "PASSED\n";
return 0;
} else {
std::cout << "FAILED\n";
return 1;
}
}
// forward declare the kernel and pipe IDs to reduce name mangling
class InputKernelID;
class OutputKernelID;
class SortInPipeID;
class SortOutPipeID;
//
// perform the actual sort on the FPGA.
//
template <typename ValueT, typename IndexT, typename KernelPtrType>
double FPGASort(queue &q, ValueT *in_ptr, ValueT *out_ptr, IndexT count) {
// the input and output pipe for the sorter
using SortInPipe =
sycl::ext::intel::pipe<SortInPipeID, sycl::vec<ValueT, kSortWidth>>;
using SortOutPipe =
sycl::ext::intel::pipe<SortOutPipeID, sycl::vec<ValueT, kSortWidth>>;
// the sorter must sort a power of 2, so round up the requested count
// to the nearest power of 2; we will pad the input to make sure the
// output is still correct
const IndexT sorter_count = fpga_tools::RoundUpPow2(count);
// allocate some memory for the merge sort to use as temporary storage
ValueT *buf_0, *buf_1;
#if defined (IS_BSP)
if ((buf_0 = malloc_device<ValueT>(sorter_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate memory for 'buf_0'\n";
std::terminate();
}
if ((buf_1 = malloc_device<ValueT>(sorter_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate memory for 'buf_1'\n";
std::terminate();
}
#else
if ((buf_0 = malloc_shared<ValueT>(sorter_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate memory for 'buf_0'\n";
std::terminate();
}
if ((buf_1 = malloc_shared<ValueT>(sorter_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate memory for 'buf_1'\n";
std::terminate();
}
#endif
// This is the element we will pad the input with. In the case of this design,
// we are sorting from smallest to largest and we want the last elements out
// to be this element, so pad with MAX. If you are sorting from largest to
// smallest, make this the MIN element. If you are sorting custom types
// which are not supported by std::numeric_limits, then you will have to set
// this padding element differently.
const auto padding_element = std::numeric_limits<ValueT>::max();
// We are sorting kSortWidth elements per cycle, so we will have
// sorter_count/kSortWidth pipe reads/writes from/to the sorter
const IndexT total_pipe_accesses = sorter_count / kSortWidth;
// launch the kernel that provides data into the sorter
auto input_kernel_event =
q.single_task<InputKernelID>([=]() [[intel::kernel_args_restrict]] {
// read from the input pointer and write it to the sorter's input pipe
KernelPtrType in(in_ptr);
for (IndexT i = 0; i < total_pipe_accesses; i++) {
// read data from device memory
bool in_range = i * kSortWidth < count;
// build the input pipe data
sycl::vec<ValueT, kSortWidth> data;
#pragma unroll
for (unsigned char j = 0; j < kSortWidth; j++) {
data[j] = in_range ? in[i * kSortWidth + j] : padding_element;
}
// write it into the sorter
SortInPipe::write(data);
}
});
// launch the kernel that reads out data from the sorter
auto output_kernel_event =
q.single_task<OutputKernelID>([=]() [[intel::kernel_args_restrict]] {
// read from the sorter's output pipe and write to the output pointer
KernelPtrType out(out_ptr);
for (IndexT i = 0; i < total_pipe_accesses; i++) {
// read data from the sorter
auto data = SortOutPipe::read();
// sorter_count is a multiple of kSortWidth
bool in_range = i * kSortWidth < count;
// only write out to device memory if the index is in range
if (in_range) {
// write output to device memory
#pragma unroll
for (unsigned char j = 0; j < kSortWidth; j++) {
out[i * kSortWidth + j] = data[j];
}
}
}
});
// launch the merge sort kernels
auto merge_sort_events =
SubmitMergeSort<ValueT, IndexT, SortInPipe, SortOutPipe, kSortWidth,
kMergeUnits>(q, sorter_count, buf_0, buf_1);
// wait for the input and output kernels to finish
auto start = high_resolution_clock::now();
input_kernel_event.wait();
output_kernel_event.wait();
auto end = high_resolution_clock::now();
// wait for the merge sort kernels to finish
for (auto &e : merge_sort_events) {
e.wait();
}
// free the memory allocated for the merge sort temporary buffers
sycl::free(buf_0, q);
sycl::free(buf_1, q);
// return the duration of the sort in milliseconds, excluding memory transfers
duration<double, std::milli> diff = end - start;
return diff.count();
}
//
// simple function to check if two regions of memory contain the same values
//
template <typename T>
bool Validate(T *val, T *ref, unsigned int count) {
for (unsigned int i = 0; i < count; i++) {
if (val[i] != ref[i]) {
std::cout << "ERROR: mismatch at entry " << i << "\n";
std::cout << "\t" << val[i] << " != " << ref[i]
<< " (val[i] != ref[i])\n";
return false;
}
}
return true;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/consume.hpp | #ifndef __CONSUME_HPP__
#define __CONSUME_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
//
// Streams in 'k_width' elements of data per cycle from a SYCL pipe and either
// writes it to memory (to_pipe==false) or writes it to a pipe (to_pipe==true)
//
template <typename Id, typename ValueT, typename IndexT, typename InPipe,
typename OutPipe, unsigned char k_width>
event Consume(queue& q, ValueT* out_ptr, IndexT total_count, IndexT offset,
bool to_pipe) {
// the number of loop iterations required to consume all of the data
const IndexT iterations = total_count / k_width;
return q.single_task<Id>([=]() [[intel::kernel_args_restrict]] {
// Pointer to the output data.
// Creating a device_ptr tells the compiler that this pointer is in
// device memory, not host memory, and avoids creating extra connections
// to host memory
// This is only done in the case where we target a BSP as device
// pointers are not supported when targeting an FPGA family/part
#if defined(IS_BSP)
device_ptr<ValueT> out(out_ptr);
#else
ValueT* out(out_ptr);
#endif
for (IndexT i = 0; i < iterations; i++) {
// get the data from the pipe
auto data = InPipe::read();
// write to either the output pipe, or to device memory
if (to_pipe) {
OutPipe::write(data);
} else {
// write the 'k_width' elements to device memory
#pragma unroll
for (unsigned char j = 0; j < k_width; j++) {
out[offset + i * k_width + j] = data[j];
}
}
}
});
}
#endif /* __CONSUME_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/sorting_networks.hpp | #ifndef __SORTINGNETWORKS_HPP__
#define __SORTINGNETWORKS_HPP__
#include <algorithm>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
using namespace sycl;
//
// Creates a merge sort network.
// Takes in two sorted lists ('a' and 'b') of size 'k_width' and merges them
// into a single sorted output in a single cycle, in the steady state.
//
// Convention:
// a = {data[0], data[2], data[4], ...}
// b = {data[1], data[3], data[5], ...}
//
template <typename ValueT, unsigned char k_width, class CompareFunc>
void MergeSortNetwork(sycl::vec<ValueT, k_width * 2>& data,
CompareFunc compare) {
if constexpr (k_width == 4) {
// Special case for k_width==4 that has 1 less compare on the critical path
#pragma unroll
for (unsigned char i = 0; i < 4; i++) {
if (!compare(data[2 * i], data[2 * i + 1])) {
std::swap(data[2 * i], data[2 * i + 1]);
}
}
if (!compare(data[1], data[4])) {
std::swap(data[1], data[4]);
}
if (!compare(data[3], data[6])) {
std::swap(data[3], data[6]);
}
#pragma unroll
for (unsigned char i = 0; i < 3; i++) {
if (!compare(data[2 * i + 1], data[2 * i + 2])) {
std::swap(data[2 * i + 1], data[2 * i + 2]);
}
}
} else {
// the general case
// this works well for k_width = 1 or 2, but is not optimal for
// k_width = 4 (see if-case above) or higher
constexpr unsigned char merge_tree_depth = fpga_tools::Log2(k_width * 2);
#pragma unroll
for (unsigned i = 0; i < merge_tree_depth; i++) {
#pragma unroll
for (unsigned j = 0; j < k_width - i; j++) {
if (!compare(data[i + 2 * j], data[i + 2 * j + 1])) {
std::swap(data[i + 2 * j], data[i + 2 * j + 1]);
}
}
}
}
}
//
// Creates a bitonic sorting network.
// It accepts and sorts 'k_width' elements per cycle, in the steady state.
// For more info see: https://en.wikipedia.org/wiki/Bitonic_sorter
//
template <typename ValueT, unsigned char k_width, class CompareFunc>
void BitonicSortNetwork(sycl::vec<ValueT, k_width>& data, CompareFunc compare) {
#pragma unroll
for (unsigned char k = 2; k <= k_width; k *= 2) {
#pragma unroll
for (unsigned char j = k / 2; j > 0; j /= 2) {
#pragma unroll
for (unsigned char i = 0; i < k_width; i++) {
const unsigned char l = i ^ j;
if (l > i) {
const bool comp = compare(data[i], data[l]);
const bool cond1 = ((i & k) == 0) && !comp;
const bool cond2 = ((i & k) != 0) && comp;
if (cond1 || cond2) {
std::swap(data[i], data[l]);
}
}
}
}
}
}
//
// The sorting network kernel.
// This kernel streams in 'k_width' elements per cycle, sends them through a
// 'k_width' wide bitonic sorting network, and writes the sorted output or size
// 'k_width' to device memory. The result is an output array ('out_ptr') of size
// 'total_count' where each set of 'k_width' elements is sorted.
//
template <typename Id, typename ValueT, typename IndexT, typename InPipe,
unsigned char k_width, class CompareFunc>
event SortNetworkKernel(queue& q, ValueT* out_ptr, IndexT total_count,
CompareFunc compare) {
// the number of loop iterations required to process all of the data
const IndexT iterations = total_count / k_width;
return q.single_task<Id>([=]() [[intel::kernel_args_restrict]] {
// Creating a device_ptr tells the compiler that this pointer is in
// device memory, not host memory, and avoids creating extra connections
// to host memory
// This is only done in the case where we target a BSP as device
// pointers are not supported when targeting an FPGA family/part
#if defined(IS_BSP)
device_ptr<ValueT> out(out_ptr);
#else
ValueT* out(out_ptr);
#endif
for (IndexT i = 0; i < iterations; i++) {
// read the input data from the pipe
sycl::vec<ValueT, k_width> data = InPipe::read();
// bitonic sort network sorts the k_width elements of 'data' in-place
// NOTE: there are no dependencies across loop iterations on 'data'
// here, so this sorting network can be fully pipelined
BitonicSortNetwork<ValueT, k_width>(data, compare);
// write the 'k_width' sorted elements to device memory
#pragma unroll
for (unsigned char j = 0; j < k_width; j++) {
out[i * k_width + j] = data[j];
}
}
});
}
#endif /* __SORTINGNETWORKS_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/produce.hpp | #ifndef __PRODUCE_HPP__
#define __PRODUCE_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
using namespace sycl;
//
// Produces 'k_width' elements of data per cycle into the merge unit from
// device memory
//
template<typename Id, typename ValueT, typename IndexT, typename OutPipe,
unsigned char k_width>
event Produce(queue& q, ValueT *in_ptr, IndexT count, IndexT in_block_count,
IndexT start_offset, std::vector<event>& depend_events) {
// the number of loop iterations required to produce all of the data
const IndexT iterations = count / k_width;
return q.submit([&](handler& h) {
h.depends_on(depend_events);
h.single_task<Id>([=]() [[intel::kernel_args_restrict]] {
// Pointer to the input data.
// Creating a device_ptr tells the compiler that this pointer is in
// device memory, not host memory, and avoids creating extra connections
// to host memory
// This is only done in the case where we target a BSP as device
// pointers are not supported when targeting an FPGA family/part
#if defined(IS_BSP)
device_ptr<ValueT> in(in_ptr);
#else
ValueT* in(in_ptr);
#endif
for (IndexT i = 0; i < iterations; i++) {
// read 'k_width' elements from device memory
sycl::vec<ValueT, k_width> pipe_data;
#pragma unroll
for (unsigned char j = 0; j < k_width; j++) {
pipe_data[j] = in[start_offset + i*k_width + j];
}
// write to the output pipe
OutPipe::write(pipe_data);
}
});
});
}
#endif /* __PRODUCE_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/merge.hpp | #ifndef __MERGE_HPP__
#define __MERGE_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "sorting_networks.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
using namespace sycl;
//
// Streams in two sorted list of size 'in_count`, 'k_width' elements at a time,
// from both InPipeA and InPipeB and merges them into a single sorted list of
// size 'in_count*2' to OutPipe. This merges two sorted lists of size in_count
// at a rate of 'k_width' elements per cycle.
//
template <typename Id, typename ValueT, typename IndexT, typename InPipeA,
typename InPipeB, typename OutPipe, unsigned char k_width,
class CompareFunc>
event Merge(queue& q, IndexT total_count, IndexT in_count,
CompareFunc compare) {
// sanity check on k_width
static_assert(k_width >= 1);
static_assert(fpga_tools::IsPow2(k_width));
// merging two lists of size 'in_count' into a single output list of
// double the size
const IndexT out_count = in_count * 2;
return q.single_task<Id>([=] {
// the two input and feedback buffers
sycl::vec<ValueT, k_width> a, b, network_feedback;
bool drain_a = false;
bool drain_b = false;
bool a_valid = false;
bool b_valid = false;
// track the number of elements we have read from each input pipe
// for each sublist (counts up to 'in_count')
IndexT read_from_a = 0;
IndexT read_from_b = 0;
// create a small 2 element shift register to track whether we have
// read the last inputs from the input pipes
bool read_from_a_is_last = false; // (0 == in_count)
bool read_from_b_is_last = false; // (0 == in_count)
bool next_read_from_a_is_last = (k_width == in_count);
bool next_read_from_b_is_last = (k_width == in_count);
// track the number of elements we have written to the output pipe
// for each sublist (counts up to 'out_count')
IndexT written_out_inner = 0;
// track the number of elements we have written to the output pipe
// in total (counts up to 'total_count')
IndexT written_out = 0;
// this flag indicates that the chosen buffer (from Pipe A or B) is the
// first buffer from either sublist. This indicates that no output will
// be produced and instead we will just populate the feedback buffer
bool first_in_buffer = true;
// the main processing loop
[[intel::initiation_interval(1)]]
while (written_out != total_count) {
// read 'k_width' elements from Pipe A
if (!a_valid && !drain_b) {
a = InPipeA::read();
a_valid = true;
read_from_a_is_last = next_read_from_a_is_last;
next_read_from_a_is_last = (read_from_a == in_count-2*k_width);
read_from_a += k_width;
}
// read 'k_width' elements from Pipe B
if (!b_valid && !drain_a) {
b = InPipeB::read();
b_valid = true;
read_from_b_is_last = next_read_from_b_is_last;
next_read_from_b_is_last = (read_from_b == in_count-2*k_width);
read_from_b += k_width;
}
// determine which of the two inputs to feed into the merge sort network
bool choose_a = ((compare(a[0], b[0]) || drain_a) && !drain_b);
auto chosen_data_in = choose_a ? a : b;
// create input for merge sort network sorter network
sycl::vec<ValueT, k_width * 2> merge_sort_network_data;
#pragma unroll
for (unsigned char i = 0; i < k_width; i++) {
// populate the k_width*2 sized input for the merge sort network
// from the chosen input data and the feedback data
merge_sort_network_data[2 * i] = chosen_data_in[i];
merge_sort_network_data[2 * i + 1] = network_feedback[i];
}
// merge sort network, which sorts 'merge_sort_network_data' in-place
MergeSortNetwork<ValueT, k_width>(merge_sort_network_data, compare);
if (first_in_buffer) {
// the first buffer read for a sublist doesn't create any output,
// it just creates feedback
#pragma unroll
for (unsigned char i = 0; i < k_width; i++) {
network_feedback[i] = chosen_data_in[i];
}
drain_a = drain_a | (read_from_b_is_last && !choose_a);
drain_b = drain_b | (read_from_a_is_last && choose_a);
a_valid = !choose_a;
b_valid = choose_a;
first_in_buffer = false;
} else {
sycl::vec<ValueT, k_width> out_data;
if (written_out_inner == out_count - k_width) {
// on the last iteration for a set of sublists, the feedback
// is the only data left that is valid, so it goes to the output
out_data = network_feedback;
} else {
// grab the output and feedback data from the merge sort network
#pragma unroll
for (unsigned char i = 0; i < k_width; i++) {
out_data[i] = merge_sort_network_data[i];
network_feedback[i] = merge_sort_network_data[k_width + i];
}
}
// write the output data to the output pipe
OutPipe::write(out_data);
written_out += k_width;
// check if switching to a new set of 'in_count' sorted sublists
if (written_out_inner == out_count - k_width) {
// switching, so reset all internal counters and flags
drain_a = false;
drain_b = false;
a_valid = false;
b_valid = false;
read_from_a = 0;
read_from_b = 0;
read_from_a_is_last = false; // (0 == in_count)
read_from_b_is_last = false; // (0 == in_count)
next_read_from_a_is_last = (k_width == in_count);
next_read_from_b_is_last = (k_width == in_count);
written_out_inner = 0;
first_in_buffer = true;
} else {
// not switching, so update counters and flags
written_out_inner += k_width;
drain_a = drain_a | (read_from_b_is_last && !choose_a);
drain_b = drain_b | (read_from_a_is_last && choose_a);
a_valid = !choose_a;
b_valid = choose_a;
}
}
}
});
}
#endif /* __MERGE_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/src/merge_sort.hpp | #ifndef __MERGESORT_HPP__
#define __MERGESORT_HPP__
#include <array>
#include <iostream>
#include <limits>
#include <type_traits>
#include <vector>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "consume.hpp"
#include "merge.hpp"
#include "produce.hpp"
#include "sorting_networks.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "pipe_utils.hpp"
#include "unrolled_loop.hpp"
using namespace sycl;
///////////////////////////////////////////////////////////////
// Convenient default comparators
struct LessThan {
template <class T>
bool operator()(T const& a, T const& b) const {
return a < b;
}
};
struct GreaterThan {
template <class T>
bool operator()(T const& a, T const& b) const {
return a > b;
}
};
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Forward declare kernel and pipe IDs to reduce name mangling
// Kernel and pipe ID classes for the merge units
template <int u>
class ProduceAKernelID;
template <int u>
class ProduceBKernelID;
template <int u>
class MergeKernelID;
template <int u>
class ConsumeKernelID;
class SortNetworkID;
class APipeID;
class BPipeID;
class MergePipeID;
class InternalOutPipeID;
// Kernel and pipe ID classes for the merge tree
template <int u, int v>
class MergeTreeMergeKernelID;
class InternalMergeTreePipeID;
///////////////////////////////////////////////////////////////
//
// Submits all of the merge sort kernels necessary to sort 'count' elements.
// Returns all of the events for the caller to wait on.
// NOTE: there is no need to worry about returing a std::vector by value here;
// C++ return-value-optimization (RVO) will take care of it!
//
template <typename ValueT, typename IndexT, typename InPipe, typename OutPipe,
unsigned char k_width, size_t units, typename Compare>
std::vector<event> SubmitMergeSort(queue& q, size_t count, ValueT* buf_0,
ValueT* buf_1, Compare comp) {
// sanity check the number of merge units and the width of the sorter
static_assert(units >= 1);
static_assert(fpga_tools::IsPow2(units));
static_assert(k_width >= 1);
static_assert(fpga_tools::IsPow2(k_width));
// sanity check on IndexT
static_assert(std::is_integral_v<IndexT>);
// ensure we have a valid compare function
static_assert(
std::is_invocable_r_v<bool, Compare, ValueT, ValueT>,
"The 'Compare' function type must be invocable (i.e. operator()) with two"
"'ValueT' arguments and returning a boolean");
// A depth of 0 allows the compiler to pick the depth for each pipe, which
// allows it to balance the depth of the pipeline.
constexpr size_t kDefPipeDepth = 0;
// the type that is passed around the pipes
using PipeType = sycl::vec<ValueT, k_width>;
// the pipes connecting the different kernels of each merge unit
// one set of pipes for each 'units' merge units
using APipes =
fpga_tools::PipeArray<APipeID, PipeType, kDefPipeDepth, units>;
using BPipes =
fpga_tools::PipeArray<BPipeID, PipeType, kDefPipeDepth, units>;
using MergePipes =
fpga_tools::PipeArray<MergePipeID, PipeType, kDefPipeDepth, units>;
using InternalOutPipes =
fpga_tools::PipeArray<InternalOutPipeID, PipeType, kDefPipeDepth, units>;
//////////////////////////////////////////////////////////////////////////////
// These defines make the latter code cleaner
#define SubmitSortNetworkKernel \
SortNetworkKernel<SortNetworkID, ValueT, IndexT, InPipe, k_width>
#define SubmitProduceA \
Produce<ProduceAKernelID<u>, ValueT, IndexT, APipe, k_width>
#define SubmitProduceB \
Produce<ProduceBKernelID<u>, ValueT, IndexT, BPipe, k_width>
#define SubmitMerge \
Merge<MergeKernelID<u>, ValueT, IndexT, APipe, BPipe, MergePipe, k_width>
#define SubmitConsume \
Consume<ConsumeKernelID<u>, ValueT, IndexT, MergePipe, InternalOutPipe, \
k_width>
#define SubmitMTMerge \
Merge<MergeTreeMergeKernelID<level, merge_unit>, ValueT, IndexT, MTAPipe, \
MTBPipe, MTOutPipe, k_width>
//////////////////////////////////////////////////////////////////////////////
// depth of the merge tree to reduce the sorted partitions of each merge unit
constexpr size_t kReductionLevels = fpga_tools::Log2(units);
// validate 'count'
if (count == 0) {
std::cerr << "ERROR: 'count' must be greater than 0\n";
std::terminate();
} else if (!fpga_tools::IsPow2(count)) {
std::cerr << "ERROR: 'count' must be a power of 2\n";
std::terminate();
} else if (count < 4 * units) {
std::cerr << "ERROR: 'count' must be at least 4x greater than "
<< "the number of merge units (" << units << ")\n";
std::terminate();
} else if (count > std::numeric_limits<IndexT>::max()) {
std::cerr << "ERROR: the index type does not have enough bits to count to "
<< "'count'\n";
std::terminate();
} else if ((count / units) <= k_width) {
std::cerr << "ERROR: 'count/units' (elements per merge unit) "
<< "must be greater than k_width\n";
std::terminate();
}
// validate the input buffers
if (buf_0 == nullptr) {
std::cerr << "ERROR: 'buf_0' is nullptr\n";
std::terminate();
}
if (buf_1 == nullptr) {
std::cerr << "ERROR: 'buf_1' is nullptr\n";
std::terminate();
}
// double buffering is more convenient with an array of pointers,
// so create one from the two buffers passed in by the caller
ValueT* buf[2] = {buf_0, buf_1};
// using double buffering, so track the current buffer and have a simple
// lambda to compute the next buffer index
unsigned buf_idx = 0;
auto next_buf_idx = [](unsigned buf_idx) { return buf_idx ^ 0x1; };
// the number of elements each merge unit will sort
const IndexT count_per_unit = count / units;
// each producer will produce half of the data for each merge unit
const IndexT half_count_per_unit = count_per_unit / 2;
// the number of sorting iterations each merge unit will perform
// NOTE: we subtract log2(k_width) because the bitonic sorting network
// performs the first log2(k_width) iterations of the sort while streaming
// the input data from the input pipe into device memory.
const IndexT iterations =
fpga_tools::Log2(count_per_unit) - fpga_tools::Log2(k_width);
// store the various merge unit and merge tree kernel events
std::array<std::vector<event>, units> produce_a_events, produce_b_events,
merge_events, consume_events;
std::array<std::vector<event>, kReductionLevels> mt_merge_events;
for (size_t i = 0; i < units; i++) {
produce_a_events[i].resize(iterations);
produce_b_events[i].resize(iterations);
merge_events[i].resize(iterations);
consume_events[i].resize(iterations);
}
// launch the sorting network kernel that performs the first log2(k_width)
// iterations of the sort. For example, if k_width=4, the sorting network
// sorts 4 elements per cycle, in the steady state. This means we need
// log2(4)=2 less iterations of the merge sort since we start with sorted
// sublists of size 4.
auto sort_network_event =
SubmitSortNetworkKernel(q, buf[buf_idx], count, comp);
////////////////////////////////////////////////////////////////////////////
// Launching all of the merge unit kernels
// start with inputs of size 'k_width' since the data from the input pipe
// was sent through a sorting network that sorted sublists of size 'k_width'.
IndexT in_count = k_width;
// perform the sort iterations for each merge unit
for (size_t i = 0; i < iterations; i++) {
// The Consume kernels will write to a pipe on the last iteration
bool consumer_to_pipe = (i == (iterations - 1));
// launch the merge unit kernels for this iteration of the sort using
// a front-end meta-programming unroller
fpga_tools::UnrolledLoop<units>([&](auto u) {
// the intra merge unit pipes
using APipe = typename APipes::template PipeAt<u>;
using BPipe = typename BPipes::template PipeAt<u>;
using MergePipe = typename MergePipes::template PipeAt<u>;
// if there is only 1 merge unit, there will be no merge tree, so the
// single merge unit's output pipe will be the entire sort's output pipe
using InternalOutPipe =
std::conditional_t<(units == 1), OutPipe,
typename InternalOutPipes::template PipeAt<u>>;
// build the dependency event vector
std::vector<event> wait_events;
if (i == 0) {
// on the first iteration, wait for sorting network kernel to be done so
// that all of the data is in the temp buffers in device memory
wait_events.push_back(sort_network_event);
} else {
// on all iterations (except the first), Produce kernels for the
// current iteration must wait for the Consume kernels to be done
// writing to device memory from the previous iteration.
// This is coarse grain synchronization between the Produce and Consume
// kernels of each merge unit.
wait_events.push_back(consume_events[u][i - 1]);
}
// the temporary device buffers reside in a single device allocation,
// so compute the offset into the buffer for each merge unit.
const size_t unit_buf_offset = count_per_unit * u;
// get device pointers for this merge unit's Produce and Consume kernels
ValueT* in_buf = buf[buf_idx];
ValueT* out_buf = buf[next_buf_idx(buf_idx)];
////////////////////////////////////////////////////////////////////////
// Enqueue the merge unit kernels
// Produce A
produce_a_events[u][i] =
SubmitProduceA(q, in_buf, half_count_per_unit, in_count,
unit_buf_offset, wait_events);
// Produce B
produce_b_events[u][i] =
SubmitProduceB(q, in_buf, half_count_per_unit, in_count,
unit_buf_offset + half_count_per_unit, wait_events);
// Merge
merge_events[u][i] = SubmitMerge(q, count_per_unit, in_count, comp);
// Consume
consume_events[u][i] = SubmitConsume(q, out_buf, count_per_unit,
unit_buf_offset, consumer_to_pipe);
////////////////////////////////////////////////////////////////////////
});
////////////////////////////////////////////////////////////////////////
// swap buffers
buf_idx = next_buf_idx(buf_idx);
// increase the input size
in_count *= 2;
}
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// Launching all of the merge tree kernels
// the merge tree pipe array
// NOTE: we actually only need 2^(kReductionLevels)-2 total pipes,
// but we have created a 2D pipe array with kReductionLevels*units
// pipes. The 2D pipe array makes the metaprogramming much easier and the
// front-end compiler will not use the extra pipes and therefore they
// will NOT be instantiated in hardware
using InternalMTPipes =
fpga_tools::PipeArray<InternalMergeTreePipeID, PipeType, kDefPipeDepth,
kReductionLevels, units>;
// create the merge tree connected by pipes to merge the sorted output
// of each merge unit into a single sorted output. The output of the last
// level of the merge tree will stream out of 'OutPipe'.
// NOTE: if units==1, then there is no merge tree!
fpga_tools::UnrolledLoop<kReductionLevels>([&](auto level) {
// each level of the merge tree reduces the number of sorted partitions
// by a factor of 2.
// level 0 has 'units' merge kernels, level 1 has 'units/2', and so on...
// See README.md for a good illustration.
constexpr size_t kLevelMergeUnits = units / ((1 << level) * 2);
fpga_tools::UnrolledLoop<kLevelMergeUnits>([&](auto merge_unit) {
// When level == 0, we know we will use 'MTAPipeFromMergeUnit' and
// 'MTBPipeFromMergeUnit' below. However, we cannot access
// PipeAt<-1, ...> without a compiler error. So, we will set the previous
// level to 0, knowing that we will NOT use 'MTAPipeFromMergeTree' nor
// 'MTBPipeFromMergeTree' in the case that level == 0.
constexpr size_t prev_level = (level == 0) ? 0 : level - 1;
// 'PipeA' for this merge kernel in the merge tree.
// If the merge tree level is 0, the pipe is from a merge unit,
// otherwise it is from the previous level of the merge tree.
using MTAPipeFromMergeUnit =
typename InternalOutPipes::template PipeAt<merge_unit * 2>;
using MTAPipeFromMergeTree =
typename InternalMTPipes::template PipeAt<prev_level, merge_unit * 2>;
using MTAPipe =
typename std::conditional_t<(level == 0), MTAPipeFromMergeUnit,
MTAPipeFromMergeTree>;
// 'PipeB' for this merge kernel in the merge tree.
// If the merge tree level is 0, the pipe is from a merge unit,
// otherwise it is from the previous level of the merge tree.
using MTBPipeFromMergeUnit =
typename InternalOutPipes::template PipeAt<merge_unit * 2 + 1>;
using MTBPipeFromMergeTree =
typename InternalMTPipes::template PipeAt<prev_level,
merge_unit * 2 + 1>;
using MTBPipe =
typename std::conditional_t<(level == 0), MTBPipeFromMergeUnit,
MTBPipeFromMergeTree>;
// 'OutPipe' for this merge kernel in the merge tree.
// If this is the last level, then the output pipe is the output pipe
// of the entire sorter, otherwise it is going to another level of the
// merge tree.
using MTOutPipeToMT =
typename InternalMTPipes::template PipeAt<level, merge_unit>;
using MTOutPipe =
typename std::conditional_t<(level == (kReductionLevels - 1)),
OutPipe, MTOutPipeToMT>;
// Launch the merge kernel
const auto e = SubmitMTMerge(q, in_count * 2, in_count, comp);
mt_merge_events[level].push_back(e);
});
// increase the input size
in_count *= 2;
});
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// Combine all kernel events into a single return vector
std::vector<event> ret;
// add event from the sorting network stage
ret.push_back(sort_network_event);
// add each merge unit's sorting events
for (size_t u = 0; u < units; u++) {
ret.insert(ret.end(), produce_a_events[u].begin(),
produce_a_events[u].end());
ret.insert(ret.end(), produce_b_events[u].begin(),
produce_b_events[u].end());
ret.insert(ret.end(), merge_events[u].begin(), merge_events[u].end());
ret.insert(ret.end(), consume_events[u].begin(), consume_events[u].end());
}
// add the merge tree kernel events
for (size_t level = 0; level < kReductionLevels; level++) {
ret.insert(ret.end(), mt_merge_events[level].begin(),
mt_merge_events[level].end());
}
return ret;
////////////////////////////////////////////////////////////////////////////
}
//
// A convenient function that defaults the sorter's comparator to 'LessThan'
// (i.e., operator<)
//
template <typename ValueT, typename IndexT, typename InPipe, typename OutPipe,
unsigned char k_width, size_t units>
std::vector<event> SubmitMergeSort(queue& q, IndexT count, ValueT* buf_0,
ValueT* buf_1) {
return SubmitMergeSort<ValueT, IndexT, InPipe, OutPipe, k_width, units>(
q, count, buf_0, buf_1, LessThan());
}
#endif /* __MERGESORT_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzip.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include <fstream>
#include <string>
#include "CompareGzip.hpp"
#include "WriteGzip.hpp"
#include "crc32.hpp"
#include "gzipkernel.hpp"
#include "kernels.hpp"
#include "exception_handler.hpp"
using namespace sycl;
// The minimum file size of a file to be compressed.
// Any filesize less than this results in an error.
constexpr int minimum_filesize = kVec + 1;
bool help = false;
int CompressFile(queue &q, std::string &input_file, std::vector<std::string> outfilenames,
int iterations, bool report);
void Help(void) {
// Command line arguments.
// gzip [options] filetozip [options]
// -h,--help : help
// future options?
// -p,performance : output perf metrics
// -m,maxmapping=# : maximum mapping size
std::cout << "gzip filename [options]\n";
std::cout << " -h,--help : this help text\n";
std::cout
<< " -o=<filename>,--output-file=<filename> : specify output file\n";
}
bool FindGetArg(std::string &arg, const char *str, int defaultval, int *val) {
std::size_t found = arg.find(str, 0, strlen(str));
if (found != std::string::npos) {
int value = atoi(&arg.c_str()[strlen(str)]);
*val = value;
return true;
}
return false;
}
constexpr int kMaxStringLen = 40;
bool FindGetArgString(std::string &arg, const char *str, char *str_value,
size_t maxchars) {
std::size_t found = arg.find(str, 0, strlen(str));
if (found != std::string::npos) {
const char *sptr = &arg.c_str()[strlen(str)];
for (int i = 0; i < maxchars - 1; i++) {
char ch = sptr[i];
switch (ch) {
case ' ':
case '\t':
case '\0':
str_value[i] = 0;
return true;
break;
default:
str_value[i] = ch;
break;
}
}
return true;
}
return false;
}
size_t SyclGetExecTimeNs(event e) {
size_t start_time =
e.get_profiling_info<info::event_profiling::command_start>();
size_t end_time =
e.get_profiling_info<info::event_profiling::command_end>();
return (end_time - start_time);
}
int main(int argc, char *argv[]) {
std::string infilename = "";
std::vector<std::string> outfilenames (kNumEngines);
char str_buffer[kMaxStringLen] = {0};
// Check the number of arguments specified
if (argc != 3) {
std::cerr << "Incorrect number of arguments. Correct usage: " << argv[0]
<< " <input-file> -o=<output-file>\n";
return 1;
}
for (int i = 1; i < argc; i++) {
if (argv[i][0] == '-') {
std::string sarg(argv[i]);
if (std::string(argv[i]) == "-h") {
help = true;
}
if (std::string(argv[i]) == "--help") {
help = true;
}
FindGetArgString(sarg, "-o=", str_buffer, kMaxStringLen);
FindGetArgString(sarg, "--output-file=", str_buffer, kMaxStringLen);
} else {
infilename = std::string(argv[i]);
}
}
if (help) {
Help();
return 1;
}
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
auto prop_list = property_list{property::queue::enable_profiling()};
queue q(selector, fpga_tools::exception_handler, prop_list);
auto device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<info::device::name>().c_str()
<< std::endl;
if (infilename == "") {
std::cout << "Must specify a filename to compress\n\n";
Help();
return 1;
}
// next, check valid and acceptable parameter ranges.
// if output filename not set, use the default
// name, else use the name specified by the user
outfilenames[0] = std::string(infilename) + ".gz";
if (strlen(str_buffer)) {
outfilenames[0] = std::string(str_buffer);
}
for (size_t i=1; i< kNumEngines; i++) {
// Filenames will be of the form outfilename, outfilename2, outfilename3 etc.
outfilenames[i] = outfilenames[0] + std::to_string(i+1);
}
std::cout << "Launching High-Bandwidth DMA GZIP application with " << kNumEngines
<< " engines\n";
#ifdef FPGA_EMULATOR
CompressFile(q, infilename, outfilenames, 1, true);
#elif FPGA_SIMULATOR
CompressFile(q, infilename, outfilenames, 2, true);
#else
// warmup run - use this run to warmup accelerator. There are some steps in
// the runtime that are only executed on the first kernel invocation but not
// on subsequent invocations. So execute all that stuff here before we
// measure performance (in the next call to CompressFile().
CompressFile(q, infilename, outfilenames, 1, false);
// profile performance
CompressFile(q, infilename, outfilenames, 200, true);
#endif
} catch (sycl::exception const &e) {
// Catches exceptions in the host code
std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";
// Most likely the runtime couldn't find FPGA hardware!
if (e.code().value() == CL_DEVICE_NOT_FOUND) {
std::cerr << "If you are targeting an FPGA, please ensure that your "
"system has a correctly configured FPGA board.\n";
std::cerr << "Run sys_check in the oneAPI root directory to verify.\n";
std::cerr << "If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR.\n";
std::cerr << "If you are targeting the FPGA simulator, compile with "
"-DFPGA_SIMULATOR.\n";
}
std::terminate();
}
return 0;
}
struct KernelInfo {
buffer<struct GzipOutInfo, 1> *gzip_out_buf;
buffer<unsigned, 1> *current_crc;
buffer<char, 1> *pobuf;
buffer<char, 1> *pibuf;
char *pobuf_decompress;
uint32_t buffer_crc[kMinBufferSize];
uint32_t refcrc;
const char *pref_buffer;
char *poutput_buffer;
size_t file_size;
struct GzipOutInfo out_info[kMinBufferSize];
int iteration;
bool last_block;
};
// returns 0 on success, otherwise a non-zero failure code.
int CompressFile(queue &q, std::string &input_file, std::vector<std::string> outfilenames,
int iterations, bool report) {
size_t isz;
char *pinbuf;
// Read the input file
std::string device_string =
q.get_device().get_info<info::device::name>().c_str();
// If the device is supports USM allocations, we pre-pin some buffers to
// improve DMA performance, which is needed to
// achieve peak kernel throughput. Pre-pinning is
// only supported on the USM capable BSPs. It's not
// needed on non-USM capabale BSPs to achieve peak performance.
#ifdef FPGA_SIMULATOR
bool prepin = false;
#else
bool prepin = q.get_device().has(aspect::usm_host_allocations);
#endif
// padding for the input and output buffers to deal with granularity of
// kernel reads and writes
constexpr size_t kInOutPadding = 16 * kVec;
std::ifstream file(input_file,
std::ios::in | std::ios::binary | std::ios::ate);
if (file.is_open()) {
isz = file.tellg();
if (prepin) {
pinbuf = (char *)malloc_host(
isz + kInOutPadding, q.get_context()); // Pre-pin the buffer, for faster DMA
} else { // throughput, using malloc_host().
pinbuf = new char[isz + kInOutPadding];
}
file.seekg(0, std::ios::beg);
file.read(pinbuf, isz);
file.close();
} else {
std::cout << "Error: cannot read specified input file\n";
return 1;
}
if (isz < minimum_filesize) {
std::cout << "Minimum filesize for compression is " << minimum_filesize
<< "\n";
return 1;
}
int buffers_count = iterations;
// Create an array of kernel info structures and create buffers for kernel
// input/output. The buffers are re-used between iterations, but enough
// disjoint buffers are created to support double-buffering.
struct KernelInfo *kinfo[kNumEngines];
for (size_t eng = 0; eng < kNumEngines; eng++) {
kinfo[eng] =
(struct KernelInfo *)malloc(sizeof(struct KernelInfo) * buffers_count);
if (kinfo[eng] == NULL) {
std::cout << "Cannot allocate kernel info buffer.\n";
return 1;
}
for (int i = 0; i < buffers_count; i++) {
kinfo[eng][i].file_size = isz;
// Allocating slightly larger buffers (+ 16 * kVec) to account for
// granularity of kernel writes
int outputSize =
((isz + kInOutPadding) < kMinBufferSize) ? kMinBufferSize
: (isz + kInOutPadding);
const size_t input_alloc_size = isz + kInOutPadding;
// Pre-pin buffer using malloc_host() to improve DMA bandwidth.
if (i >= 3) {
kinfo[eng][i].poutput_buffer = kinfo[eng][i - 3].poutput_buffer;
} else {
if (prepin) {
kinfo[eng][i].poutput_buffer =
(char *)malloc_host(outputSize, q.get_context());
} else {
kinfo[eng][i].poutput_buffer = (char *)malloc(outputSize);
}
std::cout << "outputSize: " << outputSize << " Prepin: "
<< prepin << "\n";
std::cout << "kMinBufferSize: " << kMinBufferSize << " isz: " << isz
<< " kInOutPadding: " << kInOutPadding << "\n";
if (kinfo[eng][i].poutput_buffer == NULL) {
std::cout << "Cannot allocate output buffer.\n";
free(kinfo[eng]);
return 1;
}
// zero pages to fully allocate them
memset(kinfo[eng][i].poutput_buffer, 0, outputSize);
}
kinfo[eng][i].last_block = true;
kinfo[eng][i].iteration = i;
kinfo[eng][i].pref_buffer = pinbuf;
kinfo[eng][i].gzip_out_buf =
i >= 3 ? kinfo[eng][i - 3].gzip_out_buf
: new buffer<struct GzipOutInfo, 1>(kMinBufferSize);
kinfo[eng][i].current_crc = i >= 3
? kinfo[eng][i - 3].current_crc
: new buffer<unsigned, 1>(kMinBufferSize);
kinfo[eng][i].pibuf = i >= 3
? kinfo[eng][i - 3].pibuf
: new buffer<char, 1>(input_alloc_size);
kinfo[eng][i].pobuf =
i >= 3 ? kinfo[eng][i - 3].pobuf : new buffer<char, 1>(outputSize);
kinfo[eng][i].pobuf_decompress = (char *)malloc(kinfo[eng][i].file_size);
}
}
// Create events for the various parts of the execution so that we can profile
// their performance.
event e_input_dma [kNumEngines][buffers_count]; // Input to the GZIP engine. This is a transfer from host to device.
event e_output_dma [kNumEngines][buffers_count]; // Output from the GZIP engine. This is transfer from device to host.
event e_crc_dma [kNumEngines][buffers_count]; // Transfer CRC from device to host
event e_size_dma [kNumEngines][buffers_count]; // Transfer compressed file size from device to host
event e_k_crc [kNumEngines][buffers_count]; // CRC kernel
event e_k_lz [kNumEngines][buffers_count]; // LZ77 kernel
event e_k_huff [kNumEngines][buffers_count]; // Huffman Encoding kernel
#ifdef FPGA_EMULATOR
#elif FPGA_SIMULATOR
#else
auto start = std::chrono::steady_clock::now();
#endif
/*************************************************/
/* Main loop where the actual execution happens */
/*************************************************/
for (int i = 0; i < buffers_count; i++) {
for (size_t eng = 0; eng < kNumEngines; eng++) {
// Transfer the input data, to be compressed, from host to device.
e_input_dma[eng][i] = q.submit([&](handler &h) {
auto in_data =
kinfo[eng][i].pibuf->get_access<access::mode::discard_write>(h);
h.copy(kinfo[eng][i].pref_buffer, in_data);
});
/************************************/
/************************************/
/* LAUNCH GZIP ENGINE */
/************************************/
/************************************/
SubmitGzipTasks(q, kinfo[eng][i].file_size, kinfo[eng][i].pibuf,
kinfo[eng][i].pobuf, kinfo[eng][i].gzip_out_buf,
kinfo[eng][i].current_crc, kinfo[eng][i].last_block,
e_k_crc[eng][i], e_k_lz[eng][i], e_k_huff[eng][i], eng);
// Transfer the output (compressed) data from device to host.
e_output_dma[eng][i] = q.submit([&](handler &h) {
auto out_data = kinfo[eng][i].pobuf->get_access<access::mode::read>(h);
h.copy(out_data, kinfo[eng][i].poutput_buffer);
});
// Transfer the file size of the compressed output file from device to host.
e_size_dma[eng][i] = q.submit([&](handler &h) {
auto out_data =
kinfo[eng][i].gzip_out_buf->get_access<access::mode::read>(h);
h.copy(out_data, kinfo[eng][i].out_info);
});
// Transfer the CRC of the compressed output file from device to host.
e_crc_dma[eng][i] = q.submit([&](handler &h) {
auto out_data =
kinfo[eng][i].current_crc->get_access<access::mode::read>(h);
h.copy(out_data, kinfo[eng][i].buffer_crc);
});
}
}
// Wait for all kernels to complete
for (int eng = 0; eng < kNumEngines; eng++) {
for (int i = 0; i < buffers_count; i++) {
e_output_dma[eng][i].wait();
e_size_dma[eng][i].wait();
e_crc_dma[eng][i].wait();
}
}
// Stop the timer.
#ifdef FPGA_EMULATOR
#elif FPGA_SIMULATOR
#else
auto end = std::chrono::steady_clock::now();
double diff_total = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
double gbps = iterations * isz / (double)diff_total / 1000000000.0;
#endif
// Check the compressed file size from each iteration. Make sure the size is actually
// less-than-or-equal to the input size. Also calculate the remaining CRC.
size_t compressed_sz[kNumEngines];
for (int eng = 0; eng < kNumEngines; eng++) {
compressed_sz[eng] = 0;
for (int i = 0; i < buffers_count; i++) {
if (kinfo[eng][i].out_info[0].compression_sz > kinfo[eng][i].file_size) {
std::cerr << "Unsupported: compressed file larger than input file( "
<< kinfo[eng][i].out_info[0].compression_sz << " )\n";
return 1;
}
// The majority of the CRC is calculated by the CRC kernel on the FPGA. But the kernel
// operates on quantized chunks of input data, so any remaining input data, that falls
// outside the quanta, is included in the overall CRC calculation via the following
// function that runs on the host. The last argument is the running CRC that was computed
// on the FPGA.
kinfo[eng][i].buffer_crc[0] =
Crc32(kinfo[eng][i].pref_buffer, kinfo[eng][i].file_size,
kinfo[eng][i].buffer_crc[0]);
// Accumulate the compressed size across all iterations. Used to
// compute compression ratio later.
compressed_sz[eng] += kinfo[eng][i].out_info[0].compression_sz;
}
}
// delete the file mapping now that all kernels are complete, and we've
// snapped the time delta
if (prepin) {
free(pinbuf, q.get_context());
} else {
delete pinbuf;
}
// Write the output compressed data from the first iteration of each engine, to a file.
for (int eng = 0; eng < kNumEngines; eng++) {
// WriteBlockGzip() returns 1 on failure
if (report && WriteBlockGzip(input_file, outfilenames[eng], kinfo[eng][0].poutput_buffer,
kinfo[eng][0].out_info[0].compression_sz,
kinfo[eng][0].file_size, kinfo[eng][0].buffer_crc[0])) {
std::cout << "FAILED\n";
return 1;
}
}
// Decompress the output from engine-0 and compare against the input file. Only engine-0's
// output is verified since all engines are fed the same input data.
if (report && CompareGzipFiles(input_file, outfilenames[0])) {
std::cout << "FAILED\n";
return 1;
}
// Generate throughput report
// First gather all the execution times.
size_t time_k_crc[kNumEngines];
size_t time_k_lz[kNumEngines];
size_t time_k_huff[kNumEngines];
size_t time_input_dma[kNumEngines];
size_t time_output_dma[kNumEngines];
for (int eng = 0; eng < kNumEngines; eng++) {
time_k_crc[eng] = 0;
time_k_lz[eng] = 0;
time_k_huff[eng] = 0;
time_input_dma[eng] = 0;
time_output_dma[eng] = 0;
for (int i = 0; i < buffers_count; i++) {
e_k_crc[eng][i].wait();
e_k_lz[eng][i].wait();
e_k_huff[eng][i].wait();
time_k_crc[eng] += SyclGetExecTimeNs(e_k_crc[eng][i]);
time_k_lz[eng] += SyclGetExecTimeNs(e_k_lz[eng][i]);
time_k_huff[eng] += SyclGetExecTimeNs(e_k_huff[eng][i]);
time_input_dma[eng] += SyclGetExecTimeNs(e_input_dma[eng][i]);
time_output_dma[eng] += SyclGetExecTimeNs(e_output_dma[eng][i]);
}
}
if (report) {
double compression_ratio =
(double)((double)compressed_sz[0] / (double)isz / iterations);
#ifdef FPGA_EMULATOR
#elif FPGA_SIMULATOR
#else
std::cout << "Throughput: " << kNumEngines * gbps << " GB/s\n\n";
for (int eng = 0; eng < kNumEngines; eng++) {
std::cout << "TP breakdown for engine #" << eng << " (GB/s)\n";
std::cout << "CRC = " << iterations * isz / (double)time_k_crc[eng]
<< "\n";
std::cout << "LZ77 = " << iterations * isz / (double)time_k_lz[eng]
<< "\n";
std::cout << "Huffman Encoding = "
<< iterations * isz / (double)time_k_huff[eng] << "\n";
std::cout << "DMA host-to-device = "
<< iterations * isz / (double)time_input_dma[eng] << "\n";
std::cout << "DMA device-to-host = "
<< iterations * isz / (double)time_output_dma[eng] << "\n\n";
}
#endif
std::cout << "Compression Ratio " << compression_ratio * 100 << "%\n";
}
// Cleanup anything that was allocated by this routine.
for (int eng = 0; eng < kNumEngines; eng++) {
for (int i = 0; i < buffers_count; i++) {
if (i < 3) {
delete kinfo[eng][i].gzip_out_buf;
delete kinfo[eng][i].current_crc;
delete kinfo[eng][i].pibuf;
delete kinfo[eng][i].pobuf;
if (prepin) {
free(kinfo[eng][i].poutput_buffer, q.get_context());
} else {
free(kinfo[eng][i].poutput_buffer);
}
}
free(kinfo[eng][i].pobuf_decompress);
}
free(kinfo[eng]);
}
if (report) std::cout << "PASSED\n";
return 0;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/crc32.cpp | #include "crc32.hpp"
// This table is CRC32s for all single byte values created by using the
// makecrc.c utility from gzip for compatibility with gzip. makecrc.c can be
// found in the gzip source code project found at
// https://git.savannah.gnu.org/git/gzip.git. The polynomial 0xedb88320 is used
// for gzip, and thus used to create this table.
//
// Not copyrighted 1990, Mark Adler.
//
const unsigned int crc32_table[] = {
0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
0x2d02ef8dL};
//
// This routine creates a Crc32 from a memory buffer (address, and length), and
// a previous crc. This routine can be called iteratively on different portions
// of the same buffer, using a previously returned crc value. The
// value 0xffffffff is used for the first buffer invocation.
unsigned int Crc32Host(
const char *pbuf, // pointer to the buffer to crc
size_t sz, // number of bytes
unsigned int previous_crc) // previous CRC, allows combining.
{
unsigned int curr_crc = ~previous_crc;
if (sz) do {
curr_crc =
crc32_table[((int)curr_crc ^ (*pbuf++)) & 0xff] ^ (curr_crc >> 8);
} while (--sz);
return curr_crc ^ 0xffffffffL;
}
unsigned int Crc32(const char *in, size_t buffer_sz,
unsigned int previous_crc) {
const int num_nibbles_parallel = 64;
const int num_sections =
buffer_sz / (num_nibbles_parallel / 2); // how many loop iterations
// now deal with the remainder, this should be done on the software host
// the post-invert also happens inside crc_reference
const char *remaining_data = &in[num_sections * (num_nibbles_parallel / 2)];
int remaining_bytes = buffer_sz % (num_nibbles_parallel / 2);
return Crc32Host(remaining_data, remaining_bytes, previous_crc);
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/WriteGzip.cpp | #define _CRT_SECURE_NO_WARNINGS
#include "WriteGzip.hpp"
#include <fcntl.h>
#include <memory.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <sycl/sycl.hpp>
#include <chrono>
#include <string>
constexpr int kDeflated = 8;
#define GZIP_MAGIC "\037\213" // Magic header for gzip files, 1F 8B
#define ORIG_NAME 0x08
#define OS_CODE 0x03 // Unix OS_CODE
typedef struct GzipHeader {
unsigned char magic[2]; // 0x1f, 0x8b
unsigned char compress_method; // 0-7 reserved, 8=deflate -- kDeflated
unsigned char flags; // b0: file probably ascii
// b1: header crc-16 present
// b2: extra field present
// b3: original file name present
// b4: file comment present
// b5,6,7: reserved
unsigned long time; // file modification time in Unix format.
// Set this to 0 for now.
unsigned char extra; // depends on compression method
unsigned char os; // operating system on which compression took place
// ...
// ? bytes ... compressd data ...
unsigned long crc;
unsigned long uncompressed_sz;
} gzip_header, *pgzip_header;
inline static void PutUlong(uint8_t *pc, unsigned long l) {
pc[0] = l & 0xff;
pc[1] = (l >> 8) & 0xff;
pc[2] = (l >> 16) & 0xff;
pc[3] = (l >> 24) & 0xff;
}
// returns 0 on success, otherwise failure
int WriteBlockGzip(
std::string &original_filename, // Original file name being compressed
std::string &out_filename, // gzip filename
char *obuf, // pointer to compressed data block
size_t blen, // length of compressed data block
size_t ilen, // original block length
uint32_t buffer_crc) // the block's crc
{
//------------------------------------------------------------------
// Setup the gzip output file header.
// max filename size is arbitrarily set to 256 bytes long
// Method is always DEFLATE
// Original filename is always set in header
// timestamp is set to 0 - ignored by gunzip
// deflate flags set to 0
// OS code is 0
int max_filename_sz = 256;
unsigned char *pgziphdr =
(unsigned char *)malloc(sizeof(gzip_header) + max_filename_sz);
if (!pgziphdr) {
std::cout << "pgzip header cannot be allocated\n";
return 1;
}
pgziphdr[0] = GZIP_MAGIC[0];
pgziphdr[1] = GZIP_MAGIC[1];
pgziphdr[2] = kDeflated;
pgziphdr[3] = ORIG_NAME;
// Set time in header to 0, this is ignored by gunzip.
pgziphdr[4] = 0;
pgziphdr[5] = 0;
pgziphdr[6] = 0;
pgziphdr[7] = 0;
// Deflate flags
pgziphdr[8] = 0;
// OS code is Linux in this case.
pgziphdr[9] = OS_CODE;
int ondx = 10;
const char *p = original_filename.c_str();
do {
pgziphdr[ondx++] = (*p);
} while (*p++);
int header_bytes = ondx;
unsigned char prolog[8];
PutUlong(((unsigned char *)prolog), buffer_crc);
PutUlong(((unsigned char *)&prolog[4]), ilen);
FILE *fo = fopen(out_filename.c_str(), "w+");
if (ferror(fo)) {
std::cout << "Cannot open file for output: " << out_filename << "\n";
free(pgziphdr);
return 1;
}
fwrite(pgziphdr, 1, header_bytes, fo);
fwrite(obuf, 1, blen, fo);
fwrite(prolog, 1, 8, fo);
if (ferror(fo)) {
std::cout << "gzip output file write failure.\n";
free(pgziphdr);
return 1;
}
if (fclose(fo)) {
perror("close");
free(pgziphdr);
return 1;
}
free(pgziphdr);
return 0;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/kernels.hpp | #ifndef __KERNELS_H__
#define __KERNELS_H__
#pragma once
#ifndef NUM_ENGINES
#define NUM_ENGINES 1
#endif
// BATCH_SIZE is the number of input files the kernel should be capable of
// compressing per invocation of the GZIP engine. This is a compile time
// constant so that hardware is built to support this number. To ensure maximum
// throughput, the minimum batch size should be chosen to cover the latency of
// re-launching the gzip engine, which requires some experimentation on the
// given system. The maximum batch size should be chosen to ensure the gzip
// engine completes execution within the desired execution time (also considered
// the latency to the receive the compile result).
#ifdef FPGA_SIMULATOR
constexpr int BATCH_SIZE = 1;
#else
constexpr int BATCH_SIZE = 12;
#endif
constexpr int kNumEngines = NUM_ENGINES;
constexpr int kCRCIndex = 0;
constexpr int kLZReductionIndex = 1;
constexpr int kStaticHuffmanIndex = 2;
// kVecPow == 2 means kVec == 4.
// kVecPow == 3 means kVec == 8.
// kVecPow == 4 means kVec == 16.
constexpr int kVecPow = 4;
constexpr int kVec = 1 << kVecPow;
constexpr int kVecX2 = 2 * kVec;
constexpr int kHufTableSize = 256;
// Maximum length of huffman codes
constexpr int kMaxHuffcodeBits = 16;
struct Uint2Gzip {
unsigned int y;
unsigned int x;
};
struct LzInput {
unsigned char data[kVec];
};
typedef struct char_arr_32 {
unsigned char arr[32];
} char_arr_32;
typedef struct DistLen {
unsigned char data[kVec];
char len[kVec];
short dist[kVec];
} DistLen, *pdist_len_t;
struct HuffmanOutput {
unsigned int data[kVec];
bool write;
};
struct TrailingOutput {
int bytecount_left;
int bytecount;
unsigned char bytes[kVec * sizeof(unsigned int)];
};
struct GzipOutInfo {
// final compressed block size
size_t compression_sz;
unsigned long crc;
};
// kLen must be == kVec
constexpr int kLen = kVec;
// depth of the dictionary buffers
constexpr int kDepth = 512;
// Assumes kDepth is a power of 2 number.
constexpr int kHashMask = kDepth - 1;
#define CONSTANT __constant
constexpr int kDebug = 1;
#define TRACE(x) \
do { \
if (kDebug) printf x; \
} while (0)
constexpr int kStaticTrees = 1;
typedef struct CtData {
unsigned short code;
unsigned short len;
} CtData;
constexpr int kMaxMatch = 258;
constexpr int kMinMatch = 3;
constexpr int kTooFar = 4096;
// All codes must not exceed kMaxBits
constexpr int kMaxBits = 15;
// number of length codes, not counting the special kEndBlock code
constexpr int kLengthCodes = 29;
// number of literal bytes, 0..255
constexpr int kLiterals = 256;
// end of literal code block
constexpr int kEndBlock = 256;
// number of literal or length codes, including kEndBlock
constexpr int kLCodes = (kLiterals + 1 + kLengthCodes);
// number of distance codes
constexpr int kDCodes = 30;
// number of codes used to transfer the bit lengths
constexpr int kBLCodes = 19;
constexpr int kMaxDistance = ((32 * 1024));
constexpr int kMinBufferSize = 16384;
struct DictString {
unsigned char s[kLen];
};
// Mapping from a distance to a distance code. dist is the distance - 1 and
// must not have side effects. dist_code[256] and dist_code[257] are never
// used.
#define d_code(dist) \
((dist) < 256 ? dist_code[dist] : dist_code[256 + ((dist) >> 7)])
#endif //__KERNELS_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CompareGzip.cpp | #include "CompareGzip.hpp"
#include <sys/stat.h>
// returns 0 on success, otherwise failure
int CompareGzipFiles(
const std::string
&original_file, // original input file to compare gzip uncompressed
const std::string &input_gzfile) // gzip file to check
{
#ifdef _MSC_VER
std::cout
<< "Info: skipping output verification on Windows, no builtin gunzip\n";
return 0;
#else
//------------------------------------------------------------------
// assume all good to start with.
int gzipstatus = 0;
//------------------------------------------------------------------
// Create temporary output filename for gunzip
char tmp_name[] = "/tmp/gzip_fpga.XXXXXX";
mode_t mask = umask(S_IXUSR);
mkstemp(tmp_name);
umask(mask);
std::string outputfile = tmp_name;
//------------------------------------------------------------------
// Check that the original file and gzipped file exist.
//------------------------------------------------------------------
// gunzip the file produced to stdout, capturing to the temp file.
std::string cmd = "gunzip -c ";
cmd += input_gzfile;
cmd += " > " + outputfile;
int gzout = ::system(cmd.c_str());
if (gzout != 0) {
gzipstatus = 3;
}
//------------------------------------------------------------------
// diff the temp file and the original.
cmd = "diff -q " + outputfile + " " + original_file;
int diffout = ::system(cmd.c_str());
if (diffout != 0) {
gzipstatus = 4;
}
//------------------------------------------------------------------
// Cleanup, remove the temp file.
(void)::remove(outputfile.c_str());
return gzipstatus;
#endif
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel.hpp | #ifndef __GZIPKERNEL_H__
#define __GZIPKERNEL_H__
#pragma once
#include <sycl/sycl.hpp>
using namespace sycl;
extern "C" void SubmitGzipTasks(
queue &sycl_device,
size_t block_size, // size of block to compress.
buffer<char, 1> *pibuf, buffer<char, 1> *pobuf,
buffer<struct GzipOutInfo, 1> *gzip_out_buf,
buffer<unsigned, 1> *current_crc, bool last_block, event &e_crc,
event &e_lz, event &e_huff, size_t engineID);
#endif //__GZIPKERNEL_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel_ll.cpp | /*
** Batching **
This is the "low-latency" variant of the GZIP reference design. It differs
from the "high-bandwidth" variant in that it tries to minimize the latency
from when the input file is available in host memory to when the compressed
result is available in host memory, particulary for small (< 128KB) input
files. Universal Shared Memory (USM) is used to reduce latency whereby the
kernel directly accesses the input/output buffers, physically located in host
memory. This is in contrast to the "high bandwidth" variant where SYCL Buffers
are DMA'ed to/from the FPGA's attached DDR. USM instead allows for a "zero
copy" design, which reduces overall latency. It takes some time to relaunch
the gzip engine and therefore, in order to maximize system throughput, it's
important to feed the gzip engine with enough data to keep it busy while the
next launch is being prepared. If done successfully, the kernel relaunch time
overlaps with kernel execution and there is very little downtime between
kernel invocations. Since this reference design is intended to be used with
small files, it's typical that one file is not enough to keep the engine busy.
Therefore the concept of "batching" is introduced. This simply means that the
gzip engine compresses multiple input files, per invocation. The minimum size
of the batch should be chosen to cover the relaunch latency and the maximum
size should be chosen to result in a desireable overall execution time (i.e. a
large batch size may take longer than desired to execute, thereby elongating
overall system latency). Determining the proper batch size takes some
experimentation.
The 3 kernels that comprise the gzip engine are separated into separate
functions. Each function contains a "batch loop" which simply iterates over
the kernel code, once per file in the batch. The batch loop has loop
pipelining disabled. This is a clear way to communicate to the compiler that
files in the batch are independent from each other. This means there's a
little bit of ramp-down/up of the batch loop between files. It's possible to
pipeline the batch loop to slightly improve performance, at the cost of area
(all variables in the loop become privatized and copied).
The pointers to the buffers in a batch are passed to the kernel via kernel
args. By having separate kernel arguments for each pointer we are able to
clearly communicate to the compiler that these pointers should be treated as
'restrict' (i.e. they will not point to the same place, which is true in this
application). An alternative implementation to store an array of pointers in
host-memory which the kernel then reads, but this makes it more difficult to
communicate that these pointers don't alias.
*/
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <vector>
#include "gzipkernel_ll.hpp"
#include "kernels.hpp"
#include "pipe_utils.hpp" // Included from DirectProgramming/C++SYCL_FPGA/include/
using namespace sycl;
// Pipes, for inter-kernel data transfer..
using acc_dist_channel_array =
fpga_tools::PipeArray< // Defined in "pipe_utils.hpp".
class dist_channel_pipe_id, // An identifier for the pipe.
struct DistLen, // The type of data in the pipe.
32, // The capacity of each pipe.
NUM_ENGINES // array dimension.
>;
using acc_dist_channel_last_array =
fpga_tools::PipeArray<
class dist_channel_last_pipe_id,
struct DistLen,
32,
NUM_ENGINES
>;
using acc_lz_to_crc_channel_array =
fpga_tools::PipeArray<
class crc_channel_pipe_id,
char_arr_32,
32,
NUM_ENGINES
>;
template <int Begin, int End>
struct Unroller {
template <typename Action>
static void step(const Action &action) {
action(std::integral_constant<int, Begin>());
Unroller<Begin + 1, End>::step(action);
}
};
template <int End>
struct Unroller<End, End> {
template <typename Action>
static void step(const Action &action) {}
};
int GetHuffLiteralBits(unsigned char ch) {
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
return static_ltree[ch].code;
}
int GetHuffLiteralLen(unsigned char ch) {
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
return static_ltree[ch].len;
}
int GetHuffRunLen(int _len, int _dist) {
int lc;
unsigned code;
int extra;
int dist;
//int local_lbits;
int local_llen;
//int local_dbits;
int local_dlen;
//local_lbits = 0;
local_llen = 0;
int base_length[kLengthCodes] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24,
28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 0,
};
int extra_lbits[kLengthCodes] // extra bits for each length code
= {0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0};
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
// distance codes. The first 256 values correspond to the distances
// 3 .. 258, the last 256 values correspond to the top 8 bits of
// the 15 bit distances.
unsigned char dist_code[512] = {
0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8,
8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 0, 0, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 21, 21,
21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29,
};
// length code for each normalized match length (0 == kMinMatch)
unsigned char length_code[kMaxMatch - kMinMatch + 1] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12,
12, 12, 13, 13, 13, 13, 14, 14, 14, 14, 15, 15, 15, 15, 16, 16, 16, 16,
16, 16, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18,
18, 18, 19, 19, 19, 19, 19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21,
21, 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23,
23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 28,
};
int extra_dbits[kDCodes] // extra bits for each distance code
= {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6,
6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13};
int base_dist[kDCodes] = {
0, 1, 2, 3, 4, 6, 8, 12, 16, 24,
32, 48, 64, 96, 128, 192, 256, 384, 512, 768,
1024, 1536, 2048, 3072, 4096, 6144, 8192, 12288, 16384, 24576,
};
CtData static_dtree[kDCodes] = {
{0, 5}, {16, 5}, {8, 5}, {24, 5}, {4, 5}, {20, 5}, {12, 5}, {28, 5},
{2, 5}, {18, 5}, {10, 5}, {26, 5}, {6, 5}, {22, 5}, {14, 5}, {30, 5},
{1, 5}, {17, 5}, {9, 5}, {25, 5}, {5, 5}, {21, 5}, {13, 5}, {29, 5},
{3, 5}, {19, 5}, {11, 5}, {27, 5}, {7, 5}, {23, 5},
};
lc = _len - kMinMatch;
code = length_code[lc];
//local_lbits = static_ltree[code + kLiterals + 1].code;
local_llen = static_ltree[code + kLiterals + 1].len;
extra = extra_lbits[code];
if (extra) {
lc -= base_length[code];
//local_lbits |= lc << local_llen;
local_llen += extra;
}
dist = _dist;
dist--;
code = d_code(dist);
//local_dbits = static_dtree[code].code;
local_dlen = static_dtree[code].len;
extra = extra_dbits[code];
if (extra) {
dist -= base_dist[code];
//local_dbits |= dist << local_dlen;
local_dlen += extra;
}
//local_lbits |= local_dbits << local_llen;
local_llen += local_dlen;
return local_llen;
}
int GetHuffRunBits(int _len, int _dist) {
int lc;
unsigned code;
int extra;
int dist;
int local_lbits, local_llen;
int local_dbits, local_dlen;
local_lbits = 0;
local_llen = 0;
int base_length[kLengthCodes] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24,
28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 0,
};
int extra_lbits[kLengthCodes] // extra bits for each length code
= {0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0};
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
// distance codes. The first 256 values correspond to the distances
// 3 .. 258, the last 256 values correspond to the top 8 bits of
// the 15 bit distances.
unsigned char dist_code[512] = {
0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8,
8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 0, 0, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 21, 21,
21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29,
};
// length code for each normalized match length (0 == kMinMatch)
unsigned char length_code[kMaxMatch - kMinMatch + 1] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12,
12, 12, 13, 13, 13, 13, 14, 14, 14, 14, 15, 15, 15, 15, 16, 16, 16, 16,
16, 16, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18,
18, 18, 19, 19, 19, 19, 19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21,
21, 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23,
23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 28,
};
int extra_dbits[kDCodes] // extra bits for each distance code
= {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6,
6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13};
int base_dist[kDCodes] = {
0, 1, 2, 3, 4, 6, 8, 12, 16, 24,
32, 48, 64, 96, 128, 192, 256, 384, 512, 768,
1024, 1536, 2048, 3072, 4096, 6144, 8192, 12288, 16384, 24576,
};
CtData static_dtree[kDCodes] = {
{0, 5}, {16, 5}, {8, 5}, {24, 5}, {4, 5}, {20, 5}, {12, 5}, {28, 5},
{2, 5}, {18, 5}, {10, 5}, {26, 5}, {6, 5}, {22, 5}, {14, 5}, {30, 5},
{1, 5}, {17, 5}, {9, 5}, {25, 5}, {5, 5}, {21, 5}, {13, 5}, {29, 5},
{3, 5}, {19, 5}, {11, 5}, {27, 5}, {7, 5}, {23, 5},
};
lc = _len - kMinMatch;
code = length_code[lc];
local_lbits = static_ltree[code + kLiterals + 1].code;
local_llen = static_ltree[code + kLiterals + 1].len;
extra = extra_lbits[code];
if (extra) {
lc -= base_length[code];
local_lbits |= lc << local_llen;
local_llen += extra;
}
dist = _dist;
dist--;
code = d_code(dist);
local_dbits = static_dtree[code].code;
local_dlen = static_dtree[code].len;
extra = extra_dbits[code];
if (extra) {
dist -= base_dist[code];
local_dbits |= dist << local_dlen;
local_dlen += extra;
}
local_lbits |= local_dbits << local_llen;
local_llen += local_dlen;
return local_lbits;
}
int GetHuffLen(int len, int dist, unsigned char ch) {
int returned_len;
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
switch (len) {
case -3:
returned_len = static_ltree[kEndBlock].len;
break;
case -2:
returned_len = 3;
break;
case -1:
returned_len = 0;
break;
case 0:
returned_len = GetHuffLiteralLen(ch);
break;
default:
returned_len = GetHuffRunLen(len, dist);
break;
}
return returned_len;
}
int IsValid(int len, int dist, unsigned char ch) {
switch (len) {
case -3:
return 1;
case -2:
return 1;
case -1:
return 0;
case 0:
return 1;
default:
return 1;
}
}
int GetHuffBits(int len, int dist, unsigned char ch) {
int bits;
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
switch (len) {
case -3:
bits = static_ltree[kEndBlock].code;
break;
case -2:
bits = ch;
break;
case -1:
bits = 0;
break;
case 0:
bits = GetHuffLiteralBits(ch);
break;
default:
bits = GetHuffRunBits(len, dist);
break;
}
return bits;
}
// assembles up to kVecX2 unsigned char values based on given huffman encoding
// writes up to kMaxHuffcodeBits * kVecX2 bits to memory
bool HufEnc(char *len, short *dist, unsigned char *data, unsigned int *outdata,
unsigned int *leftover, unsigned short *leftover_size) {
// array that contains the bit position of each symbol
unsigned short bitpos[kVec + 1];
bitpos[0] = 0;
Unroller<0, kVec>::step([&](int i) {
bitpos[i + 1] = bitpos[i] + (IsValid(len[i], dist[i], data[i])
? GetHuffLen(len[i], dist[i], data[i])
: 0);
});
// leftover is an array that carries huffman encoded data not yet written to
// memory adjust leftover_size with the number of bits to write this time
unsigned short prev_cycle_offset = *leftover_size;
*leftover_size += (bitpos[kVec] & 0x3fff);
// we'll write this cycle if we have collected enough data (kVec shorts or
// more)
bool write = *leftover_size & (kVec * (kMaxHuffcodeBits * 2));
// subtract kVec shorts from leftover size (if it's bigger
// than kVec) because we'll write those out this cycle
*leftover_size &= ~(kVec * (kMaxHuffcodeBits * 2));
// Adjust bitpos based on leftover offset from previous cycle
Unroller<0, kVec>::step(
[&](int i) { bitpos[i] += (prev_cycle_offset & 0x3fff); });
// Huffman codes have any bit alignement, so they can spill
// onto two shorts in the output array
// use ushort2 to keep each part of the code separate
// Iterate over all codes and construct ushort2 containing
// the code properly aligned
struct Uint2Gzip code[kVec];
Unroller<0, kVec>::step([&](int i) {
code[i].x = 0;
code[i].y = 0;
});
Unroller<0, kVec>::step([&](int i) {
// Codes can be more than 16 bits, so use uint32
unsigned int curr_code = GetHuffBits(len[i], dist[i], data[i]);
unsigned char bitpos_in_short = bitpos[i] & 0x01F;
unsigned long long temp = (unsigned long long)curr_code << bitpos_in_short;
unsigned int temp1 = (unsigned int)temp;
unsigned int temp2 = temp >> 32ULL;
if (IsValid(len[i], dist[i], data[i])) {
code[i].x = temp1;
code[i].y = temp2;
} else {
code[i].x = temp1;
code[i].y = temp2;
}
});
// Iterate over all destination locations and gather the required data
unsigned int new_leftover[kVec];
Unroller<0, kVec>::step([&](int i) {
new_leftover[i] = 0;
outdata[i] = 0;
Unroller<0, kVec>::step([&](int j) {
// figure out whether code[j] goes into bucket[i]
bool match_first = ((bitpos[j] >> 5) & (kVec - 1)) == i;
bool match_second =
((bitpos[j] >> 5) & (kVec - 1)) == ((i - 1) & (kVec - 1));
// if code[j] maps onto current bucket then OR its code, else OR with 0
unsigned int component =
match_first ? code[j].x : (match_second ? code[j].y : 0);
// overflow from kVec shorts, need to move onto new_leftover
bool use_later =
(bitpos[j] & (kVec * (kMaxHuffcodeBits * 2))) ||
(match_second && (((bitpos[j] >> 5) & (kVec - 1)) == kVec - 1));
// write to output
outdata[i] |= use_later ? 0 : component;
new_leftover[i] |= use_later ? component : 0;
});
});
// Apply previous leftover on the outdata
// Also, if didn't write, apply prev leftover onto newleftover
Unroller<0, kVec>::step([&](int i) {
outdata[i] |= leftover[i];
leftover[i] = outdata[i];
});
// HACK: split unroll into two unrolls to avoid compiler crash
if (write) {
Unroller<0, kVec>::step([&](int i) { leftover[i] = new_leftover[i]; });
}
return write;
}
// Helper, for accessing the parameter pack
template <int target, typename CurrentAccessor, typename... AccessorTys>
auto get(CurrentAccessor &accessor, AccessorTys &... Args) {
if constexpr (target == 0)
return accessor;
else
return get<target - 1>(Args...);
}
template <int engineID>
class CRC;
template <int engineID, int BatchSize>
event SubmitCRC(queue &q, size_t block_size, uint32_t *result_crc,
std::vector<event> &depend_on) {
event e = q.submit([&](handler &h) {
if (!depend_on.empty()) {
h.depends_on(depend_on[kCRCIndex]);
}
h.single_task<CRC<engineID>>([=]() [[intel::kernel_args_restrict]] {
auto accessor_isz = block_size;
host_ptr<uint32_t> accresult_crc(result_crc);
// See comments at top of file, regarding batching.
[[intel::disable_loop_pipelining]]
for (int iter=0;iter<BatchSize;iter++) {
const unsigned int table64[64][16] = {
{
0x0,
0xf1da05aa,
0x38c50d15,
0xc91f08bf,
0x718a1a2a,
0x80501f80,
0x494f173f,
0xb8951295,
0xe3143454,
0x12ce31fe,
0xdbd13941,
0x2a0b3ceb,
0x929e2e7e,
0x63442bd4,
0xaa5b236b,
0x5b8126c1,
},
{
0x0,
0x1d596ee9,
0x3ab2ddd2,
0x27ebb33b,
0x7565bba4,
0x683cd54d,
0x4fd76676,
0x528e089f,
0xeacb7748,
0xf79219a1,
0xd079aa9a,
0xcd20c473,
0x9faeccec,
0x82f7a205,
0xa51c113e,
0xb8457fd7,
},
{
0x0,
0xee7e8d1,
0x1dcfd1a2,
0x13283973,
0x3b9fa344,
0x35784b95,
0x265072e6,
0x28b79a37,
0x773f4688,
0x79d8ae59,
0x6af0972a,
0x64177ffb,
0x4ca0e5cc,
0x42470d1d,
0x516f346e,
0x5f88dcbf,
},
{
0x0,
0xee7e8d10,
0x78c1c61,
0xe9f29171,
0xf1838c2,
0xe166b5d2,
0x89424a3,
0xe6eaa9b3,
0x1e307184,
0xf04efc94,
0x19bc6de5,
0xf7c2e0f5,
0x11284946,
0xff56c456,
0x16a45527,
0xf8dad837,
},
{
0x0,
0x3c60e308,
0x78c1c610,
0x44a12518,
0xf1838c20,
0xcde36f28,
0x89424a30,
0xb522a938,
0x38761e01,
0x416fd09,
0x40b7d811,
0x7cd73b19,
0xc9f59221,
0xf5957129,
0xb1345431,
0x8d54b739,
},
{
0x0,
0x70ec3c02,
0xe1d87804,
0x91344406,
0x18c1f649,
0x682dca4b,
0xf9198e4d,
0x89f5b24f,
0x3183ec92,
0x416fd090,
0xd05b9496,
0xa0b7a894,
0x29421adb,
0x59ae26d9,
0xc89a62df,
0xb8765edd,
},
{
0x0,
0x6307d924,
0xc60fb248,
0xa5086b6c,
0x576e62d1,
0x3469bbf5,
0x9161d099,
0xf26609bd,
0xaedcc5a2,
0xcddb1c86,
0x68d377ea,
0xbd4aece,
0xf9b2a773,
0x9ab57e57,
0x3fbd153b,
0x5cbacc1f,
},
{
0x0,
0x86c88d05,
0xd6e01c4b,
0x5028914e,
0x76b13ed7,
0xf079b3d2,
0xa051229c,
0x2699af99,
0xed627dae,
0x6baaf0ab,
0x3b8261e5,
0xbd4aece0,
0x9bd34379,
0x1d1bce7c,
0x4d335f32,
0xcbfbd237,
},
{
0x0,
0x1b5fd1d,
0x36bfa3a,
0x2de0727,
0x6d7f474,
0x7620969,
0x5bc0e4e,
0x409f353,
0xdafe8e8,
0xc1a15f5,
0xec412d2,
0xf71efcf,
0xb781c9c,
0xacde181,
0x813e6a6,
0x9a61bbb,
},
{
0x0,
0x1b5fd1d0,
0x36bfa3a0,
0x2de07270,
0x6d7f4740,
0x76209690,
0x5bc0e4e0,
0x409f3530,
0xdafe8e80,
0xc1a15f50,
0xec412d20,
0xf71efcf0,
0xb781c9c0,
0xacde1810,
0x813e6a60,
0x9a61bbb0,
},
{
0x0,
0x6e8c1b41,
0xdd183682,
0xb3942dc3,
0x61416b45,
0xfcd7004,
0xbc595dc7,
0xd2d54686,
0xc282d68a,
0xac0ecdcb,
0x1f9ae008,
0x7116fb49,
0xa3c3bdcf,
0xcd4fa68e,
0x7edb8b4d,
0x1057900c,
},
{
0x0,
0x5e74ab55,
0xbce956aa,
0xe29dfdff,
0xa2a3ab15,
0xfcd70040,
0x1e4afdbf,
0x403e56ea,
0x9e36506b,
0xc042fb3e,
0x22df06c1,
0x7cabad94,
0x3c95fb7e,
0x62e1502b,
0x807cadd4,
0xde080681,
},
{
0x0,
0xe71da697,
0x154a4b6f,
0xf257edf8,
0x2a9496de,
0xcd893049,
0x3fdeddb1,
0xd8c37b26,
0x55292dbc,
0xb2348b2b,
0x406366d3,
0xa77ec044,
0x7fbdbb62,
0x98a01df5,
0x6af7f00d,
0x8dea569a,
},
{
0x0,
0xaa525b78,
0x8fd5b0b1,
0x2587ebc9,
0xc4da6723,
0x6e883c5b,
0x4b0fd792,
0xe15d8cea,
0x52c5c807,
0xf897937f,
0xdd1078b6,
0x774223ce,
0x961faf24,
0x3c4df45c,
0x19ca1f95,
0xb39844ed,
},
{
0x0,
0xa58b900e,
0x9066265d,
0x35edb653,
0xfbbd4afb,
0x5e36daf5,
0x6bdb6ca6,
0xce50fca8,
0x2c0b93b7,
0x898003b9,
0xbc6db5ea,
0x19e625e4,
0xd7b6d94c,
0x723d4942,
0x47d0ff11,
0xe25b6f1f,
},
{
0x0,
0x5817276e,
0xb02e4edc,
0xe83969b2,
0xbb2d9bf9,
0xe33abc97,
0xb03d525,
0x5314f24b,
0xad2a31b3,
0xf53d16dd,
0x1d047f6f,
0x45135801,
0x1607aa4a,
0x4e108d24,
0xa629e496,
0xfe3ec3f8,
},
{
0x0,
0x81256527,
0xd93bcc0f,
0x581ea928,
0x69069e5f,
0xe823fb78,
0xb03d5250,
0x31183777,
0xd20d3cbe,
0x53285999,
0xb36f0b1,
0x8a139596,
0xbb0ba2e1,
0x3a2ec7c6,
0x62306eee,
0xe3150bc9,
},
{
0x0,
0x7f6b7f3d,
0xfed6fe7a,
0x81bd8147,
0x26dcfab5,
0x59b78588,
0xd80a04cf,
0xa7617bf2,
0x4db9f56a,
0x32d28a57,
0xb36f0b10,
0xcc04742d,
0x6b650fdf,
0x140e70e2,
0x95b3f1a5,
0xead88e98,
},
{
0x0,
0x9b73ead4,
0xed96d3e9,
0x76e5393d,
0x5ca193,
0x9b2f4b47,
0xedca727a,
0x76b998ae,
0xb94326,
0x9bcaa9f2,
0xed2f90cf,
0x765c7a1b,
0xe5e2b5,
0x9b960861,
0xed73315c,
0x7600db88,
},
{
0x0,
0x172864c,
0x2e50c98,
0x3978ad4,
0x5ca1930,
0x4b89f7c,
0x72f15a8,
0x65d93e4,
0xb943260,
0xae6b42c,
0x9713ef8,
0x803b8b4,
0xe5e2b50,
0xf2cad1c,
0xcbb27c8,
0xdc9a184,
},
{
0x0,
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{
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const int num_nibbles_parallel = 64;
// this section of code should be on the hardware accelerator
const int num_sections =
accessor_isz /
(num_nibbles_parallel / 2); // how many loop iterations
unsigned int result = ~0;
char_arr_32 input_data;
for (int i = 0; i < num_sections; i++) { // Iterate over 32 byte sections)
unsigned int result_update_odd = 0;
unsigned int result_update_even = 0;
// The input file data is read by the LZ kernel and transferred here
// via a pipe.
input_data = acc_lz_to_crc_channel_array::PipeAt<engineID>::read();
// which 4 bit chunk within the section -- this loop can be unrolled, the
// total update for the crc is the xor of the updates from the nibbles
#pragma unroll
for (int nib = 0; nib < num_nibbles_parallel; nib++) { // Iterate through the 32-bytes in this section
unsigned char this_input_nibble =
input_data.arr[nib / 2] >> (4 * (nib % 2));
unsigned char this_result_nibble =
(nib < 8) ? (result >> (4 * nib)) : 0;
unsigned char this_table_index =
this_input_nibble ^ this_result_nibble;
if (nib % 2) {
result_update_odd ^= table64[nib][this_table_index & 0xf];
} else {
result_update_even ^= table64[nib][this_table_index & 0xf];
}
}
result = result_update_odd ^ result_update_even;
}
// Read and discard final data
input_data = acc_lz_to_crc_channel_array::PipeAt<engineID>::read();
accresult_crc[iter] = ~result;
}
});
});
return e;
}
template <int engineID>
class LZReduction;
template <int engineID, int BatchSize, typename... PtrTypes>
event SubmitLZReduction(queue &q, size_t block_size, bool last_block,
std::vector<event> &depend_on,
PtrTypes... ptrs) {
event e = q.submit([&](handler &h) {
auto accessor_isz = block_size;
if (!depend_on.empty()) {
h.depends_on(depend_on[kLZReductionIndex]);
}
h.single_task<LZReduction<engineID>>([=]() [[intel::kernel_args_restrict]] {
// Unpack the ptrs parameter pack and grab all of the pointers, annotating
// them as USM host pointers.
// To avoid calling the default constructors and having two stores to
// 'host_pibuf' (and therefore forcing it to a memory), we can create
// an initializer list by expanding our pack. It's the same logic as in
// SubmitGzipTasksHelper(); everything to the left of '...' is expanded
// for each value in ptrs.
host_ptr<char> host_pibuf[BatchSize];
Unroller<0, BatchSize>::step(
[&](auto i) { host_pibuf[i] = host_ptr<char>(get<i>(ptrs...)); });
// See comments at top of file, regarding batching
[[intel::disable_loop_pipelining]] for (int iter = 0;
iter < BatchSize; iter++) {
const int iter_masked =
iter % BatchSize; // Hint to the compiler that the access to
// host_pibuf is bounded.
host_ptr<char> acc_pibuf =
host_pibuf[iter_masked]; // Grab new host pointer on each iteration
// of the batch loop
//-------------------------------------
// Hash Table(s)
//-------------------------------------
[[intel::singlepump]] [[intel::numbanks(kVec)]] [
[intel::max_replicates(kVec)]] struct {
unsigned char s[kLen];
} dictionary[kDepth][kVec];
[[intel::singlepump]] [[intel::numbanks(kVec)]] [
[intel::max_replicates(
kVec)]] unsigned int dict_offset[kDepth][kVec];
// Initialize history to empty.
for (int i = 0; i < kDepth; i++) {
Unroller<0, kVec>::step([&](int k) { dict_offset[i][k] = 0; });
}
// This is the window of data on which we look for matches
// We fetch twice our data size because we have kVec offsets
unsigned char current_window[kVecX2];
// This is the window of data on which we look for matches
// We fetch twice our data size because we have kVec offsets
unsigned char compare_window[kLen][kVec][kVec];
// kVec bytes per dict----------| | |
// kVec dictionaries-----------------| |
// one for each curr win offset----------|
// load offset into these arrays
unsigned int compare_offset[kVec][kVec];
// one per kVec bytes----------| |
// one for each compwin--------------|
// Initialize input stream position
unsigned int inpos_minus_vec_div_16 = 0;
// this is ceiling of (insize-kVec)/16, original comparison was
// inpos < insize, now inpos is carried as (inpos-kVec)/16 so this is
// what we compare to
unsigned int insize_compare = (accessor_isz) / kVec;
int ctr = insize_compare - 1;
char first_valid_pos = 0;
struct DistLen dist_offs_data;
size_t inpos = 0;
char_arr_32 input_data; // Assumes kVec = 16 because CRC expects 2 x 16 bytes.
bool crc_ch_load_upper = true; // A flag used to form double-wide words to send to the CRC kernel.
// load in new data
struct LzInput in;
Unroller<0, kVec>::step([&](int i) {
in.data[i] = acc_pibuf[inpos++]; // Reads 16 bytes, just one time.
input_data.arr[i] =
in.data[i]; // Send a copy of the data to the CRC kernel, through
// a pipe. input_data is used to gang the data
// together into a wider word.
});
Unroller<0, kVec>::step(
[&](int i) { current_window[i + kVec] = in.data[i]; });
do {
//-----------------------------
// Prepare current window
//-----------------------------
// shift current window
Unroller<0, kVec>::step(
[&](int i) { current_window[i] = current_window[i + kVec]; });
// load in new data
Unroller<0, kVec>::step([&](int i) {
in.data[i] = acc_pibuf[inpos++];
input_data.arr[16 * (int)crc_ch_load_upper + i] = in.data[i];
});
// CRC kernel expects a wider word.
if (crc_ch_load_upper) { // After both halves are loaded, write the
// full struct to the channel
acc_lz_to_crc_channel_array::PipeAt<engineID>::write(input_data);
}
// The state of this signal indicates the next half to be loaded.
// i.e. if true, upper will be loaded next.
crc_ch_load_upper = !crc_ch_load_upper;
Unroller<0, kVec>::step(
[&](int i) { current_window[kVec + i] = in.data[i]; });
//-----------------------------
// Compute hash
//-----------------------------
unsigned short hash[kVec];
Unroller<0, kVec>::step([&](int i) {
hash[i] = (current_window[i] ^ (current_window[i + 1] << 6) ^
(current_window[i + 2] << 2) ^ current_window[i + 3]) &
kHashMask;
});
//-----------------------------
// Dictionary look-up
//-----------------------------
// loop over kVec compare windows, each has a different hash
Unroller<0, kVec>::step([&](int i) {
// loop over all kVec bytes
Unroller<0, kLen>::step([&](int j) {
Unroller<0, kVec>::step([&](int k) {
compare_window[k][j][i] = dictionary[hash[i]][j].s[k];
});
});
});
// loop over compare windows
Unroller<0, kVec>::step([&](int i) {
Unroller<0, kLen>::step([&](int j) {
// loop over frames in this compare window
// (they come from different dictionaries)
compare_offset[j][i] = dict_offset[hash[i]][j];
});
});
//-----------------------------
// Dictionary update
//-----------------------------
// loop over different dictionaries to store different frames
// store one frame per dictionary
// loop over kVec bytes to store
Unroller<0, kLen>::step([&](int i) {
Unroller<0, kVec>::step([&](int j) {
// store actual bytes
dictionary[hash[i]][i].s[j] = current_window[i + j];
});
});
Unroller<0, kVec>::step([&](int i) {
// loop over kVec different dictionaries and write one word to each
dict_offset[hash[i]][i] =
(inpos_minus_vec_div_16 << 4) |
i; // inpos - kVec + 0, we know that inpos - kVec has 0 as the
// 4 lower bits so really just concatenate
});
//-----------------------------
// Match search
//-----------------------------
// arrays to store length, best length etc..
unsigned char length[kVec];
bool done[kVec];
char best_length[kVec];
unsigned int best_offset[kVec];
// initialize best_length
Unroller<0, kVec>::step([&](int i) {
best_length[i] = 0;
best_offset[i] = 0;
});
// loop over each comparison window frame
// one comes from each dictionary
Unroller<0, kVec>::step([&](int i) {
// initialize length and done
Unroller<0, kVec>::step([&](int l) {
length[l] = 0;
done[l] = 0;
});
// loop over each current window
Unroller<0, kVec>::step([&](int j) {
// loop over each char in the current window
// and corresponding char in comparison window
Unroller<0, kLen>::step([&](int k) {
bool comp = current_window[k + j] == compare_window[k][i][j] &&
!done[j];
length[j] += comp;
done[j] = !comp;
});
});
// Check if this the best length
Unroller<0, kVec>::step([&](int m) {
bool update_best =
(length[m] > best_length[m]) && (compare_offset[i][m] != 0) &&
(((inpos_minus_vec_div_16 << kVecPow) | (i & (kVec - 1))) -
(compare_offset[i][m]) <
kMaxDistance);
unsigned int new_offset =
(((inpos_minus_vec_div_16 << kVecPow) | (m & (kVec - 1))) &
0x7ffff) -
((compare_offset[i][m] & 0x7ffff));
// Reconsider if new_offset is bigger than current offset, might
// take more bytes to encode
update_best = update_best && (length[m] == best_length[m]) &&
(new_offset > best_offset[m])
? false
: update_best;
best_offset[m] = (update_best ? new_offset : best_offset[m]) &
0x7ffff; // 19 bits is sufficient
best_length[m] = (update_best ? length[m] : best_length[m]) &
0x1f; // 5 bits is sufficient
});
});
//-----------------------------
// Filter matches step 1
//-----------------------------
// remove matches with offsets that are <= 0: this means they're
// self-matching or didn't match and keep only the matches that, when
// encoded, take fewer bytes than the actual match length
Unroller<0, kVec>::step([&](int i) {
best_length[i] = (((best_length[i] & 0x1f) >= 3) &&
((best_offset[i]) < kMaxDistance)
? best_length[i]
: 0) &
0x1f; // 5 bits is sufficient
// Second level filter - remove matches with len 3, greater than
// kTooFar
best_length[i] =
(((best_length[i] & 0x1f) == 3) && ((best_offset[i]) > kTooFar)
? 0
: best_length[i]) &
0x1f; // 5 bits is sufficient
// don't emmit matches for last iteration as some of the
// second part of the window might be undefined
if (ctr == 0) best_length[i] = 0;
});
//-----------------------------
// Assign first_valid_pos
//-----------------------------
// first_valid_pos is loop-carried, and tricky to compute. So first
// compute it speculatively in parallel for every possible value of
// the previous first_valid_pos.
char first_valid_pos_speculative[kVec];
Unroller<0, kVec>::step([&](int guess) {
unsigned char next_match_search = guess;
Unroller<0, kVec>::step([&](int i) {
unsigned int len = best_length[i];
// Skip to the next match
next_match_search = i >= next_match_search && len > 0
? i + len
: next_match_search;
});
first_valid_pos_speculative[guess] =
next_match_search - kVec > 0 ? next_match_search - kVec : 0;
});
// For kVec=16 (the largest currently supported), this should be a
// 16:1 mux, which is 2 6LUTs deep. For larger kVec, it will be
// worse.
unsigned char current_valid_pos = first_valid_pos;
first_valid_pos =
first_valid_pos_speculative[first_valid_pos & (kVec - 1)] &
(kVec -
1); // first_valid_pos only needs 4 bits, make this explicit
// greedy match selection
Unroller<0, (kVec)>::step([&](int i) {
unsigned int len = best_length[i];
best_length[i] = i < current_valid_pos ? -1 : best_length[i];
// Skip to the next match
current_valid_pos =
i >= current_valid_pos && len > 0 ? i + len : current_valid_pos;
});
//-----------------------------
// Setup LZ dist/len pairs to push to Huffman encode kernel
//-----------------------------
Unroller<0, kVec>::step([&](int i) {
dist_offs_data.data[i] = 0;
dist_offs_data.len[i] = -1;
dist_offs_data.dist[i] = -1;
if (best_length[i] >= 0) {
dist_offs_data.data[i] = current_window[i];
dist_offs_data.len[i] = best_length[i];
dist_offs_data.dist[i] = best_offset[i];
}
});
// acc_dist_channel::write(dist_offs_data);
acc_dist_channel_array::PipeAt<engineID>::write(dist_offs_data);
// increment input position
inpos_minus_vec_div_16++;
ctr--;
} while (ctr >= 0);
// If crc_ch_load_upper==true, then upper was to be loaded next, meaning
// lower has been loaded. So write out this partial struct.
if (crc_ch_load_upper) {
acc_lz_to_crc_channel_array::PipeAt<engineID>::write(input_data);
}
const char lasti = accessor_isz - (accessor_isz & ~(kVec - 1));
const char firstpos = first_valid_pos;
Unroller<0, kVec>::step([&](unsigned char i) {
dist_offs_data.data[i] = 0;
dist_offs_data.len[i] = -1;
dist_offs_data.dist[i] = -1;
});
Unroller<0, kVec>::step([&](unsigned char i) {
bool pred =
((i - firstpos) < (lasti - firstpos)) && ((i - firstpos) >= 0);
dist_offs_data.data[i] = pred ? current_window[i + kVec] : 0;
dist_offs_data.len[i] = pred ? 0 : -1;
});
acc_dist_channel_last_array::PipeAt<engineID>::write(dist_offs_data);
}
});
});
return e;
}
template <int engineID>
class StaticHuffman;
template <int engineID, int BatchSize, typename... PtrTypes>
event SubmitStaticHuffman(queue &q, size_t block_size,
struct GzipOutInfo *gzip_out_buf, bool last_block,
std::vector<event> &depend_on,
PtrTypes... ptrs) {
event e = q.submit([&](handler &h) {
if (!depend_on.empty()) {
h.depends_on(depend_on[kStaticHuffmanIndex]);
}
h.single_task<StaticHuffman<engineID>>([=]() [[intel::kernel_args_restrict]] {
// See comments in SubmitLZReduction, where the same parameter unpacking
// is done.
host_ptr<char> host_pobuf[BatchSize];
Unroller<0, BatchSize>::step(
[&](auto i) { host_pobuf[i] = host_ptr<char>(get<i>(ptrs...)); });
auto accessor_isz = block_size;
host_ptr<GzipOutInfo> acc_gzip_out(gzip_out_buf);
auto acc_eof = last_block ? 1 : 0;
// See comments at top of file regarding batching.
[[intel::disable_loop_pipelining]]
for (int iter=0; iter < BatchSize; iter++) {
host_ptr<char> accessor_output = host_pobuf[iter % BatchSize];
unsigned int leftover[kVec] = {0};
Unroller<0, kVec>::step([&](int i) { leftover[i] = 0; });
unsigned short leftover_size = 0;
unsigned int outpos_huffman = 0;
int ctr = ((accessor_isz) / kVec) + 2;
int odx = 0;
// Add the gzip start block marker. Assumes static huffman trees.
leftover_size = 3;
leftover[0] = ((kStaticTrees << 1) + (acc_eof));
do {
struct DistLen in;
// init the input structure for the gzip end block marker.
// this is the very last data block to be encoded and written.
Unroller<0, kVec>::step([&](int i) {
in.len[i] = -1;
in.dist[i] = -1;
in.data[i] = 0;
});
in.len[0] = ctr == 1 ? -3 : -1;
in.data[0] = 0;
in =
ctr > 2
? acc_dist_channel_array::PipeAt<engineID>::read()
: (ctr == 2
? acc_dist_channel_last_array::PipeAt<engineID>::read()
: in);
struct HuffmanOutput outdata;
outdata.write = HufEnc(in.len, in.dist, in.data, outdata.data,
leftover, &leftover_size);
// prevent out of bounds write
if (((ctr == 0) || outdata.write) && (odx < accessor_isz)) {
Unroller<0, kVec * sizeof(unsigned int)>::step([&](int i) {
accessor_output[odx + i] =
(ctr == 0) ? (unsigned char)(leftover[(i >> 2) & 0xf] >>
((i & 3) << 3))
: (unsigned char)(outdata.data[(i >> 2) & 0xf] >>
((i & 3) << 3));
});
}
outpos_huffman = outdata.write ? outpos_huffman + 1 : outpos_huffman;
odx += outdata.write ? (sizeof(unsigned int) << kVecPow) : 0;
} while (ctr--);
// Store summary values from lz and huffman
acc_gzip_out[iter].compression_sz =
(outpos_huffman * sizeof(unsigned int) * kVec) +
(leftover_size + 7) / 8;
}
});
});
return e;
}
// Helper function to launch the individual kernels that comprise the gzip
// engine. Templated on engineID to allow creation of multiple engines.
// Templated on BatchSize to specify, at compile time, the batch size for which
// hardware should be built.
// And templated on a pack of PtrTypes (which we know will be char*).
template <int engineID, int BatchSize, std::size_t... Indices>
std::vector<event> SubmitGzipTasksHelper(queue &q, size_t block_size,
struct GzipOutInfo *gzip_out_buf,
uint32_t *result_crc, bool last_block,
std::vector<event> &depend_on,
std::array<char *, BatchSize> in_ptrs,
std::array<char *, BatchSize> out_ptrs,
std::index_sequence<Indices...>) {
// A parameter pack is used for passing a batch of pointers (i.e. pointers to
// the input/output buffers in host-memory).
// submit the LZReductionKernel
// The '...' operator essentially says this: Take the pattern connected
// to the '...' (in this case, 'in_ptrs[Indices]') and replicate it
// for each value of the pack (Indices).
// This means the call quite literally expands to:
// SubmitLZReduction<BatchSize>(<other args>, in_ptrs[0], in_ptrs[1], ...);
event e_LZReduction = SubmitLZReduction<engineID,BatchSize>(q,
block_size,
last_block,
depend_on,
in_ptrs[Indices]...
);
event e_CRC = SubmitCRC<engineID,BatchSize>(q,
block_size,
result_crc,
depend_on);
event e_StaticHuffman = SubmitStaticHuffman<engineID,BatchSize>(q,
block_size,
gzip_out_buf,
last_block,
depend_on,
out_ptrs[Indices]...
);
return {e_CRC, e_LZReduction, e_StaticHuffman};
}
//template <int BatchSize>
std::vector<event> SubmitGzipTasks(queue &q, size_t block_size,
struct GzipOutInfo *gzip_out_buf,
uint32_t *result_crc, bool last_block,
std::vector<event> depend_on,
std::array<char *, BATCH_SIZE> in_ptrs,
std::array<char *, BATCH_SIZE> out_ptrs,
size_t engineID) {
// A parameter pack is used for passing a batch of pointers (i.e. pointers to
// the input/output buffers in host-memory).
// This call to the SubmitGzipTasksHelper function creates the integer
// sequence that we will use to access the input and output pointers.
// This function expands to, quite literally, the following (assuming):
// SubmitGzipTasksHelper<BatchSize>(<other_args>, in_ptrs, out_ptrs,
// 0, 1, 2, 3, 4, ..., BatchSize-1);
// Statically declare the engines so that the hardware is created for them.
// But at run time, the host can dynamically select which engine(s) to use via
// engineID.
if (engineID == 0) {
return SubmitGzipTasksHelper<0, BATCH_SIZE>(
q, block_size, gzip_out_buf, result_crc, last_block, depend_on, in_ptrs,
out_ptrs, std::make_index_sequence<BATCH_SIZE>{});
}
#if NUM_ENGINES > 1
if (engineID == 1) {
return SubmitGzipTasksHelper<1, BATCH_SIZE>(
q, block_size, gzip_out_buf, result_crc, last_block, depend_on, in_ptrs,
out_ptrs, std::make_index_sequence<BATCH_SIZE>{});
}
#endif
// Default
return SubmitGzipTasksHelper<0, BATCH_SIZE>(
q, block_size, gzip_out_buf, result_crc, last_block, depend_on, in_ptrs,
out_ptrs, std::make_index_sequence<BATCH_SIZE>{});
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel_ll.hpp | #ifndef __GZIPKERNEL_H__
#define __GZIPKERNEL_H__
#pragma once
#include <sycl/sycl.hpp>
#include "kernels.hpp"
using namespace sycl;
//extern "C"
std::vector<event> SubmitGzipTasks(queue &q, size_t block_size,
struct GzipOutInfo *gzip_out_buf,
uint32_t *result_crc, bool last_block,
std::vector<event> depend_on,
std::array<char *, BATCH_SIZE> in_ptrs,
std::array<char *, BATCH_SIZE> out_ptrs,
size_t engineID);
#endif //__GZIPKERNEL_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/crc32.hpp | #ifndef __CRC32_H__
#define __CRC32_H__
#pragma once
#include <stdint.h>
#include <stdlib.h>
uint32_t Crc32Host(
const char *pbuf, // pointer to the buffer to crc
size_t sz, // number of bytes
uint32_t previous_crc); // previous CRC, allows combining. First invocation
// would use 0xffffffff.
uint32_t Crc32(const char *pbuf, // pointer to the buffer to crc
size_t sz, // number of bytes
uint32_t previous_crc); // previous CRC, allows combining. First
// invocation would use 0xffffffff.
#endif //__CRC32_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzip_ll.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <chrono>
#include <fstream>
#include <string>
#include "CompareGzip.hpp"
#include "WriteGzip.hpp"
#include "crc32.hpp"
#include "gzipkernel_ll.hpp"
#include "kernels.hpp"
#include "exception_handler.hpp"
using namespace sycl;
// The minimum file size of a file to be compressed.
// Any filesize less than this results in an error.
constexpr int minimum_filesize = kVec + 1;
const int N_BUFFERING = 2; // Number of sets of I/O buffers to
// allocate, for the purpose of overlapping kernel
// execution with buffer preparation.
bool help = false;
int CompressFile(queue &q, std::string &input_file,
std::vector<std::string> outfilenames, int iterations,
bool report);
void Help(void) {
// Command line arguments.
// gzip [options] filetozip [options]
// -h,--help : help
// future options?
// -p,performance : output perf metrics
// -m,maxmapping=# : maximum mapping size
std::cout << "gzip filename [options]\n";
std::cout << " -h,--help : this help text\n";
std::cout
<< " -o=<filename>,--output-file=<filename> : specify output file\n";
}
bool FindGetArg(std::string &arg, const char *str, int defaultval, int *val) {
std::size_t found = arg.find(str, 0, strlen(str));
if (found != std::string::npos) {
int value = atoi(&arg.c_str()[strlen(str)]);
*val = value;
return true;
}
return false;
}
constexpr int kMaxStringLen = 40;
bool FindGetArgString(std::string &arg, const char *str, char *str_value,
size_t maxchars) {
std::size_t found = arg.find(str, 0, strlen(str));
if (found != std::string::npos) {
const char *sptr = &arg.c_str()[strlen(str)];
for (int i = 0; i < maxchars - 1; i++) {
char ch = sptr[i];
switch (ch) {
case ' ':
case '\t':
case '\0':
str_value[i] = 0;
return true;
break;
default:
str_value[i] = ch;
break;
}
}
return true;
}
return false;
}
size_t SyclGetExecTimeNs(event e) {
size_t start_time =
e.get_profiling_info<info::event_profiling::command_start>();
size_t end_time = e.get_profiling_info<info::event_profiling::command_end>();
return (end_time - start_time);
}
int main(int argc, char *argv[]) {
std::string infilename = "";
std::vector<std::string> outfilenames(kNumEngines);
char str_buffer[kMaxStringLen] = {0};
// Check the number of arguments specified
if (argc != 3) {
std::cerr << "Incorrect number of arguments. Correct usage: " << argv[0]
<< " <input-file> -o=<output-file>\n";
return 1;
}
for (int i = 1; i < argc; i++) {
if (argv[i][0] == '-') {
std::string sarg(argv[i]);
if (std::string(argv[i]) == "-h") {
help = true;
}
if (std::string(argv[i]) == "--help") {
help = true;
}
FindGetArgString(sarg, "-o=", str_buffer, kMaxStringLen);
FindGetArgString(sarg, "--output-file=", str_buffer, kMaxStringLen);
} else {
infilename = std::string(argv[i]);
}
}
if (help) {
Help();
return 1;
}
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
auto prop_list = property_list{property::queue::enable_profiling()};
queue q(selector, fpga_tools::exception_handler, prop_list);
auto device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<info::device::name>().c_str()
<< std::endl;
if (infilename == "") {
std::cout << "Must specify a filename to compress\n\n";
Help();
return 1;
}
// next, check valid and acceptable parameter ranges.
// if output filename not set, use the default
// name, else use the name specified by the user
outfilenames[0] = std::string(infilename) + ".gz";
if (strlen(str_buffer)) {
outfilenames[0] = std::string(str_buffer);
}
for (size_t i = 1; i < kNumEngines; i++) {
// Filenames will be of the form outfilename, outfilename2, outfilename3
// etc.
outfilenames[i] = outfilenames[0] + std::to_string(i + 1);
}
std::cout << "Launching Low-Latency GZIP application with " << kNumEngines
<< " engines\n";
#ifdef FPGA_EMULATOR
CompressFile(q, infilename, outfilenames, 10, true);
#elif FPGA_SIMULATOR
CompressFile(q, infilename, outfilenames, 2, true);
#else
// warmup run - use this run to warmup accelerator. There are some steps in
// the runtime that are only executed on the first kernel invocation but not
// on subsequent invocations. So execute all that stuff here before we
// measure performance (in the next call to CompressFile().
CompressFile(q, infilename, outfilenames, 1, false);
// profile performance
CompressFile(q, infilename, outfilenames, 200, true);
#endif
} catch (sycl::exception const &e) {
// Catches exceptions in the host code
std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";
// Most likely the runtime couldn't find FPGA hardware!
if (e.code().value() == CL_DEVICE_NOT_FOUND) {
std::cerr << "If you are targeting an FPGA, please ensure that your "
"system has a correctly configured FPGA board.\n";
std::cerr << "Run sys_check in the oneAPI root directory to verify.\n";
std::cerr << "If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR.\n";
std::cerr << "If you are targeting the FPGA simulator, compile with "
"-DFPGA_SIMULATOR.\n";
}
std::terminate();
}
return 0;
}
struct KernelInfo {
struct GzipOutInfo
*gzip_out_buf; // Contains meta data about the compressed file
uint32_t *current_crc; // Partial CRC of the input file
char **pobuf_ptr_array; // Array of pointers to input files to be compressed
char **pibuf_ptr_array; // Corresponding array of pointers to output from the
// gzip engine (the compressed results)
char *pref_buffer; // Original input copy of file to compress
size_t input_size;
size_t output_size;
bool last_block;
std::vector<event> kernel_event; // Events for the execution of the kernels
// that comprise the GZIP engine
};
// returns 0 on success, otherwise a non-zero failure code.
int CompressFile(queue &q, std::string &input_file,
std::vector<std::string> outfilenames, int iterations,
bool report) {
size_t isz;
char *pinbuf;
auto dev = q.get_device();
auto ctxt = q.get_context();
usm_allocator<GzipOutInfo, usm::alloc::host> alloc_GzipOutInfo(ctxt, dev);
usm_allocator<unsigned, usm::alloc::host> alloc_unsigned(ctxt, dev);
usm_allocator<char *, usm::alloc::host> alloc_char_ptr(ctxt, dev);
usm_allocator<char, usm::alloc::host> alloc_char(ctxt, dev);
// Read the input file
std::string device_string =
q.get_device().get_info<info::device::name>().c_str();
// If the device is supports USM allocations, we pre-pin some buffers to
// improve DMA performance, which is needed to
// achieve peak kernel throughput. Pre-pinning is
// only supported on the USM capable BSPs. It's not
// needed on non-USM capabale BSPs to achieve peak performance.
bool prepin = q.get_device().has(aspect::usm_host_allocations);
if (!prepin) {
std::cout << "Warning: Host allocations are not supported on this "
"platform, which means that pre-pinning is not supported. DMA "
"transfers may be slower than expected which may reduce "
"application throughput.\n\n";
}
// padding for the input and output buffers to deal with granularity of
// kernel reads and writes
constexpr size_t kInOutPadding = 16 * kVec;
std::ifstream file(input_file,
std::ios::in | std::ios::binary | std::ios::ate);
if (file.is_open()) {
isz = file.tellg();
if (prepin) {
pinbuf = (char *)malloc_host(
isz + kInOutPadding, q.get_context()); // Pre-pin the buffer, for faster DMA
} else { // throughput, using malloc_host().
pinbuf = new char[isz + kInOutPadding];
}
file.seekg(0, std::ios::beg);
file.read(pinbuf, isz);
file.close();
} else {
std::cout << "Error: cannot read specified input file\n";
return 1;
}
if (isz < minimum_filesize) {
std::cout << "Minimum filesize for compression is " << minimum_filesize
<< "\n";
return 1;
}
int buffers_count = iterations;
// Array of kernel info structures...
struct KernelInfo *kinfo[kNumEngines];
for (size_t eng = 0; eng < kNumEngines; eng++) {
kinfo[eng] = new struct KernelInfo[buffers_count];
if (kinfo[eng] == NULL) {
std::cout << "Cannot allocate kernel info buffer.\n";
return 1;
}
}
// This loop allocates host-side USM buffers, to be accessed by the kernel.
for (size_t eng = 0; eng < kNumEngines; eng++) {
for (int i = 0; i < buffers_count; i++) {
kinfo[eng][i].input_size = isz;
// Allocating slightly larger buffers (+ 16 * kVec) to account for
// granularity of kernel writes
kinfo[eng][i].output_size =
((isz + kInOutPadding) < kMinBufferSize) ? kMinBufferSize
: (isz + kInOutPadding);
const size_t input_alloc_size = isz + kInOutPadding;
kinfo[eng][i].last_block = true;
kinfo[eng][i].pref_buffer = pinbuf;
// Only allocate N_BUFFERING number of buffers and reuse them on
// subsequent iterations.
kinfo[eng][i].gzip_out_buf =
i >= N_BUFFERING ? kinfo[eng][i - N_BUFFERING].gzip_out_buf
: alloc_GzipOutInfo.allocate(BATCH_SIZE *
sizeof(GzipOutInfo));
kinfo[eng][i].current_crc =
i >= N_BUFFERING
? kinfo[eng][i - N_BUFFERING].current_crc
: alloc_unsigned.allocate(BATCH_SIZE * sizeof(uint32_t));
for (int b = 0; b < BATCH_SIZE; b++) {
kinfo[eng][i].current_crc[b] = 0;
kinfo[eng][i].gzip_out_buf[b].compression_sz = 0;
}
// Allocate space for the array of pointers. The array contains
// BATCH_SIZE number of pointers.
kinfo[eng][i].pibuf_ptr_array =
i >= N_BUFFERING
? kinfo[eng][i - N_BUFFERING].pibuf_ptr_array
: alloc_char_ptr.allocate(BATCH_SIZE * sizeof(char *));
kinfo[eng][i].pobuf_ptr_array =
i >= N_BUFFERING
? kinfo[eng][i - N_BUFFERING].pobuf_ptr_array
: alloc_char_ptr.allocate(BATCH_SIZE * sizeof(char *));
// For each pointer, allocated space for the input/output buffers
if (i <
N_BUFFERING) { // But only for the first N_BUFFERING kinfo structs
// since the buffers get subsequently reused.
for (int b = 0; b < BATCH_SIZE; b++) {
kinfo[eng][i].pibuf_ptr_array[b] =
alloc_char.allocate(input_alloc_size * sizeof(char));
kinfo[eng][i].pobuf_ptr_array[b] =
alloc_char.allocate(kinfo[eng][i].output_size * sizeof(char));
memset(kinfo[eng][i].pobuf_ptr_array[b], 0,
kinfo[eng][i].output_size); // Initialize output buf to zero.
}
}
}
}
// Vectors to store the in/out pointers for each iteration (buffers_count),
// for each engine (kNumengines), for each batch (BATCH_SIZE).
std::vector<std::array<std::array<char *, BATCH_SIZE>, kNumEngines>> in_ptrs(
buffers_count);
std::vector<std::array<std::array<char *, BATCH_SIZE>, kNumEngines>> out_ptrs(
buffers_count);
// Grab the pointers and populate the vectors
for (size_t index = 0; index < buffers_count; index++) {
for (size_t eng = 0; eng < kNumEngines; eng++) {
for (size_t i = 0; i < BATCH_SIZE; i++) {
if (i < BATCH_SIZE) {
in_ptrs[index][eng][i] = kinfo[eng][index].pibuf_ptr_array[i];
out_ptrs[index][eng][i] = kinfo[eng][index].pobuf_ptr_array[i];
} else { // Re-use first pointer to avoid invalid-arg runtime error
in_ptrs[index][eng][i] = kinfo[eng][index].pibuf_ptr_array[0];
out_ptrs[index][eng][i] = kinfo[eng][index].pobuf_ptr_array[0];
}
}
}
}
/*************************************************/
/* Main loop where the actual execution happens */
/*************************************************/
// Initialize the input buffer with the file to be compressed.
// In this reference design, for simplicity, we use the same input file
// repeatedly. We also do not bother to copy the output (the compressed
// result) out of the output buffers since it's the same on every execution.
// Recall that the input and output buffers are reused, therefore in a real
// application you'll need to both copy new files into the input buffers and
// copy the compressed results out of the output buffers. System throughput
// may degrade if these host-side operations take longer than the kernel
// execution time because you won't be able to safely invoke a new kernel
// until the copies are complete, leading to deadtime between kernel
// executions. The host-side processing time can be hidden using "N-way
// buffering" -- see the corresponding tutorial (n_way_buffering) to learn how
// this is can be done.
int initial_index = std::min(N_BUFFERING, buffers_count);
for (int index = 0; index < initial_index; index++) {
for (size_t eng = 0; eng < kNumEngines; eng++) {
for (int b = 0; b < BATCH_SIZE; b++) {
memcpy(kinfo[eng][index].pibuf_ptr_array[b],
kinfo[eng][index].pref_buffer, kinfo[eng][index].input_size);
}
}
}
#ifdef FPGA_EMULATOR
#elif FPGA_SIMULATOR
#else
auto start = std::chrono::steady_clock::now();
#endif
// Launch initial set of kernels
for (int index = 0; index < initial_index; index++) {
for (size_t eng = 0; eng < kNumEngines; eng++) {
kinfo[eng][index].kernel_event = SubmitGzipTasks(q,
kinfo[eng][index].input_size,
kinfo[eng][index].gzip_out_buf,
kinfo[eng][index].current_crc,
kinfo[eng][index].last_block,
{},
in_ptrs[index][eng],
out_ptrs[index][eng],
eng
);
}
}
// Main loop where the gzip engine is repeatedly invoked in a double-buffered
// fashion.
for (int index = initial_index; index < buffers_count; index++) {
for (size_t eng = 0; eng < kNumEngines; eng++) {
/************************************/
/************************************/
/* LAUNCH GZIP ENGINE */
/************************************/
/************************************/
kinfo[eng][index].kernel_event = SubmitGzipTasks(q,
kinfo[eng][index].input_size,
kinfo[eng][index].gzip_out_buf,
kinfo[eng][index].current_crc,
kinfo[eng][index].last_block,
kinfo[eng][index - N_BUFFERING].kernel_event,
in_ptrs[index][eng],
out_ptrs[index][eng],
eng
);
}
}
// Wait for all kernels to complete.
for (int index = buffers_count - initial_index; index < buffers_count;
index++) {
for (size_t eng = 0; eng < kNumEngines; eng++) {
for (auto event : kinfo[eng][index].kernel_event) {
event.wait();
}
}
}
// Stop the timer.
#ifdef FPGA_EMULATOR
#elif FPGA_SIMULATOR
#else
auto end = std::chrono::steady_clock::now();
double diff_total = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
if (report) {
std::cout << "Total execution time: " << (double)diff_total * 1000000
<< "us \n";
std::cout << "Average per batch_latency: "
<< (double)diff_total * 1000000 / iterations << " us \n";
}
double gbps = BATCH_SIZE * iterations * isz / (double)diff_total /
1000000000.0;
#endif
// Sanity check the compressed size of every result. Also sum the compressed
// sizes together to be later used to calculate the compression ratio.
size_t compressed_sz[kNumEngines];
for (int eng = 0; eng < kNumEngines; eng++) {
compressed_sz[eng] = 0;
for (int index = 0; index < buffers_count; index++) {
for (int b = 0; b < BATCH_SIZE; b++) {
if (kinfo[eng][index].gzip_out_buf[b].compression_sz >
kinfo[eng][index].input_size) {
std::cerr << "Unsupported: compressed file larger than input file ( "
<< kinfo[eng][index].gzip_out_buf[b].compression_sz
<< " bytes)\n";
return 1;
}
compressed_sz[eng] += kinfo[eng][index].gzip_out_buf[b].compression_sz;
}
}
}
if (report) std::cout << "Writing gzip archive to disk and verifying\n";
// Write the outputs from buffer set 0 and check for errors
for (int i = 0; i < 1;
i++) { // Here you could iterate through all the buffer sets.
for (int eng = 0; eng < kNumEngines; eng++) {
for (int b = 0; b < BATCH_SIZE; b++) {
if (report &&
WriteBlockGzip(
input_file, outfilenames[eng], kinfo[eng][i].pobuf_ptr_array[b],
kinfo[eng][i].gzip_out_buf[b].compression_sz,
kinfo[eng][i].input_size,
Crc32(kinfo[eng][i].pref_buffer, kinfo[eng][i].input_size,
kinfo[eng][i].current_crc[b]) // Compute the remaining
// piece of the CRC.
)) {
std::cout << "FAILED\n";
return 1;
}
}
}
}
// Decompress the output from engine-0 and compare against the input file.
// Only engine-0's output is verified since all engines are fed the same input
// data.
if (report && CompareGzipFiles(input_file, outfilenames[0])) {
std::cout << "FAILED\n";
return 1;
}
// Generate throughput report
// First gather all the execution times.
size_t time_k_crc[kNumEngines];
size_t time_k_lz[kNumEngines];
size_t time_k_huff[kNumEngines];
for (int eng = 0; eng < kNumEngines; eng++) {
time_k_crc[eng] = 0;
time_k_lz[eng] = 0;
time_k_huff[eng] = 0;
for (int i = 0; i < buffers_count;
i++) { // Execution times (total sums) of the individual gzip kernels
time_k_crc[eng] +=
SyclGetExecTimeNs(kinfo[eng][i].kernel_event[kCRCIndex]);
time_k_lz[eng] +=
SyclGetExecTimeNs(kinfo[eng][i].kernel_event[kLZReductionIndex]);
time_k_huff[eng] +=
SyclGetExecTimeNs(kinfo[eng][i].kernel_event[kStaticHuffmanIndex]);
}
}
if (report) {
double compression_ratio = (double)((double)compressed_sz[0] / (double)isz /
BATCH_SIZE / iterations);
#ifdef FPGA_EMULATOR
#elif FPGA_SIMULATOR
#else
std::cout << "Throughput: " << kNumEngines * gbps << " GB/s\n\n";
for (int eng = 0; eng < kNumEngines; eng++) {
std::cout << "TP breakdown for engine #" << eng << " (GB/s)\n";
std::cout << "CRC = " << BATCH_SIZE * iterations * isz / (double)time_k_crc[eng]
<< "\n";
std::cout << "LZ77 = " << BATCH_SIZE * iterations * isz / (double)time_k_lz[eng]
<< "\n";
std::cout << "Huffman Encoding = "
<< BATCH_SIZE * iterations * isz / (double)time_k_huff[eng] << "\n";
}
#endif
std::cout << "Compression Ratio " << compression_ratio * 100 << "%\n";
}
// Cleanup anything that was allocated by this routine.
// delete the file mapping now that all kernels are complete, and we've
// snapped the time delta
// delete the file mapping now that all kernels are complete, and we've
// snapped the time delta
if (prepin) {
free(pinbuf, q.get_context());
} else {
delete pinbuf;
}
for (int eng = 0; eng < kNumEngines; eng++) {
for (int i = 0; i < buffers_count; i++) {
if (i < N_BUFFERING) {
alloc_GzipOutInfo.deallocate(kinfo[eng][i].gzip_out_buf,
BATCH_SIZE * sizeof(GzipOutInfo));
alloc_unsigned.deallocate(kinfo[eng][i].current_crc,
BATCH_SIZE * sizeof(uint32_t));
// dealloc the input buffers
for (int b = 0; b < BATCH_SIZE; b++) {
alloc_char.deallocate(kinfo[eng][i].pibuf_ptr_array[b],
kinfo[eng][i].input_size * sizeof(char));
alloc_char.deallocate(kinfo[eng][i].pobuf_ptr_array[b],
kinfo[eng][i].output_size * sizeof(char));
}
// dealloc the array of input buffer pointers
alloc_char_ptr.deallocate(kinfo[eng][i].pibuf_ptr_array,
BATCH_SIZE * sizeof(char *));
alloc_char_ptr.deallocate(kinfo[eng][i].pobuf_ptr_array,
BATCH_SIZE * sizeof(char *));
}
}
delete[] kinfo[eng];
}
if (report) std::cout << "PASSED\n";
return 0;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/WriteGzip.hpp | #ifndef __WRITEGZIP_H__
#define __WRITEGZIP_H__
#pragma once
#include <iostream>
#include <string>
// returns 0 on success, otherwise failure
int WriteBlockGzip(
std::string &original_filename, // Original file name being compressed
std::string &out_filename, // gzip filename
char *obuf, // pointer to compressed data block
size_t blen, // length of compressed data block
size_t ilen, // original block length
uint32_t buffer_crc); // the block's crc
#endif //__WRITEGZIP_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CompareGzip.hpp | #ifndef __COMPAREGZIP_H__
#define __COMPAREGZIP_H__
#pragma once
#include <iostream>
#include <string>
int CompareGzipFiles(
const std::string
&original_file, // original input file to compare gzip uncompressed
const std::string &input_gzfile); // gzip file to check
#endif //__COMPAREGZIP_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/gzipkernel.cpp | #include <sycl/sycl.hpp>
#include "gzipkernel.hpp"
#include "kernels.hpp"
using namespace sycl;
// This reference design uses a template-based unroller. It's also possible
// to specify this in a more concise way using a pragma. See the loop unroll
// tutorial for more information.
template <int Begin, int End>
struct Unroller {
template <typename Action>
static void step(const Action &action) {
action(Begin);
Unroller<Begin + 1, End>::step(action);
}
};
template <int End>
struct Unroller<End, End> {
template <typename Action>
static void step(const Action &action) {}
};
int GetHuffLiteralBits(unsigned char ch) {
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
return static_ltree[ch].code;
}
int GetHuffLiteralLen(unsigned char ch) {
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
return static_ltree[ch].len;
}
int GetHuffRunLen(int len, int initial_dist) {
int lc;
unsigned code;
int extra;
int dist;
//int local_lbits;
int local_llen;
//int local_dbits;
int local_dlen;
//local_lbits = 0;
local_llen = 0;
int base_length[kLengthCodes] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24,
28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 0,
};
int extra_lbits[kLengthCodes] // extra bits for each length code
= {0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0};
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
// distance codes. The first 256 values correspond to the distances
// 3 .. 258, the last 256 values correspond to the top 8 bits of
// the 15 bit distances.
unsigned char dist_code[512] = {
0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8,
8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 0, 0, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 21, 21,
21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29,
};
// length code for each normalized match length (0 == kMinMatch)
unsigned char length_code[kMaxMatch - kMinMatch + 1] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12,
12, 12, 13, 13, 13, 13, 14, 14, 14, 14, 15, 15, 15, 15, 16, 16, 16, 16,
16, 16, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18,
18, 18, 19, 19, 19, 19, 19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21,
21, 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23,
23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 28,
};
int extra_dbits[kDCodes] // extra bits for each distance code
= {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6,
6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13};
int base_dist[kDCodes] = {
0, 1, 2, 3, 4, 6, 8, 12, 16, 24,
32, 48, 64, 96, 128, 192, 256, 384, 512, 768,
1024, 1536, 2048, 3072, 4096, 6144, 8192, 12288, 16384, 24576,
};
CtData static_dtree[kDCodes] = {
{0, 5}, {16, 5}, {8, 5}, {24, 5}, {4, 5}, {20, 5}, {12, 5}, {28, 5},
{2, 5}, {18, 5}, {10, 5}, {26, 5}, {6, 5}, {22, 5}, {14, 5}, {30, 5},
{1, 5}, {17, 5}, {9, 5}, {25, 5}, {5, 5}, {21, 5}, {13, 5}, {29, 5},
{3, 5}, {19, 5}, {11, 5}, {27, 5}, {7, 5}, {23, 5},
};
lc = len - kMinMatch;
code = length_code[lc];
//local_lbits = static_ltree[code + kLiterals + 1].code;
local_llen = static_ltree[code + kLiterals + 1].len;
extra = extra_lbits[code];
if (extra) {
lc -= base_length[code];
//local_lbits |= lc << local_llen;
local_llen += extra;
}
dist = initial_dist;
dist--;
code = d_code(dist);
//local_dbits = static_dtree[code].code;
local_dlen = static_dtree[code].len;
extra = extra_dbits[code];
if (extra) {
dist -= base_dist[code];
//local_dbits |= dist << local_dlen;
local_dlen += extra;
}
//local_lbits |= local_dbits << local_llen;
local_llen += local_dlen;
return local_llen;
}
int GetHuffRunBits(int len, int initial_dist) {
int lc;
unsigned code;
int extra;
int dist;
int local_lbits, local_llen;
int local_dbits, local_dlen;
local_lbits = 0;
local_llen = 0;
int base_length[kLengthCodes] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24,
28, 32, 40, 48, 56, 64, 80, 96, 112, 128, 160, 192, 224, 0,
};
int extra_lbits[kLengthCodes] // extra bits for each length code
= {0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0};
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
// distance codes. The first 256 values correspond to the distances
// 3 .. 258, the last 256 values correspond to the top 8 bits of
// the 15 bit distances.
unsigned char dist_code[512] = {
0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8,
8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10,
10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11,
11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
13, 13, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
15, 15, 15, 15, 0, 0, 16, 17, 18, 18, 19, 19, 20, 20, 20, 20, 21, 21,
21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28,
28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
29, 29, 29, 29, 29, 29, 29, 29,
};
// length code for each normalized match length (0 == kMinMatch)
unsigned char length_code[kMaxMatch - kMinMatch + 1] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12,
12, 12, 13, 13, 13, 13, 14, 14, 14, 14, 15, 15, 15, 15, 16, 16, 16, 16,
16, 16, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 18, 18, 18, 18, 18, 18,
18, 18, 19, 19, 19, 19, 19, 19, 19, 19, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21,
21, 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
22, 22, 22, 22, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23,
23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,
25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
26, 26, 26, 26, 26, 26, 26, 26, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27,
27, 27, 27, 28,
};
int extra_dbits[kDCodes] // extra bits for each distance code
= {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6,
6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13};
int base_dist[kDCodes] = {
0, 1, 2, 3, 4, 6, 8, 12, 16, 24,
32, 48, 64, 96, 128, 192, 256, 384, 512, 768,
1024, 1536, 2048, 3072, 4096, 6144, 8192, 12288, 16384, 24576,
};
CtData static_dtree[kDCodes] = {
{0, 5}, {16, 5}, {8, 5}, {24, 5}, {4, 5}, {20, 5}, {12, 5}, {28, 5},
{2, 5}, {18, 5}, {10, 5}, {26, 5}, {6, 5}, {22, 5}, {14, 5}, {30, 5},
{1, 5}, {17, 5}, {9, 5}, {25, 5}, {5, 5}, {21, 5}, {13, 5}, {29, 5},
{3, 5}, {19, 5}, {11, 5}, {27, 5}, {7, 5}, {23, 5},
};
lc = len - kMinMatch;
code = length_code[lc];
local_lbits = static_ltree[code + kLiterals + 1].code;
local_llen = static_ltree[code + kLiterals + 1].len;
extra = extra_lbits[code];
if (extra) {
lc -= base_length[code];
local_lbits |= lc << local_llen;
local_llen += extra;
}
dist = initial_dist;
dist--;
code = d_code(dist);
local_dbits = static_dtree[code].code;
local_dlen = static_dtree[code].len;
extra = extra_dbits[code];
if (extra) {
dist -= base_dist[code];
local_dbits |= dist << local_dlen;
local_dlen += extra;
}
local_lbits |= local_dbits << local_llen;
local_llen += local_dlen;
return local_lbits;
}
int GetHuffLen(int len, int dist, unsigned char ch) {
int returned_len;
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
switch (len) {
case -3:
returned_len = static_ltree[kEndBlock].len;
break;
case -2:
returned_len = 3;
break;
case -1:
returned_len = 0;
break;
case 0:
returned_len = GetHuffLiteralLen(ch);
break;
default:
returned_len = GetHuffRunLen(len, dist);
break;
}
return returned_len;
}
int IsValid(int len, int dist, unsigned char ch) {
switch (len) {
case -3:
return 1;
case -2:
return 1;
case -1:
return 0;
case 0:
return 1;
default:
return 1;
}
}
int GetHuffBits(int len, int dist, unsigned char ch) {
int bits;
CtData static_ltree[kLCodes + 2] = {
{12, 8}, {140, 8}, {76, 8}, {204, 8}, {44, 8}, {172, 8}, {108, 8},
{236, 8}, {28, 8}, {156, 8}, {92, 8}, {220, 8}, {60, 8}, {188, 8},
{124, 8}, {252, 8}, {2, 8}, {130, 8}, {66, 8}, {194, 8}, {34, 8},
{162, 8}, {98, 8}, {226, 8}, {18, 8}, {146, 8}, {82, 8}, {210, 8},
{50, 8}, {178, 8}, {114, 8}, {242, 8}, {10, 8}, {138, 8}, {74, 8},
{202, 8}, {42, 8}, {170, 8}, {106, 8}, {234, 8}, {26, 8}, {154, 8},
{90, 8}, {218, 8}, {58, 8}, {186, 8}, {122, 8}, {250, 8}, {6, 8},
{134, 8}, {70, 8}, {198, 8}, {38, 8}, {166, 8}, {102, 8}, {230, 8},
{22, 8}, {150, 8}, {86, 8}, {214, 8}, {54, 8}, {182, 8}, {118, 8},
{246, 8}, {14, 8}, {142, 8}, {78, 8}, {206, 8}, {46, 8}, {174, 8},
{110, 8}, {238, 8}, {30, 8}, {158, 8}, {94, 8}, {222, 8}, {62, 8},
{190, 8}, {126, 8}, {254, 8}, {1, 8}, {129, 8}, {65, 8}, {193, 8},
{33, 8}, {161, 8}, {97, 8}, {225, 8}, {17, 8}, {145, 8}, {81, 8},
{209, 8}, {49, 8}, {177, 8}, {113, 8}, {241, 8}, {9, 8}, {137, 8},
{73, 8}, {201, 8}, {41, 8}, {169, 8}, {105, 8}, {233, 8}, {25, 8},
{153, 8}, {89, 8}, {217, 8}, {57, 8}, {185, 8}, {121, 8}, {249, 8},
{5, 8}, {133, 8}, {69, 8}, {197, 8}, {37, 8}, {165, 8}, {101, 8},
{229, 8}, {21, 8}, {149, 8}, {85, 8}, {213, 8}, {53, 8}, {181, 8},
{117, 8}, {245, 8}, {13, 8}, {141, 8}, {77, 8}, {205, 8}, {45, 8},
{173, 8}, {109, 8}, {237, 8}, {29, 8}, {157, 8}, {93, 8}, {221, 8},
{61, 8}, {189, 8}, {125, 8}, {253, 8}, {19, 9}, {275, 9}, {147, 9},
{403, 9}, {83, 9}, {339, 9}, {211, 9}, {467, 9}, {51, 9}, {307, 9},
{179, 9}, {435, 9}, {115, 9}, {371, 9}, {243, 9}, {499, 9}, {11, 9},
{267, 9}, {139, 9}, {395, 9}, {75, 9}, {331, 9}, {203, 9}, {459, 9},
{43, 9}, {299, 9}, {171, 9}, {427, 9}, {107, 9}, {363, 9}, {235, 9},
{491, 9}, {27, 9}, {283, 9}, {155, 9}, {411, 9}, {91, 9}, {347, 9},
{219, 9}, {475, 9}, {59, 9}, {315, 9}, {187, 9}, {443, 9}, {123, 9},
{379, 9}, {251, 9}, {507, 9}, {7, 9}, {263, 9}, {135, 9}, {391, 9},
{71, 9}, {327, 9}, {199, 9}, {455, 9}, {39, 9}, {295, 9}, {167, 9},
{423, 9}, {103, 9}, {359, 9}, {231, 9}, {487, 9}, {23, 9}, {279, 9},
{151, 9}, {407, 9}, {87, 9}, {343, 9}, {215, 9}, {471, 9}, {55, 9},
{311, 9}, {183, 9}, {439, 9}, {119, 9}, {375, 9}, {247, 9}, {503, 9},
{15, 9}, {271, 9}, {143, 9}, {399, 9}, {79, 9}, {335, 9}, {207, 9},
{463, 9}, {47, 9}, {303, 9}, {175, 9}, {431, 9}, {111, 9}, {367, 9},
{239, 9}, {495, 9}, {31, 9}, {287, 9}, {159, 9}, {415, 9}, {95, 9},
{351, 9}, {223, 9}, {479, 9}, {63, 9}, {319, 9}, {191, 9}, {447, 9},
{127, 9}, {383, 9}, {255, 9}, {511, 9}, {0, 7}, {64, 7}, {32, 7},
{96, 7}, {16, 7}, {80, 7}, {48, 7}, {112, 7}, {8, 7}, {72, 7},
{40, 7}, {104, 7}, {24, 7}, {88, 7}, {56, 7}, {120, 7}, {4, 7},
{68, 7}, {36, 7}, {100, 7}, {20, 7}, {84, 7}, {52, 7}, {116, 7},
{3, 8}, {131, 8}, {67, 8}, {195, 8}, {35, 8}, {163, 8}, {99, 8},
{227, 8},
};
switch (len) {
case -3:
bits = static_ltree[kEndBlock].code;
break;
case -2:
bits = ch;
break;
case -1:
bits = 0;
break;
case 0:
bits = GetHuffLiteralBits(ch);
break;
default:
bits = GetHuffRunBits(len, dist);
break;
}
return bits;
}
// assembles up to kVecX2 unsigned char values based on given huffman encoding
// writes up to kMaxHuffcodeBits * kVecX2 bits to memory
bool HufEnc(char *len, short *dist, unsigned char *data, unsigned int *outdata,
unsigned int *leftover, unsigned short *leftover_size) {
// array that contains the bit position of each symbol
unsigned short bitpos[kVec + 1];
bitpos[0] = 0;
Unroller<0, kVec>::step([&](int i) {
bitpos[i + 1] = bitpos[i] + (IsValid(len[i], dist[i], data[i])
? GetHuffLen(len[i], dist[i], data[i])
: 0);
});
// leftover is an array that carries huffman encoded data not yet written to
// memory adjust leftover_size with the number of bits to write this time
unsigned short prev_cycle_offset = *leftover_size;
*leftover_size += (bitpos[kVec] & 0x3fff);
// we'll write this cycle if we have collected enough data (kVec shorts or
// more)
bool write = *leftover_size & (kVec * (kMaxHuffcodeBits * 2));
// subtract kVec shorts from leftover size (if it's bigger
// than kVec) because we'll write those out this cycle
*leftover_size &= ~(kVec * (kMaxHuffcodeBits * 2));
// Adjust bitpos based on leftover offset from previous cycle
Unroller<0, kVec>::step(
[&](int i) { bitpos[i] += (prev_cycle_offset & 0x3fff); });
// Huffman codes have any bit alignement, so they can spill
// onto two shorts in the output array
// use ushort2 to keep each part of the code separate
// Iterate over all codes and construct ushort2 containing
// the code properly aligned
struct Uint2Gzip code[kVec];
Unroller<0, kVec>::step([&](int i) {
code[i].x = 0;
code[i].y = 0;
});
Unroller<0, kVec>::step([&](int i) {
// Codes can be more than 16 bits, so use uint32
unsigned int curr_code = GetHuffBits(len[i], dist[i], data[i]);
unsigned char bitpos_in_short = bitpos[i] & 0x01F;
unsigned long long temp = (unsigned long long)curr_code << bitpos_in_short;
unsigned int temp1 = (unsigned int)temp;
unsigned int temp2 = temp >> 32ULL;
if (IsValid(len[i], dist[i], data[i])) {
code[i].x = temp1;
code[i].y = temp2;
} else {
code[i].x = temp1;
code[i].y = temp2;
}
});
// Iterate over all destination locations and gather the required data
unsigned int new_leftover[kVec];
Unroller<0, kVec>::step([&](int i) {
new_leftover[i] = 0;
outdata[i] = 0;
Unroller<0, kVec>::step([&](int j) {
// figure out whether code[j] goes into bucket[i]
bool match_first = ((bitpos[j] >> 5) & (kVec - 1)) == i;
bool match_second =
((bitpos[j] >> 5) & (kVec - 1)) == ((i - 1) & (kVec - 1));
// if code[j] maps onto current bucket then OR its code, else OR with 0
unsigned int component =
match_first ? code[j].x : (match_second ? code[j].y : 0);
// overflow from kVec shorts, need to move onto new_leftover
bool use_later =
(bitpos[j] & (kVec * (kMaxHuffcodeBits * 2))) ||
(match_second && (((bitpos[j] >> 5) & (kVec - 1)) == kVec - 1));
// write to output
outdata[i] |= use_later ? 0 : component;
new_leftover[i] |= use_later ? component : 0;
});
});
// Apply previous leftover on the outdata
// Also, if didn't write, apply prev leftover onto newleftover
Unroller<0, kVec>::step([&](int i) {
outdata[i] |= leftover[i];
leftover[i] = outdata[i];
});
// Split unroll into two unrolls to avoid compiler crash. This is a temporary
// workaround while awaiting a compiler feature.
if (write) {
Unroller<0, kVec>::step([&](int i) { leftover[i] = new_leftover[i]; });
}
return write;
}
template <int engineID>
class CRC;
template <int engineID>
class LZReduction;
template <int engineID>
class StaticHuffman;
template <int engineID>
void SubmitGzipTasksSingleEngine(
queue &q,
size_t block_size, // size of block to compress.
buffer<char, 1> *pibuf, buffer<char, 1> *pobuf,
buffer<struct GzipOutInfo, 1> *gzip_out_buf,
buffer<unsigned, 1> *result_crc, bool last_block, event &e_crc, event &e_lz,
event &e_huff) {
using acc_dist_channel = ext::intel::pipe<class some_pipe, struct DistLen>;
using acc_dist_channel_last = ext::intel::pipe<class some_pipe2, struct DistLen>;
e_crc = q.submit([&](handler &h) {
auto accessor_isz = block_size;
auto acc_pibuf = pibuf->get_access<access::mode::read>(h);
auto accresult_crc = result_crc->get_access<access::mode::discard_write>(h);
h.single_task<CRC<engineID>>([=]() [[intel::kernel_args_restrict]] {
const unsigned int table64[64][16] = {
{
0x0,
0xf1da05aa,
0x38c50d15,
0xc91f08bf,
0x718a1a2a,
0x80501f80,
0x494f173f,
0xb8951295,
0xe3143454,
0x12ce31fe,
0xdbd13941,
0x2a0b3ceb,
0x929e2e7e,
0x63442bd4,
0xaa5b236b,
0x5b8126c1,
},
{
0x0,
0x1d596ee9,
0x3ab2ddd2,
0x27ebb33b,
0x7565bba4,
0x683cd54d,
0x4fd76676,
0x528e089f,
0xeacb7748,
0xf79219a1,
0xd079aa9a,
0xcd20c473,
0x9faeccec,
0x82f7a205,
0xa51c113e,
0xb8457fd7,
},
{
0x0,
0xee7e8d1,
0x1dcfd1a2,
0x13283973,
0x3b9fa344,
0x35784b95,
0x265072e6,
0x28b79a37,
0x773f4688,
0x79d8ae59,
0x6af0972a,
0x64177ffb,
0x4ca0e5cc,
0x42470d1d,
0x516f346e,
0x5f88dcbf,
},
{
0x0,
0xee7e8d10,
0x78c1c61,
0xe9f29171,
0xf1838c2,
0xe166b5d2,
0x89424a3,
0xe6eaa9b3,
0x1e307184,
0xf04efc94,
0x19bc6de5,
0xf7c2e0f5,
0x11284946,
0xff56c456,
0x16a45527,
0xf8dad837,
},
{
0x0,
0x3c60e308,
0x78c1c610,
0x44a12518,
0xf1838c20,
0xcde36f28,
0x89424a30,
0xb522a938,
0x38761e01,
0x416fd09,
0x40b7d811,
0x7cd73b19,
0xc9f59221,
0xf5957129,
0xb1345431,
0x8d54b739,
},
{
0x0,
0x70ec3c02,
0xe1d87804,
0x91344406,
0x18c1f649,
0x682dca4b,
0xf9198e4d,
0x89f5b24f,
0x3183ec92,
0x416fd090,
0xd05b9496,
0xa0b7a894,
0x29421adb,
0x59ae26d9,
0xc89a62df,
0xb8765edd,
},
{
0x0,
0x6307d924,
0xc60fb248,
0xa5086b6c,
0x576e62d1,
0x3469bbf5,
0x9161d099,
0xf26609bd,
0xaedcc5a2,
0xcddb1c86,
0x68d377ea,
0xbd4aece,
0xf9b2a773,
0x9ab57e57,
0x3fbd153b,
0x5cbacc1f,
},
{
0x0,
0x86c88d05,
0xd6e01c4b,
0x5028914e,
0x76b13ed7,
0xf079b3d2,
0xa051229c,
0x2699af99,
0xed627dae,
0x6baaf0ab,
0x3b8261e5,
0xbd4aece0,
0x9bd34379,
0x1d1bce7c,
0x4d335f32,
0xcbfbd237,
},
{
0x0,
0x1b5fd1d,
0x36bfa3a,
0x2de0727,
0x6d7f474,
0x7620969,
0x5bc0e4e,
0x409f353,
0xdafe8e8,
0xc1a15f5,
0xec412d2,
0xf71efcf,
0xb781c9c,
0xacde181,
0x813e6a6,
0x9a61bbb,
},
{
0x0,
0x1b5fd1d0,
0x36bfa3a0,
0x2de07270,
0x6d7f4740,
0x76209690,
0x5bc0e4e0,
0x409f3530,
0xdafe8e80,
0xc1a15f50,
0xec412d20,
0xf71efcf0,
0xb781c9c0,
0xacde1810,
0x813e6a60,
0x9a61bbb0,
},
{
0x0,
0x6e8c1b41,
0xdd183682,
0xb3942dc3,
0x61416b45,
0xfcd7004,
0xbc595dc7,
0xd2d54686,
0xc282d68a,
0xac0ecdcb,
0x1f9ae008,
0x7116fb49,
0xa3c3bdcf,
0xcd4fa68e,
0x7edb8b4d,
0x1057900c,
},
{
0x0,
0x5e74ab55,
0xbce956aa,
0xe29dfdff,
0xa2a3ab15,
0xfcd70040,
0x1e4afdbf,
0x403e56ea,
0x9e36506b,
0xc042fb3e,
0x22df06c1,
0x7cabad94,
0x3c95fb7e,
0x62e1502b,
0x807cadd4,
0xde080681,
},
{
0x0,
0xe71da697,
0x154a4b6f,
0xf257edf8,
0x2a9496de,
0xcd893049,
0x3fdeddb1,
0xd8c37b26,
0x55292dbc,
0xb2348b2b,
0x406366d3,
0xa77ec044,
0x7fbdbb62,
0x98a01df5,
0x6af7f00d,
0x8dea569a,
},
{
0x0,
0xaa525b78,
0x8fd5b0b1,
0x2587ebc9,
0xc4da6723,
0x6e883c5b,
0x4b0fd792,
0xe15d8cea,
0x52c5c807,
0xf897937f,
0xdd1078b6,
0x774223ce,
0x961faf24,
0x3c4df45c,
0x19ca1f95,
0xb39844ed,
},
{
0x0,
0xa58b900e,
0x9066265d,
0x35edb653,
0xfbbd4afb,
0x5e36daf5,
0x6bdb6ca6,
0xce50fca8,
0x2c0b93b7,
0x898003b9,
0xbc6db5ea,
0x19e625e4,
0xd7b6d94c,
0x723d4942,
0x47d0ff11,
0xe25b6f1f,
},
{
0x0,
0x5817276e,
0xb02e4edc,
0xe83969b2,
0xbb2d9bf9,
0xe33abc97,
0xb03d525,
0x5314f24b,
0xad2a31b3,
0xf53d16dd,
0x1d047f6f,
0x45135801,
0x1607aa4a,
0x4e108d24,
0xa629e496,
0xfe3ec3f8,
},
{
0x0,
0x81256527,
0xd93bcc0f,
0x581ea928,
0x69069e5f,
0xe823fb78,
0xb03d5250,
0x31183777,
0xd20d3cbe,
0x53285999,
0xb36f0b1,
0x8a139596,
0xbb0ba2e1,
0x3a2ec7c6,
0x62306eee,
0xe3150bc9,
},
{
0x0,
0x7f6b7f3d,
0xfed6fe7a,
0x81bd8147,
0x26dcfab5,
0x59b78588,
0xd80a04cf,
0xa7617bf2,
0x4db9f56a,
0x32d28a57,
0xb36f0b10,
0xcc04742d,
0x6b650fdf,
0x140e70e2,
0x95b3f1a5,
0xead88e98,
},
{
0x0,
0x9b73ead4,
0xed96d3e9,
0x76e5393d,
0x5ca193,
0x9b2f4b47,
0xedca727a,
0x76b998ae,
0xb94326,
0x9bcaa9f2,
0xed2f90cf,
0x765c7a1b,
0xe5e2b5,
0x9b960861,
0xed73315c,
0x7600db88,
},
{
0x0,
0x172864c,
0x2e50c98,
0x3978ad4,
0x5ca1930,
0x4b89f7c,
0x72f15a8,
0x65d93e4,
0xb943260,
0xae6b42c,
0x9713ef8,
0x803b8b4,
0xe5e2b50,
0xf2cad1c,
0xcbb27c8,
0xdc9a184,
},
{
0x0,
0x172864c0,
0x2e50c980,
0x3978ad40,
0x5ca19300,
0x4b89f7c0,
0x72f15a80,
0x65d93e40,
0xb9432600,
0xae6b42c0,
0x9713ef80,
0x803b8b40,
0xe5e2b500,
0xf2cad1c0,
0xcbb27c80,
0xdc9a1840,
},
{
0x0,
0xa9f74a41,
0x889f92c3,
0x2168d882,
0xca4e23c7,
0x63b96986,
0x42d1b104,
0xeb26fb45,
0x4fed41cf,
0xe61a0b8e,
0xc772d30c,
0x6e85994d,
0x85a36208,
0x2c542849,
0xd3cf0cb,
0xa4cbba8a,
},
{
0x0,
0x9fda839e,
0xe4c4017d,
0x7b1e82e3,
0x12f904bb,
0x8d238725,
0xf63d05c6,
0x69e78658,
0x25f20976,
0xba288ae8,
0xc136080b,
0x5eec8b95,
0x370b0dcd,
0xa8d18e53,
0xd3cf0cb0,
0x4c158f2e,
},
{
0x0,
0x4be412ec,
0x97c825d8,
0xdc2c3734,
0xf4e14df1,
0xbf055f1d,
0x63296829,
0x28cd7ac5,
0x32b39da3,
0x79578f4f,
0xa57bb87b,
0xee9faa97,
0xc652d052,
0x8db6c2be,
0x519af58a,
0x1a7ee766,
},
{
0x0,
0x65673b46,
0xcace768c,
0xafa94dca,
0x4eedeb59,
0x2b8ad01f,
0x84239dd5,
0xe144a693,
0x9ddbd6b2,
0xf8bcedf4,
0x5715a03e,
0x32729b78,
0xd3363deb,
0xb65106ad,
0x19f84b67,
0x7c9f7021,
},
{
0x0,
0xe0c6ab25,
0x1afc500b,
0xfa3afb2e,
0x35f8a016,
0xd53e0b33,
0x2f04f01d,
0xcfc25b38,
0x6bf1402c,
0x8b37eb09,
0x710d1027,
0x91cbbb02,
0x5e09e03a,
0xbecf4b1f,
0x44f5b031,
0xa4331b14,
},
{
0x0,
0xd7e28058,
0x74b406f1,
0xa35686a9,
0xe9680de2,
0x3e8a8dba,
0x9ddc0b13,
0x4a3e8b4b,
0x9a11d85,
0xde439ddd,
0x7d151b74,
0xaaf79b2c,
0xe0c91067,
0x372b903f,
0x947d1696,
0x439f96ce,
},
{
0x0,
0x13423b0a,
0x26847614,
0x35c64d1e,
0x4d08ec28,
0x5e4ad722,
0x6b8c9a3c,
0x78cea136,
0x9a11d850,
0x8953e35a,
0xbc95ae44,
0xafd7954e,
0xd7193478,
0xc45b0f72,
0xf19d426c,
0xe2df7966,
},
{
0x0,
0xef52b6e1,
0x5d46b83,
0xea86dd62,
0xba8d706,
0xe4fa61e7,
0xe7cbc85,
0xe12e0a64,
0x1751ae0c,
0xf80318ed,
0x1285c58f,
0xfdd7736e,
0x1cf9790a,
0xf3abcfeb,
0x192d1289,
0xf67fa468,
},
{
0x0,
0x2ea35c18,
0x5d46b830,
0x73e5e428,
0xba8d7060,
0x942e2c78,
0xe7cbc850,
0xc9689448,
0xae6be681,
0x80c8ba99,
0xf32d5eb1,
0xdd8e02a9,
0x14e696e1,
0x3a45caf9,
0x49a02ed1,
0x670372c9,
},
{
0x0,
0x87a6cb43,
0xd43c90c7,
0x539a5b84,
0x730827cf,
0xf4aeec8c,
0xa734b708,
0x20927c4b,
0xe6104f9e,
0x61b684dd,
0x322cdf59,
0xb58a141a,
0x95186851,
0x12bea312,
0x4124f896,
0xc68233d5,
},
{
0x0,
0x1751997d,
0x2ea332fa,
0x39f2ab87,
0x5d4665f4,
0x4a17fc89,
0x73e5570e,
0x64b4ce73,
0xba8ccbe8,
0xaddd5295,
0x942ff912,
0x837e606f,
0xe7caae1c,
0xf09b3761,
0xc9699ce6,
0xde38059b,
},
{
0x0,
0xae689191,
0x87a02563,
0x29c8b4f2,
0xd4314c87,
0x7a59dd16,
0x539169e4,
0xfdf9f875,
0x73139f4f,
0xdd7b0ede,
0xf4b3ba2c,
0x5adb2bbd,
0xa722d3c8,
0x94a4259,
0x2082f6ab,
0x8eea673a,
},
{
0x0,
0xe6273e9e,
0x173f7b7d,
0xf11845e3,
0x2e7ef6fa,
0xc859c864,
0x39418d87,
0xdf66b319,
0x5cfdedf4,
0xbadad36a,
0x4bc29689,
0xade5a817,
0x72831b0e,
0x94a42590,
0x65bc6073,
0x839b5eed,
},
{
0x0,
0xb9fbdbe8,
0xa886b191,
0x117d6a79,
0x8a7c6563,
0x3387be8b,
0x22fad4f2,
0x9b010f1a,
0xcf89cc87,
0x7672176f,
0x670f7d16,
0xdef4a6fe,
0x45f5a9e4,
0xfc0e720c,
0xed731875,
0x5488c39d,
},
{
0x0,
0x44629f4f,
0x88c53e9e,
0xcca7a1d1,
0xcafb7b7d,
0x8e99e432,
0x423e45e3,
0x65cdaac,
0x4e87f0bb,
0xae56ff4,
0xc642ce25,
0x8220516a,
0x847c8bc6,
0xc01e1489,
0xcb9b558,
0x48db2a17,
},
{
0x0,
0x9d0fe176,
0xe16ec4ad,
0x7c6125db,
0x19ac8f1b,
0x84a36e6d,
0xf8c24bb6,
0x65cdaac0,
0x33591e36,
0xae56ff40,
0xd237da9b,
0x4f383bed,
0x2af5912d,
0xb7fa705b,
0xcb9b5580,
0x5694b4f6,
},
{
0x0,
0x66b23c6c,
0xcd6478d8,
0xabd644b4,
0x41b9f7f1,
0x270bcb9d,
0x8cdd8f29,
0xea6fb345,
0x8373efe2,
0xe5c1d38e,
0x4e17973a,
0x28a5ab56,
0xc2ca1813,
0xa478247f,
0xfae60cb,
0x691c5ca7,
},
{
0x0,
0xdd96d985,
0x605cb54b,
0xbdca6cce,
0xc0b96a96,
0x1d2fb313,
0xa0e5dfdd,
0x7d730658,
0x5a03d36d,
0x87950ae8,
0x3a5f6626,
0xe7c9bfa3,
0x9abab9fb,
0x472c607e,
0xfae60cb0,
0x2770d535,
},
{
0x0,
0xb407a6da,
0xb37e4bf5,
0x779ed2f,
0xbd8d91ab,
0x98a3771,
0xef3da5e,
0xbaf47c84,
0xa06a2517,
0x146d83cd,
0x13146ee2,
0xa713c838,
0x1de7b4bc,
0xa9e01266,
0xae99ff49,
0x1a9e5993,
},
{
0x0,
0x9ba54c6f,
0xec3b9e9f,
0x779ed2f0,
0x3063b7f,
0x98a37710,
0xef3da5e0,
0x7498e98f,
0x60c76fe,
0x9da93a91,
0xea37e861,
0x7192a40e,
0x50a4d81,
0x9eaf01ee,
0xe931d31e,
0x72949f71,
},
{
0x0,
0xc18edfc,
0x1831dbf8,
0x14293604,
0x3063b7f0,
0x3c7b5a0c,
0x28526c08,
0x244a81f4,
0x60c76fe0,
0x6cdf821c,
0x78f6b418,
0x74ee59e4,
0x50a4d810,
0x5cbc35ec,
0x489503e8,
0x448dee14,
},
{
0x0,
0xc18edfc0,
0x586cb9c1,
0x99e26601,
0xb0d97382,
0x7157ac42,
0xe8b5ca43,
0x293b1583,
0xbac3e145,
0x7b4d3e85,
0xe2af5884,
0x23218744,
0xa1a92c7,
0xcb944d07,
0x52762b06,
0x93f8f4c6,
},
{
0x0,
0xaef6c4cb,
0x869c8fd7,
0x286a4b1c,
0xd64819ef,
0x78bedd24,
0x50d49638,
0xfe2252f3,
0x77e1359f,
0xd917f154,
0xf17dba48,
0x5f8b7e83,
0xa1a92c70,
0xf5fe8bb,
0x2735a3a7,
0x89c3676c,
},
{
0x0,
0xefc26b3e,
0x4f5d03d,
0xeb37bb03,
0x9eba07a,
0xe629cb44,
0xd1e7047,
0xe2dc1b79,
0x13d740f4,
0xfc152bca,
0x172290c9,
0xf8e0fbf7,
0x1a3ce08e,
0xf5fe8bb0,
0x1ec930b3,
0xf10b5b8d,
},
{
0x0,
0x27ae81e8,
0x4f5d03d0,
0x68f38238,
0x9eba07a0,
0xb9148648,
0xd1e70470,
0xf6498598,
0xe6050901,
0xc1ab88e9,
0xa9580ad1,
0x8ef68b39,
0x78bf0ea1,
0x5f118f49,
0x37e20d71,
0x104c8c99,
},
{
0x0,
0x177b1443,
0x2ef62886,
0x398d3cc5,
0x5dec510c,
0x4a97454f,
0x731a798a,
0x64616dc9,
0xbbd8a218,
0xaca3b65b,
0x952e8a9e,
0x82559edd,
0xe634f314,
0xf14fe757,
0xc8c2db92,
0xdfb9cfd1,
},
{
0x0,
0xacc04271,
0x82f182a3,
0x2e31c0d2,
0xde920307,
0x72524176,
0x5c6381a4,
0xf0a3c3d5,
0x6655004f,
0xca95423e,
0xe4a482ec,
0x4864c09d,
0xb8c70348,
0x14074139,
0x3a3681eb,
0x96f6c39a,
},
{
0x0,
0xccaa009e,
0x4225077d,
0x8e8f07e3,
0x844a0efa,
0x48e00e64,
0xc66f0987,
0xac50919,
0xd3e51bb5,
0x1f4f1b2b,
0x91c01cc8,
0x5d6a1c56,
0x57af154f,
0x9b0515d1,
0x158a1232,
0xd92012ac,
},
{
0x0,
0x7cbb312b,
0xf9766256,
0x85cd537d,
0x299dc2ed,
0x5526f3c6,
0xd0eba0bb,
0xac509190,
0x533b85da,
0x2f80b4f1,
0xaa4de78c,
0xd6f6d6a7,
0x7aa64737,
0x61d761c,
0x83d02561,
0xff6b144a,
},
{
0x0,
0xa6770bb4,
0x979f1129,
0x31e81a9d,
0xf44f2413,
0x52382fa7,
0x63d0353a,
0xc5a73e8e,
0x33ef4e67,
0x959845d3,
0xa4705f4e,
0x20754fa,
0xc7a06a74,
0x61d761c0,
0x503f7b5d,
0xf64870e9,
},
{
0x0,
0x67de9cce,
0xcfbd399c,
0xa863a552,
0x440b7579,
0x23d5e9b7,
0x8bb64ce5,
0xec68d02b,
0x8816eaf2,
0xefc8763c,
0x47abd36e,
0x20754fa0,
0xcc1d9f8b,
0xabc30345,
0x3a0a617,
0x647e3ad9,
},
{
0x0,
0xcb5cd3a5,
0x4dc8a10b,
0x869472ae,
0x9b914216,
0x50cd91b3,
0xd659e31d,
0x1d0530b8,
0xec53826d,
0x270f51c8,
0xa19b2366,
0x6ac7f0c3,
0x77c2c07b,
0xbc9e13de,
0x3a0a6170,
0xf156b2d5,
},
{
0x0,
0x3d6029b,
0x7ac0536,
0x47a07ad,
0xf580a6c,
0xc8e08f7,
0x8f40f5a,
0xb220dc1,
0x1eb014d8,
0x1d661643,
0x191c11ee,
0x1aca1375,
0x11e81eb4,
0x123e1c2f,
0x16441b82,
0x15921919,
},
{
0x0,
0x3d6029b0,
0x7ac05360,
0x47a07ad0,
0xf580a6c0,
0xc8e08f70,
0x8f40f5a0,
0xb220dc10,
0x30704bc1,
0xd106271,
0x4ab018a1,
0x77d03111,
0xc5f0ed01,
0xf890c4b1,
0xbf30be61,
0x825097d1,
},
{
0x0,
0x60e09782,
0xc1c12f04,
0xa121b886,
0x58f35849,
0x3813cfcb,
0x9932774d,
0xf9d2e0cf,
0xb1e6b092,
0xd1062710,
0x70279f96,
0x10c70814,
0xe915e8db,
0x89f57f59,
0x28d4c7df,
0x4834505d,
},
{
0x0,
0xb8bc6765,
0xaa09c88b,
0x12b5afee,
0x8f629757,
0x37def032,
0x256b5fdc,
0x9dd738b9,
0xc5b428ef,
0x7d084f8a,
0x6fbde064,
0xd7018701,
0x4ad6bfb8,
0xf26ad8dd,
0xe0df7733,
0x58631056,
},
{
0x0,
0x5019579f,
0xa032af3e,
0xf02bf8a1,
0x9b14583d,
0xcb0d0fa2,
0x3b26f703,
0x6b3fa09c,
0xed59b63b,
0xbd40e1a4,
0x4d6b1905,
0x1d724e9a,
0x764dee06,
0x2654b999,
0xd67f4138,
0x866616a7,
},
{
0x0,
0x1c26a37,
0x384d46e,
0x246be59,
0x709a8dc,
0x6cbc2eb,
0x48d7cb2,
0x54f1685,
0xe1351b8,
0xfd13b8f,
0xd9785d6,
0xc55efe1,
0x91af964,
0x8d89353,
0xa9e2d0a,
0xb5c473d,
},
{
0x0,
0x1c26a370,
0x384d46e0,
0x246be590,
0x709a8dc0,
0x6cbc2eb0,
0x48d7cb20,
0x54f16850,
0xe1351b80,
0xfd13b8f0,
0xd9785d60,
0xc55efe10,
0x91af9640,
0x8d893530,
0xa9e2d0a0,
0xb5c473d0,
},
{
0x0,
0x191b3141,
0x32366282,
0x2b2d53c3,
0x646cc504,
0x7d77f445,
0x565aa786,
0x4f4196c7,
0xc8d98a08,
0xd1c2bb49,
0xfaefe88a,
0xe3f4d9cb,
0xacb54f0c,
0xb5ae7e4d,
0x9e832d8e,
0x87981ccf,
},
{
0x0,
0x4ac21251,
0x958424a2,
0xdf4636f3,
0xf0794f05,
0xbabb5d54,
0x65fd6ba7,
0x2f3f79f6,
0x3b83984b,
0x71418a1a,
0xae07bce9,
0xe4c5aeb8,
0xcbfad74e,
0x8138c51f,
0x5e7ef3ec,
0x14bce1bd,
},
{
0x0,
0x77073096,
0xee0e612c,
0x990951ba,
0x76dc419,
0x706af48f,
0xe963a535,
0x9e6495a3,
0xedb8832,
0x79dcb8a4,
0xe0d5e91e,
0x97d2d988,
0x9b64c2b,
0x7eb17cbd,
0xe7b82d07,
0x90bf1d91,
},
{
0x0,
0x1db71064,
0x3b6e20c8,
0x26d930ac,
0x76dc4190,
0x6b6b51f4,
0x4db26158,
0x5005713c,
0xedb88320,
0xf00f9344,
0xd6d6a3e8,
0xcb61b38c,
0x9b64c2b0,
0x86d3d2d4,
0xa00ae278,
0xbdbdf21c,
},
};
const int num_nibbles_parallel = 64;
const int num_sections = accessor_isz / (num_nibbles_parallel /
2); // how many loop iterations
unsigned int result = ~0;
for (int i = 0; i < num_sections; i++) {
unsigned int result_update_odd = 0;
unsigned int result_update_even = 0;
// which 4 bit chunk within the section -- this loop can be unrolled, the
// total update for the crc is the xor of the updates from the nibbles
#pragma unroll
for (int nib = 0; nib < num_nibbles_parallel; nib++) {
unsigned char this_input_nibble =
(acc_pibuf[(i * num_nibbles_parallel + nib) / 2] >>
(4 * (nib % 2)));
unsigned char this_result_nibble =
(nib < 8) ? (result >> (4 * nib)) : 0;
unsigned char this_table_index =
this_input_nibble ^ this_result_nibble;
if (nib % 2) {
result_update_odd ^= table64[nib][this_table_index & 0xf];
} else {
result_update_even ^= table64[nib][this_table_index & 0xf];
}
}
result = result_update_odd ^ result_update_even;
}
accresult_crc[0] = ~result;
});
});
e_lz = q.submit([&](handler &h) {
auto accessor_isz = block_size;
auto acc_pibuf = pibuf->get_access<access::mode::read>(h);
h.single_task<LZReduction<engineID>>([=]() [[intel::kernel_args_restrict]] {
//-------------------------------------
// Hash Table(s)
//-------------------------------------
[[intel::singlepump]] [[intel::numbanks(kVec)]] [
[intel::max_replicates(kVec)]] struct {
unsigned char s[kLen];
} dictionary[kDepth][kVec];
[[intel::singlepump]] [[intel::numbanks(kVec)]] [
[intel::max_replicates(
kVec)]] unsigned int dict_offset[kDepth][kVec];
// Initialize history to empty.
for (int i = 0; i < kDepth; i++) {
Unroller<0, kVec>::step([&](int k) { dict_offset[i][k] = 0; });
}
// This is the window of data on which we look for matches
// We fetch twice our data size because we have kVec offsets
unsigned char current_window[kVecX2];
// This is the window of data on which we look for matches
// We fetch twice our data size because we have kVec offsets
unsigned char compare_window[kLen][kVec][kVec];
// kVec bytes per dict----------| | |
// kVec dictionaries-----------------| |
// one for each curr win offset---------|
// load offset into these arrays
unsigned int compare_offset[kVec][kVec];
// one per kVec bytes----------| |
// one for each compwin-------------|
// Initialize input stream position
unsigned int inpos_minus_vec_div_16 = 0;
// this is ceiling of (insize-kVec)/16, original comparison was
// inpos < insize, now inpos is carried as (inpos-kVec)/16 so this is what
// we compare to
unsigned int insize_compare = (accessor_isz) / kVec;
int ctr = insize_compare - 1;
char first_valid_pos = 0;
struct DistLen dist_offs_data;
size_t inpos = 0;
// load in new data
struct LzInput in;
Unroller<0, kVec>::step([&](int i) { in.data[i] = acc_pibuf[inpos++]; });
Unroller<0, kVec>::step([&](int i) {
current_window[i + kVec] = in.data[i];
});
do {
//-----------------------------
// Prepare current window
//-----------------------------
// shift current window
Unroller<0, kVec>::step(
[&](int i) { current_window[i] = current_window[i + kVec]; });
// load in new data
Unroller<0, kVec>::step(
[&](int i) { in.data[i] = acc_pibuf[inpos++]; });
Unroller<0, kVec>::step(
[&](int i) { current_window[kVec + i] = in.data[i]; });
//-----------------------------
// Compute hash
//-----------------------------
unsigned short hash[kVec];
Unroller<0, kVec>::step([&](int i) {
hash[i] = (current_window[i] ^ (current_window[i + 1] << 6) ^
(current_window[i + 2] << 2) ^ current_window[i + 3]) &
kHashMask;
});
//-----------------------------
// Dictionary look-up
//-----------------------------
// loop over kVec compare windows, each has a different hash
Unroller<0, kVec>::step([&](int i) {
// loop over all kVec bytes
Unroller<0, kLen>::step([&](int j) {
Unroller<0, kVec>::step([&](int k) {
compare_window[k][j][i] = dictionary[hash[i]][j].s[k];
});
});
});
// loop over compare windows
Unroller<0, kVec>::step([&](int i) {
Unroller<0, kLen>::step([&](int j) {
// loop over frames in this compare window
// (they come from different dictionaries)
compare_offset[j][i] = dict_offset[hash[i]][j];
});
});
//-----------------------------
// Dictionary update
//-----------------------------
// loop over different dictionaries to store different frames
// store one frame per dictionary
// loop over kVec bytes to store
Unroller<0, kLen>::step([&](int i) {
Unroller<0, kVec>::step([&](int j) {
// store actual bytes
dictionary[hash[i]][i].s[j] = current_window[i + j];
});
});
Unroller<0, kVec>::step([&](int i) {
// loop over kVec different dictionaries and write one word to each
dict_offset[hash[i]][i] =
(inpos_minus_vec_div_16 << 4) |
i; // inpos - kVec + 0, we know that inpos - kVec has 0 as the 4
// lower bits so really just concatenate
});
//-----------------------------
// Match search
//-----------------------------
// arrays to store length, best length etc..
unsigned char length[kVec];
bool done[kVec];
char best_length[kVec];
unsigned int best_offset[kVec];
// initialize best_length
Unroller<0, kVec>::step([&](int i) {
best_length[i] = 0;
best_offset[i] = 0;
});
// loop over each comparison window frame
// one comes from each dictionary
Unroller<0, kVec>::step([&](int i) {
// initialize length and done
Unroller<0, kVec>::step([&](int l) {
length[l] = 0;
done[l] = 0;
});
// loop over each current window
Unroller<0, kVec>::step([&](int j) {
// loop over each char in the current window
// and corresponding char in comparison window
Unroller<0, kLen>::step([&](int k) {
bool comp =
current_window[k + j] == compare_window[k][i][j] && !done[j];
length[j] += comp;
done[j] = !comp;
});
});
// Check if this the best length
Unroller<0, kVec>::step([&](int m) {
bool update_best =
(length[m] > best_length[m]) && (compare_offset[i][m] != 0) &&
(((inpos_minus_vec_div_16 << kVecPow) | (i & (kVec - 1))) -
(compare_offset[i][m]) <
kMaxDistance);
unsigned int new_offset =
(((inpos_minus_vec_div_16 << kVecPow) | (m & (kVec - 1))) &
0x7ffff) -
((compare_offset[i][m] & 0x7ffff));
// Reconsider if new_offset is bigger than current offset, might
// take more bytes to encode
update_best = update_best && (length[m] == best_length[m]) &&
(new_offset > best_offset[m])
? false
: update_best;
best_offset[m] = (update_best ? new_offset : best_offset[m]) &
0x7ffff; // 19 bits is sufficient
best_length[m] = (update_best ? length[m] : best_length[m]) &
0x1f; // 5 bits is sufficient
});
});
//-----------------------------
// Filter matches step 1
//-----------------------------
// remove matches with offsets that are <= 0: this means they're
// self-matching or didn't match and keep only the matches that, when
// encoded, take fewer bytes than the actual match length
Unroller<0, kVec>::step([&](int i) {
best_length[i] = (((best_length[i] & 0x1f) >= 3) &&
((best_offset[i]) < kMaxDistance)
? best_length[i]
: 0) &
0x1f; // 5 bits is sufficient
// Second level filter - remove matches with len 3, greater than
// kTooFar
best_length[i] =
(((best_length[i] & 0x1f) == 3) && ((best_offset[i]) > kTooFar)
? 0
: best_length[i]) &
0x1f; // 5 bits is sufficient
// don't emmit matches for last iteration as some of the
// second part of the window might be undefined
if (ctr == 0) best_length[i] = 0;
});
//-----------------------------
// Assign first_valid_pos
//-----------------------------
// first_valid_pos is loop-carried, and tricky to compute. So first
// compute it speculatively in parallel for every possible value of the
// previous first_valid_pos.
char first_valid_pos_speculative[kVec];
Unroller<0, kVec>::step([&](int guess) {
unsigned char next_match_search = guess;
Unroller<0, kVec>::step([&](int i) {
unsigned int len = best_length[i];
// Skip to the next match
next_match_search =
i >= next_match_search && len > 0 ? i + len : next_match_search;
});
first_valid_pos_speculative[guess] =
next_match_search - kVec > 0 ? next_match_search - kVec : 0;
});
// For kVec=16 (the largest currently supported), this should be a 16:1
// mux, which is 2 6LUTs deep. For larger kVec, it will be worse.
unsigned char current_valid_pos = first_valid_pos;
first_valid_pos =
first_valid_pos_speculative[first_valid_pos & (kVec - 1)] &
(kVec -
1); // first_valid_pos only needs 4 bits, make this explicit
// greedy match selection
Unroller<0, (kVec)>::step([&](int i) {
unsigned int len = best_length[i];
best_length[i] = i < current_valid_pos ? -1 : best_length[i];
// Skip to the next match
current_valid_pos =
i >= current_valid_pos && len > 0 ? i + len : current_valid_pos;
});
//-----------------------------
// Setup LZ dist/len pairs to push to Huffman encode kernel
//-----------------------------
Unroller<0, kVec>::step([&](int i) {
dist_offs_data.data[i] = 0;
dist_offs_data.len[i] = -1;
dist_offs_data.dist[i] = -1;
if (best_length[i] >= 0) {
dist_offs_data.data[i] = current_window[i];
dist_offs_data.len[i] = best_length[i];
dist_offs_data.dist[i] = best_offset[i];
}
});
acc_dist_channel::write(dist_offs_data);
// increment input position
inpos_minus_vec_div_16++;
ctr--;
} while (ctr >= 0);
const char lasti = accessor_isz - (accessor_isz & ~(kVec - 1));
const char firstpos = first_valid_pos;
Unroller<0, kVec>::step([&](unsigned char i) {
dist_offs_data.data[i] = 0;
dist_offs_data.len[i] = -1;
dist_offs_data.dist[i] = -1;
});
Unroller<0, kVec>::step([&](unsigned char i) {
bool pred =
((i - firstpos) < (lasti - firstpos)) && ((i - firstpos) >= 0);
dist_offs_data.data[i] = pred ? current_window[i + kVec] : 0;
dist_offs_data.len[i] = pred ? 0 : -1;
});
acc_dist_channel_last::write(dist_offs_data);
});
});
e_huff = q.submit([&](handler &h) {
auto accessor_isz = block_size;
auto acc_gzip_out =
gzip_out_buf->get_access<access::mode::discard_write>(h);
auto accessor_output = pobuf->get_access<access::mode::discard_write>(h);
auto acc_eof = last_block ? 1 : 0;
h.single_task<StaticHuffman<engineID>>([=
]() [[intel::kernel_args_restrict]] {
unsigned int leftover[kVec] = {0};
Unroller<0, kVec>::step([&](int i) { leftover[i] = 0; });
unsigned short leftover_size = 0;
unsigned int outpos_huffman = 0;
int ctr = ((accessor_isz) / kVec) + 2;
int odx = 0;
// Add the gzip start block marker. Assumes static huffman trees.
leftover_size = 3;
leftover[0] = ((kStaticTrees << 1) + (acc_eof));
do {
struct DistLen in;
// init the input structure for the gzip end block marker.
// this is the very last data block to be encoded and written.
Unroller<0, kVec>::step([&](int i) {
in.len[i] = -1;
in.dist[i] = -1;
in.data[i] = 0;
});
in.len[0] = ctr == 1 ? -3 : -1;
in.data[0] = 0;
in = ctr > 2 ? acc_dist_channel::read()
: (ctr == 2 ? acc_dist_channel_last::read() : in);
struct HuffmanOutput outdata;
outdata.write = HufEnc(in.len, in.dist, in.data, outdata.data, leftover,
&leftover_size);
// prevent out of bounds write
if (((ctr == 0) || outdata.write) && (odx < accessor_isz)) {
Unroller<0, kVec * sizeof(unsigned int)>::step([&](int i) {
accessor_output[odx + i] =
(ctr == 0) ? (unsigned char)(leftover[(i >> 2) & 0xf] >>
((i & 3) << 3))
: (unsigned char)(outdata.data[(i >> 2) & 0xf] >>
((i & 3) << 3));
});
}
outpos_huffman = outdata.write ? outpos_huffman + 1 : outpos_huffman;
odx += outdata.write ? (sizeof(unsigned int) << kVecPow) : 0;
} while (ctr--);
// Store summary values from lz and huffman
acc_gzip_out[0].compression_sz =
(outpos_huffman * sizeof(unsigned int) * kVec) +
(leftover_size + 7) / 8;
});
});
}
void SubmitGzipTasks(queue &q,
size_t block_size, // size of block to compress.
buffer<char, 1> *pibuf, buffer<char, 1> *pobuf,
buffer<struct GzipOutInfo, 1> *gzip_out_buf,
buffer<unsigned, 1> *result_crc, bool last_block,
event &e_crc, event &e_lz, event &e_huff,
size_t engineID) {
// Statically declare the engines so that the hardware is created for them.
// But at run time, the host can dynamically select which engine(s) to use via
// engineID.
if (engineID == 0) {
SubmitGzipTasksSingleEngine<0>(q, block_size, pibuf, pobuf, gzip_out_buf,
result_crc, last_block, e_crc, e_lz, e_huff);
}
#if NUM_ENGINES > 1
if (engineID == 1) {
SubmitGzipTasksSingleEngine<1>(q, block_size, pibuf, pobuf, gzip_out_buf,
result_crc, last_block, e_crc, e_lz, e_huff);
}
#endif
// If this reference design is to be expanded to > 2 engines, declare them here.
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/**
* Feeder A Kernel.
*
* Reads all "num_matrices" matrices from FPGA DDR "elems_per_ddr_access"
* elements at a time and stores to on-chip memory. Then writes out matrices
* tile by tile to the pipe, "tile_a" elements at a time. Matrices must be
* provided in column-major order.
*
* Repeats this operation "repetitions" times to measure performance.
*
* Coordinates with the other feeder kernel to support matrix tiling by
* repeating each tile accordingly.
*
*/
template <typename TT, // Datatype of the elements of the matrix
int aspace, // Buffer location for mmhost
int rows_a, // Rows of matrix A
int common, // Columns of matrix A / rows of matrix B
int cols_b, // Columns of matrix B
int tile_a, // Tile size for matrix A
int tile_b, // Tile size for matrix B
int elems_per_ddr_access, // Number of elements per DDR access
int num_matrices, // Number of pairs of matrices to multiply
typename PipeA, // Input pipe for matrix
typename PipeDone, // Pipe to notify compute kernel when to stop
// reading inputs
int datawidth = elems_per_ddr_access * sizeof(TT) * 8>
class MatrixReadFromDDRToPipeA {
public:
#if !defined(IS_BSP)
// Customizing mmhost only supported when targetting an FPGA part/family
sycl::ext::oneapi::experimental::annotated_arg<TT *,
decltype(sycl::ext::oneapi::experimental::properties{
sycl::ext::intel::experimental::awidth<28>,
sycl::ext::intel::experimental::buffer_location<aspace>,
sycl::ext::intel::experimental::dwidth<datawidth>,
sycl::ext::intel::experimental::latency<0>,
sycl::ext::intel::experimental::maxburst<1>,
sycl::ext::intel::experimental::read_write_mode_read,
sycl::ext::intel::experimental::wait_request_requested})>
#else
TT *
#endif
a_ptr; // Input matrix pointer
int repetitions; // Number of times to write the same matrix to the pipe
void operator()() const {
// May need to perform incomplete memory read if access size doesn't evenly
// divide the matrix size
constexpr bool kIncompleteBurst = rows_a % elems_per_ddr_access != 0;
// Number of tiles
constexpr int kBlocksA = rows_a / tile_a;
constexpr int kBlocksB = cols_b / tile_b;
// Number of iterations to read from DDR to on-chip memory
constexpr int kItersPerRowCol =
rows_a / elems_per_ddr_access + (kIncompleteBurst ? 1 : 0);
constexpr int kItersToMem = common * kItersPerRowCol;
constexpr int kItersToMemBitSize =
fpga_tools::BitsForMaxValue<kItersToMem + 1>();
// Number of iterations to write matrices out to pipe
constexpr int kItersToPipe = kBlocksA * kBlocksB * common;
constexpr int kItersToPipeBitSize =
fpga_tools::BitsForMaxValue<kItersToPipe + 1>();
// Size of a full matrix
constexpr int kMatsize = rows_a * common;
// Memory attributes
constexpr short kBankWidth = elems_per_ddr_access * sizeof(TT);
constexpr int kNumBanks =
fpga_tools::Pow2(fpga_tools::CeilLog2(rows_a / elems_per_ddr_access));
#if defined(IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer lives on
// the device.
// Knowing this, the compiler won't generate hardware to potentially get
// data from the host.
sycl::device_ptr<TT> a_ptr_located(a_ptr);
#else
// Device pointers are not supported when targeting an FPGA family/part
TT *a_ptr_located(a_ptr);
#endif
// Local memory to store the matrices
[[intel::numbanks(kNumBanks)]] // NO-FORMAT: Attribute
[[intel::bankwidth(kBankWidth)]] // NO-FORMAT: Attribute
[[intel::private_copies(1)]] // NO-FORMAT: Attribute
[[intel::max_replicates(1)]] // NO-FORMAT: Attribute
TT mem[num_matrices][common][rows_a];
// Copy all "num_matrices" matrices from FPGA DDR into on-chip memory
for (int mat = 0; mat < num_matrices; mat++) {
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kItersToMemBitSize, false> i = 0; i < kItersToMem; i++) {
int write_idx = i % kItersPerRowCol;
[[intel::fpga_register]] // NO-FORMAT: Attribute
TT load_reg[elems_per_ddr_access];
// Perform the read of "elems_per_ddr_access" elements into register
// Only perform the reads that are relevant (and don't access a memory
// address that may be beyond last matrix address)
fpga_tools::UnrolledLoop<elems_per_ddr_access>([&](auto k) {
if ((write_idx * elems_per_ddr_access + k) < rows_a) {
int ptr_idx = (mat * kMatsize) +
(((int)(i) / kItersPerRowCol) * rows_a) +
(write_idx * elems_per_ddr_access) + k;
load_reg[k] = a_ptr_located[ptr_idx];
}
});
// Store the "elems_per_ddr_access" elements into on-chip memory
fpga_tools::UnrolledLoop<kItersPerRowCol>([&](auto k) {
write_idx = sycl::ext::intel::fpga_reg(write_idx);
fpga_tools::UnrolledLoop<elems_per_ddr_access>([&](auto t) {
load_reg[t] = sycl::ext::intel::fpga_reg(load_reg[t]);
if constexpr ((k * elems_per_ddr_access + t) < rows_a) {
if (write_idx == k) {
mem[mat][i / kItersPerRowCol][k * elems_per_ddr_access + t] =
load_reg[t];
}
}
});
});
} // end of i
} // end of mat
// Write every tile of all "num_matrices" matrices to the pipe; repeating
// this operation "repetitions" times to measure performance.
[[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute
for (int rep = 0; rep < repetitions; rep++) {
for (int mat = 0; mat < num_matrices; mat++) {
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kItersToPipeBitSize, false> i = 0; i < kItersToPipe; i++) {
int block = i / (kBlocksB * common);
bool get[kBlocksA];
fpga_tools::UnrolledLoop<kBlocksA>([&](auto k) {
block = sycl::ext::intel::fpga_reg(block);
get[k] = block == k;
});
// Write one column of a matrix tile to the pipe
fpga_tools::NTuple<TT, tile_a> pipe_write;
fpga_tools::UnrolledLoop<kBlocksA>([&](auto k) {
fpga_tools::UnrolledLoop<tile_a>([&](auto t) {
pipe_write.template get<t>() =
get[k] ? mem[mat][i % common][k * tile_a + t]
: sycl::ext::intel::fpga_reg(
pipe_write.template get<t>());
});
});
bool last_pipe_write = (rep == repetitions - 1) &
(mat == num_matrices - 1) &
(i == kItersToPipe - 1);
PipeA::write(pipe_write);
PipeDone::write(last_pipe_write);
} // end of i
} // end of mat
} // end of rep
} // end of operator
};
/**
* Feeder B kernel.
*
* Reads all "num_matrices" matrices from FPGA DDR "elems_per_ddr_access"
* elements at a time and stores to on-chip memory. Then writes out matrices
* tile by tile to the pipe, "tile_b" elements at a time. Matrices must be
* provided in row-major order (or, equivalently, given as the transpose).
*
* Repeats this operation "repetitions" times to measure performance.
*
* Coordinates with the other feeder kernel to support matrix tiling by
* repeating each tile accordingly.
*
*/
template <typename TT, // Datatype of the elements of the matrix
int aspace, // Buffer location for mmhost
int rows_a, // Rows of matrix A
int common, // Columns of matrix A / rows of matrix B
int cols_b, // Columns of matrix B
int tile_a, // Tile size for matrix A
int tile_b, // Tile size for matrix B
int elems_per_ddr_access, // Number of elements per DDR access
int num_matrices, // Number of pairs of matrices to multiply
typename PipeB, // Input pipe for matrix
int datawidth = elems_per_ddr_access * sizeof(TT) * 8>
class MatrixReadFromDDRToPipeB {
public:
#if !defined(IS_BSP)
// Customizing mmhost only supported when targetting an FPGA part/family
sycl::ext::oneapi::experimental::annotated_arg<TT *,
decltype(sycl::ext::oneapi::experimental::properties{
sycl::ext::intel::experimental::awidth<28>,
sycl::ext::intel::experimental::buffer_location<aspace>,
sycl::ext::intel::experimental::dwidth<datawidth>,
sycl::ext::intel::experimental::latency<0>,
sycl::ext::intel::experimental::maxburst<1>,
sycl::ext::intel::experimental::read_write_mode_read,
sycl::ext::intel::experimental::wait_request_requested})>
#else
TT *
#endif
b_ptr; // Input matrix pointer
int repetitions; // Number of times to write the same matrix to the pipe
void operator()() const {
// May need to perform incomplete memory read if access size doesn't evenly
// divide the matrix size
constexpr bool kIncompleteBurst = cols_b % elems_per_ddr_access != 0;
// Number of tiles
constexpr int kBlocksA = rows_a / tile_a;
constexpr int kBlocksB = cols_b / tile_b;
// Number of iterations to read from DDR to on-chip memory
constexpr int kItersPerRowCol =
cols_b / elems_per_ddr_access + (kIncompleteBurst ? 1 : 0);
constexpr int kItersToMem = common * kItersPerRowCol;
constexpr int kItersToMemBitSize =
fpga_tools::BitsForMaxValue<kItersToMem + 1>();
// Number of iterations to write matrices out to pipe
constexpr int kItersToPipe = kBlocksA * kBlocksB * common;
constexpr int kItersToPipeBitSize =
fpga_tools::BitsForMaxValue<kItersToPipe + 1>();
// Size of a full matrix
constexpr int kMatsize = cols_b * common;
// Memory attributes
constexpr short kBankWidth = elems_per_ddr_access * sizeof(TT);
constexpr int kNumBanks =
fpga_tools::Pow2(fpga_tools::CeilLog2(cols_b / elems_per_ddr_access));
#if defined(IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer lives on
// the device.
// Knowing this, the compiler won't generate hardware to potentially get
// data from the host.
sycl::device_ptr<TT> b_ptr_located(b_ptr);
#else
// Device pointers are not supported when targeting an FPGA family/part
TT *b_ptr_located(b_ptr);
#endif
// Local memory to store the matrices
[[intel::numbanks(kNumBanks)]] // NO-FORMAT: Attribute
[[intel::bankwidth(kBankWidth)]] // NO-FORMAT: Attribute
[[intel::private_copies(1)]] // NO-FORMAT: Attribute
[[intel::max_replicates(1)]] // NO-FORMAT: Attribute
TT mem[num_matrices][common][cols_b];
// Copy all "num_matrices" matrices from FPGA DDR into on-chip memory
for (int mat = 0; mat < num_matrices; mat++) {
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kItersToMemBitSize, false> i = 0; i < kItersToMem; i++) {
int write_idx = i % kItersPerRowCol;
[[intel::fpga_register]] // NO-FORMAT: Attribute
TT load_reg[elems_per_ddr_access];
// Perform the read of "elems_per_ddr_access" elements into register
// Only perform the reads that are relevant (and don't access a memory
// address that may be beyond last matrix address)
fpga_tools::UnrolledLoop<elems_per_ddr_access>([&](auto k) {
if ((write_idx * elems_per_ddr_access + k) < cols_b) {
int ptr_idx = (mat * kMatsize) +
(((int)(i) / kItersPerRowCol) * cols_b) +
(write_idx * elems_per_ddr_access) + k;
load_reg[k] = b_ptr_located[ptr_idx];
}
});
// Store the "elems_per_ddr_access" elements into on-chip memory
fpga_tools::UnrolledLoop<kItersPerRowCol>([&](auto k) {
write_idx = sycl::ext::intel::fpga_reg(write_idx);
fpga_tools::UnrolledLoop<elems_per_ddr_access>([&](auto t) {
load_reg[t] = sycl::ext::intel::fpga_reg(load_reg[t]);
if constexpr ((k * elems_per_ddr_access + t) < cols_b) {
if (write_idx == k) {
mem[mat][i / kItersPerRowCol][k * elems_per_ddr_access + t] =
load_reg[t];
}
}
});
});
} // end of i
} // end of mat
// Write every tile of all "num_matrices" matrices to the pipe; repeating
// this operation "repetitions" times to measure performance.
[[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute
for (int rep = 0; rep < repetitions; rep++) {
for (int mat = 0; mat < num_matrices; mat++) {
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kItersToPipeBitSize, false> i = 0; i < kItersToPipe; i++) {
int block = (i % (kBlocksB * common)) / common;
bool get[kBlocksB];
fpga_tools::UnrolledLoop<kBlocksB>([&](auto k) {
block = sycl::ext::intel::fpga_reg(block);
get[k] = block == k;
});
// Write one row of a matrix tile to the pipe
fpga_tools::NTuple<TT, tile_b> pipe_write;
fpga_tools::UnrolledLoop<kBlocksB>([&](auto k) {
fpga_tools::UnrolledLoop<tile_b>([&](auto t) {
pipe_write.template get<t>() =
get[k] ? mem[mat][i % common][k * tile_b + t]
: sycl::ext::intel::fpga_reg(
pipe_write.template get<t>());
});
});
PipeB::write(pipe_write);
} // end of i
} // end of mat
} // end of rep
} // end of operator
};
/**
* Drain Kernel.
*
* Reads all "num_matrices" matrices tile by tile from the pipe into local
* memory, "tile_a" elements at a time. Then writes the final matrix to FPGA DDR
* "elems_per_ddr_access" elements at a time. Matrices are stored in
* column-major order.
*
* Repeats this operation "repetitions" times.
*
*/
template <typename TT, // Datatype of the elements of the matrix
int aspace, // Buffer location for mmhost
int rows_a, // Rows of matrix A
int cols_b, // Columns of matrix B
int tile_a, // Tile size for matrix A
int tile_b, // Tile size for matrix B
int elems_per_ddr_access, // Number of elements per DDR access
int num_matrices, // Number of pairs of matrices to multiply
typename PipeC, // Output pipe for matrix
int datawidth = elems_per_ddr_access * sizeof(TT) * 8>
class MatrixReadPipeToDDR {
public:
#if !defined(IS_BSP)
// Customizing mmhost only supported when targetting an FPGA part/family
sycl::ext::oneapi::experimental::annotated_arg<TT *,
decltype(sycl::ext::oneapi::experimental::properties{
sycl::ext::intel::experimental::awidth<28>,
sycl::ext::intel::experimental::buffer_location<aspace>,
sycl::ext::intel::experimental::dwidth<datawidth>,
sycl::ext::intel::experimental::latency<0>,
sycl::ext::intel::experimental::maxburst<1>,
sycl::ext::intel::experimental::read_write_mode_write,
sycl::ext::intel::experimental::wait_request_requested})>
#else
TT *
#endif
c_ptr; // Input matrix pointer
int repetitions; // Number of time to read the same matrix to the pipe
void operator()() const {
// May need to perform incomplete memory read if DDR access size doesn't
// evenly divide the tile size
constexpr bool kIncompleteBurst = rows_a % elems_per_ddr_access != 0;
// Number of tiles
constexpr int kBlocksA = rows_a / tile_a;
constexpr int kBlocksB = cols_b / tile_b;
// Number of iterations to read matrices from pipe
constexpr int kItersFromPipe = kBlocksA * kBlocksB * tile_b;
constexpr int kItersFromPipeBitSize =
fpga_tools::BitsForMaxValue<kItersFromPipe + 1>();
// Number of iterations to write from on-chip memory to DDR
constexpr int kItersPerRowCol =
rows_a / elems_per_ddr_access + (kIncompleteBurst ? 1 : 0);
constexpr int kItersFromMem = cols_b * kItersPerRowCol;
constexpr int kItersFromMemBitSize =
fpga_tools::BitsForMaxValue<kItersFromMem + 1>();
// Size of a full matrix
constexpr int kMatsize = rows_a * cols_b;
// Memory attributes
constexpr short kBankWidth = elems_per_ddr_access * sizeof(TT);
constexpr int kNumBanks =
fpga_tools::Pow2(fpga_tools::CeilLog2(rows_a / elems_per_ddr_access));
#if defined(IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer lives on
// the device.
// Knowing this, the compiler won't generate hardware to potentially get
// data from the host.
sycl::device_ptr<TT> c_ptr_located(c_ptr);
#else
// Device pointers are not supported when targeting an FPGA family/part
TT *c_ptr_located(c_ptr);
#endif
// Local memory to store the matrices
[[intel::numbanks(kNumBanks)]] // NO-FORMAT: Attribute
[[intel::bankwidth(kBankWidth)]] // NO-FORMAT: Attribute
[[intel::private_copies(1)]] // NO-FORMAT: Attribute
[[intel::max_replicates(1)]] // NO-FORMAT: Attribute
TT mem[num_matrices][cols_b][rows_a];
// Read every tile of all "num_matrices" matrices from the pipe into on-chip
// memory; this operation was repeated "repetitions" times to measure
// performance.
[[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute
for (int rep = 0; rep < repetitions; rep++) {
for (int mat = 0; mat < num_matrices; mat++) {
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kItersFromPipeBitSize, false> i = 0; i < kItersFromPipe;
i++) {
int block_a = i / (kBlocksB * tile_b);
int block_b = (i % (kBlocksB * tile_b)) / tile_b;
// Read one column of a tile of the matrix from the pipe and store to
// on-chip memory "mem"
fpga_tools::NTuple<TT, tile_a> pipe_read = PipeC::read();
fpga_tools::UnrolledLoop<kBlocksA>([&](auto k) {
block_a = sycl::ext::intel::fpga_reg(block_a);
fpga_tools::UnrolledLoop<tile_a>([&](auto t) {
pipe_read.template get<t>() =
sycl::ext::intel::fpga_reg(pipe_read.template get<t>());
if (block_a == k) {
mem[mat][block_b * tile_b + (i % tile_b)][k * tile_a + t] =
pipe_read.template get<t>();
}
});
});
} // end of i
} // end of mat
} // end of rep
// Copy all matrices from on-chip memory "mem" to FPGA DDR
for (int mat = 0; mat < num_matrices; mat++) {
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kItersFromMemBitSize, false> i = 0; i < kItersFromMem; i++) {
int write_idx = i % kItersPerRowCol;
bool get[kItersPerRowCol];
fpga_tools::UnrolledLoop<kItersPerRowCol>([&](auto k) {
write_idx = sycl::ext::intel::fpga_reg(write_idx);
get[k] = write_idx == k;
});
[[intel::fpga_register]] // NO-FORMAT: Attribute
TT load_reg[elems_per_ddr_access];
// Load "elems_per_ddr_access" items from on-chip memory into register
fpga_tools::UnrolledLoop<kItersPerRowCol>([&](auto k) {
fpga_tools::UnrolledLoop<elems_per_ddr_access>([&](auto t) {
if constexpr ((k * elems_per_ddr_access + t) < rows_a) {
load_reg[t] = get[k] ? mem[mat][i / kItersPerRowCol]
[k * elems_per_ddr_access + t]
: sycl::ext::intel::fpga_reg(load_reg[t]);
}
});
});
// Perform the write of "elems_per_ddr_access" elements to DDR
// Only perform the writes that are relevant (and don't access a memory
// address that may be beyond last matrix address)
fpga_tools::UnrolledLoop<elems_per_ddr_access>([&](auto k) {
if ((write_idx * elems_per_ddr_access + k) < rows_a) {
int ptr_idx = (mat * kMatsize) +
(((int)(i) / kItersPerRowCol) * rows_a) +
(write_idx * elems_per_ddr_access) + k;
c_ptr_located[ptr_idx] = load_reg[k];
}
});
} // end of i
} // end of mat
} // end of operator
};
#endif /* __MEMORY_TRANSFERS_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/matmul.hpp | #ifndef __MATMUL_HPP__
#define __MATMUL_HPP__
#include <iostream>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "memory_transfers.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "streaming_matmul.hpp"
#if not defined(IS_BSP)
using sycl::ext::intel::experimental::property::usm::buffer_location;
#endif
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class FeederA;
class FeederB;
class Matmul;
class Drain;
class APipe;
class BPipe;
class CPipe;
class DonePipe;
/**
* Implementation of the matrix multiplication using multiple streaming kernels.
* Parameterized by datatype, matrix size, and tile size. Exercises the kernels
* by running multiple repetitions for a set of matrices.
*
* Function arguments:
* q: device queue
* a_matrix: input matrix pointer (given in column-major)
* b_matrix: input matrix pointer (given in row-major, i.e., transposed)
* c_matrix: output matrix pointer (will be stored in column-major)
* repetitions: number of repetitions of the computation to execute
*
*/
template <typename TT, // Datatype of the elements of the matrix
int rows_a, // Rows of matrix A
int common, // Columns of matrix A / rows of matrix B
int cols_b, // Columns of matrix B
int tile_a, // Tile size for matrix A
int tile_b, // Tile size for matrix B
int num_matrices> // Number of pairs of matrices to multiply
void MatmulImpl(sycl::queue &q, // Device queue
std::vector<TT> &a_matrix, // Input matrix A
std::vector<TT> &b_matrix, // Input matrix B
std::vector<TT> &c_matrix, // Output matrix C = A * B
int repetitions // Number of repetitions
) {
// Number of elements per DDR access
// NOTE: optimized for single-precision floating-point matrices
constexpr int kElemsPerDDRAccess = 8;
// Matrix sizes
constexpr int kMatsizeA = rows_a * common;
constexpr int kMatsizeB = cols_b * common;
constexpr int kMatsizeC = rows_a * cols_b;
// Buffer locations for mmhost interfaces
constexpr int kBL1 = 1;
constexpr int kBL2 = 2;
constexpr int kBL3 = 3;
// Allocate FPGA DDR memory
#if defined(IS_BSP)
TT *a = sycl::malloc_device<TT>(kMatsizeA * num_matrices, q);
TT *b = sycl::malloc_device<TT>(kMatsizeB * num_matrices, q);
TT *c = sycl::malloc_device<TT>(kMatsizeC * num_matrices, q);
#else
// malloc_device are not supported when targetting an FPGA part/family
TT *a = sycl::malloc_shared<TT>(kMatsizeA * num_matrices, q,
sycl::property_list{buffer_location(kBL1)});
TT *b = sycl::malloc_shared<TT>(kMatsizeB * num_matrices, q,
sycl::property_list{buffer_location(kBL2)});
TT *c = sycl::malloc_shared<TT>(kMatsizeC * num_matrices, q,
sycl::property_list{buffer_location(kBL3)});
#endif
// Copy matrices over
q.memcpy(a, a_matrix.data(), kMatsizeA * num_matrices * sizeof(TT)).wait();
q.memcpy(b, b_matrix.data(), kMatsizeB * num_matrices * sizeof(TT)).wait();
using PipeDataA = fpga_tools::NTuple<TT, tile_a>;
using PipeDataB = fpga_tools::NTuple<TT, tile_b>;
using PipeDataC = fpga_tools::NTuple<TT, tile_a>;
// Pipes to communicate the matrices between kernels
using PipeA = sycl::ext::intel::pipe<APipe, PipeDataA, 64>;
using PipeB = sycl::ext::intel::pipe<BPipe, PipeDataB, 64>;
using PipeC = sycl::ext::intel::pipe<CPipe, PipeDataC, 64>;
using PipeDone = sycl::ext::intel::pipe<DonePipe, bool, 64>;
// Producer kernel for matrix A
auto feeder_a_event = q.single_task<FeederA>(
MatrixReadFromDDRToPipeA<TT, kBL1, rows_a, common, cols_b, tile_a, tile_b,
kElemsPerDDRAccess, num_matrices, PipeA,
PipeDone>{a, repetitions});
// Producer kernel for matrix B
auto feeder_b_event = q.single_task<FeederB>(
MatrixReadFromDDRToPipeB<TT, kBL2, rows_a, common, cols_b, tile_a, tile_b,
kElemsPerDDRAccess, num_matrices, PipeB>{
b, repetitions});
// Matrix multiply kernel
q.single_task<Matmul>(
fpga_linalg::StreamingMatmul<TT, common, tile_a, tile_b, PipeA, PipeB,
PipeC, PipeDone>{});
// Consumer kernel for matrix C
auto drain_event = q.single_task<Drain>(
MatrixReadPipeToDDR<TT, kBL3, rows_a, cols_b, tile_a, tile_b,
kElemsPerDDRAccess, num_matrices, PipeC>{
c, repetitions});
feeder_a_event.wait();
feeder_b_event.wait();
drain_event.wait();
// Compute the total time the execution lasted
auto start_time = feeder_a_event.template get_profiling_info<
sycl::info::event_profiling::command_start>();
auto end_time = drain_event.template get_profiling_info<
sycl::info::event_profiling::command_end>();
double diff = (end_time - start_time) / 1.0e9;
std::cout << " Total duration: " << diff << " s" << std::endl;
std::cout << "Throughput: " << repetitions * num_matrices / diff * 1e-3
<< "k matrices/s" << std::endl;
// Copy result matrix back
q.memcpy(c_matrix.data(), c, kMatsizeC * num_matrices * sizeof(TT)).wait();
// Free USM
sycl::free(a, q);
sycl::free(b, q);
sycl::free(c, q);
}
#endif /* __MATMUL_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/matmul_demo.cpp | #include <iomanip>
#include <iostream>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include "exception_handler.hpp"
#include "matmul.hpp"
// Fills a matrix with random numbers within the range [l_bound, u_bound).
void FillRand(std::vector<float> &m_matrix, int l_bound, int u_bound,
int elements) {
for (int element = 0; element < elements; element++) {
m_matrix[element] =
static_cast<float>(rand()) /
(static_cast<float>((RAND_MAX) / (u_bound - l_bound))) +
l_bound;
}
}
// Compares num_matrices pairs of matrices; returns true iff they are equal
// given a tolerated error bound.
bool EqualMat(std::vector<float> &c_matrix, std::vector<float> &c_reference,
int rows, int cols, int num_matrices) {
int matsize = rows * cols;
bool passed = true;
// Floating-point error threshold value
constexpr float kEpsilon = 0.01f;
for (int matrix_idx = 0; matrix_idx < num_matrices; matrix_idx++) {
for (int col = 0; col < cols; col++) {
for (int row = 0; row < rows; row++) {
int idx = matrix_idx * matsize + col * rows + row;
if (abs(c_matrix[idx] - c_reference[idx]) > kEpsilon) {
passed = false;
#if DEBUG
std::cout << "Error: C[" << col << "][" << row << "] = "
<< c_matrix[idx]
<< " but REF[" << col << "][" << row << "] = "
<< c_reference[idx] << std::endl;
#endif
}
if (!std::isfinite(c_matrix[idx])) {
passed = false;
#if DEBUG
std::cout << "C[" << col << "][" << row << "] = " << c_matrix[idx]
<< " is not finite" << std::endl;
#endif
}
}
}
}
return passed;
}
// Output a matrix to the screen (assumes column-major format).
void PrintMat(std::vector<float> &m_matrix, int rows, int cols) {
for (int row = 0; row < rows; row++) {
for (int col = 0; col < cols; col++) {
// Copy old state of cout
std::ios oldState(nullptr);
oldState.copyfmt(std::cout);
// Edit the output format of cout
std::cout << std::fixed << std::setprecision(2);
// Print the results
std::cout << std::setw(8) << m_matrix[col * rows + row] << " ";
// Restore the output format of cout
std::cout.copyfmt(oldState);
}
std::cout << std::endl;
}
}
// Transpose num_matrices matrices in m_matrix and store the results in
// m_transposed.
void TransposeMat(std::vector<float> &m_matrix,
std::vector<float> &m_transposed, int rows, int cols,
int num_matrices) {
int matsize = rows * cols;
for (int matrix_idx = 0; matrix_idx < num_matrices; matrix_idx++) {
for (int row = 0; row < rows; row++) {
for (int col = 0; col < cols; col++) {
m_transposed[matrix_idx * matsize + row * cols + col] =
m_matrix[matrix_idx * matsize + col * rows + row];
}
}
}
}
// Multiply num_matrices pairs of matrices from a_matrix and b_matrix and store
// all the results in c_matrix.
void MatmulRef(std::vector<float> &a_matrix, std::vector<float> &b_matrix,
std::vector<float> &c_matrix, int rows_a, int common, int cols_b,
int num_matrices) {
int matsize_a = rows_a * common;
int matsize_b = cols_b * common;
int matsize_c = rows_a * cols_b;
for (int matrix_idx = 0; matrix_idx < num_matrices; matrix_idx++) {
for (int col = 0; col < cols_b; col++) {
for (int row = 0; row < rows_a; row++) {
float sum = 0;
for (int k = 0; k < common; k++) {
sum += a_matrix[matrix_idx * matsize_a + k * rows_a + row] *
b_matrix[matrix_idx * matsize_b + col * common + k];
}
c_matrix[matrix_idx * matsize_c + col * rows_a + row] = sum;
}
}
}
}
int main(int argc, char *argv[]) {
// Matrix paramters specified by build system
constexpr int kRowsA = ROWS_A;
constexpr int kCommon = COMMON;
constexpr int kColsB = COLS_B;
constexpr int kTileA = TILE_A;
constexpr int kTileB = TILE_B;
// Matrix sizes
constexpr int kMatsizeA = kRowsA * kCommon;
constexpr int kMatsizeB = kColsB * kCommon;
constexpr int kMatsizeC = kRowsA * kColsB;
// Repetitions and number of matrices to measure performance
#if FPGA_SIMULATOR
int repetitions = argc > 1 ? atoi(argv[1]) : 1;
constexpr int kNumMatrices = 1;
#elif FPGA_HARDWARE
int repetitions = argc > 1 ? atoi(argv[1]) : 819200;
constexpr int kNumMatrices = 2;
#else // #if FPGA_EMULATOR
int repetitions = argc > 1 ? atoi(argv[1]) : 16;
constexpr int kNumMatrices = 2;
#endif
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::property_list queue_properties{
sycl::property::queue::enable_profiling()};
sycl::queue q =
sycl::queue(selector, fpga_tools::exception_handler, queue_properties);
std::cout << "Running on device: "
<< q.get_device().get_info<sycl::info::device::name>().c_str()
<< std::endl;
// Create arrays to hold the input and output matrices
std::vector<float> a_matrix(kMatsizeA * kNumMatrices);
std::vector<float> b_matrix(kMatsizeB * kNumMatrices);
std::vector<float> c_matrix(kMatsizeC * kNumMatrices);
// Generate random A and B matrices
constexpr int kRandMin = 1;
constexpr int kRandMax = 10;
srand(1138);
FillRand(a_matrix, kRandMin, kRandMax, kMatsizeA * kNumMatrices);
FillRand(b_matrix, kRandMin, kRandMax, kMatsizeB * kNumMatrices);
// Calculate a reference to compare our answer to and store it in c_reference
// NOTE: since the systolic matrix multiply interprets B as transposed, we
// need to first transpose b_matrix to b_transposed to use it in the standard
// MM algorithm
std::vector<float> b_transposed(kMatsizeB * kNumMatrices);
std::vector<float> c_reference(kMatsizeC * kNumMatrices);
TransposeMat(b_matrix, b_transposed, kColsB, kCommon, kNumMatrices);
MatmulRef(a_matrix, b_transposed, c_reference, kRowsA, kCommon, kColsB,
kNumMatrices);
std::cout << " Matrix A size: " << kRowsA << " x " << kCommon
<< " (tile: " << kTileA << " x " << kCommon << ")" << std::endl
<< " Matrix B size: " << kCommon << " x " << kColsB
<< " (tile: " << kCommon << " x " << kTileB << ")" << std::endl
<< " Systolic array size: " << kTileA << " x " << kTileB << " PEs"
<< std::endl;
std::cout << "Running matrix multiplication of " << kNumMatrices
<< ((kNumMatrices > 1) ? " matrices " : " matrix ") << repetitions
<< " times" << std::endl;
// Run the matrix multiplication
MatmulImpl<float, kRowsA, kCommon, kColsB, kTileA, kTileB, kNumMatrices>(
q, a_matrix, b_matrix, c_matrix, repetitions);
#if DEBUG
// Print A, B, C and reference matrices
for (int matrix_idx = 0; matrix_idx < kNumMatrices; matrix_idx++) {
std::cout << std::endl << matrix_idx << std::endl;
std::cout << std::endl << "Matrix A" << std::endl;
std::vector<float> a_vector = {
a_matrix.begin() + matrix_idx * kMatsizeA,
a_matrix.begin() + (matrix_idx + 1) * kMatsizeA};
PrintMat(a_vector, kRowsA, kCommon);
std::cout << std::endl << "Matrix B" << std::endl;
std::vector<float> b_vector = {
b_transposed.begin() + matrix_idx * kMatsizeB,
b_transposed.begin() + (matrix_idx + 1) * kMatsizeB};
PrintMat(b_vector, kCommon, kColsB);
std::cout << std::endl << "Matrix C reference" << std::endl;
std::vector<float> c_ref_vector = {
c_reference.begin() + matrix_idx * kMatsizeC,
c_reference.begin() + (matrix_idx + 1) * kMatsizeC};
PrintMat(c_ref_vector, kRowsA, kColsB);
std::cout << std::endl << "Matrix C calculated" << std::endl;
std::vector<float> c_vector = {
c_matrix.begin() + matrix_idx * kMatsizeC,
c_matrix.begin() + (matrix_idx + 1) * kMatsizeC};
PrintMat(c_vector, kRowsA, kColsB);
}
#endif
// Verify results
bool passed = EqualMat(c_matrix, c_reference, kRowsA, kColsB, kNumMatrices);
std::cout << std::endl << (passed ? "PASSED" : "FAILED") << std::endl;
return !passed;
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::cerr << " If you are targeting an FPGA hardware, "
"ensure that your system is plugged to an FPGA board that is "
"set up correctly"
<< std::endl;
std::cerr << " If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR"
<< std::endl;
std::terminate();
}
} // end of main | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/MVDR.hpp | #ifndef __MVDR_HPP__
#define __MVDR_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <array>
// utility classes
#include "mvdr_complex.hpp"
#include "pipe_utils.hpp" // Included from DirectProgramming/C++SYCL_FPGA/include/
// MVDR processing kernels
#include "BackwardSubstitution.hpp"
#include "Beamformer.hpp"
#include "CalcWeights.hpp"
#include "ForwardSubstitution.hpp"
#include "InputDemux.hpp"
#include "SteeringVectorGenerator.hpp"
#include "StreamingQRDWrapper.hpp"
#include "DiagReciprocal.hpp"
#include "Transpose.hpp"
using namespace sycl;
// Names of kernels launched by SubmitMVDRKernels.
// This enum should be used to access elements in the returned vector of events.
enum class MVDRKernelNames {
input_demux,
transpose,
streaming_qrd,
diag_reciprocal,
steering_vector_generator,
forward_substitution,
backward_substitution,
calc_weights,
beamformer,
// count must come last
count
};
using MVDREventArray =
std::array<event, static_cast<int>(MVDRKernelNames::count)>;
// forward declare the names of all kernels to prevent name mangling
template <size_t k_instance_num>
class InputDemux;
template <size_t k_instance_num>
class Transpose;
template <size_t k_instance_num>
class StreamingQRD;
template <size_t k_instance_num>
class DiagReciprocal;
template <size_t k_instance_num>
class SteeringVectorGenerator;
template <size_t k_instance_num>
class ForwardSubstitution;
template <size_t k_instance_num>
class BackwardSubstitution;
template <size_t k_instance_num>
class CalcWeights;
template <size_t k_instance_num>
class Beamformer;
// forward declare the names of all pipes and pipe duplicators to prevent name
// mangling
template <size_t k_instance_num>
class TrainingDataPipeID;
template <size_t k_instance_num>
class XrxDataPipeID;
template <size_t k_instance_num>
class SteeringVectorsPipeID;
template <size_t k_instance_num>
class UpdateSteeringVectorsPipeID;
template <size_t k_instance_num>
class ForwardSteeringVectorsPipeID;
template <size_t k_instance_num>
class QMatrixPipeID;
template <size_t k_instance_num>
class RMatrixPipesID;
template <size_t k_instance_num>
class RDiagRecipVectorPipesID;
template <size_t k_instance_num>
class ForwardSubstitutionResultPipeID;
template <size_t k_instance_num>
class YVectorsPipeID;
template <size_t k_instance_num>
class WeightVectorsPipeID;
template <size_t k_instance_num>
class TransposedTrainingDataPipeID;
template <size_t k_instance_num>
class TrainingDataDupPipeID;
template <size_t k_instance_num>
class XrxDataDupPipeID;
template <size_t k_instance_num>
class SteeringVectorsDupPipeID;
template <size_t k_instance_num>
class ForwardSteeringVectorsDupPipeID;
template <size_t k_instance_num>
class RMatrixDupPipeID;
template <size_t k_instance_num>
class RDiagRecipVectorDupPipeID;
template <size_t k_instance_num>
class ForwardSubstitutionResultDupPipeID;
template <size_t k_instance_num>
class YVectorsDupPipeID;
template <size_t k_instance_num>
class WeightVectorsDupPipeID;
template <size_t k_instance_num>
class TransposedTrainingDataDupPipeID;
class MVDRNullPipeID;
// SubmitMVDRKernels
// Launch all the kernels to perform MVDR processing.
// Return a vector of events, one for each kernel
template <
size_t k_num_sensor_inputs, // number of sensor array inputs
size_t k_rmb_factor, // Reed-Mallett-Brennan rule
// Number of 'rows' of sensor data used
// by the QRD is k_num_sensor_inputs *
// k_rmb_factor (generally 2-5)
size_t k_num_steering_vectors, // number of steering vectors to apply to
// each input sample
size_t k_subst_unroll_factor, // unroll factor used by the forward and
// backward substitution kernels
size_t k_beam_unroll_factor, // unroll factor used by beamformer
size_t k_qrd_min_iterations, // minimum 'inner loop' iterations for the
// QRD kernel, this number can be tuned
// for best throughput
size_t k_num_complex_per_xrx_read, // Number of complex numbers (contained
// in NTuple) per read from the
// Xrx input pipes
typename DataInPipe, // Sensor data to be processed. Includes
// embedded headers to identify training
// and processing data
// Accept an NTuple containing
// k_num_complex_per_xrx_read complex
// floats per read
typename SinThetaInPipe, // sin(theta) input for generating
// steering vectors. Updated by another
// kernel with updates from the host.
// Accept one float per read.
typename DataOutPipe, // For each Xrx input data vector, send
// an output for each of the Weight
// vectors.
// Send one complex float per write.
size_t k_instance_num = 0, // To allow more than one MVDR instance
// in a system, provide a unique
// instance_num to each.
// copies of internal pipes, useful for debugging or other processing
// all default to 'null' pipes that go nowhere
typename TrainingDataPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID,
fpga_tools::NTuple<ComplexType, k_num_complex_per_xrx_read>>,
typename XrxDataPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID,
fpga_tools::NTuple<ComplexType, k_num_complex_per_xrx_read>>,
typename SteeringVectorsPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, ComplexType>,
typename ForwardSteeringVectorsPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, ComplexType>,
typename RMatrixPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, ComplexType>,
typename RDiagRecipVectorPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, float>,
typename ForwardSubstitutionResultPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, ComplexType>,
typename YVectorsPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, ComplexType>,
typename WeightVectorsPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID, ComplexType>,
typename TransposedTrainingDataPipeOut =
fpga_tools::PipeDuplicator<MVDRNullPipeID,
fpga_tools::NTuple<ComplexType, k_num_complex_per_xrx_read>>>
MVDREventArray SubmitMVDRKernels(
queue& q,
short num_xrx_per_weights // Number of xrx vectors to process with
// each set of Weight vectors.
) {
constexpr size_t kNumTrainingRows = k_num_sensor_inputs * k_rmb_factor;
constexpr size_t kTrainingMatrixSize = kNumTrainingRows * k_num_sensor_inputs;
// Template parameter checking
// Most template parameters will be checked in individual kernels
static_assert(k_num_sensor_inputs > 0,
"k_num_sensor_inputs must be greater than 0");
static_assert(k_rmb_factor > 0, "k_rmb_factor must be greater than 0");
static_assert(std::numeric_limits<short>::max() > kNumTrainingRows,
"k_num_sensor_inputs * k_rmb_factor must fit in a short");
// Multiple pipes use this type, a group of complex wrapped in an NTuple
using XrxPipeType = fpga_tools::NTuple<ComplexType, k_num_complex_per_xrx_read>;
// Training data pipe (after demux from input data)
constexpr int kTrainingDataPipeMinDepth =
kTrainingMatrixSize / k_num_complex_per_xrx_read;
using TrainingDataPipe =
sycl::ext::intel::pipe<TrainingDataPipeID<k_instance_num>, XrxPipeType,
kTrainingDataPipeMinDepth>;
using TrainingDataDupPipe =
fpga_tools::PipeDuplicator<TrainingDataDupPipeID<k_instance_num>,
XrxPipeType, TrainingDataPipe,
TrainingDataPipeOut>;
// Xrx processing data pipe and duplicator (after demux from input data)
// Must provide sufficient depth to not produce backpressure while training
// data is processed (4 full matrices is adequate)
constexpr int kXrxDataPipeMinDepth =
(kTrainingMatrixSize / k_num_complex_per_xrx_read) * 4;
using XrxDataPipe = sycl::ext::intel::pipe<XrxDataPipeID<k_instance_num>,
XrxPipeType, kXrxDataPipeMinDepth>;
// Steering vector generator pipe and duplicator, and related update pipe
// Connect SteeringVectorGenerator to ForwardSubstitution
constexpr int kSteeringVectorsPipeMinDepth =
k_num_steering_vectors * k_num_sensor_inputs * 2;
using SteeringVectorsPipe =
sycl::ext::intel::pipe<SteeringVectorsPipeID<k_instance_num>, ComplexType,
kSteeringVectorsPipeMinDepth>;
using SteeringVectorsDupPipe =
fpga_tools::PipeDuplicator<SteeringVectorsDupPipeID<k_instance_num>,
ComplexType, SteeringVectorsPipe,
SteeringVectorsPipeOut>;
using UpdateSteeringVectorsPipe =
sycl::ext::intel::pipe<UpdateSteeringVectorsPipeID<k_instance_num>, bool, 1>;
// Pipe for forwarding steering vectors used by ForwardSubstitution to
// CalcWeights and pipe duplicator
using ForwardSteeringVectorsPipe =
sycl::ext::intel::pipe<ForwardSteeringVectorsPipeID<k_instance_num>,
ComplexType, kSteeringVectorsPipeMinDepth>;
using ForwardSteeringVectorsDupPipe =
fpga_tools::PipeDuplicator<
ForwardSteeringVectorsDupPipeID<k_instance_num>, ComplexType,
ForwardSteeringVectorsPipe, ForwardSteeringVectorsPipeOut>;
// R matrix and R matrix reciprocal diagonal entries pipes and duplicator
// Connect StreamingQRD to ForwardSubstitution and BackwardSubstitution
// Need two copies of each so create 1D arrays of Pipes
// Min depth ensures we can hold 2 full R matricies in the pipe, to make sure
// pipe feeding BackwardSubstitution won't overflow while waiting for result
// from ForwardSubstitution.
constexpr int kRMatrixPipeMinDepth =
((k_num_sensor_inputs * (k_num_sensor_inputs + 1)) / 2) * 2;
using RMatrixPipes =
fpga_tools::PipeArray<RMatrixPipesID<k_instance_num>, ComplexType,
kRMatrixPipeMinDepth, 3>;
using RMatrixFSPipe = typename RMatrixPipes::template PipeAt<0>;
using RMatrixBSPipe = typename RMatrixPipes::template PipeAt<1>;
using RMatrixDRPipe = typename RMatrixPipes::template PipeAt<2>;
using RMatrixDupPipe =
fpga_tools::PipeDuplicator<RMatrixDupPipeID<k_instance_num>, ComplexType,
RMatrixFSPipe, RMatrixBSPipe, RMatrixDRPipe, RMatrixPipeOut>;
constexpr int kRDiagRecipVectorPipeMinDepth = k_num_sensor_inputs * 2;
using RDiagRecipVectorPipes =
fpga_tools::PipeArray<RDiagRecipVectorPipesID<k_instance_num>, float,
kRDiagRecipVectorPipeMinDepth, 2>;
using RDiagRecipVectorFSPipe =
typename RDiagRecipVectorPipes::template PipeAt<0>;
using RDiagRecipVectorBSPipe =
typename RDiagRecipVectorPipes::template PipeAt<1>;
using RDiagRecipVectorDupPipe =
fpga_tools::PipeDuplicator<RDiagRecipVectorDupPipeID<k_instance_num>,
float, RDiagRecipVectorFSPipe,
RDiagRecipVectorBSPipe,
RDiagRecipVectorPipeOut>;
// Forward substitution result pipe and duplicator
// Connect ForwardSubstitution to BackwardSubstitution
using ForwardSubstitutionResultPipe =
sycl::ext::intel::pipe<ForwardSubstitutionResultPipeID<k_instance_num>,
ComplexType, k_num_sensor_inputs>;
using ForwardSubstitutionResultDupPipe =
fpga_tools::PipeDuplicator<
ForwardSubstitutionResultDupPipeID<k_instance_num>, ComplexType,
ForwardSubstitutionResultPipe, ForwardSubstitutionResultPipeOut>;
// Y vectors pipe
// Y = (inverse(R x Rtranspose) ) * (complex_conjugate(C)) , where
// R is the R matrix from QRD, and C is the steering vector
// Connect BackwardSubstitution to CalcWeights
using YVectorsPipe = sycl::ext::intel::pipe<YVectorsPipeID<k_instance_num>,
ComplexType, k_num_sensor_inputs>;
using YVectorsDupPipe =
fpga_tools::PipeDuplicator<YVectorsDupPipeID<k_instance_num>,
ComplexType, YVectorsPipe, YVectorsPipeOut>;
// Weight vectors pipe
// Connect CalcWeights to Beamformer
constexpr int kWeightVectorsPipeMinDepth =
k_num_steering_vectors * k_num_sensor_inputs * 2;
using WeightVectorsPipe =
sycl::ext::intel::pipe<WeightVectorsPipeID<k_instance_num>, ComplexType,
kWeightVectorsPipeMinDepth>;
using WeightVectorsDupPipe =
fpga_tools::PipeDuplicator<WeightVectorsDupPipeID<k_instance_num>,
ComplexType, WeightVectorsPipe,
WeightVectorsPipeOut>;
// Q matrix pipe
// Q matrix not used in MVDR design, so this is a 'null' pipe (a
// PipeDuplicator with no output pipes connected)
using QMatrixColumn = fpga_tools::NTuple<ComplexType, k_num_complex_per_xrx_read>;
using QMatrixPipe =
fpga_tools::PipeDuplicator<QMatrixPipeID<k_instance_num>, QMatrixColumn>;
// transposed training data pipe
constexpr int kTransposedTrainingDataPipeMinDepth = kTrainingDataPipeMinDepth;
using TransposedTrainingDataPipe =
sycl::ext::intel::pipe<TransposedTrainingDataPipeID<k_instance_num>,
XrxPipeType, kTransposedTrainingDataPipeMinDepth>;
using TransposedTrainingDataDupPipe =
fpga_tools:: PipeDuplicator<
TransposedTrainingDataDupPipeID<k_instance_num>, XrxPipeType,
TransposedTrainingDataPipe, TransposedTrainingDataPipeOut>;
// array of events to return
// use MVDRKernelNames enum as indicies into the array
MVDREventArray events;
events[static_cast<int>(MVDRKernelNames::input_demux)] =
SubmitInputDemuxKernel<
InputDemux<k_instance_num>, // Name to use for the Kernel
k_num_complex_per_xrx_read, // Number of elements per pipe read/write
kTrainingMatrixSize, // Complex numbers per training matrix
kTrainingMatrixSize, // maximum number of complex numbers in a
// set of xrx data to be matched with each
// training matrix to support
false, // read every cycle (true) or only when
// space is available (false)
DataInPipe, // Incoming data, including headers
TrainingDataDupPipe, // Send training data to QRD
XrxDataPipe // Send sample data to Beamformer
>(q, (int)num_xrx_per_weights * (int)k_num_sensor_inputs);
events[static_cast<int>(MVDRKernelNames::steering_vector_generator)] =
SubmitSteeringVectorGeneratorKernel<
SteeringVectorGenerator<k_instance_num>, // Name to use for the
// Kernel
k_num_steering_vectors, // number of steering vectors
k_num_sensor_inputs, // number of elements in each vector
SinThetaInPipe, // sin(theta) input
SteeringVectorsDupPipe, // generated steering vectors
UpdateSteeringVectorsPipe // load new steering vectors
>(q);
events[static_cast<int>(MVDRKernelNames::transpose)] = SubmitTransposeKernel<
Transpose<k_instance_num>, // Name to use for the Kernel
ComplexType, // type of element to transpose
k_num_sensor_inputs, // number of columns in the input matrix
k_num_complex_per_xrx_read, // number of elements per pipe read/write
TrainingDataPipe, // training matrix input
TransposedTrainingDataDupPipe // Output matrix
>(q);
events[static_cast<int>(MVDRKernelNames::streaming_qrd)] =
SubmitStreamingQRDKernel<
StreamingQRD<k_instance_num>, // Name to use for the Kernel
k_qrd_min_iterations, // Minimum number of inner loop iterations
kNumTrainingRows, // Number of rows in the incoming A matrix
k_num_sensor_inputs, // Number of columns in the incoming A matrix
k_num_complex_per_xrx_read, // number of elements per pipe read
TransposedTrainingDataPipe, // A matrix input
QMatrixPipe, // Q output pipe (unused in MVDR)
RMatrixDupPipe // R output pipe
>(q);
events[static_cast<int>(MVDRKernelNames::diag_reciprocal)] =
SubmitDiagReciprocalKernel<
DiagReciprocal<k_instance_num>, // Name to use for the Kernel
k_num_sensor_inputs, // number of rows of the R matrix
RMatrixDRPipe, // Input R pipe
RDiagRecipVectorDupPipe // Output pipe for reciprocals
>(q);
events[static_cast<int>(MVDRKernelNames::forward_substitution)] =
SubmitForwardSubstitutionKernel<
ForwardSubstitution<k_instance_num>, // Name to use for the Kernel
k_num_sensor_inputs, // Number of elements in each vector
k_subst_unroll_factor, // inner loop unroll factor
k_num_steering_vectors, // Number of y vectors
RMatrixFSPipe, // lower-triangular matrix L
RDiagRecipVectorFSPipe, // 1 / diag of L
SteeringVectorsPipe, // Y vectors in
UpdateSteeringVectorsPipe, // load new Y vectors
ForwardSteeringVectorsDupPipe, // Steering vectors used to calculate
// X
ForwardSubstitutionResultDupPipe // X vectors out
>(q);
events[static_cast<int>(MVDRKernelNames::backward_substitution)] =
SubmitBackwardSubstitutionKernel<
BackwardSubstitution<k_instance_num>, // Name to use for the Kernel
k_num_sensor_inputs, // Number of elements in each vector
k_subst_unroll_factor, // inner loop unroll factor
k_num_steering_vectors, // Number of y vectors
RMatrixBSPipe, // upper-triangular matrix U.
RDiagRecipVectorBSPipe, // 1 / diag of U
ForwardSubstitutionResultPipe, // Y vectors in
YVectorsDupPipe // X vectors out
>(q);
events[static_cast<int>(MVDRKernelNames::calc_weights)] =
SubmitCalcWeightsKernel<
CalcWeights<k_instance_num>, // Name to use for the Kernel
k_num_steering_vectors, // number of steering vectors
k_num_sensor_inputs, // number of elements in each vector
YVectorsPipe, // Receive the Y vectors.
ForwardSteeringVectorsPipe, // steering vectors
WeightVectorsDupPipe // weight vectors output
>(q);
events[static_cast<int>(MVDRKernelNames::beamformer)] =
SubmitBeamformerKernel<
Beamformer<k_instance_num>, // Name to use for the Kernel
k_num_steering_vectors, // number of weight vectors
k_num_sensor_inputs, // number of elements in each vector
k_num_complex_per_xrx_read, // complex numbers per xrx pipe read
k_beam_unroll_factor, // unroll factor
XrxDataPipe, // Receive the Xrx vectors
WeightVectorsPipe, // weight vectors input
DataOutPipe // final data output
>(q, num_xrx_per_weights);
return events;
} // end of SubmitMVDRKernels()
#endif // ifndef __MVDR_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/StreamingQRDWrapper.hpp | #ifndef __STREAMING_QRD_WRAPPER_HPP__
#define __STREAMING_QRD_WRAPPER_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
// utility classes found in DirectProgramming/C++SYCL_FPGA/include
#include "streaming_qrd.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
using namespace sycl;
// SubmitStreamingQRDKernel
// Accept an input matrix one column at a time from an array of pipes. Perform
// Q R Decomposition on the array and send the result out through pipes.
template <typename StreamingQRDKernelName, // Name to use for the Kernel
size_t k_min_inner_loop_iterations, // Minimum number of inner loop
// iterations to achieve an outer
// loop II of 1. This value will
// have to be tuned for optimal
// performance. Refer to the
// Triangular Loop design pattern
// tutorial.
size_t k_a_num_rows, // Number of rows in the incoming A matrix
size_t k_a_num_cols, // Number of columns in the incoming A
// matrix, must be <= kNumRows
size_t k_pipe_width, // number of elements read/written
// (wrapped in NTuple) from/to pipes
typename AMatrixInPipe, // A matrix input, receive a full column
// of complex numbers with each read,
// wrapped in NTuple
typename QMatrixOutPipe, // Q output pipe, send a full column
// of complex numbers with each write.
// Column 0 is sent first, k_a_num_cols-1
// is sent last
typename RMatrixOutPipe // R output pipe. Send one complex number
// per write. Only upper-right elements
// of R are sent. Sent in row order,
// starting with row 0.
>
event SubmitStreamingQRDKernel(queue& q) {
// Template parameter checking
static_assert(std::numeric_limits<short>::max() > k_a_num_cols,
"k_a_num_cols must fit in a short");
static_assert(k_a_num_rows >= k_a_num_cols,
"k_a_num_rows must be greater than or equal to k_a_num_cols");
static_assert(std::numeric_limits<short>::max() > k_a_num_rows,
"k_a_num_rows must fit in a short");
static_assert(k_a_num_rows % k_pipe_width == 0,
"k_a_num_rows must be evenly divisible by k_pipe_width");
auto e = q.submit([&](sycl::handler& h) {
h.single_task<StreamingQRDKernelName>(
fpga_linalg::StreamingQRD<float, true, k_a_num_rows, k_a_num_cols,
k_min_inner_loop_iterations, k_pipe_width,
AMatrixInPipe, QMatrixOutPipe, RMatrixOutPipe,
false>());
});
return e;
}
#endif // ifndef __STREAMING_QRD_HPP_MVDR__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/UDP.hpp | #ifndef __UDP_HPP__
#define __UDP_HPP__
#include <chrono>
#include <cstdlib>
#include <iostream>
#include <thread>
#include <arpa/inet.h>
#include <net/if.h>
#include <netinet/in.h>
#include <sys/ioctl.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
#include <uuid/uuid.h>
#include <opae/access.h>
#include <opae/enum.h>
#include <opae/mmio.h>
#include <opae/properties.h>
#include <opae/utils.h>
using namespace std::chrono;
#define OPENCL_AFU_ID "3a00972e-7aac-41de-bbd1-3901124e8cda"
// The address offsets for the various CSRs related to the
// UDP offload engine on the FPGA
#define CSR_BASE_ADR 0x30000
#define CSR_FPGA_MAC_ADR (CSR_BASE_ADR + 0x00)
#define CSR_FPGA_IP_ADR (CSR_BASE_ADR + 0x08)
#define CSR_FPGA_UDP_PORT (CSR_BASE_ADR + 0x10)
#define CSR_FPGA_NETMASK (CSR_BASE_ADR + 0x18)
#define CSR_HOST_MAC_ADR (CSR_BASE_ADR + 0x20)
#define CSR_HOST_IP_ADR (CSR_BASE_ADR + 0x28)
#define CSR_HOST_UDP_PORT (CSR_BASE_ADR + 0x30)
#define CSR_PAYLOAD_PER_PACKET (CSR_BASE_ADR + 0x38)
#define CSR_CHECKSUM_IP (CSR_BASE_ADR + 0x40)
#define CSR_RESET_REG (CSR_BASE_ADR + 0x48)
#define CSR_STATUS_REG (CSR_BASE_ADR + 0x50)
#define DEST_UDP_PORT 34543
#define CHECKSUM_IP 43369
// constants
constexpr size_t kUDPDataSize = 4096; // bytes
constexpr size_t kUDPHeaderSize = 2; // bytes
constexpr size_t kUDPTotalSize = kUDPDataSize + kUDPHeaderSize; // bytes
// setting IP/gateway/netmask to the FPGA
void SetupFPGA(unsigned long fpga_mac_adr, char *fpga_ip_adr,
unsigned int fpga_udp_port, char *fpga_netmask,
unsigned long host_mac_adr, char *host_ip_adr,
unsigned int host_udp_port) {
fpga_properties filter = NULL;
fpga_token afc_token;
fpga_handle afc_handle;
fpga_guid guid;
uint32_t num_matches;
fpga_result res = FPGA_OK;
if (uuid_parse(OPENCL_AFU_ID, guid) < 0) {
fprintf(stderr, "Error parsing guid '%s'\n", OPENCL_AFU_ID);
std::terminate();
}
// Look for AFC with MY_AFC_ID
if ((res = fpgaGetProperties(NULL, &filter)) != FPGA_OK) {
fprintf(stderr, "Error: creating properties object");
std::terminate();
}
if ((res = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR)) !=
FPGA_OK) {
fprintf(stderr, "Error: setting object type");
std::terminate();
}
if ((res = fpgaPropertiesSetGUID(filter, guid)) != FPGA_OK) {
fprintf(stderr, "Error: setting GUID");
}
if ((res = fpgaEnumerate(&filter, 1, &afc_token, 1, &num_matches)) !=
FPGA_OK) {
fprintf(stderr, "Error: enumerating AFCs\n");
}
if (num_matches < 1) {
fprintf(stderr, "AFC not found.\n");
res = fpgaDestroyProperties(&filter);
std::terminate();
}
// Open AFC and map MMIO
if ((res = fpgaOpen(afc_token, &afc_handle, FPGA_OPEN_SHARED)) != FPGA_OK) {
fprintf(stderr, "Error: opening AFC\n");
std::terminate();
}
if ((res = fpgaMapMMIO(afc_handle, 0, NULL)) != FPGA_OK) {
fprintf(stderr, "Error: mapping MMIO space\n");
std::terminate();
}
// Reset AFC
// if ((res = fpgaReset(afc_handle)) != FPGA_OK) {
// fprintf(stderr, "Error: resetting AFC\n");
// std::terminate();
//}
using namespace std::chrono_literals;
// MAC reset
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_RESET_REG, 0x7)) != FPGA_OK) {
fprintf(stderr, "Error: writing RST\n");
std::terminate();
}
std::this_thread::sleep_for(1ms);
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_RESET_REG, 0x0)) != FPGA_OK) {
fprintf(stderr, "Error: writing RST\n");
std::terminate();
}
std::this_thread::sleep_for(1ms);
//
// UOE register settings. These registers are not reset even after
// fpgaClose().
//
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_FPGA_MAC_ADR, fpga_mac_adr)) !=
FPGA_OK) {
fprintf(stderr, "Error: writing FPGA MAC CSR\n");
std::terminate();
}
unsigned long tmp1 = htonl(inet_addr(fpga_ip_adr));
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_FPGA_IP_ADR, tmp1)) !=
FPGA_OK) {
fprintf(stderr, "Error: writing FPGA IP CSR\n");
std::terminate();
}
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_FPGA_UDP_PORT,
(unsigned long)fpga_udp_port)) != FPGA_OK) {
fprintf(stderr, "Error: writing FPGA UDP port CSR\n");
std::terminate();
}
unsigned long tmp2 = htonl(inet_addr(fpga_netmask));
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_FPGA_NETMASK, tmp2)) !=
FPGA_OK) {
fprintf(stderr, "Error: writing FPGA netmask CSR\n");
std::terminate();
}
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_HOST_MAC_ADR, host_mac_adr)) !=
FPGA_OK) {
fprintf(stderr, "Error: writing HOST MAC CSR\n");
std::terminate();
}
unsigned long tmp3 = htonl(inet_addr(host_ip_adr));
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_HOST_IP_ADR, tmp3)) !=
FPGA_OK) {
fprintf(stderr, "Error: writing HOST IP CSR\n");
std::terminate();
}
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_HOST_UDP_PORT,
(unsigned long)host_udp_port)) != FPGA_OK) {
fprintf(stderr, "Error:writing HOST UDP port CSR\n");
std::terminate();
}
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_PAYLOAD_PER_PACKET,
(unsigned long)kUDPDataSize)) != FPGA_OK) {
fprintf(stderr, "Error: writing payload per packet CSR\n");
std::terminate();
}
if ((res = fpgaWriteMMIO64(afc_handle, 0, CSR_CHECKSUM_IP,
(unsigned long)CHECKSUM_IP)) != FPGA_OK) {
fprintf(stderr, "Error: writing checksum IP CSR\n");
std::terminate();
}
// Read status register
unsigned long read_tmp;
if ((res = fpgaReadMMIO64(afc_handle, 0, CSR_STATUS_REG, &read_tmp)) !=
FPGA_OK) {
fprintf(stderr, "Error: reading status CSR\n");
std::terminate();
}
printf("Reading back status register from UDP offload engine: %012lx\n",
read_tmp);
// Unmap MMIO space
if ((res = fpgaUnmapMMIO(afc_handle, 0)) != FPGA_OK) {
fprintf(stderr, "Error: unmapping MMIO space\n");
std::terminate();
}
// Release accelerator
if ((res = fpgaClose(afc_handle)) != FPGA_OK) {
fprintf(stderr, "Error: closing AFC\n");
std::terminate();
}
// Destroy token
if ((res = fpgaDestroyToken(&afc_token)) != FPGA_OK) {
fprintf(stderr, "Error: destroying token\n");
std::terminate();
}
// Destroy properties object
if ((res = fpgaDestroyProperties(&filter)) != FPGA_OK) {
fprintf(stderr, "Error: destroying properties object\n");
std::terminate();
}
}
// Send packets (from input_data) to the FPGA
void UDPSender(char *fpga_ip, unsigned int port, unsigned char *input_data,
size_t packets, high_resolution_clock::time_point *t_in,
unsigned long delay_us = 0) {
int sock;
struct sockaddr_in fpgaaddr;
printf("SENDER: start\n");
if ((sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) {
printf("ERROR: failed to open sender socket\n");
std::terminate();
}
memset(&fpgaaddr, 0, sizeof(fpgaaddr));
fpgaaddr.sin_family = AF_INET;
fpgaaddr.sin_addr.s_addr = inet_addr(fpga_ip);
fpgaaddr.sin_port = htons(port);
printf("SENDER: starting to send packets\n");
auto start = high_resolution_clock::now();
for (int i = 0; i < packets; i++) {
sendto(sock, input_data + i * kUDPTotalSize, kUDPTotalSize, 0,
(struct sockaddr *)&fpgaaddr, sizeof(fpgaaddr));
if (t_in) t_in[i] = high_resolution_clock::now();
// optional delay of the producer to reduce rate of production
if (delay_us > 0)
std::this_thread::sleep_for(std::chrono::microseconds(delay_us));
}
auto end = high_resolution_clock::now();
duration<double, std::milli> diff(end - start);
double tp_mb_s = (kUDPTotalSize * packets * 1e-6) / (diff.count() * 1e-3);
std::cout << "SENDER: throughput: " << tp_mb_s << " MB/s\n";
close(sock);
printf("SENDER: closed\n\n");
}
// Receive packets (into output_data) from the FPGA
void UDPReceiver(char *host_ip, unsigned int port, unsigned char *output_data,
size_t packets, high_resolution_clock::time_point *t_out) {
int sock, res;
struct ifreq ifr;
struct sockaddr_in hostaddr;
printf("RECEIVER: start\n");
// create UDP socket
if ((sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) {
printf("ERROR: fail to open receiver socket");
std::terminate();
}
printf("RECEIVER: UDP socket created\n");
// bind to ens2 interface only
memset(&ifr, 0, sizeof(ifr));
snprintf(ifr.ifr_name, sizeof(ifr.ifr_name), "ens2");
if ((res = setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, (void *)&ifr,
sizeof(ifr))) < 0) {
perror("Server-setsockopt() error for SO_BINDTODEVICE");
printf("%s\n", strerror(errno));
close(sock);
std::terminate();
}
// Set port and IP
memset(&hostaddr, 0, sizeof(hostaddr));
hostaddr.sin_family = AF_INET;
hostaddr.sin_addr.s_addr = inet_addr(host_ip);
hostaddr.sin_port = htons(port);
// Bind to the set port and IP
if (bind(sock, (struct sockaddr *)&hostaddr, sizeof(hostaddr)) < 0) {
printf("ERROR: fail to bind");
std::terminate();
}
printf("RECEIVER: socket bound to port %d\n", DEST_UDP_PORT);
// Receive data
auto start = high_resolution_clock::now();
for (int i = 0; i < packets; i++) {
recv(sock, output_data + i * kUDPTotalSize, kUDPTotalSize, 0 /*flag*/);
if (t_out) t_out[i] = high_resolution_clock::now();
// DEBUG
// std::cout << i << std::endl;
}
auto end = high_resolution_clock::now();
duration<double, std::milli> diff(end - start);
double tp_mb_s = (kUDPTotalSize * packets * 1e-6) / (diff.count() * 1e-3);
std::cout << "RECEIVER: throughput: " << tp_mb_s << " MB/s\n";
close(sock);
printf("RECEIVER: closed\n\n");
}
unsigned char *AllocatePackets(size_t packets) {
// allocate aligned memory
auto ret = static_cast<unsigned char *>(
aligned_alloc(1024, kUDPTotalSize * packets));
// pin the memory
mlock(ret, kUDPTotalSize * packets);
return ret;
}
void FreePackets(unsigned char *ptr, size_t packets) {
// unpin the memory
munlock(ptr, kUDPTotalSize * packets);
// free the memory
free(ptr);
}
// convert an array of elements into packets including adding header
template <typename T>
void ToPackets(unsigned char *udp_bytes, T *data, size_t count) {
assert(kUDPDataSize % sizeof(T) == 0);
assert((count * sizeof(T)) % kUDPDataSize == 0);
size_t count_per_packet = kUDPDataSize / sizeof(T);
assert((count % count_per_packet) == 0);
size_t iterations = count / count_per_packet;
size_t packet_stride = kUDPDataSize + 2;
for (int i = 0; i < iterations; i++) {
udp_bytes[i * packet_stride] = 0xAB;
udp_bytes[i * packet_stride + 1] = 0xCD;
memcpy(&udp_bytes[i * packet_stride + 2], &data[i * count_per_packet],
kUDPDataSize);
}
}
// convert the bytes of packets into an array of elements
template <typename T>
void FromPackets(unsigned char *udp_bytes, T *data, size_t count) {
assert((kUDPDataSize % sizeof(T)) == 0);
assert((count * sizeof(T)) % kUDPDataSize == 0);
size_t count_per_packet = kUDPDataSize / sizeof(T);
assert((count % count_per_packet) == 0);
size_t iterations = count / count_per_packet;
size_t packet_stride = kUDPDataSize + 2;
for (int i = 0; i < iterations; i++) {
memcpy(&data[i * count_per_packet], &udp_bytes[i * packet_stride + 2],
kUDPDataSize);
}
}
// utility to parse a MAC address string
unsigned long ParseMACAddress(std::string mac_str) {
std::replace(mac_str.begin(), mac_str.end(), ':', ' ');
std::array<int, 6> mac_nums;
std::stringstream ss(mac_str);
int i = 0;
int tmp;
while (ss >> std::hex >> tmp) {
mac_nums[i++] = tmp;
}
if (i != 6) {
std::cerr << "ERROR: invalid MAC address string\n";
return 0;
}
unsigned long ret = 0;
for (size_t j = 0; j < 6; j++) {
ret += mac_nums[j] & 0xFF;
if (j != 5) {
ret <<= 8;
}
}
return ret;
}
// utility to pin a C++ thread to a specific CPU
int PinThreadToCPU(std::thread &t, int cpu_id) {
cpu_set_t cpuset;
CPU_ZERO(&cpuset);
CPU_SET(cpu_id, &cpuset);
return pthread_setaffinity_np(t.native_handle(), sizeof(cpu_set_t), &cpuset);
}
#endif /* __UDP_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_complex.hpp | #ifndef __MVDR_COMPLEX_HPP__
#define __MVDR_COMPLEX_HPP__
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
using ComplexBaseType = float;
using ComplexType = ac_complex<ComplexBaseType>;
#endif // ifndef __MVDR_COMPLEX_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/ForwardSubstitution.hpp | #ifndef __FORWARD_SUBSTITUTION_HPP__
#define __FORWARD_SUBSTITUTION_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// utility classes
#include "ParallelCopyArray.hpp"
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitForwardSubstitutionKernel
// Accept a square lower triangular matrix L (in column order) and a
// number of y input vectors, and solve Lx = y for each input vector.
// L must be real valued on the diagonal, and a vector of the reciprocals
// of the diagonal values (LDiagRecipVectorInPipe) must also be supplied.
template <typename ForwardSubstitutionKernelName, // Name to use for the Kernel
size_t k_vector_size, // Number of elements in each vector, also
// number of rows and columns in the
// square L matrix
size_t k_unroll_factor, // Factor by which to unroll the innermost
// calculation loop, so k_unroll_factor
// operations will be performed in
// parallel on each clock.
size_t k_num_y_vectors, // Number of y vectors to solve for with
// each new L matrix.
typename LMatrixInPipe, // Receive the lower-triangular matrix L.
// Diagonal must be real valued.
// Only lower left elements are sent,
// (known zero elements are skipped).
// Sent starting with first column.
// Receive one complex float per read.
typename LDiagRecipVectorInPipe, // Receive 1/ the diagonal elements
// of L. Receive one float per read.
typename YVectorsInPipe, // Receive the Y vectors.
// Receive one complex float per read.
typename UpdateYInPipe, // A valid read from this pipe indicates
// a full set of vectors are ready on the
// YVectorsInPipe.
// Accept a single bool per read
typename YVectorsOutPipe, // Forward the Y vectors used to calculate
// each X vector to downstream kernels.
// Send one complex float per write.
typename XVectorsOutPipe // Send X vectors.
// Send one complex float per write.
>
event SubmitForwardSubstitutionKernel(queue& q) {
// Template parameter checking
static_assert(k_vector_size > 0, "k_vector_size must be greater than 0");
static_assert(std::numeric_limits<short>::max() > k_vector_size,
"k_vector_size must fit in a short");
static_assert(k_num_y_vectors > 0, "k_num_y_vectors must be greater than 0");
static_assert(std::numeric_limits<char>::max() > k_num_y_vectors,
"k_num_y_vectors must fit in a char");
static_assert(k_vector_size % k_unroll_factor == 0,
"k_vector_size must be evenly divisible by k_unroll_factor");
// this type represents the number of samples to be processed in parallel
// grouping these into an array helps the compiler generate the desired local
// memory configurations
using CalcType = ParallelCopyArray<ComplexType, k_unroll_factor>;
constexpr short kNumCalcTypePerVector = k_vector_size / k_unroll_factor;
auto e = q.submit([&](handler& h) {
h.single_task<ForwardSubstitutionKernelName>([=] {
// do not proceed until the first set of y vectors are available
// Data in this pipe is always true, so we know update_y_vectors will be
// set to true here. Doing this assignment creates a memory dependency
// to ensure this pipe read can't be re-ordered relative to reads from
// YVectorsInPipe
bool update_y_vectors = UpdateYInPipe::read();
CalcType y_vectors[k_num_y_vectors][kNumCalcTypePerVector];
while (1) {
CalcType l_matrix[k_vector_size][kNumCalcTypePerVector];
float l_diag_recip_vector[k_vector_size];
// number of non-zero elements in the L matrix
// 1+2+3+...+n = (n)(n+1)/2
constexpr int kNumLElements = (k_vector_size) * (k_vector_size + 1) / 2;
// number of elements in the set of y vectors
constexpr int kNumYElements = k_vector_size * k_num_y_vectors;
constexpr int kLoadLoopIterations =
(kNumLElements > kNumYElements) ? kNumLElements : kNumYElements;
// receive the L matrix and diagonal reciprocal vector from the pipes
// receive new y_vectors if they are available
// This odd loop is a fusion of two loops with different trip counts.
short col = 0, row = 0, i = 0, j = 0;
unsigned char vector_num = 0;
for (int iteration = 0; iteration < kLoadLoopIterations; iteration++) {
// Load the L and LDiagRecip values
if (iteration < kNumLElements) {
l_matrix[col][row / k_unroll_factor][row % k_unroll_factor] =
LMatrixInPipe::read();
if (col == row) {
l_diag_recip_vector[row] = LDiagRecipVectorInPipe::read();
}
row++;
if (row == (short)k_vector_size) {
col++; // col counts 0..k_vector_size
row = col; // row counts 0..k_vector_size, 1..k_vector_size, ...
}
}
// load the Y values
if ((iteration < kNumYElements) && (update_y_vectors)) {
// non-blocking read is safe here, we know data is available
bool temp;
y_vectors[vector_num][i][j] = YVectorsInPipe::read(temp);
j++; // j counts 0..k_unroll_factor
if (j == (short)k_unroll_factor) {
j = 0;
i++; // i counts 0..kNumCalcTypePerVector
if (i == kNumCalcTypePerVector) {
i = 0;
vector_num++; // vector_num counts 0..k_num_y_vectors
}
}
}
} // end of for(i...)
// Loop through all the y vectors
for (unsigned char vector_num = 0;
vector_num < (unsigned char)k_num_y_vectors; vector_num++) {
// y_vector_intial contains the unmodified current y vector. y_vector
// is used during processing. Splitting these two vectors allows
// each to be implemented in a local memory with only one read and
// one write port.
CalcType y_vector_initial[kNumCalcTypePerVector];
CalcType y_vector[kNumCalcTypePerVector];
// This variable represents the value of y[col] for the next iteration
// of the col loop (see below). Storing this value here prevents
// the need for an additional read from y_vector[], which would result
// in a second read port for the y_vector[] memory system.
ComplexType y_at_next_col_pos;
// Load a y vector from local storage
for (short i = 0; i < kNumCalcTypePerVector; i++) {
CalcType y_elements;
fpga_tools::UnrolledLoop<k_unroll_factor>([&](auto j) {
y_elements[j] = y_vectors[vector_num][i][j];
y_vector_initial[i][j] = y_elements[j];
if (i == 0 && j == 0) {
// initialize the first value of y_at_next_col_pos
y_at_next_col_pos = y_elements[0];
}
});
}
// calculate x for the current y vector
ComplexType x_vector[k_vector_size];
// iterate over all columns in L
for (short col = 0; col < k_vector_size; col++) {
// y_scaled = y[col] / L[col][col] (diagonal value of L)
auto y_scaled = y_at_next_col_pos * l_diag_recip_vector[col];
// store the calculated result to the x_vector
x_vector[col] = y_scaled;
// iterate over all rows of L in the current column
// unroll by a factor of k_unroll_factor (so perform k_unroll_factor
// operations in parallel)
// NO-FORMAT comments are for clang-format
[[intel::speculated_iterations(0)]] // NO-FORMAT: Attribute
for (short i = 0; i < kNumCalcTypePerVector; i++) {
// These variables are used to help the compiler infer the
// desired memory organization.
CalcType l_val, y_val, y_initial_val, y_current, y_new;
short row[k_unroll_factor];
fpga_tools::UnrolledLoop<k_unroll_factor>([&](auto j) {
// calculate current location within the vector
row[j] = j + (i * (short)k_unroll_factor);
// force l values to 0 for upper right of matrix (including
// the diagonal)
l_val[j] = l_matrix[col][i][j];
if (row[j] <= col) l_val[j] = 0;
// If we place the accesses to y_vector and y_vector_intial
// inside the if/else statement, it results in a very strange
// configuration of the y_vector memory system, so use these
// intermediate variables.
y_val[j] = y_vector[i][j];
y_initial_val[j] = y_vector_initial[i][j];
if (col == 0) {
y_current[j] = y_initial_val[j];
} else {
y_current[j] = y_val[j];
}
// perform the calculation on y and store the result back into
// y_vector
y_new[j] = y_current[j] - y_scaled * l_val[j].conj();
y_vector[i][j] = y_new[j];
// update y_at_next_col_pos for the next iteration of the col
// loop
if (row[j] == col + 1) {
y_at_next_col_pos = y_new[j];
}
}); // end of unrolled loop
} // end of for( i... )
} // end of for( col... )
// write the result to the output pipe
for (short i = 0; i < (short)k_vector_size; i++) {
XVectorsOutPipe::write(x_vector[i]);
YVectorsOutPipe::write(
y_vector_initial[i / k_unroll_factor][i % k_unroll_factor]);
}
} // end of for( vector_num ... )
// Determine if a new set of Y vectors are available with a non-blocking
// read from the UpdateYInPipe pipe.
// The value read from the pipe is discarded, any data in this pipe
// indicates a new set of vectors are ready
(void)UpdateYInPipe::read(update_y_vectors);
} // end of while( 1 )
}); // end of h.single_task
}); // end of q.submit
return e;
} // end of SubmitForwardSubstitutionrKernel()
#endif // ifndef __FORWARD_SUBSTITUTION_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/InputDemux.hpp | #ifndef __INPUT_DEMUX_HPP__
#define __INPUT_DEMUX_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <cmath>
// utility classes
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitInputDemuxKernel
// Accept data from an input pipe, and split the data into two output pipes
// based on header packets detected in the data stream. Buffer up a full
// training array and matching data samples before passing any data downstream,
// so that the correct amount of each type of data is guaranteed to all
// downstream kernels, and no partial matrices are ever transferred.
template <typename InputDemuxKernelName, // Name to use for the Kernel
size_t k_pipe_width, // Number of complex numbers transferred
// on each pipe read or write
size_t k_training_size, // number of complex numbers in a full
// training matrix
size_t k_max_xrx_data_size, // maximum number of complex numbers in a
// set of xrx data to be matched with
// each training matrix to support
bool k_read_every_cycle, // When true, kernel will try to read from
// input pipe on every cycle. When false,
// only read when space is available. Set
// to false for backpressurable interfaces
typename DataInPipe, // Receive streaming data, including
// headers, from this pipe.
typename TrainingDataOutPipe, // Send training data to QRD
typename XrxDataOutPipe // Send sample data to Beamformer
>
event SubmitInputDemuxKernel(
queue& q,
int xrx_data_size // number of complex numbers in a set of
// xrx data to be matched with each
// training matrix
// (must be <= k_max_xrx_data_size)
) {
// error checking on input parameter
if (xrx_data_size > k_max_xrx_data_size) {
std::cerr << "Called SubmitInputDemuxKernel() with k_max_xrx_data_size < ";
std::cerr << "xrx_data_size" << std::endl;
std::terminate();
}
// Use an NTuple of complex numbers for reading/writing pipes
using PipeType = fpga_tools::NTuple<ComplexType, k_pipe_width>;
auto e = q.submit([&](handler& h) {
h.single_task<InputDemuxKernelName>([=] {
constexpr int kReadsPerTrainingMatrix = k_training_size / k_pipe_width;
constexpr int kMaxReadsPerXrxDataMatrix =
k_max_xrx_data_size / k_pipe_width;
int reads_per_xrx_matrix = xrx_data_size / k_pipe_width;
// multiple copies of each matrix to create a simple FIFO that has enough
// slack to allow us to use 'almost full' in the logic below
constexpr unsigned char kNumMatrixCopies = 4; // must be power of 2
static_assert(kNumMatrixCopies > 0);
static_assert((kNumMatrixCopies & (kNumMatrixCopies - 1)) == 0);
constexpr unsigned char kNumMatrixCopiesBitMask = kNumMatrixCopies - 1;
PipeType training_matrix[kNumMatrixCopies][kReadsPerTrainingMatrix];
PipeType xrx_data_matrix[kNumMatrixCopies][kMaxReadsPerXrxDataMatrix];
// track the status of each of the buffers
// NO-FORMAT comments are for clang-format
[[intel::fpga_register]] // NO-FORMAT: Attribute
bool ready_to_send[kNumMatrixCopies] = {false};
// create a 'pipeline' for the almost full signal
constexpr int kAlmostFullPipeDepth = 2;
fpga_tools::NTuple<bool, kAlmostFullPipeDepth> almost_full_pipeline;
fpga_tools::UnrolledLoop<kAlmostFullPipeDepth>([&](auto pipe_stage) {
almost_full_pipeline.template get<pipe_stage>() = false;
});
// state variables for receiving data
unsigned char rx_buffer = 0; // which buffer are we currently writing
unsigned int rx_training_count = 0;
unsigned int rx_xrx_count = 0;
enum class RxState : char {
wait_training_header, // discard data until training header
receiving_training_data, // store training data
expect_xrx_data_header, // next word should be xrx data header
receiving_xrx_data // store xrx data
};
RxState rx_state = RxState::wait_training_header;
// state variables for sending data
unsigned char tx_buffer = 0; // which buffer are we currently reading
unsigned int tx_training_count = 0;
unsigned int tx_xrx_count = 0;
bool all_training_sent = false;
bool all_xrx_sent = false;
// NO-FORMAT comments are for clang-format
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
while (1) {
// capture the current state of variables before they are modified
// by this iteration of the loop
unsigned char cur_rx_buffer = rx_buffer;
unsigned int cur_rx_training_count = rx_training_count;
unsigned int cur_rx_xrx_count = rx_xrx_count;
RxState cur_rx_state = rx_state;
unsigned char cur_tx_buffer = tx_buffer;
unsigned int cur_tx_training_count = tx_training_count;
unsigned int cur_tx_xrx_count = tx_xrx_count;
bool cur_all_training_sent = all_training_sent;
bool cur_all_xrx_sent = all_xrx_sent;
// Create a 'pipeline' for the almost full signal.
// Calculate almost full at the end of the pipeline, and on each loop
// iteration we shift the data down the pipeline. Since we are using
// an 'almost' full signal, we don't need the result right away, we
// can wait several loop iterations. This allows us to break
// dependencies between loop iterations and improve FMAX.
fpga_tools::UnrolledLoop<kAlmostFullPipeDepth - 1>([&](auto pipe_stage) {
almost_full_pipeline.template get<pipe_stage>() =
almost_full_pipeline.template get<pipe_stage + 1>();
});
bool cur_almost_full = almost_full_pipeline.first();
// Calculate almost full at the start of the pipeline
// if the NEXT buffer we would write to is not ready for use, then
// assert almost full
almost_full_pipeline.last() =
ready_to_send[(cur_rx_buffer + 1) & kNumMatrixCopiesBitMask];
// Only do the pipe read if we have space available, OR if we are
// configured to read on every cycle. Reading on every cycle means
// this block will discard data if downstream can't keep up (and
// therefore be able to track how much data is discarded).
PipeType data_in;
bool read_valid = false;
if (k_read_every_cycle || !cur_almost_full) {
data_in = DataInPipe::read(read_valid);
}
// examine received data for header markers (ignored if !read_valid)
// Real part of 0th word set to NaN indicates a header
// Imaginary part of 0th word set to 0 indicates training header, non
// zero value indicates xrx data header
bool is_header = sycl::isnan(data_in.template get<0>().real());
bool header_is_training = (data_in.template get<0>().imag() == 0.0);
// only process valid data if we are not almost full, otherwise data
// must be discarded
if (read_valid && !cur_almost_full) {
// store training data
if (cur_rx_state == RxState::receiving_training_data) {
training_matrix[cur_rx_buffer][cur_rx_training_count] = data_in;
rx_training_count++;
} else {
rx_training_count = 0;
}
// store xrx data
if (cur_rx_state == RxState::receiving_xrx_data) {
xrx_data_matrix[cur_rx_buffer][cur_rx_xrx_count] = data_in;
rx_xrx_count++;
} else {
rx_xrx_count = 0;
}
// update the rx_buffer when all data has been received
if (cur_rx_state == RxState::receiving_xrx_data &&
cur_rx_xrx_count == reads_per_xrx_matrix - 1) {
ready_to_send[cur_rx_buffer] = true;
rx_buffer = (rx_buffer + 1) & kNumMatrixCopiesBitMask;
}
// Rx state machine
if (cur_rx_state == RxState::wait_training_header) {
if (is_header && header_is_training) {
rx_state = RxState::receiving_training_data;
}
} else if (cur_rx_state == RxState::receiving_training_data) {
if (is_header) {
// unexpected header, discard the current data and start over
rx_state = RxState::wait_training_header;
} else if (cur_rx_training_count == kReadsPerTrainingMatrix - 1) {
rx_state = RxState::expect_xrx_data_header;
}
} else if (cur_rx_state == RxState::expect_xrx_data_header) {
if (is_header && !header_is_training) {
rx_state = RxState::receiving_xrx_data;
} else {
// didn't receive expected header, discard data and start over
rx_state = RxState::wait_training_header;
}
} else { // RxState::receiving_xrx_data
if (is_header) {
// unexpected header, discard the current data and start over
rx_state = RxState::wait_training_header;
} else if (cur_rx_xrx_count == reads_per_xrx_matrix - 1) {
rx_state = RxState::wait_training_header;
}
} // end of Rx state machine
} else if (read_valid) {
// if we have valid data but are almost full, we must discard all data
rx_training_count = 0;
rx_xrx_count = 0;
rx_state = RxState::wait_training_header;
}
// try to send data unless we have sent all data from the current buffer
if (!cur_all_training_sent || !cur_all_xrx_sent) {
bool write_success = false;
// send training data, if available
if (ready_to_send[cur_tx_buffer] && !cur_all_training_sent) {
TrainingDataOutPipe::write(
training_matrix[cur_tx_buffer][cur_tx_training_count],
write_success);
}
if (write_success) {
all_training_sent =
(cur_tx_training_count == kReadsPerTrainingMatrix - 1);
tx_training_count++;
}
// send xrx data, if available
if (ready_to_send[cur_tx_buffer] && !cur_all_xrx_sent) {
XrxDataOutPipe::write(
xrx_data_matrix[cur_tx_buffer][cur_tx_xrx_count],
write_success);
} else {
write_success = false;
}
if (write_success) {
all_xrx_sent = (cur_tx_xrx_count == reads_per_xrx_matrix - 1);
tx_xrx_count++;
}
} else {
// all training and xrx data from the current buffer has been sent
ready_to_send[cur_tx_buffer] = false;
tx_buffer = (tx_buffer + 1) & kNumMatrixCopiesBitMask;
all_training_sent = false;
all_xrx_sent = false;
tx_training_count = 0;
tx_xrx_count = 0;
}
} // end of while( 1 )
}); // end of h.single_task
}); // end of q.submit
return e;
} // end of SubmitInputDemuxKernel()
#endif // ifndef __INPUT_DEMUX_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/Transpose.hpp | #ifndef __TRANSPOSE_HPP__
#define __TRANSPOSE_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
using namespace sycl;
// the generic transpose class. Defined below after SubmitTransposeKernel.
template <typename T, size_t k_num_cols_in, size_t k_pipe_width,
typename MatrixInPipe, typename MatrixOutPipe>
struct Transposer;
// SubmitTransposeKernel
// Accept k_pipe_width elements of type T wrapped in NTuple
// on each read from DataInPipe. Store elements locally until we can write
// to the output array of pipes with data in transposed order.
// For simplicity of terminology, incoming data is defined to enter in 'row'
// order and exit in 'column' order, although for the purposes of the transpose
// the terms 'row' and 'column' could be interchanged.
// Row order means all data from a given row is received before any data from
// the next row is received.
// This kernel also performs flow control and ensures that no partial matrices
// will be written into the output pipe.
template <typename TransposeKernelName, // Name to use for the Kernel
typename T, // type of element to transpose
size_t k_num_cols_in, // number of columns in the input matrix
size_t k_pipe_width, // number of elements read/written
// (wrapped in NTuple) from/to pipes
typename MatrixInPipe, // Receive the input matrix in row order
// Receive k_pipe_width elements of type
// T wrapped in NTuple on each read
typename MatrixOutPipe // Send the output matrix in column order.
// Send k_pipe_width elements of type T
// wrapped in NTuple on each write.
>
event SubmitTransposeKernel(queue& q) {
// Template parameter checking
static_assert(std::numeric_limits<short>::max() > k_num_cols_in,
"k_num_cols_in must fit in a short");
static_assert(k_num_cols_in % k_pipe_width == 0,
"k_num_cols_in must be evenly divisible by k_pipe_width");
return q.single_task<TransposeKernelName>(Transposer<T, k_num_cols_in, k_pipe_width, MatrixInPipe, MatrixOutPipe>{});
}
// The generic transpose. We use classes here because we want to do partial
// template specialization on the 'k_pipe_width' to optimize the case where
// 'k_pipe_width' == 1 and this cannot be done with a function.
template <typename T, size_t k_num_cols_in, size_t k_pipe_width,
typename MatrixInPipe, typename MatrixOutPipe>
struct Transposer {
void operator()() const {
using PipeType = fpga_tools::NTuple<T, k_pipe_width>;
// This is a scratch pad memory that we will use to do the transpose.
// We read the data in from a pipe (k_pipe_width elements at at time),
// store it in this memory in row-major format and read it out in
// column-major format (again, k_pipe_width elements at a time).
constexpr int kNumScratchMemCopies = 4; // must be a power of 2
static_assert(kNumScratchMemCopies > 0);
static_assert((kNumScratchMemCopies & (kNumScratchMemCopies - 1)) == 0);
constexpr unsigned char kNumScratchMemCopiesBitMask =
kNumScratchMemCopies - 1;
constexpr int kBankwidth = k_pipe_width * sizeof(T);
// NO-FORMAT comments are for clang-format
[[intel::numbanks(1)]] // NO-FORMAT: Attribute
[[intel::bankwidth(kBankwidth)]] // NO-FORMAT: Attribute
[[intel::private_copies(1)]] // NO-FORMAT: Attribute
[[intel::max_replicates(k_pipe_width)]] // NO-FORMAT: Attribute
T scratch[kNumScratchMemCopies][k_pipe_width*k_num_cols_in];
// track the status of each of the buffers
// NO-FORMAT comments are for clang-format
[[intel::fpga_register]] // NO-FORMAT: Attribute
bool ready_to_send[kNumScratchMemCopies] = {false, false, false, false};
unsigned char rx_buffer = 0;
unsigned short rx_count = 0;
unsigned char tx_buffer = 0;
unsigned char tx_col = 0;
bool last_tx_col = false;
// create a 'pipeline' for the almost full signal
constexpr int kAlmostFullPipeDepth = 2;
fpga_tools::NTuple<bool, kAlmostFullPipeDepth> almost_full_pipeline;
fpga_tools::UnrolledLoop<kAlmostFullPipeDepth>([&](auto pipe_stage) {
almost_full_pipeline.template get<pipe_stage>() = false;
});
// NO-FORMAT comments are for clang-format
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
while (1) {
// capture current value of all status variables as we begin each loop
// iteration
unsigned char cur_rx_buffer = rx_buffer;
unsigned short cur_rx_count = rx_count;
unsigned char cur_tx_buffer = tx_buffer;
unsigned char cur_tx_col = tx_col;
bool cur_last_tx_col = last_tx_col;
// Create a 'pipeline' for the almost full signal.
// Calculate almost full at the end of the pipeline, and on each loop
// iteration we shift the data down the pipeline. Since we are using
// an 'almost' full signal, we don't need the result right away, we
// can wait several loop iterations. This allows us to break
// dependencies between loop iterations and improve FMAX.
fpga_tools::UnrolledLoop<kAlmostFullPipeDepth - 1>([&](auto pipe_stage) {
almost_full_pipeline.template get<pipe_stage>() =
almost_full_pipeline.template get<pipe_stage + 1>();
});
bool cur_almost_full = almost_full_pipeline.first();
// Calculate almost full at the start of the pipeline
// if the NEXT buffer we would write to is not ready for use, then
// assert almost full
almost_full_pipeline.last() =
ready_to_send[(cur_rx_buffer + 1) & kNumScratchMemCopiesBitMask];
// read the next data to send
PipeType data_out;
fpga_tools::UnrolledLoop<k_pipe_width>([&](auto i) {
data_out.template get<i>() = scratch[cur_tx_buffer][i*k_num_cols_in+cur_tx_col];
});
// only attempt to send the data if it is valid
if (ready_to_send[cur_tx_buffer]) {
bool write_success;
MatrixOutPipe::write(data_out, write_success);
// update the transmit buffer status only if the pipe write succeeded
if (write_success) {
if (cur_last_tx_col) {
ready_to_send[cur_tx_buffer] = false;
tx_col = 0;
tx_buffer = (cur_tx_buffer + 1) & kNumScratchMemCopiesBitMask;
last_tx_col = false;
} else {
tx_col++;
// if the current value of tx_col is 2 less than the total, then
// the next value we read out (when cur_tx_col == k_num_cols_in -1)
// is the last value for this copy
last_tx_col = (cur_tx_col == (unsigned short)k_num_cols_in - 2);
}
}
}
// as long as the internal buffers are not almost full, read new data
PipeType data_in;
bool read_valid = false;
if (!cur_almost_full) {
data_in = MatrixInPipe::read(read_valid);
}
// if we have new data, store it in the buffer and update the status
if (read_valid) {
fpga_tools::UnrolledLoop<k_pipe_width>([&](auto i) {
scratch[cur_rx_buffer][cur_rx_count*(unsigned short)k_pipe_width + i] = data_in.template get<i>();
});
// update the receive buffer status
if (cur_rx_count == (unsigned short)((k_num_cols_in - 1))) {
ready_to_send[cur_rx_buffer] = true;
rx_count = 0;
rx_buffer = (cur_rx_buffer + 1) & kNumScratchMemCopiesBitMask;
} else {
rx_count++;
}
}
} // end of while(1)
} // end of operator()()
};
// Special case for a k_pipe_width=1
// In this case, the is just a pass through kernel since the matrix is
// 1 x k_num_cols. Overriding this version allows us to save area.
template <typename T, size_t k_num_cols_in, typename MatrixInPipe,
typename MatrixOutPipe>
struct Transposer<T, k_num_cols_in, 1, MatrixInPipe, MatrixOutPipe> {
void operator()() const {
while (1) {
auto d = MatrixInPipe::read();
MatrixOutPipe::write(d);
}
}
};
#endif // ifndef __TRANSPOSE_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/CalcWeights.hpp | #ifndef __CALC_WEIGHTS_HPP__
#define __CALC_WEIGHTS_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitCalcWeightsKernel
// Accept y vector (= Rtranspose * R * Ccomplex_conj, calculated using QRD and
// forward/backward substitution) and C vector (steering vector) and calculate
// w (weights) vector = y / (Ctranspose * y)
template <
typename CalcWeightsKernelName, // Name to use for the Kernel
size_t k_num_steering_vectors, // number of steering vectors to accept
size_t k_num_elements, // number of elements in each vector
typename YVectorsInPipe, // Receive the Y vectors.
// Receive one complex float per read.
typename SteeringVectorsInPipe, // Receive the steering (c) vectors.
// Receive one complex float per read.
typename WeightVectorsOutPipe // Send Weight vectors.
// Send one complex float per write.
>
event SubmitCalcWeightsKernel(queue& q) {
// Template parameter checking
static_assert(k_num_steering_vectors > 0,
"k_num_steering_vectors must be greater than 0");
static_assert(std::numeric_limits<char>::max() > k_num_steering_vectors,
"k_num_steering_vectors must fit in a char");
static_assert(k_num_elements >= 0, "k_num_elements must be greater than 0");
static_assert(std::numeric_limits<short>::max() > k_num_elements,
"k_num_elements must fit in a short");
auto e = q.submit([&](handler& h) {
h.single_task<CalcWeightsKernelName>([=] {
while (1) {
char vector_num;
for (vector_num = 0; vector_num < (char)k_num_steering_vectors;
vector_num++) {
ComplexType y_vector[k_num_elements];
ComplexType c_vector[k_num_elements];
// read in the y and c vectors
for (short i = 0; i < (short)k_num_elements; i++) {
y_vector[i] = YVectorsInPipe::read();
c_vector[i] = SteeringVectorsInPipe::read();
}
// calculate Ct * y
ComplexType ctranspose_times_y(0);
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (short i = 0; i < (short)k_num_elements; i++) {
ctranspose_times_y += c_vector[i].conj() * y_vector[i];
}
// calculate 1 / norm(Ctranspose * y)
// Ct * y is a complex number, but it's norm is a real number (float)
// much less computationally intensive to compute reciprocal of a
// real number
float recip_norm_ctranspose_times_y =
half_precision::recip(ctranspose_times_y.mag_sqr());
// calculate the weight vectors
// We want to mulitply each element of y by 1 / Ctranspose * y.
// To reduce comutational complexity, we multiply by conj(Ct * y) and
// divide by norm(Ct * y), where norm(x) = x * conj(x).
for (short i = 0; i < (short)k_num_elements; i++) {
auto w = y_vector[i] * ctranspose_times_y.conj() *
recip_norm_ctranspose_times_y;
WeightVectorsOutPipe::write(w);
}
} // end of for( vector_num... )
} // end of while( 1 )
}); // end of h.single_task
}); // end of q.submit
return e;
} // end of SubmitCalcWeightsKernel()
#endif // ifndef __CALC_WEIGHTS_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/DiagReciprocal.hpp | #ifndef __DIAG_RECIPROCAL__
#define __DIAG_RECIPROCAL__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
// SubmitDiagReciprocalKernel
// Accept an upper-triangular square R Matrix from QR Decomposition from
// StreamingQRD. Compute the reciprocals of the square diagonal and write them
// to an output pipe. All values on the diagonal must be real-valued (imaginary
// part equal to 0)
template <typename DiagReciprocalKernelName, // name to use for kernel
size_t k_r_num_rows, // Number of rows (and cols) in R Matrix
typename RMatrixInPipe, // The R Matrix input
typename RDiagRecipVectorOutPipe // 1 / values on diagonal of R
// Matrix input
>
event SubmitDiagReciprocalKernel(queue& q) {
auto e = q.submit([&](handler& h) {
h.single_task<DiagReciprocalKernelName>([=] {
// calculate total number of elements passed in for one processing
// iteration
constexpr int kElements = k_r_num_rows * (k_r_num_rows + 1) / 2;
while (1) {
int row = 1;
int col = 1;
for (int i = 0; i < kElements; i++) {
ComplexType in = RMatrixInPipe::read();
if (row == col) {
// Reciprocal square root is cheaper to calculate than reciprocal so
// we square the values first
RDiagRecipVectorOutPipe::write(sycl::rsqrt(in.real() * in.real()));
}
// calculate next element's row and col
if (col == k_r_num_rows) {
col = row + 1;
row++;
} else {
col++;
}
}
}
}); // end of h.single_task
}); // end of q.submit
return e;
}
#endif /* __DIAG_RECIPROCAL__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/BackwardSubstitution.hpp | #ifndef __BACKWARD_SUBSTITUTION_HPP__
#define __BACKWARD_SUBSTITUTION_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// utility classes
#include "ParallelCopyArray.hpp"
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitBackwardSubstitutionKernel
// Accept an upper-right square triangular matrix U (in row order) and a
// number of y input vectors, and solve Ux = y for each input vector.
// U must be real valued on the diagonal, and a vector of the reciprocals
// of the diagonal values (UDiagRecipVectorInPipe) must also be supplied.
template <typename BackwardSubstitutionKernelName, // Name to use for the
// Kernel
size_t k_vector_size, // Number of elements in each vector, also
// number of rows and columns in the
// square U matrix
size_t k_unroll_factor, // Factor by which to unroll the innermost
// calculation loop, so k_unroll_factor
// operations will be performed in
// parallel on each clock.
size_t k_num_y_vectors, // Number of y vectors to solve for with
// each new L matrix.
typename UMatrixInPipe, // Receive the upper-triangular matrix U.
// Diagonal must be real valued.
// Only upper right elements are sent,
// (known zero elements are skipped).
// Sent starting with first row.
// Receive one complex float per read.
typename UDiagRecipVectorInPipe, // Receive 1/ the diagonal elements
// of U. Receive one float per read.
typename YVectorsInPipe, // Receive the Y vectors.
// Receive one complex float per read.
typename XVectorsOutPipe // Send X vectors.
// Send one complex float per write.
>
event SubmitBackwardSubstitutionKernel(queue& q) {
// Template parameter checking
static_assert(k_vector_size > 0, "k_vector_size must be greater than 0");
static_assert(std::numeric_limits<short>::max() > k_vector_size,
"k_vector_size must fit in a short");
static_assert(k_num_y_vectors > 0, "k_num_y_vectors must be greater than 0");
static_assert(std::numeric_limits<char>::max() > k_num_y_vectors,
"k_num_y_vectors must fit in a char");
static_assert(k_vector_size % k_unroll_factor == 0,
"k_vector_size must be evenly divisible by k_unroll_factor");
// this type represents the number of samples to be processed in parallel
// grouping these into an array helps the compiler generate the desired local
// memory configurations
using CalcType = ParallelCopyArray<ComplexType, k_unroll_factor>;
constexpr short kNumCalcTypePerVector = k_vector_size / k_unroll_factor;
auto e = q.submit([&](handler& h) {
h.single_task<BackwardSubstitutionKernelName>([=] {
while (1) {
CalcType u_matrix[k_vector_size][kNumCalcTypePerVector];
float u_diag_recip_vector[k_vector_size];
// number of non-zero elements in the U matrix
// 1+2+3+...+n = (n)(n+1)/2
constexpr int kNumUElements = (k_vector_size) * (k_vector_size + 1) / 2;
// receive the U matrix and diagonal reciprocal vector from the pipes
short col = 0;
short row = 0;
for (int i = 0; i < kNumUElements; i++) {
u_matrix[col][row / k_unroll_factor][row % k_unroll_factor] =
UMatrixInPipe::read();
if (col == row) {
u_diag_recip_vector[row] = UDiagRecipVectorInPipe::read();
}
col++;
if (col == (short)k_vector_size) {
row++; // row counts 0..k_vector_size
col = row; // col counts 0..k_vector_size, 1..k_vector_size, ...
}
}
for (char vector_num = 0; vector_num < (char)k_num_y_vectors;
vector_num++) {
// y_vector_intial contains the unmodified current y vector. y_vector
// is used during processing. Splitting these two vectors allows
// each to be implemented in a local memory with only one read and
// one write port.
CalcType y_vector_initial[kNumCalcTypePerVector];
CalcType y_vector[kNumCalcTypePerVector];
// This variable represents the value of y[col] for the next iteration
// of the col loop (see below). Storing this value here prevents
// the need for an additional read from y_vector[], which would result
// in a second read port for the y_vector[] memory system.
ComplexType y_at_next_col_pos;
// load a new y vector from the pipe
for (short i = 0; i < (short)k_vector_size; i++) {
ComplexType y_pipe_in = YVectorsInPipe::read();
y_vector_initial[i / k_unroll_factor][i % k_unroll_factor] =
y_pipe_in;
if (i == (short)k_vector_size - 1) {
y_at_next_col_pos = y_pipe_in;
}
}
// calculate x for the current y vector
ComplexType x_vector[k_vector_size];
// iterate over all columns in U
for (short col = k_vector_size - 1; col >= 0; col--) {
// y_scaled = y[col] / L[col][col] (diagonal value of L)
ComplexType y_scaled;
y_scaled = y_at_next_col_pos * u_diag_recip_vector[col];
// store the calculated result to the x_vector
x_vector[col] = y_scaled;
// iterate over all rows of U in the current column
// unroll by a factor of k_unroll_factor (so perform k_unroll_factor
// operations in parallel)
// NO-FORMAT comments are for clang-format
[[intel::speculated_iterations(0)]] // NO-FORMAT: Attribute
for (short i = 0; i < kNumCalcTypePerVector; i++) {
// These variables are used to help the compiler infer the
// desired memory organization.
CalcType u_val, y_val, y_initial_val, y_current, y_new;
short row[k_unroll_factor];
fpga_tools::UnrolledLoop<k_unroll_factor>([&](auto j) {
// calculate current location within the vector
row[j] = j + (i * (short)k_unroll_factor);
// force u values to 0 for upper right of matrix (including
// the diagonal)
u_val[j] = u_matrix[col][i][j];
if (row[j] >= col) u_val[j] = 0;
// If we place the accesses to y_vector and y_vector_intial
// inside the if/else statement, it results in a very strange
// configuration of the y_vector memory system, so use these
// intermediate variables.
y_val[j] = y_vector[i][j];
y_initial_val[j] = y_vector_initial[i][j];
if (col == (short)k_vector_size - 1) {
y_current[j] = y_initial_val[j];
} else {
y_current[j] = y_val[j];
}
// perform the calculation on y and store the result back into
// y_vector
y_new[j] = y_current[j] - y_scaled * u_val[j];
y_vector[i][j] = y_new[j];
// update y_at_next_col_pos for the next iteration of the col
// loop
if (row[j] == col - 1) {
y_at_next_col_pos = y_new[j];
}
}); // end of unrolled loop
} // end of for( v... )
} // end of for( col... )
// write the result to the output pipe
for (short i = 0; i < (short)k_vector_size; i++) {
XVectorsOutPipe::write(x_vector[i]);
}
} // end of for( vector_num ... )
} // end of while( 1 )
}); // end of h.single_task
}); // end of q.submit
return e;
} // end of SubmitBackwardSubstitutionKernel()
#endif // ifndef __BACKWARD_SUBSTITUTION_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/udp_loopback_test.cpp | #include <algorithm>
#include <chrono>
#include <cstdlib>
#include <iostream>
#include <numeric>
#include <string>
#include <thread>
#include <sys/mman.h>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "Tuple.hpp"
#include "UDP.hpp"
using WordType = unsigned long long;
static_assert(sizeof(WordType) <= kUDPDataSize);
static_assert((kUDPDataSize % sizeof(WordType)) == 0);
constexpr size_t kWordsPerPacket = kUDPDataSize / sizeof(WordType);
using namespace sycl;
using namespace std::chrono;
// declare kernel and pipe IDs globally to reduce name mangling
class RealLoopbackKernel;
class NoopKernel;
struct WriteIOPipeID {
static constexpr unsigned id = 0;
};
struct ReadIOPipeID {
static constexpr unsigned id = 1;
};
// the IO pipes
struct IOPipeType {
uchar dat[8];
};
using WriteIOPipe =
ext::intel::kernel_writeable_io_pipe<WriteIOPipeID, IOPipeType, 512>;
using ReadIOPipe =
ext::intel::kernel_readable_io_pipe<ReadIOPipeID, IOPipeType, 512>;
// submits the main processing kernel, templated on the input and output pipes
// NOTE: this kernel is agnostic to whether the input/output pipe is a 'real'
// or 'fake' IO pipe.
template <typename IOPipeIn, typename IOPipeOut>
event SubmitLoopbackKernel(queue &q) {
return q.submit([&](handler &h) {
h.single_task<RealLoopbackKernel>([=] {
while (1) {
auto data = IOPipeIn::read();
IOPipeOut::write(data);
}
});
});
}
// this is a kernel that does no work, it is used as a detection mechanism for
// the FPGA being programmed
event SubmitNoopKernel(queue &q) {
return q.submit([&](handler &h) { h.single_task<NoopKernel>([=] {}); });
}
int main(int argc, char **argv) {
unsigned long fpga_mac_adr = 0;
unsigned long host_mac_adr = 0;
unsigned int fpga_udp_port = 0;
unsigned int host_udp_port = 0;
char *fpga_ip_address = nullptr;
char *fpga_netmask = nullptr;
char *host_ip_address = nullptr;
size_t packets = 100000000;
if (argc < 8) {
std::cout << "USAGE: ./mvdr_beamforming.fpga fpga_mac_adr fpga_ip_addr "
<< "fpga_udp_port fpga_netmask host_mac_adr host_ip_addr "
<< "host_udp_port [packets]\n";
std::cout << "EXAMPLE: ./mvdr_beamforming.fpga 64:4C:36:00:2F:20 "
<< "192.168.0.11 34543 255.255.255.0 94:40:C9:71:8D:10 "
<< " 192.168.0.10 34543 1024 .\n";
}
// parse FPGA and HOST MAC addresses
fpga_mac_adr = ParseMACAddress(argv[1]);
host_mac_adr = ParseMACAddress(argv[5]);
// parse ports
fpga_udp_port = (unsigned int)atoi(argv[3]);
host_udp_port = (unsigned int)atoi(argv[7]);
// get IP addresses and netmask
fpga_ip_address = argv[2];
fpga_netmask = argv[4];
host_ip_address = argv[6];
// parse number of packets (optional arg)
if (argc > 8) {
packets = atoi(argv[8]);
}
printf("\n");
printf("FPGA MAC Address: %012lx\n", fpga_mac_adr);
printf("FPGA IP Address: %s\n", fpga_ip_address);
printf("FPGA UDP Port: %d\n", fpga_udp_port);
printf("FPGA Netmask: %s\n", fpga_netmask);
printf("Host MAC Address: %012lx\n", host_mac_adr);
printf("Host IP Address: %s\n", host_ip_address);
printf("Host UDP Port: %d\n", host_udp_port);
printf("Packets: %zu\n", packets);
printf("\n");
// set up SYCL queue
ext::intel::fpga_selector device_selector;
queue q(device_selector);
// input and output packet words
const size_t total_elements = kWordsPerPacket * packets;
std::vector<WordType> input(total_elements);
std::vector<WordType> output(total_elements);
// fill input, set output
std::iota(input.begin(), input.end(), 0);
std::fill(output.begin(), output.end(), 0);
// allocate aligned memory for input and output data
// total bytes including the 2-byte header per packet
unsigned char *input_data = AllocatePackets(packets);
unsigned char *output_data = AllocatePackets(packets);
// prepare data to be transferred, added check header 0xABCD, reset output
std::cout << "Creating packets from input data" << std::endl;
ToPackets(input_data, input.data(), total_elements);
// these are used to track the latency of each packet
std::vector<high_resolution_clock::time_point> time_in(packets);
std::vector<high_resolution_clock::time_point> time_out(packets);
// start the main kernel
std::cout << "Starting processing kernel on the FPGA" << std::endl;
auto kernel_event = SubmitLoopbackKernel<ReadIOPipe, WriteIOPipe>(q);
// Here, we start the noop kernel and wait for it to finish.
// By waiting on the finish we assure that the FPGA has been programmed with
// the image and the setting of CSRs SetupFPGA will not be undone with by the
// runtime reprogramming the FPGA.
std::cout << "Starting and waiting on Noop kernel to ensure "
<< "that the FPGA is programmed \n";
SubmitNoopKernel(q).wait();
// Setup CSRs on FPGA (this function is in UDP.hpp)
// NOTE: this must be done AFTER programming the FPGA, which happens
// when the kernel is launched (if it is not already programmed)
SetupFPGA(fpga_mac_adr, fpga_ip_address, fpga_udp_port, fpga_netmask,
host_mac_adr, host_ip_address, host_udp_port);
std::this_thread::sleep_for(10ms);
// Start the receiver
std::cout << "Starting receiver thread" << std::endl;
std::thread receiver_thread([&] {
std::this_thread::sleep_for(20ms);
std::cout << "Receiver running on CPU " << sched_getcpu() << "\n";
UDPReceiver(host_ip_address, fpga_udp_port, output_data, packets,
time_out.data());
});
// pin the receiver to core 1
if (PinThreadToCPU(receiver_thread, 1) != 0) {
std::cerr << "ERROR: could not pin receiver thread to core 1\n";
}
// give some time for the receiever to start
std::this_thread::sleep_for(10ms);
// Start the sender
std::cout << "Starting sender thread" << std::endl;
std::thread sender_thread([&] {
std::this_thread::sleep_for(20ms);
std::cout << "Sender running on CPU " << sched_getcpu() << "\n";
UDPSender(fpga_ip_address, host_udp_port, input_data, packets,
time_in.data());
});
// pin the sender to core 3
if (PinThreadToCPU(sender_thread, 3) != 0) {
std::cerr << "ERROR: could not pin sender thread to core 3\n";
}
// wait for sender and receiver threads to finish
sender_thread.join();
receiver_thread.join();
// DON'T wait for kernel to finish, since it is an infinite loop
// kernel_event.wait();
// compute average latency (ignore the first couple of packets)
double avg_latency = 0.0;
constexpr size_t kWarmupPackets = 8;
for (size_t i = kWarmupPackets; i < packets; i++) {
duration<double, std::milli> diff(time_out[i] - time_in[i]);
avg_latency += diff.count();
}
avg_latency /= (packets - kWarmupPackets);
std::cout << "Average end-to-end packet latency: " << avg_latency << " ms\n";
// convert the output bytes to data (drop the headers)
std::cout << "Getting output data from packets" << std::endl;
FromPackets(output_data, output.data(), total_elements);
// validate results
bool passed = true;
for (size_t i = 0; i < total_elements; i++) {
if (output[i] != input[i]) {
std::cerr << "ERROR: output mismatch at index " << i << ", " << output[i]
<< " != " << input[i] << " (output != input)\n";
passed = false;
}
}
// Custom free function unpins and frees memory
FreePackets(input_data, packets);
FreePackets(output_data, packets);
if (passed) {
std::cout << "PASSED\n";
return 0;
} else {
std::cout << "FAILED\n";
return 1;
}
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/FakeIOPipes.hpp | #ifndef __FAKEIOPIPES_HPP__
#define __FAKEIOPIPES_HPP__
#include <iostream>
#include <type_traits>
#include <utility>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// the "detail" namespace is commonly used in C++ as an internal namespace
// (to a file) that is not meant to be visible to the public and should be
// ignored by external users. That is to say, you should never have the line:
// "using namespace detail;" in your code!
//
// "internal" is another common name for a namespace like this.
namespace detail {
using namespace sycl;
template <typename ID, typename T, bool use_host_alloc>
class ProducerConsumerBaseImpl {
protected:
// private members
static inline T *host_data_{nullptr};
static inline T *device_data_{nullptr};
static inline size_t count_{};
static inline bool initialized_{false};
// use some fancy C++ metaprogramming to get the correct pointer type
// based on the template variable
typedef
typename std::conditional_t<use_host_alloc, host_ptr<T>, device_ptr<T>>
kernel_ptr_type;
// private constructor so users cannot make an object
ProducerConsumerBaseImpl(){};
static T *get_kernel_ptr() {
return use_host_alloc ? host_data_ : device_data_;
}
static void initialized_check() {
if (!initialized_) {
std::cerr << "ERROR: Init() has not been called\n";
std::terminate();
}
}
public:
// disable copy constructor and operator=
ProducerConsumerBaseImpl(const ProducerConsumerBaseImpl &) = delete;
ProducerConsumerBaseImpl &operator=(ProducerConsumerBaseImpl const &) =
delete;
static void Init(queue &q, size_t count) {
// make sure init hasn't already been called
if (initialized_) {
std::cerr << "ERROR: Init() was already called\n";
std::terminate();
}
// track count
count_ = count;
// check for USM support
device d = q.get_device();
if (!q.get_device().has(aspect::usm_host_allocations) && use_host_alloc) {
std::cerr << "ERROR: The selected device does not support USM host"
<< " allocations\n";
std::terminate();
}
#if defined(IS_BSP)
// Device allocations are only used in BSP mode
if (!q.get_device().has(aspect::usm_device_allocations)) {
std::cerr << "ERROR: The selected device does not support USM device"
<< " allocations\n";
std::terminate();
}
#endif
// Allocate the space the user requested. Calling a different malloc
// based on whether the user wants to use USM host allocations or not.
if (use_host_alloc) {
host_data_ = malloc_host<T>(count_, q);
} else {
host_data_ = new T[count_];
}
if (host_data_ == nullptr) {
std::cerr << "ERROR: failed to allocate space for host_data_\n";
std::terminate();
}
// if not using host allocations, allocate device memory
if (!use_host_alloc) {
device_data_ = malloc_device<T>(count_, q);
if (device_data_ == nullptr) {
std::cerr << "ERROR: failed to allocate space for"
<< "device_data_\n";
std::terminate();
}
}
initialized_ = true;
}
static void Destroy(queue &q) {
initialized_check();
// free memory depending on 'use_host_alloc' flag
if (use_host_alloc) {
// free USM host allocation
sycl::free(host_data_, q);
} else {
// free C++ allocated memory
delete[] host_data_;
// free USM device allocation
sycl::free(device_data_, q);
}
initialized_ = false;
}
static size_t Count() {
initialized_check();
return count_;
}
static T *Data() {
initialized_check();
return host_data_;
}
};
////////////////////////////////////////////////////////////////////////////////
// Producer implementation
template <typename Id, typename T, bool use_host_alloc, size_t min_capacity>
class ProducerImpl : public ProducerConsumerBaseImpl<Id, T, use_host_alloc> {
private:
// base implementation alias
using BaseImpl = ProducerConsumerBaseImpl<Id, T, use_host_alloc>;
using kernel_ptr_type = typename BaseImpl::kernel_ptr_type;
// IDs for the pipe and kernel
class PipeID;
class KernelID;
// private constructor so users cannot make an object
ProducerImpl(){};
public:
// disable copy constructor and operator=
ProducerImpl(const ProducerImpl &) = delete;
ProducerImpl &operator=(ProducerImpl const &) = delete;
// the pipe to connect to in device code
using Pipe = sycl::ext::intel::pipe<PipeID, T, min_capacity>;
// the implementation of the static
static std::pair<event, event> Start(queue &q,
size_t count = BaseImpl::count_) {
// make sure initialized has been called
BaseImpl::initialized_check();
// can't produce more data than exists
if (count > BaseImpl::count_) {
std::cerr << "ERROR: Start() called with count=" << count
<< " but allocated size is " << BaseImpl::count_ << "\n";
std::terminate();
}
// If we aren't using USM host allocations, must transfer memory to device
event dma_event;
if (!use_host_alloc) {
dma_event = q.memcpy(BaseImpl::device_data_, BaseImpl::host_data_,
BaseImpl::count_ * sizeof(T));
}
// pick the right pointer to pass to the kernel
auto kernel_ptr = BaseImpl::get_kernel_ptr();
// launch the kernel (use event.depends_on to wait on the memcpy)
auto kernel_event = q.submit([&](handler &h) {
// the kernel must wait until the DMA transfer is done before launching
// this will only take affect it we actually performed the DMA above
h.depends_on(dma_event);
// the producing kernel
// NO-FORMAT comments are for clang-format
h.single_task<Id>([=
]() [[intel::kernel_args_restrict]] { // NO-FORMAT: Attribute
kernel_ptr_type ptr(kernel_ptr);
for (size_t i = 0; i < count; i++) {
auto d = *(ptr + i);
Pipe::write(d);
}
});
});
return std::make_pair(dma_event, kernel_event);
}
};
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Consumer implementation
template <typename Id, typename T, bool use_host_alloc, size_t min_capacity>
class ConsumerImpl : public ProducerConsumerBaseImpl<Id, T, use_host_alloc> {
private:
// base implementation alias
using BaseImpl = ProducerConsumerBaseImpl<Id, T, use_host_alloc>;
using kernel_ptr_type = typename BaseImpl::kernel_ptr_type;
// IDs for the pipe and kernel
class PipeID;
class KernelID;
// private constructor so users cannot make an object
ConsumerImpl(){};
public:
// disable copy constructor and operator=
ConsumerImpl(const ConsumerImpl &) = delete;
ConsumerImpl &operator=(ConsumerImpl const &) = delete;
// the pipe to connect to in device code
using Pipe = sycl::ext::intel::pipe<PipeID, T, min_capacity>;
static std::pair<event, event> Start(queue &q,
size_t count = BaseImpl::count_) {
// make sure initialized has been called
BaseImpl::initialized_check();
// can't produce more data than exists
if (count > BaseImpl::count_) {
std::cerr << "ERROR: Start() called with count=" << count
<< " but allocated size is " << BaseImpl::count_ << "\n";
std::terminate();
}
// pick the right pointer to pass to the kernel
auto kernel_ptr = BaseImpl::get_kernel_ptr();
// launch the kernel to read the output into device side global memory
auto kernel_event = q.submit([&](handler &h) {
// NO-FORMAT comments are for clang-format
h.single_task<Id>([=
]() [[intel::kernel_args_restrict]] { // NO-FORMAT: Attribute
kernel_ptr_type ptr(kernel_ptr);
for (size_t i = 0; i < count; i++) {
auto d = Pipe::read();
*(ptr + i) = d;
}
});
});
// if the user wanted to use board memory, copy the data back to the host
event dma_event;
if (!use_host_alloc) {
// launch a task to copy the data back from the device. Use the
// event.depends_on signal to wait for the kernel to finish first.
dma_event = q.submit([&](handler &h) {
h.depends_on(kernel_event);
h.memcpy(BaseImpl::host_data_, BaseImpl::device_data_,
BaseImpl::count_ * sizeof(T));
});
}
return std::make_pair(dma_event, kernel_event);
}
};
////////////////////////////////////////////////////////////////////////////////
} // namespace detail
// alias the implementations to face the user
template <typename Id, typename T, bool use_host_alloc, size_t min_capacity = 0>
using Producer = detail::ProducerImpl<Id, T, use_host_alloc, min_capacity>;
template <typename Id, typename T, bool use_host_alloc, size_t min_capacity = 0>
using Consumer = detail::ConsumerImpl<Id, T, use_host_alloc, min_capacity>;
// convenient aliases to get a host or device allocation producer/consumer
template <typename Id, typename T, size_t min_capacity = 0>
using HostConsumer = Consumer<Id, T, true, min_capacity>;
template <typename Id, typename T, size_t min_capacity = 0>
using DeviceConsumer = Consumer<Id, T, false, min_capacity>;
template <typename Id, typename T, size_t min_capacity = 0>
using HostProducer = Producer<Id, T, true, min_capacity>;
template <typename Id, typename T, size_t min_capacity = 0>
using DeviceProducer = Producer<Id, T, false, min_capacity>;
#endif /* __FAKEIOPIPES_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/SteeringVectorGenerator.hpp | #ifndef __STEERING_VECTOR_GENERATOR_HPP__
#define __STEERING_VECTOR_GENERATOR_HPP__
#define _USE_MATH_DEFINES
#include <cmath>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitSteeringVectorGeneratorKernel
// Accept the value sin(theta) for a defined number of steering vectors from a
// pipe. Only read in new sin(theta) values when a value is available for
// every steering vector, as indicated by reads from a second pipe.
// For each sin(theta) value, generate a steering vector and write it to a
// output channel a single complex number at a time.
template <
typename SteeringVectorGeneratorKernelName, // Name to use for the Kernel
size_t k_num_steering_vectors, // number of steering vectors to generate
size_t k_num_elements, // number of elements in each vector
typename SinThetaInPipe, // sin(theta) input, updated by another
// kernel with updates from the host.
// Accept one float per read.
typename SteeringVectorsOutPipe, // Write the generated steering vectors.
// Send one complex number per write.
typename UpdateSteeringOutPipe // Write to this pipe when a full set of
// steering vectors have been sent.
// Send one bool per write.
>
event SubmitSteeringVectorGeneratorKernel(queue& q) {
// Template parameter checking
static_assert(k_num_steering_vectors > 0,
"k_num_steering_vectors must be greater than 0");
static_assert(std::numeric_limits<char>::max() > k_num_steering_vectors,
"k_num_steering_vectors must fit in a char");
static_assert(k_num_elements >= 0, "k_num_elements must be greater than 0");
static_assert(std::numeric_limits<short>::max() > k_num_elements,
"k_num_elements must fit in a short");
auto e = q.submit([&](handler& h) {
h.single_task<SteeringVectorGeneratorKernelName>([=] {
while (1) {
char vector_num;
for (vector_num = 0; vector_num < (char)k_num_steering_vectors;
vector_num++) {
// fetch the value of sintheta from the pipe
float sintheta;
sintheta = SinThetaInPipe::read();
// calculate the elements of the current steering vector and write
// them to the SteeringVectorOutPipe
// steering_vector[n] = e^-(i * pi * n * sin(theta))
// e^-(i * t) = cos(t) - i*sin(t)
for (short n = 0; n < (short)k_num_elements; n++) {
float pi_n_sintheta = (float)M_PI * n * sintheta;
ComplexType vector_element(sycl::cos(pi_n_sintheta),
(-1) * sycl::sin(pi_n_sintheta));
SteeringVectorsOutPipe::write(vector_element);
}
} // end of for(...) iterating over all steering vectors
// indicate to downstream kernels that a full set of steering vectors
// are available
// The fence here ensures that all writes to the SteeringVectorsOutPipe
// above will occur before the write to the pipe below. Without the
// fence, the compiler could re-order these pipe writes.
sycl::atomic_fence(sycl::memory_order::acq_rel,
sycl::memory_scope::device);
UpdateSteeringOutPipe::write(true);
} // end of while( 1 )
}); // end of h.single_task
}); // end of q.submit
return e;
} // end of SubmitSteeringVectorGeneratorKernel()
#endif // ifndef __STEERING_VECTOR_GENERATOR_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/Constants.hpp | #ifndef __CONSTANTS_HPP__
#define __CONSTANTS_HPP__
// Allow design parameters to be defined on the command line
// check is USM host allocations are enabled
#ifdef USM_HOST_ALLOCATIONS
constexpr bool kUseUSMHostAllocation = true;
#else
constexpr bool kUseUSMHostAllocation = false;
#endif
// Large array is 64 sensors. This is not the default because the Quartus®
// compile time at this size is very long (> 24 hours)
#ifdef LARGE_SENSOR_ARRAY
#define NUM_SENSORS 64
#endif
// number of sensors (= number of columns for QRD)
// Default is the 'small' size of 16 sensors
#ifndef NUM_SENSORS
#define NUM_SENSORS 16
#endif
// RMB factor (number of rows for QRD = NUM_SENSORS * RMB_FACTOR)
// Typically 3 or 5, larger number gives better SNR
#ifndef RMB_FACTOR
#define RMB_FACTOR 3
#endif
// use the SMALL_INPUT setting if the input pipe is unable to keep up and
// you want to reduce the bandwidth requirements without reducing the number
// of training matrices/s that can be processed
#ifdef SMALL_INPUT
#define NUM_INPUT_VECTORS NUM_SENSORS
#endif
// Number of input vectors to process with each training matrix
// Default to use the same size as the training matrix
#ifndef NUM_INPUT_VECTORS
#define NUM_INPUT_VECTORS (NUM_SENSORS * RMB_FACTOR)
#endif
// Number of steering vectors
#ifndef NUM_STEER
#define NUM_STEER 25
#endif
// Number of complex numbers received on each read from the streaming input
// pipe (= width of pipe in bytes / 8 )
// Must be a power of 2. A value less than 4 may cause the input pipe to be
// the limiting factor on throughput
#ifndef STREAMING_PIPE_WIDTH
#define STREAMING_PIPE_WIDTH 4
#endif
// Degree of folding for substitution kernels
#ifndef SUBSTITUTION_FOLDING_FACTOR
#define SUBSTITUTION_FOLDING_FACTOR 1 // default to full unroll
#endif
// Degree of folding for beamformer kernel
#ifndef BEAMFORMING_FOLDING_FACTOR
#define BEAMFORMING_FOLDING_FACTOR 1 // default to full unroll
#endif
// minimum iterations for QRD
#ifndef QRD_MIN_ITERATIONS
#define QRD_MIN_ITERATIONS 80
#endif
// constants
constexpr int kNumSensorInputs = NUM_SENSORS;
constexpr int kRMBFactor = RMB_FACTOR;
constexpr int kTrainingMatrixNumRows = NUM_SENSORS * RMB_FACTOR;
constexpr int kNumInputVectors = NUM_INPUT_VECTORS;
constexpr int kNumSteer = NUM_STEER;
constexpr int kNumComplexPerXrxPipe = STREAMING_PIPE_WIDTH;
constexpr int kSubstitutionUnrollFactor =
NUM_SENSORS / SUBSTITUTION_FOLDING_FACTOR;
constexpr int kBeamformingUnrollFactor =
NUM_SENSORS / BEAMFORMING_FOLDING_FACTOR;
constexpr int kQRDMinIterations = QRD_MIN_ITERATIONS;
#endif // __CONSTANTS_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/mvdr_beamforming.cpp | #define _USE_MATH_DEFINES
#include <cmath>
#include <chrono>
#include <cstring>
#include <iomanip>
#include <thread>
#include <vector>
#include <fstream>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
#if not defined(REAL_IO_PIPES)
#include "exception_handler.hpp"
#endif
#include "Constants.hpp"
#include "FakeIOPipes.hpp"
#include "MVDR.hpp"
#if defined(REAL_IO_PIPES) && defined(FPGA_EMULATOR)
static_assert(false, "Real IO pipes cannot be emulated for this design");
#endif
#if defined(REAL_IO_PIPES) && (defined(_WIN32) || defined(_WIN64))
static_assert(false, "Real IO pipes cannot be used in windows");
#endif
#if defined(REAL_IO_PIPES)
#include <sys/mman.h>
#include "UDP.hpp"
#endif
using namespace sycl;
using namespace std::chrono_literals;
using namespace std::chrono;
// We will have the producer and consumer use USM host allocations
// if they are enabled, otherwise they use device allocations
template <typename Id, typename T, size_t min_capacity = 0>
using MyProducer = Producer<Id, T, kUseUSMHostAllocation, min_capacity>;
template <typename Id, typename T, size_t min_capacity = 0>
using MyConsumer = Consumer<Id, T, kUseUSMHostAllocation, min_capacity>;
////////////////////////////////////////////////////////////////////////////////
// utility functions
std::ostream &operator<<(std::ostream &os, const ComplexType &val) {
os << val.real() << " + " << val.imag() << "i";
return os;
}
bool AlmostEqual(float x, float y, float epsilon = 0.0004f) {
return std::fabs(x - y) < epsilon;
}
bool AlmostEqual(ComplexType x, ComplexType y, float epsilon = 0.0004f) {
bool real_close = AlmostEqual(x.real(), y.real(), epsilon);
bool imag_close = AlmostEqual(x.imag(), y.imag(), epsilon);
return real_close && imag_close;
}
////////////////////////////////////////////////////////////////////////////////
// Forward declare the kernel names to reduce name mangling
#if not defined(REAL_IO_PIPES)
class DataProducerID;
class DataOutConsumerID;
#endif
class SinThetaProducerID;
// the data type that goes through the IO pipes; both fake and real
using XrxPipeType = fpga_tools::NTuple<ComplexType, kNumComplexPerXrxPipe>;
// size of Training Data matrix, in units of XrxPipeTypes
constexpr size_t kTrainingDataSize =
kNumSensorInputs * kTrainingMatrixNumRows / kNumComplexPerXrxPipe;
// size of data to be processed, in units of XrxPipeTypes
constexpr size_t kXrxDataSize =
kNumSensorInputs * kNumInputVectors / kNumComplexPerXrxPipe;
// size of header data per set of training and processing data matrices, in
// units of XrxPipeTypes (one header word per matrix)
constexpr size_t kHeadersSize = 2;
// total size of one 'quanta' of input data, in units of XrxPipeTypes
constexpr size_t kInputDataSize =
kTrainingDataSize + kXrxDataSize + kHeadersSize;
// total size of one 'quanta' of output data, in units of ComplexTypes
constexpr size_t kDataOutSize = kNumInputVectors * kNumSteer;
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// host producer and consumers
#if defined(REAL_IO_PIPES)
// REAL IO PIPES
struct ReadIOPipeID {
static constexpr unsigned id = 1;
};
struct WriteIOPipeID {
static constexpr unsigned id = 0;
};
using DataInPipe =
ext::intel::kernel_readable_io_pipe<ReadIOPipeID, XrxPipeType, 512>;
using DataOutPipe =
ext::intel::kernel_writeable_io_pipe<WriteIOPipeID, XrxPipeType, 512>;
#else
// FAKE IO PIPES
using DataProducer =
MyProducer<DataProducerID, XrxPipeType, kInputDataSize * 2>;
using DataInPipe = DataProducer::Pipe;
using DataOutConsumer =
MyConsumer<DataOutConsumerID, ComplexType, kDataOutSize * 2>;
using DataOutPipe = DataOutConsumer::Pipe;
#endif
using SinThetaProducer = MyProducer<SinThetaProducerID, float, kNumSteer * 2>;
using SinThetaPipe = SinThetaProducer::Pipe;
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// File I/O
bool ReadInputData(std::string in_dir, ComplexType *data_in,
int num_matrix_copies);
bool WriteOutputData(std::string out_dir, ComplexType *data_out);
bool CheckOutputData(std::string in_dir, ComplexType *data_out,
int num_matrix_copies, bool print_diffs);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
struct UDPArgs {
unsigned long fpga_mac_addr = 0;
unsigned long host_mac_addr = 0;
unsigned int fpga_udp_port = 0;
unsigned int host_udp_port = 0;
char *fpga_ip_addr = nullptr;
char *fpga_netmask = nullptr;
char *host_ip_addr = nullptr;
};
// arguments
bool ParseArgs(int argc, char *argv[], int &num_matrix_copies,
std::string &in_dir, std::string &out_dir, UDPArgs *udp_args);
void PrintUsage();
////////////////////////////////////////////////////////////////////////////////
// the main function
int main(int argc, char *argv[]) {
UDPArgs udp_args;
#if defined(FPGA_SIMULATOR)
int num_matrix_copies = 2;
#else
int num_matrix_copies = 1024;
#endif
std::string in_dir = "../data";
std::string out_dir = ".";
// parse the command line arguments
if (!ParseArgs(argc, argv, num_matrix_copies, in_dir, out_dir, &udp_args)) {
PrintUsage();
std::terminate();
}
printf("\n");
#if defined(REAL_IO_PIPES)
printf("FPGA MAC Address: %012lx\n", udp_args.fpga_mac_addr);
printf("FPGA IP Address: %s\n", udp_args.fpga_ip_addr);
printf("FPGA UDP Port: %d\n", udp_args.fpga_udp_port);
printf("FPGA Netmask: %s\n", udp_args.fpga_netmask);
printf("Host MAC Address: %012lx\n", udp_args.host_mac_addr);
printf("Host IP Address: %s\n", udp_args.host_ip_addr);
printf("Host UDP Port: %d\n", udp_args.host_udp_port);
#endif
printf("Matrices: %d\n", num_matrix_copies);
printf("Input Directory: '%s'\n", in_dir.c_str());
printf("Output Directory: '%s'\n", out_dir.c_str());
printf("\n");
bool passed = true;
const size_t in_count = kInputDataSize * num_matrix_copies;
const size_t out_count = kDataOutSize * num_matrix_copies;
// find number of full matrices.
// For the real IO pipes, we cannot send and receive a partial
// packet so we need to find the number of FULL matrices that
// we will send and receive
#if defined(REAL_IO_PIPES)
const size_t in_size = in_count * sizeof(ComplexType);
size_t full_in_packet_count = in_size / kUDPDataSize;
size_t full_in_size = full_in_packet_count * kUDPDataSize;
size_t full_in_count = full_in_size / sizeof(ComplexType);
const size_t num_full_matrix_copies = full_in_count / kInputDataSize;
const size_t full_out_count = kDataOutSize * num_full_matrix_copies;
const size_t full_out_size = full_out_count * sizeof(ComplexType);
const size_t full_out_packet_count = full_out_size / kUDPDataSize;
std::cout << "full_matrix_copies = " << num_full_matrix_copies << "\n";
std::cout << "full_in_packet_count = " << full_in_packet_count << "\n";
std::cout << "full_out_packet_count = " << full_out_packet_count << "\n";
// allocate aligned memory for raw input and output data
unsigned char *in_packets = AllocatePackets(full_in_packet_count);
unsigned char *out_packets = AllocatePackets(full_out_packet_count);
#else
// for the fake IO pipes we don't need to worry about data fitting into
// UDP packets, so the number of full matrices is the amount requested
const size_t num_full_matrix_copies = num_matrix_copies;
#endif
// the input and output data
std::vector<XrxPipeType> in_data(in_count);
std::vector<XrxPipeType> out_data(out_count);
try {
// device selector
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// create the device queue
#if defined(REAL_IO_PIPES)
queue q(selector);
#else
queue q(selector, fpga_tools::exception_handler);
#endif
device device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<info::device::name>().c_str()
<< std::endl;
// initialize the producers and consumers
#if not defined(REAL_IO_PIPES)
DataProducer::Init(q, kInputDataSize * num_matrix_copies);
DataOutConsumer::Init(q, kDataOutSize * num_matrix_copies);
#endif
SinThetaProducer::Init(q, kNumSteer);
// read the input data
passed &=
ReadInputData(in_dir, (ComplexType *)in_data.data(), num_matrix_copies);
if (!passed) {
std::terminate();
}
#if defined(REAL_IO_PIPES)
// convert the input data into UDP packets for the real IO pipes
ToPackets(in_packets, in_data.data(), full_in_count);
#else
// copy the input data to the producer fake IO pipe buffer
std::copy_n(in_data.data(), in_count, DataProducer::Data());
#endif
// calculate the sin(theta) values for each steering vector
constexpr float degree_unit = 120.0f / (kNumSteer - 1);
for (int i = 0; i < kNumSteer; i++) {
float degree = -60.0f + i * degree_unit;
SinThetaProducer::Data()[i] = sycl::sin(degree / 180.0f * M_PI);
}
// launch the mvdr kernels
MVDREventArray mvdr_events;
mvdr_events = SubmitMVDRKernels<
kNumSensorInputs, // number of sensor array inputs
kRMBFactor, // Reed-Mallett-Brennan rule
// Number of 'rows' of sensor data used
// by the QRD is k_num_sensor_inputs *
// k_rmb_factor (generally 2-5)
kNumSteer, // number of steering vectors
kSubstitutionUnrollFactor, // unroll factor used by the forward and
// backward substitution kernels
kBeamformingUnrollFactor, // unroll factor used by beamformer
kQRDMinIterations, // minimum 'inner loop' iterations for QRD
kNumComplexPerXrxPipe, // Number of complex numbers (contained
// in NTuple) per read from the
// Xrx input pipes
DataInPipe, // Input data for MVDR
SinThetaPipe, // sin(theta) input for steering vectors
DataOutPipe // output from MVDR
>(q, kNumInputVectors);
std::cout << "Launched MVDR kernels" << std::endl;
////////////////////////////////////////////////////////////////////////////
// Throughput test
////////////////////////////////////////////////////////////////////////////
std::cout << std::endl
<< "*** Launching throughput test of " << num_matrix_copies
<< " matrices ***" << std::endl;
std::cout << "Sensor inputs : " << kNumSensorInputs
<< std::endl;
std::cout << "Training matrix rows : " << kTrainingMatrixNumRows
<< std::endl;
std::cout << "Data rows per training matrix : " << kNumInputVectors
<< std::endl;
std::cout << "Steering vectors : " << kNumSteer << std::endl;
std::cout << "Streaming pipe width : " << kNumComplexPerXrxPipe
<< std::endl;
// Start the host producer for the sin theta data
// By waiting on this kernel to finish, we are assuring that the runtime
// has already programmed the FPGA with the image for this kernel. This
// makes calling SetupFPGA below safe (for the real IO pipes).
event steer_dma_event, steer_kernel_event;
std::tie(steer_dma_event, steer_kernel_event) =
SinThetaProducer::Start(q, kNumSteer);
steer_dma_event.wait();
steer_kernel_event.wait();
// Setup CSRs on FPGA (this function is in UDP.hpp)
// NOTE: this must be done AFTER programming the FPGA, which happens
// when the kernel is launched (if it is not already programmed)
#if defined(REAL_IO_PIPES)
SetupFPGA(udp_args.fpga_mac_addr, udp_args.fpga_ip_addr,
udp_args.fpga_udp_port, udp_args.fpga_netmask,
udp_args.host_mac_addr, udp_args.host_ip_addr,
udp_args.host_udp_port);
// give some time for the FPGA to set things up
std::this_thread::sleep_for(100ms);
#endif
////////////////////////////////////////////////////////////////////////////
// start the producer and consumer of data
#if defined(REAL_IO_PIPES)
// REAL IO PIPES: start CPU threads to produce/consume data to/from the
// IO pipes of the FPGA using UDP
// start the receiver
std::cout << "Starting receiver thread" << std::endl;
std::thread receiver_thread([&] {
std::this_thread::sleep_for(10ms);
std::cout << "Receiver running on CPU " << sched_getcpu() << "\n";
UDPReceiver(udp_args.host_ip_addr, udp_args.fpga_udp_port, out_packets,
full_out_packet_count, nullptr);
});
// pin the receiver to CPU 1
if (PinThreadToCPU(receiver_thread, 1) != 0) {
std::cerr << "ERROR: could not pin receiver thread to core 1\n";
}
// give a little time for the receiver to start
std::this_thread::sleep_for(20ms);
// Start the sender
std::cout << "Starting sender thread" << std::endl;
std::thread sender_thread([&] {
std::this_thread::sleep_for(10ms);
std::cout << "Sender running on CPU " << sched_getcpu() << "\n";
UDPSender(udp_args.fpga_ip_addr, udp_args.host_udp_port, in_packets,
full_in_packet_count, nullptr);
});
// pin the sender to CPU 3
if (PinThreadToCPU(sender_thread, 3) != 0) {
std::cerr << "ERROR: could not pin sender thread to core 3\n";
}
#else
// start the fake IO pipe kernels
event consume_dma_event, consume_kernel_event;
event produce_dma_event, produce_kernel_event;
std::tie(consume_dma_event, consume_kernel_event) =
DataOutConsumer::Start(q, kDataOutSize * num_matrix_copies);
std::tie(produce_dma_event, produce_kernel_event) =
DataProducer::Start(q, kInputDataSize * num_matrix_copies);
#endif
////////////////////////////////////////////////////////////////////////////
// Wait for the DMA event to finish for the producer before starting the
// timer. If USM host allocations are used, this is a noop.
produce_dma_event.wait();
auto start_time = high_resolution_clock::now();
// wait for producer and consumer to finish
#if defined(REAL_IO_PIPES)
sender_thread.join();
receiver_thread.join();
#else
produce_kernel_event.wait();
consume_kernel_event.wait();
#endif
auto end_time = high_resolution_clock::now();
#if not defined(REAL_IO_PIPES)
// Stop the timer before performing the DMA from the consumer. Again,
// if USM host allocations are used then this is a noop.
consume_dma_event.wait();
#endif
// compute latency and throughput
duration<double, std::milli> process_time(end_time - start_time);
double latency_s = process_time.count() * 1e-3;
double throughput = num_full_matrix_copies / latency_s;
std::cout << "Throughput: " << throughput << " matrices/second\n";
// copy the output back from the consumer
#if defined(REAL_IO_PIPES)
const size_t count_to_extract =
full_out_packet_count * kUDPDataSize / sizeof(ComplexType);
FromPackets(out_packets, out_data.data(), count_to_extract);
const size_t num_out_matrix_copies_to_check =
count_to_extract / kDataOutSize;
#else
std::copy_n(DataOutConsumer::Data(), out_count,
(ComplexType *)out_data.data());
const size_t num_out_matrix_copies_to_check = num_full_matrix_copies;
#endif
// check one instance of output data
passed &= CheckOutputData(in_dir, (ComplexType *)out_data.data(),
num_out_matrix_copies_to_check, true);
if (passed) {
std::cout << "Output data check succeeded" << std::endl;
} else {
std::cout << "Output data check failed" << std::endl;
}
////////////////////////////////////////////////////////////////////////////
// Post-test cleanup
////////////////////////////////////////////////////////////////////////////
#if defined(REAL_IO_PIPES)
FreePackets(in_packets, full_in_packet_count);
FreePackets(out_packets, full_out_packet_count);
#else
DataProducer::Destroy(q);
DataOutConsumer::Destroy(q);
#endif
SinThetaProducer::Destroy(q);
} catch (exception const &e) {
// Catches exceptions in the host code
std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";
// Most likely the runtime couldn't find FPGA hardware!
if (e.code().value() == CL_DEVICE_NOT_FOUND) {
std::cerr << "If you are targeting an FPGA, please ensure that your "
"system has a correctly configured FPGA board.\n";
std::cerr << "Run sys_check in the oneAPI root directory to verify.\n";
std::cerr << "If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR.\n";
}
std::terminate();
}
if (passed) {
std::cout << "PASSED\n";
return 0;
} else {
std::cout << "FAILED\n";
return 1;
}
}
bool ReadInputData(std::string in_dir, ComplexType *data_in,
int num_matrix_copies) {
// file paths relative the base directory
std::string training_real_path = in_dir + "/" + "A_real.txt";
std::string training_imag_path = in_dir + "/" + "A_imag.txt";
std::string x_real_path = in_dir + "/" + "X_real.txt";
std::string x_imag_path = in_dir + "/" + "X_imag.txt";
std::cout << "Reading training data from '" << training_real_path << " and "
<< training_imag_path << std::endl;
// parse A
std::ifstream a_real_is, a_imag_is;
a_real_is.open(training_real_path);
a_imag_is.open(training_imag_path);
if (a_real_is.fail()) {
std::cerr << "Failed to open " << training_real_path << "\n";
return false;
}
if (a_imag_is.fail()) {
std::cerr << "Failed to open " << training_imag_path << "\n";
return false;
}
constexpr float kIsTrainingData = 0.0f;
constexpr float kIsNotTrainingData = 1.0f; // any non-zero number is fine
// insert the header to mark the first training matrix
data_in[0].real() = std::nanf(""); // marks this word as a header
data_in[0].imag() = kIsTrainingData; // marks this as training data
// load the first matrix from the input file
int data_offset = kNumComplexPerXrxPipe; // skip the header
for (size_t i = 0; i < kTrainingMatrixNumRows * kNumSensorInputs; i++) {
a_real_is >> data_in[data_offset + i].real();
a_imag_is >> data_in[data_offset + i].imag();
}
a_real_is.close();
a_imag_is.close();
std::cout << "Reading input data from " << x_real_path << " and "
<< x_imag_path << std::endl;
// parse X
std::ifstream x_real_is, x_imag_is;
x_real_is.open(x_real_path);
x_imag_is.open(x_imag_path);
if (x_real_is.fail()) {
std::cerr << "Failed to open " << x_real_path << "\n";
return false;
}
if (x_imag_is.fail()) {
std::cerr << "Failed to open " << x_imag_path << "\n";
return false;
}
// insert header to mark processing data
data_offset = (kTrainingDataSize + 1) * kNumComplexPerXrxPipe;
data_in[data_offset].real() = std::nanf("");
data_in[data_offset].imag() = kIsNotTrainingData;
data_offset += kNumComplexPerXrxPipe;
// load the first matrix
for (size_t i = 0; i < kInputDataSize * kNumComplexPerXrxPipe; i++) {
x_real_is >> data_in[data_offset + i].real();
x_imag_is >> data_in[data_offset + i].imag();
}
x_real_is.close();
x_imag_is.close();
// copy the first data and training matrices num_matrix_copies times
for (size_t matrix_num = 1; matrix_num < num_matrix_copies; matrix_num++) {
for (size_t i = 0; i < kInputDataSize * kNumComplexPerXrxPipe; i++) {
size_t data_copy_index =
i + (matrix_num * kInputDataSize * kNumComplexPerXrxPipe);
data_in[data_copy_index] = data_in[i];
}
}
return true;
}
bool CheckOutputData(std::string in_dir, ComplexType *data_out,
int num_matrix_copies, bool print_diffs) {
bool match = true;
// file paths relative the base directory
std::string expected_out_real_path =
in_dir + "/" + "small_expected_out_real.txt";
std::string expected_out_imag_path =
in_dir + "/" + "small_expected_out_imag.txt";
#ifdef LARGE_SENSOR_ARRAY
expected_out_real_path = in_dir + "/" + "large_expected_out_real.txt";
expected_out_imag_path = in_dir + "/" + "large_expected_out_imag.txt";
#endif
if (print_diffs) {
std::cout << "Checking output data against " << expected_out_real_path
<< " and " << expected_out_imag_path << std::endl;
}
std::ifstream exp_real_is, exp_imag_is;
exp_real_is.open(expected_out_real_path);
exp_imag_is.open(expected_out_imag_path);
if (exp_real_is.fail()) {
std::cerr << "Failed to open " << expected_out_real_path << "\n";
return false;
}
if (exp_imag_is.fail()) {
std::cerr << "Failed to open " << expected_out_imag_path << "\n";
return false;
}
// parse the expected output data
std::vector<ComplexType> ref_data(kNumInputVectors * kNumSteer);
for (size_t i = 0; i < kNumInputVectors; i++) {
for (size_t j = 0; j < kNumSteer; j++) {
exp_real_is >> ref_data[i * kNumSteer + j].real();
exp_imag_is >> ref_data[i * kNumSteer + j].imag();
}
}
exp_real_is.close();
exp_imag_is.close();
// validate the result for all output matrices
for (size_t m = 0; m < num_matrix_copies; m++) {
for (size_t i = 0; i < kNumInputVectors; i++) {
for (size_t j = 0; j < kNumSteer; j++) {
auto result =
data_out[m * kNumSteer * kNumInputVectors + i * kNumSteer + j];
auto expected = ref_data[i * kNumSteer + j];
if (!AlmostEqual(expected, result)) {
if (print_diffs) {
std::cout << "Error in output matrix " << m << " for input vector "
<< i << ", steering vector " << j << ".\n"
<< "Expected: " << expected << ", "
<< "Actual: " << result << "\n";
}
match = false;
}
}
}
}
return match;
}
bool WriteOutputData(std::string out_dir, ComplexType *data_out) {
// file paths relative the base directory
std::string out_real_path = out_dir + "/" + "out_real.txt";
std::string out_imag_path = out_dir + "/" + "out_imag.txt";
std::cout << "Writing output to " << out_real_path << " and " << out_imag_path
<< std::endl;
std::ofstream out_real_os, out_imag_os;
out_real_os.open(out_real_path, std::ios::out | std::ios::trunc);
out_imag_os.open(out_imag_path, std::ios::out | std::ios::trunc);
if (out_real_os.fail()) {
std::cerr << "Failed to open " << out_real_path << "\n";
return false;
}
if (out_imag_os.fail()) {
std::cerr << "Failed to open " << out_imag_path << "\n";
return false;
}
for (size_t i = 0; i < kNumInputVectors; i++) {
for (size_t j = 0; j < kNumSteer; j++) {
out_real_os << std::fixed << std::setw(11)
<< data_out[i * kNumSteer + j].real() << " ";
out_imag_os << std::fixed << std::setw(11)
<< data_out[i * kNumSteer + j].imag() << " ";
}
out_real_os << std::endl;
out_imag_os << std::endl;
}
out_real_os.close();
out_imag_os.close();
return true;
}
bool ParseArgs(int argc, char *argv[], int &num_matrix_copies,
std::string &in_dir, std::string &out_dir, UDPArgs *udp_args) {
#if defined(REAL_IO_PIPES)
if (argc < 8) {
return false;
} else {
// parse FPGA and HOST MAC addresses
udp_args->fpga_mac_addr = ParseMACAddress(argv[1]);
udp_args->host_mac_addr = ParseMACAddress(argv[5]);
// parse ports
udp_args->fpga_udp_port = (unsigned int)atoi(argv[3]);
udp_args->host_udp_port = (unsigned int)atoi(argv[7]);
// get IP addresses and netmask
udp_args->fpga_ip_addr = argv[2];
udp_args->fpga_netmask = argv[4];
udp_args->host_ip_addr = argv[6];
if (argc > 8) {
if (atoi(argv[8]) > 0) {
num_matrix_copies = atoi(argv[8]);
}
}
if (argc > 9) {
in_dir = argv[9];
}
if (argc > 10) {
out_dir = argv[10];
}
return true;
}
#else
if (argc > 1) {
if (atoi(argv[1]) > 0) {
num_matrix_copies = atoi(argv[1]);
}
}
if (argc > 2) {
in_dir = argv[2];
}
if (argc > 3) {
out_dir = argv[3];
}
return true;
#endif
}
void PrintUsage() {
#if defined(REAL_IO_PIPES)
std::cout << "USAGE: ./mvdr_beamforming.fpga fpga_mac_adr fpga_ip_addr "
<< "fpga_udp_port fpga_netmask host_mac_adr host_ip_addr "
<< "host_udp_port [num_matrices] [in directory] [out directory]\n";
std::cout << "EXAMPLE: ./mvdr_beamforming.fpga 64:4C:36:00:2F:20 "
<< "192.168.0.11 34543 255.255.255.0 94:40:C9:71:8D:10 "
<< " 192.168.0.10 34543 1024 ../data .\n";
#else
std::cout << "USAGE: ./mvdr_beamforming.fpga "
<< "[num_matrices] [in directory] [out directory]\n";
std::cout << "EXAMPLE: ./mvdr_beamforming.fpga 1024 ../data .\n";
#endif
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/ParallelCopyArray.hpp | #ifndef __PARALLEL_COPY_ARRAY_HPP__
#define __PARALLEL_COPY_ARRAY_HPP__
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
// ParallelCopyArray
// Defines a struct with a single element data, which is an array of type T.
// Defies the copy and = operators to do an unrolled (parallel) assignment of
// all elements in the array. Defines the [] operator so the struct can be
// accessed like a normal array.
template <typename T, // type of elements in the array
std::size_t k_size // number of T elements in the array
>
struct ParallelCopyArray {
// constructor
ParallelCopyArray() {}
// copy constructor - do a parallel copy
ParallelCopyArray(const ParallelCopyArray& source) {
fpga_tools::UnrolledLoop<k_size>([&](auto k) { data[k] = source[k]; });
}
// assignment operator - do a parallel copy
ParallelCopyArray& operator=(const ParallelCopyArray& source) {
fpga_tools::UnrolledLoop<k_size>([&](auto k) { data[k] = source[k]; });
return *this;
}
// data accessors
T& operator[](std::size_t index) { return data[index]; }
const T& operator[](std::size_t index) const { return data[index]; }
private:
T data[k_size];
}; // end of struct ParallelCopyArray
#endif // ifndef __PARALLEL_COPY_ARRAY_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/src/Beamformer.hpp | #ifndef __BEAMFORMER_HPP__
#define __BEAMFORMER_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
// utility classes
#include "ParallelCopyArray.hpp"
#include "tuple.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "unrolled_loop.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "mvdr_complex.hpp"
using namespace sycl;
// SubmitBeamformerKernel
// Accept data from an antenna array as a vector of complex numbers (Xrx) and
// apply a group of weight vectors to each sample.
template <typename BeamformerKernelName, // Name to use for the Kernel
size_t k_num_weight_vectors, // number of weight vectors to apply to
// each incoming sample vector
size_t k_num_elements, // number of elements in each vector
size_t k_num_complex_per_xrx_read, // Number of complex numbers
// (contained in NTuple) per read
// from the XrxVectorsInPipe.
size_t k_unroll_factor, // Factor by which to unroll the
// calculation loop, so k_unroll_factor
// operations will be performed in
// parallel on each clock.
typename XrxVectorsInPipe, // Receive the Xrx vectors
// Receive a NTuple containing
// k_num_complex_per_xrx_read complex
// floats per read
typename WeightVectorsInPipe, // Weight vectors
// Accept one complex float per read.
typename DataOutPipe // For each Xrx input vector, send an
// output for each of the Weight vectors.
// Send one complex float per write.
>
event SubmitBeamformerKernel(
queue& q,
short num_xrx_per_weights // Number of xrx vectors to process with
// each set of Weight vectors.
) {
// Template parameter checking
static_assert(k_num_weight_vectors > 0,
"k_num_weight_vectors must be greater than 0");
static_assert(std::numeric_limits<char>::max() > k_num_weight_vectors,
"k_num_weight_vectors must fit in a char");
static_assert(k_num_elements >= 0, "k_num_elements must be greater than 0");
static_assert(std::numeric_limits<short>::max() > k_num_elements,
"k_num_elements must fit in a short");
static_assert(k_num_complex_per_xrx_read > 0,
"k_num_complex_per_xrx_read must be greater than 0");
static_assert(
k_num_elements % k_num_complex_per_xrx_read == 0,
"k_num_elements must be evenly divisible by k_num_complex_per_xrx_read");
static_assert(k_num_elements % k_unroll_factor == 0,
"k_num_elements must be evenly divisible by k_unroll_factor");
static_assert(k_unroll_factor >= k_num_complex_per_xrx_read,
"k_unroll_factor must be >= k_num_complex_per_xrx_read");
static_assert(
k_unroll_factor % k_num_complex_per_xrx_read == 0,
"k_unroll_factor must be evenly divisible by k_num_complex_per_xrx_read");
// data coming from the Xrx pipe
using XrxPipeType = fpga_tools::NTuple<ComplexType, k_num_complex_per_xrx_read>;
// this type represents the number of samples to be processed in parallel
using CalcType = ParallelCopyArray<ComplexType, k_unroll_factor>;
constexpr short kNumCalcTypePerVector = k_num_elements / k_unroll_factor;
auto e = q.submit([&](handler& h) {
h.single_task<BeamformerKernelName>([=] {
while (1) {
CalcType weight_vectors[k_num_weight_vectors][kNumCalcTypePerVector];
// load the weight vectors to be used with the next set of Xrx vectors
for (unsigned char vector_num = 0;
vector_num < (unsigned char)k_num_weight_vectors; vector_num++) {
// weights are loaded in reverse order
for (short i = kNumCalcTypePerVector - 1; i >= 0; i--) {
for (short j = (short)k_unroll_factor - 1; j >= 0; j--) {
weight_vectors[vector_num][i][j] = WeightVectorsInPipe::read();
}
}
}
for (int xrx_vector_num = 0; xrx_vector_num < num_xrx_per_weights;
xrx_vector_num++) {
// force adequate private copies of this variable to not limit
// throughput, extra private copies are cheap here
// NO-FORMAT comments are for clang-format
[[intel::private_copies(8)]] // NO-FORMAT: Attribute
CalcType xrx_vector[kNumCalcTypePerVector];
XrxPipeType segment;
// load a new Xrx vector
constexpr short kReadsPerCalcType =
k_unroll_factor / k_num_complex_per_xrx_read;
for (short i = 0; i < kNumCalcTypePerVector * kReadsPerCalcType;
i++) {
segment = XrxVectorsInPipe::read();
short index = i / kReadsPerCalcType;
fpga_tools::UnrolledLoop<k_num_complex_per_xrx_read>([&](auto k) {
short subindex =
(i % kReadsPerCalcType) * (short)k_num_complex_per_xrx_read +
k;
xrx_vector[index][subindex] = segment.template get<k>();
});
}
[[intel::fpga_register]] // NO-FORMAT: Attribute
CalcType accum_vector;
// don't let throughput be limited by result, adding extra private
// copies is cheap as long as we stay below the depth of an M20K
[[intel::private_copies(8)]] // NO-FORMAT: Attribute
ComplexType result[k_num_weight_vectors];
// calculate an output vector for each weight vector
for (unsigned char vector_num = 0;
vector_num < (unsigned char)k_num_weight_vectors; vector_num++) {
// zero the accumulators
fpga_tools::UnrolledLoop<k_unroll_factor>([&](auto i) { accum_vector[i] = 0; });
// calculate the sum of products of the weight and xrx vectors
// unroll by a factor of k_unroll_factor (so perform k_unroll_factor
// operations in parallel)
for (short i = 0; i < (kNumCalcTypePerVector); i++) {
fpga_tools::UnrolledLoop<k_unroll_factor>([&](auto j) {
accum_vector[j] +=
xrx_vector[i][j] * weight_vectors[vector_num][i][j].conj();
});
}
ComplexType accum_vector_sum = 0;
fpga_tools::UnrolledLoop<k_unroll_factor>(
[&](auto i) { accum_vector_sum += accum_vector[i]; });
result[vector_num] = accum_vector_sum;
} // end of for( vector_num... )
for (unsigned char vector_num = 0;
vector_num < (unsigned char)k_num_weight_vectors; vector_num++) {
// send the result out
DataOutPipe::write(result[vector_num]);
}
} // end of for( xrx_vector_num... )
} // end of while( 1 )
}); // end of h.single_task
}); // end of q.submit
return e;
} // end of SubmitBeamformerKernel()
#endif // ifndef __BEAMFORMER_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_elem_per_bank elements.
Repeat these operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Output matrix pipe
>
void MatrixReadFromDDRToPipe(
TT* matrix_ptr, // Input matrix pointer
int matrix_count, // Number of matrices to read from DDR
int repetitions // Number of times to write the same matrix to the pipe
) {
// We may perform an incomplete memory read if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = (rows % num_elem_per_bank) != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst reads of num_elem_per_bank elements required to read a
// full column
constexpr int kLoopIterPerColumn =
(rows / num_elem_per_bank) + kExtraIteration;
// Number of DDR burst reads of num_elem_per_bank to read all the matrices
constexpr int kLoopIter = kLoopIterPerColumn * columns;
// Size in bits of the loop iterator over kLoopIter iterations
constexpr int kLoopIterBitSize = fpga_tools::BitsForMaxValue<kLoopIter + 1>();
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> matrix_ptr_located(matrix_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* matrix_ptr_located(matrix_ptr);
#endif
// Repeatedly read matrix_count matrices from the DDR and send them to the
// pipe
for (int repetition = 0; repetition < repetitions; repetition++) {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
// Keep track of the current element index in the matrix
// Only useful in the case of kIncompleteBurst
int load_index = 0;
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kLoopIterBitSize, false> li = 0; li < kLoopIter; li++) {
bool last_burst_of_col;
if constexpr (kIncompleteBurst) {
// Check if we are reading the last DDR burst of the current column
last_burst_of_col =
(li % kLoopIterPerColumn) == kLoopIterPerColumn - 1;
}
fpga_tools::NTuple<TT, num_elem_per_bank> ddr_read;
// Perform the DDR burst read of num_elem_per_bank elements
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst) {
// Check if the current read index is beyond the end of the current
// matrix column
bool out_of_bounds =
last_burst_of_col &&
((k % num_elem_per_bank) > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR reads that are relevant (and don't access a
// memory address that may be beyond the matrix last address)
if (!out_of_bounds) {
ddr_read.template get<k>() =
matrix_ptr_located[matrix_index * kMatrixSize + load_index +
k];
}
} else {
ddr_read.template get<k>() =
matrix_ptr_located[matrix_index * kMatrixSize +
(int)(li)*num_elem_per_bank + k];
}
});
if constexpr (kIncompleteBurst) {
// Update the current element index in the input matrix according
// to the read size of the current iteration
load_index +=
last_burst_of_col ? rows % num_elem_per_bank : num_elem_per_bank;
}
MatrixPipe::write(ddr_read);
} // end of li
} // end of matrix_index
} // end of repetition
}
/*
Read vector_count vectors of type TT from a pipe, num_elem_per_bank by
num_elem_per_bank and write them to DDR by bursts of num_elem_per_bank
elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the vector
int vector_size, // Number of elements in the vector
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename VectorPipe // Input vector
>
void VectorReadFromPipeToDDR(
TT* vector_ptr, // Output vector pointer
int vector_count, // Number of vectors to write to the DDR
int repetitions // Number of times to read the same vector from the pipe
) {
// The number of elements in the vector may not be a multiple of
// num_elem_per_bank so we may have to do an extra incomplete write to DDR.
constexpr bool kIncompleteBurst = vector_size % num_elem_per_bank != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
constexpr int kLoopIter = (vector_size / num_elem_per_bank) + kExtraIteration;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> vector_ptr_located(vector_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* vector_ptr_located(vector_ptr);
#endif
// Repeat vector_count complete I vector pipe reads
// for as many repetitions as needed
for (int rep_idx = 0; rep_idx < repetitions; rep_idx++) {
for (int vector_idx = 0; vector_idx < vector_count; vector_idx++) {
for (int li = 0; li < kLoopIter; li++) {
TT bank[num_elem_per_bank];
for (int k = 0; k < num_elem_per_bank; k++) {
if (((li * num_elem_per_bank) + k) < vector_size) {
bank[k] = VectorPipe::read();
}
}
// Copy the I vector result to DDR
if constexpr (kIncompleteBurst) {
// Write a burst of num_elem_per_bank elements to DDR
#pragma unroll
for (int k = 0; k < num_elem_per_bank; k++) {
if (((li * num_elem_per_bank) + k) < vector_size) {
vector_ptr_located[(vector_idx * vector_size) +
(li * num_elem_per_bank) + k] = bank[k];
}
}
} else {
// Write a burst of num_elem_per_bank elements to DDR
#pragma unroll
for (int k = 0; k < num_elem_per_bank; k++) {
vector_ptr_located[(vector_idx * vector_size) +
(li * num_elem_per_bank) + k] = bank[k];
}
}
} // end of li
} // end of vector_idx
} // end of rep_idx
}
#endif /* __MEMORY_TRANSFERS_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion.hpp | #ifndef __CHOLESKY_INVERSION_HPP__
#define __CHOLESKY_INVERSION_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "streaming_cholesky.hpp"
#include "streaming_cholesky_inversion.hpp"
#include "tuple.hpp"
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class CholeskyDDRToLocalMem;
class DecompositionKernel;
class InversionKernel;
class CholeskyLocalMemToDDR;
class APipe;
class LPipe;
class IPipe;
/*
Implementation of the Cholesky-based inversion using streaming kernels
Can be configured by datatype, matrix size (must use square matrices), real
and complex.
*/
template <unsigned dimension, // Number of columns/rows in the input matrix
unsigned raw_latency_decomposition, // RAW latency for triangular
// loop optimization
unsigned raw_latency_inversion, // RAW latency for triangular loop
// optimization
bool is_complex, // Selects between ac_complex<T> and T datatype
typename T, // The datatype for the computation
typename TT = std::conditional_t<is_complex, ac_complex<T>, T>
// TT will be ac_complex<T> or T depending on is_complex
>
void CholeskyInversionImpl(
std::vector<TT> &a_matrix, // Input matrix A to invert
std::vector<TT> &i_matrix, // Output matrix I (inverse of A)
sycl::queue &q, // Device queue
int matrix_count, // Number of matrices to invert
int repetitions // Number of repetitions, for performance
// evaluation
) {
constexpr int kAMatrixSize = dimension * dimension;
constexpr int kIMatrixSize = dimension * (dimension + 1) / 2;
constexpr int kNumElementsPerDDRBurst = is_complex ? 4 : 8;
using PipeType = fpga_tools::NTuple<TT, kNumElementsPerDDRBurst>;
// Pipes to communicate the A and L matrices between kernels
using AMatrixPipe = sycl::ext::intel::pipe<APipe, PipeType, 3>;
using LMatrixPipe =
sycl::ext::intel::pipe<LPipe, TT, kNumElementsPerDDRBurst * 4>;
using IMatrixPipe =
sycl::ext::intel::pipe<IPipe, TT, kNumElementsPerDDRBurst * 4>;
// Allocate FPGA DDR memory.
#if defined (IS_BSP)
TT *a_device = sycl::malloc_device<TT>(kAMatrixSize * matrix_count, q);
TT *i_device = sycl::malloc_device<TT>(kIMatrixSize * matrix_count, q);
#else
// malloc_device are not supported when targetting an FPGA part/family
TT *a_device = sycl::malloc_shared<TT>(kAMatrixSize * matrix_count, q);
TT *i_device = sycl::malloc_shared<TT>(kIMatrixSize * matrix_count, q);
#endif
if ((a_device == nullptr) || (i_device == nullptr)) {
std::cerr << "Error when allocating FPGA DDR" << std::endl;
std::cerr << "The FPGA DDR may be full" << std::endl;
std::cerr << "Try reducing the matrix sizes/count" << std::endl;
return;
}
// Copy the matrices to decompose to the FPGA DDR
q.memcpy(a_device, a_matrix.data(), kAMatrixSize * matrix_count * sizeof(TT))
.wait();
// Launch a kernel that will repeatedly read the matrices from the FPGA DDR
// and write their content to the AMatrixPipe pipe.
auto ddr_read_event = q.single_task<CholeskyDDRToLocalMem>([=] {
MatrixReadFromDDRToPipe<TT, dimension, dimension, kNumElementsPerDDRBurst,
AMatrixPipe>(a_device, matrix_count, repetitions);
});
// Read the A matrix from the AMatrixPipe pipe and compute the Cholesky
// decomposition. Write the L output matrix to the LMatrixPipe pipe.
q.single_task<DecompositionKernel>(
fpga_linalg::StreamingCholesky<
T, is_complex, dimension, raw_latency_decomposition,
kNumElementsPerDDRBurst, AMatrixPipe, LMatrixPipe>());
// Read the L matrix from the LMatrixPipe pipe and compute the Cholesky-based
// inversion. Write the I output matrix to the IMatrixPipe pipe.
q.single_task<InversionKernel>(
fpga_linalg::StreamingCholeskyInversion<
T, is_complex, dimension, raw_latency_inversion,
kNumElementsPerDDRBurst, LMatrixPipe, IMatrixPipe>());
// Read the I matrix from the LMatrixPipe pipe and copy it to the FPGA DDR
auto ddr_write_event = q.single_task<CholeskyLocalMemToDDR>([=] {
VectorReadFromPipeToDDR<TT, kIMatrixSize, kNumElementsPerDDRBurst,
IMatrixPipe>(i_device, matrix_count, repetitions);
});
ddr_write_event.wait();
// Compute the total time the execution lasted
auto start_time = ddr_read_event.template get_profiling_info<
sycl::info::event_profiling::command_start>();
auto end_time = ddr_write_event.template get_profiling_info<
sycl::info::event_profiling::command_end>();
double diff = (end_time - start_time) / 1.0e9;
// Make sure we throw any asynchronous errors if they have occurred during
// the computation
q.throw_asynchronous();
std::cout << " Total duration: " << diff << " s" << std::endl;
std::cout << "Throughput: " << ((repetitions * matrix_count) / diff) * 1e-3
<< "k matrices/s" << std::endl;
// Copy the L matrices result from the FPGA DDR to the host memory
q.memcpy(i_matrix.data(), i_device, kIMatrixSize * matrix_count * sizeof(TT))
.wait();
// Clean allocated FPGA memory
free(a_device, q);
free(i_device, q);
}
#endif /* __CHOLESKY_INVERSION_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/src/cholesky_inversion_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <list>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
// included from ../../../../include
#include "cholesky_inversion.hpp"
// Use "#define DEBUG" to print debugging information such as matrices content
/*
COMPLEX, MATRIX_DIMENSION, FIXED_ITERATIONS_DECOMPOSITION and
FIXED_ITERATIONS_INVERSION are defined by the build system. Depending on the
value of COMPLEX, computes the real or complex Cholesky-based inversion. The
Cholesky decompostion provides the L matrix from A such that: A = LL*
Therefore we can compute inv(A) = inv(LL*)
= inv(L*) x inv(L)
= inv(L)* x inv(L)
Function arguments:
- a_matrix: The input matrix.
- i_matrix The inverse matrix. The function will overwrite this matrix.
- q: The device queue.
- matrix_count: Number of matrices to invert.
- repetitions: The number of repetitions of the computation to execute.
(for performance evaluation)
*/
template <typename T, bool is_complex>
void CholeskyInversion(std::vector<T> &a_matrix, std::vector<T> &i_matrix,
sycl::queue &q, int matrix_count, int repetitions) {
CholeskyInversionImpl<MATRIX_DIMENSION, FIXED_ITERATIONS_DECOMPOSITION,
FIXED_ITERATIONS_INVERSION, is_complex, float>(
a_matrix, i_matrix, q, matrix_count, repetitions);
}
/*
Returns true if both the real and complex parts of the given ac_complex
value are finite
*/
bool IsFinite(ac_complex<float> val) {
return std::isfinite(val.r()) && std::isfinite(val.i());
}
/*
Returns true if the given value is finite
*/
bool IsFinite(float val) { return std::isfinite(val); }
/*
Returns a random floating-point value between min and max
*/
float RandomValueInInterval(float min, float max) {
return min + static_cast<float>(rand()) /
(static_cast<float>(RAND_MAX) / (max - min));
}
/*
Generate the input matrices for the cholesky inversion
*/
template <int matrices_to_invert, int matrix_size, int columns, typename T>
void GenerateInputData(std::vector<T> &a_matrix) {
constexpr bool kComplex = COMPLEX != 0;
std::cout << "Generating " << matrices_to_invert << " random ";
if constexpr (kComplex) {
std::cout << "complex ";
} else {
std::cout << "real ";
}
std::cout << "matri" << (matrices_to_invert > 1 ? "ces" : "x") << " of size "
<< columns << "x" << columns << " " << std::endl;
constexpr size_t kRandomSeed = 1138;
// Generate the random (Hermitian and positive-definite) input matrices
srand(kRandomSeed);
// Max condition number
constexpr float kEpsilon = 0.5;
// Random min and max values for the random floating-point value
// generation
constexpr float kRandomMin = 0;
constexpr float kRandomMax = 1;
/*
Generate a random matrix with a given epsilon such that
cond(M, inf) <= (1+epsilon)/(1-epsilon)
This is helpful as having a condition number with infinite norm close to 1
improves the numerical stability of the matrix inversion.
Provided an epsilon value, this function populates the output vector with
a matrix in a row fashion.
Algorithm courtesy of Carl Christian Kjelgaard Mikkelsen ([email protected])
Once this matrix is generated, we need to alter it a little to make
it Hermitian
*/
for (int mat_idx = 0; mat_idx < matrices_to_invert; mat_idx++) {
int current_matrix = mat_idx * matrix_size;
// Generate a random matrix R with diagonal elements set to 0
// and measure the weights of the off diagonal entries
std::vector<T> r, weights, a_matrix_non_hermitian;
r.resize(columns * columns);
a_matrix_non_hermitian.resize(columns * columns);
weights.resize(columns);
for (int row = 0; row < columns; row++) {
weights[row] = {0};
for (int col = 0; col < columns; col++) {
if (col != row) {
int index = (row * columns) + col;
float random1 = RandomValueInInterval(kRandomMin, kRandomMax);
T elem;
#if COMPLEX == 1
float random1I = RandomValueInInterval(kRandomMin, kRandomMax);
elem = {random1, random1I};
r[index] = elem;
#else
elem = random1;
r[index] = elem;
#endif
weights[row] += elem;
}
}
// Construct the new diagonal element
weights[row] /= kEpsilon;
r[(row * columns) + row] = weights[row];
}
// Perform the diagonal scaling by solving:
// diag(diag(A))*output = A
for (int row = 0; row < columns; row++) {
for (int col = 0; col < columns; col++) {
int index = row * columns + col;
a_matrix_non_hermitian[index] = r[index] / r[(row * columns) + row];
}
}
// Make the matrix Hermitian
for (int row = 0; row < columns; row++) {
for (int col = 0; col < columns; col++) {
int index = row * columns + col;
a_matrix[current_matrix + index] =
(a_matrix_non_hermitian[index] +
a_matrix_non_hermitian[(col * columns) + row]) /
2;
#if COMPLEX == 1
if (row > col) {
a_matrix[current_matrix + index] =
a_matrix[current_matrix + index].conj();
}
#endif
}
}
#ifdef DEBUG
std::cout << "A MATRIX " << mat_idx << std::endl;
for (size_t row = 0; row < columns; row++) {
for (size_t col = 0; col < columns; col++) {
std::cout << a_matrix[current_matrix + (col * columns) + row] << " ";
} // end of col
std::cout << std::endl;
} // end of row
#endif
} // end of mat_idx
}
/*
Check results for correctness
*/
template <int inverted_matrices, int matrix_size, int invert_matrix_size,
int rows, int columns, typename T>
int CheckResults(std::vector<T> &a_matrix, std::vector<T> &i_matrix) {
// For output post-processing (op)
T i_matrix_op[rows][columns];
// Floating-point error threshold value at which we decide that the design
// computed an incorrect value
constexpr float kErrorThreshold = 1e-4;
// Check I matrices
std::cout << "Verifying results..." << std::endl;
for (int mat_idx = 0; mat_idx < inverted_matrices; mat_idx++) {
// Keep track of I element index
size_t i_idx = 0;
// Read the I matrix from the output vector to the i_matrix_op matrix
for (size_t j = 0; j < columns; j++) {
for (size_t i = 0; i < rows; i++) {
if (i < j) {
#if COMPLEX == 0
i_matrix_op[i][j] = i_matrix_op[j][i];
#else
i_matrix_op[i][j] = i_matrix_op[j][i].conj();
#endif
} else {
i_matrix_op[i][j] = i_matrix[(mat_idx * invert_matrix_size) + i_idx];
i_idx++;
}
}
}
#ifdef DEBUG
std::cout << "I MATRIX" << std::endl;
for (size_t i = 0; i < rows; i++) {
for (size_t j = 0; j < columns; j++) {
std::cout << i_matrix_op[i][j] << " ";
}
std::cout << std::endl;
}
#endif
// Count the number of errors found for this matrix
size_t error_count = 0;
bool error = false;
// Current A matrix start index
int current_matrix = mat_idx * matrix_size;
for (size_t i = 0; i < rows; i++) {
for (size_t j = 0; j < columns; j++) {
// Compute I x A at index i,j
T i_times_a_ij{0};
// Compute A x I at index i,j
T a_times_i_ij{0};
for (size_t k = 0; k < columns; k++) {
#if COMPLEX == 0
i_times_a_ij +=
i_matrix_op[i][k] * a_matrix[current_matrix + (k * columns) + j];
a_times_i_ij +=
a_matrix[current_matrix + (i * columns) + k] * i_matrix_op[k][j];
#else
i_times_a_ij += i_matrix_op[i][k] *
a_matrix[current_matrix + (k * columns) + j].conj();
a_times_i_ij += a_matrix[current_matrix + (i * columns) + k] *
i_matrix_op[k][j].conj();
#endif
}
// Verify that all the results are OK:
// I x A = Id at index i,j
bool i_times_a_is_id = false;
// A x I = Id at index i,j
bool a_times_i_is_id = false;
// I is finite at index i,j
bool i_is_finite = false;
#if COMPLEX == 0
if (i == j) {
// Diagonal elements
i_times_a_is_id = (abs(i_times_a_ij - 1)) < kErrorThreshold;
a_times_i_is_id = (abs(a_times_i_ij - 1)) < kErrorThreshold;
} else {
// Non diagonal elements
i_times_a_is_id = abs(i_times_a_ij) < kErrorThreshold;
a_times_i_is_id = abs(a_times_i_ij) < kErrorThreshold;
}
#else
if (i == j) {
// Diagonal elements
i_times_a_is_id = (abs(i_times_a_ij.r() - 1)) < kErrorThreshold;
a_times_i_is_id = (abs(a_times_i_ij.r() - 1)) < kErrorThreshold;
} else {
// Non diagonal elements
i_times_a_is_id = abs(i_times_a_ij.r()) < kErrorThreshold;
a_times_i_is_id = abs(a_times_i_ij.r()) < kErrorThreshold;
}
bool imag_is_zero_i_times_a = abs(i_times_a_ij.i()) < kErrorThreshold;
i_times_a_is_id &= imag_is_zero_i_times_a;
bool imag_is_zero_a_times_i = abs(a_times_i_ij.i()) < kErrorThreshold;
a_times_i_is_id &= imag_is_zero_a_times_i;
#endif
i_is_finite = IsFinite(i_matrix_op[i][j]);
// If any of the checks failed
if (!i_times_a_is_id || !a_times_i_is_id || !i_is_finite) {
// Increase the error count for this matrix
error_count++;
// Continue counting the errors even if we are going to
// produce an error
if (error) {
continue;
}
std::cerr << "Error in matrix " << mat_idx << std::endl;
if (!i_times_a_is_id) {
std::cerr << "Error: I*A at [" << i << "][" << j
<< "] = " << i_times_a_ij << std::endl;
}
if (!a_times_i_is_id) {
std::cerr << "Error: A*I at [" << i << "][" << j
<< "] = " << a_times_i_ij << std::endl;
}
if (!i_is_finite) {
std::cerr << "I[" << i << "][" << j << "] = " << i_matrix_op[i][j]
<< " is not finite" << std::endl;
}
error = true;
}
} // end of j
} // end of i
if (error_count > 0) {
std::cerr << std::endl << "FAILED" << std::endl;
std::cerr << std::endl
<< "!!!!!!!!!!!!!! " << error_count << " errors" << std::endl;
return 1;
}
} // end of mat_idx
// All passed
std::cout << std::endl << "PASSED" << std::endl;
return 0;
}
int main(int argc, char *argv[]) {
constexpr size_t kRows = MATRIX_DIMENSION;
constexpr size_t kColumns = MATRIX_DIMENSION;
constexpr size_t kAMatrixSize = kRows * kColumns;
constexpr size_t kIMatrixSize = kColumns * (kColumns + 1) / 2;
constexpr bool kComplex = COMPLEX != 0;
#if defined(FPGA_SIMULATOR)
constexpr size_t kMatricesToInvert = 1;
#else
constexpr size_t kMatricesToInvert = 8;
#endif
// Get the number of times we want to repeat the inversion from the command
// line.
#if defined(FPGA_EMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 16;
#elif defined(FPGA_SIMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 1;
#else
int repetitions = argc > 1 ? atoi(argv[1]) : 819200;
#endif
if (repetitions < 1) {
std::cerr << "Number of repetitions given is lower than 1." << std::endl;
std::cerr << "The inversion must occur at least 1 time." << std::endl;
std::cerr << "Increase the number of repetitions (e.g. 16)." << std::endl;
return 1;
}
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::queue q = sycl::queue(
selector, fpga_tools::exception_handler,
sycl::property_list{sycl::property::queue::enable_profiling()});
sycl::device device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>().c_str()
<< std::endl;
// Select a type for this compile depending on the value of COMPLEX
using T = std::conditional_t<kComplex, ac_complex<float>, float>;
// Create vectors to hold all the input and output matrices
std::vector<T> a_matrix;
std::vector<T> i_matrix;
std::vector<T> r, weights;
a_matrix.resize(kAMatrixSize * kMatricesToInvert);
i_matrix.resize(kIMatrixSize * kMatricesToInvert);
// Generate the input matrices to be inverted
GenerateInputData<kMatricesToInvert, kAMatrixSize, kColumns>(a_matrix);
std::cout << "Computing the Cholesky-based inversion of "
<< kMatricesToInvert << " matri"
<< (kMatricesToInvert > 1 ? "ces " : "x ") << repetitions
<< " times" << std::endl;
// Invert the matrices
CholeskyInversion<T, kComplex>(a_matrix, i_matrix, q, kMatricesToInvert,
repetitions);
// Check the returned matrices for correctness
return CheckResults<kMatricesToInvert, kAMatrixSize, kIMatrixSize, kRows,
kColumns>(a_matrix, i_matrix);
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::cerr << " If you are targeting FPGA hardware, "
"ensure that your system is connected to an FPGA board that "
"is set up correctly"
<< std::endl;
std::cerr << " If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR"
<< std::endl;
std::terminate();
} catch (std::bad_alloc const &e) {
std::cerr << "Caught a memory allocation exception on the host: "
<< e.what() << std::endl;
std::cerr << " You can reduce the memory requirement by reducing the "
"number of matrices generated. Specify a smaller number when "
"running the executable."
<< std::endl;
std::cerr << " In this run, more than "
<< ((kAMatrixSize + kIMatrixSize) * 2 * kMatricesToInvert *
sizeof(float)) /
pow(2, 30)
<< " GBs of memory was requested for the inversion of a "
<< "matrix of size " << kRows << " x " << kColumns << std::endl;
std::terminate();
}
} // end of main
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/main.cpp | #include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <algorithm>
#include <array>
#include <chrono>
#include <limits>
#include <numeric>
#include <sstream>
#include <string>
#include <type_traits>
#include <utility>
#include <vector>
#include "anr.hpp"
#include "anr_params.hpp"
#include "constants.hpp"
#include "data_bundle.hpp"
#include "dma_kernels.hpp"
#include "exception_handler.hpp"
using namespace sycl;
using namespace std::chrono;
////////////////////////////////////////////////////////////////////////////////
// Forward declare functions used in this file by main()
void ParseFiles(std::string data_dir, std::vector<PixelT>& in_pixels,
std::vector<PixelT>& ref_pixels, int& cols, int& rows,
ANRParams& params);
void WriteOutputFile(std::string data_dir, std::vector<PixelT>& pixels,
int cols, int rows);
double RunANR(queue& q, PixelT* in_ptr, PixelT* out_ptr, int cols, int rows,
int frames, ANRParams params, float* sig_i_lut_data_ptr);
bool Validate(PixelT* val, PixelT* ref, int rows, int cols,
double psnr_thresh = kPSNRDefaultThreshold);
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char* argv[]) {
/////////////////////////////////////////////////////////////
// reading and validating the command line arguments
std::string data_dir = "../test_data";
bool passed = true;
#if defined(FPGA_EMULATOR)
int runs = 2;
int frames = 2;
#elif defined(FPGA_SIMULATOR)
int runs = 2;
int frames = 1;
#else
int runs = 2;
int frames = 8;
#endif
// get the input data directory
if (argc > 1) {
data_dir = std::string(argv[1]);
}
// get the number of runs as the second command line argument
if (argc > 2) {
runs = atoi(argv[2]);
}
// get the number of frames as the third command line argument
if (argc > 3) {
frames = atoi(argv[3]);
}
// enforce at least two runs
if (runs < 2) {
std::cerr << "ERROR: 'runs' must be 2 or more\n";
std::terminate();
}
// enforce at least one batch
if (frames < 1) {
std::cerr << "ERROR: 'frames' must be atleast 1\n";
std::terminate();
}
/////////////////////////////////////////////////////////////
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// create the device queue
queue q(selector, fpga_tools::exception_handler);
// make sure the device supports USM device allocations
auto device = q.get_device();
#if defined(IS_BSP)
if (!device.has(aspect::usm_device_allocations)) {
std::cerr << "ERROR: The selected device does not support USM device"
<< " allocations\n";
std::terminate();
}
#endif
std::cout << "Running on device: "
<< device.get_info<info::device::name>().c_str()
<< std::endl;
// parse the input files
int cols, rows, pixel_count;
ANRParams params;
std::vector<PixelT> in_pixels, ref_pixels;
ParseFiles(data_dir, in_pixels, ref_pixels, cols, rows, params);
pixel_count = cols * rows;
// create the output pixels (initialize to all 0s)
std::vector<PixelT> out_pixels(in_pixels.size(), 0);
#if defined (IS_BSP)
// allocate memory on the device for the input and output
PixelT *in, *out;
if ((in = malloc_device<PixelT>(pixel_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'in'\n";
std::terminate();
}
if ((out = malloc_device<PixelT>(pixel_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'out'\n";
std::terminate();
}
#else
// allocate memory on the host for the input and output
PixelT *in, *out;
if ((in = malloc_shared<PixelT>(pixel_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'in'\n";
std::terminate();
}
if ((out = malloc_shared<PixelT>(pixel_count, q)) == nullptr) {
std::cerr << "ERROR: could not allocate space for 'out'\n";
std::terminate();
}
#endif
// copy the input data to the device memory and wait for the copy to finish
q.memcpy(in, in_pixels.data(), pixel_count * sizeof(PixelT)).wait();
// allocate space for the intensity sigma LUT
float* sig_i_lut_data_ptr = IntensitySigmaLUT::Allocate(q);
// create the intensity sigma LUT data locally on the host
IntensitySigmaLUT sig_i_lut_host(params);
// copy the intensity sigma LUT to the device
sig_i_lut_host.CopyData(q, sig_i_lut_data_ptr).wait();
//////////////////////////////////////////////////////////////////////////////
// track timing information in ms
std::vector<double> time(runs);
// print out some info
std::cout << "Runs: " << runs << "\n";
std::cout << "Columns: " << cols << "\n";
std::cout << "Rows: " << rows << "\n";
std::cout << "Frames: " << frames << "\n";
std::cout << "Filter Size: " << kFilterSize << "\n";
std::cout << "Pixels Per Cycle: " << kPixelsPerCycle << "\n";
std::cout << "Maximum Columns: " << kMaxCols << "\n";
std::cout << "\n";
try {
// run the design multiple times to increase the accuracy of the timing
for (int i = 0; i < runs; i++) {
// run ANR
time[i] =
RunANR(q, in, out, cols, rows, frames, params, sig_i_lut_data_ptr);
// Copy the output back from the device
q.memcpy(out_pixels.data(), out, pixel_count * sizeof(PixelT)).wait();
// validate the output on the last iteration
if (i == (runs-1)) {
passed &= Validate(out_pixels.data(), ref_pixels.data(), rows, cols);
} else {
passed &= true;
}
}
} catch (exception const& e) {
std::cout << "Caught a synchronous SYCL exception: " << e.what() << "\n";
std::terminate();
}
// free the allocated device memory
sycl::free(in, q);
sycl::free(out, q);
sycl::free(sig_i_lut_data_ptr, q);
// write the output files if device memory was used (output is meaningless
// otherwise)
WriteOutputFile(data_dir, out_pixels, cols, rows);
// print the performance results
if (passed) {
// NOTE: when run in emulation, these results do not accurately represent
// the performance of the kernels in actual FPGA hardware
double avg_time_ms =
std::accumulate(time.begin() + 1, time.end(), 0.0) / (runs - 1);
size_t input_count_mega = pixel_count * frames * sizeof(PixelT) * 1e-6;
std::cout << "Execution time: " << avg_time_ms << " ms\n";
std::cout << "Throughput: " << (input_count_mega / (avg_time_ms * 1e-3))
<< " MB/s\n";
std::cout << "PASSED\n";
return 0;
} else {
std::cout << "FAILED\n";
return 1;
}
}
// declare kernel and pipe names globally to reduce name mangling
class ANRInPipeID;
class ANROutPipeID;
class InputKernelID;
class OutputKernelID;
//
// Run the ANR algorithm on the device
//
double RunANR(queue& q, PixelT* in_ptr, PixelT* out_ptr, int cols, int rows,
int frames, ANRParams params, float* sig_i_lut_data_ptr) {
// the input and output pipe for the sorter
using PipeType = DataBundle<PixelT, kPixelsPerCycle>;
using ANRInPipe = sycl::ext::intel::pipe<ANRInPipeID, PipeType>;
using ANROutPipe = sycl::ext::intel::pipe<ANROutPipeID, PipeType>;
// launch the input and output kernels that read from and write to the device
auto input_kernel_event =
SubmitInputDMA<InputKernelID, PixelT, ANRInPipe, kPixelsPerCycle>(q,
in_ptr, rows, cols, frames);
auto output_kernel_event =
SubmitOutputDMA<OutputKernelID, PixelT, ANROutPipe, kPixelsPerCycle>(q,
out_ptr, rows, cols, frames);
// launch all ANR kernels
std::vector<std::vector<event>> anr_kernel_events(frames);
for (int i = 0; i < frames; i++) {
anr_kernel_events[i] =
SubmitANRKernels<IndexT, ANRInPipe, ANROutPipe, kFilterSize,
kPixelsPerCycle, kMaxCols>(q, cols, rows, params,
sig_i_lut_data_ptr);
}
// wait for the input and output kernels to finish
auto start = high_resolution_clock::now();
input_kernel_event.wait();
output_kernel_event.wait();
auto end = high_resolution_clock::now();
// wait for the ANR kernels to finish
for (auto& one_event_set : anr_kernel_events) {
for (auto& e : one_event_set) {
e.wait();
}
}
// return the duration in milliseconds, excluding memory transfers
duration<double, std::milli> diff = end - start;
return diff.count();
}
//
// Helper to parse pixel data files
//
void ParseDataFile(std::string filename, std::vector<PixelT>& pixels, int& cols,
int& rows) {
// create the file stream to parse
std::ifstream ifs(filename);
// make sure we opened the file
if (!ifs.is_open() || ifs.fail()) {
std::cerr << "ERROR: failed to open " << filename << " for reading\n";
std::terminate();
}
// get the header and data
std::string header_str, data_str;
if (!std::getline(ifs, header_str)) {
std::cerr << "ERROR: failed to get header line from " << filename << "\n";
std::terminate();
}
if (!std::getline(ifs, data_str)) {
std::cerr << "ERROR: failed to get data line from " << filename << "\n";
std::terminate();
}
// first two elements are the image dimensions
std::stringstream header_ss(header_str);
header_ss >> rows >> cols;
// expecting to parse cols*rows pixels from the 'data_str' line
pixels.resize(cols * rows);
// parse all of the pixels
std::stringstream data_ss(data_str);
for (int i = 0; i < cols * rows; i++) {
// parse using 64 bit integer
TmpT x;
// parse the pixel value
if (!(data_ss >> x)) {
std::cerr << "ERROR: ran out of pixels when parsing " << filename << "\n";
std::terminate();
}
// check for parsing failure
if (data_ss.fail()) {
std::cerr << "ERROR: failed to parse pixel in " << filename << "\n";
std::terminate();
}
// check if the parsed value fits in the pixel type
if (x > static_cast<TmpT>(std::numeric_limits<PixelT>::max())) {
std::cerr << "ERROR: value (" << x
<< ") is too big to store in pixel type 'T'\n";
std::terminate();
}
if (x < static_cast<TmpT>(std::numeric_limits<PixelT>::min())) {
std::cerr << "ERROR: value (" << x
<< ") is too small to store in pixel type 'T'\n";
std::terminate();
}
// set the value
pixels[i] = static_cast<PixelT>(x);
}
}
//
// Function that parses all of the input files
//
void ParseFiles(std::string data_dir, std::vector<PixelT>& in_pixels,
std::vector<PixelT>& ref_pixels, int& cols, int& rows,
ANRParams& params) {
// parse the pixel data files
int noisy_w, noisy_h;
#if FPGA_SIMULATOR
ParseDataFile(data_dir + "/small_input_noisy.data", in_pixels, noisy_w, noisy_h);
#else
ParseDataFile(data_dir + "/input_noisy.data", in_pixels, noisy_w, noisy_h);
#endif
int ref_w, ref_h;
#if FPGA_SIMULATOR
ParseDataFile(data_dir + "/small_output_ref.data", ref_pixels, ref_w, ref_h);
#else
ParseDataFile(data_dir + "/output_ref.data", ref_pixels, ref_w, ref_h);
#endif
// ensure the dimensions match
if (noisy_w != ref_w) {
std::cerr << "noisy input and reference widths do not match " << noisy_w
<< " != " << ref_w << "\n";
std::terminate();
}
if (noisy_h != ref_h) {
std::cerr << "noisy input and reference heights do not match " << noisy_h
<< " != " << ref_h << "\n";
std::terminate();
}
// set the width and height
cols = ref_w;
rows = ref_h;
// parse the ANR config parameters file
params = ANRParams::FromFile(data_dir + "/param_config.data");
// ensure the parsed filter size matches the compile time constant
if (params.filter_size != kFilterSize) {
std::cerr << "ERROR: the filter size parsed from " << data_dir
<< "/param_config.data (" << params.filter_size
<< ") does not match the compile time constant filter size "
<< "(kFilterSize = " << kFilterSize << ")\n";
std::terminate();
}
// ensure the parsed number of pixel bits matches the compile time constant
if (params.pixel_bits != kPixelBits) {
std::cerr << "ERROR: the number of bits per pixel parsed from " << data_dir
<< "/param_config.data (" << params.pixel_bits
<< ") does not match the compile time constant pixel size "
<< "kPixelBits = " << kPixelBits << ")\n";
std::terminate();
}
}
//
// Function to write the output to a file
//
void WriteOutputFile(std::string data_dir, std::vector<PixelT>& pixels,
int cols, int rows) {
std::string filename = data_dir + "/output.data";
std::ofstream ofs(filename);
// make sure we opened the file fine
if (!ofs.is_open() || ofs.fail()) {
std::cerr << "ERROR: failed to open " << filename << " for writing\n";
std::terminate();
}
// write the image dimensions
ofs << rows << " " << cols << "\n";
// write the pixels
for (auto& p : pixels) {
ofs << static_cast<TmpT>(p) << " ";
}
}
//
// Validate the output pixels using Peak signal-to-noise ratio (PSNR)
// https://en.wikipedia.org/wiki/Peak_signal-to-noise_ratio
//
// Also check the max individual pixel difference.
//
bool Validate(PixelT* val, PixelT* ref, int rows, int cols,
double psnr_thresh) {
// get the maximum value of the pixel
constexpr double max_i = std::numeric_limits<PixelT>::max();
// total number of pixels to check
int count = rows * cols;
// compute the MSE by summing the squared differences
// also find the maximum difference between the output pixel and the reference
double mse = 0.0;
for (int i = 0; i < count; i++) {
// cast to a double here because we are subtracting
auto diff = double(val[i]) - double(ref[i]);
mse += diff * diff;
}
mse /= count;
// compute the PSNR
double psnr = (20 * std::log10(max_i)) - (10 * std::log10(mse));
// check PSNR and maximum pixel difference
bool passed = true;
if (psnr <= psnr_thresh) {
std::cerr << "ERROR: Peak signal-to-noise ratio (PSNR) is too low: " << psnr
<< "\n";
passed = false;
}
return passed;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/intensity_sigma_lut.hpp | #ifndef __INTENSITY_SIGMA_LUT_HPP__
#define __INTENSITY_SIGMA_LUT_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <type_traits>
#include "anr_params.hpp"
#include "constants.hpp"
//
// A LUT for computing the intensity sigma value of a pixel
//
class IntensitySigmaLUT {
public:
// default constructor
IntensitySigmaLUT() {}
#if defined (IS_BSP)
// construct from a device_ptr (for constructing from device memory)
IntensitySigmaLUT(device_ptr<float> ptr) {
// use a pipelined LSU to load from device memory since we don't
// care about the performance of the copy.
using PipelinedLSU = ext::intel::lsu<>;
for (int i = 0; i < lut_depth; i++) {
data_[i] = PipelinedLSU::load(ptr + i);
}
}
#else
// construct from a regular pointer
IntensitySigmaLUT(float* ptr) {
for (int i = 0; i < lut_depth; i++) {
data_[i] = ptr[i];
}
}
#endif
// construct from the ANR parameters (actually builds the LUT)
IntensitySigmaLUT(ANRParams params) {
for (int i = 0; i < lut_depth; i++) {
float sig_i = sycl::sqrt(params.k * float(i) + params.sig_shot_2) *
params.sig_i_coeff;
float sig_i_inv = 1.0f / sig_i;
float sig_i_inv_squared = sig_i_inv * sig_i_inv;
float sig_i_inv_squared_2 = 0.5f * sig_i_inv_squared;
data_[i] = sig_i_inv_squared_2; // storing 0.5 * (1/sig_i)^2
}
}
// helper static method to allocate enough memory to hold the LUT
static float* Allocate(sycl::queue& q) {
#if defined (IS_BSP)
float* ptr = sycl::malloc_device<float>(lut_depth, q);
#else
float* ptr = sycl::malloc_shared<float>(lut_depth, q);
#endif
if (ptr == nullptr) {
std::cerr << "ERROR: could not allocate space for 'ptr'\n";
std::terminate();
}
return ptr;
}
// helper method to copy the data to the device
sycl::event CopyData(sycl::queue& q, float* ptr) {
return q.memcpy(ptr, data_, lut_depth * sizeof(float));
}
const float& operator[](int i) const { return data_[i]; }
private:
static constexpr int lut_depth = std::numeric_limits<PixelT>::max() -
std::numeric_limits<PixelT>::min() + 1;
float data_[lut_depth];
};
#endif /* __INTENSITY_SIGMA_LUT_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/shift_reg.hpp | #ifndef __SHIFT_REG_HPP__
#define __SHIFT_REG_HPP__
#include "data_bundle.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "unrolled_loop.hpp"
namespace fpga_tools {
//
// A class to represent a shift register of depth 'depth' holding elements
// of type 'T'.
//
template <typename T, int depth>
class ShiftReg {
T registers_[depth];
public:
// DO NOT Create a constructor for this; the compiler does not
// handle it well.
// empty default constructor since you should fill a shift-register by
// priming it, and if `T` is a struct, we might get a looping constructor.
ShiftReg() {}
// For a shift register with N columns, the first piece of data is inserted in
// index [N-1], and is read out of index [0].
//
// ```
// i=0 1 2
// ┌───┬───┬───┐
// out ◄─ │ r ◄─e ◄─g ◄─ input
// └───┴───┴───┘
// ```
void Shift(T &in) {
UnrolledLoop<0, (depth - 1)>([&](auto i) {
registers_[i] = registers_[i + 1];
});
registers_[depth - 1] = in;
}
template <int shift_amt>
void shiftSingleVal(T &in) {
UnrolledLoop<0, (depth - shift_amt)>([&](auto i) {
registers_[i] = registers_[i + shift_amt];
});
UnrolledLoop<(depth - shift_amt), depth>([&](auto i) {
registers_[i] = in;
});
}
template <int shift_amt>
void ShiftMultiVals(DataBundle<T, shift_amt> &in) {
UnrolledLoop<0, (depth - shift_amt)>([&](auto i) {
registers_[i] = registers_[i + shift_amt];
});
UnrolledLoop<0, shift_amt>([&](auto i) {
registers_[(depth - shift_amt) + i] = in[i];
});
}
// use an accessor like this to force static accesses
template <int idx>
T Get() {
static_assert(idx < depth);
return registers_[idx];
}
T &operator[](int i) { return registers_[i]; }
const T &operator[](int i) const { return registers_[i]; }
};
//
// A class to represent a 2D shift register with 'rows' rows of depth 'depth'
// holding elements of type 'T'.
//
template <typename T, int rows, int depth>
class ShiftReg2d {
ShiftReg<T, depth> registers_[rows];
public:
// DO NOT Create constructor for this; the compiler does not handle it well.
// empty default constructor since you should fill a shift-register by
// priming it, and if `T` is a struct, we might get a looping constructor.
ShiftReg2d() {}
// For a shift register with M rows and N columns, the first piece of data is
// inserted in index [M-1][N-1], and is read out of index [0][0].
// j=0 1 2
// +----+----+----+
// out <- | <- | <- | <- | i=0
// +----+----+----+
// | ^- | <- | <- | i=1
// +----+----+----+
// | ^- | <- | <- | <- input i=2
// +----+----+----+
void Shift(T &in) {
UnrolledLoop<0, (rows - 1)>([&](auto i) {
registers_[i].Shift(registers_[i + 1][0]);
});
registers_[(rows - 1)].Shift(in);
}
// For a shift register with M rows and N columns, the first column of data
// is inserted in column [N-1], and is read out of column [0].
// j=0 1 2
// ┌───┬───┬───┐
// ◄─ r ◄ e ◄ g ◄─
// ├───┼───┼───┤
// ◄─ r ◄ e ◄ g ◄─
// ├───┼───┼───┤
// ◄─ r ◄ e ◄ g ◄─
// └───┴───┴───┘
void ShiftCol(T in[rows]) {
UnrolledLoop<0, rows>([&](auto i) {
registers_[i].Shift(in[i]);
});
}
template <int shift_amt>
void ShiftCols(DataBundle<T, shift_amt> in[rows]) {
UnrolledLoop<0, rows>([&](auto i) {
registers_[i].template ShiftMultiVals<shift_amt>(in[i]);
});
}
// use an accessor like this to force static accesses
template <int row, int col>
T Get() {
static_assert(row < rows);
static_assert(col < depth);
return registers_[row][col];
}
ShiftReg<T, depth> &operator[](int i) { return registers_[i]; }
const ShiftReg<T, depth> &operator[](int i) const { return registers_[i]; }
};
} // namespace fpga_tools
#endif /* __SHIFT_REG_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr.hpp | #ifndef __ANR_HPP__
#define __ANR_HPP__
//
// This file contains a bulk of the functionality for the ANR design on the
// on the device. It contains the logic to submit the various kernels for the
// ANR pipeline.
//
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <limits>
#include <type_traits>
#include <utility>
#include <vector>
#include "anr_params.hpp"
#include "column_stencil.hpp"
#include "constants.hpp"
#include "data_bundle.hpp"
#include "intensity_sigma_lut.hpp"
#include "qfp.hpp"
#include "qfp_exp_lut.hpp"
#include "qfp_inv_lut.hpp"
#include "row_stencil.hpp"
#include "shift_reg.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
using namespace sycl;
// declare the kernel and pipe names globally to reduce name mangling
class IntraPipeID;
class VerticalKernelID;
class HorizontalKernelID;
//
// A struct to carry the new (i.e., current) pixel, the original pixel, and the
// intensity sigma from the vertical to horizontal kernel
//
struct DataForwardStruct {
DataForwardStruct() {}
DataForwardStruct(PixelT pixel_n) : pixel_n(pixel_n) {}
DataForwardStruct(PixelT pixel_n, PixelT pixel_o, float sig_i)
: pixel_n(pixel_n), pixel_o(pixel_o), sig_i(sig_i) {}
PixelT pixel_n; // the new pixel
PixelT pixel_o; // the original pixel
float sig_i; // the intensity sigma value for the pixel
};
//
// Build the power values for a 1D gaussian filter. The 'actual' gaussian values
// are exp(-x) where 'x' are the 'powers' in the 'filter'.
//
template <int size>
auto BuildGaussianPowers1D(float sigma) {
fpga_tools::ShiftReg<float, size> filter;
for (int x = -size / 2; x <= size / 2; x++) {
float x_over_sig = x / sigma;
filter[x + size / 2] = 0.5 * x_over_sig * x_over_sig; // 0.5*(x/sigma)^2
}
return filter;
}
//
// Given a float value, convert it to an unsigned pixel value by saturating it
// in the extremes (i.e., min/max).
//
PixelT Saturate(float pixel_float) {
constexpr unsigned kMaxPixelVal = std::numeric_limits<PixelT>::max();
constexpr unsigned kMinPixelVal = std::numeric_limits<PixelT>::min();
constexpr unsigned kFloatSignOffset = ((sizeof(float) * 8) - 1);
// get the bits of the float for the negative check
unsigned int pixel_float_bits = reinterpret_cast<unsigned int&>(pixel_float);
PixelT pixel;
if (pixel_float >= kMaxPixelVal) {
pixel = kMaxPixelVal;
} else if ((pixel_float_bits >> kFloatSignOffset) & 0x1) { // pixel_float < 0
pixel = kMinPixelVal;
} else {
pixel = pixel_float;
}
return pixel;
}
//
// Computes the 1D bilateral filter. The spatial filter is passed as an
// argument and the intensity filter is computed based on the pixel window
// ('buffer') and the ANR parameters ('params'). Together, the spatial and
// intensity filters create the bilateral filter.
//
template <int filter_size, int filter_size_eff = (filter_size + 1) / 2>
inline float
BilateralFilter1D(fpga_tools::ShiftReg<PixelT, filter_size>& buffer,
fpga_tools::ShiftReg<float, filter_size_eff>& spatial_power,
ANRParams params, float sig_i_inv_squared_x_half,
const ExpLUT& exp_lut,
const InvLUT& inv_lut) {
// We need to hold all pixels bits, but need the type to be signed for the
// BilateralFilter1D since it subtracts the values. So add one bit to it and
// make it a signed ac_int.
using SignedPixelT = ac_int<kPixelBits + 1, true>;
// the middle pixel index
constexpr int mid_idx = filter_size / 2;
// static asserts
static_assert(filter_size > 1);
// convert unsigned pixels to signed
fpga_tools::ShiftReg<SignedPixelT, filter_size> buffer_signed;
fpga_tools::UnrolledLoop<filter_size>([&](auto i) {
buffer_signed[i] = static_cast<SignedPixelT>(buffer[i]);
});
// build the bilateral filter
fpga_tools::ShiftReg<float, filter_size_eff> bilateral_filter;
float filter_sum = 0.0;
fpga_tools::UnrolledLoop<filter_size_eff>([&](auto i) {
// get the absolute value of the pixel differences
float intensity_diff_squared;
if constexpr (mid_idx == (i * 2)) {
// special case for middle pixel, the absolute difference will be 0
// and therefore the absolute value difference squared will also be 0
intensity_diff_squared = 0.0f;
} else {
// compute differences squared
const SignedPixelT intensity_diff =
buffer_signed[mid_idx] - buffer_signed[i * 2];
intensity_diff_squared = intensity_diff * intensity_diff;
}
// compute the filter value as e^-(intensity_component + spatial_component)
// Use a LUT to compute the exp(-x) value
float filter_val;
if constexpr (mid_idx == (i * 2)) {
// (buffer[mid_idx] - buffer[i * 2]) = 0 in this case, so the intensity
// component is 0. For similar reasons, the spatial component is also 0
// and therefore filter_val is e^(-0) = 1.
filter_val = 1.0f;
} else {
// intensity_component = 1/2 * (intensity_diff/sig_i)^2
// = 1/2*(1/sig_i)^2 *(intensity_diff)^2
// We have precomputed 1/2*(1/sig_i)^2 in the host
const float intensity_component =
intensity_diff_squared * sig_i_inv_squared_x_half;
// spatial component is a regular Gaussian that was precomputed using
// the 'BuildGaussianPowers1D' function
const float spatial_component = spatial_power[i];
// the bilateral filter power value, where the actual bilateral filter
// value is e^-(exp_power)
const float exp_power = intensity_component + spatial_component;
// now that we have the exponential power value ('exp_power'), use the
// exponential LUT ('ExpLUT') to lookup the result of exp(-exp_power).
// NOTE: when creating the exponential LUT, we stored the values of
// exp(-x) = 1/exp(x). This avoids negating the value of 'exp_power'.
const auto exp_lut_idx = ExpLUT::QFP::FromFP32(exp_power);
filter_val = ExpLUT::QFP::ToFP32(exp_lut[exp_lut_idx]);
}
// compute the bilateral filter value
bilateral_filter[i] = filter_val;
filter_sum += filter_val;
});
// Convolve the 1D bilateral filter with the pixel window
float filtered_pixel = 0.0;
fpga_tools::UnrolledLoop<filter_size_eff>([&](auto i) {
filtered_pixel += (float(buffer[i * 2]) * bilateral_filter[i]);
});
// Normalize the pixel value by the bilateral filter sum. Use the inverse
// LUT to compute 1/filter_sum. This saves area by using a 32-bit
// floating-point multiplication, instead of division.
// Computes: filtered_pixel /= filter_sum
const auto inv_lut_idx = InvLUT::QFP::FromFP32(filter_sum);
filtered_pixel *= InvLUT::QFP::ToFP32(inv_lut[inv_lut_idx]);
return filtered_pixel;
}
//
// Functor for the column stencil callback.
// This performs the 1D vertical bilateral filter. It also computes the
// intensity sigma value (sig_i) and bundles it with the original and partially
// filtered pixel to be forwarded to the horizontal kernel.
//
template <int filter_size, int filter_size_eff = (filter_size + 1) / 2>
struct VerticalFunctor {
auto operator()(int row, int col,
fpga_tools::ShiftReg<PixelT, filter_size> buffer,
fpga_tools::ShiftReg<float, filter_size_eff> spatial_power,
ANRParams params, const ExpLUT& exp_lut,
const InvLUT& inv_lut, IntensitySigmaLUT& sig_i_lut) const {
// static asserts to validate template arguments
static_assert(filter_size > 1);
// get the middle index and compute the intensity sigma from it
constexpr int mid_idx = filter_size / 2;
const PixelT middle_pixel = buffer[mid_idx];
const auto sig_i_inv_squared_x_half = sig_i_lut[middle_pixel];
// perform the vertical 1D bilateral filter
auto output_pixel_float = BilateralFilter1D<filter_size>(
buffer, spatial_power, params, sig_i_inv_squared_x_half,
exp_lut, inv_lut);
// saturate the output pixel
PixelT output_pixel = Saturate(output_pixel_float);
// return the result, which is the output pixel, as well as the intensity
// sigma value (sig_i) and the original pixel, which are forwarded to the
// horizontal kernel for the horizontal 1D bilateral calculation and alpha
// blending, respectively.
return DataForwardStruct(output_pixel, middle_pixel,
sig_i_inv_squared_x_half);
}
};
//
// Functor for the row stencil callback.
// This performs the 1D horizontal bilateral filter. It uses the intensity
// sigma (sig_i) that was forwarded from the vertical kernel.
//
template <int filter_size, int filter_size_eff = (filter_size + 1) / 2>
struct HorizontalFunctor {
auto operator()(int row, int col,
fpga_tools::ShiftReg<DataForwardStruct, filter_size> buffer,
fpga_tools::ShiftReg<float, filter_size_eff> spatial_power,
ANRParams params, ANRParams::AlphaFixedT alpha_fixed,
ANRParams::AlphaFixedT one_minus_alpha_fixed,
const ExpLUT& exp_lut, const InvLUT& inv_lut) const {
// static asserts
static_assert(filter_size > 1);
// grab the intensity sigma for the middle pixel (forwarded from the
// vertical kernel)
constexpr int mid_idx = filter_size / 2;
const float sig_i_inv_squared_x_half = buffer[mid_idx].sig_i;
// grab just the pixel data, pixel_n is the 'new' pixel forwarded from the
// vertical kernel (i.e., the partially filtered one)
fpga_tools::ShiftReg<PixelT, filter_size> buffer_pixels;
fpga_tools::UnrolledLoop<filter_size>([&](auto i) {
buffer_pixels[i] = buffer[i].pixel_n;
});
// perform the horizontal 1D bilateral filter
auto output_pixel_float = BilateralFilter1D<filter_size>(
buffer_pixels, spatial_power, params, sig_i_inv_squared_x_half,
exp_lut, inv_lut);
// saturate the output pixel
PixelT output_pixel = Saturate(output_pixel_float);
// fixed-point alpha blending with the original pixel
const PixelT original_pixel(buffer[mid_idx].pixel_o);
auto output_pixel_alpha =
(alpha_fixed * output_pixel) + (one_minus_alpha_fixed * original_pixel);
auto output_pixel_tmp = output_pixel_alpha.to_ac_int();
// return the result casted back to a pixel
return PixelT(output_pixel_tmp);
}
};
//
// Submit all of the ANR kernels (vertical and horizontal)
//
template <typename IndexT, typename InPipe, typename OutPipe,
unsigned filter_size, unsigned pixels_per_cycle,
unsigned max_cols>
std::vector<event> SubmitANRKernels(queue& q, int cols, int rows,
ANRParams params,
float* sig_i_lut_data_ptr) {
// the internal pipe between the vertical and horizontal kernels
using IntraPipeT =
fpga_tools::DataBundle<DataForwardStruct, pixels_per_cycle>;
using IntraPipe = ext::intel::pipe<IntraPipeID, IntraPipeT>;
// static asserts to validate template arguments
static_assert(filter_size > 1);
static_assert(max_cols > 1);
static_assert(pixels_per_cycle > 0);
static_assert(fpga_tools::IsPow2(pixels_per_cycle));
static_assert(max_cols > pixels_per_cycle);
static_assert(std::is_integral_v<IndexT>);
// validate the function arguments
int padded_cols = PadColumns<IndexT, filter_size>(cols);
if (cols > max_cols) {
std::cerr << "ERROR: cols exceeds the maximum (max_cols) "
<< "(" << cols << " > " << max_cols << ")\n";
std::terminate();
} else if (cols <= 0) {
std::cerr << "ERROR: cols must be strictly positive\n";
std::terminate();
} else if (rows <= 0) {
std::cerr << "ERROR: rows must be strictly positive\n";
std::terminate();
} else if ((cols % pixels_per_cycle) != 0) {
std::cerr << "ERROR: the number of columns (" << cols
<< ") must be a multiple of the number of pixels per cycle ("
<< pixels_per_cycle << ")\n";
std::terminate();
} else if ((padded_cols % pixels_per_cycle) != 0) {
std::cerr << "ERROR: the number of padded columns (" << padded_cols
<< ") must be a multiple of the number of pixels per cycle ("
<< pixels_per_cycle << ")\n";
std::terminate();
} else if (padded_cols >= std::numeric_limits<IndexT>::max()) {
// padded_cols >= cols, so just check padded_cols
std::cerr << "ERROR: the number of padded columns (" << padded_cols
<< ") is too big to be counted to by the IndexType (max="
<< std::numeric_limits<IndexT>::max() << ")\n";
std::terminate();
} else if (rows >= std::numeric_limits<IndexT>::max()) {
std::cerr << "ERROR: the number of rows (" << rows
<< ") is too big to be counted to by the IndexType (max="
<< std::numeric_limits<IndexT>::max() << ")\n";
std::terminate();
}
// cast the rows and columns to the index type and use these
// variables inside the kernel to avoid the device dealing with conversions
const IndexT cols_k(cols);
const IndexT rows_k(rows);
// create the spatial filter for the stencil operation
constexpr int filter_size_eff = (filter_size + 1) / 2; // ceil(filter_size/2)
auto spatial_power = BuildGaussianPowers1D<filter_size_eff>(params.sig_s);
// Functors or lambdas can be used for the vertical and horizontal kernels.
auto vertical_func = VerticalFunctor<filter_size>();
auto horizontal_func = HorizontalFunctor<filter_size>();
// submit the vertical kernel using a column stencil
auto vertical_kernel = q.single_task<VerticalKernelID>([=] {
// copy host side intensity sigma LUT to the device
IntensitySigmaLUT sig_i_lut(sig_i_lut_data_ptr);
// build the constexpr exp() and inverse LUT ROMs
constexpr ExpLUT exp_lut;
constexpr InvLUT inv_lut;
// Start the column stencil.
// It will callback to 'vertical_func' with all of the additional
// arguments listed after 'vertical_func' (i.e., spatial_power,
// params, ...)
ColumnStencil<PixelT, DataForwardStruct, IndexT, InPipe,
IntraPipe, filter_size, max_cols, pixels_per_cycle>(rows_k,
cols_k, PixelT(0), vertical_func, spatial_power, params,
std::cref(exp_lut), std::cref(inv_lut),
std::ref(sig_i_lut));
});
// submit the horizontal kernel using a row stencil
auto horizontal_kernel = q.single_task<HorizontalKernelID>([=] {
// build the constexpr exp() and inverse LUT ROMs
constexpr ExpLUT exp_lut;
constexpr InvLUT inv_lut;
#ifdef IP_MODE
ANRParams::AlphaFixedT alpha_fixed(0.75);
ANRParams::AlphaFixedT one_minus_alpha_fixed(0.25);
#else
// convert the alpha and (1-alpha) values to fixed-point
ANRParams::AlphaFixedT alpha_fixed(params.alpha);
ANRParams::AlphaFixedT one_minus_alpha_fixed(params.one_minus_alpha);
#endif
// Start the row stencil.
// It will callback to 'horizontal_func' with the additional all of the
// additional arguments listed after 'horizontal_func' (i.e.,
// spatial_power, params, alpha_fixed, ...)
RowStencil<DataForwardStruct, PixelT, IndexT, IntraPipe, OutPipe,
filter_size, pixels_per_cycle>(rows_k, cols_k,
DataForwardStruct(0), horizontal_func, spatial_power,
params, alpha_fixed, one_minus_alpha_fixed, std::cref(exp_lut),
std::cref(inv_lut));
});
return {vertical_kernel, horizontal_kernel};
}
#endif /* __ANR_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/row_stencil.hpp | #ifndef __ROW_STENCIL_HPP__
#define __ROW_STENCIL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <limits>
#include "data_bundle.hpp"
#include "shift_reg.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
using namespace sycl;
//
// helper function to pad the number of columns based on the filter size
//
template <typename IndexT, unsigned filter_size>
IndexT PadColumns(IndexT cols) {
constexpr int kPaddingPixels = filter_size / 2;
return cols + 2 * kPaddingPixels;
}
//
// Generic 1D row (i.e. horizontal) stencil.
//
// TEMPLATE PARAMETERS
// InType: The input pixel type. This is read in by the row stencil
// through a SYCL pipe. The pipe should be hold
// 'parallel_cols' elements of this type using the
// 'DataBundle' type (DataBundle<InType, parallel_cols>).
// OutType: The output pixel type. The same logic as the InType above.
// The data written to the output type is
// DataBundle<OutType, parallel_cols>
// IndexT: The datatype used for indexing. This type should have
// enough bits to count up to the number or rows and columns.
// InPipe: The input pipe to stream in 'parallel_cols' 'InT' values.
// OutPipe: The output pipe to stream out 'parallel_cols' 'OutT'
// values.
// filter_size: The filter size (i.e., the number of pixels to convolve).
// parallel_cols: The number of columns to compute in parallel.
// StencilFunction: The stencil callback functor, provided by the user, which
// is called for every pixel to perform the actual
// convolution. The function definition should be as follows:
//
// OutT MyStencilFunction(int, int, ShiftReg<InT, filter_size>,
// FunctionArgTypes...)
//
// The user can provide extra arguments to the callback by
// using the FunctionArgTypes parameter pack.
// FunctionArgTypes: The user-provided type parameter pack of the arguments to
// pass to the callback function.
//
//
// FUNCTION ARGUMENTS
// rows: The number of rows in the image.
// cols: The number of columns in the image.
// computed by the IP is rows*cols.
// zero_val: The 'zero' value for the stencil. This is used to pad
// the columns of the image.
// func: The user-defined functor. This is a callback that is called
// to perform the 1D convolution.
// stencil_args...: The parameter pack of arguments to be passed to the
// user-defined callback functor.
//
template <typename InType, typename OutType, typename IndexT, typename InPipe,
typename OutPipe, unsigned filter_size, unsigned parallel_cols,
typename StencilFunction, typename... FunctionArgTypes>
void RowStencil(IndexT rows, IndexT cols, const InType zero_val,
StencilFunction func, FunctionArgTypes... stencil_args) {
// types coming into and out of the kernel from pipes, respectively
using InPipeT = fpga_tools::DataBundle<InType, parallel_cols>;
using OutPipeT = fpga_tools::DataBundle<OutType, parallel_cols>;
// number of pixels to pad to the columns with
constexpr int kPaddingPixels = filter_size / 2;
// the size of the shift register to hold the window
constexpr int kShiftRegSize = filter_size + parallel_cols - 1;
constexpr IndexT kColThreshLow = kPaddingPixels;
// static asserts to validate template arguments
static_assert(filter_size > 1);
static_assert(parallel_cols > 0);
static_assert(fpga_tools::IsPow2(parallel_cols));
static_assert(std::is_integral_v<IndexT>);
static_assert(std::is_invocable_r_v<OutType, StencilFunction, int, int,
fpga_tools::ShiftReg<InType, filter_size>,
FunctionArgTypes...>);
// constants
const IndexT col_thresh_high = cols + kPaddingPixels;
const IndexT padded_cols = PadColumns<IndexT, filter_size>(cols);
const IndexT col_loop_bound = padded_cols / parallel_cols;
// the shift register
[[intel::fpga_register]]
fpga_tools::ShiftReg<InType, kShiftRegSize> shifty_pixels;
// initialize the contents of the shift register
#pragma unroll
for (int i = 0; i < kShiftRegSize; i++) {
shifty_pixels[i] = zero_val;
}
// the main processing loop for the image
[[intel::initiation_interval(1)]]
for (IndexT row = 0; row < rows; row++) {
[[intel::initiation_interval(1)]]
for (IndexT col_loop = 0; col_loop < col_loop_bound; col_loop++) {
IndexT col = col_loop * parallel_cols;
// read from the input pipe if there are still pixels to read
InPipeT new_pixels(zero_val);
if (col < cols) {
new_pixels = InPipe::read();
}
// shift in the input pixels
shifty_pixels.ShiftMultiVals(new_pixels);
// Perform the convolution on the 1D window
OutPipeT out_data(OutType(0));
fpga_tools::UnrolledLoop<0, parallel_cols>([&](auto stencil_idx) {
const int col_local = col + stencil_idx;
fpga_tools::ShiftReg<InType, filter_size> shifty_pixels_copy;
// first, make an offsetted copy of the shift register
fpga_tools::UnrolledLoop<0, filter_size>([&](auto x) {
shifty_pixels_copy[x] = shifty_pixels[x + stencil_idx];
});
// call the user's callback function for the operator
out_data[stencil_idx] = func(row, (col_local - kColThreshLow),
shifty_pixels_copy, stencil_args...);
});
// write the output data if it is in range (i.e., it is a real pixel
// and not part of the padding)
if ((col >= kColThreshLow) && (col < col_thresh_high)) {
OutPipe::write(out_data);
}
}
}
}
#endif /* __ROW_STENCIL_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/data_bundle.hpp | #ifndef __DATA_BUNDLE_HPP__
#define __DATA_BUNDLE_HPP__
namespace fpga_tools {
//
// A class used to group together 'bundle_size' elements of type 'T' into a
// struct. Similar to an array but with the copyer constructor and operator=()
// overridden to avoid expensive copys.
//
template <typename T, int bundle_size>
struct DataBundle {
T data_[bundle_size];
DataBundle() {}
DataBundle(const T op) {
#pragma unroll
for (int idx = 0; idx < bundle_size; idx++) {
data_[idx] = op;
}
}
DataBundle(const DataBundle &op) {
#pragma unroll
for (int idx = 0; idx < bundle_size; idx++) {
data_[idx] = op.data_[idx];
}
}
DataBundle &operator=(const DataBundle &op) {
#pragma unroll
for (int idx = 0; idx < bundle_size; idx++) {
data_[idx] = op.data_[idx];
}
return *this;
}
bool operator==(const DataBundle &rhs) {
bool is_equal = true;
#pragma unroll
for (int b = 0; b < bundle_size; b++) {
is_equal &= (data_[b] == rhs.data_[b]);
}
return is_equal;
}
// get a specific value in the bundle
T &operator[](int i) { return data_[i]; }
// get a raw pointer to underlying data
T *Data() { return &data_[0]; }
// For a shift register with N columns, the first piece of data is inserted in
// index [N-1], and is read out of index [0].
//
// ```
// i=0 1 2
// ┌───┬───┬───┐
// out ◄─ │ r ◄─e ◄─g ◄─ input
// └───┴───┴───┘
// ```
void Shift(T &in) {
#pragma unroll
for (int i = 0; i < (bundle_size - 1); i++) {
data_[i] = data_[i + 1];
}
data_[bundle_size - 1] = in;
}
template <int shift_amt>
void ShiftSingleVal(T &in) {
#pragma unroll
for (int i = 0; i < (bundle_size - shift_amt); i++) {
data_[i] = data_[i + shift_amt];
}
#pragma unroll
for (int i = 0; i < (shift_amt); i++) {
data_[(bundle_size - shift_amt) + i] = in;
}
}
template <int shift_amt, int bundle_sz = shift_amt>
void ShiftMultiVals(DataBundle<T, bundle_sz> &in) {
#pragma unroll
for (int i = 0; i < (bundle_size - shift_amt); i++) {
data_[i] = data_[i + shift_amt];
}
#pragma unroll
for (int i = 0; i < (shift_amt); i++) {
data_[(bundle_size - shift_amt) + i] = in[i];
}
}
};
} // namespace fpga_tools
#endif /* __DATA_BUNDLE_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/qfp.hpp | #ifndef __QFP_HPP__
#define __QFP_HPP__
#include <array>
#include <limits>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
//
// A static class that is used to convert to/from 32-bit floating point
// and quantized floating point (QFP) format. Note that, when converting from
// FP32 to QFP, we truncate the mantissa, instead of rounding. This reduces
// the area required for the conversion at the expense of decreased accuracy.
//
template <unsigned qfp_total_bits, unsigned qfp_exponent_bits, bool is_signed>
struct QFP {
QFP(const QFP&) = delete;
QFP& operator=(const QFP&) = delete;
// determine if the QFP can fit into a unsigned char or unsigned short (if
// not, default to an unsigned int)
static constexpr bool fits_in_uchar =
qfp_total_bits <= sizeof(unsigned char)*8;
static constexpr bool fits_in_ushort =
qfp_total_bits <= sizeof(unsigned short)*8;
using qfp_type =
std::conditional_t<fits_in_uchar, unsigned char,
std::conditional_t<fits_in_ushort, unsigned short, unsigned>>;
// 32-bit floating point bits based on
// https://en.wikipedia.org/wiki/Single-precision_floating-point_format
static constexpr unsigned kFP32SignBits = 1;
static constexpr unsigned kFP32ExponentBits = 8;
static constexpr unsigned kFP32MantissaBits = 23;
static constexpr unsigned kFP32TotalBits =
kFP32SignBits + kFP32ExponentBits + kFP32MantissaBits;
static constexpr int kFP32ExponentOffset =
(1 << (kFP32ExponentBits-1)) - 1;
static constexpr unsigned kFP32ExponentMask = (1 << kFP32ExponentBits) - 1;
static constexpr unsigned kFP32MantissaMask = (1 << kFP32MantissaBits) - 1;
// A union for accesing the mantissa, exponent, and sign bits
typedef union {
float f;
struct {
unsigned mantissa : kFP32MantissaBits;
unsigned exponent : kFP32ExponentBits;
unsigned sign : kFP32SignBits;
} parts;
} FloatCast;
// the number of mantissa bits for the QFP
static constexpr unsigned qfp_mantissa_bits =
qfp_total_bits - qfp_exponent_bits - is_signed;
// masks for the exponent and mantissa of the QFP
static constexpr unsigned qfp_mask = (1 << qfp_total_bits) - 1;
static constexpr unsigned qfp_exponent_mask = (1 << qfp_exponent_bits) - 1;
static constexpr unsigned qfp_mantissa_mask = (1 << qfp_mantissa_bits) - 1;
static constexpr int qfp_exponent_offset =
(1 << (qfp_exponent_bits - 1)) - 1;
// the difference in bits between the QFP and the 32-bit float
static constexpr unsigned mantissa_bit_diff =
kFP32MantissaBits - qfp_mantissa_bits;
// static asserts
static_assert(kFP32TotalBits == (sizeof(float) * 8));
static_assert(qfp_mantissa_bits <= kFP32MantissaBits);
static_assert(qfp_exponent_bits > 0);
static_assert(qfp_mantissa_bits > 0);
static_assert(qfp_total_bits > qfp_exponent_bits);
//
// convert from a 32-bit float to a QFP
//
static qfp_type FromFP32(float f) {
// use the float cast to get the parts of the FP32
FloatCast f_casted = {.f = f};
int fp32_sign = f_casted.parts.sign;
ac_int<kFP32ExponentBits + 1, true> fp32_exponent =
f_casted.parts.exponent;
ac_int<kFP32MantissaBits, false> fp32_mantissa = f_casted.parts.mantissa;
// get the most significant qfp_mantissa_bits from the float's mantissa
// NOTE: we are doing truncation here without rounding, which will further
// reduce accuracy but require less area.
auto qfp_mantissa =
(fp32_mantissa >> mantissa_bit_diff) & qfp_mantissa_mask;
// compute the QFP exponent. Subtract the FP32 offset (127) from the FP32
// exponent and add back the QFP exponent offset.
auto qfp_exponent =
fp32_exponent - kFP32ExponentOffset + qfp_exponent_offset;
// get the sign bit
int qfp_sign = fp32_sign;
// build the output ac_int
if constexpr (is_signed) {
return qfp_type((qfp_sign << (qfp_exponent_bits + qfp_mantissa_bits)) |
(qfp_exponent << qfp_mantissa_bits) | (qfp_mantissa)) &
qfp_mask;
} else {
return qfp_type((qfp_exponent << qfp_mantissa_bits) | (qfp_mantissa)) &
qfp_mask;
}
}
//
// CONSTEXPR
// convert from a 32-bit float to a QFP
//
static constexpr qfp_type FromFP32CE(float f) {
// get the sign, exponent, and mantissa from the float
int fp32_sign = (f < 0) ? 1 : 0;
int fp32_exponent =
fpga_tools::FP32ExtractExponent(f) + kFP32ExponentOffset;
int fp32_mantissa = fpga_tools::FP32ExtractMantissa(f);
// get the most significant qfp_mantissa_bits from the float's mantissa
// NOTE: we are doing truncation here, not rounding.
int qfp_mantissa =
(fp32_mantissa >> mantissa_bit_diff) & qfp_mantissa_mask;
// compute the QFP exponent. Subtract the FP32 offset (127) from the FP32
// exponent and add back the QFP exponent offset.
const int qfp_exponent_tmp =
(fp32_exponent == 0) ? 0 :
(int(fp32_exponent) - kFP32ExponentOffset + qfp_exponent_offset);
int qfp_exponent = (qfp_exponent_tmp < 0) ? 0 : qfp_exponent_tmp;
// get the sign bit
int qfp_sign = fp32_sign;
// build the output ac_int
if constexpr (is_signed) {
return qfp_type((qfp_sign << (qfp_exponent_bits + qfp_mantissa_bits)) |
(qfp_exponent << qfp_mantissa_bits) | (qfp_mantissa)) &
qfp_mask;
} else {
return qfp_type((qfp_exponent << qfp_mantissa_bits) | (qfp_mantissa)) &
qfp_mask;
}
}
//
// convert a QFP to a 32-bit float
//
static float ToFP32(qfp_type i) {
int sign_bit = 0;
if constexpr (!is_signed) {
sign_bit = (i >> (qfp_exponent_bits + qfp_mantissa_bits)) & 0x1;
}
ac_int<kFP32ExponentBits + 1, true> fp32_exponent_tmp =
(i >> qfp_mantissa_bits) & qfp_exponent_mask;
auto fp32_exponent =
fp32_exponent_tmp - qfp_exponent_offset + kFP32ExponentOffset;
ac_int<kFP32MantissaBits, true> fp32_mantissa =
(i & qfp_mantissa_mask) << mantissa_bit_diff;
FloatCast f_casted;
f_casted.parts.sign = sign_bit;
f_casted.parts.exponent = fp32_exponent;
f_casted.parts.mantissa = fp32_mantissa;
return f_casted.f;
}
//
// CONSTEXPR
// convert a QFP to a 32-bit float
//
static constexpr float ToFP32CE(qfp_type i) {
int sign_bit = 0;
if constexpr (!is_signed) {
sign_bit = (i >> (qfp_exponent_bits + qfp_mantissa_bits)) & 0x1;
}
int fp32_exponent_tmp =
int((i >> qfp_mantissa_bits) & qfp_exponent_mask);
int fp32_exponent =
fp32_exponent_tmp - qfp_exponent_offset + kFP32ExponentOffset;
int fp32_mantissa = (i & qfp_mantissa_mask) << mantissa_bit_diff;
int offset_exponent =
(fp32_exponent == 0) ? 0 : (fp32_exponent - kFP32ExponentOffset);
// https://en.wikipedia.org/wiki/Single-precision_floating-point_format
//compute the mantissa sum
float mantissa_sum = (fp32_exponent == 0) ? 0.0 : 1.0;
for (int i = 1; i <= kFP32MantissaBits; i++) {
mantissa_sum +=
((fp32_mantissa >> (kFP32MantissaBits-i)) & 0x1)
* fpga_tools::Pow(2, -i);
}
if (sign_bit == 0)
return fpga_tools::Pow(2, offset_exponent) * mantissa_sum;
else
return -1.0f * fpga_tools::Pow(2, offset_exponent) * mantissa_sum;
}
private:
QFP();
};
#endif /* _QFP_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/constants.hpp | #ifndef __CONSTANTS_HPP__
#define __CONSTANTS_HPP__
#include <sycl/ext/intel/ac_types/ac_int.hpp>
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
// The size of the filter can be changed at the command line
#ifndef FILTER_SIZE
#define FILTER_SIZE 9
#endif
constexpr unsigned kFilterSize = FILTER_SIZE;
static_assert(kFilterSize > 1);
// The number of pixels per cycle
#ifndef PIXELS_PER_CYCLE
#define PIXELS_PER_CYCLE 1
#endif
constexpr unsigned kPixelsPerCycle = PIXELS_PER_CYCLE;
static_assert(kPixelsPerCycle > 0);
static_assert(fpga_tools::IsPow2(kPixelsPerCycle) > 0);
// The maximum number of columns in the image
#ifndef MAX_COLS
#define MAX_COLS 1920 // HD
//#define MAX_COLS 3840 // 4K
//#define MAX_COLS 2048
#endif
constexpr unsigned kMaxCols = MAX_COLS;
static_assert(kMaxCols > 0);
static_assert(kMaxCols > kPixelsPerCycle);
// The maximum number of rows in the image
#ifndef MAX_ROWS
#define MAX_ROWS MAX_COLS
#endif
constexpr unsigned kMaxRows = MAX_ROWS;
static_assert(kMaxRows > 0);
// pick the indexing variable size based on kMaxCols and kMaxRows
constexpr unsigned kSmallIndexTBits =
fpga_tools::Max(fpga_tools::CeilLog2(kMaxCols),
fpga_tools::CeilLog2(kMaxRows));
using SmallIndexT = ac_int<kSmallIndexTBits, false>;
// add max() function to std::numeric_limits for IndexT
namespace std {
template<> class numeric_limits<SmallIndexT> {
public:
static constexpr int max() { return (1 << kSmallIndexTBits) - 1; };
static constexpr int min() { return 0; };
};
};
// the type used for indexing the rows and columns of the image
using IndexT = short;
static_assert(std::is_integral_v<IndexT>);
static_assert(!std::is_unsigned_v<IndexT>);
// the number of bits used for the pixel
#ifndef PIXEL_BITS
#define PIXEL_BITS 8
#endif
constexpr unsigned kPixelBits = PIXEL_BITS;
static_assert(kPixelBits > 0);
// the type to use for the pixel intensity values and a temporary type
// which should have more bits than the pixel type to check for overflow.
// We will use subtraction on the temporary type, so it must be signed.
using PixelT = ac_int<kPixelBits, false>; // 'kPixelBits' bits, unsigned
using TmpT = long long; // 64 bits, signed
constexpr int kPixelRange = (1 << kPixelBits);
static_assert(std::is_signed_v<TmpT>);
static_assert((sizeof(TmpT) * 8) > kPixelBits);
// add min() and max() functions to std::numeric_limits for PixelT
namespace std {
template<> class numeric_limits<PixelT> {
public:
static constexpr int max() { return (1 << kPixelBits) - 1; };
static constexpr int min() { return 0; };
};
};
// PSRN default threshold
// https://en.wikipedia.org/wiki/Peak_signal-to-noise_ratio
constexpr double kPSNRDefaultThreshold = 30.0;
#endif /* __CONSTANTS_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/anr_params.hpp | #ifndef __ANR_PARAMS_HPP__
#define __ANR_PARAMS_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_fixed.hpp>
#include <iostream>
#include <fstream>
#include <string>
#include <utility>
//
// A struct to hold the ANR configuration paremeters
//
struct ANRParams {
// the floating point format
using FloatT = float;
// the alpha blending computation uses fixed point format, these constants
// hold the total number of bits and the number of integer bits (the number
// of fractional bits is the difference between the two)
static constexpr int kAlphaTotalBits = 9;
static constexpr int kAlphaIntegerBits = 1;
// the ac_fixed type for the alpha value
using AlphaFixedT = ac_fixed<kAlphaTotalBits, kAlphaIntegerBits, false>;
// default constructor
ANRParams() {}
// static method to parse the ANRParams from a file
static ANRParams FromFile(std::string filename) {
// the return object
ANRParams ret;
// create the file stream to parse
std::ifstream is(filename);
// make sure we opened the file fine
if (!is.is_open() || is.fail()) {
std::cerr << "ERROR: failed to open " << filename << " for reading\n";
std::terminate();
}
// parse the lines
std::string line;
while (std::getline(is, line)) {
size_t colon_pos = line.find(':');
auto name = line.substr(0, colon_pos);
auto val = std::stod(line.substr(colon_pos + 1));
if (name == "sig_shot") {
ret.sig_shot = val;
ret.sig_shot_2 = val * val;
} else if (name == "k") {
ret.k = val;
} else if (name == "sig_i_coeff") {
ret.sig_i_coeff = val;
} else if (name == "sig_s") {
ret.sig_s = val;
} else if (name == "alpha") {
ret.alpha = val;
ret.one_minus_alpha = 1 - val;
} else if (name == "filter_size") {
ret.filter_size = val;
} else if (name == "pixel_bits") {
ret.pixel_bits = val;
} else {
std::cerr << "WARNING: unknown name " << name
<< " in ANRParams constructor\n";
}
}
return ret;
}
int filter_size; // filter size
FloatT sig_shot; // shot noise
FloatT k; // total gain
FloatT sig_i_coeff; // intensity sigma coefficient
FloatT sig_s; // spatial sigma
FloatT alpha; // alpha value for alpha blending
int pixel_bits; // the number of bits for each pixel
// precomputed values
FloatT sig_shot_2; // shot noise squared
FloatT one_minus_alpha; // 1 - alpha
};
// convenience method for printing the ANRParams
std::ostream& operator<<(std::ostream& os, const ANRParams& params) {
os << "sig_shot: " << params.sig_shot << "\n";
os << "k: " << params.k << "\n";
os << "sig_i_coeff: " << params.sig_i_coeff << "\n";
os << "sig_s: " << params.sig_s << "\n";
os << "alpha: " << params.alpha << "\n";
return os;
}
#endif /* __ANR_PARAMS_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/column_stencil.hpp | #ifndef __COLUMN_STENCIL_HPP__
#define __COLUMN_STENCIL_HPP__
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "data_bundle.hpp"
#include "shift_reg.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
using namespace sycl;
//
// Generic 1D column (i.e. vertical) stencil.
//
// TEMPLATE PARAMETERS
// InType: The input pixel type. This is read in by the row stencil
// through a SYCL pipe. The pipe should be hold
// 'parallel_cols' elements of this type using the
// 'DataBundle' type (DataBundle<InType, parallel_cols>).
// OutType: The output pixel type. The same logic as the InType above.
// The data written to the output type is
// DataBundle<OutType, parallel_cols>
// IndexT: The datatype used for indexing. This type should have
// enough bits to count up to the number or rows and columns.
// InPipe: The input pipe to stream in 'parallel_cols' 'InT' values.
// OutPipe: The output pipe to stream out 'parallel_cols' 'OutT'
// values.
// filter_size: The filter size (i.e., the number of pixels to convolve).
// max_cols: The maximum number of columns in the image. The runtime
// argument 'cols' chooses the actual number of columns, and
// it must be less than or equal to 'max_cols'. Changing
// 'max_cols' changes the area necessary for the IP, since
// it sets the size of the FIFOs for the line stores.
// parallel_cols: The number of columns to compute in parallel.
// StencilFunction: The stencil callback functor, provided by the user, which
// is called for every pixel to perform the actual
// convolution. The function definition should be as follows:
//
// OutT MyStencilFunction(int, int, ShiftReg<InT, filter_size>,
// FunctionArgTypes...)
//
// The user can provide extra arguments to the callback by
// using the FunctionArgTypes parameter pack.
// FunctionArgTypes: The user-provided type parameter pack of the arguments to
// pass to the callback function.
//
//
// FUNCTION ARGUMENTS
// rows: The number of rows in the image.
// cols: The number of columns in the image.
// computed by the IP is rows*cols.
// zero_val: The 'zero' value for the stencil. This is used to pad
// the columns of the image.
// func: The user-defined functor. This is a callback that is called
// to perform the 1D convolution.
// stencil_args...: The parameter pack of arguments to be passed to the
// user-defined callback functor.
//
template <typename InType, typename OutType, typename IndexT, typename InPipe,
typename OutPipe, unsigned filter_size, unsigned max_cols,
unsigned parallel_cols, typename StencilFunction,
typename... FunctionArgTypes>
void ColumnStencil(IndexT rows, IndexT cols, const InType zero_val,
StencilFunction func, FunctionArgTypes... stencil_args) {
// types coming into and out of the kernel from pipes, respectively
using InPipeT = fpga_tools::DataBundle<InType, parallel_cols>;
using OutPipeT = fpga_tools::DataBundle<OutType, parallel_cols>;
// constexpr
constexpr int kPaddingPixels = filter_size / 2;
constexpr int kShiftRegCols = 1 + parallel_cols - 1;
constexpr int kShiftRegRows = filter_size;
constexpr int kLineBufferFIFODepth =
(max_cols / parallel_cols) + /*filter_size*/ 1;
constexpr int kNumLineBuffers = filter_size - 1;
constexpr IndexT kColThreshLow = kPaddingPixels;
constexpr IndexT kRowThreshLow = kPaddingPixels;
constexpr IndexT kRowOutputThreshLow = 2 * kPaddingPixels;
// static asserts to validate template arguments
static_assert(filter_size > 1);
static_assert(max_cols > parallel_cols);
static_assert(parallel_cols > 0);
static_assert(fpga_tools::IsPow2(parallel_cols));
static_assert(std::is_invocable_r_v<OutType, StencilFunction, int, int,
fpga_tools::ShiftReg<InType, filter_size>,
FunctionArgTypes...>);
// constants
const IndexT row_thresh_high = kPaddingPixels + rows;
const IndexT padded_rows = rows + 2 * kRowThreshLow;
const IndexT fifo_wrap =
(cols + /*filter_size*/ 1 - 1 + (parallel_cols - 1 /*round up*/)) /
parallel_cols;
const IndexT col_loop_bound = (cols / parallel_cols);
// the 2D shift register to store the 'kShiftRegCols' columns of size
// 'kShiftRegRows'
fpga_tools::ShiftReg2d<InType, kShiftRegRows, kShiftRegCols> shifty_2d;
// the line buffer fifo
[[intel::fpga_memory]]
InPipeT line_buffer_FIFO[kLineBufferFIFODepth][kNumLineBuffers];
InPipeT last_new_pixels(zero_val);
IndexT fifo_idx = 0; // track top of FIFO
// the main processing loop for the image
// NOTE: speculated iterations here will cause a bubble, but
// small number relative padded_rows * col_loop_bound and the
// increase in Fmax justifies it.
[[intel::loop_coalesce(2), intel::initiation_interval(1),
intel::ivdep(line_buffer_FIFO)]]
for (IndexT row = 0; row < padded_rows; row++) {
[[intel::initiation_interval(1), intel::ivdep(line_buffer_FIFO)]]
for (IndexT col_loop = 0; col_loop < col_loop_bound; col_loop++) {
// the base column index for this iteration
IndexT col = col_loop * parallel_cols;
// read in values if it is time to start reading
// (row >= kRowThreshLow) and if there are still more to read
// (row < row_thresh_high)
InPipeT new_pixels(zero_val);
if ((row >= kRowThreshLow) && (row < row_thresh_high)) {
new_pixels = InPipe::read();
}
InPipeT input_val(last_new_pixels);
constexpr auto kInputShiftVals =
fpga_tools::Min(kColThreshLow, (IndexT)parallel_cols);
input_val.template ShiftMultiVals<kInputShiftVals, parallel_cols>(
new_pixels);
[[intel::fpga_register]]
InPipeT pixel_column[filter_size];
// load from FIFO to shift register
//
// ┌───────────
// ┌───┬───┬───┐ ┌───┤ FIFO
// │ ◄─ ◄─ ◄─┘ └───────────
// ├───┼───┼───┤ ┌───────────
// │ ◄─ ◄─ ◄─────┤ FIFO
// ├───┼───┼───┤ └───────────
// │ ◄─ ◄─ ◄─────────────────Input
// └───┴───┴───┘
// The attribute [[intel::ivdep(array)]] cannot penetrate lambdas, so we
// use #pragma unroll instead of fpga_tools::UnrolledLoop().
#pragma unroll
for(size_t stencil_row = 0; stencil_row < filter_size; ++stencil_row){
if (stencil_row != (filter_size - 1)) {
pixel_column[stencil_row] = line_buffer_FIFO[fifo_idx][stencil_row];
} else {
pixel_column[stencil_row] = input_val;
}
}
shifty_2d.template ShiftCols<parallel_cols>(pixel_column);
// Continue processing through FIFOs
// ┌─────────────┐
// │ FIFO ◄───┐
// └─────────────┘ │
// ┌───────────────────┘
// │ ┌─────────────┐
// └─┤ FIFO ◄───┐
// └─────────────┘ │
// └─Input
// The attribute [[intel::ivdep(array)]] cannot penetrate lambdas, so we
// use #pragma unroll instead of fpga_tools::UnrolledLoop().
#pragma unroll
for(size_t fifo_row = 0; fifo_row < filter_size - 1; ++fifo_row){
if (fifo_row != (filter_size - 2)) {
line_buffer_FIFO[fifo_idx][fifo_row] = pixel_column[fifo_row + 1];
} else {
line_buffer_FIFO[fifo_idx][(filter_size - 2)] = input_val;
}
}
// Perform the convolution on the 1D window
OutPipeT out_data((OutType)0);
fpga_tools::UnrolledLoop<0, parallel_cols>([&](auto stencil_idx) {
fpga_tools::ShiftReg<InType, kShiftRegRows> shifty_copy;
int col_local = col + stencil_idx;
fpga_tools::UnrolledLoop<0, filter_size>([&](auto stencil_row) {
shifty_copy[stencil_row] = shifty_2d[stencil_row][stencil_idx];
});
// pass a copy of the line buffer's register window.
out_data[stencil_idx] = func((row - kRowOutputThreshLow), col_local,
shifty_copy, stencil_args...);
});
// write the output data if it is in range (i.e., it is a real pixel
// and not part of the padding)
if (row >= kRowOutputThreshLow) {
OutPipe::write(out_data);
}
// increment the fifo read/write index
if (fifo_idx == (fifo_wrap - 1)) {
fifo_idx = 0;
} else {
fifo_idx++;
}
last_new_pixels = new_pixels;
}
}
}
#endif /* __COLUMN_STENCIL_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/qfp_inv_lut.hpp | #ifndef __QFP_INV_LUT_HPP__
#define __QFP_INV_LUT_HPP__
#include "qfp.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "rom_base.hpp"
// the QFP bits for the Pow2LUT
constexpr unsigned kInvQFPTotalBits = 10;
constexpr unsigned kInvQFPExponentBits = 3;
constexpr unsigned kInvLutDepth = (1 << kInvQFPTotalBits);
static_assert(kInvQFPTotalBits >= kInvQFPExponentBits);
//
// A LUT for computing 1/x
//
struct InvLUT : fpga_tools::ROMBase<unsigned short, kInvLutDepth> {
// the QFP format
using QFP = QFP<kInvQFPTotalBits, kInvQFPExponentBits, false>;
// the functor used to initialize the ROM
// NOTE: anything called from within the functor's operator() MUST be
// constexpr or else you won't get a ROM
struct InitFunctor {
constexpr unsigned short operator () (int x) const {
// treat the ROM index as a QFP number and convert to a float (f) and use
// the float to compute 1/f and initialize that entry of the ROM
float f = QFP::ToFP32CE(x);
float val = 1.0f / f ;
return QFP::FromFP32CE(val);
}
constexpr InitFunctor() = default;
};
// constexpr constructor using the initializer above
constexpr InvLUT() : ROMBase<unsigned short, kInvLutDepth>(InitFunctor()) {}
};
#endif /* __QFP_INV_LUT_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/qfp_exp_lut.hpp | #ifndef __QFP_EXP_LUT_HPP__
#define __QFP_EXP_LUT_HPP__
#include "qfp.hpp"
// Included from DirectProgramming/C++SYCL_FPGA/include/
#include "constexpr_math.hpp"
#include "rom_base.hpp"
// the QFP bits for the ExpLUT
constexpr unsigned kExpQFPTotalBits = 10;
constexpr unsigned kExpQFPExponentBits = 6;
constexpr unsigned kExpLUTDepth = (1 << kExpQFPTotalBits);
constexpr int kExpTaylorSeriesTerms = 70;
static_assert(kExpQFPTotalBits >= kExpQFPExponentBits);
static_assert(kExpTaylorSeriesTerms > 3);
//
// A LUT for computing exp(-x)
// Uses ROMBase to create a ROM initialized with the values of exp(-x)
// using quantized floating point (QFP) numbers for indices.
//
struct ExpLUT : fpga_tools::ROMBase<unsigned short, kExpLUTDepth> {
// the QFP format
using QFP = QFP<kExpQFPTotalBits, kExpQFPExponentBits, false>;
// the functor used to initialize the ROM
// NOTE: anything called from within the functor's operator() MUST be
// constexpr or else you won't get a ROM
struct InitFunctor {
constexpr unsigned short operator () (int x) const {
// treat the ROM index as a QFP number and convert to a float (f) and use
// the float to compute exp(-f) (== 1/exp(f)) and initialize that entry
// of the ROM
float f = QFP::ToFP32CE(x);
float val = 1.0f / fpga_tools::Exp(f, kExpTaylorSeriesTerms);
return QFP::FromFP32CE(val);
}
constexpr InitFunctor() = default;
};
// constexpr constructor using the initializer above
constexpr ExpLUT() : ROMBase<unsigned short, kExpLUTDepth>(InitFunctor()) {}
};
#endif /*__QFP_EXP_LUT_HPP__*/
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/src/dma_kernels.hpp | #ifndef __DMA_KERNELS_HPP__
#define __DMA_KERNELS_HPP__
//
// This file contains the kernels for reading from device memory and
// streaming into the ANR input pipe, as well as the kernels for reading from
// the ANR output pipe and writing to device memory.
//
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "data_bundle.hpp"
using namespace sycl;
using namespace fpga_tools;
//
// Kernel to read data from device memory and write it into the ANR input pipe.
//
template <typename KernelId, typename T, typename Pipe, int pixels_per_cycle>
event SubmitInputDMA(queue &q, T *in_ptr, int rows, int cols, int frames) {
using PipeType = DataBundle<T, pixels_per_cycle>;
#if defined (IS_BSP)
// LSU attribute to turn off caching
using NonCachingLSU =
ext::intel::lsu<ext::intel::burst_coalesce<true>, ext::intel::cache<0>,
ext::intel::statically_coalesce<true>,
ext::intel::prefetch<false>>;
#endif
// validate the number of columns
if ((cols % pixels_per_cycle) != 0) {
std::cerr << "ERROR: the number of columns is not a multiple of the pixels "
<< "per cycle\n";
std::terminate();
}
// the number of iterations is the number of total pixels (rows*cols)
// divided by the number of pixels per cycle
const int iterations = cols * rows / pixels_per_cycle;
// Using device memory
return q.single_task<KernelId>([=]() [[intel::kernel_args_restrict]] {
#if defined (IS_BSP)
device_ptr<T> in(in_ptr);
#else
T* in(in_ptr);
#endif
// coalesce the following two loops into a single for-loop using the
// loop_coalesce attribute
[[intel::loop_coalesce(2)]]
for (int f = 0; f < frames; f++) {
for (int i = 0; i < iterations; i++) {
PipeType pipe_data;
#pragma unroll
for (int k = 0; k < pixels_per_cycle; k++) {
#if defined (IS_BSP)
pipe_data[k] = NonCachingLSU::load(in + i * pixels_per_cycle + k);
#else
pipe_data[k] = in[i * pixels_per_cycle + k];
#endif
}
Pipe::write(pipe_data);
}
}
});
}
//
// Kernel to pull data out of the ANR output pipe and writes to device memory.
//
template <typename KernelId, typename T, typename Pipe, int pixels_per_cycle>
event SubmitOutputDMA(queue &q, T *out_ptr, int rows, int cols, int frames) {
// validate the number of columns
if ((cols % pixels_per_cycle) != 0) {
std::cerr << "ERROR: the number of columns is not a multiple of the pixels "
<< "per cycle\n";
std::terminate();
}
// the number of iterations is the number of total pixels (rows*cols)
// divided by the number of pixels per cycle
const int iterations = cols * rows / pixels_per_cycle;
// Using device memory
return q.single_task<KernelId>([=]() [[intel::kernel_args_restrict]] {
#if defined (IS_BSP)
device_ptr<T> out(out_ptr);
#else
T* out(out_ptr);
#endif
// coalesce the following two loops into a single for-loop using the
// loop_coalesce attribute
[[intel::loop_coalesce(2)]]
for (int f = 0; f < frames; f++) {
for (int i = 0; i < iterations; i++) {
auto pipe_data = Pipe::read();
#pragma unroll
for (int k = 0; k < pixels_per_cycle; k++) {
out[i * pixels_per_cycle + k] = pipe_data[k];
}
}
}
});
}
#endif /* __DMA_KERNELS_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/golden_pca.hpp | #include <math.h>
#include <iomanip>
#include <random>
#include <fstream>
/*
This file implements the steps to
identify principal components (Eigen vectors)
of a matrix and finally transform input matrix
along the directions of the principal components
Following are the main steps in order to transform an
matrix A made of multiple samples with different features.
The matrix A will contain n samples with p features
making it an n row, p columns matrix
Here are the steps performed by this file:
1. Generate random matrices
2. Standardize the matrices
3. Compute the covariance matrices of these matrices
4. Compute Eigen vectors and Eigen values of the covariance matrices using the
QR iteration method
*/
template <typename T>
class GoldenPCA {
public:
int samples; // number of samples
int features; // number of features
int matrix_count; // number of matrices
bool debug; // print debug information if true
bool benchmark_mode; // pull data from actual dataset
std::string csv_file_name; // path to the CSV file that holds the dataset
std::vector<T> a_matrix; // storage for input matrices
std::vector<T> standardized_a_matrix; // storage for standardized matrices
std::vector<T> covariance_matrix; // storage for covariance matrices
std::vector<T> eigen_values; // storage for the Eigen values
std::vector<T> eigen_vectors; // storage for the Eigen vectors
std::vector<T> iterations; // the number of QR iterations per matrix
private:
std::default_random_engine gen;
public:
// Constructor
GoldenPCA(int n, int p, int count, bool d, bool benchmark,
std::string file_name) {
samples = n;
features = p;
benchmark_mode = benchmark;
csv_file_name = file_name;
matrix_count = count;
debug = d;
a_matrix.resize(n * p * matrix_count);
standardized_a_matrix.resize(n * p * matrix_count);
covariance_matrix.resize(p * p * matrix_count);
eigen_values.resize(p * matrix_count);
eigen_vectors.resize(p * p * matrix_count);
iterations.resize(matrix_count);
}
// Generate the input matrix with index matrix_index with random numbers
void populateIthA(int matrix_index) {
constexpr float kRandomMin = 0;
constexpr float kRandomMax = 1;
std::uniform_real_distribution<float> distribution(kRandomMin, kRandomMax);
for (int row = 0; row < samples; row++) {
for (int column = 0; column < features; column++) {
float value = distribution(gen);
a_matrix[matrix_index * (samples * features) + row * features +
column] = value;
}
}
if (debug) {
std::cout << "A matrix #" << matrix_index << std::endl;
for (int row = 0; row < samples; row++) {
for (int column = 0; column < features; column++) {
std::cout << a_matrix[matrix_index * (samples * features) +
row * features + column]
<< " ";
}
std::cout << std::endl;
}
std::cout << "A=[";
for (int row = 0; row < samples; row++) {
for (int column = 0; column < features; column++) {
std::cout << a_matrix[matrix_index * (samples * features) +
row * features + column]
<< " ";
}
if (row != (samples - 1)) {
std::cout << "; ";
}
}
std::cout << "]" << std::endl;
}
}
// Generate all the input matrices
void populateA() {
if (benchmark_mode) {
// File pointer
std::ifstream fin;
// Opens the csv file
fin.open(csv_file_name, std::ios::in);
if (!fin) {
std::cerr << "Failed to open the dataset file" << std::endl;
std::terminate();
}
// Read the data from the file
for (int row = -1; row < samples; row++) {
for (int column = -1; column < features; column++) {
std::string element;
fin >> element;
if (column == -1) {
// The fisrt element is ignore as it is a string
continue;
}
// The first row contains the labels, so no data
if (row >= 0) {
a_matrix[row * features + column] = std::stof(element);
}
}
}
fin.close();
} else {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
populateIthA(matrix_index);
}
}
}
// Standardize the A matrix with index matrix_index
void standardizeIthA(int matrix_index) {
// The standardized matrix is defined as:
// standardized_a_matrix[i][j] = (a_matrix[i][j] - mean[j])/(sd[j])
// where mean[j] is the mean value of the column j and sd[j] is
// the standard deviation of this column.
// The standard deviation is defined as
// sd[j] = sqrt(sum((a[k][j] - mean[j])^2)/(N-1))
if (debug)
std::cout << "\nStandardizing A matrix #" << matrix_index << std::endl;
// The current matrix offset in a_matrix
int offset = matrix_index * samples * features;
// Compute the mean of each column
double mean[features];
if (debug) std::cout << "\nMean of each column: " << std::endl;
for (int column = 0; column < features; column++) {
mean[column] = 0;
for (int row = 0; row < samples; row++) {
mean[column] += a_matrix[offset + row * features + column];
}
mean[column] /= samples;
if (debug) std::cout << mean[column] << " ";
}
if (debug) std::cout << std::endl;
// Compute the standard deviation of each column
double standard_deviation[features];
if (debug)
std::cout << "\nStandard deviation of each column: " << std::endl;
for (int column = 0; column < features; column++) {
standard_deviation[column] = 0;
for (int row = 0; row < samples; row++) {
standard_deviation[column] +=
(a_matrix[offset + row * features + column] - mean[column]) *
(a_matrix[offset + row * features + column] - mean[column]);
}
standard_deviation[column] /= (samples - 1);
standard_deviation[column] = sqrt(standard_deviation[column]);
if (debug) std::cout << standard_deviation[column] << " ";
}
if (debug) std::cout << std::endl;
// Compute the standardized matrix A
if (debug) std::cout << "\nStandardized A matrix: " << std::endl;
for (int row = 0; row < samples; row++) {
for (int column = 0; column < features; column++) {
standardized_a_matrix[offset + row * features + column] =
(a_matrix[offset + row * features + column] - mean[column]) /
standard_deviation[column];
if (debug)
std::cout << standardized_a_matrix[offset + row * features + column]
<< " ";
}
if (debug) std::cout << std::endl;
}
}
// Standardize all the A matrices
void standardizeA() {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
standardizeIthA(matrix_index);
}
}
// Compute the covariance matrix of the matrix with index matrix_index
void computeCovarianceIthMatrix(int matrix_index) {
// The covariance matrix is defined as the product of the
// transposition of A by A. This matrix product then needs to be divided
// by the number of samples-1.
// This will result in a matrix of size features x features
if (debug)
std::cout << "\nCovariance matrix #" << matrix_index << std::endl;
int a_matrix_offset = matrix_index * samples * features;
int matrix_c_offset = matrix_index * features * features;
for (int row = 0; row < features; row++) {
for (int column = 0; column < features; column++) {
double dot_product = 0;
for (int k = 0; k < samples; k++) {
dot_product +=
standardized_a_matrix[a_matrix_offset + k * features + row] *
standardized_a_matrix[a_matrix_offset + k * features + column];
}
covariance_matrix[matrix_c_offset + row * features + column] =
dot_product / (samples - 1);
if (debug)
std::cout
<< covariance_matrix[matrix_c_offset + row * features + column]
<< " ";
}
if (debug) std::cout << std::endl;
}
if (debug) {
std::cout << "Cov=[";
for (int row = 0; row < features; row++) {
for (int column = 0; column < features; column++) {
std::cout
<< covariance_matrix[matrix_c_offset + row * features + column]
<< " ";
}
if (row != (features - 1)) {
std::cout << "; ";
}
}
std::cout << "]" << std::endl;
}
}
// Compute the covariance matrix of all the standardized A matrices
void computeCovarianceMatrix() {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
computeCovarianceIthMatrix(matrix_index);
}
}
// Compute the covariance matrix of the standardized A matrix
void computeEigenValuesAndVectors() {
// Compute the Eigen values and Eigen vectors using the QR iteration method
// This implementation uses the Wilkinson shift to speedup the convergence
constexpr float kZeroThreshold = 1e-8;
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
if (debug)
std::cout << "\nComputing Eigen values and vectors of matrix #"
<< matrix_index << std::endl;
int offset = matrix_index * features * features;
// Compute the QR decomposition of the current matrix
std::vector<double> q, r, rq;
q.resize(features * features);
r.resize(features * features);
rq.resize(features * features);
// Copy the covariance matrix into the input matrix to the QR
// decomposition
for (int k = 0; k < features * features; k++) {
rq[k] = covariance_matrix[offset + k];
}
// Initialize the Eigen vectors matrix to the identity matrix
for (int row = 0; row < features; row++) {
for (int column = 0; column < features; column++) {
eigen_vectors[offset + row * features + column] =
row == column ? 1 : 0;
}
}
// Count the number of iterations to abort if there is no convergence
int iterations = 0;
bool converged = false;
while (!converged) {
// Compute the shift value of the current matrix
double shift_value = 0;
// First find where the shift should be applied
// Start from the last submatrix
int shift_row = features - 2;
for (int row = features - 1; row >= 1; row--) {
bool row_is_zero = true;
for (int col = 0; col < row; col++) {
row_is_zero &= (fabs(rq[row * features + col]) < kZeroThreshold);
}
if (!row_is_zero) {
break;
}
shift_row--;
}
if (shift_row >= 0) {
// Compute the shift value
// Take the submatrix:
// [a b]
// [b c]
// and compute the shift such as
// mu = c - (sign(d)* b*b)/(abs(d) + sqrt(d*d + b*b))
// where d = (a - c)/2
double a = rq[shift_row + features * shift_row];
double b = rq[shift_row + features * (shift_row + 1)];
double c = rq[(shift_row + 1) + features * (shift_row + 1)];
double d = (a - c) / 2;
double b_squared = b * b;
double d_squared = d * d;
double b_squared_signed = d < 0 ? -b_squared : b_squared;
shift_value =
c - b_squared_signed / (abs(d) + sqrt(d_squared + b_squared));
}
// Use the 99% percentage of the shift value to avoid
// massive cancellations in the QRD
if (iterations == 0) {
shift_value = 0;
} else {
shift_value *= 0.99;
}
// Subtract the shift value from the diagonal of RQ
for (int row = 0; row < features; row++) {
rq[row + features * row] -= shift_value;
}
// Compute the actual QR decomposition
{
for (int row = 0; row < features; row++) {
for (int column = 0; column < features; column++) {
r[row * features + column] = 0;
q[row * features + column] = 0;
}
}
for (int i = 0; i < features; i++) {
double norm = 0;
for (int k = 0; k < features; k++) {
norm +=
double(rq[k * features + i]) * double(rq[k * features + i]);
}
double rii = std::sqrt(norm);
r[i * features + i] = rii; // r_ii = ||a_i||
for (int k = 0; k < features; k++) {
q[k * features + i] = rq[k * features + i] / rii;
}
for (int j = i + 1; j < features; j++) {
double dp = 0;
for (int k = 0; k < features; k++) {
dp += q[k * features + i] * rq[k * features + j];
}
r[i * features + j] = dp;
for (int k = 0; k < features; k++) {
rq[k * features + j] -= (dp * q[k * features + i]);
}
}
}
}
// Compute the updated Eigen vectors
std::vector<T> eigen_vectors_q_product;
eigen_vectors_q_product.resize(features * features);
for (int row = 0; row < features; row++) {
for (int col = 0; col < features; col++) {
double prod = 0;
for (int k = 0; k < features; k++) {
prod += eigen_vectors[offset + row * features + k] *
q[k * features + col];
}
eigen_vectors_q_product[row * features + col] = prod;
}
}
for (int row = 0; row < features; row++) {
for (int col = 0; col < features; col++) {
eigen_vectors[offset + row * features + col] =
eigen_vectors_q_product[row * features + col];
}
}
for (int row = 0; row < features; row++) {
for (int col = 0; col < features; col++) {
double prod = 0;
for (int k = 0; k < features; k++) {
prod += r[row * features + k] * q[k * features + col];
}
rq[row * features + col] = prod;
}
}
// Add the shift value back to the diagonal of RQ
for (int row = 0; row < features; row++) {
rq[row + features * row] += shift_value;
}
// Check if we found all Eigen Values
bool all_below_threshold = true;
for (int row = 1; row < features; row++) {
for (int col = 0; col < row; col++) {
all_below_threshold &=
(std::fabs(rq[row * features + col]) < kZeroThreshold);
}
}
converged = all_below_threshold;
iterations++;
if ((iterations > (features * features * 16)) && !benchmark_mode) {
std::cout << "Number of iterations too high" << std::endl;
break;
}
}
if ((iterations > (features * features * 16)) && !benchmark_mode) {
std::cout << "Matrix " << matrix_index
<< " required too many iterations, and is being regenerated"
<< std::endl;
populateIthA(matrix_index);
standardizeIthA(matrix_index);
computeCovarianceIthMatrix(matrix_index);
matrix_index--;
} else {
if (debug)
std::cout << "QR iteration stopped after " << iterations
<< " iterations" << std::endl;
this->iterations[matrix_index] = iterations;
if (debug)
std::cout << "Eigen values for matrix #" << matrix_index << std::endl;
for (int k = 0; k < features; k++) {
eigen_values[k + matrix_index * features] = rq[k + features * k];
if (debug) std::cout << rq[k + features * k] << " ";
}
if (debug) std::cout << std::endl;
if (debug) {
std::cout << "Eigen vectors for matrix #" << matrix_index
<< std::endl;
for (int row = 0; row < features; row++) {
for (int col = 0; col < features; col++) {
std::cout << eigen_vectors[offset + row * features + col] << " ";
}
std::cout << std::endl;
}
std::cout << std::endl;
}
}
} // end for:matrix_index
}
}; // class PCA
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "constexpr_math.hpp"
#include "tuple.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_elem_per_bank elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Output matrix pipe
>
void MatrixReadFromDDRToPipeByBlocks(
TT* matrix_ptr, // Input matrix pointer
int matrix_count, // Number of matrix to read from DDR
int repetitions // Number of time to write the same matrix to the pipe
) {
static_assert(columns % rows == 0,
"In order to be able to send the matrix by blocs, the number "
"of rows must be a multiple of the number of columns");
constexpr int kMatrixSize = rows * columns;
constexpr int kBlockCount = columns / rows;
// Repeatedly read matrix_count matrices from DDR and sends them to the pipe
for (int repetition = 0; repetition < repetitions; repetition++) {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
for (int block_index = 0; block_index < kBlockCount; block_index++) {
for (int row = 0; row < rows; row++) {
for (int column = 0; column < rows; column += num_elem_per_bank) {
// Read num_elem_per_bank elements per burst
fpga_tools::NTuple<TT, num_elem_per_bank> ddr_read;
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if (column + k < rows) {
ddr_read.template get<k>() =
matrix_ptr[matrix_index * kMatrixSize + block_index * rows +
row * columns + column + k];
}
});
MatrixPipe::write(ddr_read);
} // end of column
} // end of row
} // end of block_index
} // end of matrix_index
} // end of repetition
}
/*
Write matrix_count matrices of type TT from a pipe, num_elem_per_bank by
num_elem_per_bank and write them to DDR by bursts of num_elem_per_bank
elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Input matrix
>
void MatrixReadPipeToDDR(
TT* matrix_ptr, // Output matrix pointer
int matrix_count, // Number of matrix to write to DDR
int repetitions // Number of time to read the same matrix to the pipe
) {
// We may perform an incomplete memory write if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = rows % num_elem_per_bank != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst of num_elem_per_bank required to write a full column
constexpr int kLoopIterationsPerColumn =
rows / num_elem_per_bank + kExtraIteration;
// Number of DDR burst of num_elem_per_bank to write all the matrices
constexpr int kLoopIterations = kLoopIterationsPerColumn * columns;
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
// Repeatedly read matrix_count matrices from the pipe and write them to DDR
for (int repetition = 0; repetition < repetitions; repetition++) {
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++) {
// Keep track of the current element index in the output matrix
// Only useful in the case of kIncompleteBurst
int write_idx = 0;
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
[[intel::ivdep]] // NO-FORMAT: Attribute
for (int i = 0; i < kLoopIterations; i++) {
fpga_tools::NTuple<TT, num_elem_per_bank> pipe_read =
MatrixPipe::read();
bool last_burst_of_col;
if constexpr (kIncompleteBurst) {
// Check if we are writing the last DDR burst of the current column
last_burst_of_col =
(i % kLoopIterationsPerColumn) == kLoopIterationsPerColumn - 1;
}
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst) {
// Check if the current write index is beyond the end of the current
// matrix column
bool out_of_bounds =
last_burst_of_col && (k > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR writes that are relevant (and don't access a
// memory address that may be beyond the buffer last address)
if (!out_of_bounds) {
matrix_ptr[matrix_index * kMatrixSize + write_idx + k] =
pipe_read.template get<k>();
}
} else {
matrix_ptr[matrix_index * kMatrixSize + i * num_elem_per_bank + k] =
pipe_read.template get<k>();
}
});
if constexpr (kIncompleteBurst) {
// Update the current element index in the write buffer according
// to the write size of the current iteration
write_idx +=
last_burst_of_col ? rows % num_elem_per_bank : num_elem_per_bank;
}
} // end of i
} // end of matrix_index
} // end of repetition
}
/*
Write vector_count vectors of type TT from a pipe, one element at the time and
write them to DDR. Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int size, // Number of rows of the matrix
typename VectorPipe // Input matrix
>
void VectorReadPipeToDDR(
TT* vector_ptr, // Output matrix pointer
int vector_count, // Number of vectors to write to DDR
int repetitions // Number of time to read the same matrix to the pipe
) {
#if defined(IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> vector_ptr_located(vector_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* vector_ptr_located(vector_ptr);
#endif
// Repeat vector_count complete R matrix pipe reads
// for as many repetitions as needed
for (int repetition = 0; repetition < repetitions; repetition++) {
[[intel::loop_coalesce(2)]] // NO-FORMAT: Attribute
for (int vector_index = 0; vector_index < vector_count; vector_index++) {
for (int k = 0; k < size; k++) {
vector_ptr_located[vector_index * size + k] = VectorPipe::read();
} // end of k
} // end of vector_index
} // end of repetition
}
#endif /* __MEMORY_TRANSFERS_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/pca_demo.cpp | #include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include <vector>
#define DEBUG 0
#include "exception_handler.hpp"
#include "golden_pca.hpp"
#include "pca.hpp"
int main(int argc, char *argv[]) {
#if defined(FPGA_SIMULATOR)
// Only read a few lines of the input data when running the simulator
constexpr size_t kPCAsToCompute = 1;
constexpr size_t kFeaturesCount = 4;
constexpr size_t kSamplesCount = 8;
constexpr bool kBenchmarkMode = false;
constexpr bool kBenchmarkModeForcelyDisabled = true;
std::cout << "The benchmark mode is disabled when running the simulator"
<< std::endl;
#elif BENCHMARK
constexpr size_t kPCAsToCompute = 1;
constexpr size_t kFeaturesCount = 8;
constexpr size_t kSamplesCount = 4176;
constexpr bool kBenchmarkMode = true;
constexpr bool kBenchmarkModeForcelyDisabled = false;
#else
constexpr size_t kPCAsToCompute = 8;
constexpr bool kBenchmarkMode = false;
constexpr bool kBenchmarkModeForcelyDisabled = false;
constexpr size_t kFeaturesCount = FEATURES_COUNT;
constexpr size_t kSamplesCount = SAMPLES_COUNT;
#endif
constexpr size_t kAMatrixSize = kSamplesCount * kFeaturesCount;
constexpr size_t kEigenValuesCount = kFeaturesCount;
constexpr size_t kEigenVectorsMatrixSize = kFeaturesCount * kFeaturesCount;
constexpr int k_zero_threshold_1e = -8;
#if defined(FPGA_EMULATOR) or defined(FPGA_SIMULATOR)
int repetitions = 1;
#else
int repetitions = 4096;
#endif
std::string in_file_name = "";
if constexpr (kBenchmarkMode || kBenchmarkModeForcelyDisabled) {
// We expect to read the dataset path from the program arguments
if ((argc != 2) && (argc != 3)) {
std::cout << "Usage: " << std::endl
<< "./pca.xxx <path to abalone.csv> n" << std::endl
<< "where n is an optional parameter which specifies how many "
"times to "
"repeat the computation (for performance evaluation) "
<< std::endl;
std::terminate();
}
// Get the file path
in_file_name = std::string(argv[1]);
if (argc == 3) {
// get the number of repetitions
repetitions = std::stoi(argv[2]);
}
} else {
// We expect to read the dataset path from the program arguments
if (argc == 2) {
// get the number of repetitions
repetitions = std::stoi(argv[1]);
}
}
// Get the number of times we want to repeat the decomposition
// from the command line.
if (repetitions < 1) {
std::cout << "Number of repetitions is lower that 1." << std::endl;
std::cout << "The computation must occur at least 1 time." << std::endl;
std::cout << "Increase the number of repetitions (e.g. 16)." << std::endl;
return 1;
}
try {
// Device selector selection
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::property_list queue_properties{
sycl::property::queue::enable_profiling()};
sycl::queue q =
sycl::queue(selector, fpga_tools::exception_handler, queue_properties);
sycl::device device = q.get_device();
// Print out the device information.
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>() << std::endl;
// Create vectors to hold all the input and output matrices
std::vector<float> a_matrix;
std::vector<float> eigen_values_vector;
std::vector<float> eigen_vectors_matrix;
std::vector<ac_int<1, false>> rank_deficient_flag;
a_matrix.resize(kAMatrixSize * kPCAsToCompute);
eigen_values_vector.resize(kEigenValuesCount * kPCAsToCompute);
eigen_vectors_matrix.resize(kEigenVectorsMatrixSize * kPCAsToCompute);
rank_deficient_flag.resize(kPCAsToCompute);
if (kBenchmarkMode) {
std::cout << "Reading the input data from file." << std::endl;
std::cout << "Features count: " << kFeaturesCount << std::endl;
std::cout << "Samples count: " << kSamplesCount << std::endl;
} else {
std::cout << "Generating " << kPCAsToCompute << " random ";
std::cout << "matri" << (kPCAsToCompute > 1 ? "ces" : "x") << " of size "
<< kSamplesCount << "x" << kFeaturesCount << " " << std::endl;
}
constexpr bool print_debug_information = false;
GoldenPCA<double> pca(kSamplesCount, kFeaturesCount, kPCAsToCompute,
print_debug_information, kBenchmarkMode,
in_file_name);
pca.populateA();
pca.standardizeA();
pca.computeCovarianceMatrix();
pca.computeEigenValuesAndVectors();
// Copy all the input matrices to the of the golden implementation to the
// a_matrix that uses the float datatype, which is going to be used by the
// hardware implementation
for (int matrix_index = 0; matrix_index < kPCAsToCompute; matrix_index++) {
for (int row = 0; row < kSamplesCount; row++) {
for (int column = 0; column < kFeaturesCount; column++) {
a_matrix[matrix_index * kFeaturesCount * kSamplesCount +
column * kSamplesCount + row] =
pca.a_matrix[matrix_index * kFeaturesCount * kSamplesCount +
row * kFeaturesCount +
column]; // implicit double to float cast here
}
}
}
std::cout << "Running Principal Component analysis of " << kPCAsToCompute
<< " matri" << (kPCAsToCompute > 1 ? "ces " : "x ") << repetitions
<< " times" << std::endl;
PCAKernel<kSamplesCount, kFeaturesCount, FIXED_ITERATIONS,
k_zero_threshold_1e>(a_matrix, eigen_values_vector,
eigen_vectors_matrix, rank_deficient_flag, q,
kPCAsToCompute, repetitions);
if (DEBUG) {
for (int matrix_index = 0; matrix_index < kPCAsToCompute;
matrix_index++) {
std::cout << "\n Results : " << matrix_index << std::endl;
std::cout << "\n Eigen Values: \n";
for (int i = 0; i < kFeaturesCount; i++) {
std::cout << eigen_values_vector[matrix_index * kEigenValuesCount + i]
<< " ";
}
std::cout << "\n";
std::cout << "\n Eigen Vectors: \n";
for (int i = 0; i < kFeaturesCount; i++) {
for (int j = 0; j < kFeaturesCount; j++) {
std::cout
<< eigen_vectors_matrix[matrix_index * kEigenVectorsMatrixSize +
i * kFeaturesCount + j]
<< " ";
}
std::cout << "\n";
}
}
}
/////////////////////////////////////////////////////////////////////
///////// Sorting and matching with golden value ///////////////////
/////////////////////////////////////////////////////////////////////
std::cout << "Verifying results..." << std::endl;
std::vector<int> sort_index_golden(kFeaturesCount);
int passed_matrices = 0;
int kernel_innacurate_result_flag_count = 0;
for (int matrix_index = 0; matrix_index < kPCAsToCompute; matrix_index++) {
if (rank_deficient_flag[matrix_index] != 0) {
// Skip the verification of the current matrix as it was flagged as
// rank deficient, which is not supported by the kernel
kernel_innacurate_result_flag_count++;
continue;
}
int eigen_vectors_offset = matrix_index * kEigenVectorsMatrixSize;
int eigen_values_offset = matrix_index * kEigenValuesCount;
// Initialize the indexes for sorting the eigen values.
for (int i = 0; i < kFeaturesCount; i++) {
sort_index_golden[i] = i;
}
// Sort the golden Eigen values by reordering the indexes that we are
// going to access
// The Eigen values and vectors from the kernel are already sorted
std::sort(sort_index_golden.begin(), sort_index_golden.end(),
[=](int a, int b) {
return fabs(pca.eigen_values[eigen_values_offset + a]) >
fabs(pca.eigen_values[eigen_values_offset + b]);
});
// Absolute threshold at which we consider there is an error
constexpr float k_diff_threshold = 1e-2;
int eigen_values_errors = 0;
// Check the Eigen values
for (int i = 0; i < kFeaturesCount; i++) {
int sorted_index_golden = sort_index_golden[i];
float golden_eigen_value =
pca.eigen_values[eigen_values_offset + sorted_index_golden];
float kernel_eigen_value = eigen_values_vector[eigen_values_offset + i];
if (fabs(fabs(golden_eigen_value) - fabs(kernel_eigen_value)) >
k_diff_threshold ||
std::isnan(golden_eigen_value) || std::isnan(kernel_eigen_value)) {
eigen_values_errors++;
std::cout
<< "Mismatch between golden and kernel Eigen value for matrix "
<< matrix_index << std::endl
<< "golden: " << golden_eigen_value << std::endl
<< "kernel: " << kernel_eigen_value << std::endl;
}
}
if (eigen_values_errors != 0) {
std::cout << "Matrix: " << matrix_index << std::endl
<< "Eigen values mismatch count: " << eigen_values_errors
<< std::endl;
}
// Check the Eigen vectors
int eigen_vectors_errors = 0;
for (int row = 0; row < kFeaturesCount; row++) {
for (int column = 0; column < kFeaturesCount; column++) {
float golden_vector_element =
pca.eigen_vectors[eigen_vectors_offset + row * kFeaturesCount +
sort_index_golden[column]];
float kernel_vector_element =
eigen_vectors_matrix[eigen_vectors_offset +
column * kFeaturesCount + row];
if (fabs(fabs(golden_vector_element) - fabs(kernel_vector_element)) >
k_diff_threshold ||
std::isnan(golden_vector_element) ||
std::isnan(kernel_vector_element)) {
eigen_vectors_errors++;
std::cout << "Mismatch between golden and kernel Eigen vector "
<< "at index " << row << ", " << column << " in matrix "
<< matrix_index << std::endl
<< "golden: " << golden_vector_element << std::endl
<< "kernel: " << kernel_vector_element << std::endl
<< std::endl;
}
}
}
if (eigen_vectors_errors != 0) {
std::cout << "Matrix: " << matrix_index << std::endl
<< "Eigen vector elements mismatch count: "
<< eigen_vectors_errors << std::endl;
} else {
passed_matrices++;
}
} // end for:matrix_index
if (kernel_innacurate_result_flag_count > 0) {
std::cout << "During the execution, the kernel identified "
<< kernel_innacurate_result_flag_count
<< " rank deficient matrices." << std::endl;
std::cout << "These matrices were omitted from the data verification."
<< std::endl;
}
if ((passed_matrices + kernel_innacurate_result_flag_count) <
kPCAsToCompute) {
std::cerr << "Errors were identified." << std::endl;
std::cerr << "Pass rate: "
<< (100.0 *
(passed_matrices + kernel_innacurate_result_flag_count)) /
(kPCAsToCompute)
<< "%" << std::endl;
std::terminate();
}
std::cout << "All the tests passed." << std::endl;
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::terminate();
}
return 0;
} // end of main
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/pca/src/pca.hpp | #ifndef __PCA_HPP__
#define __PCA_HPP__
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/sycl.hpp>
#include <vector>
#include "memory_transfers.hpp"
#include "streaming_covariance_matrix.hpp"
#include "streaming_eigen.hpp"
#include "tuple.hpp"
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class InputMatrixFromDDRToLocalMem;
class CovarianceMatrixComputation;
class EigenValuesAndVectorsComputation;
class EigenVectorsFromLocalMemToDDR;
class EigenValuesFromLocalMemToDDR;
class RankDeficientFlagFromLocalMemToDDR;
class CMP;
class IMP;
class EValP;
class EVecP;
class RDFP;
/*
Implementation of the Principal component analysis using multiple streaming
kernels The input matrices are first transformed to their standardized
covariance form before the Eigen values and Eigen vectors are computed. This
function can be configured by datatype, input matrix size and works with
square or rectangular matrices.
*/
template <unsigned k_samples_count, // Number of samples in the input matrix
// (a.k.a rows)
unsigned k_features_count, // Number of features in the input matrix
// (a.k.a columns)
unsigned k_raw_latency, // RAW latency for triangular loop
// optimization in the QR iteration
int k_zero_threshold_1e, // Threshold from which we consider a
// floating point value to be 0 (e.g. -7 ->
// 10e-7)
typename T // The datatype for the computation
>
void PCAKernel(
std::vector<T> &input_matrix, // Input matrix to decompose
std::vector<T> &eigen_values_matrix, // Output matrix of Eigen values
std::vector<T> &eigen_vectors_matrix, // Output matrix of Eigen vectors
std::vector<ac_int<1, false>>
&rank_deficient_flag, // Output a flag that is 1 if the input matrix
// is considered rank deficient
sycl::queue &q, // Device queue
int matrix_count, // Number of matrices to decompose
int repetitions // Number of repetitions, for performance evaluation
) {
static_assert(k_samples_count % k_features_count == 0,
"The feature count must be a multiple of the samples count. "
"This can be artificially achieved by increasing the number of "
"samples with no data.");
static_assert(k_samples_count > k_features_count,
"The number of samples must be greater than the number of "
"samples. Failing to do so, the standardized covariance matrix "
"would be rank deficient. Processing such a matrix from the QR "
"iteration kernel is not supported.");
constexpr int kNumElementsPerDDRBurst = 8;
constexpr int kInputMatrixSize = k_samples_count * k_features_count;
constexpr int kEigenVectorsMatrixSize = k_features_count * k_features_count;
constexpr int kEigenValuesVectorSize = k_features_count;
using PipeType = fpga_tools::NTuple<T, kNumElementsPerDDRBurst>;
// Pipes to communicate the A, Q and R matrices between kernels
using InputMatrixPipe = sycl::ext::intel::pipe<IMP, PipeType, 3>;
using CovarianceMatrixPipe = sycl::ext::intel::pipe<CMP, PipeType, 3>;
using EigenValuesPipe = sycl::ext::intel::pipe<EValP, T, 3>;
using EigenVectorsPipe = sycl::ext::intel::pipe<EVecP, PipeType, 3>;
using RankDeficientFlagPipe =
sycl::ext::intel::pipe<RDFP, ac_int<1, false>, 3>;
T *input_matrix_device;
T *eigen_vectors_device;
T *eigen_values_device;
ac_int<1, false> *rank_deficient_flag_device;
if (q.get_device().has(sycl::aspect::usm_device_allocations)) {
std::cout << "Using device allocations" << std::endl;
// Allocate FPGA DDR memory.
input_matrix_device =
sycl::malloc_device<T>(kInputMatrixSize * matrix_count, q);
eigen_vectors_device =
sycl::malloc_device<T>(kEigenVectorsMatrixSize * matrix_count, q);
eigen_values_device =
sycl::malloc_device<T>(kEigenValuesVectorSize * matrix_count, q);
rank_deficient_flag_device =
sycl::malloc_device<ac_int<1, false>>(matrix_count, q);
} else if (q.get_device().has(sycl::aspect::usm_shared_allocations)) {
std::cout << "Using shared allocations" << std::endl;
// No device allocations means that we are probably in an IP authoring flow
input_matrix_device =
sycl::malloc_shared<T>(kInputMatrixSize * matrix_count, q);
eigen_vectors_device =
sycl::malloc_shared<T>(kEigenVectorsMatrixSize * matrix_count, q);
eigen_values_device =
sycl::malloc_shared<T>(kEigenValuesVectorSize * matrix_count, q);
rank_deficient_flag_device =
sycl::malloc_shared<ac_int<1, false>>(matrix_count, q);
} else {
std::cerr << "USM device allocations or USM shared allocations must be "
"supported to run this sample."
<< std::endl;
std::terminate();
}
// Check that the malloc succeeded.
if (input_matrix_device == nullptr) {
std::cerr << "Error when allocating the input matrix." << std::endl;
std::terminate();
}
if (eigen_vectors_device == nullptr) {
std::cerr << "Error when allocating the Eigen vectors matrix." << std::endl;
std::terminate();
}
if (eigen_values_device == nullptr) {
std::cerr << "Error when allocating the Eigen vectors matrix." << std::endl;
std::terminate();
}
if (rank_deficient_flag_device == nullptr) {
std::cerr << "Error when allocating the Eigen vectors matrix." << std::endl;
std::terminate();
}
// Copy the input matrices from host DDR to FPGA DDR
q.memcpy(input_matrix_device, input_matrix.data(),
kInputMatrixSize * matrix_count * sizeof(T))
.wait();
// The covariance matrix is computed by blocks for k_features_count x
// k_features_count Therefore we read the k_features_count x k_samples_count
// by blocks of k_features_count x k_features_count. k_samples_count is
// expected to be a multiple of k_features_count
// Read the input matrix from FPGA DDR by blocks
auto ddr_write_event = q.submit([&](sycl::handler &h) {
h.single_task<InputMatrixFromDDRToLocalMem>([=
]() [[intel::kernel_args_restrict]] {
MatrixReadFromDDRToPipeByBlocks<T, k_features_count, k_samples_count,
kNumElementsPerDDRBurst, InputMatrixPipe>(
input_matrix_device, matrix_count, repetitions);
});
});
// Compute the covariance matrix
q.single_task<CovarianceMatrixComputation>(
fpga_linalg::StreamingCovarianceMatrix<
T, k_samples_count, k_features_count, kNumElementsPerDDRBurst,
InputMatrixPipe, CovarianceMatrixPipe>());
// Compute the Eigen values and Eigen vectors
q.single_task<EigenValuesAndVectorsComputation>(
fpga_linalg::StreamingEigen<T, k_features_count, k_raw_latency,
kNumElementsPerDDRBurst, k_zero_threshold_1e,
CovarianceMatrixPipe, EigenValuesPipe,
EigenVectorsPipe, RankDeficientFlagPipe>());
// Write the Eigen values from local memory to FPGA DDR
auto eigen_values_event = q.single_task<EigenValuesFromLocalMemToDDR>([=
]() [[intel::kernel_args_restrict]] {
VectorReadPipeToDDR<T, k_features_count, EigenValuesPipe>(
eigen_values_device, matrix_count, repetitions);
});
// Write the rank deficient flag from local memory to FPGA DDR
auto rank_deficient_flag_event =
q.single_task<RankDeficientFlagFromLocalMemToDDR>([=
]() [[intel::kernel_args_restrict]] {
VectorReadPipeToDDR<ac_int<1, false>, 1, RankDeficientFlagPipe>(
rank_deficient_flag_device, matrix_count, repetitions);
});
// Write the Eigen vectors from local memory to FPGA DDR
auto eigen_vectors_event = q.single_task<EigenVectorsFromLocalMemToDDR>([=
]() [[intel::kernel_args_restrict]] {
MatrixReadPipeToDDR<T, k_features_count, k_features_count,
kNumElementsPerDDRBurst, EigenVectorsPipe>(
eigen_vectors_device, matrix_count, repetitions);
});
// Wait for the completion of the pipeline
eigen_values_event.wait();
eigen_vectors_event.wait();
rank_deficient_flag_event.wait();
// Compute the total time the execution lasted
auto start_time = ddr_write_event.template get_profiling_info<
sycl::info::event_profiling::command_start>();
auto end_time = eigen_vectors_event.template get_profiling_info<
sycl::info::event_profiling::command_end>();
double diff = (end_time - start_time) / 1.0e9;
std::cout << " Total duration: " << diff << " s" << std::endl;
std::cout << "Throughput: " << repetitions * matrix_count / diff * 1e-3
<< "k matrices/s" << std::endl;
// Copy the Eigen values and vectors from the FPGA DDR to the host memory
q.memcpy(eigen_vectors_matrix.data(), eigen_vectors_device,
kEigenVectorsMatrixSize * matrix_count * sizeof(T))
.wait();
q.memcpy(eigen_values_matrix.data(), eigen_values_device,
kEigenValuesVectorSize * matrix_count * sizeof(T))
.wait();
q.memcpy(rank_deficient_flag.data(), rank_deficient_flag_device,
matrix_count * sizeof(ac_int<1, false>))
.wait();
// Clean allocated FPGA memory
free(input_matrix_device, q);
free(eigen_vectors_device, q);
free(eigen_values_device, q);
free(rank_deficient_flag_device, q);
}
#endif /* __PCA_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri_demo.cpp | #include <math.h>
#include <sycl/sycl.hpp>
#include <chrono>
#include <iomanip>
#include <list>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "exception_handler.hpp"
#include "qri.hpp"
#ifdef FPGA_SIMULATOR
#define ROWS_COMPONENT_V 8
#define COLS_COMPONENT_V 8
#else
#define ROWS_COMPONENT_V ROWS_COMPONENT
#define COLS_COMPONENT_V COLS_COMPONENT
#endif
/*
COMPLEX, COLS_COMPONENT, ROWS_COMPONENT, FIXED_ITERATIONS_QRD and
FIXED_ITERATIONS_QRI are defined by the build system.
Depending on the value of COMPLEX, the real or complex QR based matrix
inversion function (QRI) is defined.
Each matrix (input and output) are represented using vectors and are
interpreted in a column fashion (transposed).
Function arguments:
- a_matrix: The input matrix to be inverted.
Interpreted as a transposed matrix.
- inv_matrix: The output matrix. The function will overwrite this matrix.
Will contain the inverse of a_matrix.
- q: The device queue.
- matrices: The number of matrices to be processed.
The input matrices are read sequentially from the a_matrix
vector.
- repetitions: The number of repetitions of the computation to execute.
(for performance evaluation)
*/
#if COMPLEX == 0
// Real single precision floating-point QR based inversion
void QRI(std::vector<float> &a_matrix, std::vector<float> &inv_matrix,
sycl::queue &q, size_t matrices, size_t repetitions) {
constexpr bool is_complex = false;
QRIImpl<COLS_COMPONENT_V, ROWS_COMPONENT_V, FIXED_ITERATIONS_QRD,
FIXED_ITERATIONS_QRI, is_complex, float>(a_matrix, inv_matrix, q,
matrices, repetitions);
}
#else
// Complex single precision floating-point QR based inversion
void QRI(std::vector<ac_complex<float> > &a_matrix,
std::vector<ac_complex<float> > &inv_matrix, sycl::queue &q,
size_t matrices, size_t repetitions) {
constexpr bool is_complex = true;
QRIImpl<COLS_COMPONENT_V, ROWS_COMPONENT_V, FIXED_ITERATIONS_QRD,
FIXED_ITERATIONS_QRI, is_complex, float>(a_matrix, inv_matrix, q,
matrices, repetitions);
}
#endif
/*
Returns a random floating-point value between min and max
*/
float RandomValueInInterval(float min, float max) {
return min + static_cast<float>(rand()) /
(static_cast<float>(RAND_MAX) / (max - min));
}
/*
returns if both the real and complex parts of the given ac_complex
value are finite
*/
bool IsFinite(ac_complex<float> val) {
return std::isfinite(val.r()) && std::isfinite(val.i());
}
/*
returns if the given value is finite
*/
bool IsFinite(float val) { return std::isfinite(val); }
/*
Generate a random matrix M with a given epsilon such that
cond(M, inf) <= (1+epsilon)/(1-epsilon)
This is helpful as having a condition number with infinite norm close to 1
reduces the numerical instability of the matrix inversion.
Provided an epsilon value, this function populates the output vector with
a matrix in a row fashion.
Algorithm courtesy of Carl Christian Kjelgaard Mikkelsen ([email protected])
Matlab code snipet this function reimplements in C++:
function [A, B]=myDiagonal(m,epsilon)
% Returns a matrix that is diagonally dominant by rows
%
% CALL SEQUENCE:
% [A, B]=ccDiagonally(m, epsilon)
%
% INPUT:
% m the dimension
% epsilon the dominance factor epsilon in (0,1]
%
% OUTPUT:
% A a matrix which is strictly diagonally domimant by rows
% B B = D\A, where D is the diagonal of A
%
% The main purpose of this function is to construct test matrices
% for, say, Gaussian elimination with no pivoting.
%
% The matrix A is not necessarily well-conditioned, but
% the infinity norm condition number of the matrix B is bounded by
%
% (1+epsilon)/(1 - epsilon)
% PROGRAMMING by Carl Christian Kjelgaard Mikkelsen ([email protected])
% 2021-10-21 Initial programming and testing.
% Generate a random matrix
R=rand(m,m)-rand(m,m);
% Eliminate the diagonal
D=diag(diag(R)); R=R-D;
% Measure the weight of the off diagonal entries
w=abs(R)*ones(m,1);
% Construct the new diagonal elements
d=w/epsilon;
% Construct the matrix which is diagonally dominant
A=R+diag(d);
% Do the diagonal scaling
B=diag(diag(A))\A;
*/
template <int size, typename T>
void GenerateMatrixWithCondititionNumber(float epsilon,
std::vector<T> &output) {
// Random min and max values for the random floating-point value generation
constexpr float kRandomMin = 0;
constexpr float kRandomMax = 1;
// Generate a random matrix R with diagonal elements set to 0
// and measure the weights of the off diagonal entries
std::vector<T> r, weights;
r.resize(size * size);
weights.resize(size);
for (int row = 0; row < size; row++) {
weights[row] = {0};
for (int col = 0; col < size; col++) {
if (col != row) {
float random1 = RandomValueInInterval(kRandomMin, kRandomMax);
T elem;
#if COMPLEX == 1
float random1I = RandomValueInInterval(kRandomMin, kRandomMax);
elem = {random1, random1I};
r[row * size + col] = elem;
#else
elem = random1;
r[row * size + col] = elem;
#endif
weights[row] += elem;
}
}
// Construct the new diagonal element
weights[row] /= epsilon;
r[row * size + row] = weights[row];
}
// Perform the diagonal scaling by solving:
// diag(diag(A))*output = A
for (int row = 0; row < size; row++) {
for (int col = 0; col < size; col++) {
output[row * size + col] = r[row * size + col] / r[row * size + row];
}
}
}
int main(int argc, char *argv[]) {
constexpr size_t kRandomSeed = 1138;
constexpr size_t kRows = ROWS_COMPONENT_V;
constexpr size_t kColumns = COLS_COMPONENT_V;
constexpr size_t kAMatrixSize = kRows * kColumns;
constexpr size_t kInverseMatrixSize = kRows * kColumns;
constexpr bool kComplex = COMPLEX != 0;
#if defined(FPGA_SIMULATOR)
constexpr size_t kMatricesToInvert = 1;
#else
constexpr size_t kMatricesToInvert = 8;
#endif
// Get the number of times we want to repeat the inversion
// from the command line.
#if defined(FPGA_EMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 16;
#elif defined(FPGA_SIMULATOR)
int repetitions = argc > 1 ? atoi(argv[1]) : 1;
#else
int repetitions = argc > 1 ? atoi(argv[1]) : 6553600;
#endif
if (repetitions < 1) {
std::cout << "Number of repetitions given is lower that 1." << std::endl;
std::cout << "The decomposition must occur at least 1 time." << std::endl;
std::cout << "Increase the number of repetitions (e.g. 16)." << std::endl;
return 1;
}
try {
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// Enable the queue profiling to time the execution
sycl::property_list
queue_properties{sycl::property::queue::enable_profiling()};
sycl::queue q = sycl::queue(selector,
fpga_tools::exception_handler,
queue_properties);
sycl::device device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<sycl::info::device::name>().c_str()
<< std::endl;
// Select a type for this compile depending on the value of COMPLEX
using TF = std::conditional_t<kComplex, ac_complex<float>, float>;
// Select a type for computing the inverse in the testbench using a more
// precise format than the kernel
using TD = std::conditional_t<kComplex, ac_complex<double>, double>;
// Create vectors to hold all the input and output matrices
std::vector<TF> a;
std::vector<TF> inv_matrix;
std::vector<TF> precomputed_inv_matrix;
a.resize(kMatricesToInvert * kAMatrixSize);
inv_matrix.resize(kMatricesToInvert * kInverseMatrixSize);
precomputed_inv_matrix.resize(kMatricesToInvert * kInverseMatrixSize);
std::cout << "Generating " << kMatricesToInvert << " random ";
if constexpr (kComplex) {
std::cout << "complex ";
} else {
std::cout << "real ";
}
std::cout << "matri" << ((kMatricesToInvert == 1) ? "x " : "ces ")
<< "of size "
<< kRows << "x" << kColumns << " " << std::endl;
// Generate the random input matrices and precompute their inverse
srand(kRandomSeed);
for (size_t i = 0; i < kMatricesToInvert; i++) {
std::vector<TF> random_matrix;
random_matrix.resize(kAMatrixSize);
// Setting an epsilon of 0.5 ensures that the inverse matrix will have
// a condition number using the infinite norm lower than 1.5/0.5 = 3
float epsilon = 0.5;
GenerateMatrixWithCondititionNumber<kRows>(epsilon, random_matrix);
// Copy the generated matrix in the A vector
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
a[i * kAMatrixSize + col * kRows + row] =
random_matrix[row * kColumns + col];
}
}
// Precompute the inverse of A using the Gaussian elimination
// A copy of A that will be modified
TD a_copy[kColumns][kRows];
// The inverse matrix that will be iteratively constructed starting from
// the identity matrix
TD inverse[kColumns][kRows];
// Copy A in a_copy and set "inverse" to the identity matrix
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
if (row == col) {
inverse[row][col] = {1.0};
} else {
inverse[row][col] = {0.0};
}
a_copy[row][col] = random_matrix[row * kColumns + col];
}
}
// If we can't find a solution using the Gaussian elimination,
// we may give up on this matrix and generate another one
bool give_up = false;
// Perform the Gaussian elimination
for (int row = 0; row < kRows; row++) {
// Find the next pivot
auto pivot = a_copy[row][row];
// If the pivot is zero, we need to swap the current row with
// another row that would give a non-zero pivot.
bool pivot_is_zero = pivot == 0.0 || pivot == -0.0;
if (pivot_is_zero) {
// Find an alternate row to use for pivoting
for (int next_row = row + 1; next_row < kRows; next_row++) {
TD potential_pivot = a_copy[next_row][row];
bool potential_pivot_is_zero =
potential_pivot == 0.0 || potential_pivot == -0.0;
// row can be used to swap
if (!potential_pivot_is_zero) {
// Swap the two rows
for (int j = 0; j < kColumns; j++) {
auto tmp = a_copy[row][j];
a_copy[row][j] = a_copy[next_row][j];
a_copy[next_row][j] = tmp;
tmp = inverse[row][j];
inverse[row][j] = inverse[next_row][j];
inverse[next_row][j] = tmp;
}
// The swap was successful, stop searching for a row to swap with
break;
}
}
// Get the new pivot
pivot = a_copy[row][row];
// If the swapping was unsuccessful are the new pivot is 0,
// give up on this matrix generate another one
give_up = pivot == 0.0 || pivot == -0.0;
if (give_up) {
break;
}
}
// Divide the current row by the pivot value
for (int k = 0; k < kColumns; k++) {
a_copy[row][k] = a_copy[row][k] / pivot;
inverse[row][k] = inverse[row][k] / pivot;
}
// Eliminate the current row in all other rows
for (int row_to_eliminate = kRows - 1; row_to_eliminate >= 0;
row_to_eliminate--) {
if (row_to_eliminate == row) {
continue;
}
auto factor = a_copy[row_to_eliminate][row];
for (int k = 0; k < kColumns; k++) {
if (k == row) {
a_copy[row_to_eliminate][k] =
a_copy[row_to_eliminate][k] - factor;
} else {
a_copy[row_to_eliminate][k] =
a_copy[row_to_eliminate][k] - (a_copy[row][k] * factor);
}
inverse[row_to_eliminate][k] =
inverse[row_to_eliminate][k] - (inverse[row][k] * factor);
}
}
}
// Compute the norm inf of both the input and the inverse matrices
// to compute the condition number and verify that it is lower than the
// expected threshold
double norm_inf_a = 0.0;
double norm_inf_inverse = 0.0;
for (size_t row = 0; row < kRows; row++) {
// Compute the norm inf of the current row on both matrices
double norm_current_row_of_a = 0.0;
double norm_current_row_of_inverse = 0.0;
for (size_t col = 0; col < kColumns; col++) {
norm_current_row_of_a += abs(random_matrix[row * kColumns + col]);
norm_current_row_of_inverse += abs(inverse[row][col]);
}
// Update the norm inf of both matrices if the norm inf of the current
// row is the new max
if (norm_current_row_of_a > norm_inf_a) {
norm_inf_a = norm_current_row_of_a;
}
if (norm_current_row_of_inverse > norm_inf_inverse) {
norm_inf_inverse = norm_current_row_of_inverse;
}
}
// Copy the current inverse matrix in the precomputed_inv_matrix vector
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
// If any of the element in not finite, give up on this matrix
if (!IsFinite(inverse[row][col])) {
give_up = true;
} else {
precomputed_inv_matrix[i * kAMatrixSize + row * kColumns + col] =
inverse[row][col];
}
}
}
// Compute the condition number
double condition_number = norm_inf_a * norm_inf_inverse;
double expected_conditionNumber = (1 + epsilon) / (1 - epsilon);
// Regenerate this matrix if:
// - the condition number is higher than the expected one
// - we gave up earlier
if (condition_number > expected_conditionNumber || give_up) {
i--;
}
#ifdef DEBUG
else {
std::cout << "A matrix" << std::endl;
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
std::cout << a[i * kAMatrixSize + col * kColumns + row] << " ";
}
std::cout << std::endl;
}
std::cout << "norm_inf_a " << norm_inf_a << std::endl;
std::cout << "norm_inf_inverse " << norm_inf_inverse << std::endl;
std::cout << "condition_number " << condition_number << std::endl;
}
#endif
}
std::cout << "Running QR inversion of " << kMatricesToInvert << " matri"
<< ((kMatricesToInvert == 1) ? "x " : "ces ")
<< repetitions << " time"
<< ((repetitions > 1) ? "s" : "")
<< std::endl;
// Launch the compute kernel
QRI(a, inv_matrix, q, kMatricesToInvert, repetitions);
// Count the number of errors found for this matrix
int error_count = 0;
// Keep track of the max difference between the precomputed matrix using the
// Gaussian elimination on the double datatype and the kernel computed
// inverse matrix using a QR based algorithm with the float datatype.
double max_diff_between_soft_and_hard = 0.0;
// For output post-processing (OP)
TF inv_matrix_op[kRows][kColumns];
// Floating-point error threshold value at which we decide that the design
// computed an incorrect value
constexpr float kErrorThreshold = 1e-4;
std::cout << "Verifying results... ";
for (int matrix = 0; matrix < kMatricesToInvert; matrix++) {
// Read the inverse matrix from the output vector to inv_matrix_op
size_t idx = 0;
for (size_t j = 0; j < kColumns; j++) {
for (size_t i = 0; i < kRows; i++) {
inv_matrix_op[j][i] = inv_matrix[matrix * kInverseMatrixSize + idx];
idx++;
}
}
#ifdef DEBUG
std::cout << "Kernel inverse" << std::endl;
for (int row = 0; row < kRows; row++) {
for (int col = 0; col < kColumns; col++) {
std::cout << inv_matrix_op[row][col] << " ";
}
std::cout << std::endl;
}
std::cout << "Precomputed inverse" << std::endl;
for (int row = 0; row < kRows; row++) {
for (int col = 0; col < kColumns; col++) {
std::cout << precomputed_inv_matrix[matrix * kAMatrixSize +
row * kColumns + col]
<< " ";
}
std::cout << std::endl;
}
#endif
// Keep track of the max difference between the precomputed inverse and
// the kernel inverse
double max_diff = 0.0;
#if COMPLEX == 1
for (size_t row = 0; row < kRows; row++) {
for (size_t col = 0; col < kColumns; col++) {
double diff_r = abs(
inv_matrix_op[row][col].r() -
precomputed_inv_matrix[matrix * kAMatrixSize + row * kColumns + col].r());
double diff_i = abs(
inv_matrix_op[row][col].i() -
precomputed_inv_matrix[matrix * kAMatrixSize + row * kColumns + col].i());
if (!std::isfinite(diff_r) || !std::isfinite(diff_r)) {
error_count++;
}
if (diff_r > max_diff) {
max_diff = diff_r;
}
if (diff_i > max_diff) {
max_diff = diff_i;
}
if (diff_r > kErrorThreshold) {
error_count++;
}
if (diff_i > kErrorThreshold) {
error_count++;
}
}
}
#else
for (size_t i = 0; i < kRows; i++) {
for (size_t j = 0; j < kColumns; j++) {
double diff = abs(
inv_matrix_op[i][j] -
precomputed_inv_matrix[matrix * kAMatrixSize + i * kColumns + j]);
if (!std::isfinite(diff)) {
error_count++;
}
if (diff > max_diff) {
max_diff = diff;
}
if (diff > kErrorThreshold) {
error_count++;
}
}
}
#endif
// Update the max diff
if (max_diff > max_diff_between_soft_and_hard) {
max_diff_between_soft_and_hard = max_diff;
}
// If an error was found, stop checking matrices
if (error_count > 0) {
break;
}
} // end of matrix
if (error_count > 0) {
std::cout << std::endl << "FAILED" << std::endl;
std::cout << std::endl
<< "!!!!!!!!!!!!!! " << error_count << " errors" << std::endl;
std::cout << "Max difference between the precomputed inverse and the "
<< "kernel value: " << max_diff_between_soft_and_hard
<< std::endl;
return 1;
}
std::cout << std::endl << "PASSED" << std::endl;
return 0;
} catch (sycl::exception const &e) {
std::cerr << "Caught a synchronous SYCL exception: " << e.what()
<< std::endl;
std::cerr << " If you are targeting an FPGA hardware, "
"ensure that your system is plugged to an FPGA board that is "
"set up correctly"
<< std::endl;
std::cerr << " If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR"
<< std::endl;
std::terminate();
} catch (std::bad_alloc const &e) {
std::cerr << "Caught a memory allocation exception on the host: "
<< e.what() << std::endl;
std::cerr << " You can reduce the memory requirement by reducing the "
"number of matrices generated. Specify a smaller number when "
"running the executable."
<< std::endl;
std::cerr << " In this run, more than "
<< (((long long)kMatricesToInvert
* (kAMatrixSize + kInverseMatrixSize)
* sizeof(float)) / pow(2, 30))
<< " GBs of memory was requested for " << kMatricesToInvert
<< " matrices, each of size " << kRows << " x " << kColumns
<< std::endl;
std::terminate();
}
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/qri.hpp | #pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <sycl/ext/intel/ac_types/ac_complex.hpp>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <chrono>
#include <cstring>
#include <type_traits>
#include <vector>
#include "memory_transfers.hpp"
#include "streaming_qrd.hpp"
#include "streaming_qri.hpp"
#include "tuple.hpp"
// Forward declare the kernel and pipe names
// (This prevents unwanted name mangling in the optimization report.)
class QRIDDRToLocalMem;
class QRD;
class QRIKernel;
class QRILocalMemToDDRQ;
class APipe;
class QPipe;
class RPipe;
class IPipe;
template <unsigned columns, // Number of columns in the input matrix
unsigned rows, // Number of rows in the input matrix
unsigned raw_latency_qrd, // RAW latency for triangular loop
// optimization in the QRD kernel
unsigned raw_latency_qri, // RAW latency for triangular loop
// optimization in the QRI kernel
bool is_complex, // Selects between ac_complex<T> and T
// datatype
typename T, // The datatype for the computation
typename TT = std::conditional_t<is_complex, ac_complex<T>, T>
// TT will be ac_complex<T> or T depending
// on is_complex
>
void QRIImpl(
std::vector<TT> &a_matrix, // Input matrix to inverse
std::vector<TT> &inverse_matrix, // Output inverse matrix
sycl::queue &q, // Device queue
size_t matrix_count, // Number of matrices to process
size_t repetitions // Number of repetitions (for performance
// evaluation)
) {
// Functional limitations
static_assert(
rows >= columns,
"only rectangular matrices with rows>=columns are matrices supported");
static_assert(columns >= 4,
"only matrices of size 4x4 or over are supported");
constexpr int kAMatrixSize = rows * columns;
constexpr int kInverseMatrixSize = rows * columns;
constexpr int kNumElementsPerDDRBurst = is_complex ? 4 : 8;
using PipeType = fpga_tools::NTuple<TT, kNumElementsPerDDRBurst>;
using AMatrixPipe = sycl::ext::intel::pipe<APipe, PipeType, 3>;
using QMatrixPipe = sycl::ext::intel::pipe<QPipe, PipeType, 3>;
using RMatrixPipe = sycl::ext::intel::pipe<RPipe, TT, 3>;
using InverseMatrixPipe = sycl::ext::intel::pipe<IPipe, PipeType, 3>;
// Create buffers and allocate space for them.
#if defined (IS_BSP)
TT *a_device = sycl::malloc_device<TT>(kAMatrixSize * matrix_count, q);
TT *i_device = sycl::malloc_device<TT>(kInverseMatrixSize * matrix_count, q);
#else
// malloc_device are not supported when targetting an FPGA part/family
TT *a_device = sycl::malloc_shared<TT>(kAMatrixSize * matrix_count, q);
TT *i_device = sycl::malloc_shared<TT>(kInverseMatrixSize * matrix_count, q);
#endif
q.memcpy(a_device, a_matrix.data(),
kAMatrixSize * matrix_count * sizeof(TT)).wait();
auto ddr_write_event = q.submit([&](sycl::handler &h) {
h.single_task<QRIDDRToLocalMem>([=]() [[intel::kernel_args_restrict]] {
MatrixReadFromDDRToPipe<TT, rows, columns, kNumElementsPerDDRBurst,
AMatrixPipe>(a_device, matrix_count, repetitions);
});
});
// Read the A matrix from the AMatrixPipe pipe and compute the QR
// decomposition. Write the Q and R output matrices to the QMatrixPipe
// and RMatrixPipe pipes.
q.single_task<QRD>(
fpga_linalg::StreamingQRD<T, is_complex, rows, columns, raw_latency_qrd,
kNumElementsPerDDRBurst,
AMatrixPipe, QMatrixPipe, RMatrixPipe>());
q.single_task<QRIKernel>(
// Read the Q and R matrices from pipes and compute the inverse of A.
// Write the result to the InverseMatrixPipe pipe.
fpga_linalg::StreamingQRI<T, is_complex, rows, columns, raw_latency_qri,
kNumElementsPerDDRBurst,
QMatrixPipe, RMatrixPipe, InverseMatrixPipe>());
auto i_event = q.single_task<QRILocalMemToDDRQ>([=
]() [[intel::kernel_args_restrict]] {
// Read the inverse matrix from the InverseMatrixPipe pipe and copy it
// to the FPGA DDR
MatrixReadPipeToDDR<TT, rows, columns, kNumElementsPerDDRBurst,
InverseMatrixPipe>(i_device, matrix_count, repetitions);
});
i_event.wait();
// Compute the total time the execution lasted
auto start_time = ddr_write_event.template
get_profiling_info<sycl::info::event_profiling::command_start>();
auto end_time = i_event.template
get_profiling_info<sycl::info::event_profiling::command_end>();
double diff = (end_time - start_time) / 1.0e9;
// Make sure we throw any asynchronous errors if they have occurred during
// the computation
q.throw_asynchronous();
std::cout << " Total duration: " << diff << " s" << std::endl;
std::cout << "Throughput: "
<< repetitions * matrix_count / diff * 1e-3
<< "k matrices/s" << std::endl;
// Copy the Q and R matrices result from the FPGA DDR to the host memory
q.memcpy(inverse_matrix.data(), i_device,
kInverseMatrixSize * matrix_count * sizeof(TT)).wait();
// Clean allocated FPGA memory
free(a_device, q);
free(i_device, q);
} | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qri/src/memory_transfers.hpp | #ifndef __MEMORY_TRANSFERS_HPP__
#define __MEMORY_TRANSFERS_HPP__
#include "tuple.hpp"
#include "constexpr_math.hpp"
#include "unrolled_loop.hpp"
/*
Read matrix_count matrices of type TT from DDR by bursts of num_elem_per_bank
elements, and write the matrices to the "MatrixPipe" pipe num_elem_per_bank by
num_elem_per_bank elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Output matrix pipe
>
void MatrixReadFromDDRToPipe(
TT* matrix_ptr, // Input matrix pointer
int matrix_count,// Number of matrix to read from DDR
int repetitions // Number of time to write the same matrix to the pipe
) {
// We may perform an incomplete memory read if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = rows%num_elem_per_bank != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst reads of num_elem_per_bank elements required to read a
// full column
constexpr int kLoopIterPerColumn = rows / num_elem_per_bank + kExtraIteration;
// Number of DDR burst reads of num_elem_per_bank to read all the matrices
constexpr int kLoopIter = kLoopIterPerColumn * columns;
// Size in bits of the loop iterator over kLoopIter iterations
constexpr int kLoopIterBitSize = fpga_tools::BitsForMaxValue<kLoopIter + 1>();
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> matrix_ptr_located(matrix_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* matrix_ptr_located(matrix_ptr);
#endif
// Repeatedly read matrix_count matrices from DDR and sends them to the pipe
for (int repetition = 0; repetition < repetitions; repetition++){
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++){
// Keep track of the current element index in the matrix
// Only useful in the case of kIncompleteBurst
int load_index = 0;
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
for (ac_int<kLoopIterBitSize, false> li = 0; li < kLoopIter; li++) {
bool last_burst_of_col;
if constexpr (kIncompleteBurst){
// Check if we are reading the last DDR burst of the current column
last_burst_of_col = (li % kLoopIterPerColumn)
== kLoopIterPerColumn - 1;
}
fpga_tools::NTuple<TT, num_elem_per_bank> ddr_read;
// Perform the DDR burst read of num_elem_per_bank elements
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst){
// Check if the current read index is beyond the end of the current
// matrix column
bool out_of_bounds = last_burst_of_col &&
((k % num_elem_per_bank) > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR reads that are relevant (and don't access a
// memory address that may be beyond the matrix last address)
if (!out_of_bounds) {
ddr_read.template get<k>() = matrix_ptr_located
[matrix_index * kMatrixSize + load_index + k];
}
}
else{
ddr_read.template get<k>() = matrix_ptr_located
[matrix_index * kMatrixSize + (int)(li)*num_elem_per_bank + k];
}
});
if constexpr (kIncompleteBurst){
// Update the current element index in the input matrix according
// to the read size of the current iteration
load_index += last_burst_of_col ? rows % num_elem_per_bank :
num_elem_per_bank;
}
MatrixPipe::write(ddr_read);
} // end of li
} // end of matrix_index
} // end of repetition
}
/*
Write matrix_count matrices of type TT from a pipe, num_elem_per_bank by
num_elem_per_bank and write them to DDR by bursts of num_elem_per_bank
elements.
Repeat this operations "repetitions" times.
*/
template <typename TT, // Datatype of the elements of the matrix
int rows, // Number of rows of the matrix
int columns, // Number of columns of the matrix
int num_elem_per_bank, // Number of TT elements per DDR burst access
typename MatrixPipe // Input matrix
>
void MatrixReadPipeToDDR(
TT* matrix_ptr, // Output matrix pointer
int matrix_count,// Number of matrix to write to DDR
int repetitions // Number of time to read the same matrix to the pipe
) {
// We may perform an incomplete memory write if the number of elements per row
// is not a multiple of the DDR burst size
constexpr bool kIncompleteBurst = rows%num_elem_per_bank != 0;
constexpr int kExtraIteration = kIncompleteBurst ? 1 : 0;
// Number of DDR burst of num_elem_per_bank required to write a full column
constexpr int kLoopIterPerColumn = rows / num_elem_per_bank + kExtraIteration;
// Number of DDR burst of num_elem_per_bank to write all the matrices
constexpr int kLoopIter = kLoopIterPerColumn * columns;
// Size in bits of the loop iterator over kLoopIter iterations
constexpr int kLoopIterBitSize = fpga_tools::BitsForMaxValue<kLoopIter + 1>();
// Size of a full matrix
constexpr int kMatrixSize = rows * columns;
#if defined (IS_BSP)
// When targeting a BSP, we instruct the compiler that this pointer
// lives on the device.
// Knowing this, the compiler won't generate hardware to
// potentially get data from the host.
sycl::device_ptr<TT> matrix_ptr_located(matrix_ptr);
#else
// Device pointers are not supported when targeting an FPGA
// family/part
TT* matrix_ptr_located(matrix_ptr);
#endif
// Repeatedly read matrix_count matrices from the pipe and write them to DDR
for (int repetition = 0; repetition < repetitions; repetition++){
for (int matrix_index = 0; matrix_index < matrix_count; matrix_index++){
// Keep track of the current element index in the output matrix
// Only useful in the case of kIncompleteBurst
int write_idx = 0;
[[intel::initiation_interval(1)]] // NO-FORMAT: Attribute
[[intel::ivdep]] // NO-FORMAT: Attribute
for (ac_int<kLoopIterBitSize, false> li = 0; li < kLoopIter; li++) {
fpga_tools::NTuple<TT, num_elem_per_bank> pipe_read =
MatrixPipe::read();
bool last_burst_of_col;
if constexpr (kIncompleteBurst){
// Check if we are writing the last DDR burst of the current column
last_burst_of_col =
(li % kLoopIterPerColumn) == kLoopIterPerColumn - 1;
}
fpga_tools::UnrolledLoop<num_elem_per_bank>([&](auto k) {
if constexpr (kIncompleteBurst){
// Check if the current write index is beyond the end of the current
// matrix column
bool out_of_bounds = last_burst_of_col &&
(k > ((rows - 1) % num_elem_per_bank));
// Only perform the DDR writes that are relevant (and don't access a
// memory address that may be beyond the buffer last address)
if (!out_of_bounds) {
matrix_ptr_located[matrix_index * kMatrixSize + write_idx + k] =
pipe_read.template get<k>();
}
}
else{
matrix_ptr_located[matrix_index * kMatrixSize
+ int(li) * num_elem_per_bank + k] = pipe_read.template get<k>();
}
});
if constexpr (kIncompleteBurst){
// Update the current element index in the write buffer according
// to the write size of the current iteration
write_idx += last_burst_of_col ? rows % num_elem_per_bank :
num_elem_per_bank;
}
} // end of li
} // end of matrix_index
} // end of repetition
}
#endif /* __MEMORY_TRANSFERS_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db.cpp | //==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <assert.h>
#include <fcntl.h>
#include <limits.h>
#include <memory.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <algorithm>
#include <chrono>
#include <fstream>
#include <functional>
#include <iostream>
#include <numeric>
#include <set>
#include <sstream>
#include <string>
#include <string_view>
#include <vector>
#include "db_utils/Date.hpp"
#include "db_utils/LikeRegex.hpp"
#include "dbdata.hpp"
#include "exception_handler.hpp"
using namespace sycl;
// include files depending on the query selected
#if (QUERY == 1)
#include "query1/query1_kernel.hpp"
bool DoQuery1(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency);
#elif (QUERY == 9)
#include "query9/query9_kernel.hpp"
bool DoQuery9(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency);
#elif (QUERY == 11)
#include "query11/query11_kernel.hpp"
bool DoQuery11(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency);
#elif (QUERY == 12)
#include "query12/query12_kernel.hpp"
bool DoQuery12(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency);
#endif
//
// print help for the program
//
void Help() {
std::cout << "USAGE:\n";
std::cout << "\t./db --dbroot=<database root directory> [...]\n";
std::cout << "\n";
std::cout << "Optional Arguments:\n";
std::cout << "\t--args=<comma separated arguments for query>"
" see the examples below\n";
std::cout << "\t--test enables testing of the query."
" This overrides the arguments to the query (--args) "
"and uses default input from TPCH documents\n";
std::cout << "\t--print print the query results to stdout\n";
std::cout << "\t--runs how many iterations of the query to run\n";
std::cout << "\t--help print this help message\n";
std::cout << "\n";
std::cout << "Examples:\n";
std::cout << "./db --dbroot=/path/to/database/files "
<< "[--test] [--args=<DATE,DELTA>]\n";
std::cout << "\t ./db --dbroot=/path/to/database/files --test\n";
std::cout << "\t ./db --dbroot=/path/to/database/files "
<< "--args=1998-12-01,90\n";
std::cout << "\n";
std::cout << "./db --dbroot=/path/to/database/files "
<< "[--test] [--args=<COLOUR>]\n";
std::cout << "\t ./db --dbroot=/path/to/database/files --test\n";
std::cout << "\t ./db --dbroot=/path/to/database/files --args=GREEN\n";
std::cout << "\n";
std::cout << "./db --dbroot=/path/to/database/files "
<< "[--test] [--args=<NATION>]\n";
std::cout << "\t ./db --dbroot=/path/to/database/files --test\n";
std::cout << "\t ./db --dbroot=/path/to/database/files "
<< "--args=GERMANY\n";
std::cout << "\n";
std::cout << "./db --dbroot=/path/to/database/files [--test] "
<< "[--args=<SHIPMODE1,SHIPMODE2,DATE>]\n";
std::cout << "\t ./db --dbroot=/path/to/database/files --test\n";
std::cout << "\t ./db --dbroot=/path/to/database/files "
<< "--args=MAIL,SHIP,1994-01-10\n";
std::cout << "\n";
}
//
// determine if a string starts with a prefix
//
bool StrStartsWith(std::string& str, std::string prefix) {
return str.find(prefix) == 0;
}
//
// main
//
int main(int argc, char* argv[]) {
// argument defaults
Database dbinfo;
std::string db_root_dir = ".";
std::string args = "";
unsigned int query = QUERY;
bool test_query = false;
#if defined(FPGA_EMULATOR)
unsigned int runs = 1;
#elif defined(FPGA_SIMULATOR)
unsigned int runs = 1;
#else
unsigned int runs = 5;
#endif
bool print_result = false;
bool need_help = false;
// parse the command line arguments
for (int i = 1; i < argc; i++) {
std::string arg(argv[i]);
if (arg == "--help" || arg == "-h") {
need_help = true;
} else {
std::string str_after_equals = arg.substr(arg.find("=") + 1);
if (StrStartsWith(arg, "--dbroot=")) {
db_root_dir = str_after_equals;
} else if (StrStartsWith(arg, "--query=")) {
query = atoi(str_after_equals.c_str());
} else if (StrStartsWith(arg, "--args=")) {
args = str_after_equals;
} else if (StrStartsWith(arg, "--test")) {
test_query = true;
} else if (StrStartsWith(arg, "--print")) {
print_result = true;
} else if (StrStartsWith(arg, "--runs")) {
#ifndef FPGA_EMULATOR
// for hardware, ensure at least two iterations to ensure we can run
// a 'warmup' iteration
runs = std::max(2, atoi(str_after_equals.c_str()) + 1);
#else
// for emulation and simulation, allow a single iteration and
// don't add a 'warmup' run
runs = std::max(1, atoi(str_after_equals.c_str()));
#endif
} else {
std::cout << "WARNING: ignoring unknown argument '" << arg << "'\n";
}
}
}
// print help if needed or asked
if (need_help) {
Help();
return 0;
}
// make sure the query is supported
if (!(query == 1 || query == 9 || query == 11 || query == 12)) {
std::cerr << "ERROR: unsupported query (" << query << "). "
<< "Only queries 1, 9, 11 and 12 are supported\n";
return 1;
}
if (query != QUERY) {
std::cerr << "ERROR: project not currently configured for query " << query
<< "\n";
std::cerr << "\trerun CMake using the command: 'cmake .. -DQUERY=" << query
<< "'\n";
return 1;
}
try {
// queue properties to enable profiling
auto props = property_list{property::queue::enable_profiling()};
#if FPGA_SIMULATOR
auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
auto selector = sycl::ext::intel::fpga_selector_v;
#else // #if FPGA_EMULATOR
auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif
// create the device queue
queue q(selector, fpga_tools::exception_handler, props);
device device = q.get_device();
std::cout << "Running on device: "
<< device.get_info<info::device::name>().c_str()
<< std::endl;
// parse the database files located in the 'db_root_dir' directory
bool success = dbinfo.Parse(db_root_dir);
if (!success) {
std::cerr << "ERROR: couldn't read the DB files\n";
return 1;
}
std::cout << "Database SF = " << kSF << "\n";
// make sure the parsed database files match the set scale factor
if (!dbinfo.ValidateSF()) {
std::cerr << "ERROR: could not validate the "
<< "scale factor of the parsed database files\n";
return 1;
}
// track timing information for each run
std::vector<double> total_latency(runs);
std::vector<double> kernel_latency(runs);
// run 'runs' iterations of the query
for (unsigned int run = 0; run < runs && success; run++) {
// run the selected query
if (query == 1) {
#if (QUERY == 1)
success = DoQuery1(q, dbinfo, db_root_dir, args,
test_query, print_result,
kernel_latency[run], total_latency[run]);
#endif
} else if (query == 9) {
// query9
#if (QUERY == 9)
success = DoQuery9(q, dbinfo, db_root_dir, args,
test_query, print_result,
kernel_latency[run], total_latency[run]);
#endif
} else if (query == 11) {
// query11
#if (QUERY == 11)
success = DoQuery11(q, dbinfo, db_root_dir, args,
test_query, print_result,
kernel_latency[run], total_latency[run]);
#endif
} else if (query == 12) {
// query12
#if (QUERY == 12)
success = DoQuery12(q, dbinfo, db_root_dir, args,
test_query, print_result,
kernel_latency[run], total_latency[run]);
#endif
} else {
std::cerr << "ERROR: unsupported query (" << query << ")\n";
return 1;
}
}
if (success) {
// don't analyze the runtime in emulation
#if !defined(FPGA_EMULATOR) && !defined(FPGA_SIMULATOR)
// compute the average total latency across all iterations,
// excluding the first 'warmup' iteration
double total_latency_avg =
std::accumulate(total_latency.begin() + 1, total_latency.end(), 0.0) /
(double)(runs - 1);
double kernel_latency_avg =
std::accumulate(kernel_latency.begin() + 1, kernel_latency.end(), 0.0) /
(double)(runs - 1);
// print the performance results
std::cout << "Processing time: " << total_latency_avg << " ms\n";
std::cout << "Kernel time: " << kernel_latency_avg << " ms\n";
std::cout << "Throughput: " << ((1 / kernel_latency_avg) * 1e3)
<< " queries/s\n";
#endif
std::cout << "PASSED\n";
} else {
std::cout << "FAILED\n";
return 1;
}
} catch (exception const& e) {
// Catches exceptions in the host code
std::cout << "Caught a SYCL host exception:\n" << e.what() << "\n";
// Most likely the runtime couldn't find FPGA hardware!
if (e.code().value() == CL_DEVICE_NOT_FOUND) {
std::cout << "If you are targeting an FPGA, please ensure that your "
"system has a correctly configured FPGA board.\n";
std::cout << "If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR.\n";
std::cout << "If you are targeting the FPGA simulator, compile with "
"-DFPGA_SIMULATOR.\n";
}
std::terminate();
}
return 0;
}
#if (QUERY == 1)
bool DoQuery1(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency) {
// NOTE: this is fixed based on the TPCH docs
Date date = Date("1998-12-01");
unsigned int DELTA = 90;
// parse the query arguments
if (!test && !args.empty()) {
std::stringstream ss(args);
std::string tmp;
std::getline(ss, tmp, ',');
DELTA = atoi(tmp.c_str());
} else {
if (!args.empty()) {
std::cout << "Testing query 1, therefore ignoring the '--args' flag\n";
}
}
// check query arguments
if (!(DELTA <= 120 && DELTA >= 60)) {
std::cerr << "ERROR: DELTA must be in the range [60,120]\n";
return false;
}
// compute query interval
Date low_date = date.PreviousDate(DELTA);
unsigned int low_date_compact = low_date.ToCompact();
std::cout << "Running Q1 within " << DELTA << " days of " << date.year << "-"
<< date.month << "-" << date.day << std::endl;
// the query output data
std::array<DBDecimal, kQuery1OutSize> sum_qty = {0}, sum_base_price = {0},
sum_disc_price = {0}, sum_charge = {0},
avg_qty = {0}, avg_price = {0},
avg_discount = {0}, count = {0};
// perform the query
bool success =
SubmitQuery1(q, dbinfo, low_date_compact, sum_qty, sum_base_price,
sum_disc_price, sum_charge, avg_qty, avg_price, avg_discount,
count, kernel_latency, total_latency);
if (success) {
// validate the results of the query, if requested
if (test) {
success = dbinfo.ValidateQ1(db_root_dir, sum_qty, sum_base_price,
sum_disc_price, sum_charge, avg_qty,
avg_price, avg_discount, count);
}
// print the results of the query, if requested
if (print) {
dbinfo.PrintQ1(sum_qty, sum_base_price, sum_disc_price, sum_charge,
avg_qty, avg_price, avg_discount, count);
}
}
return success;
}
#endif
#if (QUERY == 9)
bool DoQuery9(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency) {
// the default colour regex based on the TPCH documents
std::string colour = "GREEN";
// parse the query arguments
if (!test && !args.empty()) {
std::stringstream ss(args);
std::getline(ss, colour, ',');
} else {
if (!args.empty()) {
std::cout << "Testing query 9, therefore ignoring the '--args' flag\n";
}
}
// convert the colour regex to uppercase characters (convention)
transform(colour.begin(), colour.end(), colour.begin(), ::toupper);
std::cout << "Running Q9 with colour regex: " << colour << std::endl;
// the output of the query
std::array<DBDecimal, 25 * 2020> sum_profit;
// perform the query
bool success = SubmitQuery9(q, dbinfo, colour, sum_profit, kernel_latency,
total_latency);
if (success) {
// validate the results of the query, if requested
if (test) {
success = dbinfo.ValidateQ9(db_root_dir, sum_profit);
}
// print the results of the query, if requested
if (print) {
dbinfo.PrintQ9(sum_profit);
}
}
return success;
}
#endif
#if (QUERY == 11)
bool DoQuery11(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency) {
// the default nation, based on the TPCH documents
std::string nation = "GERMANY";
// parse the query arguments
if (!test && !args.empty()) {
std::stringstream ss(args);
std::getline(ss, nation, ',');
} else {
if (!args.empty()) {
std::cout << "Testing query 11, therefore ignoring the '--args' flag\n";
}
}
// convert the nation name to uppercase characters (convention)
transform(nation.begin(), nation.end(), nation.begin(), ::toupper);
std::cout << "Running Q11 for nation " << nation.c_str()
<< " (key=" << (int)(dbinfo.n.name_key_map[nation]) << ")"
<< std::endl;
// the query output
std::vector<DBIdentifier> partkeys(kPartTableSize);
std::vector<DBDecimal> partkey_values(kPartTableSize);
// perform the query
bool success = SubmitQuery11(q, dbinfo, nation, partkeys, partkey_values,
kernel_latency, total_latency);
if (success) {
// validate the results of the query, if requested
if (test) {
success = dbinfo.ValidateQ11(db_root_dir, partkeys, partkey_values);
}
// print the results of the query, if requested
if (print) {
dbinfo.PrintQ11(partkeys, partkey_values);
}
}
return success;
}
#endif
#if (QUERY == 12)
bool DoQuery12(queue& q, Database& dbinfo, std::string& db_root_dir,
std::string& args, bool test, bool print, double& kernel_latency,
double& total_latency) {
// the default query date and shipmodes, based on the TPCH documents
Date date = Date("1994-01-01");
std::string shipmode1 = "MAIL", shipmode2 = "SHIP";
// parse the query arguments
if (!test && !args.empty()) {
std::stringstream ss(args);
std::string tmp;
std::getline(ss, tmp, ',');
date = Date(tmp);
if (ss.good()) {
std::getline(ss, shipmode1, ',');
}
if (ss.good()) {
std::getline(ss, shipmode2, ',');
}
} else {
if (!args.empty()) {
std::cout << "Testing query 12, therefore ignoring the '--args' flag\n";
}
}
// check the arguments, date must be January 1 of some year
if (date.month != 1 || date.day != 1) {
std::cerr << "ERROR: Date must be first of January "
<< "in the given year (e.g. 1994-01-01)\n";
return false;
}
// compute the interval for the query
Date low_date = date;
Date high_date = Date(low_date.year + 1, low_date.month, low_date.day);
std::cout << "Running Q12 between years " << low_date.year << " and "
<< high_date.year << " for SHIPMODES " << shipmode1 << " and "
<< shipmode2 << std::endl;;
// the output of the query
std::array<DBDecimal, 2> high_line_count, low_line_count;
// perform the query
bool success = SubmitQuery12(
q, dbinfo, low_date.ToCompact(), high_date.ToCompact(),
ShipmodeStrToInt(shipmode1), ShipmodeStrToInt(shipmode2), high_line_count,
low_line_count, kernel_latency, total_latency);
if (success) {
// validate the results of the query, if requested
if (test) {
success =
dbinfo.ValidateQ12(db_root_dir, high_line_count, low_line_count);
}
// print the results of the query, if requested
if (print) {
dbinfo.PrintQ12(shipmode1, shipmode2, high_line_count, low_line_count);
}
}
return success;
}
#endif
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/dbdata.cpp | #include <assert.h>
#include <algorithm>
#include <cctype>
#include <cmath>
#include <iomanip>
#include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <stdio.h>
#include <vector>
#include "dbdata.hpp"
#include "db_utils/Date.hpp"
// choose a file separator based on the platform (Windows or Linux)
#if defined(WIN32) || defined(_WIN32) || defined(_MSC_VER)
constexpr char kSeparator = '\\';
#else
constexpr char kSeparator = '/';
#endif
//
// split a row in the database file on its separator ('|')
//
std::vector<std::string> SplitRowStr(const std::string& row) {
std::stringstream ss(row);
std::string segment;
std::vector<std::string> columns;
while (std::getline(ss, segment, '|')) {
columns.push_back(segment);
}
return columns;
}
//
// appends 'n' characters of a string to a vector
//
void AppendStringToCharVec(std::vector<char>& v, const std::string& str,
const unsigned int n) {
// append the 'n' characters, padding with null terminators ('\0')
const size_t str_n = str.size();
for (size_t i = 0; i < n; i++) {
v.push_back(i < str_n ? str[i] : '\0');
}
}
//
// convert a money string (i.e. '1209.12' dollars) to
// the internal 'cents' representation (i.e. '120912' cents)
//
DBDecimal MoneyFloatToCents(const std::string& money_float_str) {
// parse money string
std::istringstream ss(money_float_str);
std::string dollars_str, cents_str;
std::getline(ss, dollars_str, '.');
std::getline(ss, cents_str, '.');
DBDecimal dollars = atoi(dollars_str.c_str());
DBDecimal cents = atoi(cents_str.c_str());
// convert to fixed point format (i.e. in cents)
return dollars * 100 + cents;
}
//
// convert a SHIPMODE string to the internal representation (integer)
//
int ShipmodeStrToInt(std::string& shipmode_str) {
if (shipmode_str == "REG AIR") {
return 0;
} else if (shipmode_str == "AIR") {
return 1;
} else if (shipmode_str == "RAIL") {
return 2;
} else if (shipmode_str == "SHIP") {
return 3;
} else if (shipmode_str == "TRUCK") {
return 4;
} else if (shipmode_str == "MAIL") {
return 5;
} else if (shipmode_str == "FOB") {
return 6;
} else {
std::cerr << "WARNING: Found unknown SHIPMODE '" << shipmode_str
<< " defaulting to REG AIR\n";
return 0;
}
}
//
// check if two decimal values are within an epsilon of each other
//
bool AlmostEqual(double x, double y, double epsilon = 0.01f) {
return std::fabs(x - y) < epsilon;
}
//
// trim the leading whitespace of a std::string
//
void ltrim(std::string& s) {
s.erase(s.begin(), std::find_if(s.begin(), s.end(), [](int ch) {
return !std::isspace(ch);
}));
}
//
// trim the trailing whitespace of a std::string
//
void rtrim(std::string& s) {
s.erase(std::find_if(s.rbegin(), s.rend(), [](int ch) {
return !std::isspace(ch);
}).base(), s.end());
}
//
// trim leading and trailing whitespace of a string
//
void trim(std::string& s) {
ltrim(s);
rtrim(s);
}
//
// the main parsing function
// parses '*.tbl' files location in directory 'db_root_dir'
//
bool Database::Parse(std::string db_root_dir) {
std::cout << "Parsing database files in: " << db_root_dir << std::endl;
bool success = true;
// parse each table
success &= ParseLineItemTable(db_root_dir + kSeparator + "lineitem.tbl", l);
success &= ParseOrdersTable(db_root_dir + kSeparator +"orders.tbl", o);
success &= ParsePartsTable(db_root_dir + kSeparator + "part.tbl", p);
success &= ParseSupplierTable(db_root_dir + kSeparator + "supplier.tbl", s);
success &= ParsePartSupplierTable(db_root_dir + kSeparator + "partsupp.tbl", ps);
success &= ParseNationTable(db_root_dir + kSeparator + "nation.tbl", n);
return success;
}
//
// parse the LINEITEM table
//
bool Database::ParseLineItemTable(std::string f, LineItemTable& tbl) {
std::cout << "Parsing LINEITEM table from: " << f << "\n";
// populate data row by row (as presented in the file)
std::ifstream ifs(f);
std::string line;
tbl.rows = 0;
if (!ifs.is_open()) {
std::cout << "Failed to parse LINEITEM table\n";
return false;
}
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 16);
tbl.orderkey.push_back(std::stoll(column_data[0]));
tbl.partkey.push_back(std::stoll(column_data[1]));
tbl.suppkey.push_back(std::stoll(column_data[2]));
tbl.linenumber.push_back(std::stoll(column_data[3]));
tbl.quantity.push_back(std::stoll(column_data[4]));
tbl.extendedprice.push_back(MoneyFloatToCents(column_data[5]));
tbl.discount.push_back(MoneyFloatToCents(column_data[6]));
tbl.tax.push_back(MoneyFloatToCents(column_data[7]));
tbl.returnflag.push_back(column_data[8].at(0));
tbl.linestatus.push_back(column_data[9].at(0));
tbl.shipdate.push_back(Date(column_data[10]).ToCompact());
tbl.commitdate.push_back(Date(column_data[11]).ToCompact());
tbl.receiptdate.push_back(Date(column_data[12]).ToCompact());
AppendStringToCharVec(tbl.shipinstruct, column_data[13], 25);
tbl.shipmode.push_back(ShipmodeStrToInt(column_data[14]));
AppendStringToCharVec(tbl.comment, column_data[15], 44);
tbl.rows++;
}
for (size_t i = 0; i < kPaddingRows; i++) {
tbl.orderkey.push_back(0);
tbl.partkey.push_back(0);
tbl.suppkey.push_back(0);
tbl.linenumber.push_back(0);
tbl.quantity.push_back(0);
tbl.extendedprice.push_back(0);
tbl.discount.push_back(0);
tbl.tax.push_back(0);
tbl.returnflag.push_back(0);
tbl.linestatus.push_back(0);
tbl.shipdate.push_back(0);
tbl.commitdate.push_back(0);
tbl.receiptdate.push_back(0);
tbl.shipmode.push_back(0);
}
std::cout << "Finished parsing LINEITEM table with " << tbl.rows << " rows\n";
return true;
}
//
// parse the ORDERS table
//
bool Database::ParseOrdersTable(std::string f, OrdersTable& tbl) {
std::cout << "Parsing ORDERS table from: " << f << "\n";
// populate data row by row (as presented in the file)
std::ifstream ifs(f);
std::string line;
tbl.rows = 0;
if (!ifs.is_open()) {
std::cout << "Failed to parse ORDERS table\n";
return false;
}
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 9);
// store date for this row
tbl.orderkey.push_back(std::stoll(column_data[0]));
tbl.custkey.push_back(std::stoll(column_data[1]));
tbl.orderstatus.push_back(column_data[2][0]);
tbl.totalprice.push_back(MoneyFloatToCents(column_data[3]));
tbl.orderdate.push_back(Date(column_data[4]).ToCompact());
tbl.orderpriority.push_back((int)(column_data[5][0] - '0'));
AppendStringToCharVec(tbl.clerk, column_data[6], 15);
tbl.shippriority.push_back(std::stoi(column_data[7]));
AppendStringToCharVec(tbl.comment, column_data[8], 80);
tbl.rows++;
}
for (size_t i = 0; i < kPaddingRows; i++) {
tbl.orderkey.push_back(0);
tbl.custkey.push_back(0);
tbl.orderstatus.push_back(0);
tbl.totalprice.push_back(0);
tbl.orderdate.push_back(0);
tbl.orderpriority.push_back(0);
tbl.shippriority.push_back(0);
}
std::cout << "Finished parsing ORDERS table with " << tbl.rows << " rows\n";
return true;
}
//
// parse the PARTS table
//
bool Database::ParsePartsTable(std::string f, PartsTable& tbl) {
std::cout << "Parsing PARTS table from: " << f << "\n";
// populate data row by row (as presented in the file)
std::ifstream ifs(f);
std::string line;
tbl.rows = 0;
if (!ifs.is_open()) {
std::cout << "Failed to parse PARTS table\n";
return false;
}
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 9);
tbl.partkey.push_back(std::stoll(column_data[0]));
// formatting part name: no spaces, all uppercase
transform(column_data[1].begin(), column_data[1].end(),
column_data[1].begin(), ::toupper);
AppendStringToCharVec(tbl.name, column_data[1], 55);
AppendStringToCharVec(tbl.mfgr, column_data[2], 25);
AppendStringToCharVec(tbl.brand, column_data[3], 10);
AppendStringToCharVec(tbl.type, column_data[4], 25);
tbl.size.push_back(std::stoi(column_data[5]));
AppendStringToCharVec(tbl.container, column_data[6], 10);
tbl.retailprice.push_back(MoneyFloatToCents(column_data[7]));
AppendStringToCharVec(tbl.comment, column_data[8], 23);
tbl.rows++;
}
for (size_t i = 0; i < kPaddingRows; i++) {
tbl.partkey.push_back(0);
AppendStringToCharVec(tbl.name, "INVALID", 55);
}
std::cout << "Finished parsing PARTS table with " << tbl.rows << " rows\n";
return true;
}
//
// parse the SUPPLIER table
//
bool Database::ParseSupplierTable(std::string f, SupplierTable& tbl) {
std::cout << "Parsing SUPPLIER table from: " << f << "\n";
// populate data row by row (as presented in the file)
std::ifstream ifs(f);
std::string line;
tbl.rows = 0;
if (!ifs.is_open()) {
std::cout << "Failed to parse SUPPLIER table\n";
return false;
}
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 7);
tbl.suppkey.push_back(std::stoll(column_data[0]));
AppendStringToCharVec(tbl.name, column_data[1], 25);
AppendStringToCharVec(tbl.address, column_data[2], 40);
tbl.nationkey.push_back((unsigned char)(std::stoul(column_data[3])));
AppendStringToCharVec(tbl.phone, column_data[4], 15);
tbl.acctbal.push_back(MoneyFloatToCents(column_data[5]));
AppendStringToCharVec(tbl.comment, column_data[6], 101);
tbl.rows++;
}
for (size_t i = 0; i < kPaddingRows; i++) {
tbl.suppkey.push_back(0);
AppendStringToCharVec(tbl.name, "INVALID", 25);
tbl.nationkey.push_back(0);
tbl.acctbal.push_back(0);
}
std::cout << "Finished parsing SUPPLIER table with " << tbl.rows << " rows\n";
return true;
}
//
// parse the PARTSUPPLIER table
//
bool Database::ParsePartSupplierTable(std::string f, PartSupplierTable& tbl) {
std::cout << "Parsing PARTSUPPLIER table from: " << f << "\n";
// populate data row by row (as presented in the file)
std::ifstream ifs(f);
std::string line;
tbl.rows = 0;
if (!ifs.is_open()) {
std::cout << "Failed to parse PARTSUPPLIER table\n";
return false;
}
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 5);
tbl.partkey.push_back(std::stoll(column_data[0]));
tbl.suppkey.push_back(std::stoll(column_data[1]));
tbl.availqty.push_back(std::stoi(column_data[2]));
tbl.supplycost.push_back(MoneyFloatToCents(column_data[3]));
AppendStringToCharVec(tbl.comment, column_data[4], 199);
tbl.rows++;
}
for (size_t i = 0; i < kPaddingRows; i++) {
tbl.partkey.push_back(0);
tbl.suppkey.push_back(0);
tbl.availqty.push_back(0);
tbl.supplycost.push_back(0);
}
std::cout << "Finished parsing PARTSUPPLIER table with " << tbl.rows
<< " rows\n";
return true;
}
//
// parse the NATION table
//
bool Database::ParseNationTable(std::string f, NationTable& tbl) {
std::cout << "Parsing NATION table from: " << f << "\n";
// populate data row by row (as presented in the file)
std::ifstream ifs(f);
std::string line;
tbl.rows = 0;
if (!ifs.is_open()) {
std::cout << "Failed to parse NATION table\n";
return false;
}
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 4);
DBIdentifier nationkey = std::stoll(column_data[0]);
std::string nationname = column_data[1];
tbl.nationkey.push_back(nationkey);
// convention: all upper case
trim(nationname);
transform(nationname.begin(), nationname.end(), nationname.begin(),
::toupper);
AppendStringToCharVec(tbl.name, nationname, 25);
tbl.regionkey.push_back(std::stoll(column_data[2]));
AppendStringToCharVec(tbl.comment, column_data[3], 152);
// add entry into map
tbl.name_key_map[nationname] = nationkey;
tbl.key_name_map[nationkey] = nationname;
tbl.rows++;
}
std::cout << "Finished parsing NATION table with " << tbl.rows << " rows\n";
return true;
}
//
// Checks the size of each parsed table against the expected size based
// on the selected scale factor
//
bool Database::ValidateSF() {
bool ret = true;
if (l.rows != kLineItemTableSize) {
std::cerr << "LineItem table size has " << l.rows << " rows"
<< " when it should have " << kLineItemTableSize << "\n";
ret = false;
}
if (o.rows != kOrdersTableSize) {
std::cerr << "Orders table size has " << o.rows << " rows"
<< " when it should have " << kOrdersTableSize << "\n";
ret = false;
}
if (p.rows != kPartTableSize) {
std::cerr << "Parts table size has " << p.rows << " rows"
<< " when it should have " << kPartTableSize << "\n";
ret = false;
}
if (s.rows != kSupplierTableSize) {
std::cerr << "Supplier table size has " << s.rows << " rows"
<< " when it should have " << kSupplierTableSize << "\n";
ret = false;
}
if (ps.rows != kPartSupplierTableSize) {
std::cerr << "PartSupplier table size has " << ps.rows << " rows"
<< " when it should have " << kPartSupplierTableSize << "\n";
ret = false;
}
if (n.rows != kNationTableSize) {
std::cerr << "Nation table size has " << n.rows << " rows"
<< " when it should have " << kNationTableSize << "\n";
ret = false;
}
return ret;
}
//
// validate the results of Query 1
//
bool Database::ValidateQ1(std::string db_root_dir,
std::array<DBDecimal, 3 * 2>& sum_qty,
std::array<DBDecimal, 3 * 2>& sum_base_price,
std::array<DBDecimal, 3 * 2>& sum_disc_price,
std::array<DBDecimal, 3 * 2>& sum_charge,
std::array<DBDecimal, 3 * 2>& avg_qty,
std::array<DBDecimal, 3 * 2>& avg_price,
std::array<DBDecimal, 3 * 2>& avg_discount,
std::array<DBDecimal, 3 * 2>& count) {
std::cout << "Validating query 1 test results" << std::endl;
// populate date row by row (as presented in the file)
std::string path(db_root_dir + kSeparator + "answers" + kSeparator + "q1.out");
std::ifstream ifs(path);
bool valid = true;
if (!ifs.is_open()) {
std::cout << "Failed to open " << path << "\n";
return false;
}
// this will hold the line read from the input file
std::string line;
// do nothing with the first line, it is a header line
std::getline(ifs, line);
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 10);
char rf = column_data[0][0];
char ls = column_data[1][0];
double sum_qty_gold = std::stod(column_data[2]);
double sum_base_price_gold = std::stod(column_data[3]);
double sum_disc_price_gold = std::stod(column_data[4]);
double sum_charge_gold = std::stod(column_data[5]);
double avg_qty_gold = std::stod(column_data[6]);
double avg_price_gold = std::stod(column_data[7]);
double avg_disc_gold = std::stod(column_data[8]);
unsigned int count_order_gold = std::stoll(column_data[9]);
unsigned int rf_idx;
if (rf == 'R') {
rf_idx = 0;
} else if (rf == 'A') {
rf_idx = 1;
} else { // == 'N'
rf_idx = 2;
}
unsigned int ls_idx;
if (ls == 'O') {
ls_idx = 0;
} else { // == 'F'
ls_idx = 1;
}
unsigned int idx = ls_idx * 3 + rf_idx;
assert(idx < 6);
double sum_qty_res = (double)(sum_qty[idx]);
double sum_base_price_res = (double)(sum_base_price[idx]) / (100.00);
double sum_disc_price_res =
(double)(sum_disc_price[idx]) / (100.00 * 100.00);
double sum_charge_res =
(double)(sum_charge[idx]) / (100.00 * 100.00 * 100.00);
double avg_qty_res = (double)(avg_qty[idx]);
double avg_price_res = (double)(avg_price[idx]) / (100.00);
double avg_disc_res = (double)(avg_discount[idx]) / (100.00);
unsigned int count_order_res = count[idx];
if (!AlmostEqual(sum_qty_gold, sum_qty_res, 0.01f)) {
std::cerr << "ERROR: sum_qty for returnflag=" << rf
<< " and linestatus=" << ls << " (Expected=" << sum_qty_gold
<< ", Result=" << sum_qty_res << ")\n";
valid = false;
}
if (!AlmostEqual(sum_base_price_gold, sum_base_price_res, 0.01f)) {
std::cerr << "ERROR: sum_base_price for returnflag=" << rf
<< " and linestatus=" << ls
<< " (Expected=" << sum_base_price_gold
<< ", Result=" << sum_base_price_res << ")\n";
valid = false;
}
if (!AlmostEqual(sum_disc_price_gold, sum_disc_price_res, 0.01f)) {
std::cerr << "ERROR: sum_disc_price for returnflag=" << rf
<< " and linestatus=" << ls
<< " (Expected=" << sum_disc_price_gold
<< ", Result=" << sum_disc_price_res << ")\n";
valid = false;
}
if (!AlmostEqual(sum_charge_gold, sum_charge_res, 0.01f)) {
std::cerr << "ERROR: sum_charge for returnflag=" << rf
<< " and linestatus=" << ls << " (Expected=" << sum_charge_gold
<< ", Result=" << sum_charge_res << ")\n";
valid = false;
}
if (!AlmostEqual(avg_qty_gold, avg_qty_res, 1.0f)) {
std::cerr << "ERROR: avg_qty for returnflag=" << rf
<< " and linestatus=" << ls << " (Expected=" << avg_qty_gold
<< ", Result=" << avg_qty_res << ")\n";
valid = false;
}
if (!AlmostEqual(avg_price_gold, avg_price_res, 1.0f)) {
std::cerr << "ERROR: avg_price for returnflag=" << rf
<< " and linestatus=" << ls << " (Expected=" << avg_price_gold
<< ", Result=" << avg_price_res << ")\n";
valid = false;
}
if (!AlmostEqual(avg_disc_gold, avg_disc_res, 1.0f)) {
std::cerr << "ERROR: avg_disc for returnflag=" << rf
<< " and linestatus=" << ls << " (Expected=" << avg_disc_gold
<< ", Result=" << avg_disc_res << ")\n";
valid = false;
}
if (count_order_gold != count_order_res) {
std::cerr << "ERROR: count for returnflag=" << rf
<< " and linestatus=" << ls << " (Expected=" << count_order_gold
<< ", Result=" << count_order_res << ")\n";
valid = false;
}
}
return valid;
}
//
// validate the results of Query 9
//
bool Database::ValidateQ9(std::string db_root_dir,
std::array<DBDecimal, 25 * 2020>& sum_profit) {
std::cout << "Validating query 9 test results" << std::endl;
// populate date row by row (as presented in the file)
std::string path(db_root_dir + kSeparator + "answers" + kSeparator + "q9.out");
std::ifstream ifs(path);
std::string line;
bool valid = true;
if (!ifs.is_open()) {
std::cout << "Failed to open " << path << "\n";
return false;
}
// do nothing with the first line, it is a header line
std::getline(ifs, line);
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 3);
std::string nationname_gold = column_data[0];
trim(nationname_gold);
transform(nationname_gold.begin(), nationname_gold.end(),
nationname_gold.begin(), ::toupper);
assert(n.name_key_map.find(nationname_gold) != n.name_key_map.end());
unsigned char nationkey_gold = n.name_key_map[nationname_gold];
unsigned int year_gold = std::stoi(column_data[1]);
double sum_profit_gold = std::stod(column_data[2]);
double sum_profit_res =
(double)(sum_profit[year_gold * 25 + nationkey_gold]) / (100.0 * 100.0);
if (!AlmostEqual(sum_profit_gold, sum_profit_res, 0.01f)) {
std::cerr << "ERROR: sum_profit for " << nationname_gold << " in "
<< year_gold << " did not match (Expected=" << sum_profit_gold
<< ", Result=" << sum_profit_res << ")\n";
valid = false;
}
}
return valid;
}
//
// validate the results of Query 11
//
bool Database::ValidateQ11(std::string db_root_dir,
std::vector<DBIdentifier>& partkeys,
std::vector<DBDecimal>& partkey_values) {
std::cout << "Validating query 11 test results" << std::endl;
// populate date row by row (as presented in the file)
std::string path(db_root_dir + kSeparator + "answers" + kSeparator + "q11.out");
std::ifstream ifs(path);
std::string line;
size_t i = 0;
if (!ifs.is_open()) {
std::cout << "Failed to open " << path << "\n";
return false;
}
bool valid = true;
// do nothing with the first line, it is a header line
std::getline(ifs, line);
while (std::getline(ifs, line)) {
// split row into column strings by separator ('|')
std::vector<std::string> column_data = SplitRowStr(line);
assert(column_data.size() == 2);
assert(i < kPartTableSize);
DBIdentifier partkey_gold = std::stoll(column_data[0]);
double value_gold = std::stod(column_data[1]);
DBIdentifier partkey_res = partkeys[i];
double value_res = (double)(partkey_values[i]) / (100.00);
if (partkey_gold != partkey_res) {
std::cerr << "ERROR: partkeys at index " << i << " do not match "
<< "(Expected=" << partkey_gold << ", Result=" << partkey_res
<< ")\n";
valid = false;
}
if (!AlmostEqual(value_gold, value_res, 0.01f)) {
std::cerr << "ERROR: value at index " << i << " do not match "
<< "(Expected=" << value_gold << ", Result=" << value_res
<< ")\n";
valid = false;
}
i++;
}
assert(i > 0);
return valid;
}
//
// validate the results of Query 12
//
bool Database::ValidateQ12(std::string db_root_dir,
std::array<DBDecimal, 2> high_line_count,
std::array<DBDecimal, 2> low_line_count) {
std::cout << "Validating query 12 test results" << std::endl;
// populate date row by row (as presented in the file)
std::string path(db_root_dir + kSeparator + "answers" + kSeparator + "q12.out");
std::ifstream ifs(path);
std::vector<std::string> column_data;
std::string line;
bool valid = true;
if (!ifs.is_open()) {
std::cout << "Failed to open " << path << "\n";
return false;
}
// do nothing with the first line, it is a header line
std::getline(ifs, line);
// MAIL shipmode
std::getline(ifs, line);
column_data = SplitRowStr(line);
assert(column_data.size() == 3);
DBDecimal mail_high_count_gold = std::stoll(column_data[1]);
DBDecimal mail_low_count_gold = std::stoll(column_data[2]);
if (mail_high_count_gold != high_line_count[0]) {
std::cerr << "ERROR: MAIL high_count (Expected=" << mail_high_count_gold
<< ", Result=" << high_line_count[0] << ")\n";
valid = false;
}
if (mail_low_count_gold != low_line_count[0]) {
std::cerr << "ERROR: MAIL low_count (Expected=" << mail_low_count_gold
<< ", Result=" << low_line_count[0] << ")\n";
valid = false;
}
// SHIP shipmode
std::getline(ifs, line);
column_data = SplitRowStr(line);
assert(column_data.size() == 3);
DBDecimal ship_high_count_gold = std::stoll(column_data[1]);
DBDecimal ship_low_count_gold = std::stoll(column_data[2]);
if (ship_high_count_gold != high_line_count[1]) {
std::cerr << "ERROR: SHIP high_count (Expected=" << ship_high_count_gold
<< ", Result=" << high_line_count[1] << ")\n";
valid = false;
}
if (ship_low_count_gold != low_line_count[1]) {
std::cerr << "ERROR: SHIP low_count (Expected=" << ship_low_count_gold
<< ", Result=" << low_line_count[1] << ")\n";
valid = false;
}
return valid;
}
//
// print the results of Query 1
//
void Database::PrintQ1(std::array<DBDecimal, 3 * 2>& sum_qty,
std::array<DBDecimal, 3 * 2>& sum_base_price,
std::array<DBDecimal, 3 * 2>& sum_disc_price,
std::array<DBDecimal, 3 * 2>& sum_charge,
std::array<DBDecimal, 3 * 2>& avg_qty,
std::array<DBDecimal, 3 * 2>& avg_price,
std::array<DBDecimal, 3 * 2>& avg_discount,
std::array<DBDecimal, 3 * 2>& count) {
// line status (ls) and return flag (rf)
const std::array<char, 2> ls = {'O', 'F'};
const std::array<char, 3> rf = {'R', 'A', 'N'};
// print the header
std::cout << "l|l|sum_qty|sum_base_price|sum_disc_price|"
"sum_charge|avg_qty|avg_price|avg_disc|count_order\n";
// Copy old state of cout
std::ios oldState(nullptr);
oldState.copyfmt(std::cout);
// Edit the output format of cout
std::cout << std::fixed << std::setprecision(2);
// print the results
for (int ls_idx = 0; ls_idx < 2; ls_idx++) {
for (int rf_idx = 0; rf_idx < 3; rf_idx++) {
int i = ls_idx * 3 + rf_idx;
std::cout << rf[rf_idx] << "|" << ls[ls_idx] << "|" << sum_qty[i] << "|"
<< (double)(sum_base_price[i]) / 100.0 << "|"
<< (double)(sum_disc_price[i]) / (100.00 * 100.00) << "|"
<< (double)(sum_charge[i]) / (100.00 * 100.00 * 100.00) << "|"
<< avg_qty[i] << "|" << (double)(avg_price[i]) / 100.0 << "|"
<< (double)(avg_discount[i]) / 100.0 << "|" << count[i] << "\n";
}
}
// Restore the output format of cout
std::cout.copyfmt(oldState);
}
//
// print the results of Query 9
//
void Database::PrintQ9(std::array<DBDecimal, 25 * 2020>& sum_profit) {
// row of Q9 output for local sorting
struct Row {
Row(std::string& nation, int year, DBDecimal sum_profit)
: nation(nation), year(year), sum_profit(sum_profit) {}
std::string nation;
int year;
DBDecimal sum_profit;
void print() {
std::cout << nation << "|" << year << "|"
<< (double)(sum_profit) / (100.0 * 100.0) << "\n";
}
};
// create the rows
std::vector<Row> outrows;
for (unsigned char nat = 0; nat < kNationTableSize; nat++) {
std::string nation_name = n.key_name_map[nat];
for (int y = 1992; y <= 1998; y++) {
outrows.push_back(Row(nation_name, y, sum_profit[y * 25 + nat]));
}
}
// sort rows by year
std::sort(outrows.begin(), outrows.end(),
[](const Row& a, const Row& b) -> bool {
return a.year > b.year;
});
// sort rows by nation
// stable_sort() preserves the order of the previous sort
std::stable_sort(outrows.begin(), outrows.end(),
[](const Row& a, const Row& b) -> bool {
return a.nation < b.nation;
});
// print the header
std::cout << "nation|o_year|sum_profit\n";
// Copy old state of cout
std::ios oldState(nullptr);
oldState.copyfmt(std::cout);
// Edit the output format of cout
std::cout << std::fixed << std::setprecision(2);
// print the results
for (int i = 0; i < outrows.size(); i++) {
outrows[i].print();
}
// Restore the output format of cout
std::cout.copyfmt(oldState);
}
//
// print the results of Query 11
//
void Database::PrintQ11(std::vector<DBIdentifier>& partkeys,
std::vector<DBDecimal>& partkey_values) {
// print the header
std::cout << "ps_partkey|value\n";
// Copy old state of cout
std::ios oldState(nullptr);
oldState.copyfmt(std::cout);
// Edit the output format of cout
std::cout << std::fixed << std::setprecision(2);
// print the results
for (int i = 0; i < partkeys.size(); i++) {
std::cout << partkeys[i] << "|" << (double)(partkey_values[i]) / (100.00)
<< "\n";
}
// Restore the output format of cout
std::cout.copyfmt(oldState);
}
//
// print the results of Query 12
//
void Database::PrintQ12(std::string& SM1, std::string& SM2,
std::array<DBDecimal, 2> high_line_count,
std::array<DBDecimal, 2> low_line_count) {
// print the header
std::cout << "l_shipmode|high_line_count|low_line_count\n";
// Copy old state of cout
std::ios oldState(nullptr);
oldState.copyfmt(std::cout);
// Edit the output format of cout
std::cout << std::fixed;
// print the results
std::cout << SM1 << "|" << high_line_count[0] << "|" << low_line_count[0]
<< "\n";
std::cout << SM2 << "|" << high_line_count[1] << "|" << low_line_count[1]
<< "\n";
// Restore the output format of cout
std::cout.copyfmt(oldState);
} | cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/dbdata.hpp | #ifndef __DBDATA_HPP__
#define __DBDATA_HPP__
#pragma once
#include <array>
#include <string>
#include <type_traits>
#include <unordered_map>
#include <vector>
// database types
using DBIdentifier = unsigned int;
using DBUint = unsigned int;
using DBInt = unsigned int;
using DBDecimal = long long;
using DBDate = unsigned int;
// Set the scale factor
//
// The default (and only option) scale factor for
// emulation is 0.01; a scale factor of 1 for emulation
// takes far too long.
//
// The default scale factor for hardware is 1. However,
// the SF_SMALL flag allows the hardware design to be compiled
// with a scale factor of 0.01
#if defined(FPGA_EMULATOR) || defined(FPGA_SIMULATOR) || defined(SF_SMALL)
constexpr float kSF = 0.01f;
#else
constexpr float kSF = 1.0f;
#endif
// add some padding rows to the end of each table.
// this avoids having to predicate global memory when the access granularity
// is not a multiple of the total number of rows.
// 16 was chosen because it is the largest access granularity
constexpr size_t kPaddingRows = 16;
// ensure the selected scale factor is supported
static_assert((kSF == 0.01f || kSF == 1.0f), "Unsupported Scale Factor (kSF)");
// table sizes based on the Scale Factor (kSF)
constexpr int kPartTableSize = kSF * 200000;
constexpr int kPartSupplierTableSize = kSF * 800000;
constexpr int kOrdersTableSize = kSF * 1500000;
constexpr int kSupplierTableSize = kSF * 10000;
constexpr int kCustomerTableSize = kSF * 150000;
// LINEITEM table is not a strict multiple of kSF
constexpr int LineItemTableSizeFnc() {
if (kSF == 0.01f) {
return 60175;
} else if (kSF == 1.0f) {
return 6001215;
} else {
return 0; // error, should be caught by kSF static_assert
}
}
constexpr int kLineItemTableSize = LineItemTableSizeFnc();
constexpr int kNationTableSize = 25;
constexpr int kRegionTableSize = 5;
constexpr int kLineStatusSize = 2;
constexpr int kReturnFlagSize = 3;
constexpr int kQuery1OutSize = kReturnFlagSize * kLineStatusSize;
// helpers
DBDate DateFromString(std::string& date_str);
int ShipmodeStrToInt(std::string& shipmode_str);
// LINEITEM table
struct LineItemTable {
std::vector<DBIdentifier> orderkey;
std::vector<DBIdentifier> partkey;
std::vector<DBIdentifier> suppkey;
std::vector<DBInt> linenumber;
std::vector<DBDecimal> quantity;
std::vector<DBDecimal> extendedprice;
std::vector<DBDecimal> discount;
std::vector<DBDecimal> tax;
std::vector<char> returnflag;
std::vector<char> linestatus;
std::vector<DBDate> shipdate;
std::vector<DBDate> commitdate;
std::vector<DBDate> receiptdate;
std::vector<char> shipinstruct;
std::vector<int> shipmode;
std::vector<char> comment;
size_t rows;
};
// ORDERS table
struct OrdersTable {
std::vector<DBIdentifier> orderkey;
std::vector<DBIdentifier> custkey;
std::vector<char> orderstatus;
std::vector<DBDecimal> totalprice;
std::vector<DBDate> orderdate;
std::vector<int> orderpriority;
std::vector<char> clerk;
std::vector<int> shippriority;
std::vector<char> comment;
size_t rows;
};
// PARTS table
struct PartsTable {
std::vector<DBIdentifier> partkey;
std::vector<char> name;
std::vector<char> mfgr;
std::vector<char> brand;
std::vector<char> type;
std::vector<int> size;
std::vector<char> container;
std::vector<DBDecimal> retailprice;
std::vector<char> comment;
size_t rows;
};
// SUPPLIER table
struct SupplierTable {
std::vector<DBIdentifier> suppkey;
std::vector<char> name;
std::vector<char> address;
std::vector<unsigned char> nationkey;
std::vector<char> phone;
std::vector<DBDecimal> acctbal;
std::vector<char> comment;
size_t rows;
};
// PARTSUPP table
struct PartSupplierTable {
std::vector<DBIdentifier> partkey;
std::vector<DBIdentifier> suppkey;
std::vector<int> availqty;
std::vector<DBDecimal> supplycost;
std::vector<char> comment;
size_t rows;
};
// NATION table
struct NationTable {
std::vector<DBIdentifier> nationkey;
std::vector<char> name;
std::vector<DBIdentifier> regionkey;
std::vector<char> comment;
std::unordered_map<std::string, unsigned char> name_key_map;
std::array<std::string, kNationTableSize> key_name_map;
size_t rows;
};
// the database
struct Database {
LineItemTable l;
OrdersTable o;
PartsTable p;
SupplierTable s;
PartSupplierTable ps;
NationTable n;
bool Parse(std::string db_root_dir);
// validation functions
bool ValidateSF();
bool ValidateQ1(std::string db_root_dir,
std::array<DBDecimal, 3 * 2>& sum_qty,
std::array<DBDecimal, 3 * 2>& sum_base_price,
std::array<DBDecimal, 3 * 2>& sum_disc_price,
std::array<DBDecimal, 3 * 2>& sum_charge,
std::array<DBDecimal, 3 * 2>& avg_qty,
std::array<DBDecimal, 3 * 2>& avg_price,
std::array<DBDecimal, 3 * 2>& avg_discount,
std::array<DBDecimal, 3 * 2>& count);
bool ValidateQ9(std::string db_root_dir,
std::array<DBDecimal, 25 * 2020>& sum_profit);
bool ValidateQ11(std::string db_root_dir, std::vector<DBIdentifier>& partkeys,
std::vector<DBDecimal>& partkey_values);
bool ValidateQ12(std::string db_root_dir,
std::array<DBDecimal, 2> high_line_count,
std::array<DBDecimal, 2> low_line_count);
// print functions
void PrintQ1(std::array<DBDecimal, 3 * 2>& sum_qty,
std::array<DBDecimal, 3 * 2>& sum_base_price,
std::array<DBDecimal, 3 * 2>& sum_disc_price,
std::array<DBDecimal, 3 * 2>& sum_charge,
std::array<DBDecimal, 3 * 2>& avg_qty,
std::array<DBDecimal, 3 * 2>& avg_price,
std::array<DBDecimal, 3 * 2>& avg_discount,
std::array<DBDecimal, 3 * 2>& count);
void PrintQ9(std::array<DBDecimal, 25 * 2020>& sum_profit);
void PrintQ11(std::vector<DBIdentifier>& partkeys,
std::vector<DBDecimal>& partkey_values);
void PrintQ12(std::string& SM1, std::string& SM2,
std::array<DBDecimal, 2> high_line_count,
std::array<DBDecimal, 2> low_line_count);
private:
bool ParseLineItemTable(std::string f, LineItemTable& tbl);
bool ParseOrdersTable(std::string f, OrdersTable& tbl);
bool ParsePartsTable(std::string f, PartsTable& tbl);
bool ParseSupplierTable(std::string f, SupplierTable& tbl);
bool ParsePartSupplierTable(std::string f, PartSupplierTable& tbl);
bool ParseNationTable(std::string f, NationTable& tbl);
};
#endif /* __DBDATA_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Date.hpp | #ifndef __DATE_HPP__
#define __DATE_HPP__
#pragma once
#include <fstream>
#include <sstream>
#include <string>
//
// Class for storing and computing operations on a date
//
class Date {
public:
Date(const int y, const int m, const int d) : year(y), month(m), day(d) {}
Date(std::string date_str) {
// parse money string
std::istringstream ss(date_str);
std::string year_str, month_str, day_str;
std::getline(ss, year_str, '-');
std::getline(ss, month_str, '-');
std::getline(ss, day_str, '-');
year = atoi(year_str.c_str());
month = atoi(month_str.c_str());
day = atoi(day_str.c_str());
}
//
// determine if the date is valid
//
bool Valid() const {
if (year <= 0 || month > 12 || month <= 0 || day > 31 || day <= 0) {
return false;
}
if (month == 4 || month == 6 || month == 9 || month == 11) {
if (day > 30) {
return false;
}
} else if (month == 1 || month == 3 || month == 5 || month == 7 ||
month == 8 || month == 10 || month == 12) {
if (day > 31) {
return false;
}
} else /* month == 4 (February) */ {
if (day > 29) {
return false;
} else if (day == 29 && !((((year % 4 == 0) && (year % 100 != 0)) ||
(year % 400 == 0)))) {
return false;
}
}
return true;
}
//
// get the previous day
//
Date PreviousDay(const Date& d) {
if (!d.Valid()) {
return d;
} else {
auto newDate = Date(d.year, d.month, d.day - 1);
if (newDate.Valid()) return newDate;
newDate = Date(d.year, d.month - 1, 31);
if (newDate.Valid()) return newDate;
newDate = Date(d.year, d.month - 1, 30);
if (newDate.Valid()) return newDate;
newDate = Date(d.year, d.month - 1, 29);
if (newDate.Valid()) return newDate;
newDate = Date(d.year, d.month - 1, 28);
if (newDate.Valid()) return newDate;
newDate = Date(d.year - 1, 12, 31);
if (newDate.Valid()) return newDate;
newDate = Date(31, 12, d.year - 1);
return newDate;
}
}
//
// get the next day
//
Date NextDay(const Date& d) {
if (!d.Valid()) {
return d;
} else {
auto newDate = Date(d.year, d.month, d.day + 1);
if (newDate.Valid()) return newDate;
newDate = Date(d.year, d.month + 1, 1);
if (newDate.Valid()) return newDate;
newDate = Date(d.year + 1, 1, 1);
if (newDate.Valid()) return newDate;
return newDate;
}
}
//
// get a date a certain number of days in the future
//
Date LaterDate(const int days) {
Date newDate = *this;
for (unsigned int i = 0; i < days; i++) {
newDate = NextDay(newDate);
}
return newDate;
}
//
// get a date a certain number of days in the past
//
Date PreviousDate(const int days) {
Date newDate = *this;
for (unsigned int i = 0; i < days; i++) {
newDate = PreviousDay(newDate);
}
return newDate;
}
Date operator++() {
Date d = *this;
*this = NextDay(d);
return d;
}
Date operator++(int) {
*this = NextDay(*this);
return *this;
}
Date operator--() {
Date d = *this;
*this = PreviousDay(d);
return d;
}
Date operator--(int) {
*this = PreviousDay(*this);
return *this;
}
//
// Date in a compressed format
// DAY bits = ceil(lg(31)) = 5
// MONTH bits = ceil(lg(12)) = 4
// YEAR bits = 32-5-4 = 23
// DATE format is:
// 32 8 4 0
// YYYYYYYYYYYYYYYYYYYYYYYMMMMDDDDD
//
unsigned int ToCompact() const {
unsigned int y = (unsigned int)year;
unsigned int m = (unsigned int)month;
unsigned int d = (unsigned int)day;
return (((y)&0x07FFFFF) << 9) | (((m)&0x000F) << 5) | ((d)&0x001F);
}
void FromCompact(const unsigned int date) {
year = ((date >> 9) & 0x07FFFFF);
month = ((date >> 5) & 0x000F);
day = (date & 0x001F);
}
int year, month, day;
};
#endif /* __DATE_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/LikeRegex.hpp | #ifndef __LIKEREGEX_HPP__
#define __LIKEREGEX_HPP__
#pragma once
#include <array>
#include <type_traits>
//
// Regex LIKE engine that can match: *WORD*, *WORD and WORD*
// where the string has max_str_length words or length at most max_word_length.
// If words are shorter than max_word_length, they are padded with '\0'.
//
template <unsigned int max_word_length, unsigned int max_str_length>
class LikeRegex {
// static asserts
static_assert(max_word_length < max_str_length,
"The maximum word length must be less than the maximum string length");
static_assert(max_word_length > 0,
"The word must have a positive non-zero maximum length");
static_assert(max_str_length > 0,
"The string must have a positive non-zero maximum length");
public:
void Match() {
// find true length of string
str_true_len = GetStrLength();
// find true length of WORD
word_true_len = GetWordLength();
// determine if there is a match
match_start_idx = max_str_length;
match_end = max_str_length;
#pragma unroll
for (unsigned int i = 0; i < max_str_length; i++) {
// check if str[i:i+max_word_length] matches word
bool matches = true;
#pragma unroll
for (unsigned int j = 0; j < max_word_length; j++) {
if ((i + j < max_str_length) && (word[j] != '\0') &&
(str[i + j] != '\0') && (word[j] != str[i + j])) {
matches = false;
break;
}
}
if (matches && (i < str_true_len) &&
((i + word_true_len) <= str_true_len)) {
match_start_idx = i;
match_end = i + word_true_len;
}
}
}
// determines the true length of the input string (null terminated)
unsigned int GetStrLength() const {
unsigned int len = 0;
#pragma unroll
for (unsigned int i = 0; i < max_str_length; i++) {
if (len == 0 && str[i] == '\0') {
len = i;
}
}
return len;
}
// determines the true length of the regex word (null terminated)
unsigned int GetWordLength() const {
unsigned int len = 0;
#pragma unroll
for (unsigned int i = 0; i < max_word_length; i++) {
if (len == 0 && word[i] == '\0') {
len = i;
}
}
return len;
}
// does the string contain the word (i.e. matches %WORD%)
bool Contains() {
return (match_start_idx < max_str_length) && (match_end < max_str_length);
}
// does the string start with the word (i.e. matches WORD%)
bool AtStart() {
return match_start_idx == 0;
}
// does the string end with the word (i.e. matches %WORD)
bool AtEnd() {
return match_end == str_true_len;
}
char word[max_word_length];
char str[max_str_length];
unsigned int match_start_idx, match_end;
unsigned int word_true_len, str_true_len;
};
#endif /* __LIKEREGEX_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/MapJoin.hpp | #ifndef __MAPJOIN_HPP__
#define __MAPJOIN_HPP__
#pragma once
#include <functional>
#include <set>
#include <tuple>
#include <type_traits>
#include <utility>
#include "Unroller.hpp"
#include "Tuple.hpp"
#include "StreamingData.hpp"
//
// MapJoin implementation
//
template<typename MapType, typename T2Pipe, typename T2Data, int t2_win_size,
typename JoinPipe, typename JoinType>
void MapJoin(MapType map_data[], bool map_valid[]) {
//////////////////////////////////////////////////////////////////////////////
// static asserts
static_assert(t2_win_size > 0,
"Table 2 window size must be positive and non-zero");
static_assert(
std::is_same<unsigned int, decltype(T2Data().PrimaryKey())>::value,
"T2Data must have 'PrimaryKey()' function that returns an 'unsigned "
"int'");
static_assert(std::is_same<bool, decltype(T2Data().valid)>::value,
"T2Data must have a 'valid' boolean member");
static_assert(std::is_same<bool, decltype(JoinType().valid)>::value,
"JoinType must have a 'valid' boolean member");
//////////////////////////////////////////////////////////////////////////////
bool done = false;
while (!done) {
// read from the input pipe
bool valid_pipe_read;
StreamingData<T2Data, t2_win_size> in_data = T2Pipe::read(valid_pipe_read);
// check if the producer is done
done = in_data.done && valid_pipe_read;
if (!done && valid_pipe_read) {
// join the input data windows into output data
StreamingData<JoinType, t2_win_size> join_data(false, true);
// initialize all outputs to false
UnrolledLoop<0, t2_win_size>([&](auto i) {
join_data.data.template get<i>().valid = false;
});
// check for match in the map and join if valid
UnrolledLoop<0, t2_win_size>([&](auto j) {
const bool t2_win_valid = in_data.data.template get<j>().valid;
const unsigned int t2_key =
in_data.data.template get<j>().PrimaryKey();
if (t2_win_valid && map_valid[t2_key]) {
// NOTE: order below important if Join() overrides valid
join_data.data.template get<j>().valid = true;
join_data.data.template get<j>().Join(map_data[t2_key],
in_data.data.template get<j>());
}
});
// write out joined data
JoinPipe::write(join_data);
}
}
}
#endif /* __MAPJOIN_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Accumulator.hpp | #ifndef __ACCUMULATOR_HPP__
#define __ACCUMULATOR_HPP__
#pragma once
#include <limits>
#include <type_traits>
#include "Tuple.hpp"
#include "Unroller.hpp"
///////////////////////////////////////////////////////
//
// Register-based accumulator
// Accumulates into size bins of type StorageType
//
template <typename StorageType, int size, typename IndexType = unsigned int>
class RegisterAccumulator {
// static asserts
static_assert(std::is_arithmetic<StorageType>::value,
"StorageType must be arithmetic to support accumulation");
static_assert(std::is_integral<IndexType>::value,
"IndexType must be an integral type");
static_assert(std::numeric_limits<IndexType>::max() >= (size - 1),
"IndexType must be large enough to index the entire array");
public:
// initialize the memory to 0
void Init() {
UnrolledLoop<0, size>([&](auto i) {
registers.template get<i>() = 0;
});
}
// accumulate 'value' into register 'index' (i.e. registers[index] += value)
void Accumulate(IndexType index, StorageType value) {
UnrolledLoop<0, size>([&](auto i) {
registers.template get<i>() += (i == index) ? value : 0;
});
}
// template version of accumulate
template <IndexType index>
void Accumulate(StorageType value) {
static_assert(index < size, "index is out of range");
registers.template get<index>() += value;
}
// get the value of memory at 'index'
StorageType Get(IndexType index) {
StorageType ret;
UnrolledLoop<0, size>([&](auto i) {
if (i == index) {
ret = registers.template get<i>();
}
});
return ret;
}
// template version of get
template <IndexType index>
StorageType Get() {
static_assert(index < size, "index is out of range");
return registers.template get<index>();
}
// register storage using tuples
NTuple<size, StorageType> registers;
};
///////////////////////////////////////////////////////
#endif /* __ACCUMULATOR_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/ShannonIterator.hpp | #ifndef __SHANNONITERATOR_HPP__
#define __SHANNONITERATOR_HPP__
#pragma once
#include <array>
#include <type_traits>
#include "Tuple.hpp"
#include "Unroller.hpp"
//
// This class is intended to improve iterator performance for the FPGA.
// It optimizes the critical by precomputing the iterator change and comparison
// and stores the results in a shift register.
// This process is called 'Shannonization'.
//
// Templated on the following variables:
// CounterType - the datatype to use for the counter
// default = size_t
// shift_register_size - the size of the shift register to use
// step_size - the amount to change the counters on each step (e.g.
// i += step_size)
// default = 1
// increment - boolean where true=increment, false=decrement
// default = true
// inclusive - whether the end of the range is include or not (e.g.
// i < 100 vs i <= 100)
// default = false
//
template <typename CounterType, int shift_register_size,
CounterType step_size = 1, bool increment = true,
bool inclusive = false>
class ShannonIterator {
// static asserts
static_assert(std::is_integral<CounterType>::value,
"CounterType must be an integral type");
static_assert(shift_register_size > 1,
"shift_register_size must great than"
"one (otherwise just use a normal iterator!)");
static_assert(step_size > 0,
"step_size must great than 0"
"step_size==0: does no work,"
"step_size<0: use the increment template instead");
public:
//
// Constructor
// Counts from start...end, inclusive/exclusive depends on inclusive template
//
ShannonIterator(CounterType start, CounterType end) : end_(end) {
// initialize the counter shift register
UnrolledLoop<0, kCountShiftRegisterSize>([&](auto i) {
if (increment) {
counter_.template get<i>() = start + (i * step_size);
} else {
counter_.template get<i>() = start - (i * step_size);
}
});
// initialize the in range boolean shift register
UnrolledLoop<0, kInRangeShiftRegisterSize>([&](auto i) {
CounterType val = counter_.template get<i>();
// depends on increment and inclusive template parameters,
// which are determined at compile time)
if (increment) {
inrange_.template get<i>() = inclusive ? (val <= end_) : (val < end_);
} else {
inrange_.template get<i>() = inclusive ? (val >= end_) : (val > end_);
}
});
}
//
// move the iterator, return whether the counter is in range
//
bool Step() {
// shift the in range checks
UnrolledLoop<0, kInRangeShiftRegisterSize - 1>([&](auto i) {
inrange_.template get<i>() = inrange_.template get<i + 1>();
});
// compute the new in range check
if (increment) {
inrange_.last() =
inclusive ? (counter_.last() <= end_) : (counter_.last() < end_);
} else {
inrange_.last() =
inclusive ? (counter_.last() >= end_) : (counter_.last() > end_);
}
// shift the counters
UnrolledLoop<0, shift_register_size - 1>([&](auto i) {
counter_.template get<i>() = counter_.template get<i + 1>();
});
// compute the new counter
if (increment) {
counter_.last() += step_size;
} else {
counter_.last() -= step_size;
}
// return whether the index is currently in range (post-increment)
return InRange();
}
//
// returns whether the given counter is in range
// defaults to the head counter
//
template <int i = 0>
bool InRange() {
static_assert(i < kInRangeShiftRegisterSize, "i out of range");
return inrange_.template get<i>();
}
//
// returns the given counter value
// defaults to the head counter
//
template <int i = 0>
CounterType Index() {
static_assert(i < kCountShiftRegisterSize, "i out of range");
return counter_.template get<i>();
}
private:
static constexpr int kCountShiftRegisterSize = shift_register_size;
static constexpr int kInRangeShiftRegisterSize = shift_register_size - 1;
// the shift register of counters
NTuple<shift_register_size, CounterType> counter_;
// the shift register of in range checks
NTuple<kInRangeShiftRegisterSize, bool> inrange_;
// the ending value
CounterType end_;
};
#endif /* __SHANNONITERATOR_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Unroller.hpp | #ifndef __UNROLLER_HPP__
#define __UNROLLER_HPP__
#pragma once
#include <type_traits>
#include <utility>
//
// The code below creates the constexprs 'make_integer_range'
// and 'make_index_range' these are akin to 'std::make_integer_sequence'
// and 'std::make_index_sequence', respectively.
// However they allow you to specificy a range and can either increment
// or decrement, rather than a strict increasing sequence
//
template <typename T, typename, T begin, bool increase>
struct integer_range_impl;
// incrementing case
template <typename T, T... N, T begin>
struct integer_range_impl<T, std::integer_sequence<T, N...>, begin, true> {
using type = std::integer_sequence<T, N + begin...>;
};
// decrementing case
template <typename T, T... N, T begin>
struct integer_range_impl<T, std::integer_sequence<T, N...>, begin, false> {
using type = std::integer_sequence<T, begin - N...>;
};
// integer_range
template <typename T, T begin, T end>
using integer_range = typename integer_range_impl<T,
std::make_integer_sequence<T, (begin < end) ? end - begin : begin - end>,
begin,
(begin < end)>::type;
//
// make_integer_range
//
// USAGE:
// make_integer_range<int,1,10>{} ==> 1,2,...,9
// make_integer_range<int,10,1>{} ==> 10,9,...,2
//
template <class T, T begin, T end>
using make_integer_range = integer_range<T, begin, end>;
//
// make_index_range
//
// USAGE:
// make_index_range<1,10>{} ==> 1,2,...,9
// make_index_range<10,1>{} ==> 10,9,...,2
//
template <std::size_t begin, std::size_t end>
using make_index_range = integer_range<std::size_t, begin, end>;
//
// The code below creates the constexprs 'make_integer_pow2_sequence'
// and 'make_index_pow2_sequence'. These generate the sequence
// 2^0, 2^1, 2^2, ... , 2^(N-1) = 1,2,4,...,2^(N-1)
//
template <typename T, typename>
struct integer_pow2_sequence_impl;
template <typename T, T... Pows>
struct integer_pow2_sequence_impl<T, std::integer_sequence<T, Pows...>> {
using type = std::integer_sequence<T, (T(1) << Pows)...>;
};
// integer_pow2_sequence
template <typename T, T N>
using integer_pow2_sequence =
typename integer_pow2_sequence_impl<T,
std::make_integer_sequence<T, N>>::type;
//
// make_integer_pow2_sequence
//
// USAGE:
// make_integer_pow2_sequence<int,5>{} ==> 1,2,4,8,16
//
template <class T, T N>
using make_integer_pow2_sequence = integer_pow2_sequence<T, N>;
//
// make_index_pow2_sequence
//
// USAGE:
// make_index_pow2_sequence<5>{} ==> 1,2,4,8,16
//
template <std::size_t N>
using make_index_pow2_sequence = integer_pow2_sequence<std::size_t, N>;
///////////////////////////////////////////////////////////////////////////////
//
// Example usage for UnrolledLoop constexpr:
//
// Base
// UnrolledLoop(std::integer_sequence<int,5,2,7,8>{},[&](auto i) {
// /* i = 5,2,7,8 */
// });
//
// Case A
// UnrolledLoop<10>([&](auto i) {
// /* i = 0,1,...,9 */
// });
//
// Case B
// UnrolledLoop<10>([&](auto i) {
// /* i = 0,1,...,9 */
// });
//
// Case C
// UnrolledLoop<char, 1, 10>([&](auto i) {
// /* i = 1,2,...,9 */
// });
// UnrolledLoop<char, 10, 1>([&](auto i) {
// /* i = 10,9,...,2 */
// });
//
// Case D
// UnrolledLoop<1, 10>([&](auto i) {
// /* i = 1,2,...,9 */
// });
// UnrolledLoop<10, 1>([&](auto i) {
// /* i = 10,9,...,2 */
// });
//
///////////////////////////////////////////////////////////////////////////////
//
// Base implementation
// Templated on:
// ItType - the type of the iterator (size_t, int, char, ...)
// ItType... - the indices to iterate on
// F - the function to run for each index (i.e. the lamda)
//
template <class ItType, ItType... inds, class F>
constexpr void UnrolledLoop(std::integer_sequence<ItType, inds...>, F&& f) {
(f(std::integral_constant<ItType, inds>{}), ...);
}
//
// Convience implementation (A)
// performs UnrolledLoop in range [0,n) with iterator of type ItType
//
template <class ItType, ItType n, class F>
constexpr void UnrolledLoop(F&& f) {
UnrolledLoop(std::make_integer_sequence<ItType, n>{}, std::forward<F>(f));
}
//
// Convenience implementation (B)
// performs UnrolledLoop in range [0,n) with an iterator of type std::size_t
//
template <std::size_t n, class F>
constexpr void UnrolledLoop(F&& f) {
UnrolledLoop(std::make_index_sequence<n>{}, std::forward<F>(f));
}
//
// Convenience implementation (C)
// performs UnrolledLoop from start...end with an iterator of type ItType
// NOTE: start is INCLUSIVE, end is EXCLUSIVE
// NOTE: if start<=end, sequence is start,start+1,...,end-1
// if end<=start, sequence is start,start-1,...,end+1
//
template <class ItType, ItType start, ItType end, class F>
constexpr void UnrolledLoop(F&& f) {
UnrolledLoop(make_integer_range<ItType, start, end>{}, std::forward<F>(f));
}
//
// Convenience implementation (C)
// performs UnrolledLoop from start...end with an iterator of type size_t
// NOTE: start is INCLUSIVE, end is EXCLUSIVE
// NOTE: if start<=end, sequence is start,start+1,...,end-1
// if end<=start, sequence is start,start-1,...,end+1
//
template <std::size_t start, std::size_t end, class F>
constexpr void UnrolledLoop(F&& f) {
UnrolledLoop(make_index_range<start, end>{}, std::forward<F>(f));
}
#endif /* __UNROLLER_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Misc.hpp | #ifndef __MISC_HPP__
#define __MISC_HPP__
#pragma once
#include <type_traits>
//// Some useful math functions
//
// computes 2^n where 'n' is a compile time constant
//
template <typename T>
static constexpr T Pow2(T n) {
return T(1) << n;
}
//
// base-2 logarithm
//
template <typename T>
static constexpr T Log2(T n) {
return ((n < 2) ? T(0) : T(1) + Log2(n / 2));
}
//
// round up Log2
//
template <typename T>
static constexpr T CeilLog2(T n) {
return ((n == 1) ? T(0) : Log2(n - 1) + T(1));
}
//
// Count the number of bits set to '1'
//
template <typename T>
constexpr T CountOnes(T val) {
T count = T(0);
while (val != 0) {
count += val & 1;
val >>= 1;
}
return count;
};
//
// Find the position of the Nth '1' (starting at 1)
// E.g. (11 = 4'b1011)
// PositionOfNthOne(1, 11) = 1
// PositionOfNthOne(2, 11) = 2
// PositionOfNthOne(3, 11) = 4
//
template <typename T>
constexpr T PositionOfNthOne(T n, T bits) {
T set = T(0);
T pos = T(0);
while (set < n) {
set += bits & 1;
bits = bits >> 1;
pos++;
}
return pos;
};
#endif /* __MISC_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/StreamingData.hpp | #ifndef __STREAMINGDATA_HPP__
#define __STREAMINGDATA_HPP__
#pragma once
#include <type_traits>
#include "Tuple.hpp"
//
// Generic datatype for streaming data that holds 'Size' elements of type 'Type'
//
template <typename Type, int Size>
class StreamingData {
// static asserts
static_assert(Size > 0, "Size positive and non-zero");
public:
StreamingData() : done(false), valid(false) {}
StreamingData(bool done, bool valid) : done(done), valid(valid) {}
StreamingData(bool done, bool valid, NTuple<Size, Type>& data)
: done(done), valid(valid), data(data) {}
// signals that the upstream component is done computing
bool done;
// marks if the entire tuple ('data') is valid
bool valid;
// the payload data
NTuple<Size, Type> data;
};
#endif /* __STREAMINGDATA_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/fifo_sort.hpp | #ifndef __FIFO_SORT_H__
#define __FIFO_SORT_H__
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iostream>
#include <tuple>
#include <utility>
#include "Misc.hpp"
/*
The sort() function in this header implements a local-memory-based FIFO-Based
Merge Sorter, which has been based on the architecture shown in Figure 8c) of
the following paper on a high performance sorting architecture for large
datasets on FPGA:
[1] D. Koch and J. Torresen, "FPGASort: a high performance sorting architecture
exploiting run-time reconfiguration on fpgas for large problem sorting",
in FPGA '11: ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, Monterey CA USA, 2011. https://dl.acm.org/doi/10.1145/1950413.1950427
The design is templated on the number of elements to sort, 'sort_size',
and is composed of 'num_stages' (= log2(sort_size)) merge stages, where each
stage contains 2 FIFOs for storing sorted data, and output-selection logic.
The FIFOs in each stage have size 'sz_fifo'.
_______________________________________________________________________
Stage 1 | Stage 2 | .... | Stage 'num_stages' |
sz_fifo: 1 2 4,8.., 'sort_size'/2
FIFO A FIFO A FIFO A
/ \ / \ / \
input_pipe --> --> -----....-----> --> output_pipe
\ / \ / \ /
FIFO B FIFO B FIFO B
_______________________________________________________________________
For each stage, the high-level algorithm in the paper is as follows:
1. [Ramp Up] Store the incoming data into FIFO A for sz_fifo iterations.
2. [Steady state] Now that FIFO A has enough data for comparison, FIFO B may
begin receiving data and each iteration, depending on which data at the front of
FIFO A or FIFO B is selected by the comparison (the lesser for ascending sort),
one piece of data is outputted. Alternate the input-receiving FIFO every sz_fifo
iterations, and ensure that for each two separate sorted sets of sz_fifo
inputted, one merged set of 2*sz_fifo is outputted. It is guaranteed based on
the fill pattern that neither FIFO will ever exceed its fill capacity.
To optimize the Fmax of the design, the loading of data from FIFO A/B was
removed from the critical path by making use of a set of 'Preloaders', Preloader
A and Preloader B, in addition to the FIFOs in each stage. These caching storage
units are of size sz_preload (a single-digit number) and are implemented in
registers. With these preloaders, the algorithm for each stage is changed as
follows:
1. [Ramp Up] Store sz_preload incoming elements into Preloader A. Store sz_fifo
elements into FIFO A.
2. [Steady state] Now that FIFO A and Preloader A have enough data for
comparison, Preloader B, followed by FIFO B when the Preloader is full, may
begin receiving data and each iteration, depending on which data at the front of
Preloader A or Preloader B is selected by the comparison (the lesser for
ascending sort), one piece of data is outputted. Alternate the input-receiving
FIFO/Preloader (preloader receives until full, then FIFO receives) every sz_fifo
iterations, and ensure that for each two separate sorted sets of sz_fifo
inputted, one merged set of 2*sz_fifo is outputted. It is guaranteed based on
the fill pattern that neither FIFO will ever exceed its fill capacity.
The total latency from first element in to last element out (number of cycles
for ii=1) is ~ 2*sort_size, and the total element-capacity of all the FIFOs is
2*(sort_size-1).
Consecutive sets of sort_size data can be streamed into the kernel, thus at
steady state, the effective total latency does not comprise the ramp up and is
reduced to ~sort_size.
The motivation for this design using FIFOs implemented with local memory arrays
instead of pipes is primarily so that the FIFOs/storage units for the merged
data in each stage could themselves be left as an abstract unit which can be
optimized. Furthermore, the paper cited above presents the idea of using a
shared memory block of size N instead of of two FIFOs of size N, which could
nearly half the area usage (depending on how the addressing is implemented).
The reasoning behind this is that for each merge stage at steady state, one
element will be inputted and one element outputted each cyle, so after the
initial filling of N elements, the number of elements stored will remain
constant at N.
*/
namespace ihc {
//========================= Sort Function Signature ==========================//
// Convenience Functor structs LessThan and GreaterThan that can be passed to
// sort(Compare compare) by the user if SortType has a compare function
// 'bool operator<(const SortType &t) const' or
// 'bool operator>(const SortType &t) const'
struct LessThan {
template <class T>
bool operator()(T const &a, T const &b) const {
return a < b;
}
};
struct GreaterThan {
template <class T>
bool operator()(T const &a, T const &b) const {
return a > b;
}
};
// For SortType being 4 bytes wide, supported sort_size template values are
// powers of 2 from [2 to 2^16] for A10 and [2 to 2^19] for S10.
template <class SortType, int sort_size, class input_pipe, class output_pipe,
class Compare>
void sort(Compare compare);
// Sort function overload for no compare parameter - ascending order by default.
// Assumes that SortType has a compare function equivalent to:
// 'bool operator<(const SortType &t) const'
template <class SortType, int sort_size, class input_pipe,
class output_pipe>
void sort() {
sort<SortType, sort_size, input_pipe, output_pipe>(LessThan());
}
//============================ Utility Functions =============================//
template <int begin, int end, int sz_fifo>
struct stage_unroller {
template <typename Action>
static void step(const Action &action) {
action(std::integral_constant<int, begin>(),
std::integral_constant<int, sz_fifo>());
stage_unroller<begin + 1, end, sz_fifo + sz_fifo>::step(action);
}
};
template <int end, int sz_fifo>
struct stage_unroller<end, end, sz_fifo> {
template <typename Action>
static void step(const Action &action) {}
};
template <int It, int end>
struct unroller {
template <typename Action>
static void step(const Action& action) {
action(std::integral_constant<int, It>());
unroller<It + 1, end>::step(action);
}
};
template <int end>
struct unroller<end, end> {
template <typename Action>
static void step(const Action&) {}
};
template <typename T_arr, int size>
static void ShiftLeft(T_arr (&Array)[size]) {
unroller<0, size - 1>::step([&](auto j) { Array[j] = Array[j + 1]; });
}
//============================= FIFO Definition ==============================//
// FIFO class of size fixed_sz_fifo (should be a power of 2 for optimal
// performance).
//
// The Enqueue(), Dequeue(), and Peek() functions can be used to insert,
// remove, and read data that is in the FIFO. Whenever Enqueue() or
// Dequeue() are used, UpdateSize() should
// be used to update the size trackers for the FIFO as they are not
// updated by default to optimize the performance of the data transaction
// functions. If it is never necessary for the user to check whether the FIFO
// is full or empty, UpdateSize() does not need to be used.
template <class T, int fixed_sz_fifo>
class FIFO {
private:
T memory_[fixed_sz_fifo];
// front_/back_ indicate the next location where an Enqueue/Dequeue operation
// will take place respectively.
int front_;
int back_;
int increment_front_; // stores front_ + 1
int increment_back_; // stores back_ + 1
// empty_counter_ is initialized to -1 and indicates an empty FIFO when < 0
// (single bit check). empty_counter_ is incremented on
// UpdateSize(did_dequeue=false, did_enqueue=true), decremented upon
// UpdateSize(did_dequeue=true, did_enqueue=false). empty_counter_dec_,
// empty_counter_inc_, etc. store the decrements and increments of
// empty_counter_ and are used to quickly update empty_counter_ upon calling
// UpdateSize().
int empty_counter_;
int empty_counter_dec_; // stores empty_counter_ - 1
int empty_counter_inc_; // stores empty_counter_ + 1
int empty_counter_dec_inc_; // stores empty_counter_dec_ + 1
int empty_counter_inc_inc_; // stores empty_counter_inc_ + 1
int empty_counter_dec_dec_; // stores empty_counter_dec_ - 1
int empty_counter_inc_dec_; // stores empty_counter_inc_ - 1
bool CheckEmpty() { return empty_counter_ < 0; }
public:
// Precomputed value indicating whether the FIFO is empty, providing
// a no-op empty query.
bool empty;
FIFO() {}
void Enqueue(T data) {
memory_[back_] = data;
back_ = increment_back_ % (fixed_sz_fifo);
increment_back_ = back_ + 1;
}
T Peek() { return memory_[front_]; }
void Dequeue() {
front_ = increment_front_ % fixed_sz_fifo;
increment_front_ = front_ + 1;
}
void UpdateSize(bool did_dequeue, bool did_enqueue) {
if (did_dequeue && !did_enqueue) {
// Equivalent to empty_counter_--
empty_counter_ = empty_counter_dec_;
empty_counter_inc_ = empty_counter_inc_dec_;
empty_counter_dec_ = empty_counter_dec_dec_;
} else if (!did_dequeue && did_enqueue) {
// Equivalent to empty_counter_++
empty_counter_ = empty_counter_inc_;
empty_counter_inc_ = empty_counter_inc_inc_;
empty_counter_dec_ = empty_counter_dec_inc_;
}
empty = CheckEmpty(); // check if empty now
empty_counter_inc_dec_ = empty_counter_inc_ - 1;
empty_counter_inc_inc_ = empty_counter_inc_ + 1;
empty_counter_dec_dec_ = empty_counter_dec_ - 1;
empty_counter_dec_inc_ = empty_counter_dec_ + 1;
}
void Initialize() {
front_ = 0;
back_ = 0;
increment_front_ = 1;
increment_back_ = 1;
empty_counter_ = -1;
empty = true;
empty_counter_dec_ = empty_counter_ - 1;
empty_counter_inc_ = empty_counter_ + 1;
empty_counter_inc_dec_ = empty_counter_inc_ - 1;
empty_counter_inc_inc_ = empty_counter_inc_ + 1;
empty_counter_dec_dec_ = empty_counter_dec_ - 1;
empty_counter_dec_inc_ = empty_counter_dec_ + 1;
}
#ifdef DEBUG
void PrintFIFO(std::string name, bool neverFull) {
int numEntries = empty_counter_ != fixed_sz_fifo - 1
? (back_ - front_ + fixed_sz_fifo) % fixed_sz_fifo
: fixed_sz_fifo;
if (neverFull) numEntries = (back_ - front_ + fixed_sz_fifo) % fixed_sz_fifo;
std::cout << "FIFO [" << name << "] Contents (Num=" << numEntries << "): ";
for (int i = 0; i < numEntries; i++) {
std::cout << memory_[(front_ + i) % fixed_sz_fifo] << " ";
}
std::cout << std::endl;
}
#endif
};
//=========================== Preloader Definition ===========================//
template <class T, char sz_preload, char ld_dist>
class Preloader {
private:
// preloaded_data_: registers for storing the preloaded data
// data_in_flight_: data in flight
// valids_in_flight_: load decisions in flight
[[intel::fpga_register]] T preloaded_data_[sz_preload];
[[intel::fpga_register]] T data_in_flight_[ld_dist];
[[intel::fpga_register]] bool valids_in_flight_[ld_dist];
// preload_count_ stores the address where to insert the next item in
// preloaded_data_.
unsigned char preload_count_;
char preload_count_dec_; // stores preload_count_ - 1
char preload_count_inc_; // stores preload_count_ + 1
char preload_count_dec_dec_; // stores preload_count_dec_ - 1
char preload_count_dec_inc_; // stores preload_count_dec_ + 1
// full_counter_ is initialized to sz_preload-1 and indicates a full Preloader
// when < 0 (single bit check). Decremented on an increase in preload_count_ or
// new data being inserted in flight. full_counter_dec_, full_counter_inc_, etc.
// store the decrements and increments of full_counter_ and are used to quickly
// update full_counter_.
char full_counter_;
char full_counter_inc_; // stores full_counter_ + 1
char full_counter_dec_; // stores full_counter_ - 1
char full_counter_inc_inc_; // stores full_counter_inc_ + 1
char full_counter_dec_inc_; // stores full_counter_dec_ + 1
char full_counter_inc_dec_; // stores full_counter_inc_ - 1
char full_counter_dec_dec_; // stores full_counter_dec_ - 1
// empty_counter_ is initialized to -1 and indicates an empty Preloader when <
// 0 (single bit check). Incremented on an increase in preload_count_ or new
// data being inserted in flight. empty_counter_dec_, empty_counter_inc_, etc.
// store the decrements and increments of empty_counter_ and are used to
// quickly update empty_counter_.
char empty_counter_;
char empty_counter_dec_; // stores empty_counter_ - 1
char empty_counter_inc_; // stores empty_counter_ + 1
char empty_counter_inc_dec_; // stores empty_counter_inc_ - 1
char empty_counter_dec_dec_; // stores empty_counter_dec_ - 1
char empty_counter_inc_inc_; // stores empty_counter_inc_ + 1
char empty_counter_dec_inc_; // stores empty_counter_dec_ + 1
// Computation of each index of preloaded_data_ == preload_count_, precomputed
// in advance of EnqueueFront to remove compare from the critical path
[[intel::fpga_register]] bool preload_count_equal_indices_[sz_preload];
// Computation of each index of preloaded_data_ == preload_count_dec_,
// precomputed in advance of EnqueueFront to remove compare from the critical
// path
[[intel::fpga_register]] bool preload_count_dec_equal_indices_[sz_preload];
bool CheckEmpty() { return empty_counter_ < 0; }
bool CheckFull() { return full_counter_ < 0; }
void EnqueueFront(T data) {
// Equivalent to preloaded_data_[preload_count_] = data;
// Implemented this way to convince the compiler to implement
// preloaded_data_ in registers because it wouldn't cooperate even with the
// intel::fpga_register attribute.
unroller<0, sz_preload>::step([&](auto s) {
if (preload_count_equal_indices_[s]) preloaded_data_[s] = data;
});
// Equivalent to preload_count_++
preload_count_ = preload_count_inc_;
preload_count_inc_ = preload_count_ + 1;
}
// Used to precompute computation of each index of preloaded_data_ ==
// preload_count_dec_ and computation of each index of preloaded_data_ ==
// preload_count_.
void UpdateComparePrecomputations() {
unroller<0, sz_preload>::step([&](auto s) {
const bool preload_count_equal = (s == preload_count_);
const bool preload_count_dec_equal = (s == preload_count_dec_);
preload_count_equal_indices_[s] = preload_count_equal;
preload_count_dec_equal_indices_[s] = preload_count_dec_equal;
});
}
public:
// Precomputed values indicating whether the FIFO is empty/full, providing
// no-op empty/full queries.
bool empty;
bool full;
Preloader() {}
T Peek() { return preloaded_data_[0]; }
void Dequeue() {
ShiftLeft(preloaded_data_);
// Equivalent to preload_count_--
preload_count_inc_ = preload_count_;
preload_count_ = preload_count_dec_;
unroller<0, sz_preload>::step([&](auto s) {
preload_count_equal_indices_[s] = preload_count_dec_equal_indices_[s];
});
}
void prestore(T data) {
EnqueueFront(data);
// Equivalent to preload_count_dec_++
preload_count_dec_ = preload_count_dec_inc_;
preload_count_dec_dec_++;
preload_count_dec_inc_++;
// Equivalent to full_counter_--
full_counter_ = full_counter_dec_;
full = CheckFull();
full_counter_inc_ = full_counter_inc_dec_;
full_counter_dec_ = full_counter_dec_dec_;
full_counter_inc_inc_ = full_counter_inc_ + 1;
full_counter_dec_inc_ = full_counter_dec_ + 1;
full_counter_inc_dec_ = full_counter_inc_ - 1;
full_counter_dec_dec_ = full_counter_dec_ - 1;
// Equivalent to empty_counter_++
empty_counter_ = empty_counter_inc_;
empty = false;
empty_counter_dec_ = empty_counter_dec_inc_;
empty_counter_inc_ = empty_counter_inc_inc_;
empty_counter_inc_dec_ = empty_counter_inc_ - 1;
empty_counter_dec_dec_ = empty_counter_dec_ - 1;
empty_counter_inc_inc_ = empty_counter_inc_ + 1;
empty_counter_dec_inc_ = empty_counter_dec_ + 1;
UpdateComparePrecomputations();
}
// Insert the decision to preload, and the corresponding data (garbage data
// if insert = false). Shift the data in flight, and store the data from
// ld_dist-1 iterations ago into the preloader if valid.
// Set did_dequeue = true if Dequeue() was called after the last call
// of AdvanceCycle().
void AdvanceCycle(bool insert, T insert_data, bool did_dequeue) {
data_in_flight_[ld_dist - 1] = insert_data;
valids_in_flight_[ld_dist - 1] = insert;
ShiftLeft(valids_in_flight_);
ShiftLeft(data_in_flight_);
bool valid_data_arrived = valids_in_flight_[0];
if (valid_data_arrived) EnqueueFront(data_in_flight_[0]);
// If Dequeue() was called and no valid data was stored into preloaded_data_
// during this call, the number of elements in the preloader decreased.
// If Dequeue() was not called and valid data was just stored
// into preloaded_data_ during this call, the number of elements in the
// preloader increased.
if (did_dequeue && !valid_data_arrived) // then preload_count_dec_--
preload_count_dec_ = preload_count_dec_dec_;
else if (!did_dequeue && valid_data_arrived) // then preload_count_dec_++
preload_count_dec_ = preload_count_dec_inc_;
preload_count_dec_dec_ = preload_count_dec_ - 1;
preload_count_dec_inc_ = preload_count_dec_ + 1;
// If Dequeue() was called and didn't add new valid in-flight data,
// the [eventual] number of elements in the preloader decreased.
// If Dequeue() wasn't called and did add new valid in-flight data,
// the [eventual] number of elements in the preloader increased.
if (did_dequeue && !insert) {
// Equivalent to full_counter_++
full_counter_ = full_counter_inc_;
full_counter_inc_ = full_counter_inc_inc_;
full_counter_dec_ = full_counter_dec_inc_;
// Equivalent to empty_counter_--
empty_counter_ = empty_counter_dec_;
empty_counter_inc_ = empty_counter_inc_dec_;
empty_counter_dec_ = empty_counter_dec_dec_;
} else if (!did_dequeue && insert) {
// Equivalent to full_counter_--
full_counter_ = full_counter_dec_;
full_counter_inc_ = full_counter_inc_dec_;
full_counter_dec_ = full_counter_dec_dec_;
// Equivalent to empty_counter_++
empty_counter_ = empty_counter_inc_;
empty_counter_inc_ = empty_counter_inc_inc_;
empty_counter_dec_ = empty_counter_dec_inc_;
}
empty = CheckEmpty();
full = CheckFull();
full_counter_inc_inc_ = full_counter_inc_ + 1;
full_counter_dec_inc_ = full_counter_dec_ + 1;
full_counter_inc_dec_ = full_counter_inc_ - 1;
full_counter_dec_dec_ = full_counter_dec_ - 1;
empty_counter_inc_dec_ = empty_counter_inc_ - 1;
empty_counter_dec_dec_ = empty_counter_dec_ - 1;
empty_counter_inc_inc_ = empty_counter_inc_ + 1;
empty_counter_dec_inc_ = empty_counter_dec_ + 1;
UpdateComparePrecomputations();
}
void Initialize() {
unroller<0, ld_dist>::step([&](auto j) { valids_in_flight_[j] = false; });
preload_count_ = 0;
preload_count_dec_ = -1;
preload_count_inc_ = 1;
preload_count_dec_dec_ = preload_count_dec_ - 1;
preload_count_dec_inc_ = preload_count_dec_ + 1;
full = false;
full_counter_ = sz_preload - 1;
full_counter_inc_ = full_counter_ + 1;
full_counter_dec_ = full_counter_ - 1;
full_counter_inc_inc_ = full_counter_inc_ + 1;
full_counter_dec_inc_ = full_counter_dec_ + 1;
full_counter_inc_dec_ = full_counter_inc_ - 1;
full_counter_dec_dec_ = full_counter_dec_ - 1;
empty = false;
empty_counter_ = -1;
empty_counter_dec_ = empty_counter_ - 1;
empty_counter_inc_ = empty_counter_ + 1;
empty_counter_inc_dec_ = empty_counter_inc_ - 1;
empty_counter_dec_dec_ = empty_counter_dec_ - 1;
empty_counter_inc_inc_ = empty_counter_inc_ + 1;
empty_counter_dec_inc_ = empty_counter_dec_ + 1;
UpdateComparePrecomputations();
}
#ifdef DEBUG
void PrintPreloadedData() {
int N = (int)preload_count <= sz_preload ? preload_count : 0;
for (int i = 0; i < N; i++) std::cout << preloaded_data_[i] << " ";
std::cout << std::endl;
}
#endif
};
//============================= Merge Stage =============================//
// A merge iteration for a single stage of the FIFO Merge Sorter. The first
// output_start iterations are an initial loading phase, after which valid data
// can be outputted. sz_fifo: Number of cycles after which the receiving FIFO is
// switched. sort_size: Total number of elements to be sorted.
template <class SortType, int sort_size, int sz_fifo, char sz_preload,
char ld_dist, class Compare>
void merge(FIFO<SortType, sz_fifo> &fifo_a, FIFO<SortType, sz_fifo> &fifo_b,
const int output_start, int &remove_count_a, int &remove_count_b,
bool &removed_n_a, bool &removed_n_b, int &receive_count,
bool &is_receiving_b, const int i, SortType &stream_in_data,
SortType &out_data, int &remove_count_a_inc, int &remove_count_b_inc,
bool &removed_n_a_increment, bool &removed_n_b_increment,
Preloader<SortType, sz_preload, ld_dist> &preloader_a,
Preloader<SortType, sz_preload, ld_dist> &preloader_b,
int &remove_count_a_inc_inc, int &remove_count_b_inc_inc,
Compare compare) {
const bool reading_in_stream = i < sort_size;
#ifdef DEBUG
if (reading_in_stream)
std::cout << "Input stream data: " << stream_in_data << std::endl;
#endif
// Main block for comparing FIFO data and selecting an output
if (i >= output_start) {
// Main decision: Choose which Preloader's data should be outputted
const bool force_extract_b =
removed_n_a || (!reading_in_stream && preloader_a.empty);
const bool force_extract_a =
removed_n_b || (!reading_in_stream && preloader_b.empty);
SortType fifo_a_front = preloader_a.Peek();
SortType fifo_b_front = preloader_b.Peek();
const bool extract_b =
!force_extract_a && (force_extract_b || compare(fifo_b_front, fifo_a_front));
// Check whether each FIFO has arriving data, and has available data
const bool a_data_incoming = reading_in_stream && !is_receiving_b;
const bool b_data_incoming = reading_in_stream && is_receiving_b;
const bool a_has_data = (a_data_incoming || !fifo_a.empty);
const bool b_has_data = (b_data_incoming || !fifo_b.empty);
// Make decision for whether should store FIFO data into preloader
const bool front_b_not_full = !preloader_b.full || extract_b;
const bool store_front_b = (extract_b && b_has_data) ||
(b_data_incoming && fifo_b.empty && front_b_not_full);
const bool front_a_not_full = !preloader_a.full || !extract_b;
const bool store_front_a = (!extract_b && a_has_data) ||
(a_data_incoming && fifo_a.empty && front_a_not_full);
// Select output data, update counters, and shift preloader data
if (extract_b) {
out_data = fifo_b_front;
// Equivalent to remove_count_b++; removed_n_b = remove_count_b == sz_fifo;
remove_count_b = remove_count_b_inc;
remove_count_b_inc = remove_count_b_inc_inc;
removed_n_b = removed_n_b_increment;
// Shift preloaded data
preloader_b.Dequeue();
} else {
out_data = fifo_a_front;
// Equivalent to remove_count_a++; removed_n_a = remove_count_a == sz_fifo;
remove_count_a = remove_count_a_inc;
remove_count_a_inc = remove_count_a_inc_inc;
removed_n_a = removed_n_a_increment;
// Shift preloaded data
preloader_a.Dequeue();
}
#ifdef DEBUG
std::cout << " out data: " << out_data << std::endl;
#endif
// Precompute these operations
removed_n_a_increment = remove_count_a_inc == sz_fifo;
removed_n_b_increment = remove_count_b_inc == sz_fifo;
remove_count_a_inc_inc = remove_count_a_inc + 1;
remove_count_b_inc_inc = remove_count_b_inc + 1;
// Grant permission for the next sz_fifo-set to go through to the output
// stream when valid
if (removed_n_a && removed_n_b) {
remove_count_a = 0;
remove_count_b = 0;
remove_count_a_inc = 1;
remove_count_b_inc = 1;
removed_n_a = false;
removed_n_b = false;
removed_n_a_increment = 1 == sz_fifo;
removed_n_b_increment = 1 == sz_fifo;
remove_count_a_inc_inc = 2;
remove_count_b_inc_inc = 2;
}
// Select the data that that should be stored in the preloader. Either data
// from the FIFO or the in_data just received if the FIFO is empty
// (bypassing the FIFO).
SortType data_fifo_a = fifo_a.Peek();
SortType data_fifo_b = fifo_b.Peek();
if (is_receiving_b && fifo_b.empty)
data_fifo_b = stream_in_data;
else if (!is_receiving_b && fifo_a.empty)
data_fifo_a = stream_in_data;
// Indicates whether the stream_in_data bypassed the receiving FIFO and
// was inserted directly into the Preloader for that FIFO. If true, the
// stream_in_data should not enter the receiving FIFO.
bool bypass = (store_front_b && fifo_b.empty && is_receiving_b) ||
(store_front_a && fifo_a.empty && !is_receiving_b);
// Dequeue from FIFO if storing into preloader and did not bypass.
// Store (must be after loading otherwise FIFO can get full) to FIFO if data
// incoming and didn't store to preloader with bypass. Update size trackers
// of FIFOs.
const bool deq_b = store_front_b && !fifo_b.empty;
const bool deq_a = store_front_a && !fifo_a.empty;
const bool store_b = b_data_incoming && !bypass;
const bool store_a = a_data_incoming && !bypass;
if (deq_b) fifo_b.Dequeue();
if (deq_a) fifo_a.Dequeue();
if (store_b)
fifo_b.Enqueue(stream_in_data);
else if (store_a)
fifo_a.Enqueue(stream_in_data);
fifo_a.UpdateSize(deq_a, store_a);
fifo_b.UpdateSize(deq_b, store_b);
// Send the to-be-loaded FIFO data to the preloader (validity of data
// given by store_frontX), and update the data in flight. This to-be-loaded
// data is realized ld_dist-1 iterations later.
// Update size trackers of preloaders.
preloader_a.AdvanceCycle(store_front_a, data_fifo_a, !extract_b);
preloader_b.AdvanceCycle(store_front_b, data_fifo_b, extract_b);
}
// Initial loading phase, fill Preloader before FIFO
else if (reading_in_stream) {
if (is_receiving_b) {
if (!preloader_b.full)
preloader_b.prestore(stream_in_data);
else {
fifo_b.Enqueue(stream_in_data);
fifo_b.UpdateSize(false, true);
}
} else {
if (!preloader_a.full)
preloader_a.prestore(stream_in_data);
else {
fifo_a.Enqueue(stream_in_data);
fifo_a.UpdateSize(false, true);
}
}
}
// Determine the receiving FIFO, alternates every sz_fifo iterations
if (++receive_count == sz_fifo) {
is_receiving_b = !is_receiving_b;
receive_count = 0;
}
#ifdef DEBUG
fifo_a.PrintFIFO("fifo_a " + std::to_string(sz_fifo), false);
fifo_b.PrintFIFO("fifo_b " + std::to_string(sz_fifo), false);
preloader_a.PrintPreloadedData();
preloader_b.PrintPreloadedData();
std::cout << std::endl;
#endif
}
//========================== SortStages Definition ===========================//
// The Stages alias references a tuple of (FIFO<SZ=1>, FIFO<SZ=2>, FIFO<SZ=4>,
// ... FIFO<SZ=sort_size/2>). i.e. FIFOs with power of 2 memory sizes.
template <class SortType, char num_stages>
struct SortStages {
template <int... indices>
static std::tuple<FIFO<SortType, Pow2(indices)>...> make_array(
std::integer_sequence<int, indices...>);
using Stages =
decltype(make_array(std::make_integer_sequence<int, num_stages>()));
};
//=================================== Sort ===================================//
template <class SortType, int sort_size, class input_pipe, class output_pipe,
class Compare>
void sort(Compare compare) {
static_assert(
std::is_same<bool, decltype(compare(std::declval<SortType>(),
std::declval<SortType>()))>::value,
"The signature of the compare function should be equivalent to the "
"following: bool cmp(const Type1 &a, const Type2 &b);");
//constexpr char num_stages = std::integral_constant<char, Log2(sort_size)>();
constexpr unsigned char num_stages = std::integral_constant<unsigned char, Log2(sort_size)>();
// Create FIFOs
typename SortStages<SortType, num_stages>::Stages fifosA;
typename SortStages<SortType, num_stages>::Stages fifosB;
// Create Preloaders
const char sz_preload = 15;
const char ld_dist = sz_preload + 1; // can be at most sz_preload+1
Preloader<SortType, sz_preload, ld_dist> preloadersA[num_stages];
Preloader<SortType, sz_preload, ld_dist> preloadersB[num_stages];
// Number of elements removed from FIFO A/B in each stage
int remove_count_a[num_stages];
int remove_count_b[num_stages];
// Whether sz_fifo elements have been removed from FIFO A/B in each stage
bool removed_n_a[num_stages];
bool removed_n_b[num_stages];
// Precomputations for remove_count_A/B and removed_SZ_FIFO_A/B variables
int remove_count_a_inc[num_stages];
int remove_count_b_inc[num_stages];
int remove_count_a_inc_inc[num_stages];
int remove_count_b_inc_inc[num_stages];
bool removed_n_a_increment[num_stages];
bool removed_n_b_increment[num_stages];
// How many elements the current receiving FIFO (A or B) has received. Reset
// when equal to sz_fifo.
int receive_count[num_stages];
// Whether FIFO B is receiving input data. If false, FIFO A is receiving.
bool is_receiving_b[num_stages];
// The data transfered between the sort stages
[[intel::fpga_register]] SortType stream_data[num_stages + 1];
// Used in stage unroller to determine when a stage should begin, and when
// a stage should start outputting data.
int output_start[num_stages];
int stage_start[num_stages];
stage_unroller<0, num_stages, 1>::step([&](auto s, auto sz_fifo) {
// Sort variables
remove_count_a[s] = 0;
remove_count_b[s] = 0;
receive_count[s] = 0;
removed_n_a[s] = false;
removed_n_b[s] = false;
is_receiving_b[s] = false;
remove_count_a_inc[s] = 1;
remove_count_b_inc[s] = 1;
remove_count_a_inc_inc[s] = 2;
remove_count_b_inc_inc[s] = 2;
removed_n_a_increment[s] = s == 0 ? true : false;
removed_n_b_increment[s] = s == 0 ? true : false;
// FIFOs and Preloaders
std::get<s>(fifosA).Initialize();
std::get<s>(fifosB).Initialize();
preloadersA[s].Initialize();
preloadersB[s].Initialize();
// Stage selection variables
output_start[s] = sz_preload + sz_fifo;
stage_start[s] = (s == 0) ? 0 : stage_start[s - 1] + output_start[s - 1];
});
constexpr int kOutputStartLastStage =
num_stages * sz_preload + sort_size - 1;
constexpr int kTotalIter = kOutputStartLastStage + sort_size;
// Sort
//[[intel::initiation_interval(1)]]
for (int i = 0; i < kTotalIter; i++) {
#ifdef DEBUG
std::cout << "I: " << i << std::endl;
#endif
if (i < sort_size) stream_data[0] = input_pipe::read();
// All sort stages
stage_unroller<0, num_stages, 1>::step([&](auto s, auto sz_fifo) {
if (i >= stage_start[s])
merge<SortType, sort_size, sz_fifo, sz_preload, ld_dist>(
std::get<s>(fifosA), std::get<s>(fifosB), output_start[s],
remove_count_a[s], remove_count_b[s], removed_n_a[s], removed_n_b[s],
receive_count[s], is_receiving_b[s], i - stage_start[s],
stream_data[s], stream_data[s + 1], remove_count_a_inc[s],
remove_count_b_inc[s], removed_n_a_increment[s],
removed_n_b_increment[s], preloadersA[s], preloadersB[s],
remove_count_a_inc_inc[s], remove_count_b_inc_inc[s], compare);
});
if (i >= kOutputStartLastStage)
output_pipe::write(stream_data[num_stages]);
}
}
} // namespace ihc
#endif //__FIFO_SORT_H__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/MergeJoin.hpp | #ifndef __MERGE_JOIN_HPP__
#define __MERGE_JOIN_HPP__
#pragma once
#include <functional>
#include <set>
#include <tuple>
#include <type_traits>
#include <utility>
#include "Unroller.hpp"
#include "Tuple.hpp"
#include "StreamingData.hpp"
#include "ShannonIterator.hpp"
using namespace sycl;
//
// Joins two tables into a single table
// Assumptions:
// - Both tables sorted by same 'primary' key (PrimaryKey() function of
// table types)
// - Table 1 rows have unique primary keys
// - Table 2 can have multiple rows with the same primary key
// More information and pseudocode can be found here:
// https://en.wikipedia.org/wiki/Sort-merge_join
//
template<typename T1Pipe, typename T1Type, int t1_win_size,
typename T2Pipe, typename T2Type, int t2_win_size,
typename OutPipe, typename JoinType>
void MergeJoin() {
//////////////////////////////////////////////////////////////////////////////
// static asserts
static_assert(t1_win_size > 0,
"Table 1 window size must be positive and non-zero");
static_assert(t2_win_size > 0,
"Table 2 window size must be positive and non-zero");
static_assert(
std::is_same_v<unsigned int, decltype(T1Type().PrimaryKey())>,
"T1Type must have 'PrimaryKey()' function that returns an 'unsigned "
"int'");
static_assert(
std::is_same_v<unsigned int, decltype(T2Type().PrimaryKey())>,
"T2Type must have 'PrimaryKey()' function that returns an 'unsigned "
"int'");
static_assert(std::is_same_v<bool, decltype(T1Type().valid)>,
"T1Type must have a 'valid' boolean member");
static_assert(std::is_same_v<bool, decltype(T2Type().valid)>,
"T2Type must have a 'valid' boolean member");
static_assert(std::is_same_v<bool, decltype(JoinType().valid)>,
"JoinType must have a 'valid' boolean member");
//////////////////////////////////////////////////////////////////////////////
// is the producer of table 1 and table 2 input are done streaming in
bool t1_done = false, t2_done = false;
// is the data read from the pipes are valid
bool t1_win_valid = false, t2_win_valid = false;
// are table 1 and 2 initialized with valid data
bool t1_initialized = false, t2_initialized = false;
// whether to keep going in the processing loop
bool keep_going = true;
// whether the computation has finished or not
bool done_comp = false;
// boolean to select either moving the table 1 window, or the table 2 window
bool move_t1_win = false;
// the table window data
StreamingData<T1Type, t1_win_size> t1_win;
StreamingData<T2Type, t2_win_size> t2_win;
[[intel::initiation_interval(1)]]
while (keep_going) {
//////////////////////////////////////////////////////
// update T1 window
if (!t1_initialized || !t1_win_valid || (move_t1_win && t2_win_valid) ||
(done_comp && !t1_done)) {
t1_win = T1Pipe::read(t1_win_valid);
if (t1_win_valid) {
t1_done = t1_win.done;
t1_initialized = true;
}
}
// update T2 window
if (!t2_initialized || !t2_win_valid || (!move_t1_win && t1_win_valid) ||
(done_comp && !t2_done)) {
t2_win = T2Pipe::read(t2_win_valid);
if (t2_win_valid) {
t2_done = t2_win.done;
t2_initialized = true;
}
}
//////////////////////////////////////////////////////
if (!done_comp && t1_win.valid && t2_win.valid && t1_win_valid &&
t2_win_valid && !t1_done && !t2_done) {
//////////////////////////////////////////////////////
//// join the input data windows into output data
StreamingData<JoinType, t2_win_size> join_data(false, true);
// initialize all outputs to false
UnrolledLoop<0, t2_win_size>([&](auto i) {
join_data.data.template get<i>().valid = false;
});
// crossbar join
UnrolledLoop<0, t2_win_size>([&](auto i) {
const bool t2_data_valid = t2_win.data.template get<i>().valid;
const auto t2_key = t2_win.data.template get<i>().PrimaryKey();
UnrolledLoop<0, t1_win_size>([&](auto j) {
const bool t1_data_valid = t1_win.data.template get<j>().valid;
const auto t1_key = t1_win.data.template get<j>().PrimaryKey();
if (t1_data_valid && t2_data_valid &&
(t1_key == t2_key)) {
// NOTE: order below important if Join() overrides valid
join_data.data.template get<i>().valid = true;
join_data.data.template get<i>().Join(
t1_win.data.template get<j>(), t2_win.data.template get<i>());
}
});
});
//////////////////////////////////////////////////////
//////////////////////////////////////////////////////
//// tell caller to write output data
OutPipe::write(join_data);
//////////////////////////////////////////////////////
}
//////////////////////////////////////////////////////
//// state variables
move_t1_win =
(t1_win.data.last().PrimaryKey() < t2_win.data.last().PrimaryKey());
keep_going = !t1_done || !t2_done;
done_comp = t1_done || t2_done;
//////////////////////////////////////////////////////
}
}
//
// Joins two tables into a single table
// Assumptions:
// - Both tables sorted by same 'primary' key (PrimaryKey() function of
// table types)
// - Table 1 has a maximum of 't1_max_duplicates' rows with the same primary
// key (sorted by this key, so consecutive)
// - Table 2 can have unlimited numbers of rows with same primary key
//
// NOTE: If t1_max_duplicates == 1, MergeJoin should be used as it will be more
// efficient More information and pseudocode can be found here:
// https://en.wikipedia.org/wiki/Sort-merge_join
//
template<typename T1Pipe, typename T1Type, int t1_max_duplicates,
typename T2Pipe, typename T2Type, int t2_win_size,
typename OutPipe, typename JoinType>
void DuplicateMergeJoin() {
//////////////////////////////////////////////////////////////////////////////
// static asserts
static_assert(t1_max_duplicates > 0,
"Table 1 maximum duplicates be positive and non-zero");
static_assert(t2_win_size > 0,
"Table 2 window size must be positive and non-zero");
static_assert(
std::is_same_v<unsigned int, decltype(T1Type().PrimaryKey())>,
"T1Type must have 'PrimaryKey()' function that returns an 'unsigned "
"int'");
static_assert(
std::is_same_v<unsigned int, decltype(T2Type().PrimaryKey())>,
"T2Type must have 'PrimaryKey()' function that returns an 'unsigned "
"int'");
static_assert(std::is_same_v<bool, decltype(T1Type().valid)>,
"T1Type must have a 'valid' boolean member");
static_assert(std::is_same_v<bool, decltype(T2Type().valid)>,
"T2Type must have a 'valid' boolean member");
static_assert(std::is_same_v<bool, decltype(JoinType().valid)>,
"JoinType must have a 'valid' boolean member");
//////////////////////////////////////////////////////////////////////////////
// is the producer of table 1 and table 2 input are done streaming in
bool t1_done = false, t2_done = false;
// is the data read from the pipes are valid
bool t1_win_valid = false, t2_win_valid = false;
// are table 1 and 2 initialized with valid data
bool t1_initialized = false, t2_initialized = false;
// whether to keep going in the processing loop
bool keep_going = true;
// whether the computation has finished or not
bool done_comp = false;
// boolean to select either moving the table 1 window, or the table 2 window
bool move_t1_win = false;
// the table window data
StreamingData<T1Type, t1_max_duplicates> t1_win;
StreamingData<T2Type, t2_win_size> t2_win;
[[intel::initiation_interval(1)]]
while (keep_going) {
//////////////////////////////////////////////////////
// update T1 window
if (!t1_initialized || !t1_win_valid || (move_t1_win && t2_win_valid) ||
(done_comp && !t1_done)) {
t1_win = T1Pipe::read(t1_win_valid);
if (t1_win_valid) {
t1_done = t1_win.done;
t1_initialized = true;
}
}
// update T2 window
if (!t2_initialized || !t2_win_valid || (!move_t1_win && t1_win_valid) ||
(done_comp && !t2_done)) {
t2_win = T2Pipe::read(t2_win_valid);
if (t2_win_valid) {
t2_done = t2_win.done;
t2_initialized = true;
}
}
//////////////////////////////////////////////////////
if (!done_comp && t1_win.valid && t2_win.valid && t1_win_valid &&
t2_win_valid && !t1_done && !t2_done) {
//////////////////////////////////////////////////////
//// join the input data windows into output data
StreamingData<JoinType, t1_max_duplicates * t2_win_size> join_data(false,
true);
// initialize all validity to false
UnrolledLoop<0, t1_max_duplicates * t2_win_size>([&](auto i) {
join_data.data.template get<i>().valid = false;
});
// full crossbar join producing up to t1_max_duplicates*t2_win_size
UnrolledLoop<0, t1_max_duplicates>([&](auto i) {
const bool t1_data_valid = t1_win.data.template get<i>().valid;
const unsigned int t1_key = t1_win.data.template get<i>().PrimaryKey();
UnrolledLoop<0, t2_win_size>([&](auto j) {
const bool t2_data_valid = t2_win.data.template get<j>().valid;
const unsigned int t2_key =
t2_win.data.template get<j>().PrimaryKey();
if (t1_data_valid && t2_data_valid && (t1_key == t2_key)) {
// NOTE: order below important if Join() overrides valid
join_data.data.template get<i * t2_win_size + j>().valid = true;
join_data.data.template get<i * t2_win_size + j>().Join(
t1_win.data.template get<i>(), t2_win.data.template get<j>());
}
});
});
//////////////////////////////////////////////////////
//////////////////////////////////////////////////////
//// write output data
OutPipe::write(join_data);
//////////////////////////////////////////////////////
}
//////////////////////////////////////////////////////
//// state variables
move_t1_win =
(t1_win.data.last().PrimaryKey() < t2_win.data.last().PrimaryKey());
keep_going = !t1_done || !t2_done;
done_comp = t1_done || t2_done;
//////////////////////////////////////////////////////
}
}
#endif /* __MERGE_JOIN_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/CachedMemory.hpp | #ifndef __CACHED_MEMORY_HPP__
#define __CACHED_MEMORY_HPP__
template <typename StorageType, int n, int cache_n,
typename IndexType = int>
class CachedMemory {
// static asserts
static_assert(n > 0);
static_assert(cache_n >= 0);
static_assert(std::is_arithmetic<StorageType>::value,
"StorageType must be arithmetic to support accumulation");
static_assert(std::is_integral<IndexType>::value,
"IndexType must be an integral type");
static_assert(std::numeric_limits<IndexType>::max() >= (n - 1),
"IndexType must be large enough to index the entire array");
public:
CachedMemory() {}
void Init(StorageType init_val = 0) {
for (int i = 0; i < n; i++) {
mem[i] = init_val;
}
#pragma unroll
for (int i = 0; i < cache_n + 1; i++) {
cache_value[i] = init_val;
cache_tag[i] = 0;
}
}
auto Get(IndexType idx) {
// grab the value from memory
StorageType ret = mem[idx];
// check for this value in the cache as well
#pragma unroll
for (int i = 0; i < cache_n + 1; i++) {
if (cache_tag[i] == idx) {
ret = cache_value[i];
}
}
return ret;
}
void Set(IndexType idx, StorageType val) {
// store the new value in the actual memory, and the start of the shift
// register cache
mem[idx] = val;
cache_value[cache_n] = val;
cache_tag[cache_n] = idx;
// shift the shift register cache
#pragma unroll
for (int i = 0; i < cache_n; i++) {
cache_value[i] = cache_value[i + 1];
cache_tag[i] = cache_tag[i + 1];
}
}
private:
// internal storage
StorageType mem[n];
// internal cache for hiding write latency
[[intel::fpga_register]]
StorageType cache_value[cache_n + 1];
[[intel::fpga_register]]
int cache_tag[cache_n + 1];
};
#endif /* __CACHED_MEMORY_HPP__ */ | hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/db_utils/Tuple.hpp | #ifndef __TUPLE_HPP__
#define __TUPLE_HPP__
#pragma once
#include <type_traits>
//
// Generic tuple
//
// USAGE EXAMPLE:
// Tuple<char,short,int,long> my_tuple;
// char a = my_tuple.get<0>();
// short b = my_tuple.get<1>();
// int c = my_tuple.get<2>();
// long d = my_tuple.get<3>();
//
template <typename... Tys>
struct Tuple {
Tuple(Tys... Args) : values(Args...) {}
Tuple() {}
//
// get the index'th item in the tuple of values
//
template <int index>
auto& get() {
static_assert(index < NumTys, "index out of bounds");
return get_impl<index, Tys...>(values);
}
//
// helper to get the first element in the tuple
//
auto& first() { return get<0>(); }
//
// helper to get the last element in the tuple
//
auto& last() { return get<NumTys - 1>(); }
private:
//
// generic tuple implementation: recursive case
//
template <typename CurrentTy, typename... OtherTys>
struct tuple_impl {
tuple_impl(CurrentTy& current, OtherTys... others)
: value(current), other_values(others...) {}
tuple_impl() {}
using ValueTy = CurrentTy;
ValueTy value;
tuple_impl<OtherTys...> other_values;
};
//
// generic tuple implementation: base case
//
template <typename FinalTy>
struct tuple_impl<FinalTy> {
tuple_impl(FinalTy& current) : value(current) {}
tuple_impl() {}
using ValueTy = FinalTy;
ValueTy value;
};
// the tuple values
tuple_impl<Tys...> values;
// the number of tuple values
constexpr static auto NumTys = sizeof...(Tys);
//
// implementation of 'get' for general tuple
//
template <int index, typename HeadTy, typename... TailTys>
static auto& get_impl(tuple_impl<HeadTy, TailTys...>& sub_tuple) {
if constexpr (index == 0) {
// base case
return sub_tuple.value;
} else {
// recursive case
return get_impl<index - 1, TailTys...>(sub_tuple.other_values);
}
}
};
//
// NTuple implementation
// This is convenient way to have N elements of the same type
// somewhat like an std::array
//
template <int, typename Type>
using NTupleElem = Type;
template <typename Type, std::size_t... Idx>
static auto make_NTupleImpl(std::index_sequence<Idx...>)
-> Tuple<NTupleElem<Idx, Type>...>;
template <int N, typename Type>
using make_NTuple =
decltype(make_NTupleImpl<Type>(std::make_index_sequence<N>()));
//
// convenience alias for a tuple of N elements of the same type
//
// USAGE EXAMPLE:
// NTuple<10,int> elements;
// elements.get<3>() = 17;
//
template <int N, typename Type>
using NTuple = make_NTuple<N, Type>;
#endif /* __TUPLE_HPP__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query9/query9_kernel.hpp | #ifndef __QUERY9_KERNEL_HPP__
#define __QUERY9_KERNEL_HPP__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../dbdata.hpp"
using namespace sycl;
bool SubmitQuery9(queue& q, Database& dbinfo,
std::string colour,
std::array<DBDecimal, 25 * 2020>& sum_profit,
double& kernel_latency, double& total_latency);
#endif //__QUERY9_KERNEL_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query9/query9_kernel.cpp | #include <array>
#include <stdio.h>
#include <type_traits>
#include <vector>
#include "query9_kernel.hpp"
#include "pipe_types.hpp"
#include "onchip_memory_with_cache.hpp" // DirectProgramming/C++SYCL_FPGA/include
#include "../db_utils/Accumulator.hpp"
#include "../db_utils/LikeRegex.hpp"
#include "../db_utils/MapJoin.hpp"
#include "../db_utils/MergeJoin.hpp"
#include "../db_utils/Misc.hpp"
#include "../db_utils/ShannonIterator.hpp"
#include "../db_utils/Tuple.hpp"
#include "../db_utils/Unroller.hpp"
#include "../db_utils/fifo_sort.hpp"
using namespace std::chrono;
//
// NOTE: See the README file for a diagram of how the different kernels are
// connected
//
// kernel class names
class ProducerOrders;
class FilterParts;
class ProducePartSupplier;
class JoinPartSupplierSupplier;
class JoinLineItemOrders;
class FeedSort;
class FifoSort;
class ConsumeSort;
class JoinEverything;
class Compute;
/////////////////////////////////////////////////////////////////////////////
// sort configuration
using SortType = SortData;
// need to sort at most 6% of the lineitem table
constexpr int kNumSortStages = CeilLog2(kLineItemTableSize * 0.06);
constexpr int kSortSize = Pow2(kNumSortStages);
using SortInPipe = pipe<class SortInputPipe, SortType>;
using SortOutPipe = pipe<class SortOutputPipe, SortType>;
static_assert(kLineItemTableSize * 0.06 <= kSortSize,
"Must be able to sort all part keys");
/////////////////////////////////////////////////////////////////////////////
//
// Helper function to shuffle the valid values in 'input' into 'output' using
// the bits template
// For example, consider this simple case:
// input = {7,8}
// if bits = 1 (2'b01), then output = {0,7}
// if bits = 2 (2'b01), then output = {0,8}
// if bits = 3 (2'b01), then output = {7,8}
//
template <char bits, int tuple_size, typename TupleType>
void Shuffle(NTuple<tuple_size, TupleType>& input,
NTuple<tuple_size, TupleType>& output) {
// get number of ones (number of valid entries) in the input
constexpr char kNumOnes = CountOnes<char>(bits);
// static asserts
static_assert(tuple_size > 0,
"tuple_size must strictly positive");
static_assert(kNumOnes <= tuple_size,
"Number of valid bits in bits cannot exceed the size of the tuple");
// full crossbar to reorder valid entries of 'input'
UnrolledLoop<0, kNumOnes>([&](auto i) {
constexpr char pos = PositionOfNthOne<char>(i + 1, bits) - 1;
output.template get<i>() = input.template get<pos>();
});
}
bool SubmitQuery9(queue& q, Database& dbinfo, std::string colour,
std::array<DBDecimal, 25 * 2020>& sum_profit,
double& kernel_latency, double& total_latency) {
// copy the regex string to character array, pad with NULL characters
std::array<char, 11> regex_word;
for (size_t i = 0; i < 11; i++) {
regex_word[i] = (i < colour.size()) ? colour[i] : '\0';
}
// create space for the input buffers
// the REGEX
buffer regex_word_buf(regex_word);
// PARTS
buffer p_name_buf(dbinfo.p.name);
// SUPPLIER
buffer s_nationkey_buf(dbinfo.s.nationkey);
// PARTSUPPLIER
buffer ps_partkey_buf(dbinfo.ps.partkey);
buffer ps_suppkey_buf(dbinfo.ps.suppkey);
buffer ps_supplycost_buf(dbinfo.ps.supplycost);
// ORDERS
buffer o_orderkey_buf(dbinfo.o.orderkey);
buffer o_orderdate_buf(dbinfo.o.orderdate);
// LINEITEM
buffer l_orderkey_buf(dbinfo.l.orderkey);
buffer l_partkey_buf(dbinfo.l.partkey);
buffer l_suppkey_buf(dbinfo.l.suppkey);
buffer l_quantity_buf(dbinfo.l.quantity);
buffer l_extendedprice_buf(dbinfo.l.extendedprice);
buffer l_discount_buf(dbinfo.l.discount);
// setup the output buffer (the profit for each nation and year)
buffer sum_profit_buf(sum_profit);
// number of producing iterations depends on the number of elements per cycle
const size_t l_rows = dbinfo.l.rows;
const size_t l_iters =
(l_rows + kLineItemJoinWinSize - 1) / kLineItemJoinWinSize;
const size_t o_rows = dbinfo.o.rows;
const size_t o_iters =
(o_rows + kOrdersJoinWinSize - 1) / kOrdersJoinWinSize;
const size_t ps_rows = dbinfo.ps.rows;
const size_t ps_iters =
(ps_rows + kPartSupplierDuplicatePartkeys - 1)
/ kPartSupplierDuplicatePartkeys;
const size_t p_rows = dbinfo.p.rows;
const size_t p_iters =
(p_rows + kRegexFilterElementsPerCycle - 1)
/ kRegexFilterElementsPerCycle;
// start timer
high_resolution_clock::time_point host_start = high_resolution_clock::now();
/////////////////////////////////////////////////////////////////////////////
//// FilterParts Kernel:
//// Filter the PARTS table and produce the filtered LINEITEM table
auto filter_parts_event = q.submit([&](handler& h) {
// REGEX word accessor
accessor regex_word_accessor(regex_word_buf, h, read_only);
// PARTS table accessors
accessor p_name_accessor(p_name_buf, h, read_only);
// LINEITEM table accessors
accessor l_orderkey_accessor(l_orderkey_buf, h, read_only);
accessor l_partkey_accessor(l_partkey_buf, h, read_only);
accessor l_suppkey_accessor(l_suppkey_buf, h, read_only);
// kernel to filter parts table based on REGEX
h.single_task<FilterParts>([=]() [[intel::kernel_args_restrict]] {
// a map where the key is the partkey and the value is whether
// that partkeys name matches the given regex
bool partkeys_matching_regex[kPartTableSize + 1];
///////////////////////////////////////////////
//// Stage 1
// find valid parts with REGEX
LikeRegex<11, 55> regex[kRegexFilterElementsPerCycle];
// initialize regex word
for (size_t i = 0; i < 11; i++) {
const char c = regex_word_accessor[i];
UnrolledLoop<0, kRegexFilterElementsPerCycle>([&](auto re) {
regex[re].word[i] = c;
});
}
// stream in rows of PARTS table and check partname against REGEX
[[intel::initiation_interval(1), intel::ivdep]]
for (size_t i = 0; i < p_iters; i++) {
UnrolledLoop<0, kRegexFilterElementsPerCycle>([&](auto re) {
const size_t idx = i * kRegexFilterElementsPerCycle + re;
const bool idx_range = idx < p_rows;
// read in partkey
// valid partkeys in range [1,kPartTableSize]
const DBIdentifier partkey = idx_range ? idx + 1 : 0;
// read in regex string
UnrolledLoop<0, 55>([&](auto k) {
regex[re].str[k] = p_name_accessor[idx * 55 + k];
});
// run regex matching
regex[re].Match();
// mark valid partkey
if (idx_range) {
partkeys_matching_regex[partkey] = regex[re].Contains();
}
});
}
///////////////////////////////////////////////
///////////////////////////////////////////////
//// Stage 2
// read in the LINEITEM table (kLineItemJoinWinSize rows at a time)
// row is valid if its PARTKEY matched the REGEX
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < l_iters + 1; i++) {
bool done = (i == l_iters);
bool valid = (i != l_iters);
// bulk read of data from global memory
NTuple<kLineItemJoinWinSize, LineItemMinimalRow> data;
UnrolledLoop<0, kLineItemJoinWinSize>([&](auto j) {
size_t idx = i * kLineItemJoinWinSize + j;
bool in_range = idx < l_rows;
DBIdentifier orderkey = l_orderkey_accessor[idx];
DBIdentifier partkey = l_partkey_accessor[idx];
DBIdentifier suppkey = l_suppkey_accessor[idx];
bool matches_partkey_name_regex = partkeys_matching_regex[partkey];
bool data_is_valid = in_range && matches_partkey_name_regex;
data.get<j>() = LineItemMinimalRow(data_is_valid, idx, orderkey,
partkey, suppkey);
});
// write to pipe
LineItemPipe::write(LineItemMinimalRowPipeData(done, valid, data));
}
///////////////////////////////////////////////
});
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// ProducerOrders Kernel: produce the ORDERS table
auto producer_orders_event = q.submit([&](handler& h) {
// ORDERS table accessors
accessor o_orderkey_accessor(o_orderkey_buf, h, read_only);
accessor o_orderdate_accessor(o_orderdate_buf, h, read_only);
// produce ORDERS table (kOrdersJoinWinSize rows at a time)
h.single_task<ProducerOrders>([=]() [[intel::kernel_args_restrict]] {
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < o_iters + 1; i++) {
bool done = (i == o_iters);
bool valid = (i != o_iters);
// bulk read of data from global memory
NTuple<kOrdersJoinWinSize, OrdersRow> data;
UnrolledLoop<0, kOrdersJoinWinSize>([&](auto j) {
size_t idx = i * kOrdersJoinWinSize + j;
bool in_range = idx < l_rows;
DBIdentifier orderkey_tmp = o_orderkey_accessor[idx];
DBDate orderdate = o_orderdate_accessor[idx];
DBIdentifier orderkey =
in_range ? orderkey_tmp : std::numeric_limits<DBIdentifier>::max();
data.get<j>() = OrdersRow(in_range, orderkey, orderdate);
});
// write to pipe
OrdersPipe::write(OrdersRowPipeData(done, valid, data));
}
});
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// JoinLineItemOrders Kernel: join the LINEITEM and ORDERS table
auto join_lineitem_orders_event = q.submit([&](handler& h) {
// kernel to join LINEITEM and ORDERS table
h.single_task<JoinLineItemOrders>([=]() [[intel::kernel_args_restrict]] {
// JOIN LINEITEM and ORDERS table
MergeJoin<OrdersPipe, OrdersRow, kOrdersJoinWinSize,
LineItemPipe, LineItemMinimalRow, kLineItemJoinWinSize,
LineItemOrdersPipe, LineItemOrdersMinimalJoined>();
// join is done, tell downstream
LineItemOrdersPipe::write(
LineItemOrdersMinimalJoinedPipeData(true, false));
});
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// JoinPartSupplierSupplier Kernel: join the PARTSUPPLIER and SUPPLIER tables
auto join_partsupplier_supplier_event = q.submit([&](handler& h) {
// SUPPLIER table accessors
size_t s_rows = dbinfo.s.rows;
accessor s_nationkey_accessor(s_nationkey_buf, h, read_only);
// kernel to join partsupplier and supplier tables
h.single_task<JoinPartSupplierSupplier>(
[=]() [[intel::kernel_args_restrict]] {
// +1 is to account for fact that SUPPKEY is [1,kSF*10000]
unsigned char nation_key_map_data[kSupplierTableSize + 1];
bool nation_key_map_valid[kSupplierTableSize + 1];
for (int i = 0; i < kSupplierTableSize + 1; i++) {
nation_key_map_valid[i] = false;
}
///////////////////////////////////////////////
//// Stage 1
// populate the array map
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < s_rows; i++) {
// NOTE: based on TPCH docs, SUPPKEY is guaranteed
// to be unique in range [1:kSF*10000]
DBIdentifier s_suppkey = i + 1;
unsigned char s_nationkey = s_nationkey_accessor[i];
nation_key_map_data[s_suppkey] = s_nationkey;
nation_key_map_valid[s_suppkey] = true;
}
///////////////////////////////////////////////
///////////////////////////////////////////////
//// Stage 2
// MAPJOIN PARTSUPPLIER and SUPPLIER tables by suppkey
MapJoin<unsigned char, PartSupplierPipe, PartSupplierRow,
kPartSupplierDuplicatePartkeys, PartSupplierPartsPipe,
SupplierPartSupplierJoined>(nation_key_map_data,
nation_key_map_valid);
// tell downstream we are done
PartSupplierPartsPipe::write(
SupplierPartSupplierJoinedPipeData(true, false));
///////////////////////////////////////////////
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// ProducePartSupplier Kernel: produce the PARTSUPPLIER table
auto produce_part_supplier_event = q.submit([&](handler& h) {
// PARTSUPPLIER table accessors
accessor ps_partkey_accessor(ps_partkey_buf, h, read_only);
accessor ps_suppkey_accessor(ps_suppkey_buf, h, read_only);
accessor ps_supplycost_accessor(ps_supplycost_buf, h, read_only);
// kernel to produce the PARTSUPPLIER table
h.single_task<ProducePartSupplier>([=]() [[intel::kernel_args_restrict]] {
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < ps_iters + 1; i++) {
bool done = (i == ps_iters);
bool valid = (i != ps_iters);
// bulk read of data from global memory
NTuple<kPartSupplierDuplicatePartkeys, PartSupplierRow> data;
UnrolledLoop<0, kPartSupplierDuplicatePartkeys>([&](auto j) {
size_t idx = i * kPartSupplierDuplicatePartkeys + j;
bool in_range = idx < ps_rows;
DBIdentifier partkey = ps_partkey_accessor[idx];
DBIdentifier suppkey = ps_suppkey_accessor[idx];
DBDecimal supplycost = ps_supplycost_accessor[idx];
data.get<j>() =
PartSupplierRow(in_range, partkey, suppkey, supplycost);
});
// write to pipe
PartSupplierPipe::write(PartSupplierRowPipeData(done, valid, data));
}
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// Compute Kernel: do the final computation on the data
auto computation_kernel_event = q.submit([&](handler& h) {
// LINEITEM table accessors
accessor l_quantity_accessor(l_quantity_buf, h, read_only);
accessor l_extendedprice_accessor(l_extendedprice_buf, h, read_only);
accessor l_discount_accessor(l_discount_buf, h, read_only);
// output accessors
accessor sum_profit_accessor(sum_profit_buf, h, write_only, no_init);
h.single_task<Compute>([=]() [[intel::kernel_args_restrict]] {
// the accumulators
constexpr int kAccumCacheSize = 8;
NTuple<kFinalDataMaxSize, fpga_tools::OnchipMemoryWithCache<
DBDecimal, (25 * 7), kAccumCacheSize>>
sum_profit_local;
// initialize the accumulators
UnrolledLoop<0, kFinalDataMaxSize>([&](auto j) {
sum_profit_local.template get<j>().init(0);
});
bool done = false;
[[intel::initiation_interval(1)]]
do {
FinalPipeData pipe_data = FinalPipe::read();
done = pipe_data.done;
const bool pipeDataValid = !pipe_data.done && pipe_data.valid;
UnrolledLoop<0, kFinalDataMaxSize>([&](auto j) {
FinalData D = pipe_data.data.get<j>();
bool D_valid = pipeDataValid && D.valid;
unsigned int D_idx = D.lineitemIdx;
// grab LINEITEM data from global memory and compute 'amount'
DBDecimal quantity=0, extendedprice=0, discount=0, supplycost=0;
if(D_valid) {
quantity = l_quantity_accessor[D_idx];
extendedprice = l_extendedprice_accessor[D_idx];
discount = l_discount_accessor[D_idx];
supplycost = D.supplycost;
}
// Why quantity x 100? So we can divide 'amount' by 100*100 later
DBDecimal amount = (extendedprice * (100 - discount)) -
(supplycost * quantity * 100);
// compute index based on order year and nation
// See Date.hpp
unsigned int orderyear = (D.orderdate >> 9) & 0x07FFFFF;
unsigned int nation = D.nationkey;
unsigned char idx = (orderyear - 1992) * 25 + nation;
unsigned char idx_final = D_valid ? idx : 0;
DBDecimal amount_final = D_valid ? amount : 0;
auto current_amount = sum_profit_local.template get<j>().read(idx_final);
auto computed_amount = current_amount + amount_final;
sum_profit_local.template get<j>().write(idx_final, computed_amount);
});
} while (!done);
// push back the accumulated data to global memory
for (size_t n = 0; n < 25; n++) {
for (size_t y = 0; y < 7; y++) {
size_t in_idx = y * 25 + n;
size_t out_idx = (y + 1992) * 25 + n;
DBDecimal amount = 0;
UnrolledLoop<0, kFinalDataMaxSize>([&](auto j) {
amount += sum_profit_local.template get<j>().read(in_idx);
});
sum_profit_accessor[out_idx] = amount;
}
}
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// FeedSort Kernel: kernel to filter out invalid data and feed the sorter
auto feed_sort_event = q.submit([&](handler& h) {
h.single_task<FeedSort>([=]() [[intel::kernel_args_restrict]] {
bool done = false;
size_t num_rows = 0;
[[intel::initiation_interval(1)]]
do {
// get data from upstream
bool valid;
LineItemOrdersMinimalJoinedPipeData pipe_data =
LineItemOrdersPipe::read(valid);
done = pipe_data.done && valid;
if (!done && valid && pipe_data.valid) {
NTuple<kLineItemOrdersJoinWinSize, LineItemOrdersMinimalJoined>
shuffle_data;
unsigned char valid_count = 0;
char valid_bits = 0;
// convert the 'valid' bits in the tuple to a bitset (valid_bits)
UnrolledLoop<0, kLineItemOrdersJoinWinSize>([&](auto i) {
constexpr char mask = 1 << i;
valid_bits |= pipe_data.data.get<i>().valid ? mask : 0;
});
// full crossbar to do the shuffling from pipe_data to shuffle_data
UnrolledLoop<0, Pow2(kLineItemOrdersJoinWinSize)>([&](auto i) {
if (valid_bits == i) {
Shuffle<i, kLineItemOrdersJoinWinSize,
LineItemOrdersMinimalJoined>(pipe_data.data,
shuffle_data);
valid_count = CountOnes<char>(i);
}
});
// Send the data to sorter.
// The idea here is that this loop executes in the range
// [0,kLineItemOrdersJoinWinSize] times.
// However, we know that at most 6% of the data will match the filter
// and go to the sorter. So, that means for every ~16 pieces of
// data, we expect <1 will match the filter and go to the sorter.
// Therefore, so long as kLineItemOrdersJoinWinSize <= 16
// this loop will, on average, execute ONCE per outer loop iteration
// (i.e. statistically, valid_count=1 for every 16 pieces of data).
// NOTE: for this loop to get good throughput it is VERY important to:
// A) Apply the [[intel::speculated_iterations(0)]] attribute
// B) Explicitly bound the loop iterations
// For an explanation why, see the optimize_inner_loops tutorial.
[[intel::initiation_interval(1), intel::speculated_iterations(0)]]
for (char i = 0; i < valid_count &&
i < kLineItemOrdersJoinWinSize; i++) {
UnrolledLoop<0, kLineItemOrdersJoinWinSize>([&](auto j) {
if (j == i) {
SortInPipe::write(SortData(shuffle_data.get<j>()));
}
});
}
num_rows += valid_count;
}
} while (!done);
// send in pad data to ensure we send in exactly kSortSize elements
ShannonIterator<int, 3> i(num_rows, kSortSize);
while (i.InRange()) {
SortInPipe::write(
SortData(0, std::numeric_limits<DBIdentifier>::max(), 0, 0));
i.Step();
}
// drain the input pipe
while (!done) {
bool valid;
LineItemOrdersMinimalJoinedPipeData pipe_data =
LineItemOrdersPipe::read(valid);
done = pipe_data.done && valid;
}
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// ConsumeSort Kernel: consume the output of the sorter
auto consume_sort_event = q.submit([&](handler& h) {
h.single_task<ConsumeSort>([=]() [[intel::kernel_args_restrict]] {
bool done = false;
size_t num_rows = 0;
// read out data from the sorter until 'done' signal from upstream
[[intel::initiation_interval(1)]]
do {
bool valid;
SortData in_data = SortOutPipe::read(valid);
done = (in_data.partkey == std::numeric_limits<DBIdentifier>::max()) &&
valid;
num_rows += valid ? 1 : 0;
if (!done && valid) {
NTuple<1, LineItemOrdersMinimalJoined> out_data;
out_data.get<0>() = LineItemOrdersMinimalJoined(
true, in_data.lineitemIdx, in_data.partkey, in_data.suppkey,
in_data.orderdate);
LineItemOrdersSortedPipe::write(
LineItemOrdersMinimalSortedPipeData(false, true, out_data));
}
} while (!done);
// tell downstream kernel that the sort is done
LineItemOrdersSortedPipe::write(
LineItemOrdersMinimalSortedPipeData(true, false));
// drain the data we don't care about from the sorter
ShannonIterator<int, 3> i(num_rows, kSortSize);
while (i.InRange()) {
bool valid;
(void)SortOutPipe::read(valid);
if (valid) {
i.Step();
}
}
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// FifoSort Kernel: the sorter
auto sort_event = q.submit([&](handler& h) {
h.single_task<FifoSort>([=]() [[intel::kernel_args_restrict]] {
ihc::sort<SortType, kSortSize, SortInPipe, SortOutPipe>(ihc::LessThan());
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// JoinEverything Kernel: join the sorted
//// LINEITEM+ORDERS with SUPPLIER+PARTSUPPLIER
auto join_li_o_s_ps_event = q.submit([&](handler& h) {
h.single_task<JoinEverything>([=]() [[intel::kernel_args_restrict]] {
DuplicateMergeJoin<PartSupplierPartsPipe, SupplierPartSupplierJoined,
kPartSupplierDuplicatePartkeys,
LineItemOrdersSortedPipe, LineItemOrdersMinimalJoined,
1, FinalPipe, FinalData>();
// join is done, tell downstream
FinalPipe::write(FinalPipeData(true, false));
});
});
/////////////////////////////////////////////////////////////////////////////
// wait for kernel to finish
filter_parts_event.wait();
computation_kernel_event.wait();
join_li_o_s_ps_event.wait();
sort_event.wait();
consume_sort_event.wait();
feed_sort_event.wait();
produce_part_supplier_event.wait();
join_partsupplier_supplier_event.wait();
join_lineitem_orders_event.wait();
producer_orders_event.wait();
high_resolution_clock::time_point host_end = high_resolution_clock::now();
duration<double, std::milli> diff = host_end - host_start;
// gather profiling info
auto filter_parts_start =
filter_parts_event
.get_profiling_info<info::event_profiling::command_start>();
auto computation_end =
computation_kernel_event
.get_profiling_info<info::event_profiling::command_end>();
// calculating the kernel execution time in ms
auto kernel_execution_time = (computation_end - filter_parts_start) * 1e-6;
kernel_latency = kernel_execution_time;
total_latency = diff.count();
return true;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query9/pipe_types.hpp | #ifndef __PIPE_TYPES_H__
#define __PIPE_TYPES_H__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../db_utils/StreamingData.hpp"
#include "../dbdata.hpp"
using namespace sycl;
//
// A single row of the PARTSUPPLIER table
// with a subset of the columns (needed for this query)
//
class PartSupplierRow {
public:
PartSupplierRow() : valid(false), partkey(0), suppkey(0), supplycost(0) {}
PartSupplierRow(bool v_valid, DBIdentifier v_partkey, DBIdentifier v_suppkey,
DBDecimal v_supplycost)
: valid(v_valid),
partkey(v_partkey),
suppkey(v_suppkey),
supplycost(v_supplycost) {}
// NOTE: this is not true, but is key to be used by MapJoin
DBIdentifier PrimaryKey() const { return suppkey; }
bool valid;
DBIdentifier partkey;
DBIdentifier suppkey;
DBDecimal supplycost;
};
//
// A row of the join SUPPLIER and PARTSUPPLIER table
//
class SupplierPartSupplierJoined {
public:
SupplierPartSupplierJoined()
: valid(false), partkey(0), suppkey(0), supplycost(0), nationkey(0) {}
SupplierPartSupplierJoined(bool v_valid, DBIdentifier v_partkey,
DBIdentifier v_suppkey, DBDecimal v_supplycost,
unsigned char v_nationkey)
: valid(v_valid),
partkey(v_partkey),
suppkey(v_suppkey),
supplycost(v_supplycost),
nationkey(v_nationkey) {}
DBIdentifier PrimaryKey() const { return partkey; }
void Join(const unsigned char nation_key, const PartSupplierRow& ps_row) {
partkey = ps_row.partkey;
suppkey = ps_row.suppkey;
supplycost = ps_row.supplycost;
nationkey = nation_key;
}
bool valid;
DBIdentifier partkey;
DBIdentifier suppkey;
DBDecimal supplycost;
unsigned char nationkey;
};
//
// A single row of the ORDERS table
// with a subset of the columns (needed for this query)
//
class OrdersRow {
public:
OrdersRow() : valid(false), orderkey(0), orderdate(0) {}
OrdersRow(bool v_valid, DBIdentifier v_orderkey, DBDate v_orderdate)
: valid(v_valid), orderkey(v_orderkey), orderdate(v_orderdate) {}
DBIdentifier PrimaryKey() const { return orderkey; }
bool valid;
DBIdentifier orderkey;
DBDate orderdate;
};
//
// A single row of the LINEITEM table
// with a subset of the columns (needed for this query)
//
class LineItemMinimalRow {
public:
LineItemMinimalRow()
: valid(false), idx(0), orderkey(0), partkey(0), suppkey(0) {}
LineItemMinimalRow(bool v_valid, unsigned int v_idx, DBIdentifier v_orderkey,
DBIdentifier v_partkey, DBIdentifier v_suppkey)
: valid(v_valid),
idx(v_idx),
orderkey(v_orderkey),
partkey(v_partkey),
suppkey(v_suppkey) {}
DBIdentifier PrimaryKey() const { return orderkey; }
bool valid;
unsigned int idx;
DBIdentifier orderkey, partkey, suppkey;
};
//
// A row of the join LINEITEM and ORDERS table
//
class LineItemOrdersMinimalJoined {
public:
LineItemOrdersMinimalJoined()
: valid(false), lineitemIdx(0), partkey(0), suppkey(0), orderdate(0) {}
LineItemOrdersMinimalJoined(bool v_valid, unsigned int v_lineitem_idx,
DBIdentifier v_partkey, DBIdentifier v_suppkey,
DBDate v_orderdate)
: valid(v_valid),
lineitemIdx(v_lineitem_idx),
partkey(v_partkey),
suppkey(v_suppkey),
orderdate(v_orderdate) {}
DBIdentifier PrimaryKey() { return partkey; }
void Join(const OrdersRow& o_row, const LineItemMinimalRow& li_row) {
lineitemIdx = li_row.idx;
partkey = li_row.partkey;
suppkey = li_row.suppkey;
orderdate = o_row.orderdate;
}
bool valid;
unsigned int lineitemIdx;
DBIdentifier partkey;
DBIdentifier suppkey;
DBDate orderdate;
};
//
// Datatype to be sent to be sorted by the FifoSorter
//
class SortData {
public:
SortData() {}
SortData(unsigned int v_lineitem_idx, DBIdentifier v_partkey,
DBIdentifier v_suppkey, DBDate v_orderdate)
: lineitemIdx(v_lineitem_idx),
partkey(v_partkey),
suppkey(v_suppkey),
orderdate(v_orderdate) {}
SortData(const LineItemOrdersMinimalJoined& d)
: lineitemIdx(d.lineitemIdx),
partkey(d.partkey),
suppkey(d.suppkey),
orderdate(d.orderdate) {}
bool operator<(const SortData& t) const { return partkey < t.partkey; }
bool operator>(const SortData& t) const { return partkey > t.partkey; }
bool operator<=(const SortData& t) const { return partkey <= t.partkey; }
bool operator>=(const SortData& t) const { return partkey >= t.partkey; }
bool operator==(const SortData& t) const { return partkey == t.partkey; }
bool operator!=(const SortData& t) const { return partkey != t.partkey; }
unsigned int lineitemIdx;
DBIdentifier partkey;
DBIdentifier suppkey;
DBDate orderdate;
};
//
// The final data used to compute the 'amount'
//
class FinalData {
public:
FinalData()
: valid(false),
partkey(0),
lineitemIdx(0),
orderdate(0),
supplycost(0),
nationkey(0) {}
FinalData(bool v_valid, DBIdentifier v_partkey, unsigned int v_lineitem_idx,
DBDate v_orderdate, DBDecimal v_supplycost,
unsigned char v_nationkey)
: valid(v_valid),
partkey(v_partkey),
lineitemIdx(v_lineitem_idx),
orderdate(v_orderdate),
supplycost(v_supplycost),
nationkey(v_nationkey) {}
DBIdentifier PrimaryKey() { return partkey; }
void Join(const SupplierPartSupplierJoined& s_ps_row,
const LineItemOrdersMinimalJoined& li_o_row) {
valid = s_ps_row.suppkey == li_o_row.suppkey;
partkey = s_ps_row.partkey;
lineitemIdx = li_o_row.lineitemIdx;
orderdate = li_o_row.orderdate;
supplycost = s_ps_row.supplycost;
nationkey = s_ps_row.nationkey;
}
bool valid;
DBIdentifier partkey;
unsigned int lineitemIdx;
DBDate orderdate;
DBDecimal supplycost;
unsigned char nationkey;
};
// joining window sizes
constexpr int kRegexFilterElementsPerCycle = 1;
constexpr int kOrdersJoinWinSize = 1;
constexpr int kLineItemJoinWinSize = 2;
constexpr int kLineItemOrdersJoinWinSize = kLineItemJoinWinSize;
constexpr int kLineItemOrdersSortedWinSize = 1;
constexpr int kPartSupplierDuplicatePartkeys = 4;
constexpr int kFinalDataMaxSize =
kPartSupplierDuplicatePartkeys * kLineItemOrdersSortedWinSize;
// pipe data
using LineItemMinimalRowPipeData =
StreamingData<LineItemMinimalRow, kLineItemJoinWinSize>;
using OrdersRowPipeData =
StreamingData<OrdersRow, kOrdersJoinWinSize>;
using LineItemOrdersMinimalJoinedPipeData =
StreamingData<LineItemOrdersMinimalJoined, kLineItemOrdersJoinWinSize>;
using LineItemOrdersMinimalSortedPipeData =
StreamingData<LineItemOrdersMinimalJoined, 1>;
using PartSupplierRowPipeData =
StreamingData<PartSupplierRow, kPartSupplierDuplicatePartkeys>;
using SupplierPartSupplierJoinedPipeData =
StreamingData<SupplierPartSupplierJoined, kPartSupplierDuplicatePartkeys>;
using FinalPipeData =
StreamingData<FinalData, kFinalDataMaxSize>;
// pipes
using LineItemPipe =
sycl::pipe<class LineItemPipeClass, LineItemMinimalRowPipeData>;
using OrdersPipe =
sycl::pipe<class OrdersPipeClass, OrdersRowPipeData>;
using LineItemOrdersPipe =
sycl::pipe<class LineItemOrdersPipeClass,
LineItemOrdersMinimalJoinedPipeData>;
using LineItemOrdersSortedPipe =
sycl::pipe<class LineItemOrdersSortedPipeClass,
LineItemOrdersMinimalSortedPipeData>;
using PartSupplierPartsPipe =
sycl::pipe<class PartSupplierPartsPipeClass,
SupplierPartSupplierJoinedPipeData>;
using PartSupplierPipe =
sycl::pipe<class PartSupplierPipeClass, PartSupplierRowPipeData>;
using FinalPipe =
sycl::pipe<class FinalPipeClass, FinalPipeData>;
#endif /* __PIPE_TYPES_H__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query12/query12_kernel.cpp | #include <array>
#include <limits>
#include <stdio.h>
#include "query12_kernel.hpp"
#include "pipe_types.hpp"
#include "../db_utils/MergeJoin.hpp"
#include "../db_utils/Unroller.hpp"
#include "../db_utils/Tuple.hpp"
using namespace std::chrono;
// kernel class names
class LineItemProducer;
class OrdersProducer;
class Join;
class Compute;
bool SubmitQuery12(queue& q, Database& dbinfo, DBDate low_date,
DBDate high_date, int shipmode1, int shipmode2,
std::array<DBDecimal, 2>& high_line_count,
std::array<DBDecimal, 2>& low_line_count,
double& kernel_latency, double& total_latency) {
// create space for the input buffers
// LINEITEM table
buffer l_orderkey_buf(dbinfo.l.orderkey);
buffer l_shipmode_buf(dbinfo.l.shipmode);
buffer l_commitdate_buf(dbinfo.l.commitdate);
buffer l_shipdate_buf(dbinfo.l.shipdate);
buffer l_receiptdate_buf(dbinfo.l.receiptdate);
// ORDERS table
buffer o_orderkey_buf(dbinfo.o.orderkey);
buffer o_orderpriority_buf(dbinfo.o.orderpriority);
// setup the output buffers
buffer high_line_count_buf(high_line_count);
buffer low_line_count_buf(low_line_count);
// number of producing iterations depends on the number of elements per cycle
const size_t l_rows = dbinfo.l.rows;
const size_t l_iters =
(l_rows + kLineItemJoinWindowSize - 1) / kLineItemJoinWindowSize;
const size_t o_rows = dbinfo.o.rows;
const size_t o_iters =
(o_rows + kOrderJoinWindowSize - 1) / kOrderJoinWindowSize;
// start timer
high_resolution_clock::time_point host_start = high_resolution_clock::now();
/////////////////////////////////////////////////////////////////////////////
//// LineItemProducer Kernel: produce the LINEITEM table
auto produce_lineitem_event = q.submit([&](handler& h) {
size_t l_rows = dbinfo.l.rows;
accessor l_orderkey_accessor(l_orderkey_buf, h, read_only);
accessor l_shipmode_accessor(l_shipmode_buf, h, read_only);
accessor l_commitdate_accessor(l_commitdate_buf, h, read_only);
accessor l_shipdate_accessor(l_shipdate_buf, h, read_only);
accessor l_receiptdate_accessor(l_receiptdate_buf, h, read_only);
h.single_task<LineItemProducer>([=]() [[intel::kernel_args_restrict]] {
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < l_iters + 1; i++) {
bool done = (i == l_iters);
bool valid = (i != l_iters);
// bulk read of data from global memory
NTuple<kLineItemJoinWindowSize, LineItemRow> data;
UnrolledLoop<0, kLineItemJoinWindowSize>([&](auto j) {
size_t idx = (i*kLineItemJoinWindowSize + j);
bool in_range = idx < l_rows;
DBIdentifier key_tmp = l_orderkey_accessor[idx];
int shipmode = l_shipmode_accessor[idx];
DBDate commitdate = l_commitdate_accessor[idx];
DBDate shipdate = l_shipdate_accessor[idx];
DBDate receiptdate = l_receiptdate_accessor[idx];
DBIdentifier key =
in_range ? key_tmp : std::numeric_limits<DBIdentifier>::max();
data.get<j>() = LineItemRow(in_range, key, shipmode, commitdate,
shipdate, receiptdate);
});
// write to pipe
LineItemProducerPipe::write(LineItemRowPipeData(done, valid, data));
}
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// OrdersProducer Kernel: produce the ORDERS table
auto produce_orders_event = q.submit([&](handler& h) {
size_t o_rows = dbinfo.o.rows;
accessor o_orderkey_accessor(o_orderkey_buf, h, read_only);
accessor o_orderpriority_accessor(o_orderpriority_buf, h, read_only);
h.single_task<OrdersProducer>([=]() [[intel::kernel_args_restrict]] {
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < o_iters + 1; i++) {
bool done = (i == o_iters);
bool valid = (i != o_iters);
// bulk read of data from global memory
NTuple<kOrderJoinWindowSize, OrdersRow> data;
UnrolledLoop<0, kOrderJoinWindowSize>([&](auto j) {
size_t idx = (i*kOrderJoinWindowSize + j);
bool in_range = idx < o_rows;
DBIdentifier key_tmp = o_orderkey_accessor[idx];
int orderpriority = o_orderpriority_accessor[idx];
DBIdentifier key =
in_range ? key_tmp : std::numeric_limits<DBIdentifier>::max();
data.get<j>() = OrdersRow(in_range, key, orderpriority);
});
// write to pipe
OrdersProducerPipe::write(OrdersRowPipeData(done, valid, data));
}
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// Join kernel
auto join_event = q.submit([&](handler& h) {
// streaming query12 computation
h.single_task<Join>([=]() [[intel::kernel_args_restrict]] {
MergeJoin<OrdersProducerPipe, OrdersRow, kOrderJoinWindowSize,
LineItemProducerPipe, LineItemRow, kLineItemJoinWindowSize,
JoinedProducerPipe, JoinedRow>();
// join is done, tell downstream
JoinedProducerPipe::write(JoinedRowPipeData(true, false));
});
});
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
//// Compute Kernel
auto compute_event = q.submit([&](handler& h) {
// output write accessors
accessor high_line_count_accessor(high_line_count_buf, h, write_only, no_init);
accessor low_line_count_accessor(low_line_count_buf, h, write_only, no_init);
h.single_task<Compute>([=]() [[intel::kernel_args_restrict]] {
// local accumulators
DBDecimal high_line_count1_local = 0, high_line_count2_local = 0;
DBDecimal low_line_count1_local = 0, low_line_count2_local = 0;
bool done;
[[intel::initiation_interval(1)]]
do {
// get joined row from pipe
JoinedRowPipeData joined_data = JoinedProducerPipe::read();
// upstream kernel tells this kernel when it is done
done = joined_data.done;
if (!done && joined_data.valid) {
DBDecimal high_line_count1_local_tmp[kLineItemJoinWindowSize];
DBDecimal low_line_count1_local_tmp[kLineItemJoinWindowSize];
DBDecimal high_line_count2_local_tmp[kLineItemJoinWindowSize];
DBDecimal low_line_count2_local_tmp[kLineItemJoinWindowSize];
UnrolledLoop<0, kLineItemJoinWindowSize>([&](auto i) {
// determine 'where' criteria of query
const bool is_shipmode1 =
(joined_data.data.get<i>().shipmode == shipmode1);
const bool is_shipmode2 =
(joined_data.data.get<i>().shipmode == shipmode2);
const bool valid_shipmode = (is_shipmode1 || is_shipmode2);
const bool valid_commitdate =
(joined_data.data.get<i>().commitdate <
joined_data.data.get<i>().receiptdate);
const bool valid_shipdate = (joined_data.data.get<i>().shipdate <
joined_data.data.get<i>().commitdate);
const bool receipt_within_year_of_date =
((joined_data.data.get<i>().receiptdate >= low_date) &&
(joined_data.data.get<i>().receiptdate < high_date));
const bool urgent_or_high =
(joined_data.data.get<i>().orderpriority == 1 ||
joined_data.data.get<i>().orderpriority == 2);
const bool do_computation = joined_data.data.get<i>().valid &&
valid_shipmode && valid_commitdate && valid_shipdate &&
receipt_within_year_of_date;
if (do_computation) {
// is this order priority urgent or high
const DBDecimal high_line_val = urgent_or_high ? 1 : 0;
const DBDecimal low_line_val = urgent_or_high ? 0 : 1;
high_line_count1_local_tmp[i] = is_shipmode1 ? high_line_val : 0;
low_line_count1_local_tmp[i] = is_shipmode1 ? low_line_val : 0;
high_line_count2_local_tmp[i] = is_shipmode2 ? high_line_val : 0;
low_line_count2_local_tmp[i] = is_shipmode2 ? low_line_val : 0;
} else {
high_line_count1_local_tmp[i] = 0;
low_line_count1_local_tmp[i] = 0;
high_line_count2_local_tmp[i] = 0;
low_line_count2_local_tmp[i] = 0;
}
});
// this creates an adder reduction tree from *_local_tmp to *_local
UnrolledLoop<0, kLineItemJoinWindowSize>([&](auto i) {
high_line_count1_local += high_line_count1_local_tmp[i];
low_line_count1_local += low_line_count1_local_tmp[i];
high_line_count2_local += high_line_count2_local_tmp[i];
low_line_count2_local += low_line_count2_local_tmp[i];
});
}
} while (!done);
// write back the local data to global memory
high_line_count_accessor[0] = high_line_count1_local;
high_line_count_accessor[1] = high_line_count2_local;
low_line_count_accessor[0] = low_line_count1_local;
low_line_count_accessor[1] = low_line_count2_local;
});
});
/////////////////////////////////////////////////////////////////////////////
// wait for the Compute kernel to finish
produce_orders_event.wait();
produce_lineitem_event.wait();
join_event.wait();
compute_event.wait();
// stop timer
high_resolution_clock::time_point host_end = high_resolution_clock::now();
duration<double, std::milli> diff = host_end - host_start;
//// gather profiling info
auto start_time =
compute_event.get_profiling_info<info::event_profiling::command_start>();
auto end_time =
compute_event.get_profiling_info<info::event_profiling::command_end>();
// calculating the kernel execution time in ms
auto kernel_execution_time = (end_time - start_time) * 1e-6;
kernel_latency = kernel_execution_time;
total_latency = diff.count();
return true;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query12/pipe_types.hpp | #ifndef __PIPE_TYPES_H__
#define __PIPE_TYPES_H__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../db_utils/StreamingData.hpp"
#include "../dbdata.hpp"
using namespace sycl;
//
// A single row of the ORDERS table
// with a subset of the columns (needed for this query)
//
class OrdersRow {
public:
OrdersRow() : valid(false), orderkey(0), orderpriority(0) {}
OrdersRow(bool v_valid, DBIdentifier v_key, int v_orderpriority)
: valid(v_valid), orderkey(v_key), orderpriority(v_orderpriority) {}
DBIdentifier PrimaryKey() const { return orderkey; }
bool valid;
DBIdentifier orderkey;
int orderpriority;
};
//
// A single row of the LINEITEM table
// with a subset of the columns (needed for this query)
//
class LineItemRow {
public:
LineItemRow()
: valid(false),
orderkey(0),
shipmode(0),
commitdate(0),
shipdate(0),
receiptdate(0) {}
LineItemRow(bool v_valid, DBIdentifier v_key, int v_shipmode,
DBDate v_commitdate, DBDate v_shipdate, DBDate v_receiptdate)
: valid(v_valid),
orderkey(v_key),
shipmode(v_shipmode),
commitdate(v_commitdate),
shipdate(v_shipdate),
receiptdate(v_receiptdate) {}
DBIdentifier PrimaryKey() const { return orderkey; }
bool valid;
DBIdentifier orderkey;
int shipmode;
DBDate commitdate;
DBDate shipdate;
DBDate receiptdate;
};
//
// A row of the join LINEITEM and ORDERS table
//
class JoinedRow {
public:
JoinedRow()
: valid(false),
orderpriority(0),
shipmode(0),
commitdate(0),
shipdate(0),
receiptdate(0) {}
JoinedRow(bool v_valid, DBIdentifier v_key, int v_orderpriority, int v_shipmode,
DBDate v_commitdate, DBDate v_shipdate, DBDate v_receiptdate)
: valid(v_valid),
orderpriority(v_orderpriority),
shipmode(v_shipmode),
commitdate(v_commitdate),
shipdate(v_shipdate),
receiptdate(v_receiptdate) {}
void Join(const OrdersRow& o_row, const LineItemRow& l_row) {
orderpriority = o_row.orderpriority;
shipmode = l_row.shipmode;
commitdate = l_row.commitdate;
shipdate = l_row.shipdate;
receiptdate = l_row.receiptdate;
}
bool valid;
int orderpriority;
int shipmode;
DBDate commitdate;
DBDate shipdate;
DBDate receiptdate;
};
// JOIN window sizes
constexpr int kOrderJoinWindowSize = 4;
constexpr int kLineItemJoinWindowSize = 8;
// pipe data types
using OrdersRowPipeData = StreamingData<OrdersRow, kOrderJoinWindowSize>;
using LineItemRowPipeData = StreamingData<LineItemRow, kLineItemJoinWindowSize>;
using JoinedRowPipeData = StreamingData<JoinedRow, kLineItemJoinWindowSize>;
// the pipes
using OrdersProducerPipe =
pipe<class OrdersProducerPipeClass, OrdersRowPipeData>;
using LineItemProducerPipe =
pipe<class LineItemProducerPipeClass, LineItemRowPipeData>;
using JoinedProducerPipe =
pipe<class JoinedProducerPipeClass, JoinedRowPipeData>;
#endif /* __PIPE_TYPES_H__ */
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query12/query12_kernel.hpp | #ifndef __QUERY12_KERNEL_HPP__
#define __QUERY12_KERNEL_HPP__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../dbdata.hpp"
using namespace sycl;
bool SubmitQuery12(queue& q, Database& dbinfo,
DBDate low_date, DBDate high_date,
int shipmode1, int shipmode2,
std::array<DBDecimal, 2>& high_line_count,
std::array<DBDecimal, 2>& low_line_count,
double& kernel_latency, double& total_latency);
#endif //__QUERY12_KERNEL_HPP__
| hpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query11/query11_kernel.cpp | #include <stdio.h>
#include <type_traits>
#include "query11_kernel.hpp"
#include "pipe_types.hpp"
#include "../db_utils/CachedMemory.hpp"
#include "../db_utils/MapJoin.hpp"
#include "../db_utils/Misc.hpp"
#include "../db_utils/Tuple.hpp"
#include "../db_utils/Unroller.hpp"
#include "../db_utils/fifo_sort.hpp"
#include "onchip_memory_with_cache.hpp" // DirectProgramming/C++SYCL_FPGA/include
using namespace std::chrono;
// kernel class names
class ProducePartSupplier;
class JoinPartSupplierParts;
class Compute;
class FifoSort;
class ConsumeSort;
///////////////////////////////////////////////////////////////////////////////
// sort configuration
using SortType = OutputData;
constexpr int kNumSortStages = CeilLog2(kPartTableSize);
constexpr int kSortSize = Pow2(kNumSortStages);
static_assert(kPartTableSize <= kSortSize,
"Must be able to sort all part keys");
// comparator for the sorter to sort in descending order
struct GreaterThan {
inline bool operator()(const SortType& a, const SortType& b) {
return a.partvalue > b.partvalue;
}
};
// input and output pipes for the sorter
using SortInPipe = pipe<class SortInputPipe, SortType>;
using SortOutPipe = pipe<class SortOutputPipe, SortType>;
///////////////////////////////////////////////////////////////////////////////
bool SubmitQuery11(queue& q, Database& dbinfo, std::string& nation,
std::vector<DBIdentifier>& partkeys,
std::vector<DBDecimal>& values,
double& kernel_latency, double& total_latency) {
// find the nationkey based on the nation name
assert(dbinfo.n.name_key_map.find(nation) != dbinfo.n.name_key_map.end());
unsigned char nationkey = dbinfo.n.name_key_map[nation];
// ensure correctly sized output buffers
partkeys.resize(kPartTableSize);
values.resize(kPartTableSize);
// create space for the input buffers
// SUPPLIER
buffer s_nationkey_buf(dbinfo.s.nationkey);
// PARTSUPPLIER
buffer ps_partkey_buf(dbinfo.ps.partkey);
buffer ps_suppkey_buf(dbinfo.ps.suppkey);
buffer ps_availqty_buf(dbinfo.ps.availqty);
buffer ps_supplycost_buf(dbinfo.ps.supplycost);
// setup the output buffers
buffer partkeys_buf(partkeys);
buffer values_buf(values);
// number of producing iterations depends on the number of elements per cycle
const size_t ps_rows = dbinfo.ps.rows;
const size_t ps_iters = (ps_rows + kJoinWinSize - 1) / kJoinWinSize;
// start timer
high_resolution_clock::time_point host_start = high_resolution_clock::now();
///////////////////////////////////////////////////////////////////////////
//// ProducePartSupplier Kernel
auto produce_ps_event = q.submit([&](handler& h) {
// PARTSUPPLIER table accessors
accessor ps_partkey_accessor(ps_partkey_buf, h, read_only);
accessor ps_suppkey_accessor(ps_suppkey_buf, h, read_only);
accessor ps_availqty_accessor(ps_availqty_buf, h, read_only);
accessor ps_supplycost_accessor(ps_supplycost_buf, h, read_only);
// kernel to produce the PARTSUPPLIER table
h.single_task<ProducePartSupplier>([=]() [[intel::kernel_args_restrict]] {
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < ps_iters; i++) {
// bulk read of data from global memory
NTuple<kJoinWinSize, PartSupplierRow> data;
UnrolledLoop<0, kJoinWinSize>([&](auto j) {
size_t idx = i * kJoinWinSize + j;
bool in_range = idx < ps_rows;
DBIdentifier partkey = ps_partkey_accessor[idx];
DBIdentifier suppkey = ps_suppkey_accessor[idx];
int availqty = ps_availqty_accessor[idx];
DBDecimal supplycost = ps_supplycost_accessor[idx];
data.get<j>() =
PartSupplierRow(in_range, partkey, suppkey, availqty, supplycost);
});
// write to pipe
ProducePartSupplierPipe::write(
PartSupplierRowPipeData(false, true, data));
}
// tell the downstream kernel we are done producing data
ProducePartSupplierPipe::write(PartSupplierRowPipeData(true, false));
});
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// JoinPartSupplierParts Kernel
auto join_event = q.submit([&](handler& h) {
// SUPPLIER table accessors
size_t s_rows = dbinfo.s.rows;
accessor s_nationkey_accessor(s_nationkey_buf, h, read_only);
h.single_task<JoinPartSupplierParts>([=]() [[intel::kernel_args_restrict]] {
// initialize the array map
// +1 is to account for fact that SUPPKEY is [1,kSF*10000]
unsigned char nation_key_map_data[kSupplierTableSize + 1];
bool nation_key_map_valid[kSupplierTableSize + 1];
for (int i = 0; i < kSupplierTableSize + 1; i++) {
nation_key_map_valid[i] = false;
}
// populate MapJoiner map
// why a map? keys may not be sequential
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < s_rows; i++) {
// NOTE: based on TPCH docs, SUPPKEY is guaranteed to be unique
// in the range [1:kSF*10000]
DBIdentifier s_suppkey = i + 1;
unsigned char s_nationkey = s_nationkey_accessor[i];
nation_key_map_data[s_suppkey] = s_nationkey;
nation_key_map_valid[s_suppkey] = true;
}
// MAPJOIN PARTSUPPLIER and SUPPLIER tables by suppkey
MapJoin<unsigned char, ProducePartSupplierPipe, PartSupplierRow,
kJoinWinSize, PartSupplierPartsPipe,
SupplierPartSupplierJoined>(nation_key_map_data,
nation_key_map_valid);
// tell downstream we are done
PartSupplierPartsPipe::write(
SupplierPartSupplierJoinedPipeData(true,false));
});
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// Compute Kernel
auto compute_event = q.single_task<Compute>([=] {
constexpr int kAccumCacheSize = 15;
fpga_tools::OnchipMemoryWithCache<DBDecimal, kPartTableSize,
kAccumCacheSize> partkey_values;
// initialize accumulator
partkey_values.init(0);
bool done = false;
[[intel::initiation_interval(1)]]
while (!done) {
bool valid_pipe_read;
SupplierPartSupplierJoinedPipeData pipe_data =
PartSupplierPartsPipe::read(valid_pipe_read);
done = pipe_data.done && valid_pipe_read;
if (valid_pipe_read && !done) {
UnrolledLoop<0, kJoinWinSize>([&](auto j) {
SupplierPartSupplierJoined data = pipe_data.data.template get<j>();
if (data.valid && data.nationkey == nationkey) {
// partkeys start at 1
DBIdentifier index = data.partkey - 1;
DBDecimal val = data.supplycost * (DBDecimal)(data.availqty);
auto curr_val = partkey_values.read(index);
partkey_values.write(index, curr_val + val);
}
});
}
}
// sort the {partkey, partvalue} pairs based on partvalue.
// we will send in kSortSize - kPartTableSize dummy values with a
// minimum value so that they are last (sorting from highest to lowest)
[[intel::initiation_interval(1)]]
for (size_t i = 0; i < kSortSize; i++) {
size_t key = (i < kPartTableSize) ? (i + 1) : 0;
auto val = (i < kPartTableSize) ? partkey_values.read(i)
: std::numeric_limits<DBDecimal>::min();
SortInPipe::write(OutputData(key, val));
}
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// ConsumeSort kernel
auto consume_sort_event = q.submit([&](handler& h) {
// output buffer accessors
accessor partkeys_accessor(partkeys_buf, h, write_only, no_init);
accessor values_accessor(values_buf, h, write_only, no_init);
h.single_task<ConsumeSort>([=]() [[intel::kernel_args_restrict]] {
int i = 0;
bool i_in_range = 0 < kSortSize;
bool i_next_in_range = 1 < kSortSize;
bool i_in_parttable_range = 0 < kPartTableSize;
bool i_next_in_parttable_range = 1 < kPartTableSize;
// grab all kSortSize elements from the sorter
[[intel::initiation_interval(1)]]
while (i_in_range) {
bool pipe_read_valid;
OutputData D = SortOutPipe::read(pipe_read_valid);
if (pipe_read_valid) {
if (i_in_parttable_range) {
partkeys_accessor[i] = D.partkey;
values_accessor[i] = D.partvalue;
}
i_in_range = i_next_in_range;
i_next_in_range = i < kSortSize - 2;
i_in_parttable_range = i_next_in_parttable_range;
i_next_in_parttable_range = i < kPartTableSize - 2;
i++;
}
}
});
});
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//// FifoSort Kernel
auto sort_event = q.single_task<FifoSort>([=] {
ihc::sort<SortType, kSortSize, SortInPipe, SortOutPipe>(GreaterThan());
});
///////////////////////////////////////////////////////////////////////////
// wait for kernels to finish
produce_ps_event.wait();
join_event.wait();
compute_event.wait();
sort_event.wait();
consume_sort_event.wait();
high_resolution_clock::time_point host_end = high_resolution_clock::now();
duration<double, std::milli> diff = host_end - host_start;
// gather profiling info
auto start_time =
consume_sort_event
.get_profiling_info<info::event_profiling::command_start>();
auto end_time = consume_sort_event
.get_profiling_info<info::event_profiling::command_end>();
// calculating the kernel execution time in ms
auto kernel_execution_time = (end_time - start_time) * 1e-6;
kernel_latency = kernel_execution_time;
total_latency = diff.count();
return true;
}
| cpp |
oneAPI-samples | data/projects/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/src/query11/query11_kernel.hpp | #ifndef __QUERY11_KERNEL_HPP__
#define __QUERY11_KERNEL_HPP__
#pragma once
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include "../dbdata.hpp"
using namespace sycl;
bool SubmitQuery11(queue& q, Database& dbinfo,
std::string& nation,
std::vector<DBIdentifier>& partkeys,
std::vector<DBDecimal>& values,
double& kernel_latency, double& total_latency);
#endif //__QUERY11_KERNEL_HPP__
| hpp |
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