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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx Inc.
// Engineer: Parimal Patel
// Create Date: 06/21/2016 09:22:41 AM
// Module Name: PdmDes
// Project Name: PYNQ
//////////////////////////////////////////////////////////////////////////////////
module PdmDes(
input clk,
input en,
output done,
output [15:0] dout,
output pdm_m_clk_o,
input pdm_m_data_i
);
parameter C_PDM_FREQ_HZ=;
reg en_int=0;
reg done_int=0;
reg clk_int=0;
reg pdm_clk_rising;
reg [15:0] pdm_tmp, dout;
integer cnt_bits=0;
integer cnt_clk=0;
assign done = done_int;
assign pdm_m_clk_o = clk_int;
// register en input
always @(posedge clk)
en_int <= en;
// Sample input serial data process
always @(posedge clk)
if (en==0)
pdm_tmp <= 0;
else
if (pdm_clk_rising)
pdm_tmp <= {pdm_tmp[14:0],pdm_m_data_i};
// Count the number of sampled bits
always @(posedge clk)
begin
if (en_int==0)
cnt_bits <=0;
else
if (pdm_clk_rising)
begin
if (cnt_bits == 15)
cnt_bits <=0;
else
cnt_bits <= cnt_bits + 1;
end
end
// Generate the done signal
always @(posedge clk)
begin
if (pdm_clk_rising)
begin
if (cnt_bits==0)
begin
if (en_int)
begin
done_int<=1;
dout <= pdm_tmp;
end
end
end
else
done_int <= 0;
end
// Generate PDM Clock, that runs independent from the enable signal, therefore
// the onboard microphone will always send data
always @(posedge clk)
begin
// clk_int <= 0;
if (cnt_clk == 24) // (C_SYS_CLK_FREQ_MHZ*)/(C_PDM_FREQ_HZ*2))-1 where C_SYS_CLK_FREQ_MHZ=100, C_PDM_FREQ_HZ=2MHz
begin
cnt_clk <= 0;
clk_int <= ~clk_int;
if (clk_int == 0)
pdm_clk_rising <= 1;
end
else
begin
cnt_clk <= cnt_clk + 1;
pdm_clk_rising <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct S { int a, b; S() {} S(int _a, int _b) { a = _a; b = _b; } const bool operator<(const S &o) const { return a < o.a; } }; string exm; inline void exf(void) { cout << exm << n ; exit(0); } template <typename T> inline void showAll(vector<T> &v, string sep = ) { for (T &here : v) cout << here << sep; } template <typename T> inline void showAll(T arr[], int st, int end, string sep = ) { for (int i = st; i <= end; i++) cout << arr[i] << sep; } template <typename T> inline vector<int> int_seperation(T N, int d = 10) { vector<int> v; while (N) { v.push_back(N % d); N /= d; } reverse(v.begin(), v.end()); return v; } const int SIZE = 500009; char s[SIZE], t[SIZE]; int main() { int n, k; scanf( %d %d , &n, &k); scanf( %s %s , s + 1, t + 1); long long INF = 1e18, ans = 0, diff = 0; for (int i = 1; i <= n; i++) { diff = 2 * diff + (t[i] - s[i]); diff = min(diff, INF); ans += min(diff + 1, (long long)k); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string b; cin >> b; if (b.length() < 4) { cout << b << n ; continue; } cout << b[0]; for (int i = 1; i < b.length(); i += 2) { cout << b[i]; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; inline int read() { int a = 0; char c = getchar(); bool f = 0; while (!isdigit(c)) { if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) { a = (a << 3) + (a << 1) + (c ^ 0 ); c = getchar(); } return f ? -a : a; } int point[51][3], N; void solve(int l, int r, int dir) { if (l == r) printf( (%01d*abs(((1-abs((t-%d)))+abs((abs((t-%d))-1))))) , point[l][dir] / 2, l, l); else { putchar( ( ); solve(l, l + r >> 1, dir); putchar( + ); solve((l + r >> 1) + 1, r, dir); putchar( ) ); } } int main() { N = read(); for (int i = 1; i <= N; ++i) { point[i][0] = read(); point[i][1] = read(); point[i][2] = read(); } solve(1, N, 0); putchar( n ); solve(1, N, 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, tot, arr[105], sum[100050][105], a[100050], s[105]; bool Solved(int x, int y) { for (int i = 1; i <= tot; ++i) if (sum[y][i] - sum[x - 1][i] < s[i]) return false; return true; } int main() { long long ans; scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); int t = k; for (int i = 2; i * i <= t; ++i) if (t % i == 0) { arr[++tot] = i; for (; t % i == 0; t /= i) s[tot]++; } if (t > 1) arr[++tot] = t, s[tot] = 1; for (int i = 1; i <= n; ++i) for (int j = 1; j <= tot; ++j) for (; a[i] % arr[j] == 0; a[i] /= arr[j]) sum[i][j]++; for (int i = 1; i <= n; ++i) for (int j = 1; j <= tot; ++j) sum[i][j] += sum[i - 1][j]; ans = 0; for (int i = 1, L, R, mid; i <= n; ++i) { L = i - 1; R = n + 1; while (L + 1 < R) { mid = (L + R) / 2; if (Solved(i, mid)) R = mid; else L = mid; } ans += n - R + 1; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int BITS(long long __a) { short int __c = 0; __a <<= 1; while (__a) __c += ((__a >>= 1) & 1); return __c; } inline bool prime(int n) { for (int i = 3; i * i <= n; i += 2) if (n % i == 0) return false; return true; } set<int> s; int N, M, V[100010], A[100010]; int main() { cin >> N >> M; for (int i = 0; i < N; i++) cin >> V[i]; s.insert(V[N - 1]); A[N - 1] = 1; for (int i = N - 2; i >= 0; i--) { s.insert(V[i]); A[i] = ((int)s.size()); } for (int i = 0; i < M; i++) { int j; cin >> j; cout << A[j - 1] << endl; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } int lo = 0, hi = m; while (lo < hi) { int mid = (lo + hi) / 2; int last = 0; bool b = true; for (int i = 0; i < n; ++i) { int delta = (last - a[i] + m) % m; if (delta <= mid) continue; if (a[i] < last) { b = false; break; } last = a[i]; } if (b) { hi = mid; } else { lo = mid + 1; } } cout << lo << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDLXTP_PP_SYMBOL_V
/**
* sdlxtp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> arr[100005]; vector<int> v1[100005]; int visited[100005]; stack<int> s; int n, m; set<int> se[100005]; void dfs(int node) { int i; visited[node] = 1; int n = v1[node].size(); for (i = 0; i < n; i++) { if (visited[v1[node][i]] == 0) { dfs(v1[node][i]); } } s.push(node); } bool check(int mid) { int i; bool ans = true; for (i = 1; i <= mid; i++) { v1[arr[i].first].push_back(arr[i].second); se[arr[i].first].insert(arr[i].second); } for (i = 1; i <= n; i++) visited[i] = 0; for (i = 1; i <= n; i++) { if (visited[i] == 0) { dfs(i); } } int x; x = s.top(); s.pop(); while (!s.empty()) { if (se[x].find(s.top()) == se[x].end()) ans = false; x = s.top(); s.pop(); } for (i = 1; i <= n; i++) { v1[i].clear(); se[i].clear(); } return ans; } int main() { int i, j, k; scanf( %d , &n); scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d , &arr[i].first); scanf( %d , &arr[i].second); } int l = 0, r = m, mid; while (l <= r) { mid = (l + r) / 2; bool temp1 = check(mid); if (mid == m) { if (temp1 == false) { printf( -1 n ); return 0; } else { r = mid - 1; continue; } } bool temp2 = check(mid + 1); if (temp1 == false && temp2 == true) { printf( %d n , mid + 1); return 0; } else if (temp2 == true) { r = mid - 1; } else { l = mid + 1; } } printf( -1 n ); return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_load (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct people { int a, d, id; bool operator<(people other) const { if (a != other.a) return a > other.a; return id < other.id; } }; people s[111]; int n; int main() { int i, j, ans = 0; scanf( %d , &n); for (i = 1; i <= n; ++i) { scanf( %d%d , &s[i].a, &s[i].d); s[i].id = i; } sort(s + 1, s + 1 + n); vector<int> ret; for (i = 1; i <= n; ++i) { if (s[i].d < 0) { ret.push_back(s[i].id); } } for (auto v : ret) { for (i = 1; i <= n; ++i) { if (s[i].id == v) { j = i; while (j < n && (s[j].a + s[j].d < s[j + 1].a || (s[j].a + s[j].d == s[j + 1].a && s[j].id > s[j + 1].id))) { swap(s[j], s[j + 1]); ans++; j++; } s[j].a = s[j].a + s[j].d; break; } } } ret.clear(); for (i = n; i >= 1; --i) { if (s[i].d > 0) { ret.push_back(s[i].id); } } for (auto v : ret) { for (i = n; i >= 1; --i) { if (s[i].id == v) { j = i; while (j > 1 && (s[j].a + s[j].d > s[j - 1].a || (s[j].a + s[j].d == s[j - 1].a && s[j].id < s[j - 1].id))) { swap(s[j], s[j - 1]); ans++; j--; } s[j].a = s[j].a + s[j].d; break; } } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int MOD = 1e9 + 7; long long int INF = 1e18; long long int sub(long long int a, long long int b, long long int p = MOD) { return ((a % p) - (b % p) + p) % p; } long long int mult(long long int a, long long int b, long long int p = MOD) { return ((a % p) * (b % p)) % p; } long long int add(long long int a, long long int b, long long int p = MOD) { return (a % p + b % p) % p; } long long int fpow(long long int n, long long int k, long long int p = MOD) { long long int r = 1; while (k > 0) { if (k & 1) r = r * n % p; n = n * n % p; k = k >> 1; } return r; } long long int inv(long long int a, long long int p = MOD) { return fpow(a, p - 2, p); } long long int power(long long int a, long long int b) { long long int ans = 1; long long int i; for (i = 1; i < b + 1; i++) { ans *= a; } return ans; } long long int fdiv(long long int a, long long int b, long long int p = MOD) { long long int yinv = inv(b); long long int ans = (a * yinv) % p; return ans; } unsigned long long int I1018 = 1000000000000000000; const unsigned long long int I10e5 = 100000; const long long int I10e6 = 1e6; template <typename T> istream &operator>>(istream &in, vector<T> &a) { for (auto &item : a) { in >> item; } return in; } template <typename T, typename U> ostream &operator<<(ostream &out, pair<T, U> &a) { cout << a.first << << a.second; return out; } template <typename T, typename U> istream &operator>>(istream &out, pair<T, U> &a) { cin >> a.first >> a.second; return out; } template <typename T, typename U> ostream &operator<<(ostream &out, map<T, U> &a) { for (auto &item : a) { out << item << endl; } return out; } template <typename T> ostream &operator<<(ostream &out, vector<T> &a) { for (auto &item : a) { out << item << ; } return out; } template <typename T> ostream &operator<<(ostream &out, vector<vector<T>> &a) { for (auto &item : a) { out << item << n ; } return out; } std::vector<bool> is_prime; std::vector<long long int> primes; void sieve(long long int n) { is_prime.resize(n + 2, true); primes.clear(); long long int p; for (p = 2; p * p <= n; p++) { if (is_prime[p]) { long long int i; for (i = p * p; i <= n; i += p) { is_prime[i] = false; } } } is_prime[0] = is_prime[1] = false; long long int i; for (i = 2; i <= n; i++) { if (is_prime[i]) { primes.emplace_back(i); } } } map<long long int, long long int> prime_factors(long long int n) { map<long long int, long long int> s; long long int i; long long int tc = 0; while (n % 2 == 0) { tc++; n /= 2; } if (tc > 0) { s[2] = tc; } for (i = 3; i <= sqrt(n); i += 2) { tc = 0; while (n % i == 0) { tc++; n /= i; } if (tc > 0) { s[i] = tc; } } if (n > 2) { s[n] += 1; } return s; } std::vector<long long int> fact_vec; void fact_fun(long long int n) { fact_vec.resize(n + 10); long long int i; fact_vec[0] = 1; for (i = 1; i <= n + 2; i++) { fact_vec[i] = (fact_vec[i - 1] * i) % MOD; } } long long int npr(long long int n, long long int r) { long long int ans = fact_vec[n]; ans /= fact_vec[n - r]; return ans; } long long int ncr(long long int n, long long int r) { long long int ans = fact_vec[n]; ans = fdiv(ans, fact_vec[n - r]); ans = fdiv(ans, fact_vec[r]); return ans; } long long int nc2(long long int n) { return (n * (n - 1)) / 2; } int main() { long long int i, j; ios::sync_with_stdio(false); cin.tie(0); string s; cin >> s; long long int n = s.length(); std::vector<long long int> cnt(n + 10, 0); for (i = 0; i < n; i++) { cnt[i + 1] = cnt[i] + ((s[i] >= A && s[i] <= Z ) ? 1 : 0); } long long int ans = INF; for (i = 0; i < n + 1; i++) { long long int left = i - cnt[i]; long long int right = cnt[n] - cnt[i]; ans = min(ans, left + right); } cout << ans << endl; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: small_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module small_rom (
address,
clock,
q);
parameter init_file = ""; //PG
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter ram_type = "AUTO"; // M10K MLAB AUTO
input [11:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = lpm_hint,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.ram_block_type = ram_type,
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../../roms/maxam.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../../roms/maxam.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL small_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_rom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int T, n; char Ls[400000 + 5], ps[400000 + 5]; long long ans; long long read() { long long x = 0, F = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) F = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * F; } struct AC_automaton { int tr[400000 + 5][26], cnt; int C_end[400000 + 5], fail[400000 + 5], Ans[400000 + 5], lst[400000 + 5]; void Clear() { cnt = 0; fail[0] = 0; memset(tr[0], 0, sizeof(tr[0])); memset(Ans, 0, sizeof(Ans)); } void Insert(char *s, int id) { int p = 0, len = strlen(s); for (int i = 0; i < len; i++) { int num = s[i] - a ; if (!tr[p][num]) { tr[p][num] = ++cnt; C_end[cnt] = 0; memset(tr[cnt], 0, sizeof(tr[cnt])); fail[cnt] = 0; } p = tr[p][num]; } C_end[p]++; } void Build() { queue<int> Q; for (int i = 0; i < 26; i++) if (tr[0][i]) Q.push(tr[0][i]); while (!Q.empty()) { int k = Q.front(); Q.pop(); for (int i = 0; i < 26; i++) if (tr[k][i]) { int nxt = tr[k][i]; fail[nxt] = tr[fail[k]][i]; Q.push(nxt); lst[nxt] = C_end[fail[nxt]] ? fail[nxt] : lst[fail[nxt]]; } else tr[k][i] = tr[fail[k]][i]; } } void Query(char *s) { int p = 0; int len = strlen(s); for (int i = 0; i < len; i++) { if (s[i] < a || s[i] > z ) { p = 0; continue; } p = tr[p][s[i] - a ]; for (int j = p; j; j = lst[j]) Ans[i] += C_end[j]; } } } ac, ac2; int main() { ac.Clear(); ac2.Clear(); scanf( %s , Ls); n = read(); int L; for (int i = 1; i <= n; i++) { scanf( %s , ps); ac.Insert(ps, i); L = strlen(ps); reverse(ps, ps + L); ac2.Insert(ps, i); } int len = strlen(Ls); ac.Build(), ac2.Build(); ac.Query(Ls); reverse(Ls, Ls + len); ac2.Query(Ls); for (int i = 0; i < len - 1; i++) ans += 1LL * ac.Ans[i] * ac2.Ans[len - i - 2]; printf( %lld , ans); } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module video_scaler_mul_kbM_MulnS_1(clk, ce, a, b, p);
input clk;
input ce;
input[28 - 1 : 0] a;
input[20 - 1 : 0] b;
output[48 - 1 : 0] p;
reg signed [28 - 1 : 0] a_reg0;
reg signed [20 - 1 : 0] b_reg0;
wire signed [48 - 1 : 0] tmp_product;
reg signed [48 - 1 : 0] buff0;
reg signed [48 - 1 : 0] buff1;
reg signed [48 - 1 : 0] buff2;
assign p = buff2;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
end
end
endmodule
`timescale 1 ns / 1 ps
module video_scaler_mul_kbM(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
video_scaler_mul_kbM_MulnS_1 video_scaler_mul_kbM_MulnS_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { int j = i - x; int k = i + y; if (j < 0) j = 0; if (k > n - 1) k = n - 1; int min = INT_MAX, index = -1; for (int l = j; l <= k; l++) { if (min > a[l]) { min = a[l]; index = l; } } if (index == i) { cout << index + 1 << n ; break; } else { i = index - 1; } } return 0; } |
`timescale 1 ns / 1 ps
module averager_tb();
parameter WIDTH = 8;
reg avg_on;
reg clk;
reg [13:0]din;
reg [WIDTH-1:0]period;
reg restart;
reg [WIDTH-1:0]threshold;
reg [32-WIDTH-1:0]n_avg_min;
reg tvalid;
wire [3:0]wen;
wire [31:0]dout;
wire [32-WIDTH-1:0] n_avg;
wire ready;
wire avg_on_out;
wire [WIDTH+1:0]addr;
system_wrapper
DUT (
.addr(addr),
.avg_on(avg_on),
.clk(clk),
.din(din),
.n_avg_min(n_avg_min),
.dout(dout),
.n_avg(n_avg),
.period(period),
.ready(ready),
.restart(restart),
.threshold(threshold),
.tvalid(tvalid),
.wen(wen),
.avg_on_out(avg_on_out)
);
parameter CLK_PERIOD = 8;
initial begin
clk = 0;
avg_on = 1;
din = 0;
restart = 0;
tvalid = 0;
period = 0;
n_avg_min = 20;
threshold = 0;
#(CLK_PERIOD * 2**(WIDTH-1))
period = 2**WIDTH - 1;
threshold = 2**WIDTH - 6;
#(CLK_PERIOD * 2**(WIDTH-1)) tvalid = 1;
#(81*CLK_PERIOD) restart = 1;
#(CLK_PERIOD) restart = 0;
#(10 * CLK_PERIOD) avg_on = 1;
#(2000 * CLK_PERIOD) restart = 1;
#(CLK_PERIOD) restart = 0;
#(10 * CLK_PERIOD) avg_on = 1;
#(2000 * CLK_PERIOD) restart = 1;
#(CLK_PERIOD) restart = 0;
#(10 * CLK_PERIOD) avg_on = 0;
#(2000 * CLK_PERIOD) restart = 1;
#(CLK_PERIOD) restart = 0;
#(1000 * CLK_PERIOD) restart = 1;
#(CLK_PERIOD) restart = 0;
#(100000*CLK_PERIOD)
$finish;
end
always #(CLK_PERIOD/2) clk = ~clk;
always begin
#(CLK_PERIOD * 2**(WIDTH-1)) din = 1;
#(CLK_PERIOD * 2**(WIDTH-1)) din = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, s; scanf( %lld , &a); a = a - 2; if (a % 3 == 0) { printf( 1 2 %lld , a - 1); } else printf( 1 1 %lld , a); return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 200005; const int Maxd = 10; int bits[1 << Maxd]; int t; char str[Maxn]; int slen; int main() { for (int i = 1; i < 1 << Maxd; i++) bits[i] = 1 + bits[i - (i & -i)]; scanf( %d , &t); while (t--) { scanf( %s , str); slen = strlen(str); int cur = 0; for (int i = 0; i < slen; i++) cur ^= 1 << int(str[i] - 0 ); bool solved = false; for (int i = slen - 1; i >= 0 && !solved; i--) { int my = str[i] - 0 ; cur ^= 1 << my; for (int j = my - 1; j >= 0 && !solved; j--) { cur ^= 1 << j; if (i + 1 + bits[cur] <= slen) { solved = true; str[i] = j + 0 ; int pnt = i + 1; int lft = slen - (i + 1 + bits[cur]); while (lft--) str[pnt++] = 9 ; for (int l = Maxd - 1; l >= 0; l--) if (cur & 1 << l) str[pnt++] = 0 + l; } cur ^= 1 << j; } } int pnt = 0; while (str[pnt] == 0 ) pnt++; for (int i = pnt; i < slen - pnt; i++) printf( %c , str[i]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int check(vector<long long> &a, long long q) { multiset<long long> s; for (int j = 0; j < n; ++j) { if (q + a[j] >= 0) { q += a[j]; s.insert(a[j]); } else if (a[j] > (*s.begin())) { q += (a[j] - (*s.begin())); s.erase(s.begin()); s.insert(a[j]); } } return s.size(); } int main() { ios::sync_with_stdio(false); cin >> n >> m; vector<pair<long long, int> > b(m); vector<int> out(m); vector<long long> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 0; i < m; ++i) { cin >> b[i].first; b[i].second = i; } sort(b.begin(), b.end()); int pre = -1, li = 0; for (int i = 0; i <= n && pre != m - 1; ++i) { int l = pre + 1, h = m - 1; while (l < h) { int md = (h + l) >> 1; if (check(a, b[md].first) >= i) { h = md; } else { l = md + 1; } } if (check(a, b[l].first) != i) { continue; } for (int j = pre + 1; j < l; ++j) { out[b[j].second] = n - li; } li = i; out[b[l].second] = n - i; pre = l; } while (pre != m) { out[b[pre++].second] = n - li; } for (int i = 0; i < m; ++i) { cout << out[i] << n ; } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file inside CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of register file memories ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_rf.v,v $
// Revision 1.3 2003/04/07 01:21:56 lampret
// RFRAM type always need to be defined.
//
// Revision 1.2 2002/06/08 16:19:09 lampret
// Added generic flip-flop based memory macro instantiation.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.13 2001/11/20 18:46:15 simons
// Break point bug fixed
//
// Revision 1.12 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.11 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.10 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_rf(
// Clock and reset
clk, rst,
// Write i/f
supv, wb_freeze, addrw, dataw, we, flushpipe,
// Read i/f
id_freeze, addra, addrb, dataa, datab, rda, rdb,
// Debug
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Write i/f
//
input supv;
input wb_freeze;
input [aw-1:0] addrw;
input [dw-1:0] dataw;
input we;
input flushpipe;
//
// Read i/f
//
input id_freeze;
input [aw-1:0] addra;
input [aw-1:0] addrb;
output [dw-1:0] dataa;
output [dw-1:0] datab;
input rda;
input rdb;
//
// SPR access for debugging purposes
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [dw-1:0] from_rfa;
wire [dw-1:0] from_rfb;
reg [dw:0] dataa_saved;
reg [dw:0] datab_saved;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrw;
wire [dw-1:0] rf_dataw;
wire rf_we;
wire spr_valid;
wire rf_ena;
wire rf_enb;
reg rf_we_allow;
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
//
// RF write enable is either from SPRS or normal from CPU control
//
always @(posedge rst or posedge clk)
if (rst)
rf_we_allow <= #1 1'b1;
else if (~wb_freeze)
rf_we_allow <= #1 ~flushpipe;
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
// assign rf_ena = 1'b1; // does not work with single-stepping
//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze | spr_valid;
// assign rf_enb = 1'b1;
//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
if (rst) begin
dataa_saved <= #1 33'b0;
end
else if (id_freeze & !dataa_saved[32]) begin
dataa_saved <= #1 {1'b1, from_rfa};
end
else if (!id_freeze)
dataa_saved <= #1 33'b0;
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
if (rst) begin
datab_saved <= #1 33'b0;
end
else if (id_freeze & !datab_saved[32]) begin
datab_saved <= #1 {1'b1, from_rfb};
end
else if (!id_freeze)
datab_saved <= #1 33'b0;
`ifdef OR1200_RFRAM_TWOPORT
//
// Instantiation of register file two-port RAM A
//
or1200_tpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(rf_addra),
.di_a(32'h0000_0000),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
//
// Instantiation of register file two-port RAM B
//
or1200_tpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),
.di_a(32'h0000_0000),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
`else
`ifdef OR1200_RFRAM_DUALPORT
//
// Instantiation of register file two-port RAM A
//
or1200_dpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.oe_a(1'b1),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
//
// Instantiation of register file two-port RAM B
//
or1200_dpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.oe_a(1'b1),
.addr_a(addrb),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
`else
`ifdef OR1200_RFRAM_GENERIC
//
// Instantiation of generic (flip-flop based) register file
//
or1200_rfram_generic rf_a(
// Clock and reset
.clk(clk),
.rst(rst),
// Port A
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.ce_b(rf_enb),
.addr_b(addrb),
.do_b(from_rfb),
// Port W
.ce_w(rf_we),
.we_w(rf_we),
.addr_w(rf_addrw),
.di_w(rf_dataw)
);
`else
//
// RFRAM type not specified
//
initial begin
$display("Define RFRAM type.");
$finish;
end
`endif
`endif
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2, t = ; cin >> s1 >> s2; int n = s1.size(), c = 0, c1 = 0, c2 = 0; for (int i = 0; i < n; i++) { if (s1[i] != s2[i]) c++; } if (c % 2 != 0) cout << impossible << endl; else { c1 = c2 = c / 2; for (int i = 0; i < n; i++) { if (s1[i] == s2[i]) t += s1[i]; else if (s1[i] != s2[i]) { if (c1 > 0) { c1--; t += s1[i]; } else if (c2 > 0) { c2--; t += s2[i]; } } } cout << t << endl; } } |
#include <bits/stdc++.h> using namespace std; bool isNonDegenerateTriangle(int a, int b, int c) { return (a + b > c && b + c > a && c + a > b); } bool isDegenerateTriangle(int a, int b, int c) { return (a + b == c || b + c == a || c + a == b); } int main() { int n; cin >> n; long long int a[n], s = 0; for (int i = 0; i < n; i++) { cin >> a[i]; s += a[i]; } sort(a, a + n); cout << 2 * a[n - 1] - s + 1; } |
#include <bits/stdc++.h> using namespace std; bool check(string s) { for (int i = 0; i < s.size() / 2; i++) if (s[i] != s[s.size() - 1 - i]) return 0; return 1; } int main() { int jopa; string s; cin >> s; int p = 0; char a = s[0]; for (int i = 0; i < s.size(); i++) if (s[i] == a) p++; if (p >= s.size() - 1) { cout << Impossible ; return 0; } int n = s.size(); s = s + s; for (int i = 1; i < n; i++) { if (i + n - 1 >= s.size()) break; if (check(s.substr(i, n)) && s.substr(i, n) != s.substr(0, n)) { cout << 1; return 0; } } cout << 2; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(*i $Id: NStrongRec.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Module NStrongRecPropFunct (Import N : NAxiomsSig').
Include NSubPropFunct N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
(** We need a result similar to [f_equal], but for setoid equalities. *)
Lemma f_equiv : forall f g x y,
(N.eq==>Aeq)%signature f g -> N.eq x y -> Aeq (f x) (g y).
Proof.
auto.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0.
repeat red; intros.
apply f_equiv; auto.
apply recursion_wd; try red; auto.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt.
apply strong_rec0_wd; auto.
now rewrite Enn'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
apply f_equiv; auto with *.
rewrite recursion_succ; try (repeat red; auto with *; fail).
apply f_wd.
apply recursion_wd; try red; auto with *.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ.
apply f_wd; auto with *.
red; intros; rewrite strong_rec0_0; auto with *.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
apply f_wd; auto with *.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Implicit Arguments strong_rec [A].
End NStrongRecPropFunct.
|
#include <bits/stdc++.h> using namespace std; int a[301][301], h, w, dp[301][301]; int used[601][601]; int dx[] = {0, 1, -1, 0, 0, 1, -1, 1, -1}; int dy[] = {0, 0, 0, 1, -1, 1, 1, -1, -1}; int read() { int x; scanf( %d , &x); return x; } bool check(int x, int y) { if (x >= 1 && x <= h && y >= 1 && y <= w && !used[x][y]) return true; else return false; } void dfs(int x, int y, int component) { used[x][y] = component; for (int i = 1; i <= 8; i++) { int kx = dx[i] + x, ky = dy[i] + y; if (check(kx, ky) && a[x][y] == a[kx][ky]) { dfs(kx, ky, component); } } } void init() { for (int i = 0; i <= 600; i++) { for (int j = 0; j <= 600; j++) { used[i][j] = 0; } } } int main() { int q; q = read(); while (q--) { h = read(), w = read(); init(); for (int i = 1; i <= h; i++) { for (int j = 1; j <= w; j++) { a[i][j] = read(); } } int cntfirst = 0, cntsecond = 0; for (int i = 1; i <= h; i++) { for (int j = 1; j <= w; j++) { if (!used[i][j]) dfs(i, j, cntfirst + 1), cntfirst++; } } for (int i = h / 2 + 1; i <= h; i++) { for (int j = 1; j <= w; j++) { dp[i - h / 2][j] = a[i][j]; } } for (int i = 1; i <= h / 2; i++) { for (int j = 1; j <= w; j++) { dp[i + h / 2][j] = a[i][j]; } } for (int i = 1; i <= h; i++) { for (int j = 1; j <= w; j++) { a[i][j] = dp[i][j]; } } init(); for (int i = 1; i <= h; i++) { for (int j = 1; j <= w; j++) { if (!used[i][j]) dfs(i, j, cntsecond + 1), cntsecond++; } } if (cntfirst <= cntsecond) { printf( NO n ); } else { printf( YES n ); } } } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
`timescale 1ns/100ps
module sync_bits #(
// Number of bits to synchronize
parameter NUM_OF_BITS = 1,
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter ASYNC_CLK = 1)(
input [NUM_OF_BITS-1:0] in,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out);
generate if (ASYNC_CLK == 1) begin
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out = cdc_sync_stage2;
end else begin
assign out = in;
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; const int MAXN = 1e6 + 3; const double EPS = (1e-7); int dcmp(double x, double y) { return fabs(x - y) <= EPS ? 0 : x < y ? -1 : 1; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long power(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m, v; cin >> n >> m >> v; int maxcon = ((n - 1) * (n - 2)) / 2 + 1; if (m > maxcon or m < n - 1) { cout << -1 << endl; } else { for (int i = 1; i <= n; i++) { if (i != v) { cout << i << << v << n ; m--; } } int pr = 1; if (pr == v) { pr++; } for (int i = 1; i <= n and m; i++) { if (i != v and i != pr) { for (int j = i + 1; j <= n and m; j++) { if (j != v and j != pr) { cout << i << << j << endl; m--; } } } } } } |
#include <bits/stdc++.h> using namespace std; void work(); int main() { work(); return 0; } char S[222222]; char T[222222]; int t[256][256]; void work() { int n; while (scanf( %d , &n) == 1) { memset(t, 0, sizeof(t)); int ans = 0; scanf( %s%s , S + 1, T + 1); for (int i = (1), END = (n); i <= END; i++) if (S[i] != T[i]) { ans++; t[S[i]][T[i]] = i; } bool two = false; for (int i = ( a ), END = ( z ); i <= END; i++) for (int j = (i + 1), END = ( z ); j <= END; j++) if (t[i][j] && t[j][i]) { two = true; printf( %d n%d %d n , ans - 2, t[i][j], t[j][i]); i = 256; j = 256; } if (two) continue; for (int i = ( A ), END = ( Z ); i <= END; i++) for (int j = (i + 1), END = ( Z ); j <= END; j++) if (t[i][j] && t[j][i]) { two = true; printf( %d n%d %d n , ans - 2, t[i][j], t[j][i]); i = 256; j = 256; } if (two) continue; bool one = false; for (int i = ( a ), END = ( z ); i <= END; i++) { int pos = -1; for (int j = ( a ), END = ( z ); j <= END; j++) if (t[i][j]) pos = t[i][j]; if (pos == -1) continue; for (int j = ( a ), END = ( z ); j <= END; j++) if (t[j][i]) { one = true; printf( %d n%d %d n , ans - 1, pos, t[j][i]); i = j = 256; } } if (one) continue; for (int i = ( A ), END = ( Z ); i <= END; i++) { int pos = -1; for (int j = ( A ), END = ( Z ); j <= END; j++) if (t[i][j]) pos = t[i][j]; if (pos == -1) continue; for (int j = ( A ), END = ( Z ); j <= END; j++) if (t[j][i]) { one = true; printf( %d n%d %d n , ans - 1, pos, t[j][i]); i = j = 256; } } if (one) continue; printf( %d n%d %d n , ans, -1, -1); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } sort(a.begin(), a.end()); int curr_len = 0; int l = 0, r = a.size() - 1; while (l <= r) { if (a[l] - 1 < int(1e6) - a[r]) { curr_len = a[l] - 1; ++l; } else { curr_len = int(1e6) - a[r]; --r; } } cout << curr_len; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 gen(chrono::system_clock::now().time_since_epoch().count()); const int M = 3e5 + 7; const int N = 1e6 + 7; int n, q, l, r, t[N * 4], ans[N], k, x, tn = 1; map<int, vector<int> > p; map<int, vector<pair<int, int> > > otr; map<int, vector<pair<int, int> > > R; void update(int v, int tl, int tr, int pos, int x) { if (tr == tl + 1) { t[v] = min(t[v], x); return; } int mid = (tl + tr) / 2; if (pos < mid) update(v << 1, tl, mid, pos, x); else update((v << 1) + 1, mid, tr, pos, x); t[v] = min(t[v << 1], t[(v << 1) + 1]); return; } long long query(int v, int tl, int tr, int l, int r) { if (r <= tl || tr <= l) return 1e9; if (l <= tl && tr <= r) return t[v]; int mid = (tl + tr) / 2; return min(query(v << 1, tl, mid, l, r), query((v << 1) + 1, mid, tr, l, r)); } int query(int l, int r) { return query(1, 0, tn, l, r); } void update(int pos, int x) { update(1, 0, tn, pos, x); return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> q; while (tn < N) tn <<= 1; for (int i = 0; i < n; i++) { cin >> x; if (p[x].size()) otr[i].push_back({p[x].back(), i - p[x].back()}); p[x].push_back(i); } for (int i = 0; i < q; i++) { cin >> l >> r; l--; r--; R[r].push_back({l, i}); } for (int i = 1; i < tn * 2; i++) t[i] = 1e9 + 7; for (int i = 0; i < q; i++) ans[i] = 1e9 + 7; for (int i = 1; i < N; i++) { for (int j = 0; j < otr[i].size(); j++) update(otr[i][j].first, otr[i][j].second); for (int j = 0; j < R[i].size(); j++) ans[R[i][j].second] = query(R[i][j].first, i + 1); } for (int i = 0; i < q; i++) cout << (ans[i] >= n * 2 ? -1 : ans[i]) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using vint = vector<int>; using pint = pair<int, int>; using vpint = vector<pint>; template <typename A, typename B> inline void chmin(A& a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A& a, B b) { if (a < b) a = b; } template <class A, class B> ostream& operator<<(ostream& ost, const pair<A, B>& p) { ost << { << p.first << , << p.second << } ; return ost; } template <class T> ostream& operator<<(ostream& ost, const vector<T>& v) { ost << { ; for (int i = 0; i < v.size(); i++) { if (i) ost << , ; ost << v[i]; } ost << } ; return ost; } struct Cactus { vector<vector<int>> G; vector<vector<int>> cs; vector<int> vis, par, dep; void dfs(int v) { vis[v] = 1; for (auto u : G[v]) { if (!vis[u]) { par[u] = v; dep[u] = dep[v] + 1; dfs(u); } else if (dep[u] < dep[v]) { int w = v; vector<int> c{w}; while (true) { w = par[w]; c.push_back(w); if (w == u) break; } cs.push_back(c); } } } Cactus(const vector<vector<int>>& G) : G(G) { vis.resize(G.size()); par.resize(G.size()); dep.resize(G.size()); dfs(0); } }; int N, M; int A[555555], B[555555]; int info[555555]; int dp[555555]; int memA[555555], memB[555555]; signed main() { scanf( %d%d , &N, &M); vint lis; vector<vint> G(N); map<pint, int> edgeID; for (int i = 0; i < (M); i++) { scanf( %d%d , &A[i], &B[i]); A[i]--; B[i]--; G[A[i]].push_back(B[i]); G[B[i]].push_back(A[i]); edgeID[{A[i], B[i]}] = i; edgeID[{B[i], A[i]}] = i; } Cactus cac(G); fill_n(info, M, -1); for (auto c : cac.cs) { if (c.size() == 2) continue; vint id; for (int i = 0; i < (c.size()); i++) { int a = c[i]; int b = c[(i + 1) % c.size()]; id.push_back(edgeID[{a, b}]); } rotate(id.begin(), min_element((id).begin(), (id).end()), id.end()); int m = max_element((id).begin(), (id).end()) - id.begin(); bool ok = true; for (int i = 0; i < m; i++) if (id[i] > id[i + 1]) ok = false; for (int i = m; i + 1 < id.size(); i++) if (id[i] < id[i + 1]) ok = false; if (!ok) continue; info[id[0]] = id[m]; } for (int i = 0; i < (N); i++) dp[i] = 1; for (int i = M - 1; i >= 0; i--) { int addA = dp[B[i]]; int addB = dp[A[i]]; if (info[i] != -1) { int k = info[i]; int tmp = memA[k] + memB[k]; addA -= tmp; addB -= tmp; } memA[i] = dp[A[i]]; memB[i] = dp[B[i]]; dp[A[i]] += addA; dp[B[i]] += addB; } for (int i = 0; i < (N); i++) dp[i]--; for (int i = 0; i < (N); i++) { if (i) printf( ); printf( %d , dp[i]); } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int t; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { int m; int n; cin >> m >> n; vector<int> a[500]; vector<int> b[500]; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { int temp; cin >> temp; a[i].push_back(temp); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int temp; cin >> temp; b[i].push_back(temp); } } pair<int, int> place; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[0][0] == b[i][j]) { place = make_pair(i, j); } } } map<int, int> rows; for (int i = 0; i < m; i++) { rows.insert({a[i][0], i}); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cout << a[rows[b[place.first][i]]][j] << ; } cout << n ; } } } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire [31:0] A;
wire [24:0] B;
reg [15:0] C;
assign A = B;
assign B = C;
initial begin
C = 0;
#1 if (A !== 32'h0) begin
$display("FAILED -- A === %h", A);
$finish;
end
C = -1;
#1 if (A !== 32'h00_00_ff_ff) begin
$display("FAILED -- A == %h instead of 0000ffff", A);
$finish;
end
$display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__MAJ3_FUNCTIONAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long t, t0, t2, x, x2; void cmp(long double &temp, long long &o, long long &o2, long long y, long long y2) { if (y2 > x2) return; long double newTemp = (1.0 * t * y + t2 * y2) / (y + y2); if (newTemp < t0) return; if (newTemp > temp + 1e-9) return; if (newTemp < temp || y + y2 > o + o2) o = y, o2 = y2, temp = newTemp; } int main() { cin >> t >> t2 >> x >> x2 >> t0; if (t0 == t2) { if (t != t0) cout << 0 << << x2 << endl; else cout << x << << x2 << endl; } else if (t0 == t) cout << x << << 0 << endl; else { long double temp = 1e9; long long o = 0, o2 = 0; cmp(temp, o, o2, 0, x2); cmp(temp, o, o2, x, 0); for (long long y = 0; y <= x; y++) { long long y2 = (y * (t0 - t) + t2 - t0 - 1) / (t2 - t0); cmp(temp, o, o2, y, y2); } cout << o << << o2 << endl; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02.03.2016 13:08:19
// Design Name:
// Module Name: d2str
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D2STR_B#
(
parameter integer len = 16 // Symbols to show
)
(
output wire [127:0] str,
input wire [len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin
assign str[8*i+7:8*i] = d[i]? "1" : "0";
end
for (i = len; i < 16; i = i + 1) begin
assign str[8*i+7:8*i] = " ";
end
endgenerate
endmodule
module D2STR_H#
(
parameter integer len = 16 // Symbols to show
)
(
input wire GCLK,
output reg [127:0] str = "????????????????",
input wire [4*len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin: test
always @(posedge GCLK) begin
case (d[4*i+3:4*i])
4'd0: str[8*i+7:8*i] <= "0";
4'd1: str[8*i+7:8*i] <= "1";
4'd2: str[8*i+7:8*i] <= "2";
4'd3: str[8*i+7:8*i] <= "3";
4'd4: str[8*i+7:8*i] <= "4";
4'd5: str[8*i+7:8*i] <= "5";
4'd6: str[8*i+7:8*i] <= "6";
4'd7: str[8*i+7:8*i] <= "7";
4'd8: str[8*i+7:8*i] <= "8";
4'd9: str[8*i+7:8*i] <= "9";
4'd10: str[8*i+7:8*i] <= "A";
4'd11: str[8*i+7:8*i] <= "B";
4'd12: str[8*i+7:8*i] <= "C";
4'd13: str[8*i+7:8*i] <= "D";
4'd14: str[8*i+7:8*i] <= "E";
4'd15: str[8*i+7:8*i] <= "F";
default: str[8*i+7:8*i] <= " ";
endcase
end
end
for (i = len; i < 16; i = i + 1) begin
always @(posedge GCLK) begin
str[8*i+7:8*i] <= " ";
end
end
endgenerate
endmodule
module D2STR_D#
(
parameter integer len = 4 // Symbols to show
)
(
input wire GCLK,
output reg [127:0] str = "????????????????",
input wire [4*len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin: test
always @(posedge GCLK) begin
case (d[4*i+3:4*i])
4'd0: str[8*i+7:8*i] <= "0";
4'd1: str[8*i+7:8*i] <= "1";
4'd2: str[8*i+7:8*i] <= "2";
4'd3: str[8*i+7:8*i] <= "3";
4'd4: str[8*i+7:8*i] <= "4";
4'd5: str[8*i+7:8*i] <= "5";
4'd6: str[8*i+7:8*i] <= "6";
4'd7: str[8*i+7:8*i] <= "7";
4'd8: str[8*i+7:8*i] <= "8";
4'd9: str[8*i+7:8*i] <= "9";
4'd10: str[8*i+7:8*i] <= " ";
4'd11: str[8*i+7:8*i] <= " ";
4'd12: str[8*i+7:8*i] <= " ";
4'd13: str[8*i+7:8*i] <= " ";
4'd14: str[8*i+7:8*i] <= " ";
4'd15: str[8*i+7:8*i] <= "-";
default: str[8*i+7:8*i] <= " ";
endcase
end
end
for (i = len; i < 16; i = i + 1) begin
always @(posedge GCLK) begin
str[8*i+7:8*i] <= " ";
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; bool prime[100001]; bool ispoweroftwo(long long int x) { return x && !(x & (x - 1)); } long long int xorcal(long long int n) { if (n % 4 == 0) return n; if (n % 4 == 1) return 1; if (n % 4 == 2) return n + 1; if (n % 4 == 3) return 0; } void sieve(long long int n) { memset(prime, true, sizeof(prime)); prime[0] = false; prime[1] = false; for (long long int i = 2; i * i <= n; i++) { if (prime[i] == true) { for (long long int j = i * i; j <= n; j += i) { prime[j] = false; } } } } bool isprime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 or n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i += 6) { if (n % i == 0 or n % (i + 2) == 0) return false; } return true; } long long int modinverse(long long int a, long long int m) { long long int m0 = m; long long int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long int q = a / m; long long int t = m; m = a % m; a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long int gcd(long long int a, long long int b) { if (a == 0) { return b; } return (b % a, a); } long long int power(long long int A, long long int B) { if (A == 0) return 0; if (B == 0) return 1; long long int y; if (B % 2 == 0) { y = power(A, B / 2); y = (y * y) % 1000000007; } else { y = A % 1000000007; y = (y * power(A, B - 1) % 1000000007) % 1000000007; } return (long long int)((y + 1000000007) % 1000000007); } int main() { ios_base::sync_with_stdio(false); long long int n; cin >> n; string s; cin >> s; char f[10]; for (long long int i = 1; i < 10; i++) { cin >> f[i]; } long long int fl = 0; for (long long int i = 0; i < n; i++) { if (s[i] < f[s[i] - 0 ]) { s[i] = f[s[i] - 0 ]; fl = 1; } else if (fl == 1 and s[i] > f[s[i] - 0 ]) { break; } } cout << s << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, v[10004]; vector<array<int, 3> > ans; void go(int x, int y, int z) { v[x] -= x * z; v[y] += x * z; ans.push_back({x, y, z}); } int main() { int t; cin >> t; while (t--) { ans.clear(); int sum = 0; cin >> n; for (int i = 1; i <= n; ++i) { cin >> v[i]; sum += v[i]; } if (sum % n) { cout << -1 << n ; continue; } for (int i = 2; i <= n; ++i) { if (v[i] % i) { go(1, i, i - v[i] % i); } go(i, 1, v[i] / i); } for (int i = 2; i <= n; ++i) { go(1, i, sum / n); } assert((int)ans.size() <= 3 * n); cout << ans.size() << n ; for (auto &[x, y, z] : ans) { cout << x << << y << << z << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a, b, c, n, m, k, x, y, z, cnt, ans, tt; string s; vector<long long> v, q, t; int main() { long long c0, c1, h; cin >> tt; while (tt--) { cin >> n >> c0 >> c1 >> h >> s; cnt = 0; ans = 0; for (long long i = 0; i < s.size(); i++) { if (s[i] == 1 ) cnt++; else ans++; } if (c0 == c1) cout << c0 * n << n ; else if (c0 + h < c1) cout << c0 * n + (cnt * h) << n ; else if (c1 + h < c0) cout << (c1 * n) + (ans * h) << n ; else cout << (c1 * cnt) + (c0 * ans) << n ; } } |
#include <bits/stdc++.h> #pragma GCC optimaze( Ofast ); #pragma GCC optimize( unroll-loops ) using namespace std; const long long maxk = 1e8 + 113; const long long maxb = 1e18 + 113; const long long inf = 2e18; struct line { long long k, b; line() { this->k = 0; this->b = 0; } line(long long k, long long b) { this->k = k; this->b = b; } long long func(long long x) { return k * x + b; } }; struct LiChao { vector<line> ms; vector<int> le, re; long long range; LiChao() { this->range = maxk - 113; ms.push_back(line()); le.push_back(-1); re.push_back(-1); } LiChao(long long range) { this->range = range; ms.push_back(line()); le.push_back(-1); re.push_back(-1); } void clear() { ms.clear(); le.clear(); re.clear(); ms.push_back(line()); le.push_back(-1); re.push_back(-1); } void push(int v, bool e) { if (!e && le[v] == -1) { le[v] = ms.size(); ms.push_back(ms[v]); le.push_back(-1); re.push_back(-1); } if (e && re[v] == -1) { re[v] = ms.size(); ms.push_back(ms[v]); le.push_back(-1); re.push_back(-1); } } void add(int v, long long l, long long r, line in) { long long m = (l + r) >> 1; if (l > r) return; if (in.func(m) > ms[v].func(m)) swap(in, ms[v]); if (l == r) return; if (in.func(l) > ms[v].func(l)) { push(v, 0); add(le[v], l, m, in); } else { push(v, 1); add(re[v], m + 1, r, in); } } void add(line in) { add(0, -range, range, in); } long long get(int v, long long l, long long r, long long x) { if (l >= r) return ms[v].func(x); long long m = (l + r) >> 1; if (x <= m) { if (le[v] == -1) return ms[v].func(x); return max(get(le[v], l, m, x), ms[v].func(x)); } else { if (re[v] == -1) return ms[v].func(x); return max(get(re[v], m + 1, r, x), ms[v].func(x)); } } long long get(long long x) { return get(0, -range, range, x); } }; signed main() { srand(1); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.setf(ios::fixed); cout.precision(15); long long n, s; cin >> n >> s; long long df = 0; vector<pair<long long, long long>> ed; for (int i = 0; i < n; i++) { long long v, c; cin >> v >> c; df = max(df, v); ed.push_back({c, -v}); } ed.push_back({s, 1}); sort(ed.begin(), ed.end()); long long range = 1e9 + 113 + s / df; LiChao ms(range); long long le = -1; for (int i = 0; i < ed.size(); i++) { ed[i].second *= -1; long long r = max(le, 1LL); while (ms.get(r) < ed[i].first) r <<= 1; r = min(r, range); while (le + 1 < r) { long long m = (le + r) / 2; if (ms.get(m) < ed[i].first) le = m; else r = m; } if (ed[i].second != -1) { long long k = ed[i].second; ms.add(line(k, -r * k + ms.get(r) - ed[i].first)); le = r; } else { cout << r; return 0; } } } |
#include <bits/stdc++.h> using namespace std; bool compare(vector<long long> &A, vector<long long> &B) { if (A[0] - A[1] > B[0] - B[1]) return true; return false; } int main() { long long(n), (a), (b); scanf( %lld%lld%lld , &(n), &(a), &(b)); ; vector<vector<long long>> A, B; long long sum = 0; for (long long i = 0; i < (n); i++) { long long(a), (b); scanf( %lld%lld , &(a), &(b)); ; if (a > b) B.push_back(vector<long long>{a, b}); else A.push_back(vector<long long>{a, b}); sum += b; } if (b == 0) { printf( %lld n , sum); return 0; } long long val = 1; while (a--) val *= 2; sort((B).begin(), (B).end(), compare); while (B.size() > b) { A.push_back(B[B.size() - 1]); B.pop_back(); } long long store = 0; for (long long i = 0; i < (B.size()); i++) { sum += B[i][0] - B[i][1]; if (B.size() == b && i == b - 1) store = B[i][1] - B[i][0]; } long long ans = sum; for (long long i = 0; i < (B.size()); i++) { long long temp = sum; temp -= B[i][0]; temp += B[i][0] * val; ans = max(ans, temp); } for (long long i = 0; i < (A.size()); i++) { long long temp = sum + store; temp -= A[i][1]; temp += A[i][0] * val; ans = max(ans, temp); } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = RDLU ; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int &x, int y, int mod = 1000000007) { x += y; if (x >= mod) x -= mod; } void et() { puts( -1 ); exit(0); } struct ant { long long pos; char d; void rd() { cin >> pos >> d; pos--; } bool operator<(const ant &o) const { return pos < o.pos; } } a[300105]; long long t; int ans[300105]; vector<pair<int, int> > pre; void fmain() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> t; for (int(i) = 0; (i) < (int)(n); (i)++) a[i].rd(); for (int(i) = 0; (i) < (int)(n); (i)++) pre.push_back({a[i].pos, i}); sort(pre.begin(), pre.end()); long long offset = 0; for (int(i) = 0; (i) < (int)(n); (i)++) { if (a[i].d == R ) { (offset += (a[i].pos + t) / m) %= n; a[i].pos = (t + a[i].pos) % m; } else { if (t >= 1 + a[i].pos) { offset += n - 1; offset += n - (t - (a[i].pos + 1)) / m % n; offset %= n; } a[i].pos = ((long long)a[i].pos - t) % m + m; a[i].pos %= m; } } sort(a, a + n); for (int(i) = 0; (i) < (int)(n); (i)++) ans[pre[i].second] = a[(i + offset) % n].pos + 1; for (int(i) = 0; (i) < (int)(n); (i)++) cout << ans[i] << ; } int main() { fmain(); return 0; } |
#include <bits/stdc++.h> using namespace std; int key; long long dis[1000]; struct pt { long long x, y, z; } f[8], point[8]; long long meow(int a, int b) { long long ta, tb, tc; ta = f[a].x - f[b].x; tb = f[a].y - f[b].y; tc = f[a].z - f[b].z; return (ta * ta + tb * tb + tc * tc); } int chk() { int i, j, cnta, cntb, cntc, k; long long dis, sq2, sq3, ik; for (i = 0; i < 8; i++) { for (j = 0; j < 8; j++) { if (i != j && f[i].x == f[j].x && f[i].y == f[j].y && f[i].z == f[j].z) return false; } } for (i = 0; i < 8; i++) { for (j = 0; j < 8; j++) { dis = meow(i, j); cnta = cntb = cntc = 0; for (k = 0; k < 8; k++) { ik = meow(i, k); if (ik == dis) cnta++; if (ik == dis * 2) cntb++; if (ik == dis * 3) cntc++; } if (cnta == 3 && cntb == 3 && cntc == 1) break; } if (j == 8) return false; } return true; } void go(int r) { if (r == 8) { if (chk()) { key = 1; cout << YES << endl; for (int i = 0; i < 8; i++) cout << f[i].x << << f[i].y << << f[i].z << endl; } return; } f[r] = point[r]; go(r + 1); if (key) return; swap(f[r].x, f[r].y); go(r + 1); if (key) return; swap(f[r].y, f[r].z); go(r + 1); if (key) return; swap(f[r].x, f[r].y); go(r + 1); if (key) return; swap(f[r].y, f[r].z); go(r + 1); if (key) return; swap(f[r].x, f[r].y); go(r + 1); return; } int main() { int i; for (i = 0; i < 8; i++) cin >> point[i].x >> point[i].y >> point[i].z; key = 0; f[0] = point[0]; go(1); if (!key) cout << NO << endl; return 0; } |
// Fast Multisource Pulse Registration System
// Module:
// event_tagger
// Pulse Registration and Time Stamping
// (c) Sergey V. Polyakov 2006-forever
module event_tagger(
strobe_channels,
delta_channels,
clk,
reset_counter,
capture_operate, counter_operate,
data,
ready
);
input [3:0] strobe_channels;
input [3:0] delta_channels;
input clk;
input reset_counter;
input capture_operate;
input counter_operate;
output ready;
output [46:0] data;
reg [35:0] timer = 36'b0;
reg [3:0] old_delta = 3'b0;
reg ready = 0;
reg [46:0] data = 47'b0;
always @(posedge clk)
begin
if (delta_channels != old_delta) // First monitor delta inputs
begin
data[35:0] <= timer[35:0];
data[39:36] <= delta_channels;
data[44:40] <= 0; // reserved
data[45] <= 1; // record type
data[46] <= (timer==1'b0) ? 1'b1 : 1'b0; // wraparound
ready <= capture_operate;
old_delta <= delta_channels;
end
else if (strobe_channels != 4'b0 || (timer == 36'b0 && counter_operate))
begin
data[35:0] <= timer[35:0];
data[39:36] <= strobe_channels;
data[44:40] <= 0; // reserved
data[45] <= 0; // record type
data[46] <= (timer==36'b0) ? 1'b1 : 1'b0; // wraparound
ready <= capture_operate;
end
else
begin
ready <= 0;
data <= 47'bX;
end
/*if (reset_counter)
timer <= 0;
else if (counter_operate)
timer <= timer + 1;*/
timer <= reset_counter ? 0 : timer + counter_operate;
end
endmodule
|
#include <bits/stdc++.h> const long long int mod = 1e9 + 7; using namespace std; long long int p, q, r, s; long long int len(long long int x) { long long int count = 0; while (x > 0) { x = x / 10; count++; } return count; } long long int fx(long long int x) { long long int count = 9; if (x <= 9) return x; p = len(x); q = x % 10; x /= 10; r = x / pow(10, p - 2); s = pow(10, p - 2); x = x % s; if (p == 2) { count += r; if (q < r) count--; return count; } for (int i = (1); i <= (p - 2); i++) count += 9 * pow(10, i - 1); count += (r - 1) * pow(10, p - 2); count += x + 1; if (q < r) count--; return count; } int main() { long long int y, z; cin >> y >> z; long long int temp = fx(z) - fx(y - 1); cout << temp << endl; } |
#include <bits/stdc++.h> const double pi = (double)(2.0 * acos(0.0)); const int inf = 1 << 30; const double eps = 1E-9; const double e = exp(1.0); const int sz = 100000 + 5; const int mod = 1000000000 + 7; using namespace std; int main() { double x, y, z, res, v; string st = ; scanf( %lf %lf %lf , &x, &y, &z); if (x < 1.0 + eps && y < 1.0 + eps && z < 1.0 + eps) { res = 1e18; v = z * log(y) + log(log(1.0 / x)); if (res > v + eps) res = v, st = x^y^z ; v = y * log(z) + log(log(1.0 / x)); if (res > v + eps) res = v, st = x^z^y ; v = log(y) + log(z) + log(log(1.0 / x)); if (res > v + eps) res = v, st = (x^y)^z ; v = z * log(x) + log(log(1.0 / y)); if (res > v + eps) res = v, st = y^x^z ; v = x * log(z) + log(log(1.0 / y)); if (res > v + eps) res = v, st = y^z^x ; v = log(x) + log(z) + log(log(1.0 / y)); if (res > v + eps) res = v, st = (y^x)^z ; v = y * log(x) + log(log(1.0 / z)); if (res > v + eps) res = v, st = z^x^y ; v = x * log(y) + log(log(1.0 / z)); if (res > v + eps) res = v, st = z^y^x ; v = log(x) + log(y) + log(log(1.0 / z)); if (res > v + eps) res = v, st = (z^x)^y ; cout << st << endl; } else { res = -1e18; if (x > 1.0 + eps) { v = z * log(y) + log(log(x)); if (res + eps < v) res = v, st = x^y^z ; v = y * log(z) + log(log(x)); if (res + eps < v) res = v, st = x^z^y ; v = log(y) + log(z) + log(log(x)); if (res + eps < v) res = v, st = (x^y)^z ; } if (y > 1.0 + eps) { v = z * log(x) + log(log(y)); if (res + eps < v) res = v, st = y^x^z ; v = x * log(z) + log(log(y)); if (res + eps < v) res = v, st = y^z^x ; v = log(x) + log(z) + log(log(y)); if (res + eps < v) res = v, st = (y^x)^z ; } if (z > 1.0 + eps) { v = y * log(x) + log(log(z)); if (res + eps < v) res = v, st = z^x^y ; v = x * log(y) + log(log(z)); if (res + eps < v) res = v, st = z^y^x ; v = log(x) + log(y) + log(log(z)); if (res + eps < v) res = v, st = (z^x)^y ; } cout << st << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int N, K; int A[310000]; int dp[31000][210][4][2]; int ins(int i, int k, int bit) { if (k == 1) { if (bit % 2 == 0) return A[i]; return -A[i]; } if (k == K) { if (bit / 2 == 0) return -A[i]; return A[i]; } int res = 0; if (bit % 2 == 0) res += A[i]; else res -= A[i]; if (bit / 2 == 0) res -= A[i]; else res += A[i]; return res; } int main() { for (int(i) = 0; (i) < (31000); (i)++) for (int(j) = 0; (j) < (210); (j)++) for (int(k) = 0; (k) < (4); (k)++) for (int(l) = 0; (l) < (2); (l)++) dp[i][j][k][l] = -(1 << 30); scanf( %d%d , &N, &K); for (int(i) = 0; (i) < (N); (i)++) scanf( %d , &A[i]); dp[0][0][0][0] = 0; for (int(i) = 0; (i) < (N); (i)++) { for (int(j) = 0; (j) < (K + 1); (j)++) for (int(b) = 0; (b) < (4); (b)++) { dp[i + 1][j][b][0] = max(dp[i + 1][j][b][0], dp[i][j][b][0]); dp[i + 1][j + 1][b % 2 * 2][1] = max(dp[i + 1][j + 1][b % 2 * 2][1], dp[i][j][b][0] + ins(i, j + 1, b % 2 * 2)); dp[i + 1][j + 1][b % 2 * 2][1] = max(dp[i + 1][j + 1][b % 2 * 2][1], dp[i][j][b][1] + ins(i, j + 1, b % 2 * 2)); dp[i + 1][j + 1][b % 2 * 2 + 1][1] = max(dp[i + 1][j + 1][b % 2 * 2 + 1][1], dp[i][j][b][0] + ins(i, j + 1, b % 2 * 2 + 1)); dp[i + 1][j + 1][b % 2 * 2 + 1][1] = max(dp[i + 1][j + 1][b % 2 * 2 + 1][1], dp[i][j][b][1] + ins(i, j + 1, b % 2 * 2 + 1)); dp[i + 1][j][b][1] = max(dp[i + 1][j][b][1], dp[i][j][b][1] + ins(i, j, b)); dp[i + 1][j][b][0] = max(dp[i + 1][j][b][0], dp[i][j][b][1]); } for (int(j) = 0; (j) < (K + 1); (j)++) for (int(k) = 0; (k) < (4); (k)++) for (int(l) = 0; (l) < (2); (l)++) if (dp[i + 1][j][k][l] < -(1 << 29)) dp[i + 1][j][k][l] = -(1 << 30); } int res = -(1 << 30); for (int(b) = 0; (b) < (4); (b)++) for (int(l) = 0; (l) < (2); (l)++) res = max(res, dp[N][K][b][l]); cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; const int M = 11, L = 11, N = 1002; const int Mod = 1e9 + 9; char a[L], to[99]; int n; int dp[2][M * L][N], ch[M * L][4], fail[M * L]; int len[N]; int ans = 0; inline void mo(int& x) { x = (x >= Mod ? x - Mod : x); } struct AC_automaton { int cnt; inline void init() { cnt = 0; to[ A ] = 0, to[ C ] = 1, to[ G ] = 2, to[ T ] = 3; } inline void insert() { int l = strlen(a + 1), now = 0; for (int i = 1; i <= l; i++) { if (!ch[now][to[a[i]]]) ch[now][to[a[i]]] = ++cnt; now = ch[now][to[a[i]]]; } len[now] = max(len[now], l); } inline void build() { queue<int> Q; for (int i = 0; i < 4; i++) if (ch[0][i]) Q.push(ch[0][i]); while (!Q.empty()) { int x = Q.front(); Q.pop(); len[x] = max(len[x], len[fail[x]]); for (int i = 0; i < 4; i++) { if (ch[x][i]) fail[ch[x][i]] = ch[fail[x]][i], Q.push(ch[x][i]); else ch[x][i] = ch[fail[x]][i]; } } } inline void work() { dp[0][0][1] = 1; for (int i = 1; i <= n; i++) { memset(dp[i & 1], 0, sizeof(dp[i & 1])); for (int j = 0; j <= cnt; j++) for (int k = 0; k <= i; k++) { if (dp[!(i & 1)][j][k]) { for (int t = 0; t < 4; t++) { if (len[ch[j][t]] + k > i) mo(dp[i & 1][ch[j][t]][i + 1] += dp[!(i & 1)][j][k]); else mo(dp[i & 1][ch[j][t]][k] += dp[!(i & 1)][j][k]); } } } } for (int j = 0; j <= cnt; j++) mo(ans += dp[n & 1][j][n + 1]); } } T; int main() { int m; scanf( %d%d , &n, &m); T.init(); for (int i = 1; i <= m; i++) { scanf( %s , a + 1); T.insert(); } T.build(); T.work(); printf( %d , ans); return 0; } |
`timescale 1 ns / 1 ps
module axis_trigger #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter AXIS_TDATA_SIGNED = "FALSE"
)
(
// System signals
input wire aclk,
input wire pol_data,
input wire [AXIS_TDATA_WIDTH-1:0] msk_data,
input wire [AXIS_TDATA_WIDTH-1:0] lvl_data,
output wire trg_flag,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg [1:0] int_comp_reg;
wire int_comp_wire;
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign int_comp_wire = $signed(s_axis_tdata & msk_data) >= $signed(lvl_data);
end
else
begin : UNSIGNED
assign int_comp_wire = (s_axis_tdata & msk_data) >= lvl_data;
end
endgenerate
always @(posedge aclk)
begin
if(s_axis_tvalid)
begin
int_comp_reg <= {int_comp_reg[0], int_comp_wire};
end
end
assign s_axis_tready = 1'b1;
assign trg_flag = s_axis_tvalid & (pol_data ^ int_comp_reg[0]) & (pol_data ^ ~int_comp_reg[1]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int maxn = 2e5 + 6; const long long int inf = 2e18 + 1; long long int a[maxn]; int main() { long long int n, k; cin >> n >> k; long long int next[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; } next[n - 1] = n; for (long long int i = n - 2; i >= 0; i--) { if (a[i + 1] != 1) { next[i] = i + 1; } else { next[i] = next[i + 1]; } } long long int ans = 0; for (long long int i = 0; i < n; i++) { if (k == 1) { ans++; } long long int r = i; long long int mul = a[i]; long long int sum = a[i]; while (next[r] != n && a[next[r]] <= inf / mul) { mul = mul * a[next[r]]; sum = sum + next[r] - r - 1 + a[next[r]]; r = next[r]; long long int check = -1; if (mul % k == 0) { check = mul / k; } long long int store = next[r] - r - 1; if (check >= sum && check <= sum + store) { ans = ans + 1; } } } cout << ans; return 0; } |
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 09:51:09
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module subRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin : GENSTOP
mult #(.SW(SW))
inst_mult (
.clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { char ch = getchar(); x = 0; while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); } int n, m, mx, now, a[5200]; signed main() { read(n), read(m); int tmp = 0; for (int i = 3; i <= n; ++i) { if (i & 1) ++tmp; mx += tmp; } if (m > mx) return puts( -1 ), 0; a[1] = 1, a[2] = 2; int p = n + 1; tmp = 0; for (int i = 3; i <= n; ++i) { if (i & 1) ++tmp; if (now + tmp > m) { p = i - 1; break; } now += tmp, a[i] = i; } m -= now; if (m) a[p + 1] = p - m * 2 + 1 + p, p += 2; else ++p; for (int i = p; i <= n; ++i) a[i] = 200000000 + i * n; for (int i = 1; i <= n; ++i) printf( %d , a[i]); puts( ); return 0; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A clock synchronization FIFO where the enqueue and dequeue sides are in
// different clock domains.
// The depth of the FIFO is strictly 1 element. Implementation uses only
// 1 register to minimize hardware
// There are no restrictions w.r.t. clock frequencies
// FULL and EMPTY signal are pessimistic, that is, they are asserted
// immediately when the FIFO becomes FULL or EMPTY, but their deassertion
// is delayed due to synchronization latency.
module SyncFIFO1(
sCLK,
sRST,
dCLK,
sENQ,
sD_IN,
sFULL_N,
dDEQ,
dD_OUT,
dEMPTY_N
) ;
parameter dataWidth = 1 ;
// input clock domain ports
input sCLK ;
input sRST ;
input sENQ ;
input [dataWidth -1 : 0] sD_IN ;
output sFULL_N ;
// destination clock domain ports
input dCLK ;
input dDEQ ;
output dEMPTY_N ;
output [dataWidth -1 : 0] dD_OUT ;
// FIFO DATA
(* ASYNC_REG = "TRUE" *)
reg [dataWidth -1 : 0] syncFIFO1Data ;
// Reset generation
wire dRST = sRST;
// sCLK registers
reg sEnqToggle, sDeqToggle, sSyncReg1;
// dCLK registers
reg dEnqToggle, dDeqToggle, dSyncReg1;
// output assignment
assign dD_OUT = syncFIFO1Data;
assign dEMPTY_N = dEnqToggle != dDeqToggle;
assign sFULL_N = sEnqToggle == sDeqToggle;
always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin
if (sRST == `BSV_RESET_VALUE) begin
syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY {dataWidth {1'b0}};
sEnqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0;
sDeqToggle <= `BSV_ASSIGNMENT_DELAY 1'b1; // FIFO marked as full during reset
end
else begin
if (sENQ && (sEnqToggle == sDeqToggle)) begin
syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY sD_IN;
sEnqToggle <= `BSV_ASSIGNMENT_DELAY ! sEnqToggle;
end
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dDeqToggle; // clock domain crossing
sDeqToggle <= `BSV_ASSIGNMENT_DELAY sSyncReg1;
end
end
always @(posedge dCLK or `BSV_RESET_EDGE dRST) begin
if (dRST == `BSV_RESET_VALUE) begin
dEnqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0;
dDeqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else begin
if (dDEQ && (dEnqToggle != dDeqToggle)) begin
dDeqToggle <= `BSV_ASSIGNMENT_DELAY ! dDeqToggle;
end
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sEnqToggle; // clock domain crossing
dEnqToggle <= `BSV_ASSIGNMENT_DELAY dSyncReg1;
end
end
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin : initBlock
syncFIFO1Data = {((dataWidth + 1)/2){2'b10}} ;
sEnqToggle = 1'b0;
sDeqToggle = 1'b0;
sSyncReg1 = 1'b0;
dEnqToggle = 1'b0;
dDeqToggle = 1'b0;
dSyncReg1 = 1'b0;
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
always@(posedge sCLK)
begin: error_checks1
reg enqerror ;
enqerror = 0;
if (sRST == ! `BSV_RESET_VALUE)
begin
if ( sENQ && (sEnqToggle != sDeqToggle)) begin
enqerror = 1;
$display( "Warning: SyncFIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end
end
always@(posedge dCLK)
begin: error_checks2
reg deqerror ;
deqerror = 0;
if (dRST == ! `BSV_RESET_VALUE)
begin
if ( dDEQ && (dEnqToggle == dDeqToggle)) begin
deqerror = 1;
$display( "Warning: SyncFIFO1: %m -- Dequeuing from an empty full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 100; const int MAXT = 1e10 + 1000; int N; long long T; const double EPS = 1e-12; const double CHTLB = -1; const double CHTUB = 1e20; double V, t; double pow(double b, long long p) { assert(p >= 0); if (p == 0) return 1; if (p == 1) return b; double r = static_cast<double>(1); for (; p; p >>= 1, b *= b) if (p & 1) r *= b; return r; } long long rlog2(long long v) { long long ret = 1; while (v >>= 1) ret++; return ret; } bool equ(const double& a, const double& b) { return abs(a - b) < EPS; } bool Q; double r[MAXN]; struct Line { public: Line() { m = b = -1; id = -1; } Line(const double& a, const double& c) { m = a; b = c; id = -1; } Line(const long long& s) { m = b = -1; id = s; } Line(const double& a, const double& c, const int& s) { m = a, b = c, id = s; } double m; double b; int id; bool operator<(const Line& o) const { if (!Q) return o.m > m; else return r[o.id] > r[id]; } double operator()(const double& x) const { return m * x + b; } bool operator()(const double& x, const double& y) const { return equ((*this)(x), y); } pair<double, double> operator*(const Line& o) const { assert(!equ(m, o.m)); double x = (o.b - b) / (m - o.m); double y = (o.b * m - b * o.m) / (m - o.m); return make_pair(x, y); } bool keep(const Line& l, const Line& r) const { return (l * *this).first < (*this * r).first; } }; struct CHT { public: multiset<Line> lines; CHT() { Q = false; } void pout() { for (multiset<Line>::iterator it = lines.begin(); it != lines.end(); it++) { cerr << it->m << x + << it->b << ( << it->id << ) up to << r[it->id] << n ; } } bool insert(const Line& l) { if (lines.empty()) { r[l.id] = CHTUB; lines.insert(l); return true; } multiset<Line>::iterator c = lines.lower_bound(l); if (c != lines.end()) { if (equ(c->m, l.m)) { if (l.b > c->b) lines.erase(c); else return false; } } c = lines.insert(l); multiset<Line>::iterator p[2], n[2]; n[0] = c; p[0] = c; if (c != lines.begin() and ++n[0] != lines.end()) { --p[0]; if (!c->keep(*p[0], *n[0])) { lines.erase(c); return false; } } if (c == lines.begin()) { } else { p[0] = c, p[1] = --p[0]; while (p[0] != lines.begin()) { p[1]--; if (p[0]->keep(*p[1], *c)) { break; } else { lines.erase(p[0]); p[0] = p[1]; } } r[p[0]->id] = ((*p[0]) * (*c)).first; } n[0] = c, n[1] = ++n[0]; if (n[0] == lines.end()) { r[c->id] = CHTUB; } else { while (++n[1] != lines.end()) { if (n[0]->keep(*c, *n[1])) { break; } else { lines.erase(n[0]); n[0] = n[1]; } } r[c->id] = ((*n[0]) * (*c)).first; } return true; } double operator()(const double& x) const { assert(CHTLB < x and x < CHTUB); Q = true; multiset<Line>::iterator c = lines.lower_bound(x); Q = false; assert(c != lines.end()); return (*c)(x); } } hull; struct mat { public: vector<vector<double> > m; private: int L, W; void fix() { L = m.size(); W = m[0].size(); } public: void pout() { fix(); for (int l = 0; l < L; l++) { for (int w = 0; w < W; w++) { cerr << m[l][w] << ; } cerr << n ; } cerr << n ; } mat(const int& l = 1, const int& w = 1) { L = l, W = w; vector<double> r(W, 0); m = vector<vector<double> >(L, r); if (l == w) { for (int i = 0; i < l; i++) m[i][i] = 1; } } vector<double>& operator[](const int& r) { fix(); assert(0 <= r and r < L); return m[r]; } double& operator()(const int& r, const int& c) { fix(); assert(0 <= r and r < L); assert(0 <= c and c < W); return m[r][c]; } mat operator*(mat& o) { fix(); o.fix(); assert(W == o.L); mat ret(L, o.W); for (int l = 0; l < L; l++) { for (int c = 0; c < o.W; c++) { ret[l][c] = 0; for (int i = 0; i < W; i++) { ret[l][c] += m[l][i] * o.m[i][c]; } } } return ret; } }; int a[MAXN], b[MAXN]; double p[MAXN]; double dp; long long ct; mat st[500]; long long next(double p, double a, double cut) { long long v = rlog2(T - ct); st[0].m = {{static_cast<double>(1) - p, p * V, p * a}, {0, 1, 1}, {0, 0, 1}}; for (int i = 1; i <= v; i++) { st[i] = st[i - 1] * st[i - 1]; } mat cm(3, 3); mat dpm(3, 1); dpm.m = {{dp}, {static_cast<double>(ct)}, {1}}; long long dt = 0; for (long long i = v; i >= 0; i--) { if (ct + dt + (1LL << i) > T) continue; mat cmt = cm * st[i]; if (V * (ct + dt + (1LL << i)) - (cmt * dpm)[0][0] > cut) ; else { cm = cmt; dt += (1LL << i); assert(equ(static_cast<double>(dt), cm[1][2])); } } mat rt = cm * dpm; assert(equ(static_cast<double>(ct + dt), rt[1][0])); if (dt + ct < T and V * (ct + dt) - rt[0][0] < cut) { dt++; rt = st[0] * rt; } dp = rt[0][0]; return dt + ct; } int main() { Q = false; cerr << setprecision(10); scanf( %d%lld , &N, &T); V = 0; for (int i = 0; i < N; i++) { scanf( %d%d%Lf , a + i, b + i, p + i); if ((t = b[i] * p[i]) > V) V = t; } for (int i = 0; i < N; i++) { hull.insert(Line(p[i], p[i] * a[i], i)); } ct = 0; dp = 0; for (auto path : hull.lines) { ct = next(p[path.id], a[path.id], r[path.id]); assert(ct <= T); if (ct == T) break; } printf( %.10Lg n , dp); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int a, b, n; cin >> n >> a >> b; vector<int> A(n); for (int &x : A) cin >> x; sort(A.begin(), A.end()); if (A[b] - A[b - 1] == 0) { cout << 0 n ; return; } cout << A[b] - A[b - 1] << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); } |
#include <bits/stdc++.h> using namespace std; string name[1010]; int score[1010]; bool good[1010]; map<string, int> mp; int main(void) { int N, i; cin >> N; for ((i) = 0; (i) < (int)(N); (i)++) cin >> name[i] >> score[i]; for ((i) = 0; (i) < (int)(N); (i)++) mp[name[i]] += score[i]; int M = 0; for (__typeof((mp).begin()) itr = (mp).begin(); itr != (mp).end(); itr++) M = max(M, (itr->second)); for ((i) = 0; (i) < (int)(N); (i)++) good[i] = (mp[name[i]] == M); mp.clear(); for ((i) = 0; (i) < (int)(N); (i)++) { mp[name[i]] += score[i]; if (good[i] && mp[name[i]] >= M) break; } cout << name[i] << endl; return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_fmul(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input valid_i,
output reg [31:0] r,
output reg valid_o
);
wire a_sign = a[31];
wire [7:0] a_expn = a[30:23];
wire [23:0] a_mant = {1'b1, a[22:0]};
wire b_sign = b[31];
wire [7:0] b_expn = b[30:23];
wire [23:0] b_mant = {1'b1, b[22:0]};
reg r_zero;
reg r_sign;
reg [7:0] r_expn;
reg [23:0] r_a_mant;
reg [23:0] r_b_mant;
reg r_valid;
/* Stage 1 */
always @(posedge sys_clk) begin
if(alu_rst)
r_valid <= 1'b0;
else
r_valid <= valid_i;
r_zero <= (a_expn == 8'd0)|(b_expn == 8'd0);
r_sign <= a_sign ^ b_sign;
r_expn <= a_expn + b_expn - 8'd127;
r_a_mant <= a_mant;
r_b_mant <= b_mant;
end
/* Stage 2 */
reg r1_zero;
reg r1_sign;
reg [7:0] r1_expn;
reg [47:0] r1_mant;
reg r1_valid;
always @(posedge sys_clk) begin
if(alu_rst)
r1_valid <= 1'b0;
else
r1_valid <= r_valid;
r1_zero <= r_zero;
r1_sign <= r_sign;
r1_expn <= r_expn;
r1_mant <= r_a_mant*r_b_mant;
end
/* Stage 3 */
reg r2_zero;
reg r2_sign;
reg [7:0] r2_expn;
reg [47:0] r2_mant;
reg r2_valid;
always @(posedge sys_clk) begin
if(alu_rst)
r2_valid <= 1'b0;
else
r2_valid <= r1_valid;
r2_zero <= r1_zero;
r2_sign <= r1_sign;
r2_expn <= r1_expn;
r2_mant <= r1_mant;
end
/* Stage 4 */
reg r3_zero;
reg r3_sign;
reg [7:0] r3_expn;
reg [47:0] r3_mant;
reg r3_valid;
always @(posedge sys_clk) begin
if(alu_rst)
r3_valid <= 1'b0;
else
r3_valid <= r2_valid;
r3_zero <= r2_zero;
r3_sign <= r2_sign;
r3_expn <= r2_expn;
r3_mant <= r2_mant;
end
/* Stage 5 */
reg r4_zero;
reg r4_sign;
reg [7:0] r4_expn;
reg [47:0] r4_mant;
reg r4_valid;
always @(posedge sys_clk) begin
if(alu_rst)
r4_valid <= 1'b0;
else
r4_valid <= r3_valid;
r4_zero <= r3_zero;
r4_sign <= r3_sign;
r4_expn <= r3_expn;
r4_mant <= r3_mant;
end
/* Stage 6 */
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= r4_valid;
if(r4_zero)
r <= {1'bx, 8'd0, 23'bx};
else begin
if(~r4_mant[47])
r <= {r4_sign, r4_expn, r4_mant[45:23]};
else
r <= {r4_sign, r4_expn+8'd1, r4_mant[46:24]};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int T, n, m, sa[40010], sb[40010], ls, du[201], ans; bool g[201][201]; int getint() { int w = 0; bool q = 0; char c = getchar(); while ((c > 9 || c < 0 ) && c != - ) c = getchar(); if (c == - ) c = getchar(), q = 1; while (c >= 0 && c <= 9 ) w = w * 10 + c - 0 , c = getchar(); return q ? -w : w; } void dfs(int u) { while (du[u]) { for (int i = 1; i <= n; i++) if (g[u][i]) { ls++; sa[ls] = u; sb[ls] = i; du[u]--, du[i]--; g[u][i] = g[i][u] = 0; u = i; break; } } } int main() { T = getint(); while (T--) { ans = n = getint(); m = getint(); for (int i = 1, x, y; i <= m; i++) { x = getint(); y = getint(); g[x][y] = g[y][x] = 1; du[x]++; du[y]++; } for (int i = 1; i <= n; i++) ans -= du[i] & 1; printf( %d n , ans); for (int i = 1; i <= n; i++) if (du[i] & 1) while (du[i]) dfs(i); for (int i = 1; i <= n; i++) while (du[i]) dfs(i); for (int i = 1; i <= ls; i++) printf( %d %d n , sa[i], sb[i]); ls = 0; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_2_V
`define SKY130_FD_SC_LS__A31OI_2_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31oi_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_2_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: pattern_fifo.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 217 06/23/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_pattern_fifo (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [8:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
output [8:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({9{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 9,
altsyncram_component.width_b = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "36"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "MLAB"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL "rdaddress[4..0]"
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL "wraddress[4..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pattern_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pattern_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pattern_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pattern_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pattern_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pattern_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 5; int now; int n, m, c, a[MAX]; int main() { cin >> n >> m >> c; c /= 2; while (m--) { int x; scanf( %d , &x); if (x <= c) { for (int i = 1; i <= n; i++) { if (a[i] == 0 || a[i] > x) { a[i] = x; printf( %d n , i); fflush(stdout); break; } } } else { for (int i = n; i >= 1; i--) { if (a[i] == 0 || a[i] < x) { a[i] = x; printf( %d n , i); fflush(stdout); break; } } } now = 0; for (int i = 1; i <= n; i++) { if (a[i] != 0) now++; } if (now == n) break; } return 0; } |
#include <bits/stdc++.h> const int MN = 1e3 + 10; const int K = 20; int N, M, T, id[MN], t[MN], ctr, m[1 << K]; bool conn[MN][MN]; char s[10]; std::vector<int> a[MN], on[K + 1]; struct Mod { public: char c; int a, b; void out() const { printf( %c %d %d n , c, a, b); } }; std::vector<Mod> f; void flip(int a, int b) { f.push_back({conn[a][b] ? - : + , a, b}); conn[a][b] ^= 1; } void dfs(int n) { for (int x : a[n]) if (!~id[x]) dfs(x); id[n] = ctr; t[ctr] = n; ++ctr; } int main() { memset(id, -1, sizeof id); scanf( %d%d%d , &N, &M, &T); for (int i = 0, u, v; i < M; ++i) scanf( %d%d , &u, &v), a[u].push_back(v), conn[u][v] = 1; ctr = 0; for (int i = 1; i <= N; ++i) if (!~id[i]) dfs(i); for (int i = std::min(N, K) - 1; i; --i) for (int j = i - 1; j >= 0; --j) if (!conn[t[i]][t[j]]) { a[t[i]].push_back(t[j]); conn[t[i]][t[j]] = 1; f.push_back({ + , t[i], t[j]}); } for (int i = 0; i < 1 << K; ++i) if (__builtin_popcount(i) <= 3) on[__builtin_popcount(i)].push_back(i); memset(m, -1, sizeof m); for (int i = K; i < N; ++i) { f.push_back({ + , t[i], t[i]}); int n = t[i], v = 0; for (int x : a[n]) if (id[x] < K) v |= 1 << id[x]; bool ok = 0; for (int j = 0; !ok; ++j) { assert(j <= 3); for (int k : on[j]) if (!~m[v ^ k]) { m[v ^ k] = n; for (int b = 0; b < K; ++b) if (k >> b & 1) flip(n, t[b]); ok = 1; break; } } } printf( %u n , f.size()); for (int i = 0; i < f.size(); ++i) f[i].out(); fflush(stdout); for (int i = 0; i < T; ++i) { int v = 0; bool lose = 0; for (int j = 0; j < std::min(N, K); ++j) { printf( ? 1 %d n , t[j]); fflush(stdout); scanf( %s , s); if (s[0] == S ) return 0; if (s[0] == W ) v |= 1 << j; if (s[0] == L ) { lose = 1, v = j; break; } } if (lose) printf( ! %d n , t[v]); else printf( ! %d n , m[v]); fflush(stdout); scanf( %s , s); if (s[0] == W ) return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; int long long n, a, b, x = 4, y = 2, ans, m, ans1, ans2, ans3; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> m >> a >> b; while (x > 0 || y > 0) { ans++; n = m; while (x > 0 && n >= a) { x--; n -= a; } while (y > 0 && n >= b) { y--; n -= b; } } x = 4; y = 2; while (x > 0 || y > 0) { ans1++; n = m; while (y > 0 && n >= b) { y--; n -= b; } while (x > 0 && n >= a) { x--; n -= a; } } x = 4; y = 2; while (x > 0 || y > 0) { ans2++; n = m; while (x > 0 && y > 0 && n >= a + b) { x--; y--; n -= a + b; } while (y > 0 && n >= b) { y--; n -= b; } while (x > 0 && n >= a) { x--; n -= a; } } x = 4; y = 2; while (x > 0 || y > 0) { ans3++; n = m; while (x > 0 && y > 0 && n >= a + b) { x--; y--; n -= a + b; } while (x > 0 && n >= a) { x--; n -= a; } while (y > 0 && n >= b) { y--; n -= b; } } cout << min(min(ans, ans1), min(ans2, ans3)); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A2111O_FUNCTIONAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int dx[8] = {-1, -1, -1, 0, 1, 1, 1, 0}; const int dy[8] = {-1, 0, 1, 1, 1, 0, -1, -1}; const int MAX = 2 * 1000 + 10; const long long INF = 1e18; const int MOD = 1e9 + 7; long long n, m, x, y, a[MAX], b[MAX], c[MAX], d[MAX]; long long dp[MAX][20]; long long sol(long long n, long long ind) { if (n < 0) return -MOD; if (ind > m or n == 0) return 0; if (dp[n][ind] != -1) return dp[n][ind]; long long &ans = dp[n][ind]; ans = y + sol(n - x, ind); for (long long i = 0; i <= n; i++) { if (i * c[ind] > n or i * b[ind] > a[ind]) break; ans = max(ans, i * d[ind] + sol(n - i * c[ind], ind + 1)); } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m >> x >> y; for (long long i = 1; i <= m; i++) { cin >> a[i] >> b[i] >> c[i] >> d[i]; } memset(dp, -1, sizeof(dp)); cout << sol(n, 0) << n ; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gl_fdbk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_clk_gl_fdbk_hz(c12 ,c16 );
output c12 ;
input c16 ;
wire c13 ;
wire c14 ;
wire c15 ;
wire net26 ;
wire net043 ;
bw_clk_gclk_inv_224x x5 (
.clkout (net043 ),
.clkin (c13 ) );
bw_clk_gclk_inv_288x x6 (
.clkout (c14 ),
.clkin (c15 ) );
bw_clk_gclk_inv_224x x7 (
.clkout (c12 ),
.clkin (c13 ) );
bw_clk_gclk_inv_288x x8 (
.clkout (net26 ),
.clkin (c15 ) );
bw_clk_gclk_inv_224x xc14 (
.clkout (c15 ),
.clkin (c16 ) );
bw_clk_gclk_inv_192x x1 (
.clkout (c13 ),
.clkin (c14 ) );
endmodule
module bw_clk_gl_fdbk_vrt(c12 ,gclk );
output gclk ;
input c12 ;
wire c10 ;
wire c11a ;
wire net55 ;
wire net077 ;
wire c8 ;
wire c9 ;
wire net67 ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (net077 ),
.clkin (c8 ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8 ),
.clkin (c9 ) );
bw_clk_gclk_inv_r90_256x xc11_0_ (
.clkout (c11a ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_192x xc8_1_ (
.clkout (net55 ),
.clkin (c9 ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10 ),
.clkin (c11a ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9 ),
.clkin (c10 ) );
bw_clk_gclk_inv_r90_256x xc11_1_ (
.clkout (net67 ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (gclk ),
.clkin (c8 ) );
endmodule
module bw_clk_gl_fdbk_clstr(rclk ,gclk );
output rclk ;
input gclk ;
supply1 vdd ;
supply0 vss ;
wire [0:0] c3 ;
wire net28 ;
wire net47 ;
wire net49 ;
wire net51 ;
wire net53 ;
wire net54 ;
wire net56 ;
wire c4 ;
wire c5 ;
wire net62 ;
wire cclk ;
wire net66 ;
bw_clk_cclk_inv_128x xc2_3_ (
.clkout (net51 ),
.clkin (c3[0] ) );
bw_clk_cclk_inv_96x xc3_1_ (
.clkout (net66 ),
.clkin (c4 ) );
bw_clk_cclk_inv_64x xc4_0_ (
.clkout (c4 ),
.clkin (c5 ) );
bw_clk_cclk_inv_64x xc4_1_ (
.clkout (net62 ),
.clkin (c5 ) );
bw_clk_cclk_inv_48x xc5_0_ (
.clkout (c5 ),
.clkin (cclk ) );
bw_clk_cclk_inv_48x xc5_1_ (
.clkout (net28 ),
.clkin (cclk ) );
bw_clk_cclk_hdr_64x xclhdr (
.cluster_cken (vdd ),
.grst_l (vdd ),
.arst_l (vdd ),
.adbginit_l (vdd ),
.gclk (gclk ),
.rst_l (net53 ),
.dbginit_l (net54 ),
.so (net56 ),
.clk (cclk ),
.se (vss ),
.si (vss ),
.gdbginit_l (vdd ),
.rclk (vss ) );
bw_clk_cclk_inv_128x xc2_0_ (
.clkout (rclk ),
.clkin (c3[0] ) );
bw_clk_cclk_inv_128x xc2_1_ (
.clkout (net47 ),
.clkin (c3[0] ) );
bw_clk_cclk_inv_128x xc2_2_ (
.clkout (net49 ),
.clkin (c3[0] ) );
bw_clk_cclk_inv_96x xc3_0_ (
.clkout (c3[0] ),
.clkin (c4 ) );
endmodule
module bw_clk_gl_fdbk(clk_fdbk_in ,clk_fdbk_out );
output clk_fdbk_out ;
input clk_fdbk_in ;
wire clk12 ;
wire gclk ;
bw_clk_gl_fdbk_hz i0 (
.c12 (clk12 ),
.c16 (clk_fdbk_in ) );
bw_clk_gl_fdbk_vrt i1 (
.c12 (clk12 ),
.gclk (gclk ) );
bw_clk_gl_fdbk_clstr i2 (
.rclk (clk_fdbk_out ),
.gclk (gclk ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int k, x, n, m; scanf( %d%d%d%d , &k, &x, &n, &m); for (int f1 = 0; f1 <= 1; f1++) { for (int f2 = 0; f2 <= 1; f2++) { for (int f3 = 0; f3 <= 1; f3++) { int h1 = n, h2 = m; if (f1) h1--; if (f1 || f3) h2--; if (f2) h1--, h2--; if (!f2 && f3) h2--; if (h1 < 0 || h2 < 0) continue; for (int i = 0; i <= h1 / 2; i++) { for (int j = 0; j <= h2 / 2; j++) { long long las1 = i, las2 = j; for (int t = 3; t <= k; t++) { long long tmp1 = las2, tmp2 = las1 + las2; las1 = tmp1, las2 = tmp2; if (t == 3 && f1) las2++; if (t >= 4 && t % 2 == 0 && f2) las2++; if (t >= 4 && t % 2 == 1 && f3) las2++; } if (las2 == x) { if (f2) printf( C ); for (int h = 1; h <= i; h++) printf( AC ); for (int h = 1; h <= h1 - 2 * i; h++) printf( Z ); if (f1) printf( A ); printf( n ); if (f1 || f3) printf( C ); for (int h = 1; h <= j; h++) printf( AC ); for (int h = 1; h <= h2 - 2 * j; h++) printf( Z ); if (f2 || f3) printf( A ); printf( n ); return 0; } } } } } } printf( Happy new year! n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int sz2 = 5e5 + 1; int fact[sz2]; int inv_fact[sz2]; int mul(int a, int b) { return (long long)a * b % mod; } int add(int a, int b) { int res = (long long)a + b; if (res < 0) res += mod; else if (res > mod) res -= mod; return res; } int bpow(int x, int p) { int res = 1; while (p) { if (p & 1) res = mul(res, x); p >>= 1; if (p) x = mul(x, x); } return res; } int inv(int x) { return bpow(x, mod - 2); } void calc_fact() { fact[0] = inv_fact[0] = 1; for (int i = 1; i < sz2; i++) { fact[i] = mul(fact[i - 1], i); inv_fact[i] = inv(fact[i]); } } int cnk(int n, int k) { if (k > n) return 0; return mul(fact[n], mul(inv_fact[k], inv_fact[n - k])); } const int sz = 55; int dp[sz * sz][sz][sz]; int dp1[sz * sz][sz]; int dp2[sz][sz][sz][sz][3]; void solve() { int n, t; cin >> n >> t; vector<pair<int, int>> a(n); for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; a[i].second--; } dp[0][0][0] = 1; dp1[0][0] = 1; for (int i = 0; i < n; i++) { if (a[i].second <= 1) { for (int j = t; j >= 0; j--) { for (int k = 0; k < n; k++) { for (int l = 0; l < n; l++) { if (j + a[i].first <= t) dp[j + a[i].first][k + (a[i].second == 0)] [l + (a[i].second == 1)] = add(dp[j + a[i].first][k + (a[i].second == 0)] [l + (a[i].second == 1)], dp[j][k][l]); } } } } else { for (int j = t; j >= 0; j--) { for (int k = 0; k < n; k++) { if (j + a[i].first <= t) dp1[j + a[i].first][k + 1] = add(dp1[j + a[i].first][k + 1], dp1[j][k]); } } } } dp2[1][1][0][0][0] = 1; dp2[1][0][1][0][1] = 1; dp2[1][0][0][1][2] = 1; for (int i = 1; i < n; i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k <= n; k++) { for (int l = 0; l <= n; l++) { for (int h = 0; h < 3; h++) { for (int g = 0; g < 3; g++) { if (g != h) dp2[i + 1][j + (g == 0)][k + (g == 1)][l + (g == 2)][g] = add(dp2[i + 1][j + (g == 0)][k + (g == 1)][l + (g == 2)][g], dp2[i][j][k][l][h]); } } } } } } int ans = 0; for (int i = 0; i <= t; i++) { for (int j = 0; j <= n; j++) { for (int k = 0; k <= n; k++) { for (int l = 0; l <= n; l++) { if (j + k + l > n) continue; int p = mul( mul(dp[i][j][k], dp1[t - i][l]), add(dp2[j + k + l][j][k][l][0], add(dp2[j + k + l][j][k][l][1], dp2[j + k + l][j][k][l][2]))); int r = mul(fact[j], mul(fact[k], fact[l])); ans = add(ans, mul(p, r)); } } } } cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); calc_fact(); int q = 1; for (; q > 0; q--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int b, p, f; int h, c; cin >> b >> p >> f >> h >> c; if (b >= p * 2 + f * 2) cout << p * h + f * c << endl; else { if (c >= h) { cout << min(b / 2, f) * c + min((b - min(b / 2, f) * 2) / 2, p) * h << endl; } else cout << min(b / 2, p) * h + min((b - min(b / 2, p) * 2) / 2, f) * c << endl; } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/06/2016 02:02:25 PM
// Design Name:
// Module Name: mdct_myidct
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module stego_encode(clk, rst, start, message, data_in, data_out, rdy);
output [7:0] data_out;
output rdy;
input clk, rst, start, message;
input [7:0] data_in;
wire rdy;
wire [7:0] data_out;
wire [11:0] dct;
wire rdy_i;
// 1/18*4096
reg signed [8:0] Q_1 = {9'd228};
// 18*4096
reg signed [5:0] Q_2 = {6'd18};
// signed intermediate input
reg signed [11:0] dct_signed;
reg signed [11:0] dct_signed_2;
reg signed [20:0] dct_q_i_0;
reg signed [20:0] dct_q_i_1;
reg signed [8:0] dct_q_i_2;
reg signed [8:0] dct_q_i_3;
// qunatized dct coifficient
reg signed [8:0] dct_q;
reg signed [8:0] data_out_i_0;
reg signed [14:0] data_out_i_1;
reg signed [14:0] data_out_i_2;
reg signed [11:0] data_out_i_3;
reg signed [11:0] data_out_i_4;
reg signed [11:0] data_out_i;
// counter of time
reg [5:0] cnt_t;
reg [12:0] start_on_count;
reg start_force=0, start_forced=0;
reg start_went_on;
// Msg fifo things
reg [5:0] start_cnt;
reg [5:0] rdy_cnt;
wire wr_en, rd_en;
reg msg_embed;
reg [2:0] wr_bit;
reg [2:0] rd_bit;
reg [7:0] msg_fifo;
reg [18:0] lfsr_1;
reg [21:0] lfsr_2;
reg [22:0] lfsr_3;
wire lfsr_out;
always @(posedge clk) begin
if (rst) begin
start_on_count <= 0;
start_went_on <= 0;
end
else begin
if (start) begin
start_on_count <= 0;
start_went_on <= 1;
end
if (~start && start_went_on && ~start_forced) begin
start_on_count <= start_on_count + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
start_force <= 0;
start_forced <= 0;
end else begin
if (start_on_count >= 11'd1000 && start_on_count <= 11'd1128) begin
//start_force <= 1;
end else begin
start_force <= 0;
end
if (start_on_count == 11'd1128) begin
start_forced <= 1;
end else begin
start_forced <= start_forced;
end
end
end
reg [2:0] rdy_i_d;
always @(posedge clk) begin
if (rst) begin
rdy_i_d <= 0;
end else begin
rdy_i_d <= {rdy_i_d[1:0], rdy_i};
end
end
always @(posedge clk) begin
if (rst) begin
cnt_t <= 0;
end
else begin
if (rdy_i_d[0]) begin
cnt_t <= cnt_t + 1;
end
end
end
// Pipeline stage 1
always @(*) begin
dct_q_i_0 = dct_signed*Q_1;
dct_q_i_1 = dct_q_i_0[20] == 1 ? ~dct_q_i_0+1 : dct_q_i_0;
dct_q_i_2 = dct_q_i_1[11] == 1 ? dct_q_i_1[20:12]+12'd1 : dct_q_i_1[20:12];
dct_q_i_3 = dct_q_i_0[20] == 1 ? ~dct_q_i_2+1 : dct_q_i_2;
end
// Pipeline stage 2
always @(*) begin
data_out_i_0 = dct_q;
data_out_i_0[0] = msg_embed;
data_out_i_1 = data_out_i_0*Q_2;
data_out_i_2 = (data_out_i_1[14] == 1) ? ~data_out_i_1+1 : data_out_i_1;
data_out_i_3 = (|(data_out_i_2[14:11]) ? (data_out_i_1[14] == 1 ? -12'd2048 : 12'd2047) : data_out_i_2[11:0]);
data_out_i_4 = (data_out_i_1[14] == 1) ? ~data_out_i_3+1 : data_out_i_3;
end
reg rdy_debug;
always @(posedge clk) begin
if (rst) begin
dct_signed <= 0;
dct_signed_2 <= 0;
data_out_i <= 0;
dct_q <= 0;
rdy_debug <= 0;
end
else begin
// Pipeline stage 1
if (rdy_i) begin
dct_signed <= dct;
end
// Pipeline stage 2
if (rdy_i_d[0]) begin
dct_q <= dct_q_i_3;
dct_signed_2 <= dct_signed;
end
// Pipeline stage 3
if (rdy_i_d[1]) begin
data_out_i <= (cnt_t == 6'd43 ? data_out_i_4 : dct_signed_2);
if (cnt_t == 6'd43) begin
rdy_debug <= 1;
end
else begin
rdy_debug <= 0;
end
end
end
end
always @(posedge clk) begin
if (rst) begin
start_cnt <= 0;
rdy_cnt <= 0;
end else begin
if (start) begin
start_cnt <= start_cnt + 1'b1;
end
if (rdy_i) begin
rdy_cnt <= rdy_cnt + 1'b1;
end
end
end
assign wr_en = ((start_cnt == 0) && start);
assign rd_en = ((rdy_cnt == 0) && rdy_i);
always @(posedge clk) begin
if (rst) begin
wr_bit <= 0;
rd_bit <= 0;
msg_fifo <= 0;
msg_embed <= 0;
end else begin
if (wr_en) begin
wr_bit <= wr_bit + 1'b1;
msg_fifo[wr_bit] <= message;
end
if (rd_en) begin
rd_bit <= rd_bit + 1'b1;
msg_embed <= msg_fifo[rd_bit]^lfsr_out;
end
end
end
assign lfsr_out = lfsr_1[18] ^ lfsr_2[21] ^ lfsr_3[22];
always @(posedge clk) begin
if (rst) begin
lfsr_1 <= 19'd1876;
lfsr_2 <= 22'd20007;
lfsr_3 <= 23'd14376;
end
else begin
if (rd_en) begin
lfsr_1 <= {lfsr_1[17:0], lfsr_1[18]^lfsr_1[17]^lfsr_1[16]^lfsr_1[13]};
lfsr_2 <= {lfsr_2[20:0], lfsr_2[21]^lfsr_2[20]};
lfsr_3 <= {lfsr_3[21:0], lfsr_3[22]^lfsr_3[21]^lfsr_3[20]^lfsr_3[7]};
end
end
end
MDCT dct_1 (.clk(clk), .rst(rst), .dcti(data_in), .idv(start), .odv(rdy_i), .dcto(dct));
myidct_less_lut idct_1 (.clk(clk), .rst(rst), .dct_2d(data_out_i), .start( rdy_i_d[2]|start_force), .rdy(rdy), .idct_2d(data_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; int l[5010], r[5010]; vector<int> vc; long long f[2][10100]; int cost[10100]; int doit(int x, int y) { if (vc[x] <= l[y]) return l[y] - vc[x]; if (vc[x] >= r[y]) return vc[x] - r[y]; return 0; } int main() { int start = 0; int n; scanf( %d %d , &n, &start); vc.push_back(start); for (int i = 1; i <= n; ++i) { scanf( %d %d , &l[i], &r[i]); vc.push_back(l[i]); vc.push_back(r[i]); } sort(vc.begin(), vc.end()); vc.erase(unique(vc.begin(), vc.end()), vc.end()); int now = 0, nxt = 1; int cnt = vc.size(); for (int i = 0; i < cnt; ++i) { cost[i] = doit(i, 1); } for (int i = 0; i < cnt; ++i) { f[now][i] = abs(vc[i] - start) + cost[i]; } for (int i = 1; i < n; ++i) { memset(cost, 0, sizeof cost); for (int j = 0; j < cnt; ++j) { cost[j] = doit(j, i + 1); } int mn = f[now][cnt - 1], mx = cnt - 1; for (int j = cnt - 1; j >= 0; --j) { if (j < cnt - 1 && f[now][j] - (vc[cnt - 1] - vc[j]) < mn) { mn = f[now][j] - (vc[cnt - 1] - vc[j]); mx = j; } f[nxt][j] = f[now][mx] + vc[mx] - vc[j] + cost[j]; } mn = f[now][0], mx = 0; for (int j = 0; j < cnt; ++j) { if (j && f[now][j] - (vc[j] - vc[0]) < mn) { mn = f[now][j] - (vc[j] - vc[0]); mx = j; } f[nxt][j] = min(f[nxt][j], f[now][mx] + vc[j] - vc[mx] + cost[j]); } swap(now, nxt); } long long ans = 1e18; for (int i = 0; i < cnt; ++i) ans = min(ans, f[now][i]); printf( %I64d n , ans); } |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S4_altera_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAMB16_S4_altera_new (
address,
clken,
clock,
data,
wren,
q);
input [7:0] address;
input clken;
input clock;
input [11:0] data;
input wren;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.clocken0 (clken),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "lr_new.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "lr_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "lr_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long a[5010], b[5010], n, dp[5010]; int main() { cin >> n; for (long long i = 1ll; i <= n; i++) scanf( %I64d , &a[i]), b[i] = a[i]; sort(b + 1ll, b + n + 1ll); dp[0ll] = (long long)1000000000000000007; for (long long i = 1ll; i <= n; i++) { for (long long j = 1ll; j <= n; j++) { dp[j] = min(dp[j - 1ll], dp[j] + abs(b[j] - a[i])); } } cout << dp[n] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k, ans = 0, t; cin >> t; while (t--) { cin >> n >> k; ans = 0; while (n > 0) { if (n % k == 0) { n /= k; ans++; } else { ans += n % k; n -= n % k; } } cout << ans << n ; } } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: Sora_RCB_top
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Non-Posted Packet Generator wrapper file.
// Connects the NonPosted Packet Slicer and Non-Posted Packet Builder modules
// together
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang:
// add logic for TX descriptor request ----------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module non_posted_pkt_gen(
input clk,
input rst,
/// Jiansong: control signal for transfer recovering
input transferstart,
//inputs from dma_ctrl_wrapper
input [63:0] dmaras,
input [31:0] dmarad,
input [31:0] dmarxs,
input rd_dma_start_one,
/// Jiansong: added for TX descriptor request
input rd_TX_des_start_one,
input [63:0] TX_des_addr,
//inputs from pcie block plus
input [2:0] read_req_size,
input [15:0] req_id,
//outputs to non posted header fifo
output non_posted_fifo_wren,
output [63:0] non_posted_fifo_data,
//in and outs to tag_generator
output tag_inc,
input tag_gnt,
input [7:0] tag_value,
//outputs to read_request_wrapper
output [4:0] tx_waddr,
output [31:0] tx_wdata,
output tx_we
);
//internal wrapper connections
wire [31:0] dmarad_reg;
wire [63:0] dmaras_reg;
wire [9:0] length;
wire ack,go; //handshake signals
wire isDes;
non_posted_pkt_slicer non_posted_pkt_slicer_inst(
.clk(clk),
.rst(rst),
/// Jiansong: control signal for transfer recovering
.transferstart(transferstart),
//interface to dma_ctrl_wrapper
.rd_TX_des_start_one(rd_TX_des_start_one),/// Jiansong:
.TX_des_addr(TX_des_addr), /// added for TX des request
.isDes(isDes), ///
.rd_dma_start(rd_dma_start_one),
.dmarad(dmarad),
.dmarxs(dmarxs),
.dmaras(dmaras),
.read_req_size(read_req_size), //from pcie block
//interface to non_posted_pkt_builder
.ack(ack),
.go(go),
.dmarad_reg(dmarad_reg[31:0]),
.dmaras_reg(dmaras_reg[63:0]),
.length(length[9:0])
);
non_posted_pkt_builder non_posted_pkt_builder_inst(
.clk(clk),
.rst(rst),
.req_id(req_id[15:0]), //from pcie block
//interface to/from non_posted_pkt_slicer
.go(go),
.ack(ack),
.dmaras(dmaras_reg[63:0]),
.dmarad(dmarad_reg[31:0]),
.length(length[9:0]),
.isDes(isDes), /// Jiansong:
//interface to/from tag_generator
.tag_value(tag_value[7:0]),
.tag_gnt(tag_gnt),
.tag_inc(tag_inc),
//interface to/from a64_64_distram_np(non-posted header fifo)
.header_data_out(non_posted_fifo_data[63:0]),
.header_data_wren(non_posted_fifo_wren),
//interface to read_request_wrapper
.tx_waddr(tx_waddr[4:0]),
.tx_wdata(tx_wdata[31:0]),
.tx_we(tx_we)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 7; int cnt[N], a[N], idx, l, r, n; long long ans, sum; int main() { scanf( %d , &n); for (int i = (1); i <= (n); ++i) { scanf( %d , a + i); if (a[i] >= i) l++, cnt[a[i] - i]++; else r++; ans += abs(a[i] - i); } sum = ans, idx = 0; for (int i = (0); i <= ((n - 1)); ++i) { l -= cnt[i], r += cnt[i]; sum = sum - l + r - abs(a[n - i] - n) + a[n - i] - 2; cnt[a[n - i] + i]++, l++, r--; if (sum < ans) ans = sum, idx = i + 1; } printf( %lld %d n , ans, idx); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_V |
//
// .. hwt-autodoc::
//
module FullAdder (
input wire a,
input wire b,
input wire ci,
output reg co,
output reg s
);
always @(a, b, ci) begin: assig_process_co
co = a & b | (a & ci) | (b & ci);
end
always @(a, b, ci) begin: assig_process_s
s = a ^ b ^ ci;
end
endmodule
//
// .. hwt-autodoc::
//
module RippleAdder1 #(
parameter p_wordlength = 4
) (
input wire[3:0] a,
input wire[3:0] b,
input wire ci,
output reg co,
output reg[3:0] s
);
reg[4:0] c;
reg sig_fa_0_a;
reg sig_fa_0_b;
reg sig_fa_0_ci;
wire sig_fa_0_co;
wire sig_fa_0_s;
reg sig_fa_1_a;
reg sig_fa_1_b;
reg sig_fa_1_ci;
wire sig_fa_1_co;
wire sig_fa_1_s;
reg sig_fa_2_a;
reg sig_fa_2_b;
reg sig_fa_2_ci;
wire sig_fa_2_co;
wire sig_fa_2_s;
reg sig_fa_3_a;
reg sig_fa_3_b;
reg sig_fa_3_ci;
wire sig_fa_3_co;
wire sig_fa_3_s;
FullAdder fa_0_inst (
.a(sig_fa_0_a),
.b(sig_fa_0_b),
.ci(sig_fa_0_ci),
.co(sig_fa_0_co),
.s(sig_fa_0_s)
);
FullAdder fa_1_inst (
.a(sig_fa_1_a),
.b(sig_fa_1_b),
.ci(sig_fa_1_ci),
.co(sig_fa_1_co),
.s(sig_fa_1_s)
);
FullAdder fa_2_inst (
.a(sig_fa_2_a),
.b(sig_fa_2_b),
.ci(sig_fa_2_ci),
.co(sig_fa_2_co),
.s(sig_fa_2_s)
);
FullAdder fa_3_inst (
.a(sig_fa_3_a),
.b(sig_fa_3_b),
.ci(sig_fa_3_ci),
.co(sig_fa_3_co),
.s(sig_fa_3_s)
);
always @(ci, sig_fa_0_co, sig_fa_1_co, sig_fa_2_co, sig_fa_3_co) begin: assig_process_c
c = {{{{sig_fa_3_co, sig_fa_2_co}, sig_fa_1_co}, sig_fa_0_co}, ci};
end
always @(c) begin: assig_process_co
co = c[4];
end
always @(sig_fa_0_s, sig_fa_1_s, sig_fa_2_s, sig_fa_3_s) begin: assig_process_s
s = {{{sig_fa_3_s, sig_fa_2_s}, sig_fa_1_s}, sig_fa_0_s};
end
always @(a) begin: assig_process_sig_fa_0_a
sig_fa_0_a = a[0];
end
always @(b) begin: assig_process_sig_fa_0_b
sig_fa_0_b = b[0];
end
always @(c) begin: assig_process_sig_fa_0_ci
sig_fa_0_ci = c[0];
end
always @(a) begin: assig_process_sig_fa_1_a
sig_fa_1_a = a[1];
end
always @(b) begin: assig_process_sig_fa_1_b
sig_fa_1_b = b[1];
end
always @(c) begin: assig_process_sig_fa_1_ci
sig_fa_1_ci = c[1];
end
always @(a) begin: assig_process_sig_fa_2_a
sig_fa_2_a = a[2];
end
always @(b) begin: assig_process_sig_fa_2_b
sig_fa_2_b = b[2];
end
always @(c) begin: assig_process_sig_fa_2_ci
sig_fa_2_ci = c[2];
end
always @(a) begin: assig_process_sig_fa_3_a
sig_fa_3_a = a[3];
end
always @(b) begin: assig_process_sig_fa_3_b
sig_fa_3_b = b[3];
end
always @(c) begin: assig_process_sig_fa_3_ci
sig_fa_3_ci = c[3];
end
generate if (p_wordlength != 4)
$error("%m Generated only for this param value");
endgenerate
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// TOP
//-----------------------------------------------------------------
module top
(
// 32MHz clock
input clk /*verilator public*/,
// UART
input rx /*verilator public*/,
output tx /*verilator public*/,
// I/O Bus
inout [15:0] W1A /*verilator public*/,
inout [15:0] W1B /*verilator public*/,
inout [15:0] W2C /*verilator public*/,
// SPI Flash
output flash_cs /*verilator public*/,
output flash_si /*verilator public*/,
input flash_so /*verilator public*/,
output flash_sck /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter OSC_KHZ = 32000;
parameter CLK_KHZ = 32000;
parameter UART_BAUD = 115200;
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
// Port C
`define W2C_UNUSED_RANGE 15:0
`define W2C_UNUSED_WIDTH 16
// Port B
`define W1B_UNUSED_RANGE 15:0
`define W1B_UNUSED_WIDTH 16
// Port A
`define W1A_UNUSED_RANGE 15:0
`define W1A_UNUSED_WIDTH 16
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// Reset
reg reset = 1'b1;
reg rst_next = 1'b1;
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire dmem_we;
wire dmem_stb;
reg dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
reg imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
wire [3:0] dmem_web = (dmem_stb & dmem_we) ? dmem_sel : 4'b0;
// BlockRAM
ram
#(
.block_count(3) // 24KB
)
u_ram
(
.clka_i(clk),
.ena_i(1'b1),
.wea_i(4'b0),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.clkb_i(clk),
.enb_i(1'b1),
.web_i(dmem_web),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r)
);
// CPU
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE("DISABLED"),
.ENABLE_DCACHE("DISABLED"),
.REGISTER_FILE_TYPE("XILINX")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk),
.rst_i(reset),
.fault_o(),
.break_o(),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(),
.imem0_cyc_o(),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(),
.dmem0_cyc_o(),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.UART_BAUD(UART_BAUD),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk),
.rst_i(reset),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
.uart_tx_o(tx),
.uart_rx_i(rx),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
// Reset Generator
always @(posedge clk)
if (rst_next == 1'b0)
reset <= 1'b0;
else
rst_next <= 1'b0;
// Ack
always @(posedge clk or posedge reset)
if (reset == 1'b1)
dmem_ack <= 1'b0;
else
dmem_ack <= dmem_stb;
// Ack
always @(posedge clk or posedge reset)
if (reset == 1'b1)
imem_ack <= 1'b0;
else
imem_ack <= imem_stb;
//-----------------------------------------------------------------
// Unused pins
//-----------------------------------------------------------------
assign W1A[`W1A_UNUSED_RANGE] = {`W1A_UNUSED_WIDTH{1'bz}};
assign W1B[`W1B_UNUSED_RANGE] = {`W1B_UNUSED_WIDTH{1'bz}};
assign W2C[`W2C_UNUSED_RANGE] = {`W2C_UNUSED_WIDTH{1'bz}};
assign flash_cs = 1'b0;
assign flash_sck = 1'b0;
assign flash_si = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> static ostream& operator<<(ostream& stream, const vector<T>& t); template <typename T> static istream& read(T, T, istream& = cin); template <typename T> static istream& operator>>(istream& stream, vector<T>& t) { return read((t).begin(), (t).end(), stream); } template <typename T> static istream& read(T b, T e, istream& stream) { for (T it = b; it != e; ++it) stream >> *it; return stream; } template <typename T> static void print(T x, string end = n ) { cout << x << end; } template <typename T> static ostream& print(T b, T e, string sep = , ostream& stream = cout) { for (T it = b; it != e; ++it) { stream << *it; if (it + 1 != e) stream << sep; } return stream; } template <typename T> static void print(vector<T> arr, string sep = ) { if (arr.empty()) { return; } print(arr.begin(), arr.end(), sep); cout << n ; } void _() { int n; cin >> n; vector<int> arr(n); cin >> arr; vector<int> tmp(1, n + 1); vector<string> ans(n + 1, string(n, 0 )); for (int j = 0; j <= n - 1; ++j) { int l = 0; vector<int> n_tmp; int ones = arr[j], zeros = n + 1 - arr[j]; for (int x : tmp) { int take_zeros = min(zeros, x - (ones > 0)); int take_ones = x - take_zeros; if (x == 1) { if (ones > zeros) take_ones = 1, take_zeros = 0; else take_ones = 0, take_zeros = 1; } zeros -= take_zeros; ones -= take_ones; for (int i = l; i <= l + take_zeros - 1; ++i) ans[i][j] = 0 ; l += take_zeros; for (int i = l; i <= l + take_ones - 1; ++i) ans[i][j] = 1 ; l += take_ones; if (take_zeros) n_tmp.push_back(take_zeros); if (take_ones) n_tmp.push_back(take_ones); } tmp = n_tmp; } print(n + 1); print(ans, n ); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << fixed << setprecision(15); _(); } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_performance_counter (
// inputs:
address,
begintransfer,
clk,
reset_n,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 3: 0] address;
input begintransfer;
input clk;
input reset_n;
input write;
input [ 31: 0] writedata;
wire clk_en;
reg [ 63: 0] event_counter_0;
reg [ 63: 0] event_counter_1;
reg [ 63: 0] event_counter_2;
reg [ 63: 0] event_counter_3;
wire global_enable;
wire global_reset;
wire go_strobe_0;
wire go_strobe_1;
wire go_strobe_2;
wire go_strobe_3;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
wire stop_strobe_0;
wire stop_strobe_1;
wire stop_strobe_2;
wire stop_strobe_3;
reg [ 63: 0] time_counter_0;
reg [ 63: 0] time_counter_1;
reg [ 63: 0] time_counter_2;
reg [ 63: 0] time_counter_3;
reg time_counter_enable_0;
reg time_counter_enable_1;
reg time_counter_enable_2;
reg time_counter_enable_3;
wire write_strobe;
//control_slave, which is an e_avalon_slave
assign clk_en = -1;
assign write_strobe = write & begintransfer;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_0 <= 0;
else if ((time_counter_enable_0 & global_enable) | global_reset)
if (global_reset)
time_counter_0 <= 0;
else
time_counter_0 <= time_counter_0 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_0 <= 0;
else if ((go_strobe_0 & global_enable) | global_reset)
if (global_reset)
event_counter_0 <= 0;
else
event_counter_0 <= event_counter_0 + 1;
end
assign stop_strobe_0 = (address == 0) && write_strobe;
assign go_strobe_0 = (address == 1) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_0 <= 0;
else if (clk_en)
if (stop_strobe_0 | global_reset)
time_counter_enable_0 <= 0;
else if (go_strobe_0)
time_counter_enable_0 <= -1;
end
assign global_enable = time_counter_enable_0 | go_strobe_0;
assign global_reset = stop_strobe_0 && writedata[0];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_1 <= 0;
else if ((time_counter_enable_1 & global_enable) | global_reset)
if (global_reset)
time_counter_1 <= 0;
else
time_counter_1 <= time_counter_1 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_1 <= 0;
else if ((go_strobe_1 & global_enable) | global_reset)
if (global_reset)
event_counter_1 <= 0;
else
event_counter_1 <= event_counter_1 + 1;
end
assign stop_strobe_1 = (address == 4) && write_strobe;
assign go_strobe_1 = (address == 5) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_1 <= 0;
else if (clk_en)
if (stop_strobe_1 | global_reset)
time_counter_enable_1 <= 0;
else if (go_strobe_1)
time_counter_enable_1 <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_2 <= 0;
else if ((time_counter_enable_2 & global_enable) | global_reset)
if (global_reset)
time_counter_2 <= 0;
else
time_counter_2 <= time_counter_2 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_2 <= 0;
else if ((go_strobe_2 & global_enable) | global_reset)
if (global_reset)
event_counter_2 <= 0;
else
event_counter_2 <= event_counter_2 + 1;
end
assign stop_strobe_2 = (address == 8) && write_strobe;
assign go_strobe_2 = (address == 9) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_2 <= 0;
else if (clk_en)
if (stop_strobe_2 | global_reset)
time_counter_enable_2 <= 0;
else if (go_strobe_2)
time_counter_enable_2 <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_3 <= 0;
else if ((time_counter_enable_3 & global_enable) | global_reset)
if (global_reset)
time_counter_3 <= 0;
else
time_counter_3 <= time_counter_3 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_3 <= 0;
else if ((go_strobe_3 & global_enable) | global_reset)
if (global_reset)
event_counter_3 <= 0;
else
event_counter_3 <= event_counter_3 + 1;
end
assign stop_strobe_3 = (address == 12) && write_strobe;
assign go_strobe_3 = (address == 13) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_3 <= 0;
else if (clk_en)
if (stop_strobe_3 | global_reset)
time_counter_enable_3 <= 0;
else if (go_strobe_3)
time_counter_enable_3 <= -1;
end
assign read_mux_out = ({32 {(address == 0)}} & time_counter_0[31 : 0]) |
({32 {(address == 1)}} & time_counter_0[63 : 32]) |
({32 {(address == 2)}} & event_counter_0) |
({32 {(address == 4)}} & time_counter_1[31 : 0]) |
({32 {(address == 5)}} & time_counter_1[63 : 32]) |
({32 {(address == 6)}} & event_counter_1) |
({32 {(address == 8)}} & time_counter_2[31 : 0]) |
({32 {(address == 9)}} & time_counter_2[63 : 32]) |
({32 {(address == 10)}} & event_counter_2) |
({32 {(address == 12)}} & time_counter_3[31 : 0]) |
({32 {(address == 13)}} & time_counter_3[63 : 32]) |
({32 {(address == 14)}} & event_counter_3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char buf[1 << 20], *p1, *p2; template <class T> inline void read(T &n) { char ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 20, stdin), p1 == p2) ? 0 : *p1++); T w = 1, x = 0; while (!isdigit(ch)) { if (ch == - ) w = -1; ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 20, stdin), p1 == p2) ? 0 : *p1++); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 20, stdin), p1 == p2) ? 0 : *p1++); } n = x * w; } const int maxn = 200005; int n, m, q; char s[maxn]; int sa[maxn], rk[maxn], y[maxn]; void Rsort() { static int c[maxn]; for (int i = 1; i <= m; i++) c[i] = 0; for (int i = 1; i <= n; i++) c[rk[i]]++; for (int i = 1; i <= m; i++) c[i] += c[i - 1]; for (int i = n; i >= 1; i--) sa[c[rk[y[i]]]--] = y[i]; } void getSA() { for (int i = 1; i <= n; i++) rk[i] = s[i], y[i] = i; m = 122, Rsort(); for (int k = 1;; k <<= 1) { int num = 0; for (int i = n - k + 1; i <= n; i++) y[++num] = i; for (int i = 1; i <= n; i++) if (sa[i] > k) y[++num] = sa[i] - k; Rsort(), swap(rk, y); num = rk[sa[1]] = 1; for (int i = 2; i <= n; i++) { if (y[sa[i]] == y[sa[i - 1]] && y[sa[i] + k] == y[sa[i - 1] + k]) rk[sa[i]] = num; else rk[sa[i]] = ++num; } if (num == n) return; m = num; } } int height[maxn], st[maxn][19], Log[maxn]; void getheight() { for (int i = 1, k = 0; i <= n; i++) { if (rk[i] == 1) continue; if (k) k--; int j = sa[rk[i] - 1]; while (i + k <= n && j + k <= n && s[i + k] == s[j + k]) k++; height[rk[i]] = k; } for (int i = 2; i <= n; i++) Log[i] = Log[i >> 1] + 1; for (int i = 1; i <= n; i++) st[i][0] = height[i]; for (int j = 1; j <= Log[n]; j++) for (int i = 1; i + (1 << j) - 1 <= n; i++) st[i][j] = min(st[i][j - 1], st[i + (1 << (j - 1))][j - 1]); } int query(int l, int r) { if (rk[l] > rk[r]) swap(l, r); int L = rk[l] + 1, R = rk[r]; int i = Log[R - L + 1]; return min(st[L][i], st[R - (1 << i) + 1][i]); } int A[maxn], B[maxn], X, Y, bel[maxn]; int bot[maxn << 1], tot, S[maxn << 1], top, sum[maxn << 1], h[maxn << 1]; bool cmp(int x, int y) { return rk[x] < rk[y]; } long long ans, f[maxn << 1]; void solve() { read(X), read(Y); ans = tot = 0; for (int i = 1; i <= X; i++) { read(A[i]); bel[A[i]] = 1, bot[++tot] = A[i]; } for (int i = 1; i <= Y; i++) { read(B[i]); if (bel[B[i]]) ans += n - B[i] + 1, bel[B[i]] = 3; else bel[B[i]] = 2, bot[++tot] = B[i]; } sort(bot + 1, bot + tot + 1, cmp); top = 0; for (int i = 1; i <= tot; i++) sum[i] = sum[i - 1] + (bel[bot[i]] >= 2); for (int i = 1; i <= tot; i++) { h[i] = query(bot[i], bot[i - 1]); while (top && h[i] < h[S[top]]) top--; f[i] = f[S[top]] + 1ll * h[i] * (sum[i - 1] - sum[S[top] - 1]); if (bel[bot[i]] & 1) ans += f[i]; S[++top] = i; } top = 0; for (int i = 1; i <= tot; i++) sum[i] = sum[i - 1] + (bel[bot[i]] & 1); for (int i = 1; i <= tot; i++) { while (top && h[i] < h[S[top]]) top--; f[i] = f[S[top]] + 1ll * h[i] * (sum[i - 1] - sum[S[top] - 1]); if (bel[bot[i]] >= 2) ans += f[i]; S[++top] = i; } for (int i = 1; i <= X; i++) bel[A[i]] = 0; for (int i = 1; i <= Y; i++) bel[B[i]] = 0; printf( %lld n , ans); } int main() { scanf( %d%d , &n, &q); scanf( %s , s + 1); getSA(), getheight(); for (int i = 1; i <= q; i++) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); double fRand(double fMin, double fMax) { double f = (double)rand() / RAND_MAX; return fMin + f * (fMax - fMin); } template <class T> T min(T a, T b, T c) { return min(a, min(b, c)); } template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } int n, a[100005], cnt[100005]; vector<int> d[100005]; int power(int x, int n) { if (n == 0) return 1; if (n & 1) return ((long long)x * power(x, n - 1)) % 1000000007; int p = power(x, n / 2); return ((long long)p * p) % 1000000007; } int main() { scanf( %d , &n); for (int i = (1); i <= (n); ++i) { scanf( %d , &a[i]); ++cnt[a[i]]; } int m = *max_element(a + 1, a + n + 1); for (int x = (1); x <= (m); ++x) cnt[x] += cnt[x - 1]; for (int x = (1); x <= (m); ++x) for (int i = (x); i <= (m); i += x) d[i].push_back(x); int ans = 0; for (int x = (1); x <= (m); ++x) { int k = (int)d[x].size(), q[k]; for (int i = (0); i <= (k - 2); ++i) q[i] = cnt[d[x][i + 1] - 1] - cnt[d[x][i] - 1]; q[k - 1] = cnt[m] - cnt[d[x][k - 1] - 1]; int prod = 1; for (int i = (0); i <= (k - 2); ++i) prod = ((long long)prod * power(i + 1, q[i])) % 1000000007; prod = ((long long)prod * (power(k, q[k - 1]) - power(k - 1, q[k - 1]) + 1000000007)) % 1000000007; ans = (ans + prod) % 1000000007; } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int S[1000007], X[1000007], Y[1000007], W[1000007], C[1000007]; char s[10]; void dfs(int x) { if (!S[x]) { W[x] = X[x]; return; } dfs(X[x]); if (S[x] > 1) dfs(Y[x]); if (S[x] == 1) W[x] = W[X[x]] ^ 1; if (S[x] == 2) W[x] = W[X[x]] & W[Y[x]]; if (S[x] == 3) W[x] = W[X[x]] | W[Y[x]]; if (S[x] == 4) W[x] = W[X[x]] ^ W[Y[x]]; } void change(int x) { if (!S[x]) return; if (S[x] == 1) C[X[x]] = C[x]; if (S[x] == 2) { if (!W[X[x]] && !W[Y[x]]) C[X[x]] = C[Y[x]] = 0; else if (W[X[x]] && W[Y[x]]) C[X[x]] = C[Y[x]] = C[x]; else C[X[x]] = W[X[x]] ? 0 : C[x], C[Y[x]] = W[Y[x]] ? 0 : C[x]; } if (S[x] == 3) { if (!W[X[x]] && !W[Y[x]]) C[X[x]] = C[Y[x]] = C[x]; else if (W[X[x]] && W[Y[x]]) C[X[x]] = C[Y[x]] = 0; else C[X[x]] = W[X[x]] ? C[x] : 0, C[Y[x]] = W[Y[x]] ? C[x] : 0; } if (S[x] == 4) C[X[x]] = C[Y[x]] = C[x]; change(X[x]); if (S[x] > 1) change(Y[x]); } int main() { int n, m, x, u, v, w, q; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s%d , s, &X[i]); if (s[0] == I ) S[i] = 0; if (s[0] == N ) S[i] = 1; if (s[0] == A ) S[i] = 2; if (s[0] == O ) S[i] = 3; if (s[0] == X ) S[i] = 4; if (S[i] > 1) scanf( %d , &Y[i]); } C[1] = 1; dfs(1); change(1); for (int i = 1; i <= n; i++) { if (!S[i]) printf( %d , W[1] ^ C[i]); } printf( n ); return 0; } |
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
(* abc9_box, lib_whitebox *)
module adder_lut4(
output lut4_out,
(* abc9_carry *)
output cout,
input [0:3] in,
(* abc9_carry *)
input cin
);
parameter [0:15] LUT=0;
parameter IN2_IS_CIN = 0;
wire [0:3] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3]} : {in[0], in[1], in[2], in[3]};
// Output function
wire [0:7] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15]};
wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} :
{s1[1], s1[3], s1[5], s1[7]};
wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};
assign lut4_out = li[3] ? s3[0] : s3[1];
// Carry out function
assign cout = (s2[2]) ? cin : s2[3];
endmodule
(* abc9_lut=1, lib_whitebox *)
module frac_lut4(
input [0:3] in,
output [0:1] lut2_out,
output lut4_out
);
parameter [0:15] LUT = 0;
// Effective LUT input
wire [0:3] li = in;
// Output function
wire [0:7] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15]};
wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} :
{s1[1], s1[3], s1[5], s1[7]};
wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};
assign lut2_out[0] = s2[2];
assign lut2_out[1] = s2[3];
assign lut4_out = li[3] ? s3[0] : s3[1];
endmodule
(* abc9_flop, lib_whitebox *)
module scff(
output reg Q,
input D,
input clk
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge clk)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge R)
if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module sh_dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffs(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge S)
if (!S)
Q <= 1'b1;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffn(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffnr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge R)
if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffns(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge S)
if (!S)
Q <= 1'b1;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffsr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge S or negedge R)
if (!S)
Q <= 1'b1;
else if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffnsr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge S or negedge R)
if (!S)
Q <= 1'b1;
else if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for VHDL std.textio & ieee.std_logic_textio functions implemented using VPI.
`timescale 1ns/1ns
typedef enum integer { false, true } boolean;
typedef enum integer { read_mode , write_mode , append_mode } file_open_kind;
module vhdl_textio_test;
string line;
int file;
string str;
bit [3:0][7:0] str_lim;
real r;
int in;
integer i;
byte by;
time t;
boolean boo;
logic l;
logic [7:0] lv;
bit bi;
bit [7:0] biv;
initial begin
static string filename = "vpi_textio_text.tmp";
// values to be saved
str = "test_string";
str_lim = "TEST";
r = -2.5e3;
in = 120;
i = -12;
by = 8'h1f;
t = 100ns;
boo = true;
l = 1'bx;
lv = 8'b110101xz;
bi = 1'b0;
biv = 8'b10111001;
// write test
$ivlh_file_open(file, filename, write_mode);
$ivlh_write(line, str, 0); // standard format
$ivlh_write(line, " ", 0);
$ivlh_write(line, str_lim, 4); // string format
$ivlh_write(line, " ", 0);
$ivlh_write(line, r, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, in, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, i, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, by, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, t, 2); // time format
// this will be intentionally skipped during the read test
$ivlh_write(line, " ", 0);
$ivlh_write(line, l, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, lv, 0);
if(line != "test_string TEST -2500.000000 120 -12 31 100 ns X 110101XZ") begin
$display("FAILED 1");
$finish();
end
$ivlh_writeline(file, line);
// writeline should clear the written string
if(line != "") begin
$display("FAILED 2");
$finish();
end
$ivlh_write(line, boo, 1); // boolean format
$ivlh_write(line, " ", 0);
$ivlh_write(line, l, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, lv, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, bi, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, biv, 0);
$ivlh_write(line, " ", 0);
$ivlh_write(line, biv, 3); // hex format
if(line != "TRUE X 110101XZ 0 10111001 B9") begin
$display("FAILED 3");
$finish();
end
$ivlh_writeline(file, line);
$fclose(file);
// reset variables
str = "";
r = 0;
in = 0;
i = 0;
by = 0;
t = 0s;
boo = false;
l = 0;
lv = 0;
bi = 0;
biv = 0;
// read test
$ivlh_file_open(file, filename, read_mode );
$ivlh_readline(file, line);
$ivlh_read(line, str, 0); // standard format
$ivlh_read(line, str_lim, 4); // string format
$ivlh_read(line, r, 0);
$ivlh_read(line, in, 0);
$ivlh_read(line, i, 0);
$ivlh_read(line, by, 0);
$ivlh_read(line, t, 2); // time format
$ivlh_readline(file, line);
$ivlh_read(line, boo, 1); // boolean format
$ivlh_read(line, l, 0);
$ivlh_read(line, lv, 0);
$ivlh_read(line, bi, 0);
$ivlh_read(line, biv, 0);
$ivlh_read(line, biv, 3); // hex format
$fclose(file);
// compare read and expected values
if(str != "test_string") begin
$display("FAILED 5");
$finish();
end
if(str_lim != "TEST") begin
$display("FAILED 6");
$finish();
end
if(r != -2.5e3) begin
$display("FAILED 7");
$finish();
end
if(in !== 120) begin
$display("FAILED 8");
$finish();
end
if(i !== -12) begin
$display("FAILED 9");
$finish();
end
if(by !== 8'h1f) begin
$display("FAILED 10");
$finish();
end
if(t != 100ns) begin
$display("FAILED 11");
$finish();
end
if(boo !== true) begin
$display("FAILED 12");
$finish();
end
if(l !== 1'bx) begin
$display("FAILED 13");
$finish();
end
if(lv !== 8'b110101xz) begin
$display("FAILED 14");
$finish();
end
if(bi !== 1'b0) begin
$display("FAILED 15");
$finish();
end
if(biv !== 8'b10111001) begin
$display("FAILED 16");
$finish();
end
$display("PASSED");
end
endmodule
|
// Library - static, Cell - th24w22, View - schematic
// LAST TIME SAVED: May 23 16:50:53 2014
// NETLIST TIME: May 23 16:51:13 2014
`timescale 1ns / 1ns
module th24w22 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24w22";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N14 ( .d(net051), .g(d), .s(net037), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net051), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net037), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net051), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net051), .g(c), .s(net037), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net051), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net035));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net035), .d(net051));
pfet_b P4 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net035));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net051));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net051);
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937_64 rng( (unsigned)chrono::system_clock::now().time_since_epoch().count()); const long double error = 1e-7; const long double PI = acosl(-1); const int nmax = 2e5 + 10; int master[nmax]; int sz[nmax]; void init(int u) { master[u] = u; sz[u] = 1; return; } int fnd(int u) { if (master[u] == u) return u; return master[u] = fnd(master[u]); } bool unite(int u, int v) { u = fnd(u); v = fnd(v); if (u == v) return false; if (sz[u] < sz[v]) swap(u, v); sz[u] += sz[v]; master[v] = u; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n, m; cin >> n >> m; vector<long long int> A(n + 1), B(m + 1); for (int i = 1; i <= n; i++) { cin >> A[i]; } for (int i = 1; i <= m; i++) { cin >> B[i]; } vector<pair<long long int, pair<int, int>>> edges; long long int totcost = 0; for (int i = 1; i <= n; i++) { int k; cin >> k; for (int j = 0; j < k; j++) { int x; cin >> x; edges.emplace_back(A[i] + B[x], make_pair(i, n + x)); totcost += A[i] + B[x]; } } for (int i = 1; i <= n + m; i++) init(i); sort(edges.begin(), edges.end()); reverse(edges.begin(), edges.end()); long long int ans = 0; for (auto e : edges) { if (unite(e.second.first, e.second.second)) ans += e.first; } ans = totcost - ans; cout << ans << endl; return 0; } |
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module xor_32(
input [31:0] a, //input values
input [31:0] b,
output [31:0] out //output value
);
//output is the XOR of a and b
assign out[0] = a[0] ^ b[0];
assign out[1] = a[1] ^ b[1];
assign out[2] = a[2] ^ b[2];
assign out[3] = a[3] ^ b[3];
assign out[4] = a[4] ^ b[4];
assign out[5] = a[5] ^ b[5];
assign out[6] = a[6] ^ b[6];
assign out[7] = a[7] ^ b[7];
assign out[8] = a[8] ^ b[8];
assign out[9] = a[9] ^ b[9];
assign out[10] = a[10] ^ b[10];
assign out[11] = a[11] ^ b[11];
assign out[12] = a[12] ^ b[12];
assign out[13] = a[13] ^ b[13];
assign out[14] = a[14] ^ b[14];
assign out[15] = a[15] ^ b[15];
assign out[16] = a[16] ^ b[16];
assign out[17] = a[17] ^ b[17];
assign out[18] = a[18] ^ b[18];
assign out[19] = a[19] ^ b[19];
assign out[20] = a[20] ^ b[20];
assign out[21] = a[21] ^ b[21];
assign out[22] = a[22] ^ b[22];
assign out[23] = a[23] ^ b[23];
assign out[24] = a[24] ^ b[24];
assign out[25] = a[25] ^ b[25];
assign out[26] = a[26] ^ b[26];
assign out[27] = a[27] ^ b[27];
assign out[28] = a[28] ^ b[28];
assign out[29] = a[29] ^ b[29];
assign out[30] = a[30] ^ b[30];
assign out[31] = a[31] ^ b[31];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; void err() { cout << 033[39;0m << endl; } template <class T, class... Ts> void err(const T& arg, const Ts&... args) { cout << arg << ; err(args...); } const int N = 100000 + 5; int n, h, m, k; int H[N]; pair<int, int> M[N]; int main() { scanf( %d%d%d%d , &n, &h, &m, &k); m /= 2; for (int i = 1; i <= n; i++) { scanf( %d%d , &H[i], &M[i].first); M[i].second = i; M[i].first %= m; M[i].first++; } sort(M + 1, M + 1 + n); int res = 0, t = 0; for (int i = 1; i <= n; i++) { int num = 0; if (M[i].first < k) { int l = lower_bound(M + 1, M + 1 + n, make_pair(M[i].first, 0)) - M; int r = upper_bound(M + 1, M + 1 + n, make_pair(m - k + M[i].first, inf)) - M - 1; num = r - l + 1; } else { num += upper_bound(M + 1, M + 1 + n, make_pair(M[i].first - k, inf)) - M - 1; num += n - (lower_bound(M + 1, M + 1 + n, make_pair(M[i].first, 0)) - M) + 1; } if (res < num) { res = num; t = M[i].first; } } vector<int> kk; for (int i = 1; i <= n; i++) { int num = 0; if (M[i].first < k) { int l = lower_bound(M + 1, M + 1 + n, make_pair(M[i].first, 0)) - M; int r = upper_bound(M + 1, M + 1 + n, make_pair(m - k + M[i].first, inf)) - M - 1; num = r - l + 1; if (num == res) { for (int i = 1; i < l; i++) kk.push_back(M[i].second); for (int i = r + 1; i <= n; i++) kk.push_back(M[i].second); break; } } else { int l = upper_bound(M + 1, M + 1 + n, make_pair(M[i].first - k, inf)) - M - 1; num += l; int r = lower_bound(M + 1, M + 1 + n, make_pair(M[i].first, 0)) - M; num += n - r + 1; if (num == res) { for (int i = l + 1; i < r; i++) kk.push_back(M[i].second); break; } } } cout << (n - res) << << t - 1 << endl; sort(kk.begin(), kk.end()); for (int i = 0; i < kk.size(); i++) { printf( %d , kk[i]); } puts( ); return 0; } |
/*!
* <b>Module:</b>gtx_comma_align
* @file gtx_comma_align.v
* @date 2015-07-11
* @author Alexey
*
* @brief comma aligner implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* gtx_comma_align.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtx_comma_align.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
module gtx_comma_align(
input wire rst,
input wire clk,
// input data comes this way (standart 8/10 bit notation)
// cycle 0: {[hgfedcba]=1st byte,[hgfedcba]=0st byte}
// cycle 1: {[hgfedcba]=3rd byte,[hgfedcba]=2dn byte}
// => {[cycle1 data], [cycle0 data]} = as if we were reading by dwords
input wire [19:0] indata,
output wire [19:0] outdata,
// outdata contains comma
output wire comma,
// pulse, indicating that stream was once again adjusted to a comma
// if asserted after link was down - OK
// if asserted during a work - most likely indicates an error in a stream
output wire realign
// asserted when input stream looks like comma, but it is not
// later on after 10/8 it would get something link NOTINTHETABLE error anyways
// output wire error
);
// only comma character = K28.5, has 5 '1's or 5 '0's in a row.
// after we met it, call it a comma group, we could compare other symbols
/*
// create a window
reg [19:0] indata_r;
wire [23:0] window;
always @ (posedge clk)
indata_r <= indata;
assign window = {indata_r[17:0], indata[19:14]};
// search for a comma group - parallel 24-bit window into 20 5-bit words
// transposed -> 5 x 20-bit words
wire [19:0] lane0;
wire [19:0] lane1;
wire [19:0] lane2;
wire [19:0] lane3;
wire [19:0] lane4;
assign lane0 = window[19:0];
assign lane1 = window[20:1];
assign lane2 = window[21:2];
assign lane3 = window[22:3];
assign lane4 = window[23:4];
// calcute at what position in a window comma group is detected,
// so the position in actual {indata_r, indata} would be +2 from the left side
wire [19:0] comma_pos;
assign comma_pos = lane0 & lane1 & lane2 & lane3 & lane4;
*/
// seach for a comma
// TODO make it less expensive
reg [19:0] indata_r;
wire [38:0] window;
always @ (posedge clk)
indata_r <= indata;
assign window = {indata[18:0], indata_r};
// there is only 1 matched subwindow due to 20-bit comma's non-repetative pattern
wire [19:0] subwindow [19:0];
wire [19:0] comma_match;
wire [19:0] comma_match_p;
reg [19:0] aligned_data;
reg [19:0] comma_match_prev;
wire comma_detected;
wire [19:0] comma_p = 20'b10101010100101111100;
wire [19:0] comma_n = 20'b10101010101010000011;
genvar ii;
generate
for (ii = 0; ii < 20; ii = ii + 1)
begin: look_for_comma
assign subwindow[ii] = window[ii + 19:ii];
// assign comma_match[ii] = subwindow[ii] == 20'b01010101010011111010 | subwindow[ii] == 20'b01010101011100000101;
// stream comes inverted
assign comma_match_p[ii] = subwindow[ii] == comma_p;
assign comma_match[ii] = comma_match_p[ii] | subwindow[ii] == comma_n;
end
endgenerate
assign comma_detected = |comma_match;
// save the shift count
always @ (posedge clk)
comma_match_prev <= rst ? 20'h1 : comma_detected ? comma_match : comma_match_prev;
// shift
/* TODO
wire [38:0] shifted_window;
assign shifted_window = comma_detected ? {window >> (comma_match - 1)} : {window >> (comma_match_prev - 1)};
*/
// temp shift
wire [19:0] shifted_window;
wire [19:0] ored_subwindow [19:0];
wire [19:0] ored_subwindow_comdet [19:0];
assign ored_subwindow_comdet[0] = {20{comma_match_p[0]}} & comma_p | {20{~comma_match_p[0] & comma_match[0]}} & comma_n;
assign ored_subwindow[0] = {20{comma_match_prev[0]}} & subwindow[0];
generate
for (ii = 1; ii < 20; ii = ii + 1)
begin: or_all_possible_windows
assign ored_subwindow_comdet[ii] = {20{comma_match_p[ii]}} & comma_p | {20{~comma_match_p[ii] & comma_match[ii]}} & comma_n | ored_subwindow_comdet[ii-1]; // SuppressThisWarning VEditor -warning would be fixed in future releases
assign ored_subwindow[ii] = {20{comma_match_prev[ii]}} & subwindow[ii] | ored_subwindow[ii-1]; // SuppressThisWarning VEditor -warning would be fixed in future releases
end
endgenerate
assign shifted_window = comma_detected ? ored_subwindow_comdet[19] : ored_subwindow[19];
always @ (posedge clk)
// aligned_data <= comma_detected ? {window >> (comma_match - 1)}[19:0] : {window >> (comma_match_prev - 1)}[19:0];
aligned_data <= shifted_window[19:0];
// form outputs
assign comma = comma_detected;
assign realign = comma_detected & |(comma_match_prev ^ comma_match);
assign outdata = aligned_data;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int tt; cin >> tt; while (tt--) { int n; cin >> n; cout << (1ll * ((n - 1) / 2) * (((n - 1) / 2) + 1) * (2 * ((n - 1) / 2) + 1) * 8) / 6 << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SEDFXBP_FUNCTIONAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hdll__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_FUNCTIONAL_V |
// ----------------------------------------------------------------------------
// -- capeta_test.v: CSoC scan chain control and cadence ATPG
// -- All the received characters are echoed
// ----------------------------------------------------------------------------
// -- (C) BQ. Fev 2017. Written by Leandro Heck ()
// -- GPL license
// ----------------------------------------------------------------------------
`default_nettype none
module part_tester #(
parameter SHOW_INIT_MSG = 1,
parameter BAUDRATE = `B9600,
parameter NPIS = 14,
parameter NPOS = 11
)(
input wire clk, // -- System clock
input wire rst, // -- Reset active high (@BTN0)
// UART
input wire rx, // -- Serial input
output wire tx, // -- Serial output
// DEBUG
output wire [7:0] leds, // -- Board leds
output wire [7:0] sseg, // -- Board 7Segment Display
output wire [3:0] an, // -- 7Segment Display enable
// PART UNDER TEST
output wire [1:14] part_pis_o, // primary input
input wire [1:11] part_pos_i // primary outputs
);
reg [1:0] master_rst_n; // -- Master, active low, asynchonous reset, synchronous release
wire rx_rcv; // -- Received character signal
wire [7:0] rx_data; // -- Received data
wire [7:0] tx_data; // -- Received data
wire tx_start; // --
wire tx_ready; // -- Transmitter ready signal
// Async reset synchronization
always @(posedge clk or posedge rst) begin
if (rst) begin
master_rst_n <= 0;
end
else begin
master_rst_n[1] <= 1;
master_rst_n[0] <= master_rst_n[1];
end
end
uart_tx #(.BAUDRATE(BAUDRATE)) tx0 (
.clk(clk),
.rstn(master_rst_n[0]),
.start(tx_start),
.data(tx_data),
.ready(tx_ready),
.tx(tx)
);
uart_rx #(.BAUDRATE(BAUDRATE)) rx0 (
.clk(clk),
.rstn(master_rst_n[0]),
.rx(rx),
.rcv(rx_rcv),
.data(rx_data)
);
cmd_parser #(
.SHOW_INIT_MSG(SHOW_INIT_MSG),
.NPIS(NPIS),
.NPOS(NPOS)
)
cp0 (
.clk(clk),
.rstn(master_rst_n[0]),
//
.tx_start_o(tx_start),
.tx_data_o(tx_data),
.tx_ready_i(tx_ready),
//
.rx_data(rx_data),
.new_rx_data(rx_rcv),
//
.leds(leds),
.sseg(sseg),
.an(an),
//
.part_pis_o(part_pis_o),
.part_pos_i(part_pos_i)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND2B_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2b (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V |
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