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// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module dut_qa_contents;
reg clk;
reg rst_n;
reg [`WIDTH-1:0] in_data;
reg in_nd;
reg [`MWIDTH-1:0] in_m;
reg [`MSG_WIDTH-1:0] in_msg;
reg in_msg_nd;
wire [`WIDTH-1:0] out_data;
wire out_nd;
wire [`MWIDTH-1:0] out_m;
wire [`MSG_WIDTH-1:0] out_msg;
wire out_msg_nd;
wire error;
initial begin
$from_myhdl(clk, rst_n, in_data, in_nd, in_m, in_msg, in_msg_nd);
$to_myhdl(out_data, out_nd, out_m, out_msg, out_msg_nd, error);
end
qa_contents #(`WIDTH, `MWIDTH) qa_contents_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.in_m(in_m),
.in_msg(in_msg),
.in_msg_nd(in_msg_nd),
.out_data(out_data),
.out_nd(out_nd),
.out_m(out_m),
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
.error(error)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2015 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad};
bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d};
bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06};
bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199};
bit [9*32-1:0] w9 = {32'hca800ac1,
32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621};
bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32,
32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8};
bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e,
32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784};
bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e,
32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302};
bit [17*32-1:0] w17 = {32'hf1e322ac,
32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23,
32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1};
function [7:0] bytehash (input [32*32-1:0] data);
integer i;
bytehash = 0;
for (i=0; i<32*32; ++i) begin
bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8];
end
return bytehash;
endfunction
// Aggregate outputs into a single result vector
// verilator lint_off WIDTH
wire [63:0] result = (bytehash(w4)
^ bytehash(w8m)
^ bytehash(w8)
^ bytehash(w8p)
^ bytehash(w9)
^ bytehash(w16m)
^ bytehash(w16)
^ bytehash(w16p)
^ bytehash(w17));
// verilator lint_on WIDTH
`define EXPECTED_SUM 64'h2bc7c2a98a302891
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
// verilator lint_off SELRANGE
`checkhw(w4,3,32'h7c709753);
`checkhw(w4,2,32'hbc8f6059);
`checkhw(w4,1,32'h3b0db464);
`checkhw(w4,0,32'h721a8fad);
`checkhw(w8m,7,31'h7146e1bf);
`checkhw(w8m,6,32'ha8549e42);
`checkhw(w8m,5,32'hca6960bd);
`checkhw(w8m,4,32'h191b7f9b);
`checkhw(w8m,3,32'h93d79866);
`checkhw(w8m,2,32'hf4489e2b);
`checkhw(w8m,1,32'h8e9a3236);
`checkhw(w8m,0,32'h1d2a2d1d);
`checkhw(w8,7,32'hc211addc);
`checkhw(w8,6,32'he5d4a057);
`checkhw(w8,5,32'h5cbf88fe);
`checkhw(w8,4,32'h42cf42e2);
`checkhw(w8,3,32'heb584263);
`checkhw(w8,2,32'ha585f118);
`checkhw(w8,1,32'h231531c8);
`checkhw(w8,0,32'hc73f7b06);
`checkhw(w8p,8,1'b1);
`checkhw(w8p,7,32'h096aa54b);
`checkhw(w8p,6,32'h48aae18e);
`checkhw(w8p,5,32'hf9502cea);
`checkhw(w8p,4,32'h518c8b61);
`checkhw(w8p,3,32'h9e8641a2);
`checkhw(w8p,2,32'h0dc0249c);
`checkhw(w8p,1,32'hd421a87a);
`checkhw(w8p,0,32'hb8ee9199);
`checkhw(w9,8,32'hca800ac1);
`checkhw(w9,7,32'h0de4823a);
`checkhw(w9,6,32'ha51663ac);
`checkhw(w9,5,32'h96351446);
`checkhw(w9,4,32'h6b0bbcd5);
`checkhw(w9,3,32'h4a64b530);
`checkhw(w9,2,32'h4967d59a);
`checkhw(w9,1,32'hfcc17292);
`checkhw(w9,0,32'h57926621);
`checkhw(w16m,15,31'h77ad72c7);
`checkhw(w16m,14,32'h73aa9cbb);
`checkhw(w16m,13,32'h7ecf026d);
`checkhw(w16m,12,32'h985a3ed2);
`checkhw(w16m,11,32'hfe961c1d);
`checkhw(w16m,10,32'h7a01df72);
`checkhw(w16m,9,32'h79e13d71);
`checkhw(w16m,8,32'hb69e2e32);
`checkhw(w16m,7,32'h09fcbc45);
`checkhw(w16m,6,32'hcfd738c1);
`checkhw(w16m,5,32'hc197ac7c);
`checkhw(w16m,4,32'hc316d727);
`checkhw(w16m,3,32'h903034e4);
`checkhw(w16m,2,32'h92a047d1);
`checkhw(w16m,1,32'h6a5357af);
`checkhw(w16m,0,32'ha82ce9c8);
// verilator lint_on SELRANGE
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w4 = w4 >>> 1;
w8m = w8m >>> 1;
w8 = w8 >>> 1;
w8p = w8p >>> 1;
w9 = w9 >>> 1;
w16m = w16m >>> 1;
w16 = w16 >>> 1;
w16p = w16p >>> 1;
w17 = w17 >>> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int NN = 1 << 20; int qpow(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = (long long)ret * a % mod; a = (long long)a * a % mod; b >>= 1; } return ret; } namespace NTT { const int g = 3; int x[NN << 2], y[NN << 2], wn[NN << 2]; void init() { for (int i = 0; i <= 20; i++) wn[i] = qpow(g, (mod - 1) / (1 << i)); } void brc(int *F, int len) { int j = len / 2; for (int i = 1; i <= len - 2; i++) { if (i < j) swap(F[i], F[j]); int k = len / 2; while (j >= k) j -= k, k >>= 1; if (j < k) j += k; } } void NTT(int *F, int len, int t) { int id = 0; brc(F, len); for (int h = 2; h <= len; h <<= 1) { id++; for (int j = 0; j < len; j += h) { int E = 1; for (int k = j; k < j + h / 2; k++) { int u = F[k], v = (long long)E * F[k + h / 2] % mod; F[k] = (u + v) % mod, F[k + h / 2] = ((u - v) % mod + mod) % mod; E = (long long)E * wn[id] % mod; } } } if (t == -1) { for (int i = 1; i <= len / 2 - 1; i++) swap(F[i], F[len - i]); long long inv = qpow(len, mod - 2); for (int i = 0; i <= len - 1; i++) F[i] = (long long)F[i] % mod * inv % mod; } } } // namespace NTT int a[NN], n, k; int main() { NTT::init(); scanf( %d%d , &n, &k); for (int i = 1; i <= k; i++) { int x; scanf( %d , &x); a[x] = 1; } NTT::NTT(a, 1 << 20, 1); for (int i = 0; i < (1 << 20); i++) a[i] = qpow(a[i], n / 2); NTT::NTT(a, 1 << 20, -1); int ans = 0; for (int i = 0; i <= 9 * n / 2; i++) ans = (ans + 1ll * a[i] * a[i]) % mod; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct time { int s; int e; }; int main() { int n; cin >> n; int s, e; int minc = INT_MAX, maxc = -1; for (int i = 0; i < n; i++) { cin >> s >> e; if (minc > e) { minc = e; } if (maxc < s) { maxc = s; } } int m; cin >> m; int maxp = -1, minp = INT_MAX; for (int i = 0; i < m; i++) { cin >> s >> e; if (minp > e) { minp = e; } if (maxp < s) { maxp = s; } } int p = maxp - minc; int q = maxc - minp; if (p < 0 && q < 0) { cout << 0; } else { cout << max(p, q); } } |
#include <bits/stdc++.h> const int inf = 1000000007; const double pi = 2 * acos(0.0); using namespace std; int gcd(int a, int b) { a = abs(a); b = abs(b); while (b) { a = a % b; swap(a, b); } return a; } int main() { map<long long, int> m; long long n, k; scanf( %lld%lld , &n, &k); long long arr[n]; for (long long i = 0; i < n; i++) { scanf( %lld , &arr[i]); m.insert(make_pair(arr[i], 1)); } vector<long long> ans; long long sum = 0; for (int i = 1; i < 1e9; i++) { if (sum > k) { ans.pop_back(); break; } if (m[i] != 1) { sum += i; ans.push_back(i); } } printf( %d n , ans.size()); for (long long i : ans) { printf( %d , i); } } |
#include <bits/stdc++.h> using namespace std; void precalc(){}; const int N = 3010; int n, m; vector<vector<int>> g; vector<vector<int>> dist; pair<int, int> pre[N][3], post[N][3]; void bfs(int x) { queue<int> q; q.push(x); while (q.size()) { int head = q.front(); q.pop(); for (auto c : g[head]) { if (dist[x][c] > n) { dist[x][c] = dist[x][head] + 1; q.push(c); } } } } inline bool distinct(int a, int b, int c, int d) { vector<int> z = {a, b, c, d}; sort(z.begin(), z.end()); return z[0] != z[1] && z[1] != z[2] && z[2] != z[3]; } void solve(int ncase) { cin >> n >> m; g.assign(n + 1, vector<int>()); dist.assign(n + 1, vector<int>(n + 1, n + 1)); for (int i = 1; i <= n; i++) { dist[i][i] = 0; } for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; g[x].push_back(y); } for (int i = 1; i <= n; i++) { bfs(i); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (dist[j][i] <= n) { pair<int, int> tmppre = pair<int, int>(dist[j][i], j); if (tmppre > pre[i][2]) { pre[i][2] = tmppre; if (pre[i][2] > pre[i][1]) { swap(pre[i][2], pre[i][1]); if (pre[i][1] > pre[i][0]) { swap(pre[i][1], pre[i][0]); } } } } if (dist[i][j] <= n) { pair<int, int> tmppost = pair<int, int>(dist[i][j], j); if (tmppost > post[i][2]) { post[i][2] = tmppost; if (post[i][2] > post[i][1]) { swap(post[i][2], post[i][1]); if (post[i][1] > post[i][0]) { swap(post[i][1], post[i][0]); } } } } } } int ans = -1; vector<int> ret(4); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j || dist[i][j] > n) continue; for (int a = 0; a < 3; a++) { if (pre[i][a].second == 0) continue; for (int b = 0; b < 3; b++) { if (post[j][b].second == 0) continue; int tmp = pre[i][a].first + dist[i][j] + post[j][b].first; if (tmp > ans && distinct(pre[i][a].second, i, j, post[j][b].second)) { ans = tmp; ret = {pre[i][a].second, i, j, post[j][b].second}; } } } } } cout << ret[0] << << ret[1] << << ret[2] << << ret[3] << endl; } int main() { int T = 1; int ncase = 0; while (T--) { solve(++ncase); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 5e4 + 5; const int SQRN = 210; const int BSZ = 256; vector<int> g[MAXN]; int v[MAXN], lvl[MAXN], pai[MAXN]; int jump[MAXN], best[MAXN][SQRN]; int trie[BSZ * 20 + 5][2]; int n, q, cnt_trie = 1; void predfs(int cur, int p) { for (auto viz : g[cur]) { if (viz == p) continue; lvl[viz] = lvl[cur] + 1; pai[viz] = cur; predfs(viz, cur); } } void build(int cur, int k, int root) { if (k >= BSZ) return; jump[root] = cur; int val = v[cur] ^ k; int tcur = 1; for (int i = 16; i >= 0; i--) { bool viz = val & (1 << i); if (!trie[tcur][viz]) trie[tcur][viz] = ++cnt_trie; tcur = trie[tcur][viz]; } if (pai[cur] == cur) return; build(pai[cur], k + 1, root); } int find_best(int mask) { int cur = 1; int resp = 0; for (int i = 16; i >= 0; i--) { bool want = 1 ^ ((bool)(mask & (1 << i))); if (trie[cur][want]) cur = trie[cur][want], resp += (1 << i); else cur = trie[cur][!want]; } return resp; } int main() { scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); for (int i = 1; i <= n - 1; i++) { int a, b; scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } pai[1] = 1; predfs(1, 1); for (int i = 1; i <= n; i++) { build(i, 0, i); for (int k = 0; k * BSZ <= n; k++) best[i][k] = find_best(k * BSZ); memset(trie, 0, sizeof(trie)); cnt_trie = 1; } while (q--) { int a, b; scanf( %d %d , &a, &b); int w = 0; int respf = 0; while (lvl[jump[b]] > lvl[a]) { respf = max(respf, best[b][w]); b = pai[jump[b]]; w++; } int dist = w * BSZ; while (b != a) { respf = max(respf, v[b] ^ dist); b = pai[b]; dist++; } respf = max(respf, v[a] ^ dist); printf( %d n , respf); } } |
`default_nettype none
`timescale 1ns/1ns
module tb_membusif();
wire clk, reset;
clock clock(clk, reset);
// avalon
reg a_write = 0;
reg a_read = 0;
reg [31:0] a_writedata = 0;
reg [1:0] a_address;
wire [31:0] a_readdata;
wire a_waitrequest;
// membus
wire b_rq_cyc;
wire b_rd_rq;
wire b_wr_rq;
wire [21:35] b_ma;
wire [18:21] b_sel;
wire b_fmc_select;
wire [0:35] b_mb_write;
wire b_wr_rs;
wire [0:35] b_mb_read = b_mb_read_0 | b_mb_read_1;
wire b_addr_ack = b_addr_ack_0 | b_addr_ack_1;
wire b_rd_rs = b_rd_rs_0 | b_rd_rs_1;
membusif membusif0(
.clk(clk),
.reset(reset),
.s_address(a_address),
.s_write(a_write),
.s_read(a_read),
.s_writedata(a_writedata),
.s_readdata(a_readdata),
.s_waitrequest(a_waitrequest),
.m_rq_cyc(b_rq_cyc),
.m_rd_rq(b_rd_rq),
.m_wr_rq(b_wr_rq),
.m_ma(b_ma),
.m_sel(b_sel),
.m_fmc_select(b_fmc_select),
.m_mb_write(b_mb_write),
.m_wr_rs(b_wr_rs),
.m_mb_read(b_mb_read),
.m_addr_ack(b_addr_ack),
.m_rd_rs(b_rd_rs));
// Memory
wire [17:0] cm_address;
wire cm_write;
wire cm_read;
wire [35:0] cm_writedata;
wire [35:0] cm_readdata;
wire cm_waitrequest;
wire [0:35] b_mb_read_0;
wire b_addr_ack_0;
wire b_rd_rs_0;
// core161c_x cmem(
// core164 cmem(
core32k cmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(b_rq_cyc),
.membus_rd_rq_p0(b_rd_rq),
.membus_wr_rq_p0(b_wr_rq),
.membus_ma_p0(b_ma),
.membus_sel_p0(b_sel),
.membus_fmc_select_p0(b_fmc_select),
.membus_mb_in_p0(b_mb_write),
.membus_wr_rs_p0(b_wr_rs),
.membus_mb_out_p0(b_mb_read_0),
.membus_addr_ack_p0(b_addr_ack_0),
.membus_rd_rs_p0(b_rd_rs_0),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0),
.m_address(cm_address),
.m_write(cm_write),
.m_read(cm_read),
.m_writedata(cm_writedata),
.m_readdata(cm_readdata),
.m_waitrequest(cm_waitrequest)
);
// memory_16k cmem_x(
memory_32k cmem_x(
.i_clk(clk),
.i_reset_n(reset),
.i_address(cm_address),
.i_write(cm_write),
.i_read(cm_read),
.i_writedata(cm_writedata),
.o_readdata(cm_readdata),
.o_waitrequest(cm_waitrequest));
reg [17:0] fm_address = 0;
reg fm_write = 0;
reg fm_read = 0;
reg [35:0] fm_writedata = 0;
wire [35:0] fm_readdata;
wire fm_waitrequest;
wire [0:35] b_mb_read_1;
wire b_addr_ack_1;
wire b_rd_rs_1;
fast162_dp fmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(b_rq_cyc),
.membus_rd_rq_p0(b_rd_rq),
.membus_wr_rq_p0(b_wr_rq),
.membus_ma_p0(b_ma),
.membus_sel_p0(b_sel),
.membus_fmc_select_p0(b_fmc_select),
.membus_mb_in_p0(b_mb_write),
.membus_wr_rs_p0(b_wr_rs),
.membus_mb_out_p0(b_mb_read_1),
.membus_addr_ack_p0(b_addr_ack_1),
.membus_rd_rs_p0(b_rd_rs_1),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0),
.s_address(fm_address),
.s_write(fm_write),
.s_read(fm_read),
.s_writedata(fm_writedata),
.s_readdata(fm_readdata),
.s_waitrequest(fm_waitrequest)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
cmem_x.ram.ram[3] = 36'o101010101010;
cmem_x.ram.ram[4] = 123;
cmem_x.ram.ram[5] = 321;
cmem_x.ram.ram['o123] = 36'o112233445566;
cmem_x.ram.ram['o124] = 36'o111111111111;
cmem_x.ram.ram['o40123] = 36'o111111111111;
fmem.ff[3] = 36'o777777666666;
fmem.ff[4] = 36'o555555444444;
fmem.ff[5] = 36'o333333222222;
#5;
#200;
#5000;
/*
@(posedge clk);
fm_address <= 3;
fm_write <= 1;
fm_writedata <= 36'o1000123;
@(negedge fm_write);
@(posedge clk);
fm_address <= 5;
fm_write <= 1;
fm_writedata <= 36'o101202303404;
@(negedge fm_write);
@(posedge clk);
fm_address <= 3;
fm_read <= 1;
@(negedge fm_read);
*/
// write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o0040123;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
#2000;
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o0000555;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o101202;
@(negedge a_write);
/* // write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o0000124;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
*/
/*
// write low word
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o111222;
@(negedge a_write);
// write high word
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o333444;
@(negedge a_write);
*/
end
initial begin
#40000;
$finish;
end
reg [0:35] data;
always @(posedge clk) begin
if(~a_waitrequest & a_write)
a_write <= 0;
if(~a_waitrequest & a_read) begin
a_read <= 0;
data <= a_readdata;
end
if(~fm_waitrequest & fm_write)
fm_write <= 0;
if(~fm_waitrequest & fm_read) begin
fm_read <= 0;
data <= fm_readdata;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_SN_SYMBOL_V
/**
* udp_dff$PS_pp$sN: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_SN_SYMBOL_V
|
#include <bits/stdc++.h> const int MAX_N = (int)1e5 + 123; const double eps = 1e-6; const int inf = (int)1e9 + 123; using namespace std; int n, k; int mini = inf; string second; int sum[MAX_N]; int main() { cin >> n >> k >> second; for (int i = 0; i < int((second).size()); i++) sum[i] = (i > 0 ? sum[i - 1] : 0) + (second[i] == 0 ); vector<int> q; for (int i = 0; i < int((second).size()); i++) if (second[i] == 0 ) q.push_back(i); for (int i = 0; i < int((second).size()); i++) { if (sum[int((second).size()) - 1] - (i > 0 ? sum[i - 1] : 0) < k + 1) break; int l = i, r = int((second).size()) - 1, mid = -1, ans = -1; while (l <= r) { mid = (l + r) / 2; if (sum[mid] - (i > 0 ? sum[i - 1] : 0) >= k + 1) { ans = mid; r = mid - 1; } else l = mid + 1; } assert(ans != -1); int now = ans - i; if ((ans - i + 1) % 2 == 1) { int mid = (ans + i) / 2; auto it = lower_bound(q.begin(), q.end(), mid); if (it != q.end()) now = min(now, max(*it - i, ans - *it)); if (it != q.begin()) { it--; now = min(now, max(*it - i, ans - *it)); } } else { int mid = (ans + i) / 2 + 1; auto it = lower_bound(q.begin(), q.end(), mid); if (it != q.end()) now = min(now, max(*it - i, ans - *it)); mid--; it = lower_bound(q.begin(), q.end(), mid); if (it != q.end()) now = min(now, max(*it - i, ans - *it)); if (it != q.begin()) { it--; now = min(now, max(*it - i, ans - *it)); } } mini = min(mini, now); } cout << mini; return 0; } |
// When triggered, turn the output to maximum and start fading to black
// by teknohog
module pwm_fade (clk, trigger, drive);
input trigger;
input clk;
output drive;
`define FADE_BITS 27
parameter LEVEL_BITS = 8;
// Average block interval in clock cycles is
// 2**32 / (clk * 0.5**ll2 * miners) * clk
// where (clk * 0.5**ll2 * miners) is the hashrate
parameter LOCAL_MINERS = 1;
//parameter LOOP_LOG2 = 5;
//localparam FADE_BITS = 32 + LOOP_LOG2 - $clog2(LOCAL_MINERS);
// Xilinx ISE 13.2 cannot handle $clog2 in localparam, but it works
// in the index
//`define FADE_BITS (32 + LOOP_LOG2 - $clog2(LOCAL_MINERS))
reg [LEVEL_BITS-1:0] pwm_counter = 0;
always @(posedge clk) pwm_counter = pwm_counter + 1;
reg [`FADE_BITS-1:0] fade_counter = 0;
always @(posedge clk)
if (trigger) fade_counter = 0 - 1;
else if (|fade_counter) fade_counter = fade_counter - 1;
// For some reason, {FADE_BITS{1}} sets the register to zero, but
// 0-1 works. Also, it needs to be explicitly initialized to
// zero. Could be just a Nexys2 quirk, as these LEDs are routed to
// general I/O pins too.
wire [LEVEL_BITS-1:0] level;
assign level = fade_counter[`FADE_BITS-1:`FADE_BITS-LEVEL_BITS];
// With <= we cannot have true zero; with < we cannot have full
// brightness. This is a rather fundamental problem, since we need
// 256 timeslices to fill the whole, but the choice of "off" would
// require an extra bit... of course, it is possible to get by
// using a little extra logic.
assign drive = (pwm_counter < level);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_7_1 (
Din,
Dout
);
input wire [47 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(48),
.DIN_FROM(38),
.DIN_TO(23)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency read mode. In this case
// we are generating the unmodulated low frequency carrier.
// The A/D samples at that same rate and the result is serialized.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_read(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
lo_is_125khz, divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input lo_is_125khz; // redundant signal, no longer used anywhere
input [7:0] divisor;
reg [7:0] to_arm_shiftreg;
reg [7:0] pck_divider;
reg ant_lo;
// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
// which is high for (divisor+1) pck0 cycles and low for the same duration
// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
ant_lo = !ant_lo;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
// this task also runs at pck0 frequency (24Mhz) and is used to serialize
// the ADC output which is then clocked into the ARM SSP.
// because ant_lo always transitions when pck_divider = 0 we use the
// pck_divider counter to sync our other signals off it
// we read the ADC value when pck_divider=7 and shift it out on counts 8..15
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !ant_lo)
to_arm_shiftreg <= adc_d;
else
begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
// simulation showed a glitch occuring due to the LSB of the shifter
// not being set as we shift bits out
// this ensures the ssp_din remains low after a transfer and suppresses
// the glitch that would occur when the last data shifted out ended in
// a 1 bit and the next data shifted out started with a 0 bit
to_arm_shiftreg[0] <= 1'b0;
end
end
// ADC samples on falling edge of adc_clk, data available on the rising edge
// example of ssp transfer of binary value
// start of transfer is indicated by the rise of the ssp_frame signal
// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
// the ARM by the falling edge of ssp_clk
// _______________________________
// ssp_frame__| |__
// _______ ___ ___
// ssp_din __| |_______| |___| |______
// _ _ _ _ _ _ _ _ _ _
// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
// serialized SSP data is gated by ant_lo to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !ant_lo;
// SSP clock always runs at 24Mhz
assign ssp_clk = pck0;
// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;
// unused signals tied low
assign pwr_hi = 1'b0;
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
// this is the antenna driver signal
assign pwr_lo = ant_lo;
// ADC clock out of phase with antenna driver
assign adc_clk = ~ant_lo;
// ADC clock also routed to debug pin
assign dbg = adc_clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_2_V
`define SKY130_FD_SC_LP__INVLP_2_V
/**
* invlp: Low Power Inverter.
*
* Verilog wrapper for invlp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_2_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e5L + 11, M = N * 2; int a[M], b[M], c[M]; int back[M]; struct SegTree { ll flag[N * 8]; ll val[N * 4]; void push(int x) { val[x] += flag[x]; flag[2 * x] += flag[x]; flag[2 * x + 1] += flag[x]; flag[x] = 0; } void change(int l, int r, int ql, int qr, int c, int x = 1) { push(x); if (ql == l && qr == r) { flag[x] = c; push(x); } else { if (qr <= (l + r) / 2) { change(l, (l + r) / 2, ql, qr, c, 2 * x); push(2 * x + 1); } else if (ql >= (l + r) / 2) { push(2 * x); change((l + r) / 2, r, ql, qr, c, 2 * x + 1); } else { change(l, (l + r) / 2, ql, (l + r) / 2, c, 2 * x); change((l + r) / 2, r, (l + r) / 2, qr, c, 2 * x + 1); } val[x] = min(val[2 * x], val[2 * x + 1]); } } ll query(int l, int r, int ql, int qr, int x = 1) { push(x); if (ql == l && qr == r) return val[x]; if (qr <= (l + r) / 2) return query(l, (l + r) / 2, ql, qr, 2 * x); else if (ql >= (l + r) / 2) return query((l + r) / 2, r, ql, qr, 2 * x + 1); else return min(query(l, (l + r) / 2, ql, (l + r) / 2, 2 * x), query((l + r) / 2, r, (l + r) / 2, qr, 2 * x + 1)); } } st; vector<int> e[N]; int cnt = 0; int in[N], out[N], id[N]; void dfs(int x) { id[x] = ++cnt; in[x] = cnt; for (int i : e[x]) dfs(i); out[x] = cnt; } int n; ll query(int x) { return st.query(1, n + 1, id[x], id[x] + 1) - back[x]; } int main() { int q; cin >> n >> q; for (int i = 1; i <= 2 * n - 2; i++) { scanf( %d%d%d , a + i, b + i, c + i); if (i <= n - 1) e[a[i]].push_back(b[i]); else back[a[i]] = c[i]; } dfs(1); for (int i = 1; i <= n - 1; i++) st.change(1, n + 1, in[b[i]], out[b[i]] + 1, c[i]); for (int i = 2; i <= n; i++) st.change(1, n + 1, id[i], id[i] + 1, back[i]); while (q--) { int t, u, v; scanf( %d%d%d , &t, &u, &v); if (t == 1) { int i = u, w = v; if (i <= n - 1) { st.change(1, n + 1, in[b[i]], out[b[i]] + 1, w - c[i]); c[i] = w; } else { st.change(1, n + 1, id[a[i]], id[a[i]] + 1, w - c[i]); back[a[i]] = w; c[i] = w; } } else { ll ans = st.query(1, n + 1, in[u], out[u] + 1) - query(u) + query(v); if (id[v] >= in[u] && id[v] <= out[u]) ans = min(ans, query(v) - query(u)); printf( %lld n , ans); } } } |
`include "project_defines.v"
module rgb_generator #(
parameter X_FRONT_PORCH = 32,
parameter X_BACK_PORCH = 32
)(
input clk, // 100MHz system clock signal
input rst, // reset signal
//Generated Signals to Drive Display
output [9:0] o_image_width,
output [9:0] o_image_height,
output o_vsync,
output o_hsync,
output [2:0] o_r_out, // vga red signal
output [2:0] o_g_out, // vga green signal
output [1:0] o_b_out, // vga blue signal
//From the below control signal, the PPU returns this value
input [5:0] i_sys_palette_idx_in, // system palette index (selects output color)
//X, Y, Y Next, pixel clock and a vblank
output [9:0] o_nes_x_out, // nes x coordinate
output [9:0] o_nes_y_out, // nes y coordinate
output [9:0] o_nes_y_next_out, // next line's nes y coordinate
output reg o_pix_pulse_out, // 1 clk pulse prior to o_nes_x update
output o_vblank // indicates a vblank is occuring (no PPU vram access)
);
//local parameters
// NES screen dimensions (256x240).
localparam FRAME_WIDTH = 400;
localparam FRAME_HEIGHT = 260;
//localparam FRAME_HEIGHT = 3;
localparam VBLANK_START_X = 365;
localparam VBLANK_START_Y = 238;
localparam VBLANK_END_X = 32;
localparam VBLANK_END_Y = 259;
//localparam X_FRONT_PORCH = 32;
//localparam X_FRONT_PORCH = 32;
localparam IMAGE_Y_FP = 0; //XXX: This doesn't work when IMAGE_Y_FP > 0
localparam IMAGE_Y_BP = 0;
localparam IMAGE_WIDTH = 256;
localparam IMAGE_HEIGHT = 240;
//localparam IMAGE_HEIGHT = 2;
localparam FPS = 60;
localparam CLK_DIV = `CLOCK_RATE / (FPS * 400 * 260);
//localparam VBLANK_TIMEOUT = `CLOCK_RATE / FPS;
reg [8:0] r_x_pos;
reg [8:0] r_y_pos;
reg [7:0] r_rgb;
wire [8:0] w_x_pos;
wire [8:0] w_y_pos;
wire [31:0] w_clk_div = CLK_DIV;
reg [7:0] r_clk_div_count;
//Submodules
//Asynchronous Logic
assign o_r_out = r_rgb[7:5];
assign o_g_out = r_rgb[4:2];
assign o_b_out = r_rgb[1:0];
//synchronous logic
always @ (posedge clk) begin
if (rst) begin
r_clk_div_count <= 4;
o_pix_pulse_out <= 0;
end
else begin
//Stobe
o_pix_pulse_out <= 0;
if (r_clk_div_count < w_clk_div - 1) begin
r_clk_div_count <= r_clk_div_count + 1;
end
else begin
r_clk_div_count <= 0;
o_pix_pulse_out <= 1;
end
end
end
always @ (*) begin
if (o_hsync == 0) begin
r_rgb = 0;
end
else begin
// Lookup RGB values based on sys_palette_idx. Table is an approximation of the NES
// system palette. Taken from http://nesdev.parodius.com/NESTechFAQ.htm#nessnescompat.
case (i_sys_palette_idx_in)
6'h00: r_rgb = { 3'h3, 3'h3, 2'h1 };
6'h01: r_rgb = { 3'h1, 3'h0, 2'h2 };
6'h02: r_rgb = { 3'h0, 3'h0, 2'h2 };
6'h03: r_rgb = { 3'h2, 3'h0, 2'h2 };
6'h04: r_rgb = { 3'h4, 3'h0, 2'h1 };
6'h05: r_rgb = { 3'h5, 3'h0, 2'h0 };
6'h06: r_rgb = { 3'h5, 3'h0, 2'h0 };
6'h07: r_rgb = { 3'h3, 3'h0, 2'h0 };
6'h08: r_rgb = { 3'h2, 3'h1, 2'h0 };
6'h09: r_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0a: r_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0b: r_rgb = { 3'h0, 3'h1, 2'h0 };
6'h0c: r_rgb = { 3'h0, 3'h1, 2'h1 };
6'h0d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h10: r_rgb = { 3'h5, 3'h5, 2'h2 };
6'h11: r_rgb = { 3'h0, 3'h3, 2'h3 };
6'h12: r_rgb = { 3'h1, 3'h1, 2'h3 };
6'h13: r_rgb = { 3'h4, 3'h0, 2'h3 };
6'h14: r_rgb = { 3'h5, 3'h0, 2'h2 };
6'h15: r_rgb = { 3'h7, 3'h0, 2'h1 };
6'h16: r_rgb = { 3'h6, 3'h1, 2'h0 };
6'h17: r_rgb = { 3'h6, 3'h2, 2'h0 };
6'h18: r_rgb = { 3'h4, 3'h3, 2'h0 };
6'h19: r_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1a: r_rgb = { 3'h0, 3'h5, 2'h0 };
6'h1b: r_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1c: r_rgb = { 3'h0, 3'h4, 2'h2 };
6'h1d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h20: r_rgb = { 3'h7, 3'h7, 2'h3 };
6'h21: r_rgb = { 3'h1, 3'h5, 2'h3 };
6'h22: r_rgb = { 3'h2, 3'h4, 2'h3 };
6'h23: r_rgb = { 3'h5, 3'h4, 2'h3 };
6'h24: r_rgb = { 3'h7, 3'h3, 2'h3 };
6'h25: r_rgb = { 3'h7, 3'h3, 2'h2 };
6'h26: r_rgb = { 3'h7, 3'h3, 2'h1 };
6'h27: r_rgb = { 3'h7, 3'h4, 2'h0 };
6'h28: r_rgb = { 3'h7, 3'h5, 2'h0 };
6'h29: r_rgb = { 3'h4, 3'h6, 2'h0 };
6'h2a: r_rgb = { 3'h2, 3'h6, 2'h1 };
6'h2b: r_rgb = { 3'h2, 3'h7, 2'h2 };
6'h2c: r_rgb = { 3'h0, 3'h7, 2'h3 };
6'h2d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h30: r_rgb = { 3'h7, 3'h7, 2'h3 };
6'h31: r_rgb = { 3'h5, 3'h7, 2'h3 };
6'h32: r_rgb = { 3'h6, 3'h6, 2'h3 };
6'h33: r_rgb = { 3'h6, 3'h6, 2'h3 };
6'h34: r_rgb = { 3'h7, 3'h6, 2'h3 };
6'h35: r_rgb = { 3'h7, 3'h6, 2'h3 };
6'h36: r_rgb = { 3'h7, 3'h5, 2'h2 };
6'h37: r_rgb = { 3'h7, 3'h6, 2'h2 };
6'h38: r_rgb = { 3'h7, 3'h7, 2'h2 };
6'h39: r_rgb = { 3'h7, 3'h7, 2'h2 };
6'h3a: r_rgb = { 3'h5, 3'h7, 2'h2 };
6'h3b: r_rgb = { 3'h5, 3'h7, 2'h3 };
6'h3c: r_rgb = { 3'h4, 3'h7, 2'h3 };
6'h3d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3f: r_rgb = { 3'h0, 3'h0, 2'h0 };
endcase
end
end
assign o_vblank = ((r_x_pos == VBLANK_START_X) && (r_y_pos == VBLANK_START_Y)) ? 1 :
((r_x_pos == VBLANK_END_X) && (r_y_pos == VBLANK_END_Y)) ? 0 : o_vblank;
assign w_x_pos = r_x_pos - X_FRONT_PORCH;
assign w_y_pos = r_y_pos - IMAGE_Y_FP;
assign o_nes_x_out = {1'b0, w_x_pos};
assign o_nes_y_out = {1'b0, w_y_pos};
assign o_nes_y_next_out = (r_x_pos == (FRAME_WIDTH / 2)) ? o_nes_y_out + 1 :
!rst ? o_nes_y_next_out :
10'h000;
assign o_hsync = (o_vsync) &&
((o_nes_x_out >= X_FRONT_PORCH) &&
(o_nes_x_out <= X_FRONT_PORCH + IMAGE_WIDTH + X_BACK_PORCH));
assign o_vsync = ((o_nes_y_out == IMAGE_Y_FP) ) ? 1'b1 :
((o_nes_y_out == (IMAGE_Y_FP + IMAGE_HEIGHT + IMAGE_Y_BP))) ? 1'b0:
!rst ? o_vsync :
1'b0;
assign o_image_width = (X_FRONT_PORCH + IMAGE_WIDTH + X_BACK_PORCH);
assign o_image_height = (IMAGE_Y_FP + IMAGE_HEIGHT + IMAGE_Y_BP);
//Positional data
always @ (posedge clk) begin
if (rst) begin
/*
r_x_pos <= VBLANK_START_X;
r_y_pos <= VBLANK_START_Y;
*/
r_x_pos <= 0;
r_y_pos <= 0;
end
else begin
//Increment Position
if (o_pix_pulse_out) begin
if (r_x_pos < (FRAME_WIDTH - 1)) begin
r_x_pos <= r_x_pos + 1;
end
else begin
r_x_pos <= 0;
if (r_y_pos < (FRAME_HEIGHT - 1)) begin
r_y_pos <= r_y_pos + 1;
end
else begin
r_y_pos <= 0;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long int a, b; cin >> a >> b; if (a == 9 and b == 1) { cout << 9 << << 10; } else if (a == b) { cout << a * 10 << << a * 10 + 1; } else if (b - a == 1) { cout << a * 10 + 9 << << b * 10 << endl; } else { cout << -1 << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_4_V
`define SKY130_FD_SC_LS__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_4_V
|
module umult8(reg_A, reg_B, result);
// INPUTS
input [0:7] reg_A, reg_B;
// OUTPUTS
output [0:15] result;
// REGISTERS
reg [0:15] p8a_0;
reg [0:15] p8b_0;
reg [0:15] pt;
reg [0:15] result;
// INTEGERS (contols for loops)
integer i;
always @ (reg_A or reg_B)
begin
// reg_B
// x reg_A
// -------
// result
p8a_0=16'b0;
p8b_0=16'b0;
pt=16'b0;
// extend operand B
p8b_0={{8{1'b0}},reg_B[0:7]};
// extend operand A
p8a_0={{8{1'b0}},reg_A[0:7]};
// compute sum due to partial products
/*
// not using for loop
pt=pt+(p8a_0[15]?(p8b_0):16'b0);
pt=pt+(p8a_0[14]?(p8b_0<<8'd1):16'b0);
pt=pt+(p8a_0[13]?(p8b_0<<8'd2):16'b0);
pt=pt+(p8a_0[12]?(p8b_0<<8'd3):16'b0);
pt=pt+(p8a_0[11]?(p8b_0<<8'd4):16'b0);
pt=pt+(p8a_0[10]?(p8b_0<<8'd5):16'b0);
pt=pt+(p8a_0[9]?(p8b_0<<8'd6):16'b0);
pt=pt+(p8a_0[8]?(p8b_0<<8'd7):16'b0);
*/
// same computation as above, but using for loop
for (i=15; i>7; i=i-1)
begin
pt=pt+(p8a_0[i]?(p8b_0<<(8'd15-i)):16'b0);
end
// store sum as result
result<=pt;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O2111AI_PP_BLACKBOX_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_PP_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd1 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module Selector_Casillas(
clk,
boton_arriba,
boton_abajo,
boton_izq,
boton_der,
boton_elige,
turno_p1,
turno_p2,
guarda_c1,
guarda_c2,
guarda_c3,
guarda_c4,
guarda_c5,
guarda_c6,
guarda_c7,
guarda_c8,
guarda_c9,
p1_mm,
p2_mm,
cuadro
);
input clk;
input boton_elige, boton_arriba, boton_abajo, boton_izq, boton_der;
input turno_p1, turno_p2;
output reg p1_mm, p2_mm;
output reg [3:0] cuadro;
output reg [1:0] guarda_c1, guarda_c2, guarda_c3, guarda_c4, guarda_c5, guarda_c6, guarda_c7, guarda_c8, guarda_c9;
initial cuadro <= 4'b0101;
always @(posedge clk)//posedge boton_arriba, posedge boton_abajo, posedge boton_izq, posedge boton_der, posedge boton_elige)
begin
if ((boton_abajo == 1'b1) & (cuadro >= 4'b0001) & (cuadro <= 4'b0110))
cuadro = cuadro + 4'b0011;
else if ((boton_arriba == 1'b1) & (cuadro >= 4'b0100) & (cuadro <= 4'b1001))
cuadro = cuadro - 4'b0011;
else if ((boton_izq == 1'b1) & (cuadro > 4'b0001) & (cuadro <= 4'b1001) & (cuadro!=4'b0111) & (cuadro!=4'b0100))
cuadro = cuadro - 4'b0001;
else if ((boton_der == 1'b1) & (cuadro >= 4'b0001) & (cuadro < 4'b1001) & (cuadro!=4'b0011) & (cuadro!=4'b0110))
cuadro = cuadro + 4'b0001;
else if ((boton_elige == 1'b1) & (cuadro >= 4'b0001) & (cuadro <= 4'b1001))
begin
if (turno_p1 == 1'b1 & turno_p2 == 1'b0)
begin
//Guarda en los registros
if (cuadro == 4'b0001 & guarda_c1 != 2'b11 & guarda_c1 != 2'b01)
guarda_c1 = 2'b11;
else if (cuadro == 4'b0010 & guarda_c2 != 2'b11 & guarda_c2 != 2'b01)
guarda_c2 = 2'b11;
else if (cuadro == 4'b0011 & guarda_c3 != 2'b11 & guarda_c3 != 2'b01)
guarda_c3 = 2'b11;
else if (cuadro == 4'b0100 & guarda_c4 != 2'b11 & guarda_c4 != 2'b01)
guarda_c4 = 2'b11;
else if (cuadro == 4'b0101 & guarda_c5 != 2'b11 & guarda_c5 != 2'b01)
guarda_c5 = 2'b11;
else if (cuadro == 4'b0110 & guarda_c6 != 2'b11 & guarda_c6 != 2'b01)
guarda_c6 = 2'b11;
else if (cuadro == 4'b0111 & guarda_c7 != 2'b11 & guarda_c7 != 2'b01)
guarda_c7 = 2'b11;
else if (cuadro == 4'b1000 & guarda_c8 != 2'b11 & guarda_c8 != 2'b01)
guarda_c8 = 2'b11;
else if (cuadro == 4'b1001 & guarda_c9 != 2'b11 & guarda_c9 != 2'b01)
guarda_c9 = 2'b11;
//pone al jugador en movimiento
//equis <= cuadro;
p1_mm = 1'b1;
p2_mm = 1'b0;
cuadro = 4'b0101;
end
else if (turno_p1 == 1'b0 & turno_p2 == 1'b1)
begin
//Guarda en los registros
if (cuadro == 4'b0001 & guarda_c1 != 2'b11 & guarda_c1 != 2'b01)
guarda_c1 = 2'b01;
else if (cuadro == 4'b0010 & guarda_c2 != 2'b11 & guarda_c2 != 2'b01)
guarda_c2 = 2'b01;
else if (cuadro == 4'b0011 & guarda_c3 != 2'b11 & guarda_c3 != 2'b01)
guarda_c3 = 2'b01;
else if (cuadro == 4'b0100 & guarda_c4 != 2'b11 & guarda_c4 != 2'b01)
guarda_c4 = 2'b01;
else if (cuadro == 4'b0101 & guarda_c5 != 2'b11 & guarda_c5 != 2'b01)
guarda_c5 = 2'b01;
else if (cuadro == 4'b0110 & guarda_c6 != 2'b11 & guarda_c6 != 2'b01)
guarda_c6 = 2'b01;
else if (cuadro == 4'b0111 & guarda_c7 != 2'b11 & guarda_c7 != 2'b01)
guarda_c7 = 2'b01;
else if (cuadro == 4'b1000 & guarda_c8 != 2'b11 & guarda_c8 != 2'b01)
guarda_c8 = 2'b01;
else if (cuadro == 4'b1001 & guarda_c9 != 2'b11 & guarda_c9 != 2'b01)
guarda_c9 = 2'b01;
//pone al jugador en movimiento
//circulo <= cuadro;
p1_mm = 1'b0;
p2_mm = 1'b1;
cuadro = 4'b0101;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream fin( in.in ); ofstream fout( out.out ); const int N = 1e5 + 10; int n, m, erased[N], cnt[N], rem[N]; vector<int> a[N], v[N]; deque<vector<int> > ind[N]; queue<int> q; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x; cin >> x; a[i].push_back(x); if (x != -1) v[i].push_back(x); else erased[j]++; } sort(v[i].begin(), v[i].end()); v[i].resize(unique(v[i].begin(), v[i].end()) - v[i].begin()); vector<int> vec; for (int j = 0; j < v[i].size(); j++) ind[i].push_back(vec); for (int j = 0; j < m; j++) if (a[i][j] != -1) ind[i][lower_bound(v[i].begin(), v[i].end(), a[i][j]) - v[i].begin()] .push_back(j); } vector<int> res; for (int i = 0; i < m; i++) if (erased[i] == n) res.push_back(i + 1); while (res.size() < m) { for (int i = 0; i < n; i++) { if (rem[i] || ind[i].empty()) continue; rem[i] = ind[i][0].size(); for (int j = 0; j < ind[i][0].size(); j++) { int k = ind[i][0][j]; cnt[k]++; if (cnt[k] == n - erased[k]) q.push(k); } ind[i].pop_front(); } if (q.empty()) break; while (!q.empty()) { int j = q.front(); q.pop(); res.push_back(j + 1); for (int i = 0; i < n; i++) if (a[i][j] != -1) rem[i]--; } } if (res.size() < m) cout << -1; else for (int i = 0; i < res.size(); i++) cout << res[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using vll = vector<ll>; using vvll = vector<vll>; using vb = vector<bool>; using vd = vector<double>; using vs = vector<string>; using pii = pair<int, int>; using pll = pair<ll, ll>; using pdd = pair<double, double>; using vpii = vector<pii>; using vvpii = vector<vpii>; using vpll = vector<pll>; using vvpll = vector<vpll>; using vpdd = vector<pdd>; using vvpdd = vector<vpdd>; template <typename T> void ckmin(T& a, const T& b) { a = min(a, b); } template <typename T> void ckmax(T& a, const T& b) { a = max(a, b); } mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); namespace __input { template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } template <class Arg, class... Args> void re(Arg& first, Args&... rest) { re(first); re(rest...); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& a) { for (int i = 0; i < (int((a).size())); i++) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = 0; i < (SZ); i++) re(a[i]); } } // namespace __input using namespace __input; namespace __output { template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T, size_t SZ> void pr(const array<T, SZ>& x); template <class T> void pr(const vector<T>& x); template <class T> void pr(const set<T>& x); template <class T1, class T2> void pr(const map<T1, T2>& x); template <class T> void pr(const T& x) { cout << x; } template <class Arg, class... Args> void pr(const Arg& first, const Args&... rest) { pr(first); pr(rest...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T, bool pretty = true> void prContain(const T& x) { if (pretty) pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? pretty ? , : : , a), fst = 0; if (pretty) pr( } ); } template <class T> void pc(const T& x) { prContain<T, false>(x); pr( n ); } template <class T, size_t SZ> void pr(const array<T, SZ>& x) { prContain(x); } template <class T> void pr(const vector<T>& x) { prContain(x); } template <class T> void pr(const set<T>& x) { prContain(x); } template <class T1, class T2> void pr(const map<T1, T2>& x) { prContain(x); } void ps() { pr( n ); } template <class Arg> void ps(const Arg& first) { pr(first); ps(); } template <class Arg, class... Args> void ps(const Arg& first, const Args&... rest) { pr(first, ); ps(rest...); } } // namespace __output using namespace __output; namespace __algorithm { template <typename T> void dedup(vector<T>& v) { sort((v).begin(), (v).end()); v.erase(unique((v).begin(), (v).end()), v.end()); } template <typename T> typename vector<T>::iterator find(vector<T>& v, const T& x) { auto it = lower_bound((v).begin(), (v).end(), x); return it != v.end() && *it == x ? it : v.end(); } template <typename T> size_t index(vector<T>& v, const T& x) { auto it = find(v, x); assert(it != v.end() && *it == x); return it - v.begin(); } template <typename C, typename T, typename OP> vector<T> prefixes(const C& v, T id, OP op) { vector<T> r(int((v).size()) + 1, id); for (int i = 0; i < (int((v).size())); i++) r[i + 1] = op(r[i], v[i]); return r; } template <typename C, typename T, typename OP> vector<T> suffixes(const C& v, T id, OP op) { vector<T> r(int((v).size()) + 1, id); for (int i = (int((v).size())) - 1; i >= 0; i--) r[i] = op(v[i], r[i + 1]); return r; } } // namespace __algorithm using namespace __algorithm; struct monostate { friend istream& operator>>(istream& is, const __attribute__((unused)) monostate& ms) { return is; } friend ostream& operator<<(ostream& os, const __attribute__((unused)) monostate& ms) { return os; } } ms; template <typename W = monostate> struct wedge { int u, v, i; W w; wedge<W>(int _u = -1, int _v = -1, int _i = -1) : u(_u), v(_v), i(_i) {} int operator[](int loc) const { return u ^ v ^ loc; } friend void re(wedge& e) { re(e.u, e.v, e.w); --e.u, --e.v; } friend void pr(const wedge& e) { pr(e.u, <- , e.w, -> , e.v); } }; namespace __io { void setIn(string second) { freopen(second.c_str(), r , stdin); } void setOut(string second) { freopen(second.c_str(), w , stdout); } void setIO(string second = ) { ios_base::sync_with_stdio(0); cin.tie(0); cout << fixed; cout.precision(15); if (int((second).size())) { setIn(second + .in ), setOut(second + .out ); } } } // namespace __io using namespace __io; template <typename E> struct tree { int V; vector<E> edges; vector<vector<E>> adj; vi subt_sz; vb erased; tree() {} tree(int _V) : V(_V) { edges.resize(V - 1); adj.resize(V), subt_sz.resize(V), erased.resize(V); } tree(const vector<E>& __edges) : tree(int((__edges).size()) + 1) { edges = __edges; init(); } void init() { for (int i = 0; i < (int((edges).size())); i++) { auto& e = edges[i]; e.i = i; assert(0 <= e.u && e.u < V && 0 <= e.v && e.v < V); adj[e.u].push_back(e); adj[e.v].push_back(e); } } friend void re(tree& t) { re(t.edges); t.init(); } friend void pr(const tree& t) { pr( {V= , t.V, , t.edges, } ); } void erase(int v) { erased[v] = true; } void calc_subt_sz(int v, int p = -1) { subt_sz[v] = 1; for (auto& e : adj[v]) if (int u = e[v]; !erased[u] && u != p) { calc_subt_sz(u, v); subt_sz[v] += subt_sz[u]; } } int centroid(int v) { calc_subt_sz(v); int c = v; FIND: for (auto& e : adj[c]) if (int u = e[c]; !erased[u]) { if (subt_sz[u] < subt_sz[c] && 2 * subt_sz[u] >= subt_sz[v]) { c = u; goto FIND; } } return c; } }; using E = wedge<int>; tree<E> tr; vi w; vd tot, der; void go(int r, int v, int p = -1, double d = 0.) { double tmp = w[v] * sqrt(d); tot[r] += tmp * d; der[r] += tmp; for (auto& e : tr.adj[v]) if (e[v] != p) { go(r, e[v], v, d + e.w); } } pair<double, int> best = {DBL_MAX, -1}; void solve(int v) { v = tr.centroid(v); double cd = 0.; pair<double, int> n{0., -1}; for (auto& e : tr.adj[v]) { int u = e[v]; tot[u] = der[u] = 0.; go(u, u, v, e.w); cd += tot[u]; ckmax(n, make_pair(der[u], u)); } ckmin(best, make_pair(cd, v + 1)); tr.erase(v); if (n.second != -1 && !tr.erased[n.second]) solve(n.second); } int main() { setIO(); int N; re(N); w.resize(N); re(w); tr = tree<E>(N); re(tr); tot.resize(N), der.resize(N); solve(0); ps(best.second, best.first); return 0; } |
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2018/11/07 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
module autoinst_precomment (
why,
/*AUTOARG*/
// Inputs
nnnot
);
input why;
input nnnot;
autoinst_wildcard_sub sub0
(
.sd_ras_ (foobar_ras_),
//.sd0_dqm7_l (dontdome),
/*AUTOINST*/
// Inouts
.sd0_dqm7_l (sd0_dqm7_l),
.sd0_dqm6_l (sd0_dqm6_l),
.sd0_dqm5_l (sd0_dqm5_l),
.sd0_dqm4_l (sd0_dqm4_l),
.sd0_dqm3_l (sd0_dqm3_l),
.sd0_dqm2_l (sd0_dqm2_l),
.sd0_dqm1_l (sd0_dqm1_l),
.sd0_dqm0_l (sd0_dqm0_l),
.sd0_ba1 (sd0_ba1),
.sd0_ba0 (sd0_ba0),
.sd0_adrs11 (sd0_adrs11),
.sd0_adrs10 (sd0_adrs10),
.sd0_adrs9 (sd0_adrs9),
.sd0_adrs8 (sd0_adrs8),
.sd0_adrs7 (sd0_adrs7),
.sd0_adrs6 (sd0_adrs6),
.sd0_adrs5 (sd0_adrs5),
.sd0_adrs4 (sd0_adrs4),
.sd0_adrs3 (sd0_adrs3),
.sd0_adrs2 (sd0_adrs2),
.sd0_adrs1 (sd0_adrs1),
.sd0_adrs0 (sd0_adrs0),
.sd0_clk (sd0_clk));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T lowbit(T x) { return x & -x; } const int N = 2e5 + 10; int n, m; int q; int res; int les[N], more[N]; bool vis[N]; void solve() { cin >> n >> m; while (m--) { int u, v; scanf( %d%d , &u, &v); if (u > v) les[u]++, more[v]++; else les[v]++, more[u]++; } for (int i = 1; i <= n; ++i) { if (!more[i]) res++, vis[i] = 1; } cin >> q; while (q--) { int x; scanf( %d , &x); int a, b; if (x == 1) { scanf( %d%d , &a, &b); if (a > b) les[a]++, more[b]++; else les[b]++, more[a]++; if (vis[a] && more[a]) vis[a] = 0, res--; if (vis[b] && more[b]) vis[b] = 0, res--; } if (x == 2) { scanf( %d%d , &a, &b); if (a > b) les[a]--, more[b]--; else les[b]--, more[a]--; if (!vis[a] && !more[a]) res++, vis[a] = 1; if (!vis[b] && !more[b]) res++, vis[b] = 1; } if (x == 3) { cout << res << endl; } } } signed main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1 << 17; const int INF = 7 << 28; struct T { int maxa, minr; T() : maxa(0), minr(INF) {} T(int a, int b) : maxa(a), minr(b) {} T operator+(T t) const { return T(max(maxa, t.maxa), min(minr, t.minr)); } }; T a[MAXN * 2]; int del[MAXN * 2]; int l[MAXN], r[MAXN], t[MAXN]; void setDel(int i, int d) { del[i] += d; a[i].minr -= d; } void push(int i) { setDel(i * 2, del[i]); setDel(i * 2 + 1, del[i]); del[i] = 0; } void com(int i) { push(i); a[i] = a[i * 2] + a[i * 2 + 1]; } void clear(int i) { int j; for (j = 0; (1 << j) < MAXN; j++) ; for (; j; j--) push(i >> j); } T get(int i) { clear(i); T ret = T(); while (i) { if (~i & 1) ret = a[i + 1] + ret; i >>= 1; } return ret; } void modify(int i, T t) { i += MAXN; clear(i); a[i] = t; del[i] = 0; i >>= 1; while (i) { com(i); i >>= 1; } } void init() { fill(a, a + MAXN * 2, T()); } void put(int t) { printf( %d , t); } int main() { int n; int i, j, k; int ans = 0; init(); scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d%d , &l[i], &r[i], &t[i]); r[i]++; } for (i = 1; i <= n; i++) { if (max(ans, l[i]) + t[i] <= r[i]) { put(0); modify(i, T(t[i], max(ans, l[i]) - l[i])); ans = max(ans, l[i]) + t[i]; } else { int ra, rr; j = 1; ra = 0; rr = INF; while (j < MAXN) { push(j); j = j * 2 + 1; if (max(a[j].maxa, ra) < min(rr, a[j].minr)) { ra = max(a[j].maxa, ra); rr = min(a[j].minr, rr); j--; } } T temp = get(j); int move = max(temp.maxa, min(temp.minr, a[j].maxa)); if (max(ans - move, l[i]) + t[i] > r[i] || max(ans - move, l[i]) + t[i] >= ans) { put(-1); continue; } move = min(move, ans - l[i]); j = 1; while (j < MAXN) { j = j * 2 + 1; if (a[j].maxa < move) j--; } put(j - MAXN); temp = get(j); move = min(temp.minr, a[j].maxa); ans -= move; modify(j - MAXN, T(0, INF)); while (j != 1) { if (~j & 1) setDel(j + 1, move); j >>= 1; com(j); } modify(i, T(t[i], max(ans, l[i]) - l[i])); ans = max(ans, l[i]) + t[i]; } } printf( n ); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_clgen.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [3:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [3:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {4{1'b0}};
assign cnt_one = cnt == {{3{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {4{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{3{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// Brief Description: Contains the capture registers for data back from the
// RAM as well as the FIFO used by the drawing engine data path for
// read-modify-write
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log: mc_mff_key.v.rca $
//
// Revision: 1.3 Thu Aug 6 22:11:31 2009 linstale
// Update with 072709 drop version.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_mff_key
#(parameter BYTES = 4)
(
input [(BYTES*8)-1:0] data_in,
input [31:0] key_in,
input [1:0] pix,
input [2:0] kcnt,
input [BYTES-1:0] mask_in,
output reg [BYTES-1:0] key_mask
);
reg [BYTES-1:0] key_mask_tmp1;
reg [BYTES-1:0] key_mask_tmp2;
// Color keying support logic.
// This logic compares source or destination data (depending on key control)
// to a key color, and masks the write if there is a match.
// Interpertation of kcnt:
// 0xx = no masking
// 100 = source masking, mask keyed color
// 101 = destination masking, mask keyed color
// 110 = source masking, mask NOT keyed color
// 111 = destination masking, mask NOT keyed color
always @* begin
// Each of the 16 bytes or 8 words or 4 longwords are compared according
// to pixel format
casex(pix)
2'b00:
begin
key_mask_tmp1[0] = (data_in[7:0] == key_in[7:0]);
key_mask_tmp1[1] = (data_in[15:8] == key_in[7:0]);
key_mask_tmp1[2] = (data_in[23:16] == key_in[7:0]);
key_mask_tmp1[3] = (data_in[31:24] == key_in[7:0]);
if((BYTES == 16) || (BYTES == 8)) begin
key_mask_tmp1[4] = (data_in[39:32] == key_in[7:0]);
key_mask_tmp1[5] = (data_in[47:40] == key_in[7:0]);
key_mask_tmp1[6] = (data_in[55:48] == key_in[7:0]);
key_mask_tmp1[7] = (data_in[63:56] == key_in[7:0]);
end
if(BYTES == 16) begin
key_mask_tmp1[8] = (data_in[71:64] == key_in[7:0]);
key_mask_tmp1[9] = (data_in[79:72] == key_in[7:0]);
key_mask_tmp1[10] = (data_in[87:80] == key_in[7:0]);
key_mask_tmp1[11] = (data_in[95:88] == key_in[7:0]);
key_mask_tmp1[12] = (data_in[103:96] == key_in[7:0]);
key_mask_tmp1[13] = (data_in[111:104] == key_in[7:0]);
key_mask_tmp1[14] = (data_in[119:112] == key_in[7:0]);
key_mask_tmp1[15] = (data_in[127:120] == key_in[7:0]);
end
end
2'bx1: begin
key_mask_tmp1[1:0] = (data_in[15:0] == key_in[15:0]) ? 2'b11 : 2'b00;
key_mask_tmp1[3:2] = (data_in[31:16] == key_in[15:0]) ? 2'b11 : 2'b00;
if((BYTES == 16) || (BYTES == 8)) begin
key_mask_tmp1[5:4] = (data_in[47:32] == key_in[15:0]) ? 2'b11 : 2'b00;
key_mask_tmp1[7:6] = (data_in[63:48] == key_in[15:0]) ? 2'b11 : 2'b00;
end
if(BYTES == 16) begin
key_mask_tmp1[9:8] = (data_in[79:64] == key_in[15:0]) ? 2'b11 : 2'b00;
key_mask_tmp1[11:10] = (data_in[95:80] == key_in[15:0]) ? 2'b11 : 2'b00;
key_mask_tmp1[13:12] = (data_in[111:96] == key_in[15:0]) ? 2'b11 : 2'b00;
key_mask_tmp1[15:14] = (data_in[127:112] == key_in[15:0]) ? 2'b11 : 2'b00;
end
end
2'b10: begin
key_mask_tmp1[3:0] = (data_in[23:0] == key_in[23:0]) ? 4'b1111 : 4'b0000;
if((BYTES == 16) || (BYTES == 8)) begin
key_mask_tmp1[7:4] = (data_in[55:32] == key_in[23:0]) ? 4'b1111 : 4'b0000;
end
if(BYTES == 16) begin
key_mask_tmp1[11:8] = (data_in[87:64] == key_in[23:0]) ? 4'b1111 : 4'b0000;
key_mask_tmp1[15:12] = (data_in[119:96] == key_in[23:0]) ? 4'b1111 : 4'b0000;
end
end
default: begin
key_mask_tmp1[3:0] = 4'b0000;
if((BYTES == 16) || (BYTES == 8)) key_mask_tmp1[7:4] = 4'b0000;
if(BYTES == 16) key_mask_tmp1[15:8] = 8'b00000000;
end
endcase // casex(pix)
// The final mask is inverted if necessary, depending on key control
key_mask_tmp2 = !kcnt[1] ? key_mask_tmp1 : ~key_mask_tmp1;
// The mask is ignored and set to zero if 2d color keying is disabled
key_mask[3:0] = mask_in[3:0] | {4{(kcnt[2] & kcnt[0])}} & key_mask_tmp2[3:0];
if((BYTES == 16) || (BYTES == 8)) key_mask[7:4] = mask_in[7:4] | {4{(kcnt[2] & kcnt[0])}} & key_mask_tmp2[7:4];
if(BYTES == 16) key_mask[15:8] = mask_in[15:8] | {8{(kcnt[2] & kcnt[0])}} & key_mask_tmp2[15:8];
end // always @ *
endmodule // mc_mff_key
|
#include <bits/stdc++.h> using namespace std; struct BIT { int bit[200005]; void init() { memset(bit, 0, sizeof(bit)); } void add(int k, int x) { k++; while (k < 200005) { bit[k] += x; k += k & -k; } } int get(int k) { k++; int ret = 0; while (k > 0) { ret += bit[k]; k -= k & -k; } return ret; } int get(int s, int t) { return get(t) - get(s - 1); } }; BIT bit[3]; set<int> st[3]; set<int>::iterator it; int A[200005]; char str[200005]; int n; int ctoi(char c) { if (c == R ) return 0; if (c == P ) return 1; if (c == S ) return 2; return -1; } int get(int l, int r, int c) { l = max(l, 0); r = min(r, n - 1); if (l > r) return 0; return bit[c].get(l, r); } void rm(int v) { st[A[v]].erase(v); bit[A[v]].add(v, -1); } void ins(int v) { st[A[v]].insert(v); bit[A[v]].add(v, 1); } int query() { int ret = 0; for (int i = 0; i < 3; i++) { int x = i, y = i + 1, z = i - 1; if (z < 0) z += 3; if (y >= 3) y -= 3; int my = n, mz = n; it = st[y].begin(); if (it != st[y].end()) my = *it; it = st[z].begin(); if (it != st[z].end()) mz = *it; int My = -1, Mz = -1; it = st[y].end(); if (it != st[y].begin()) { it--; My = *it; } it = st[z].end(); if (it != st[z].begin()) { it--; Mz = *it; } ret += st[x].size(); if (my < mz) { if (Mz < My) { if (mz < Mz) { ret -= get(my, mz, x); ret -= get(Mz, My, x); } else { ret -= get(min(my, Mz), max(mz, My), x); } } else { ret -= get(my, mz, x); } } else if (Mz < My) { ret -= get(Mz, My, x); } } return ret; } int main() { int Q; scanf( %d %d , &n, &Q); scanf( %s , &str); for (int i = 0; i < 3; i++) bit[i].init(); for (int i = 0; i < n; i++) { A[i] = ctoi(str[i]); ins(i); } printf( %d n , query()); while (Q--) { int t; scanf( %d %s , &t, &str); t--; rm(t); A[t] = ctoi(str[0]); ins(t); printf( %d n , query()); } return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std; const int maxn = 3e5 + 7; int n, f[maxn][20], dep[maxn]; set<int> s1, s2; int mx = 0; long long ans = 0; int path(int o, int p) { if (dep[o] < dep[p]) swap(o, p); int dis = dep[o] - dep[p]; for (int i = 19; i >= 0; --i) { if (dep[f[o][i]] >= dep[p]) { o = f[o][i]; } } if (o == p) return dis; for (int i = 19; i >= 0; --i) { if (f[o][i] != f[p][i]) { dis += 2 * (dep[o] - dep[f[o][i]]); o = f[o][i]; p = f[p][i]; } } return dis + 2; } void solve(int v) { int u; scanf( %d , &u); f[v][0] = u; dep[v] = dep[u] + 1; for (int i = 1; i < 20; ++i) { f[v][i] = f[f[v][i - 1]][i - 1]; } int dis1 = s1.empty() ? 0 : path(v, *s1.begin()); int dis2 = s2.empty() ? 0 : path(v, *s2.begin()); if (max(dis1, dis2) < mx) return; if (max(dis1, dis2) > mx) { mx = max(dis1, dis2); if (dis1 >= dis2) { for (auto &i : s2) { if (path(i, v) == mx) { s1.insert(i); } } s2.clear(); s2.insert(v); } else { for (auto &i : s1) { if (path(i, v) == mx) { s2.insert(i); } } s1.clear(); s1.insert(v); } } else { if (dis1 >= dis2) { s2.insert(v); } else { s1.insert(v); } } ans = s1.size() + s2.size(); } int main() { scanf( %d , &n); for (int i = 0; i < 20; ++i) { f[1][i] = 1; f[2][i] = 1; } s1.insert(1); mx = 1; for (int i = 2; i <= n + 1; ++i) { solve(i); printf( %lld n , ans); } return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This module takes the BT.656 stream and puts out 32-bit
* chunks coded in YCbCr 4:2:2 that correspond to 2 pixels.
* Only pixels from the active video area are taken into account.
* The field signal indicates the current field used for interlacing.
* Transitions on this signal should be monitored to detect the start
* of frames.
* When the input signal is stable, this modules puts out no more
* than one chunk every 4 clocks.
*/
module bt656cap_decoder(
input vid_clk,
input [7:0] p,
output reg stb,
output reg field,
output reg [31:0] ycc422
);
reg [7:0] ioreg;
always @(posedge vid_clk) ioreg <= p;
reg [1:0] byten;
reg [31:0] inreg;
initial begin
byten <= 2'd0;
inreg <= 32'd0;
end
always @(posedge vid_clk) begin
if(&ioreg) begin
/* sync word */
inreg[31:24] <= ioreg;
byten <= 2'd1;
end else begin
byten <= byten + 2'd1;
case(byten)
2'd0: inreg[31:24] <= ioreg;
2'd1: inreg[23:16] <= ioreg;
2'd2: inreg[15: 8] <= ioreg;
2'd3: inreg[ 7: 0] <= ioreg;
endcase
end
end
reg in_field;
reg in_hblank;
reg in_vblank;
initial begin
in_field <= 1'b0;
in_hblank <= 1'b0;
in_vblank <= 1'b0;
stb <= 1'b0;
end
always @(posedge vid_clk) begin
stb <= 1'b0;
if(byten == 2'd0) begin
/* just transferred a new 32-bit word */
if(inreg[31:8] == 24'hff0000) begin
/* timing code */
in_hblank <= inreg[4];
in_vblank <= inreg[5];
in_field <= inreg[6];
end else begin
/* data */
if(~in_hblank && ~in_vblank) begin
stb <= 1'b1;
field <= in_field;
ycc422 <= inreg;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); int a[32][101111], n, m, d[32][111111], b[111111], t[400111]; pair<pair<int, int>, int> p[111111]; int bit(int mask, int i) { return (mask & (1 << i)) > 0; } void build(int v, int tl, int tr) { if (tl == tr) t[v] = b[tl]; else { int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); t[v] = (t[v * 2] & t[v * 2 + 1]); } } int get(int v, int tl, int tr, int l, int r) { if (l > r) return (1 << 30) - 1; if (l == tl && r == tr) return t[v]; int tm = (tl + tr) / 2; return get(v * 2, tl, tm, l, min(r, tm)) & get(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r); } int main() { scanf( %d%d , &n, &m); int len = (int)sqrt(n + .0) + 1; for (int cs = 0; cs < m; ++cs) { int l, r, q; scanf( %d%d%d , &l, &r, &q); p[cs] = make_pair(make_pair(l, r), q); for (int j = 0; j < 30; ++j) { int w = bit(q, j); if (w == 0) continue; a[j][l]++; a[j][r + 1]--; } } for (int i = 0; i < 30; ++i) { int second = 0; for (int j = 1; j <= n; ++j) { second += a[i][j]; a[i][j] = a[i][j - 1] + second; } } for (int i = 1; i <= n; ++i) { int ans = 0; for (int j = 0; j < 30; ++j) ans += (1 << j) * (a[j][i] - a[j][i - 1] > 0); b[i] = ans; } build(1, 1, n); for (int i = 0; i < m; ++i) { int l = p[i].first.first, r = p[i].first.second, q = p[i].second; if (get(1, 1, n, l, r) != q) { puts( NO ); return 0; } } puts( YES ); for (int i = 1; i <= n; ++i) printf( %d , b[i]); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:44:46 09/24/2013
// Design Name: Data_Parameters
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_data_parameters.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Data_Parameters
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_data_parameters;
// Inputs
reg clock;
reg reset;
reg [3:0] mem_address;
reg write_value_reg_en;
reg [1:0] write_data_selector;
// Outputs
wire [3:0] write_value;
// Instantiate the Unit Under Test (UUT)
Data_Parameters uut (
.clock(clock),
.reset(reset),
.mem_address(mem_address),
.write_value_reg_en(write_value_reg_en),
.write_data_selector(write_data_selector),
.write_value(write_value)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
mem_address = 0;
write_value_reg_en = 0;
write_data_selector = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e3 + 5; const int mod = 1e9 + 9; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; cout << (2 * n) - 1 << << 2 << endl << 1 << << 2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> starts(m), ends(m), results; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; starts[l - 1]++; ends[r - 1]++; } int open = 0; for (int i = 0; i < m; i++) { open += starts[i]; if (open == 0) results.push_back(i + 1); open -= ends[i]; } std::cout << results.size() << std::endl; for (auto p : results) cout << p << ; cout << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND4B_FUNCTIONAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxN = 1e5 + 10; int n, m, s, f; int t[maxN], l[maxN], r[maxN]; bool inside(int l, int m, int r) { return l <= m && m <= r; } void slv() { int d = f > s ? 1 : -1; m++; t[m] = inf, l[m] = inf, r[m] = -inf; int tm = 1; int p = 1; while (true) { if (s == f) break; if (tm != t[p]) s += d, printf( %c , d > 0 ? R : L ); else { if (inside(l[p], s, r[p]) || inside(l[p], s + d, r[p])) printf( X ); else printf( %c , d > 0 ? R : L ), s += d; p++; } tm++; } } int main() { while (~scanf( %d%d%d%d , &n, &m, &s, &f)) { for (int i = 1; i <= m; i++) scanf( %d%d%d , &t[i], &l[i], &r[i]); slv(); } return 0; } |
//*******************************************************************************************************************************************************/
// Module Name: reg_array_dual
// Module Type: Synchronous Dual Port Memory Array
// Author: Shreyas Vinod
// Purpose: General Purpose Register Array for Neptune I v3.0
// Description: A synchronous unidirectional dual port general purpose register array with a simple fault mechanism to detect dual write single address
// collisions.
//*******************************************************************************************************************************************************/
module reg_array_dual(clk, rst, we1, we2, add1, add2, wr1, wr2, mem_fault, rd1, rd2);
// Parameter Definitions
parameter width = 'd16; // Register Array Width
parameter depth = 'd8; // Register Array Depth
parameter add_width = 'd3; // Register Addressing Width
// Inputs
input wire clk /* System Clock */, rst /* System Reset. Resets Memory Fault Flag. */; // Management Interfaces
input wire we1 /* Write Enable to Port I */, we2 /* Write Enable to Port II */; // Control Interfaces
input wire [add_width-1:0] add1 /* Address for Port I */, add2 /* Address for Port I */;
input [width-1:0] wr1 /* Write Port I */, wr2 /* Write Port II */;
// Outputs
output reg mem_fault /* Memory Write Collision Fault Flag */;
output reg [width-1:0] rd1 /* Read Port I */, rd2 /* Read Port II */;
// Internal
reg [width-1:0] mem_arr [0:depth-1] /* Memory Array */;
// Fault Logic
always@(posedge clk) begin
if(rst) mem_fault <= 1'b0;
else if((we1 && we2) && (add1 && add2)) mem_fault <= 1'b1;
end
// Memory Read Block
always@(posedge clk) begin
rd1 [width-1:0] <= mem_arr[add1] [width-1:0]; // Read to Port I if re1 is true.
rd2 [width-1:0] <= mem_arr[add2] [width-1:0]; // Read to Port II if re2 is true.
end
// Memory Write Block
always@(posedge clk) begin
if(we1) mem_arr[add1] [width-1:0] <= wr1 [width-1:0]; // Write from Port I if we1 is true.
if(we2) mem_arr[add2] [width-1:0] <= wr2 [width-1:0]; // Write from Port II if we2 is true.
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
supply0 [1:0] low;
supply1 [1:0] high;
reg [7:0] isizedwire;
reg ionewire;
`ifdef never_just_for_verilog_mode
wire oonewire; // From sub of t_inst_v2k_sub.v
`endif
wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v
wire [1:0] tied;
wire [3:0] tied_also;
hello hsub (.tied_also);
t_inst_v2k_sub sub
(
// Outputs
.osizedreg (osizedreg[7:0]),
// verilator lint_off IMPLICIT
.oonewire (oonewire),
// verilator lint_on IMPLICIT
.tied (tied[1:0]),
// Inputs
.isizedwire (isizedwire[7:0]),
.ionewire (ionewire));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
ionewire <= 1'b1;
isizedwire <= 8'd8;
end
if (cyc==2) begin
if (low != 2'b00) $stop;
if (high != 2'b11) $stop;
if (oonewire !== 1'b1) $stop;
if (isizedwire !== 8'd8) $stop;
if (tied != 2'b10) $stop;
if (tied_also != 4'b1010) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module hello(tied_also);
initial $write ("Hello\n");
output reg [3:0] tied_also = 4'b1010;
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) #pragma comment(linker, /STACK:1024000000,1024000000 ) const long double pi = acosl(-1.); int T; const long long mod = 258280327; long long gcd(long long x, long long y) { if (!y) return x; return gcd(y, x % y); } long long quickfind(long long x, long long y) { long long result = 1; while (y) { if (y & 1) result = result * x % mod; y >>= 1; x = x * x % mod; } return result; } using namespace std; int dfn[33333]; int cnt[33333]; struct master { int x, y, z; master(int x = 0, int y = 0, int z = 0) : x(x), y(y), z(z) {} }; int n; int size[33333]; vector<master> cd[33333]; vector<int> ans; int q[11111111] = {0}; int h = 5000000, t = 5000000 - 1; void solve() { for (int i = 1; i <= n; i++) q[++t] = i, size[i] = 4; while (h <= t) { int x = q[h++]; if ((int)cd[x].size() == 0) continue; int y = cd[x][(int)cd[x].size() - 1].x; int z = cd[x][(int)cd[x].size() - 1].y; size[x]--, size[y]++, size[z]++; if (size[y] > 9 || size[z] > 9) { size[x]++; size[y]--; size[z]--; q[++t] = x; continue; } ans.push_back(cd[x][(int)cd[x].size() - 1].z); cd[x].pop_back(); q[++t] = x; } } int main() { srand(time(NULL)); scanf( %d , &n); for (int i = 1; i <= n << 2; i++) { int a, b, c; scanf( %d , &a); scanf( %d , &b); scanf( %d , &c); cd[a].push_back(master(b, c, i)); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= 16; j++) { int x = rand() % 4; int y = rand() % 4; swap(cd[i][x], cd[i][y]); } } solve(); if ((int)ans.size() == n * 4) { printf( YES n ); printf( %d , ans[0]); for (int i = 1; i <= (int)ans.size() - 1; i++) printf( %d , ans[i]); puts( ); } else printf( NO n ); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: rep_jbi_sc3_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module rep_jbi_sc3_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline char nc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline void read(int &x) { char c = nc(), b = 1; for (; !(c >= 0 && c <= 9 ); c = nc()) { if (c == - ) b = -b; } for (x = 0; c >= 0 && c <= 9 ; x = x * 10 + c - 0 , c = nc()) ; x *= b; } const int N = 500001; const int sqN = 708; int ans[N]; int fre[N]; int v[N]; int block[sqN]; int flag[sqN]; int answer = 0; vector<int> bl; struct query { int l; int r; int idx; } Q[N]; bool comp(query q1, query q2) { if (q1.l / sqN != q2.l / sqN) { return q1.l < q2.l; } if ((q1.l / sqN) & 1) { return q1.r < q2.r; } return q1.r > q2.r; } inline void add(int idx) { int val = v[idx]; fre[val]++; if (fre[val] == 1) { answer++; block[val / sqN]++; if (!flag[val / sqN]) { flag[val / sqN] = 1; bl.push_back(val / sqN); } } if (fre[val] == 2) { answer--; block[val / sqN]--; } } inline void rem(int idx) { int val = v[idx]; fre[val]--; if (fre[val] == 1) { answer++; block[val / sqN]++; if (!flag[val / sqN]) { flag[val / sqN] = 1; bl.push_back(val / sqN); } } if (fre[val] == 0) { answer--; block[val / sqN]--; } } inline int solve() { if (answer == 0) { return 0; } while (!bl.empty() && block[bl.back()] < 1) flag[bl.back()] = 0, bl.pop_back(); int i = bl.back(); for (int j = i * sqN; j < i * sqN + sqN; j++) { if (fre[j] == 1) { return j; } } } int main() { int n; read(n); for (int i = 0; i < n; i++) { read(v[i]); } int q, l, r; read(q); for (int i = 0; i < q; i++) { read(l); read(r); l--; r--; Q[i].l = l; Q[i].r = r; Q[i].idx = i; } sort(Q, Q + q, comp); l = 0, r = -1; for (int i = 0; i < q; i++) { int L = Q[i].l; int R = Q[i].r; while (l < L) { rem(l); l++; } while (l > L) { l--; add(l); } while (r < R) { r++; add(r); } while (r > R) { rem(r); r--; } ans[Q[i].idx] = solve(); } for (int i = 0; i < q; i++) { printf( %d n , ans[i]); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long long max(long long a, long long b) { if (a > b) { return a; } else { return b; } } long long min(long long a, long long b) { if (a < b) { return a; } else { return b; } } long long power(long long b, long long e) { if (e == 0) return 1; if (e % 2) return ((b * power((b) * (b), (e - 1) / 2))); else return power((b) * (b), e / 2); } long long modpower(long long b, long long e, long long q) { long long MOD = q; if (e == 0) return 1; if (e % 2) return ((b % MOD) * modpower((b % MOD) * (b % MOD), (e - 1) / 2, q)) % MOD; else return modpower((b % MOD) * (b % MOD), e / 2, q) % MOD; } void dpv(vector<long long> v) { for (long long i = 0; i < v.size(); i++) { cout << v[i] << ; } cout << n ; } void dpv(vector<pair<long long, long long> > v) { for (long long i = 0; i < v.size(); i++) { cout << v[i].first << << v[i].second << n ; } } void dpv(set<long long> v) { for (auto i : v) { cout << i << ; } cout << n ; } void oblivious() { string s; cin >> s; long long p = 0, ans = 0, q = 1; for (long long i = 0; i <= s.length(); i++) { if (s[i] == + || s[i] == - || i == s.length()) { ans += p * q; p = 0; if (i == s.length()) { continue; } if (s[i] == + ) { q = 1; } else if (s[i] == - ) { q = -1; } } else { p = (10 * p + s[i] - 0 ); } } long long u = ans; long long y = 0; string s1; if (u == 0) { s1.push_back( 0 ); } else { while (u != 0) { s1.push_back(u % 10 + 0 ); u = u / 10; } } reverse(s1.begin(), s1.end()); for (long long i = 0; i < s1.length(); i++) { long long z = s1[i]; while (z--) { cout << + ; } cout << .> ; cout << n ; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { oblivious(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/14/2016 05:02:16 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// select 300 DPI or 600 DPI mode
`define DPI_300
// `define DPI_600
// Period of CIS clock is equal to 60MHz/USB_CLK_DIV
// Must be an even number
`define USB_CLK_DIV 'd12
// Sample ADC 16.7ns before the next rising edge of CIS_CLK
`define ADC_CLK_DELAY (`USB_CLK_DIV/2)-1
// Issue write pulse immediately before next rising edge of ADC_CLK
// `define WR_PULSE_DELAY (`USB_CLK_DIV/2)-2
`define WR_PULSE_DELAY 4
// define the clock window when the LED needs to be off
`define CIS_LED_OFF 'd40
`define CIS_LED_ON 'd70
// define the clock cycle at which the oscilloscope should be triggered
`define SCOPE_SYNC_POS 'd1000
`ifdef DPI_300
`define CIS_CLK_PER_LINE 'd2700
`else
`define CIS_CLK_PER_LINE 'd5300
`endif
module top(
// Inputs from USB IC
input USB_CLK,
// Inputs from ADC
input [7:0] ADC_DATA,
// Outputs to CIS module
output CIS_MODE,
output reg CIS_CLK,
output reg CIS_SP,
output reg CIS_LED_BLUE,
output reg CIS_LED_GREEN,
output reg CIS_LED_RED,
// Outputs to USB IC
output [7:0] USB_DATA,
output reg USB_WR_L,
// Outputs to ADC
output reg ADC_CLK,
// Outputs to oscilloscope
output reg SCOPE_SYNC
);
// internal reg variables
reg [3:0] counter_usb_clk;
reg [12:0] counter_cis_clk;
// Set the DPI mode of the scanner
`ifdef DPI_300
assign CIS_MODE = 'b0;
`else
assign CIS_MODE = 'b1;
`endif
assign USB_DATA = ADC_DATA;
initial begin
// output initializations
USB_WR_L = 'b0;
CIS_CLK = 'b0;
CIS_SP = 'b1;
CIS_LED_BLUE = 'b1;
CIS_LED_GREEN = 'b1;
CIS_LED_RED = 'b1;
SCOPE_SYNC = 'b0;
// internal counter variables
counter_usb_clk = 'd1;
counter_cis_clk = 'd1;
end
// Generate the clock used to read out from the CIS module
// by dividing down the 60MHz clock
always @(posedge USB_CLK) begin
// Generate the CIS clock signal
if (0 <= counter_usb_clk && counter_usb_clk < (`USB_CLK_DIV/2)) begin
CIS_CLK <= 'b1;
end else begin
CIS_CLK <= 'b0;
end
// Generate the shifted ADC sampling clock
if (`ADC_CLK_DELAY <= counter_usb_clk && counter_usb_clk < (`ADC_CLK_DELAY+`USB_CLK_DIV/2)) begin
ADC_CLK <= 'b1;
end else begin
ADC_CLK <= 'b0;
end
// Increment the clock counter
if (counter_usb_clk == (`USB_CLK_DIV-1)) begin
counter_usb_clk <= 'd0;
end else begin
counter_usb_clk <= counter_usb_clk + 'd1;
end
end
always @(negedge USB_CLK) begin
if (counter_usb_clk == `WR_PULSE_DELAY) begin
USB_WR_L <= 'b0;
end else begin
USB_WR_L <= 'b1;
end
end
always @(posedge CIS_CLK) begin
// update LED settings
if (counter_cis_clk == `CIS_LED_OFF) begin
CIS_LED_BLUE <= 'b0;
CIS_LED_GREEN <= 'b0;
CIS_LED_RED <= 'b0;
end else if (counter_cis_clk == `CIS_LED_ON) begin
CIS_LED_BLUE <= 'b1;
CIS_LED_GREEN <= 'b1;
CIS_LED_RED <= 'b1;
end
// update CIS counter
if (counter_cis_clk == `CIS_CLK_PER_LINE) begin
counter_cis_clk <= 'd1;
CIS_SP <= 'b1;
end else begin
counter_cis_clk <= counter_cis_clk + 'd1;
CIS_SP <= 'b0;
end
// update SCOPE_SYNC signal
if (counter_cis_clk == `SCOPE_SYNC_POS) begin
SCOPE_SYNC <= 1'b1;
end else begin
SCOPE_SYNC <= 1'b0;
end
end
endmodule
|
#include<bits/stdc++.h> #define rep(i,a,b) for(long long i=a;i<b;i++) #define pb push_back #define f first #define s second #define is insert #define vector_int vector<int> #define ll long long #define pqi priority_queue<int> #define all(x) x.begin(),x.end() #define mem(x,y) memset(x,y,sizeof(x)) #define sz(x) (int)x.size() #define pii pair<int,int> #define pll pair<ll,ll> #define INF 1e9 #define INFL 1e18 #define mod 1000000007 #define fast ios::sync_with_stdio(false);cin.tie(0); using namespace std; int equalPartition(int n, vector<int> arr) { int sum = 0; int i, j; // Calculate sum of all elements for (i = 0; i < n; i++) sum += arr[i]; if (sum % 2 != 0) return false; bool part[sum / 2 + 1][n + 1]; // initialize top row as true for (i = 0; i <= n; i++) part[0][i] = true; // initialize leftmost column, // except part[0][0], as 0 for (i = 1; i <= sum / 2; i++) part[i][0] = false; // Fill the partition table in bottom up manner for (i = 1; i <= sum / 2; i++) { for (j = 1; j <= n; j++) { part[i][j] = part[i][j - 1]; if (i >= arr[j - 1]) part[i][j] = part[i][j] || part[i - arr[j - 1]][j - 1]; } } /* // uncomment this part to print table for (i = 0; i <= sum/2; i++) { for (j = 0; j <= n; j++) cout<<part[i][j]; cout<<endl; } */ return part[sum / 2][n]; } void solve(){ ll n=0;cin>>n; vector<int> arr; for(int i=0;i<n;i++) { int x; cin>>x; arr.pb(x); } if(equalPartition( n,arr)==0) cout<<0<<endl; else { for(int i=0;i<n;i++){ int x=arr[i]; arr[i]=0; if(equalPartition(n,arr)==0) { cout<<1<<endl<<i+1<<endl; break; } else{ arr[i]=x; } } } } int main() { solve(); return 0; } |
//==================================================================================================
// Filename : DECO_CORDIC_OP.v
// Created On : 2016-10-03 13:00:49
// Last Modified : 2016-10-03 14:44:53
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : DECODER TO TO SELECT THE THIRD MUX AND INVERT SIGN
//
//
//==================================================================================================
`timescale 1ns / 1ps
module DECO_CORDIC_EXT #(parameter W = 32)(
input wire [W-1:0] data_i,
input wire operation,
input wire [1:0] shift_region_flag,
output reg sel_mux_3,
output reg [W-1:0] data_out
);
always @(*) begin
if(operation == 1'b0)
begin //COSENO
case (shift_region_flag)
2'b00 : begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
2'b01 : begin
sel_mux_3 = 1'b1;
data_out = {~data_i[W-1],data_i[W-2:0]};
end
2'b10 : begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
2'b11 : begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
default: begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
endcase
end
else begin ///SENO
case (shift_region_flag)
2'b00 : begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
2'b01 : begin
sel_mux_3 = 1'b0;
data_out = data_i;
end
2'b10 : begin
sel_mux_3 = 1'b0;
data_out = {~data_i[W-1],data_i[W-2:0]};;
end
2'b11 : begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
default: begin
sel_mux_3 = 1'b1;
data_out = data_i;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> long long gcd(long long x, long long y) { if (x > y) std::swap(x, y); return y % x == 0 ? x : gcd(y % x, x); } using namespace std; int main() { int n; scanf( %d , &n); int a[20]; bool flag = true; for (int i = (1); i <= (n); i++) scanf( %d , a + i); for (int i = (1); i <= (n - 1); i++) if (abs(a[i] - a[i + 1]) >= 2) flag = false; if (flag) puts( YES ); else puts( NO ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 100; vector<int> v[MAX_N]; int dp[MAX_N], ans, deep[MAX_N]; void dfs(int x, int fa, int dep) { int i; deep[x] = dep; for (i = 0; i < v[x].size(); i++) { int y = v[x][i]; if (y == fa) continue; dfs(y, x, dep + 1); } } void dfs(int x, int fa) { int i; dp[x] = 0; for (i = 0; i < v[x].size(); i++) { int y = v[x][i]; if (y == fa) continue; dfs(y, x); ans = max(ans, dp[x] + dp[y] + 1); dp[x] = max(dp[x], dp[y] + 1); } } int main(void) { int T, n, a, b, da, db, i, x, y; cin >> T; while (T--) { scanf( %d%d%d%d%d , &n, &a, &b, &da, &db); for (i = 1; i <= n; i++) v[i].clear(); for (i = 1; i < n; i++) { scanf( %d%d , &x, &y); v[x].push_back(y); v[y].push_back(x); } dfs(a, -1, 0); if (deep[b] <= da) { puts( Alice ); continue; } if (da * 2 >= db) { puts( Alice ); continue; } ans = 0; dfs(1, -1); if (da * 2 >= ans) puts( Alice ); else puts( Bob ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dlatch_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_asin_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arcsin_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
module tb_SystolicDataSetupRow #(
parameter DATA_BITS = 8,
parameter MATRIX_SIZE = 8,
parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1
) ();
reg clock;
reg reset;
integer count;
reg [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:MATRIX_SIZE-1];
wire [DATA_BITS-1:0] data_out [0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1];
SystolicDataSetupRow #(
.DATA_BITS(DATA_BITS),
.MATRIX_SIZE(MATRIX_SIZE),
.OUTPUT_SIZE(OUTPUT_SIZE)
) DUT (
.clock(clock),
.reset(reset),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clock = 1'b0;
reset = 1'b0;
$dumpfile("Systolic.vcd") ;
$dumpvars;
end
always begin
#5 clock = ~clock;
#5 clock = ~clock;
end
initial begin
#10 reset = 1'b1;
#20 reset = 1'b0;
#30
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j=0 ; j< MATRIX_SIZE;j++)
data_in[i][j]=8'h00;
#60
count=0;
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j =0; j< MATRIX_SIZE;j++) begin
data_in[i][j]=count;
count= count+1;
end
#50
count=0;
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j=0 ; j< MATRIX_SIZE;j++) begin
data_in[i][j]=count+3;
count= count+1;
end
#50 $finish;
end
endmodule
|
//#############################################################################
//# Function: A Padring IO Domain #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module oh_pads_domain
#(parameter TYPE = "SOFT",// asic cell type selector
parameter DIR = "NO", // "NO", "SO", "EA", "WE"
parameter NGPIO = 8, // total IO signal pads
parameter NVDDIO = 8, // total IO supply pads
parameter NVSSIO = 8, // total IO ground pads
parameter NVDD = 8, // total core supply pads
parameter NVSS = 8, // total core ground pads
parameter POC = 1, // 1 = place poc cell
parameter LEFTCUT = 1, // 1 = place cut on left (seen from center)
parameter RIGHTCUT = 1 // 1 = place cut on right (seen from center
)
(//pad
inout [NGPIO-1:0] pad, // pad
//feed through signals
inout vddio, // io supply
inout vssio, // io ground
inout vdd, // core supply
inout vss, // common ground
inout poc, // power-on-ctrl
//core facing signals
input [NGPIO-1:0] dout, // data to drive to pad
output [NGPIO-1:0] din, // data from pad
input [NGPIO-1:0] oen, // output enable (bar)
input [NGPIO-1:0] ie, // input enable
input [NGPIO*8-1:0] cfg // io config
);
generate
genvar i;
//#####################
//# IO BUFFERS
//#####################
for(i=0;i<NGPIO;i=i+1)
begin : padio
asic_iobuf #(.DIR(DIR),
.TYPE(TYPE))
i0 (// data to core
.din (din[i]),
// data from core
.dout (dout[i]),
//tristate controls
.ie (ie[i]),
.oen (oen[i]),
// config signals
.cfg (cfg[i*8+:8]),
// padring signals
.poc (poc),
.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.pad (pad[i]));
end
//######################
//# IO SUPPLY PINS
//######################
for(i=0;i<NVDDIO;i=i+1)
begin : padvddio
asic_iovddio #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
//######################
//# IO GROUND PINS
//######################
for(i=0;i<NVSSIO;i=i+1)
begin: padvssio
asic_iovssio #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
//######################
//# CORE SUPPLY PINS
//######################
for(i=0;i<NVDD;i=i+1)
begin: padvdd
asic_iovdd #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
//######################
//# CORE GROUND PINS
//######################
for(i=0;i<NVSS;i=i+1)
begin: padvss
asic_iovss #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
//######################
//# CUT CELLS
//######################
if (LEFTCUT==1)
begin: padcutleft
asic_iocut #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
if (RIGHTCUT==1)
begin: padcutright
asic_iocut #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
//######################
//# POWER ON CONTROL
//######################
if (POC==1)
begin: padpoc
asic_iopoc #(.DIR(DIR),
.TYPE(TYPE))
i0 (.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.poc (poc));
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." )
// End:
|
`timescale 1 ns / 1 ps
module s2mm #
(
// Users to add parameters here
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12,
parameter integer C_DATACOUNT_BITS = 12,
parameter integer C_PIXEL_STORE_WIDTH = 8,
// User parameters ends
// Parameters of Axi Master Bus Interface M_AXI
parameter integer C_M_AXI_BURST_LEN = 16,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)
(
input wire [C_IMG_WBITS-1:0] img_width,
input wire [C_IMG_HBITS-1:0] img_height,
input wire clk,
input wire resetn,
/// @NOTE: resetting will keep until current transaction done.
/// if under idle state when negedge of soft_resetn,
/// don't need resetting, i.e. resetting will keep zero.
input wire soft_resetn,
output wire resetting,
/// sream to fifo
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire s2mm_full,
input wire s2mm_almost_full,
output wire [C_PIXEL_WIDTH+1 : 0] s2mm_wr_data,
output wire s2mm_wr_en,
/// fifo to memory
output wire s2mm_sof,
input wire [C_M_AXI_ADDR_WIDTH-1:0] s2mm_addr,
input wire [C_M_AXI_DATA_WIDTH/C_PIXEL_STORE_WIDTH*(C_PIXEL_WIDTH+2)-1 : 0] s2mm_rd_data,
input wire s2mm_empty,
output wire s2mm_rd_en,
input wire [C_DATACOUNT_BITS-1:0] s2mm_rd_data_count,
// Ports of Axi Master Bus Interface M_AXI
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output wire [7 : 0] m_axi_awlen,
output wire [2 : 0] m_axi_awsize,
output wire [1 : 0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3 : 0] m_axi_awcache,
output wire [2 : 0] m_axi_awprot,
output wire [3 : 0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [1 : 0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready
);
localparam C_PM1 = C_PIXEL_WIDTH - 1;
localparam C_PP1 = C_PIXEL_WIDTH + 1;
localparam C_PP2 = C_PIXEL_WIDTH + 2;
localparam C_ADATA_PIXELS = C_M_AXI_DATA_WIDTH/C_PIXEL_STORE_WIDTH;
function integer reverseI(input integer i);
begin
reverseI = C_ADATA_PIXELS-1-i;
end
endfunction
function integer sofIdx(input integer i);
begin
sofIdx = i * C_PP2 + C_PIXEL_WIDTH;
end
endfunction
function integer eolIdx(input integer i);
begin
eolIdx = i * C_PP2 + C_PP1;
end
endfunction
// stream to fifo
wire working;
assign working = (resetn && soft_resetn);
assign resetting = ~working;
/// use s2f_aclk
assign s2mm_wr_data = {s_axis_tlast, s_axis_tuser, s_axis_tdata};
assign s2mm_wr_en = s_axis_tvalid && s_axis_tready;
reg sready;
assign s_axis_tready = sready;
always @ (posedge clk) begin
if (resetting)
sready <= 0;
else if (s2mm_wr_en && s2mm_almost_full)
sready <= 0;
else
sready <= 1;
end
// fifo to mm
/// use f2m_aclk
wire [C_M_AXI_DATA_WIDTH-1 : 0] s2mm_pixel_data;
generate
genvar i;
for (i = 0; i < C_M_AXI_DATA_WIDTH/C_PIXEL_WIDTH; i = i+1) begin: single_pixel
assign s2mm_pixel_data[i*C_PIXEL_STORE_WIDTH + C_PM1 : i*C_PIXEL_STORE_WIDTH]
= s2mm_rd_data[reverseI(i)*C_PP2 + C_PM1 : reverseI(i)*C_PP2];
end
endgenerate
FIFO2MM # (
.C_DATACOUNT_BITS(C_DATACOUNT_BITS),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_IMG_WBITS(C_IMG_WBITS),
.C_IMG_HBITS(C_IMG_HBITS),
.C_ADATA_PIXELS(C_ADATA_PIXELS)
) FIFO2MM_inst (
.img_width(img_width),
.img_height(img_height),
.soft_resetn(soft_resetn),
//.resetting(resetting),
//.sof(s2mm_rd_data[sofIdx(reverseI(0))]),
.din(s2mm_pixel_data),
//.empty(s2mm_empty),
.rd_en(s2mm_rd_en),
.rd_data_count(s2mm_rd_data_count),
.frame_pulse(s2mm_sof),
.base_addr(s2mm_addr),
.M_AXI_ACLK(clk),
.M_AXI_ARESETN(resetn),
.M_AXI_AWADDR(m_axi_awaddr),
.M_AXI_AWLEN(m_axi_awlen),
.M_AXI_AWSIZE(m_axi_awsize),
.M_AXI_AWBURST(m_axi_awburst),
.M_AXI_AWLOCK(m_axi_awlock),
.M_AXI_AWCACHE(m_axi_awcache),
.M_AXI_AWPROT(m_axi_awprot),
.M_AXI_AWQOS(m_axi_awqos),
.M_AXI_AWVALID(m_axi_awvalid),
.M_AXI_AWREADY(m_axi_awready),
.M_AXI_WDATA(m_axi_wdata),
.M_AXI_WSTRB(m_axi_wstrb),
.M_AXI_WLAST(m_axi_wlast),
.M_AXI_WVALID(m_axi_wvalid),
.M_AXI_WREADY(m_axi_wready),
.M_AXI_BRESP(m_axi_bresp),
.M_AXI_BVALID(m_axi_bvalid),
.M_AXI_BREADY(m_axi_bready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, t, lim = 16; int w[4], g[1005]; char ch[4][1005]; int num[4][4]; int s[4][4][4]; int dp[1005][16][16][16][16]; int main() { scanf( %d , &n); for (int i = 0; i < 4; i++) scanf( %d , &w[i]); for (int i = 0; i < 4; i++) scanf( %s , ch[i]); memset(dp, 0x3f, sizeof(dp)); for (int i = 0; i < n; i++) { t = 0; for (int j = 0; j < 4; j++) t <<= 1, t += (ch[j][i] == . ); g[i] = t; } for (int i = n; i < n + 5; i++) g[i] = lim - 1; dp[0][g[0]][g[1]][g[2]][g[3]] = 0; for (int i = 0; i < 4; i++) for (int j = 0; j < 4 - i; j++) { for (int k = 0; k < 4; k++) for (int p = 0; p < 4; p++) num[k][p] = 0; for (int k = 0; k <= i; k++) for (int p = j; p <= j + i; p++) num[k][p] = 1; for (int k = 0; k < 4; k++) { t = 0; for (int p = 0; p < 4; p++) t <<= 1, t += num[k][p]; s[i][j][k] = t; } } for (int i = 0; i < n; i++) for (int a = 0; a < lim; a++) for (int b = 0; b < lim; b++) for (int c = 0; c < lim; c++) for (int d = 0; d < lim; d++) { if (dp[i][a][b][c][d] >= 0x3f3f3f3f) continue; if (a == lim - 1) dp[i + 1][b][c][d][g[i + 4]] = min(dp[i + 1][b][c][d][g[i + 4]], dp[i][a][b][c][d]); for (int j = 0; j < 4; j++) for (int k = 0; k < 4 - j; k++) dp[i][a | s[j][k][0]][b | s[j][k][1]][c | s[j][k][2]] [d | s[j][k][3]] = min(dp[i][a | s[j][k][0]][b | s[j][k][1]] [c | s[j][k][2]][d | s[j][k][3]], dp[i][a][b][c][d] + w[j]); } printf( %d , dp[n - 1][lim - 1][lim - 1][lim - 1][lim - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; namespace fio { streambuf* in = cin.rdbuf(); char bb[1000000], *s = bb, *t = bb; inline long long read() { long long x = 0; char ch = (s == t && (t = (s = bb) + in->sgetn(bb, 1000000), s == t) ? EOF : *s++); while (ch < 48) ch = (s == t && (t = (s = bb) + in->sgetn(bb, 1000000), s == t) ? EOF : *s++); while (ch >= 48) x = x * 10 + ch - 48, ch = (s == t && (t = (s = bb) + in->sgetn(bb, 1000000), s == t) ? EOF : *s++); return x; } } // namespace fio using fio::read; long long n; int m, llm; int lim[26]; vector<int> road[26]; map<array<int, 26>, int> huaji; array<int, 26> pm; class mat { public: int val[125][125]; int* operator[](int x) { return val[x]; } mat operator*(mat _) { mat ans; for (int i = 1; i <= llm; i++) for (int u = 1; u <= llm; u++) { ans[i][u] = 0; for (int j = 1; j <= llm; j++) ans[i][u] = (ans[i][u] + val[i][j] * _[j][u]) % 12345; } return ans; } }; mat ksm(mat x, long long y) { mat ans = x; y--; for (; y; y >>= 1, x = x * x) if (y & 1) ans = ans * x; return ans; } mat base; int ans; int main() { n = read(), m = read(); if (!n) return cout << 1, 0; if (!m) return cout << 0, 0; for (int i = 1, x, y; i <= m; i++) x = read() + 0 - A , road[x].emplace_back(y = read()), lim[x] = max(lim[x], 1) * road[x].back(); while (pm[25] < max(lim[25], 1)) { huaji[pm] = ++llm, pm[0]++; for (int i = 0; i < 25; i++) if (lim[i]) pm[i + 1] += pm[i] / lim[i], pm[i] %= lim[i]; else pm[i + 1] += pm[i], pm[i] = 0; } for (pair<array<int, 26>, int> it : huaji) for (int i = 0; i < 26; i++) if (lim[i]) it.first[i] = (it.first[i] + 1) % lim[i], base[it.second][huaji[it.first]]++, it.first[i] = (it.first[i] - 1 + lim[i]) % lim[i]; base = ksm(base, n); for (pair<array<int, 26>, int> it : huaji) { bool flag = 1; for (int i = 0, fx = 0; flag && i < 26; i++, flag &= fx, fx = 0) if (!lim[i]) fx = 1; else for (int p : road[i]) fx |= !(it.first[i] % p); flag ? ans = (ans + base[1][it.second]) % 12345 : ans; } cout << ans << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_PP_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline int read() { int x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { write(x); puts( ); } struct Node { int x, y, w; } a, b, c, g[6005]; int n, x, y, S, m[5][5], f[5][5][5]; long long now1, now2, ans1, ans2, ans3; inline int gcd(int x, int y) { return x % y ? gcd(y, x % y) : y; } int main() { n = read(); for (int i = 1; i <= n; i++) { g[i].x = read(); g[i].y = read(); } for (int i = 1; i <= n; i++) { memset(f, 0, sizeof f); a.x = (g[i].x + 3) % 4 + 1; a.y = (g[i].y + 3) % 4 + 1; for (int j = 1; j <= n; j++) { if (i != j) { if (abs(g[i].x - g[j].x) * abs(g[i].y - g[j].y)) { f[(g[j].x + 3) % 4 + 1][(g[j].y + 3) % 4 + 1] [(gcd(abs(g[i].x - g[j].x), abs(g[i].y - g[j].y)) + 3) % 4 + 1]++; } else { f[(g[j].x + 3) % 4 + 1][(g[j].y + 3) % 4 + 1] [(abs(g[i].x - g[j].x) + abs(g[i].y - g[j].y) + 3) % 4 + 1]++; } } } for (int j = 0; j < 16; j++) { b.x = j / 4 + 1; b.y = j % 4 + 1; for (b.w = 1; b.w <= 4; b.w++) { now1 = f[b.x][b.y][b.w]; f[b.x][b.y][b.w]--; for (int k = 0; k < 16; k++) { c.x = k / 4 + 1; c.y = k % 4 + 1; S = a.x * (b.y - c.y) + b.x * (c.y - a.y) + c.x * (a.y - b.y); if (S & 1) continue; S /= 2; for (c.w = (b.w + 1) % 2 + 1; c.w <= 4; c.w += 2) { now2 = now1 * f[c.x][c.y][c.w]; a.w = gcd(abs(b.x - c.x) + 4, abs(b.y - c.y) + 4); if ((S + (a.w + b.w + c.w) / 2) & 1) continue; if (b.w % 2 + c.w % 2) { ans1 += now2; } else { ans2 += now2; } } } f[b.x][b.y][b.w]++; } } } writeln(ans1 / 2 + ans2 / 6); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; int st[maxn << 2]; int a[maxn], b[maxn]; vector<int> pos[maxn]; void build(int id, int l, int r) { if (l == r) { st[id] = a[l]; return; } int mid = (l + r) >> 1; build(id << 1, l, mid); build(id << 1 | 1, mid + 1, r); st[id] = min(st[id << 1], st[id << 1 | 1]); } void update(int id, int l, int r, int u, int val) { if (l > u || r < u) return; if (l == r) { st[id] = val; return; } int mid = (l + r) >> 1; update(id << 1, l, mid, u, val); update(id << 1 | 1, mid + 1, r, u, val); st[id] = min(st[id << 1], st[id << 1 | 1]); } int GetMin(int id, int l, int r, int u, int v) { if (l > v || r < u) return 1e9; if (u <= l && r <= v) return st[id]; int mid = (l + r) >> 1; return min(GetMin(id << 1, l, mid, u, v), GetMin(id << 1 | 1, mid + 1, r, u, v)); } string Solve() { int n; cin >> n; for (int i = (1), _b = (n); i <= _b; ++i) pos[i].clear(); for (int i = (1), _b = (n); i <= _b; ++i) cin >> a[i]; for (int i = (n), _b = (1); i >= _b; --i) pos[a[i]].push_back(i); for (int i = (1), _b = (n); i <= _b; ++i) cin >> b[i]; build(1, 1, n); int l = 1; for (int i = (1), _b = (n); i <= _b; ++i) { if (pos[b[i]].empty()) return NO ; int nxt = pos[b[i]].back(); pos[b[i]].pop_back(); if (GetMin(1, 1, n, l, nxt) != b[i]) return NO ; update(1, 1, n, nxt, 1e9); } return YES ; } int main() { iostream::sync_with_stdio(false); cin.tie(0); int q; cin >> q; for (int i = (1), _b = (q); i <= _b; ++i) cout << Solve() << n ; return 0; } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_output1 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 31: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 31: 0] data_out;
wire [ 31: 0] out_port;
wire [ 31: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; string s, t; int dp[1005][1005]; int solve(int i, int j) { if (i == s.size()) return t.size() - j; if (j == t.size()) return s.size() - i; if (dp[i][j] != -1) return dp[i][j]; if (s[i] == t[j]) return solve(i + 1, j + 1); int c1 = solve(i + 1, j + 1) + 1; int c2 = solve(i, j + 1) + 1; int c3 = solve(i + 1, j) + 1; return dp[i][j] = (min(c1, min(c2, c3))); } int shft1 = 0; void print(int i, int j) { if (i == s.size()) { for (int xx = j; xx < t.size(); xx++) { cout << INSERT << 1 + xx << << t[xx] << endl; } return; } if (j == t.size()) { for (int xx = 0; xx < s.size() - i; xx++) { cout << DELETE << j + 1 << endl; } return; } int c = -2; if (s[i] == t[j]) { return print(i + 1, j + 1); } int c1 = solve(i + 1, j + 1) + 1; int c2 = solve(i, j + 1) + 1; int c3 = solve(i + 1, j) + 1; int optimal = solve(i, j); if (optimal == c1) { cout << REPLACE << j + 1 << << t[j] << endl; print(i + 1, j + 1); } else if (optimal == c2) { cout << INSERT << j + 1 << << t[j] << endl; shft1++; print(i, j + 1); } else if (optimal == c3) { cout << DELETE << j + 1 << << endl; shft1--; print(i + 1, j); } } int main() { cin >> s >> t; memset(dp, -1, sizeof dp); cout << solve(0, 0) << endl; print(0, 0); return 0; } |
#include <bits/stdc++.h> using namespace std; double eps = 1e-12; const int MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; const double PI = acos(-1.0); const int MAXN = 1; double l, v1, v2; int n, k; bool Judge(double m) { double t = (l - m * v1) / (v2 - v1); if (t < 0) return false; double pos = 0, lim = 0; int sum = n; while (sum > 0) { sum -= k; lim = pos + v2 * t; pos += 2 * v2 * v1 / (v2 + v1) * t; } if (lim <= l) return true; return false; } int main(int argc, char const *argv[]) { cin >> n >> l >> v1 >> v2 >> k; double lb = l / v2 - eps, ub = l / v1 + eps; for (int c = 1; c <= 300; ++c) { double m = (lb + ub) / 2.0; if (Judge(m)) ub = m; else lb = m; } printf( %.12f n , ub); return 0; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long mod(long long n, long long m) { long long ret = n % m; if (ret < 0LL) ret += m; return ret; } long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long exp(long long a, long long b, long long m) { if (b == 0LL) return 1LL; if (b == 1LL) return mod(a, m); long long k = mod(exp(a, b / 2, m), m); if (b & 1LL) { return mod(a * mod(k * k, m), m); } else return mod(k * k, m); } const long long MAXN = 300100; long long res[MAXN]; pair<long long, long long> P[MAXN]; long long dist(pair<long long, long long> a, pair<long long, long long> b) { return abs(a.first - b.first) + abs(a.second - b.second); } long long n; long long dp[MAXN][3][4][4]; const long long inf = 2e9; long long solve(long long id, long long j, long long xo, long long yo) { if (j == 3) { if (xo == 3 && yo == 3) return 0; return -inf; } if (id == n + 1) { return -inf; } long long &x = dp[id][j][xo][yo]; if (x != -1) return x; x = 0; long long op0 = solve(id + 1, j, xo, yo); x = op0; for (long long it1 = 0; it1 <= 2; it1++) { for (long long it2 = 0; it2 <= 2; it2++) { long long sum1 = it1 * P[id].first - (2 - it1) * P[id].first; long long sum2 = it2 * P[id].second - (2 - it2) * P[id].second; if (it1 + xo <= 3 && it2 + yo <= 3) { x = max(x, sum1 + sum2 + solve(id + 1, j + 1, xo + it1, yo + it2)); } } } return x; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i <= n; i++) { cin >> P[i].first >> P[i].second; } memset(dp, -1, sizeof(dp)); long long tot = 0; for (long long i = 1; i <= n; i++) { tot += dist(P[i], P[(i == n ? 1 : i + 1)]); } cout << solve(1, 0, 0, 0) << ; for (long long i = 4; i <= n; i++) cout << tot << ; cout << n ; } |
#include <bits/stdc++.h> using namespace std; int n; int ans; bool one, two, three; vector<int> v; int main() { scanf( %d , &n); while (one == false || two == false || three == false) { for (int i = 1; i <= n; i++) { if (!one) { if (i % 2 == 0) { ans++; v.push_back(i); } if ((n % 2 == 0 && i == n) || (n % 2 != 0 && i == n - 1)) { one = true; break; } } else if (!two) { if (i % 2 != 0) { ans++; v.push_back(i); } if ((n % 2 != 0 && i == n) || (n % 2 == 0 && i == n - 1)) { two = true; break; } } else if (!three) { if (i % 2 == 0) { ans++; v.push_back(i); } if ((n % 2 == 0 && i == n) || (n % 2 != 0 && i == n - 1)) { three = true; goto A; } } } } A: printf( %d n , ans); for (int i = 0; i < v.size(); i++) { printf( %d , v[i]); } } |
module LCDCONTROL (
input CLK, RST,
input WRITE,
input [8:0] WRDATA,
output reg STATUS,
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA // LCD Data bus 8 bits
);
reg [8:0] cmd;
reg [4:0] en_cnt;
reg [17:0] wait_cnt;
wire st;
wire busy;
reg rst_dly;
reg [19:0] dly_cnt;
assign LCD_RW = 1'b0; // always write
assign LCD_BLON = 1'b1; // Backlight on
assign LCD_RS = cmd[8];
assign LCD_DATA = cmd[7:0];
assign LCD_EN = (en_cnt!=0) ? 1'b1 : 1'b0;
assign st = (WRITE==1 && busy==0) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge RST)
begin
if (RST) begin
dly_cnt <= 20'h0;
rst_dly <= 1'b1;
end
else if (dly_cnt!=20'hFFFFF)
begin
dly_cnt <= dly_cnt + 20'h1;
rst_dly <= 1'b1;
end
else
begin
rst_dly <= 1'b0;
end
end
always @(posedge CLK or posedge RST)
begin
if (RST)
cmd <= 9'h0;
else if (rst_dly)
cmd <= 9'h0;
else if (st)
cmd <= WRDATA[8:0];
end
always @(posedge CLK or posedge RST)
begin
if (RST)
en_cnt <= 5'h0;
else if (rst_dly)
en_cnt <= 5'h0;
else if (st)
en_cnt <= 5'h10;
else if (en_cnt!=5'h0)
en_cnt <= en_cnt - 5'h1;
end
always @(posedge CLK or posedge RST)
begin
if (RST)
wait_cnt <= 18'h00000;
else if (rst_dly)
wait_cnt <= 18'h00000;
else if (en_cnt == 5'h1)
wait_cnt <= 18'h3FFFF; // this should be changed depending on the command
else if (wait_cnt!=18'h0)
wait_cnt <= wait_cnt - 18'h1;
end
assign busy = (en_cnt==5'h0 && wait_cnt==18'h0) ? 1'b0 : 1'b1;
always @(posedge CLK or posedge RST)
begin
if (RST)
STATUS <= 1'b1;
else if (rst_dly)
STATUS <= 1'b1;
else
STATUS <= st | busy;
end
endmodule
|
#include <bits/stdc++.h> constexpr int Maxn = 2e5 + 7; constexpr int Maxm = 1e6 + 7; constexpr int Mod = 1e9 + 7; int n, k, sum, root; void add(int bit[], int p, int v) { for (; p < Maxn; p += p & -p) bit[p] = (bit[p] + v) % Mod; } int query(int bit[], int p) { int res = 0; for (; p; p -= p & -p) res = (res + bit[p]) % Mod; return res; } struct Edge { int nxt, to, w; } e[Maxn << 1]; int head[Maxn], edge_cnt, res; inline void add_edge(int u, int v, int w) { e[++edge_cnt].to = v; e[edge_cnt].nxt = head[u]; e[edge_cnt].w = w; head[u] = edge_cnt; } int a[Maxn], siz[Maxn], f[Maxn]; int del[Maxn]; void getroot(int u, int fa) { siz[u] = 1; f[u] = 0; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (!del[v] && v != fa) { getroot(v, u); siz[u] += siz[v]; f[u] = std::max(f[u], siz[v]); } } f[u] = std::max(f[u], sum - siz[u]); if (f[u] < f[root]) root = u; } int val[2][Maxn], num[2][Maxn]; void DFS(int u, int fa, int rcol, int col, int nxt, int tot, int opt) { tot = (tot + a[u]) % Mod; if (opt == 0) { if (k >= nxt) { int cnt = query(num[rcol], k - nxt + 1); int cur = query(val[rcol], k - nxt + 1); res = (res + 1LL * cnt * tot % Mod) % Mod; res = (res + cur) % Mod; } if (k >= nxt + 1) { int cnt = query(num[rcol ^ 1], k - nxt); int cur = query(val[rcol ^ 1], k - nxt); res = (res + 1LL * cnt * tot % Mod) % Mod; res = (res + cur) % Mod; } if (k >= nxt) res = (res + tot) % Mod; } else if (opt == 1) { add(num[rcol], nxt + 1, 1); add(val[rcol], nxt + 1, tot); } else { add(num[rcol], nxt + 1, Mod - 1); add(val[rcol], nxt + 1, Mod - tot); } for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to, w = e[i].w; if (del[v] || v == fa) continue; int nxtstp = nxt; if (w != col) ++nxtstp; DFS(v, u, rcol, w, nxtstp, tot, opt); } } void solve(int u) { del[u] = 1; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to, w = e[i].w; if (!del[v]) { DFS(v, u, w, w, 0, a[u], 0); DFS(v, u, w, w, 0, 0, 1); } } for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to, w = e[i].w; if (!del[v]) DFS(v, u, w, w, 0, 0, -1); } for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (!del[v]) { root = 0, sum = siz[v]; getroot(v, 0); solve(root); } } } int main() { scanf( %d%d , &n, &k); f[0] = sum = n; for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1, u, v, w; i <= n - 1; ++i) { scanf( %d%d%d , &u, &v, &w); add_edge(u, v, w), add_edge(v, u, w); } getroot(1, 0); solve(root); for (int i = 1; i <= n; ++i) res = (res + a[i]) % Mod; printf( %d n , res); } |
#include <bits/stdc++.h> int main() { int i, l, j; char t; char kb[100] = qwertyuiopasdfghjkl;zxcvbnm,./ ; char s[1000]; scanf( %c , &t); scanf( %s , s); l = strlen(s); for (i = 0; i < l; i++) { for (j = 0; j < 30; j++) { if (kb[j] == s[i]) { if (t == R ) { printf( %c , kb[j - 1]); } else if (t == L ) { printf( %c , kb[j + 1]); } } } } } |
#include <bits/stdc++.h> using namespace std; int maze[1500][1500]; pair<int, int> was[1500][1500]; int n, m; int sr, sc; inline int rem(int x, int y) { x %= y; return (x < 0) ? x + y : x; } bool dfs(int r, int c) { int rm = rem(r, n), cm = rem(c, m); if (maze[rm][cm] == 1) { return was[rm][cm] != pair<int, int>(r, c); } int rmn, cmn; if (maze[rm][cm] == 0) { maze[rm][cm] = 1; was[rm][cm] = pair<int, int>(r, c); rmn = rem(r, n), cmn = rem(c - 1, m); if (maze[rmn][cmn] != -1 && dfs(r, c - 1)) return true; rmn = rem(r, n), cmn = rem(c + 1, m); if (maze[rmn][cmn] != -1 && dfs(r, c + 1)) return true; rmn = rem(r + 1, n), cmn = rem(c, m); if (maze[rmn][cmn] != -1 && dfs(r + 1, c)) return true; rmn = rem(r - 1, n), cmn = rem(c, m); if (maze[rmn][cmn] != -1 && dfs(r - 1, c)) return true; } return false; } void TheSolution(istream& input, ostream& output) { input >> n >> m; string s; memset(maze, -1, sizeof(maze)); for (int i = 0; i < n; i++) { input >> s; for (int j = 0; j < m; j++) { if (s[j] == . ) maze[i][j] = 0; if (s[j] == S ) { sr = i; sc = j; maze[i][j] = 0; } was[i][j] = pair<int, int>(-1000000, -1000000); } } output << (dfs(sr, sc) ? Yes : No ); } int main() { TheSolution(cin, cout); return 0; } |
#include <bits/stdc++.h> using namespace std; const int limit = 320; int v[100000]; int dp[limit][100000]; int n; static int bruteforce(int p, int k) { int cnt = 0; while (p < n) { cnt++; p = p + v[p] + k; } return cnt; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> v[i]; for (int j = 1; j < limit; j++) { for (int i = n - 1; i >= 0; i--) { if (i + j + v[i] >= n) dp[j][i] = 1; else dp[j][i] = 1 + dp[j][i + j + v[i]]; } } int q; cin >> q; for (int i = 0, p, k; i < q; ++i) { cin >> p >> k; --p; if (k < limit) cout << dp[k][p] << n ; else cout << bruteforce(p, k) << n ; } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; long long a[MAXN], b[MAXN]; long long n, s; bool check(long long k) { for (int i = 1; i <= n; i++) b[i] = 0; long long sum = s - 1, p = 2, q = 1, h = 1; a[1] = b[1] = 1; while (p <= n) { q *= k, h++; for (int i = 1; i <= q && p <= n; i++, p++) a[p] = h, sum -= h, b[h]++; } if (sum < 0) return 0; p = n; while (sum > 0) { h++; if (b[a[p]] == 1) --p; long long t = min(sum, h - a[p]); sum -= t, b[a[p]]--, a[p] += t, p--; } return 1; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> s; if (s < 2 * n - 1 || s > n * (n + 1) / 2) { cout << No << endl; exit(0); } int l = 1, r = n - 1; while (l < r) { int m = (l + r) >> 1; if (check(m)) r = m; else l = m + 1; } check(l); sort(a + 1, a + n + 1); cout << Yes << endl; for (int p = 1, i = 2, cnt = 0; i <= n; i++) { while (a[p] < a[i] - 1) p++, cnt = 0; cout << p << ; ++cnt; if (cnt == l) cnt = 0, ++p; } cout << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_jump_pixel/pikachu_jump_pixel_stub.v
// Design : pikachu_jump_pixel
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module pikachu_jump_pixel(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [12:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch <= 9 && ch >= 0 ) { x = 10 * x + ch - 0 ; ch = getchar(); } return x * f; } void print(int x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) print(x / 10); putchar(x % 10 + 0 ); } const int N = 200100, inf = 0X3f3f3f3f; int last[N], ecnt; struct EDGE { int to, nt; } e[N]; inline void add(int u, int v) { e[++ecnt] = (EDGE){v, last[u]}; last[u] = ecnt; } int n; int dep[N], anc[N][20], low[N][20]; int time_in[N], time_out[N], tim; void dfs(int u) { time_in[u] = ++tim; for (int i = 1; (1 << i) <= dep[u]; ++i) anc[u][i] = anc[anc[u][i - 1]][i - 1]; for (int i = last[u]; i; i = e[i].nt) dfs(e[i].to); time_out[u] = tim; } inline int getlca(int u, int v) { if (dep[u] < dep[v]) swap(u, v); int len = dep[u] - dep[v]; for (int i = 0; (1 << i) <= len; ++i) if ((1 << i) & len) u = anc[u][i]; if (u == v) return u; for (int i = 18; ~i; --i) if (anc[u][i] != anc[v][i]) u = anc[u][i], v = anc[v][i]; return anc[u][0]; } inline void update(int &x, int y) { if (dep[y] < dep[x]) x = y; } struct node { int x, y, pos; friend bool operator<(const node &a, const node &b) { return a.x == b.x ? a.pos < b.pos : a.x < b.x; } } q[N << 3]; int tot; int bit[N]; inline void modify(int x) { for (; x <= n; x += (x & -x)) bit[x]++; } inline int query(int x) { int res(0); for (; x; x -= (x & -x)) res += bit[x]; return res; } int ans[N], cur[N]; bool book[N]; int main() { n = read(); int m, Q; register int i, j, u, v, grd; for (i = 2; i <= n; ++i) u = anc[i][0] = read(), dep[i] = dep[u] + 1, add(u, i); dfs(1); m = read(); for (i = 1; i <= n; ++i) low[i][0] = i; for (i = 1; i <= m; ++i) u = read(), v = read(), grd = getlca(u, v), update(low[u][0], grd), update(low[v][0], grd), q[++tot] = (node){time_in[u], time_in[v], -inf}, q[++tot] = (node){time_in[v], time_in[u], -inf}; for (i = n; i > 1; --i) update(low[anc[i][0]][0], low[i][0]); for (i = 1; i <= 18; ++i) for (u = 1; u <= n; ++u) low[u][i] = low[low[u][i - 1]][i - 1]; Q = read(); for (i = 1; i <= Q; ++i) { u = read(), v = read(), grd = getlca(u, v); if (dep[low[u][18]] > dep[grd] || dep[low[v][18]] > dep[grd]) { ans[i] = -1; continue; } for (j = 18; ~j; --j) if (dep[low[u][j]] > dep[grd]) u = low[u][j], ans[i] += 1 << j; for (j = 18; ~j; --j) if (dep[low[v][j]] > dep[grd]) v = low[v][j], ans[i] += 1 << j; if (u == grd || v == grd) { ans[i]++; continue; } book[i] = 1; q[++tot] = (node){time_in[u] - 1, time_in[v] - 1, i}; q[++tot] = (node){time_in[u] - 1, time_out[v], -i}; q[++tot] = (node){time_out[u], time_in[v] - 1, -i}; q[++tot] = (node){time_out[u], time_out[v], i}; } sort(q + 1, q + 1 + tot); for (i = 1; i <= tot; ++i) if (q[i].pos == -inf) modify(q[i].y); else q[i].pos > 0 ? cur[q[i].pos] += query(q[i].y) : cur[-q[i].pos] -= query(q[i].y); for (i = 1; i <= Q; ++i) { if (cur[i]) ans[i]++; else if (book[i]) ans[i] += 2; print(ans[i]), puts( ); } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dist_mem_gen_v7_2.v when simulating
// the core, dist_mem_gen_v7_2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dist_mem_gen_v7_2(
a,
spo
);
input [13 : 0] a;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(14),
.C_DEFAULT_DATA("0"),
.C_DEPTH(16384),
.C_FAMILY("spartan6"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("dist_mem_gen_v7_2.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32)
)
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, sz[100005], msz[100005], xsz[100005], lsz[100005], son[100005], ans[100005]; vector<int> G[100005]; void dfs(int u) { sz[u] = 1; lsz[u] = n; son[u] = -1; for (int v : G[u]) { dfs(v), sz[u] += sz[v]; if (son[u] == -1 || sz[v] > sz[son[u]]) son[u] = v; if (sz[v] > msz[u]) xsz[u] = msz[u], msz[u] = sz[v]; else xsz[u] = max(xsz[u], sz[v]); lsz[u] = min(lsz[u], sz[v]); } if (n - sz[u] > msz[u]) xsz[u] = msz[u], msz[u] = n - sz[u]; else xsz[u] = max(xsz[u], n - sz[u]); if (n - sz[u]) lsz[u] = min(lsz[u], n - sz[u]); } multiset<int> st, st2; void ser1(int u) { st.insert(sz[u]); for (int v : G[u]) ser1(v); } void dfs1(int u) { for (int v : G[u]) if (v != son[u]) { dfs1(v); st.clear(); } if (son[u] != -1) dfs1(son[u]); if (n - sz[u] != msz[u]) { int L = xsz[u], R = msz[u], mid; for (; L < R;) { mid = L + R >> 1; multiset<int>::iterator it = st.lower_bound(msz[u] - mid); if (it != st.end() && (*it) <= mid - lsz[u]) R = mid; else L = mid + 1; } ans[u] = L; } for (int v : G[u]) if (v != son[u]) ser1(v); st.insert(sz[u]); } void ser2(int u) { st.erase(st.find(sz[u])); for (int v : G[u]) ser2(v); } void dfs2(int u) { st.erase(st.find(sz[u])); for (int v : G[u]) if (v != son[u]) { st2.insert(sz[u]); dfs2(v); ser1(v); st2.erase(st2.find(sz[u])); } if (son[u] != -1) { int v = son[u]; st2.insert(sz[u]); dfs2(v); st2.erase(st2.find(sz[u])); } for (int v : G[u]) if (v != son[u]) ser2(v); if (n - sz[u] == msz[u]) { int L = xsz[u], R = msz[u], mid; for (; L < R;) { mid = L + R >> 1; multiset<int>::iterator it = st.lower_bound(msz[u] - mid), it2 = st2.lower_bound(msz[u] - mid + sz[u]); if (it != st.end() && (*it) <= mid - lsz[u]) R = mid; else if (it2 != st2.end() && (*it2) <= mid - lsz[u] + sz[u]) R = mid; else L = mid + 1; } ans[u] = L; } } int main() { scanf( %d , &n); for (int i = (1), LIM = (n); i <= LIM; i++) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); } dfs(0); dfs1(G[0][0]); dfs2(G[0][0]); for (int i = (1), LIM = (n); i <= LIM; i++) printf( %d n , ans[i]); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_2_V
`define SKY130_FD_SC_LS__OR3_2_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_2_V
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
/* Make the ECC on erased flash be all 1's */
module bch_blank_ecc #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* First cycle */
input ce, /* Accept input word/cycle output word */
output [BITS-1:0] xor_out,
output first, /* First output cycle */
output last /* Last output cycle */
);
`include "bch.vh"
`include "bch_encode.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam EB = `BCH_ECC_BITS(P);
localparam ECC_WORDS = (EB + BITS - 1) / BITS;
localparam [EB-1:0] ENC = encoder_poly(0);
if (PIPELINE_STAGES > 1)
blank_ecc_only_supports_1_pipeline_stage u_beos1ps();
function [ECC_WORDS*BITS-1:0] erased_ecc;
input dummy;
reg [EB-1:0] lfsr;
begin
lfsr = 0;
repeat (`BCH_DATA_BITS(P))
lfsr = (lfsr << 1) ^ (lfsr[EB-1] ? 0 : ENC);
erased_ecc = ~(lfsr << (ECC_WORDS*BITS - EB));
end
endfunction
localparam [ECC_WORDS*BITS-1:0] ERASED_ECC = erased_ecc(0);
wire _last;
if (ECC_WORDS == 1) begin
assign _last = start;
assign xor_out = ERASED_ECC;
end else if (ECC_WORDS == 2) begin
reg start0 = 0;
always @(posedge clk) begin
if (start)
start0 <= #TCQ start;
else if (ce)
start0 <= #TCQ 0;
end
assign _last = start0;
if (PIPELINE_STAGES > 0) begin
assign xor_out = start0 ? ERASED_ECC[BITS+:BITS] :
ERASED_ECC[0+:BITS];
end else
assign xor_out = start ? ERASED_ECC[BITS+:BITS] :
ERASED_ECC[0+:BITS];
end else begin
reg [(ECC_WORDS-1)*BITS-1:0] ecc_xor = ERASED_ECC;
wire [$clog2(ECC_WORDS+1)-1:0] count;
assign _last = count == 0;
counter #(ECC_WORDS, ECC_WORDS - 2, -1) u_counter(
.clk(clk),
.reset(start),
.ce(ce),
.count(count)
);
if (PIPELINE_STAGES > 0) begin
/* Add registered outputs to distributed RAM */
reg [BITS-1:0] xor_bits = ERASED_ECC[(ECC_WORDS-1)*BITS+:BITS];
always @(posedge clk) begin
if (start)
xor_bits <= #TCQ ERASED_ECC[(ECC_WORDS-1)*BITS+:BITS];
else if (ce)
xor_bits <= #TCQ ecc_xor[count*BITS+:BITS];
end
assign xor_out = xor_bits;
end else
assign xor_out = start ?
ERASED_ECC[(ECC_WORDS-1)*BITS+:BITS] :
ecc_xor[count*BITS+:BITS];
end
pipeline_ce #(PIPELINE_STAGES > 0) u_control_pipeline [1:0] (
.clk(clk),
.ce(ce || start),
.i({start, _last}),
.o({first, last})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:100000000 ) int matrix[900][900]; int tmp[900][900]; int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; vector<pair<int, int> > all; void go(int x, int y) { queue<pair<int, int> > q; tmp[x][y] = 1; q.push(make_pair(x, y)); all.push_back(make_pair(x, y)); while (!q.empty()) { x = q.front().first; y = q.front().second; q.pop(); for (int i = 0; i < 4; i++) { if (x + dx[i] >= 0 && x + dx[i] <= 799 && y + dy[i] >= 0 && y + dy[i] <= 799) { if (matrix[x + dx[i]][y + dy[i]] != 255 && tmp[x + dx[i]][y + dy[i]] == 0) { tmp[x + dx[i]][y + dy[i]] = 1; q.push(make_pair(x + dx[i], y + dy[i])); all.push_back(make_pair(x + dx[i], y + dy[i])); } } } } } vector<int> path; int cnt = 0; void bfs(int x1, int y1, int x2, int y2) { for (int i = 0, maxi = (int)(all).size(); i < maxi; i++) { int x = all[i].first; int y = all[i].second; tmp[x][y] = 0; } all.clear(); path.clear(); cnt = 0; queue<pair<int, int> > q; q.push(make_pair(x1, y1)); tmp[x1][y1] = 111; all.push_back(make_pair(x1, y1)); while (!q.empty()) { for (int i = 0, maxi = (int)(q).size(); i < maxi; i++) { int x = q.front().first; int y = q.front().second; q.pop(); if (x == x2 && y == y2) { cnt = 0; while (x != x1 || y != y1) { int j = tmp[x][y] - 1; cnt++; path.push_back(j); x = x - dx[j]; y = y - dy[j]; } return; } for (int j = 0; j < 4; j++) { if (x + dx[j] >= 0 && x + dx[j] <= 799 && y + dy[j] >= 0 && y + dy[j] <= 799) { if (matrix[x + dx[j]][y + dy[j]] != 255 && tmp[x + dx[j]][y + dy[j]] == 0) { tmp[x + dx[j]][y + dy[j]] = j + 1; q.push(make_pair(x + dx[j], y + dy[j])); all.push_back(make_pair(x + dx[j], y + dy[j])); } } } } } } string ans = ; int main() { int x1, y1, x2, y2; scanf( %d %d %d %d , &x1, &y1, &x2, &y2); x1 += 400; y1 += 400; x2 += 400; y2 += 400; int m; scanf( %d , &m); int max_x = 0, min_x = 800, max_y = 0, min_y = 800; for (int i = 0; i < m; i++) { int x, y; scanf( %d %d , &x, &y); x += 400; y += 400; min_x = min(min_x, x); max_x = max(max_x, x); min_y = min(min_y, y); max_y = max(max_y, y); matrix[x][y] = 255; } go(x1, y1); if (m == 0 || tmp[x1][y1] != tmp[x2][y2]) { printf( -1 ); return 0; } while (true) { bfs(x1, y1, x2, y2); reverse(path.begin(), path.end()); for (int i = 0; i < cnt; i++) { if (path[i] == 0) ans += R ; else if (path[i] == 1) ans += U ; else if (path[i] == 2) ans += L ; else if (path[i] == 3) ans += D ; int j = path[i]; x1 += dx[j]; y1 += dy[j]; if (matrix[x2 + dx[j]][y2 + dy[j]] != 255) { x2 += dx[j]; y2 += dy[j]; path.push_back(j); cnt++; } if (min(y1, y2) > max_y || max(y1, y2) < min_y || min(x1, x2) > max_x || max(x1, x2) < min_x || x1 == x2 && y1 == y2) break; } if (x1 == x2 && y1 == y2) { cout << ans; return 0; } bool flag = false; if (min(y1, y2) > max_y) { if (max(x1, x2) >= min_x) { int diff = max(x1, x2) - min_x + 1; x1 -= diff; x2 -= diff; for (int i = 0; i < diff; i++) ans += L ; } if (max(y1, y2) >= min_y) { int diff = max(y1, y2) - min_y + 1; y1 -= diff; y2 -= diff; for (int i = 0; i < diff; i++) ans += D ; } flag = true; } else if (max(y1, y2) < min_y) { if (max(x1, x2) >= min_x) { int diff = max(x1, x2) - min_x + 1; x1 -= diff; x2 -= diff; for (int i = 0; i < diff; i++) ans += L ; } if (max(y1, y2) >= min_y) { int diff = max(y1, y2) - min_y + 1; y1 -= diff; y2 -= diff; for (int i = 0; i < diff; i++) ans += D ; } flag = true; } else if (min(x1, x2) > max_x) { if (max(y1, y2) >= min_y) { int diff = max(y1, y2) - min_y + 1; y1 -= diff; y2 -= diff; for (int i = 0; i < diff; i++) ans += D ; } if (max(x1, x2) >= min_x) { int diff = max(x1, x2) - min_x + 1; x1 -= diff; x2 -= diff; for (int i = 0; i < diff; i++) ans += L ; } flag = true; } else if (max(x1, x2) < min_x) { if (max(y1, y2) >= min_y) { int diff = max(y1, y2) - min_y + 1; y1 -= diff; y2 -= diff; for (int i = 0; i < diff; i++) ans += D ; } if (max(x1, x2) >= min_x) { int diff = max(x1, x2) - min_x + 1; x1 -= diff; x2 -= diff; for (int i = 0; i < diff; i++) ans += L ; } flag = true; } if (flag) { if (y2 > y1) { int y = min_y; int x; for (int i = 290; i < 510; i++) { if (matrix[i][y] == 255) { x = i; break; } } if (x2 < x) { int diff = x - x2; x1 += diff; x2 += diff; for (int i = 0; i < diff; i++) ans += R ; } if (y2 != y1) { int diff = y - y1 - 1; y2 = y - 1; y1 = y2; for (int i = 0; i < diff; i++) ans += U ; } } else { if (min(y1, y2) <= max_y) { int diff = max_y - min(y1, y2) + 1; y1 += diff; y2 += diff; for (int i = 0; i < diff; i++) ans += U ; } int y = max_y; int x; for (int i = 290; i < 510; i++) { if (matrix[i][y] == 255) { x = i; break; } } if (x2 < x) { int diff = x - x2; x1 += diff; x2 += diff; for (int i = 0; i < diff; i++) ans += R ; } if (y2 != y1) { int diff = y1 - y - 1; y1 -= diff; y2 = y + 1; for (int i = 0; i < diff; i++) ans += D ; } } if (x2 > x1) { if (max(x1, x2) >= min_x) { int diff = max(x1, x2) - min_x + 1; x2 -= diff; x1 -= diff; for (int i = 0; i < diff; i++) ans += L ; } if (max(y1, y2) >= min_y) { int diff = max(y1, y2) - min_y + 1; y2 -= diff; y1 -= diff; for (int i = 0; i < diff; i++) ans += D ; } int x = min_x; int y; for (int i = 290; i < 510; i++) { if (matrix[x][i] == 255) { y = i; break; } } if (y1 < y) { int diff = y - y1; y1 += diff; y2 += diff; for (int i = 0; i < diff; i++) ans += U ; } if (x2 != x1) { int diff = x - x1 - 1; x1 += diff; x2 = x - 1; for (int i = 0; i < diff; i++) ans += R ; } cout << ans; return 0; } else { if (min(x1, x2) <= max_x) { int diff = max_x - min(x1, x2) + 1; x1 += diff; x2 += diff; for (int i = 0; i < diff; i++) ans += R ; } if (max(y1, y2) >= min_y) { int diff = max(y1, y2) - min_y + 1; y2 -= diff; y1 -= diff; for (int i = 0; i < diff; i++) ans += D ; } int x = max_x; int y; for (int i = 290; i < 510; i++) { if (matrix[x][i] == 255) { y = i; break; } } if (y1 < y) { int diff = y - y1; y1 += diff; y2 += diff; for (int i = 0; i < diff; i++) ans += U ; } while (x2 != x1) { int diff = x1 - x - 1; x1 -= diff; x2 = x + 1; for (int i = 0; i < diff; i++) ans += L ; } cout << ans; return 0; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int f[100][300] = {0}; int main() { std::ios::sync_with_stdio(false); string s1, s2; cin >> s1 >> s2; int t1 = 0, t2 = 0, q = 0; for (int i = 0; i < s1.length(); i += 1) { if (s1[i] == + ) t1++; else t1--; } for (int i = 0; i < s2.length(); i += 1) { if (s2[i] == + ) t2++; else if (s2[i] == - ) t2--; else q++; } int w = t1 - t2; int dta = 20; f[0][dta] = 1; for (int i = 1; i <= q; i += 1) { for (int j = -10; j <= 10; j += 1) { f[i][j + dta] = f[i - 1][j + dta - 1] + f[i - 1][j + dta + 1]; } } double ans = f[q][w + dta] / double(1 << q); cout << fixed << setprecision(12) << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVGND_PP_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1000000 + 10; const int Mod = 998244353; const int alp = 3; int n, S; int C[MAX]; int dp[MAX]; namespace opt { int N; int a[MAX], b[MAX], w[MAX], tmp[MAX]; int Pow(int a, int b) { int k = 1; for (; b; b /= 2, a = (long long)a * a % Mod) if (b % 2 == 1) k = (long long)k * a % Mod; return k; } void FFT(int *a, int S, int d) { if (d == N) return; FFT(a, S, d << 1); FFT(a, S + d, d << 1); for (int i = S, j = S, p = 0; i < N / 2; i += d, j += d << 1, p += d) { int G = a[j], K = a[j + d]; tmp[i] = ((long long)G + (long long)w[p] * K) % Mod; tmp[i + N / 2] = ((long long)G + (long long)w[p + N / 2] * K) % Mod; } for (int i = S; i < N; i += d) a[i] = tmp[i]; } void conv(int *aa, int *bb, int *c, int n) { for (int i = 0; i < n; ++i) a[i] = aa[i], b[i] = bb[i]; if (n <= 500) { for (int i = 0; i < n * 2; ++i) c[i] = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) c[i + j] = (c[i + j] + (long long)a[i] * b[j]) % Mod; for (int i = 0; i < n; ++i) a[i] = b[i] = 0; return; } N = 1; for (; N < n; N <<= 1) ; N <<= 1; w[0] = 1; w[1] = Pow(alp, (Mod - 1) / N); for (int i = 2; i <= N; ++i) w[i] = (long long)w[i - 1] * w[1] % Mod; FFT(a, 0, 1); FFT(b, 0, 1); for (int i = 0; i < N; ++i) a[i] = (long long)a[i] * b[i] % Mod; for (int i = 0; i < N; ++i) b[i] = a[i ? (N - i) : 0]; FFT(b, 0, 1); int InvN = Pow(N, Mod - 2); for (int i = 0; i < N; ++i) { c[i] = (long long)b[i] * InvN % Mod; a[i] = b[i] = 0; } } } // namespace opt int a[MAX], b[MAX], c[MAX]; void solve(int l, int r) { if (r == l + 1) return; int mid = (l + r) / 2; solve(l, mid); int i; int need = r - l; for (long long i = 0; i < need; i++) a[i] = b[i] = 0; if (l > 0) { for (long long i = 0; i < mid - l; i++) a[i] = dp[i + l]; for (long long i = 0; i < need; i++) b[i] = dp[i]; opt::conv(a, b, c, need); for (long long i = 0; i < need; i++) { c[i] *= 2; if (c[i] >= Mod) c[i] -= Mod; } } else { for (long long i = 0; i < mid - l; i++) a[i] = b[i] = dp[i + l]; opt::conv(a, b, c, need); } for (long long i = 0; i < need; i++) { a[i] = c[i]; b[i] = C[i]; } opt::conv(a, b, c, need); for (long long i = mid; i < r; i++) { dp[i] += c[i - l]; if (dp[i] >= Mod) dp[i] -= Mod; } solve(mid, r); } int main() { int i; scanf( %d%d , &n, &S); for (long long i = 1; i <= n; i++) { int a; scanf( %d , &a); C[a] = 1; } int N = 1; for (; N <= S; N *= 2) ; dp[0] = 1; solve(0, N); for (long long i = 1; i <= S; i++) printf( %d n , dp[i]); return 0; } |
#include <bits/stdc++.h> inline int read() { char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); int k = 0, kk = 1; if (c == - ) c = getchar(), kk = -1; while (c >= 0 && c <= 9 ) k = k * 10 + c - 0 , c = getchar(); return kk * k; } using namespace std; void write(int x) { if (x < 0) x = -x, putchar( - ); if (x / 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(int x) { write(x); puts( ); } int n, m, k, x[1000000], y[1000000], l[1000000], r[1000000], f[1000000]; struct lsg { int x, y, d, bj; } a[1000000], ff[1000000]; bool cmp1(lsg x, lsg y) { return x.d < y.d; } bool cmp2(lsg x, lsg y) { return x.x < y.x; } bool cmp3(lsg x, lsg y) { return x.y > y.y; } bool pd(int kkk) { int d = 0, dd = 0, ddd = 0; memset(a, 0, sizeof(a)); for (int i = 1; i <= k; i++) { a[++d].d = x[i] - kkk; a[d].x = y[i] - kkk; a[d].y = y[i] + kkk; a[d].bj = i; a[++d].d = x[i] + kkk + 1; a[d].bj = -i; } a[++d].d = 1; a[++d].d = n; sort(a + 1, a + 1 + d, cmp1); a[d + 1].d = -1e9; for (int i = 1; i <= d; i++) { if (a[i].bj > 0) { ff[++dd].x = a[i].x; ff[dd].y = a[i].y; ff[dd].bj = a[i].bj; } else if (a[i].bj < 0) { int kk = 0; for (int j = 1; j <= dd; j++) if (ff[j].bj != -a[i].bj) ff[++kk] = ff[j]; dd = kk; } if (a[i].d != a[i + 1].d && a[i].d >= 1 && a[i].d <= n) { sort(ff + 1, ff + 1 + dd, cmp2); l[++ddd] = 1; r[ddd] = m; f[ddd] = a[i].d; for (int j = 1; j <= dd; j++) { if (l[ddd] >= ff[j].x) l[ddd] = max(l[ddd], ff[j].y + 1); } sort(ff + 1, ff + 1 + dd, cmp3); for (int j = 1; j <= dd; j++) { if (r[ddd] <= ff[j].y) r[ddd] = min(r[ddd], ff[j].x - 1); } } } int ll = 1, rr = ddd, lll = m, rrr = 1; f[ddd + 1] = n; f[ddd + 2] = n + 1; while (l[ll] > r[ll] && ll <= rr) ll++; while (l[rr] > r[rr] && ll <= rr) rr--; if (f[rr + 1] - 1 - f[ll] > kkk * 2) return 0; for (int i = ll; i <= rr; i++) lll = min(lll, l[i]), rrr = max(rrr, r[i]); if (rrr - lll > kkk * 2) return 0; return 1; } signed main() { n = read(); m = read(); k = read(); for (int i = 1; i <= k; i++) x[i] = read(), y[i] = read(); int l = 0, r = max(n, m); while (l < r) { int m = (l + r) / 2; if (pd(m)) r = m; else l = m + 1; } cout << l << endl; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(false); cin.tie(0); long long x; cin >> x; for (long long i = 1; i <= x; i++) { for (long long j = i; j <= x; j++) { if (j % i == 0 && i * j > x && j / i < x) { cout << j << << i << endl; return 0; } } } cout << -1 << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; long long A[N]; int n; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> A[i]; int ans = 1; int len = 1; for (int i = 1; i < n; i++) { if (A[i] <= 2 * A[i - 1]) len++, ans = max(len, ans); else len = 1; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[4]; int cur[100005]; void work(int x, int y, int z, int w, int tp) { if (x + z < y + w) return; if (x + z >= y + w + 2) return; int nlen = x + y + z + w; for (int pl = 1; pl <= nlen; pl += 2) { if (x) cur[pl] = 0, x--; else cur[pl] = 2, z--; } for (int pl = 2; pl <= nlen; pl += 2) { if (y) cur[pl] = 1, y--; else cur[pl] = 3, w--; } for (int pl = 1; pl < nlen; pl++) if (abs(cur[pl] - cur[pl + 1]) != 1) return; printf( YES n ); for (int i = 1; i <= nlen; i++) { if (tp) printf( %d , 3 - cur[i]); else printf( %d , cur[i]); } exit(0); } int main() { cin >> a[0] >> a[1] >> a[2] >> a[3]; work(a[0], a[1], a[2], a[3], 0); work(a[3], a[2], a[1], a[0], 1); printf( NO n ); return 0; } |
/*
Single BiQuad IIR Filter. Uses a single DSP block and
Scaling factor = 17-clog2(max(abs(COEFF)))
Multiply COEFFs by 2^SCALING
*/
module BiquadSingle #(
parameter WIDTH_D = 18, // Data path width
parameter WIDTH_C = 18, // Coeffecient bit width
parameter COEFF_B0 = 0, // Coeffecient B0
parameter COEFF_B1 = 0, // Coeffecient B1
parameter COEFF_B2 = 0, // Coeffecient B2
parameter COEFF_A1 = 0, // Coeffecient A1
parameter COEFF_A2 = 0 // Coeffecient A2
)
(
input clk, // System clock
input rst, // Reset, active high & synchronous
input inStrobe, // Strobe on new dataIn
input signed [WIDTH_D-1:0] dataIn, // Input to filter
output reg outStrobe, // Strobes on new dataOut
output signed [WIDTH_D-1:0] dataOut // Output from filter
);
function real AbsMax;
input real a, b;
begin
a = (a < 0) ? -a : a;
b = (b < 0) ? -b : b;
AbsMax = (a > b) ? a : b;
end
endfunction
// Xilinx ISE doesn't like using system calls for localparam, so we use
// parameter here.
parameter SCALING = -1 + $clog2($rtoi(2**(WIDTH_D-1)/
AbsMax(AbsMax(AbsMax(AbsMax(COEFF_B0,
COEFF_B1),
COEFF_B2),
COEFF_A1),
COEFF_A2)));
localparam ST_IDLE = 0;
localparam ST_X_B0 = 1;
localparam ST_X_B1 = 2;
localparam ST_X_B2 = 3;
localparam ST_Y_A1 = 4;
localparam ST_Y_A2 = 5;
// Calculation Engine Registers
reg signed [WIDTH_D-1:0] multInA;
reg signed [WIDTH_C-1:0] multInB;
reg signed [WIDTH_D+WIDTH_C-1:0] multOut;
reg signed [WIDTH_D+WIDTH_C+2:0] adderOut; // Allocate for multiply + 3 bits adder growth
reg signed [WIDTH_D-1:0] y;
reg signed [WIDTH_D-1:0] yD1;
reg signed [WIDTH_D-1:0] x;
reg signed [WIDTH_D-1:0] xD1;
reg signed [WIDTH_D-1:0] xD2;
// State Machine Registers
reg [2:0] state;
reg [2:0] stateD1;
reg [2:0] stateD2;
reg storeY;
// Zero out everything for initialization
initial begin
y = 'd0;
yD1 = 'd0;
x = 'd0;
xD1 = 'd0;
xD2 = 'd0;
multInA = 'd0;
multInB = 'd0;
multOut = 'd0;
adderOut = 'd0;
state = ST_IDLE;
stateD1 = ST_IDLE;
stateD2 = ST_IDLE;
storeY = 1'b0;
outStrobe = 1'b0;
end
assign dataOut = y;
// Calculation Engine - Should infer to DSP48 in Xilinx
always @(posedge clk) begin
if (rst) begin
y <= 'd0;
yD1 <= 'd0;
x <= 'd0;
xD1 <= 'd0;
xD2 <= 'd0;
multInA <= 'd0;
multInB <= 'd0;
multOut <= 'd0;
adderOut <= 'd0;
outStrobe <= 1'b0;
end
else begin
// Register X & delayed X on enable strobe
if (inStrobe) begin
x <= dataIn;
xD1 <= x;
xD2 <= xD1;
end
// Register Y & delayed Y on output strobe
if (storeY) begin
y <= adderOut[SCALING+:WIDTH_D];
yD1 <= y;
end
outStrobe <= storeY;
// Determine inputs into multiplier (DSP48)
case (state)
ST_IDLE : begin
multInA <= x;
multInB <= $rtoi(COEFF_B0 * 2**SCALING);
end
ST_X_B0 : begin
multInA <= x;
multInB <= $rtoi(COEFF_B0 * 2**SCALING);
end
ST_X_B1 : begin
multInA <= xD1;
multInB <= $rtoi(COEFF_B1 * 2**SCALING);
end
ST_X_B2 : begin
multInA <= xD2;
multInB <= $rtoi(COEFF_B2 * 2**SCALING);
end
ST_Y_A1 : begin
multInA <= y;
multInB <= $rtoi(-COEFF_A1 * 2**SCALING);
end
ST_Y_A2 : begin
multInA <= yD1;
multInB <= $rtoi(-COEFF_A2 * 2**SCALING);
end
endcase
// Determine Adder Function (DSP48)
case (stateD2)
ST_IDLE : begin
adderOut <= multOut;
end
ST_X_B0 : begin
adderOut <= multOut;
end
ST_X_B1 : begin
adderOut <= multOut + adderOut;
end
ST_X_B2 : begin
adderOut <= multOut + adderOut;
end
ST_Y_A1 : begin
adderOut <= multOut + adderOut;
end
ST_Y_A2 : begin
adderOut <= multOut + adderOut;
end
endcase
multOut <= multInA * multInB;
end
end
// State Machine to drive inputs to calculation engine
always @(posedge clk) begin
if (rst) begin
state <= ST_IDLE;
stateD1 <= ST_IDLE;
stateD2 <= ST_IDLE;
end
else begin
stateD1 <= state;
stateD2 <= stateD1;
storeY <= (stateD2 == ST_Y_A2);
case (state)
ST_IDLE : state <= (inStrobe) ? ST_X_B0 : ST_IDLE;
ST_X_B0 : state <= ST_X_B1;
ST_X_B1 : state <= ST_X_B2;
ST_X_B2 : state <= ST_Y_A1;
ST_Y_A1 : state <= ST_Y_A2;
ST_Y_A2 : state <= (inStrobe) ? ST_X_B0 : ST_IDLE;
default : state <= ST_IDLE;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_TB_V
`define SKY130_FD_SC_LS__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[210000], b[2100000]; vector<pair<int, int> > ans; int main() { int N, M, i, j, k; scanf( %d%d , &N, &M); if (N <= M) { puts( -1 ); return 0; } for (i = 0; i < N; i++) scanf( %d%d , &a[i].first, &a[i].second); sort(a, a + N); for (i = 0; i <= M; i++) for (j = 0; i + j <= M; j++) { int l = i, r = N - 1 - j; int first = a[l].first + a[r].first, second = a[l].second + a[r].second; bool flag = 1; for (k = l; k <= r; k++) b[k] = make_pair(first - a[k].first, second - a[k].second); reverse(b + l, b + r + 1); int p = l, q = l, cnt = 0; while (p <= r && q <= r) { if (a[p] < b[q]) ++p; else if (a[p] > b[q]) ++q; else { ++cnt; ++p; ++q; } } if (r - l + 1 - cnt + i + j <= M) ans.push_back(make_pair(first, second)); } sort(ans.begin(), ans.end()); ans.resize(unique(ans.begin(), ans.end()) - ans.begin()); cout << ans.size() << endl; for (i = 0; i < ans.size(); i++) printf( %.12f %.12f n , ans[i].first / 2.0, ans[i].second / 2.0); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; char str[MAXN]; int main() { scanf( %s , str); int n = strlen(str); printf( 3 nL 2 nR 2 nR %d , 2 * n - 1); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
genvar g;
reg [31:0] gen_pre_PLUSPLUS = 32'h0;
reg [31:0] gen_pre_MINUSMINUS = 32'h0;
reg [31:0] gen_post_PLUSPLUS = 32'h0;
reg [31:0] gen_post_MINUSMINUS = 32'h0;
reg [31:0] gen_PLUSEQ = 32'h0;
reg [31:0] gen_MINUSEQ = 32'h0;
reg [31:0] gen_TIMESEQ = 32'h0;
reg [31:0] gen_DIVEQ = 32'h0;
reg [31:0] gen_MODEQ = 32'h0;
reg [31:0] gen_ANDEQ = 32'h0;
reg [31:0] gen_OREQ = 32'h0;
reg [31:0] gen_XOREQ = 32'h0;
reg [31:0] gen_SLEFTEQ = 32'h0;
reg [31:0] gen_SRIGHTEQ = 32'h0;
reg [31:0] gen_SSRIGHTEQ = 32'h0;
generate
for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1;
for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1;
for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1;
for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
`ifndef verilator //UNSUPPORTED
for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1;
for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1;
for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1;
for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
`endif
endgenerate
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 3) begin
`ifdef TEST_VERBOSE
$write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS);
$write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS);
$write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS);
$write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS);
$write("gen_PLUSEQ %b\n", gen_PLUSEQ);
$write("gen_MINUSEQ %b\n", gen_MINUSEQ);
$write("gen_TIMESEQ %b\n", gen_TIMESEQ);
$write("gen_DIVEQ %b\n", gen_DIVEQ);
$write("gen_MODEQ %b\n", gen_MODEQ);
$write("gen_ANDEQ %b\n", gen_ANDEQ);
$write("gen_OREQ %b\n", gen_OREQ);
$write("gen_XOREQ %b\n", gen_XOREQ);
$write("gen_SLEFTEQ %b\n", gen_SLEFTEQ);
$write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ);
$write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ);
`endif
if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop;
if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop;
`ifndef verilator //UNSUPPORTED
if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop;
if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop;
if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop;
if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop;
if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop;
if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop;
if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop;
if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void display(vector<int> &a) { for (int z : a) cout << z << ; cout << endl; } int dx[4] = {0, 0, 1, -1}; int dy[4] = {1, -1, 0, 0}; const int mod = 998244353; const long long INF64 = 3e18; void smxl(long long &a, long long b) { if (a < b) a = b; } void smnl(long long &a, long long b) { if (a > b) a = b; } void adsl(long long &a, long long b) { a += b; if (a >= mod) a -= mod; } void misl(long long &a, long long b) { a -= b; if (a >= mod) a -= mod; if (a < 0) a += mod; } void smx(long long &a, long long b) { if (a < b) a = b; } void smn(long long &a, long long b) { if (a > b) a = b; } void ads(long long &a, long long b) { a += b; if (a >= mod) a -= mod; } void mis(long long &a, long long b) { a -= b; if (a >= mod) a -= mod; if (a < 0) a += mod; } long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long egcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = egcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long mbinp(long long a, long long b) { a %= mod; if (b == 0) return 1; long long ans = mbinp(a, b / 2); long long tmp = (ans * ans) % mod; if (b % 2) return ((tmp * a) % mod); return ((tmp) % mod); } long long binp(long long a, long long b) { if (b == 0) return 1; long long ans = binp(a, b / 2); long long tmp = (ans * ans); if (b % 2) return ((tmp * a)); return ((tmp)); } long long C(int n, int m) { long long ret = 1; for (int i = 1; i <= m; i++) { ret *= (n - i + 1); ret /= i; } return ret; } long long overbinp(long long a, int b) { long long res = 1; while (b) { if (b & 1) { if (res < INF64 / a) res *= a; else return INF64; } if (b > 1) { if (a < INF64 / a) a *= a; else return INF64; } b >>= 1; } return res; } class DSU { vector<int> par; vector<int> siize; public: DSU(int n) { par.resize(n); siize.resize(n); for (int i = 0; i < n; i++) { par[i] = i; siize[i] = 1; } } public: int get(int x) { return (x == par[x] ? x : par[x] = get(par[x])); } public: void merge(int a, int b) { int x = get(a); int y = get(b); if (x == y) return; if (siize[x] < siize[y]) swap(x, y); par[y] = x; siize[x] += siize[y]; } }; class BinaryLift { vector<vector<int> > binlift; int n; public: BinaryLift(vector<int> rnk, vector<int> par) { n = (int)par.size(); binlift.resize(n); for (int i = 0; i < n; i++) binlift[i].resize(20); for (int i = 0; i < n; i++) binlift[i][0] = par[i]; for (int j = 1; j < 20; j++) for (int i = 0; i < n; i++) { if ((1 << j) < rnk[i]) binlift[i][j] = binlift[binlift[i][j - 1]][j - 1]; else binlift[i][j] = -1; } } public: int get_kth_ancestor(int x, int k) { int pt = x; for (int i = 19; i >= 0; i--) { if (pt == -1) exit(0); if (k & (1 << i)) pt = binlift[pt][i]; } return pt; } public: int get_th_ancestor(int x, int k) { int pt = x; for (int i = 19; i >= 0; i--) { if (k & (1 << i)) pt = binlift[pt][i]; } return pt; } }; class SparseTable2D { vector<vector<vector<vector<int> > > > sparse; vector<vector<int> > inp; int m, n; private: int lg2(int x) { int out = 0; while ((1 << out) <= x) out++; return out - 1; } public: int rmin(int x1, int y1, int x2, int y2) { int lenx = x2 - x1 + 1; int lx = lg2(lenx) + 1; int leny = y2 - y1 + 1; int ly = lg2(leny) + 1; return min( min(sparse[lx][x1][ly][y1], sparse[lx][x1][ly][y2 + 1 - (1 << ly)]), min(sparse[lx][x2 + 1 - (1 << lx)][ly][y1], sparse[lx][x2 + 1 - (1 << lx)][ly][y2 + 1 - (1 << ly)])); } public: SparseTable2D(vector<vector<int> > input, string param) { n = input.size(); m = input[0].size(); inp = input; if (param == min ) prepromin(); } private: void prepromin() { int lln, lm; lln = lg2(n) + 1; lm = lg2(m) + 1; sparse.resize(lln); for (int i = 0; i < lln; i++) sparse[i].resize(n); for (int i = 0; i < lln; i++) for (int j = 0; j < n; j++) sparse[i][j].resize(lm); for (int i = 0; i < lln; i++) for (int j = 0; j < n; j++) for (int k = 0; k < lm; k++) sparse[i][j][k].resize(m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) sparse[0][i][0][j] = inp[i][j]; for (int j = 1; j < lm; j++) for (int k = 0; k + (1 << j) - 1 < m; k++) sparse[0][i][j][k] = min(sparse[0][i][j - 1][k], sparse[0][i][j - 1][k + (1 << (j - 1))]); } for (int i = 1; i < lln; i++) for (int j = 0; j + (1 << i) - 1 < n; j++) for (int k = 0; k < lm; k++) for (int h = 0; h < m; h++) sparse[i][j][k][h] = min(sparse[i - 1][j][k][h], sparse[i - 1][j + (1 << (i - 1))][k][h]); } }; class SparseTable { vector<vector<long long> > sparse; int n; vector<int> input; private: int lg2(int x) { int out = 0; while ((1 << out) <= x) out++; return out - 1; } public: int rmaxpos(int left, int right) { int len = right - left + 1; int lg = lg2(len); return (input[sparse[left][lg]] > input[sparse[left + len - (1 << lg)][lg]] ? sparse[left][lg] : sparse[left + len - (1 << lg)][lg]); } public: int rmaxval(int left, int right) { int len = right - left + 1; int lg = lg2(len); return (input[sparse[left][lg]] > input[sparse[left + len - (1 << lg)][lg]] ? input[sparse[left][lg]] : input[sparse[left + len - (1 << lg)][lg]]); } public: int rminpos(int left, int right) { int len = right - left + 1; int lg = lg2(len); return (input[sparse[left][lg]] < input[sparse[left + len - (1 << lg)][lg]] ? sparse[left][lg] : sparse[left + len - (1 << lg)][lg]); } public: int rminval(int left, int right) { int len = right - left + 1; int lg = lg2(len); return (input[sparse[left][lg]] < input[sparse[left + len - (1 << lg)][lg]] ? input[sparse[left][lg]] : input[sparse[left + len - (1 << lg)][lg]]); } public: long long rsum(int left, int right) { long long ans = 0; int pos; while (left <= right) { for (int i = 19; i >= 0; i--) if ((1 << i) <= right - left + 1) { pos = i; break; } ans += sparse[left][pos]; left = left + (1 << pos); } return ans; } public: SparseTable(vector<int> inp, string operation) { input = inp; n = inp.size(); if (operation == min ) prepromin(); else if (operation == max ) prepromax(); else if (operation == sum ) preprosum(); } private: void prepromin() { sparse.resize(n); int x = lg2(n) + 1; for (int i = 0; i < n; i++) sparse[i].resize(x); for (int i = 0; i < n; i++) sparse[i][0] = i; for (int j = 1; j < x; j++) for (int i = 0; i + (1 << (j)) - 1 < n; i++) sparse[i][j] = (input[sparse[i][j - 1]] < input[sparse[i + (1 << (j - 1))][j - 1]] ? sparse[i][j - 1] : sparse[i + (1 << (j - 1))][j - 1]); } void prepromax() { sparse.resize(n); int x = lg2(n) + 1; for (int i = 0; i < n; i++) sparse[i].resize(x); for (int i = 0; i < n; i++) sparse[i][0] = i; for (int j = 1; j < x; j++) for (int i = 0; i + (1 << (j)) - 1 < n; i++) sparse[i][j] = (input[sparse[i][j - 1]] > input[sparse[i + (1 << (j - 1))][j - 1]] ? sparse[i][j - 1] : sparse[i + (1 << (j - 1))][j - 1]); } void preprosum() { sparse.resize(n); int x = lg2(n) + 1; for (int i = 0; i < n; i++) sparse[i].resize(x); for (int i = 0; i < n; i++) sparse[i][0] = input[i]; for (int j = 1; j < x; j++) for (int i = 0; i + (1 << (j)) - 1 < n; i++) sparse[i][j] = sparse[i][j - 1] + sparse[i + (1 << (j - 1))][j - 1]; } }; class Vector { public: pair<long long, long long> x; public: Vector(pair<long long, long long> a, pair<long long, long long> b) { x.first = b.first - a.first; x.second = b.second - a.second; } public: long double getMagnitude() { return sqrtl(x.first * x.first + x.second * x.second); } }; class Line { public: pair<long long, long long> x, y; public: Line(pair<long long, long long> a, pair<long long, long long> b) { x = a; y = b; } private: long double dotProduct(Vector a, Vector b) { return a.x.first * b.x.first + a.x.second * b.x.second; } private: long double crossProduct(Vector a, Vector b) { return a.x.first * b.x.second - a.x.second * b.x.first; } private: long double magnitude(Vector a) { return a.getMagnitude(); } public: long double distanceToA(pair<long long, long long> c) { return dotProduct(Vector(x, y), Vector(x, c)) / magnitude(Vector(x, y)); } public: long double orthogonalDistance(pair<long long, long long> c) { return crossProduct(Vector(x, y), Vector(x, c)) / magnitude(Vector(x, y)); } public: pair<long double, long double> intersection(Line l) { pair<long double, long double> ans; ans.first = (long double)((x.first * y.second - x.second * y.first) * (l.x.first - l.y.first) - (x.first - y.first) * (l.x.first * l.y.second - l.x.second * l.y.first)) / ((x.first - y.first) * (l.x.second - l.y.second) - (x.second - y.second) * (l.x.first - l.y.first)); ans.second = (long double)((x.first * y.second - x.second * y.first) * (l.x.second - l.y.second) - (x.second - y.second) * (l.x.first * l.y.second - l.x.second * l.y.first)) / ((x.first - y.first) * (l.x.second - l.y.second) - (x.second - y.second) * (l.x.first - l.y.first)); return ans; } }; class PruferCode { vector<int> code; vector<pair<int, int> > edges; public: PruferCode(vector<int> cc) { code = cc; findEdges(); } private: void findEdges() { map<int, int> mp; set<int> has; set<int> wait; for (int z : code) { mp[z]++; has.insert(z); } for (int i = 0; i < code.size() + 2; i++) if (!has.count(i)) wait.insert(i); for (int i = 0; i < code.size(); i++) { int now = *wait.begin(); edges.push_back(make_pair(now, code[i])); mp[now]++; mp[code[i]]--; if (mp[code[i]] == 0) { has.erase(code[i]); wait.insert(code[i]); } wait.erase(now); } assert(wait.size() == 2); edges.push_back(make_pair(*wait.begin(), *wait.rbegin())); } public: vector<pair<int, int> > getEdges() { return edges; } }; class Segment { pair<long long, long long> x, y; public: Segment(pair<long long, long long> a, pair<long long, long long> b) { x = a; y = b; } private: long double dotProduct(Vector a, Vector b) { return a.x.first * b.x.first + a.x.second * b.x.second; } private: long double crossProduct(Vector a, Vector b) { return a.x.first * b.x.second - a.x.second * b.x.first; } private: long double magnitude(Vector a) { return a.getMagnitude(); } public: long double distanceToA(pair<long long, long long> c) { return dotProduct(Vector(x, y), Vector(x, c)) / magnitude(Vector(x, y)); } public: long double distanceToSegment(pair<long long, long long> c) { if (distanceToA(c) >= 0 && distanceToA(c) <= magnitude(Vector(x, y))) return crossProduct(Vector(x, y), Vector(x, c)) / magnitude(Vector(x, y)); else return min(magnitude(Vector(x, c)), magnitude(Vector(y, c))); } }; class HopcroftKarp { vector<int> matched; vector<vector<pair<int, int> > > adj; int left; int right; public: HopcroftKarp(vector<vector<pair<int, int> > > inp, int l, int r) { adj = inp; left = l; matched.resize(l); for (int i = 0; i < l; i++) matched[i] = -1; right = r; } public: vector<int> match() { bool cont = true; set<int> lfree, rfree; for (int i = 0; i < left; i++) lfree.insert(i); for (int i = left; i < left + right; i++) rfree.insert(i); vector<bool> yet(left, 0); for (int i = 0; i < left; i++) for (int j = 0; j < adj[i].size(); j++) if (adj[i][j].second == 1 && rfree.count(adj[i][j].first) && !yet[i]) { yet[i] = true; matched[i] = adj[i][j].first; adj[i][j].second = 2; for (int x = 0; x < adj[adj[i][j].first].size(); x++) if (adj[adj[i][j].first][x].first == i) adj[adj[i][j].first][x].second = 2; rfree.erase(adj[i][j].first); lfree.erase(i); } while (cont) { vector<int> par(left + right, -1); queue<pair<int, int> > kyou; for (int z : lfree) kyou.push(make_pair(z, 0)); int update = -1; vector<int> vis(left + right, 0); while (kyou.size()) { pair<int, int> frt = kyou.front(); kyou.pop(); if (rfree.count(frt.first)) { update = frt.first; break; } if (frt.second == 0) { for (pair<int, int> z : adj[frt.first]) { if (z.second == 1 && !vis[z.first]) { par[z.first] = frt.first; vis[z.first] = 1; kyou.push(make_pair(z.first, 1)); } } } else { for (pair<int, int> z : adj[frt.first]) { if (z.second == 2 && !vis[z.first]) { par[z.first] = frt.first; vis[z.first] = 1; kyou.push(make_pair(z.first, 0)); } } } } int x = update; int cnt = 0; while (x != -1 && par[x] != -1) { for (int i = 0; i < adj[x].size(); i++) if (adj[x][i].first == par[x]) { adj[x][i].second = (cnt == 0 ? 2 : 1); if (cnt == 0) { matched[par[x]] = x; rfree.erase(x); lfree.erase(par[x]); } } for (int i = 0; i < adj[par[x]].size(); i++) if (adj[par[x]][i].first == x) adj[par[x]][i].second = (cnt == 0 ? 2 : 1); cnt++; cnt %= 2; x = par[x]; } if (update == -1) cont = false; } return matched; } }; class Triangle { pair<long long, long long> x, y, z; public: Triangle(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c) { x = a; y = b; z = c; } private: long double crossProduct(Vector a, Vector b) { return a.x.first * b.x.second - a.x.second * b.x.first; } public: long double perimeter() { long double s1, s2, s3; s1 = Vector(x, y).getMagnitude(); s2 = Vector(y, z).getMagnitude(); s3 = Vector(x, z).getMagnitude(); return s1 + s2 + s3; } public: long double area() { return abs(crossProduct(Vector(x, y), Vector(x, z))); } }; class SuffixArray { vector<int> order; vector<int> lcp; string str; public: SuffixArray(string in) { str = in; str += $ ; order.resize(str.length()); lcp.resize(str.length()); compute(); } void compute() { vector<pair<char, int> > a; vector<int> equi(order.size()); vector<int> bij(order.size()); for (int i = 0; i < str.length(); i++) a.push_back(make_pair(str[i], i)); sort(a.begin(), a.end()); for (int i = 0; i < str.length(); i++) order[i] = a[i].second; equi[order[0]] = 0; int r = 0; for (int i = 1; i < str.length(); i++) { if (a[i].first == a[i - 1].first) equi[order[i]] = r; else equi[order[i]] = ++r; } int k = 0; while ((1 << k) < str.length()) { vector<pair<pair<int, int>, int> > a(str.length()); for (int i = 0; i < str.length(); i++) a[i] = make_pair( make_pair(equi[i], equi[(i + (1 << k)) % (str.length())]), i); sort(a.begin(), a.end()); for (int i = 0; i < str.length(); i++) { order[i] = a[i].second; bij[order[i]] = i; } int r = 0; equi[order[0]] = 0; for (int i = 1; i < str.length(); i++) { if (a[i].first == a[i - 1].first) equi[order[i]] = r; else equi[order[i]] = ++r; } k++; } k = 0; for (int i = 0; i < str.length() - 1; i++) { int p = bij[i]; int j = order[p - 1]; while (i + k < str.length() && j + k < str.length() && str[i + k] == str[j + k]) k++; lcp[p] = k; k = max(k - 1, 0); } } public: int count(string ptr) { int low = 0; int hi = str.length() - 1; int res1, res2; res1 = 0; res2 = 1e9; while (low <= hi) { int mid = (low + hi) / 2; bool gr = false; int i = 0; for (i; i < min(ptr.length(), str.length() - order[mid]); i++) { if (ptr[i] != str[order[mid] + i]) { if (ptr[i] > str[order[mid] + i]) gr = true; break; } } if (i == ptr.length()) { res2 = min(res2, mid); hi = mid - 1; } else if (!gr) hi = mid - 1; else low = mid + 1; } low = 0; hi = str.length() - 1; while (low <= hi) { int mid = (low + hi) / 2; bool gr = false; int i = 0; for (i; i < min(ptr.length(), str.length() - order[mid] + 1); i++) { if (ptr[i] != str[order[mid] + i]) { if (ptr[i] > str[order[mid] + i]) gr = true; break; } } if (i == ptr.length()) { res1 = max(res1, mid); low = mid + 1; } else if (!gr) hi = mid - 1; else low = mid + 1; } if (res2 == 1e9) return 0; return (res1 - res2 + 1); } public: vector<int> get() { return order; } public: vector<int> getLcp() { return lcp; } public: long long diffSubstrings() { long long out = 0; for (int i = 1; i < str.length(); i++) out += str.length() - order[i] - lcp[i] - 1; return out; } }; string longestCommonSubstring(string a, string b) { int len = 0; string res = a + % + b; SuffixArray sf = SuffixArray(res); vector<int> order = sf.get(); vector<int> lcp = sf.getLcp(); vector<int> col(order.size()); for (int i = 0; i < order.size(); i++) { if (order[i] < a.length()) col[order[i]] = 1; else if (order[i] > a.length()) col[order[i]] = 2; } int pos = -1; for (int i = 1; i < order.size(); i++) if (col[order[i]] + col[order[i - 1]] == 3) { if (lcp[i] > len) { len = max(len, lcp[i]); pos = (col[order[i]] == 1 ? order[i] : order[i - 1]); } } return a.substr(pos, len); } void solve() { int n, k; cin >> n >> k; vector<int> all(n); vector<int> bij(n + 1); set<int> st; for (int i = 0; i < n; i++) { cin >> all[i]; bij[all[i]] = i; st.insert(i); } set<int> b; vector<int> bb(k); for (int i = 0; i < k; i++) { int x; cin >> x; bb[i] = x; b.insert(x); } long long ans = 1; for (int i = 0; i < k; i++) { int pos = bij[bb[i]]; auto t = st.find(pos); auto m = t; m++; if (t == st.begin()) { auto r = t; r++; if (b.count(all[*r])) { cout << 0 << n ; return; } else { st.erase(*r); } } else if (m == st.end()) { auto r = t; r--; if (b.count(all[*r])) { cout << 0 << n ; return; } else st.erase(*r); } else { auto r = t; auto q = t; r++; q--; if (!b.count(all[*r]) && !b.count(all[*q])) { ans *= 2; ans %= mod; st.erase(*r); } else if (!b.count(all[*r])) st.erase(*r); else if (!b.count(all[*q])) st.erase(*q); else { cout << 0 << n ; return; } } b.erase(bb[i]); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_SYMBOL_V
`define SKY130_FD_SC_LS__O2BB2A_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_SYMBOL_V
|
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