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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_HS__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, c0, c1, h; cin >> n >> c0 >> c1 >> h; string second; cin >> second; int cost1 = 0, z = 0, o = 0; for (int i = 0; i < second.length(); i++) { if (second[i] == 0 ) { cost1 += c0; z++; } else { cost1 += c1; o++; } } int cost2 = o * h + c0 * (second.length()); int cost3 = z * h + c1 * (second.length()); cout << min(cost1, min(cost2, cost3)) << endl; } return 0; } |
`timescale 1 ns / 1 ps
module axis_scaler #
(
parameter integer AXIS_TDATA_WIDTH = 14
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire signed [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Slave side
input wire signed [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
// Master side
input wire m_axis_tready,
output wire signed [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg signed [AXIS_TDATA_WIDTH-1:0] s_axis_tdata_reg,s_axis_tdata_next;
reg [AXIS_TDATA_WIDTH*2-1:0] int_data_reg, int_data_next;
wire multiply = s_axis_tvalid & m_axis_tready;
always @(posedge aclk)
begin
if(~aresetn)
begin
s_axis_tdata_reg <= 0;
s_axis_tdata_next <= 0;
int_data_reg <= 0;
int_data_next <= 0;
end
else
begin
if(multiply)
begin
s_axis_tdata_reg <= s_axis_tdata;
s_axis_tdata_next <= s_axis_tdata_reg;
int_data_reg <= s_axis_tdata_next*cfg_data;
int_data_next <= int_data_reg;
end
end
end
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
//scales down relative to 2^(AXIS_TDATA_WIDTH-2), e.g. cfg=4096 for 14 bit equals scale of 1
assign m_axis_tdata = int_data_next[AXIS_TDATA_WIDTH*2-3:AXIS_TDATA_WIDTH-2];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100000, M = 10, pw[5] = {1, 10, 100, 1000, 10000}; const unsigned long long mod = 1ULL << 58, inv = 6723469279985657373ULL; struct comp { unsigned long long a[4]; comp(int X = 0) { a[0] = X; a[1] = a[2] = a[3] = 0; } unsigned long long &operator[](const int &p) { return a[p]; } comp operator+(const comp &p) const { comp res; for (int i = 0; i < 4; ++i) res.a[i] = a[i] + p.a[i]; return res; } comp operator-(const comp &p) const { comp res; for (int i = 0; i < 4; ++i) res.a[i] = a[i] - p.a[i]; return res; } comp operator*(const unsigned long long &p) const { comp res; for (int i = 0; i < 4; ++i) res.a[i] = a[i] * p; return res; } comp operator*(const comp &p) const { comp res; static unsigned long long tmp[7]; for (int i = 0; i < 7; ++i) tmp[i] = 0; for (int i = 0; i < 4; ++i) for (int j = 0; j < 4; ++j) tmp[i + j] += a[i] * p.a[j]; for (int i = 2; i >= 0; --i) { for (int j = 0; j < 4; ++j) tmp[i + j] -= tmp[i + 4]; tmp[i + 4] = 0; } for (int i = 0; i < 4; ++i) res.a[i] = tmp[i]; return res; } }; comp Power(comp a, int k) { comp res(1); for (; k; k >>= 1, a = a * a) if (k & 1) res = res * a; return res; } comp wn[M + 9]; void Get_wn() { wn[0][0] = wn[M][0] = 1; wn[1][3] = -1; for (int i = 1; i < M; ++i) wn[i] = wn[i - 1] * wn[1]; } int gg = 0; void DFT(comp *a, int t) { static comp dft[M]; for (int d = 0; d < 5; ++d) { for (int i = 0; i < N; ++i) { if (i / pw[d] % M) continue; for (int j = 0; j < M; ++j) dft[j] = 0; for (int j = 0; j < M; ++j) for (int k = 0; k < M; ++k) dft[j] = dft[j] + a[i + k * pw[d]] * wn[t ? M - j * k % M : j * k % M]; for (int j = 0; j < M; ++j) a[i + j * pw[d]] = dft[j]; } } if (!t) return; for (int i = 0; i < N; ++i) a[i] = a[i] * inv; } int n; comp a[N + 9]; void into() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); ++a[x][0]; } } void Get_ans() { DFT(a, 0); for (int i = 0; i < N; ++i) a[i] = Power(a[i], n); DFT(a, 1); } void work() { Get_wn(); Get_ans(); } void outo() { for (int i = 0; i < n; ++i) printf( %llu n , a[i][0] >> 5 & mod - 1); } int main() { into(); work(); outo(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2005; int n, m, ans[N], h[N]; bitset<N> a[N]; vector<int> e[N]; bool check1() { for (int i = (int)(1); i <= (int)(n); i++) if (e[i].size() & 1) return 0; return 1; } void gauss() { int it = 1; for (int i = (int)(1); i <= (int)(n); i++) { int j = it; for (; j <= n; j++) if (a[j][i]) break; if (j > n) continue; if (j > it) swap(a[j], a[it]); h[it] = i; for (int j = (int)(it + 1); j <= (int)(n); j++) if (a[j][i]) a[j] ^= a[it]; it++; } int las = n + 1; for (int i = (int)(it - 1); i >= (int)(1); i--) { for (int j = (int)(h[i] + 1); j <= (int)(las - 1); j++) ans[j] = 0; ans[h[i]] = a[i][0]; for (int j = (int)(1); j <= (int)(i - 1); j++) if (a[j][h[i]]) a[j] ^= a[i]; las = h[i]; } for (int i = (int)(1); i <= (int)(las - 1); i++) ans[i] = 0; } void solve() { scanf( %d%d , &n, &m); for (int i = (int)(1); i <= (int)(n); i++) e[i].clear(); for (int i = (int)(1); i <= (int)(m); i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } if (check1()) { puts( 1 ); for (int i = (int)(1); i <= (int)(n); i++) printf( 1 ); puts( ); return; } for (int i = (int)(1); i <= (int)(n); i++) { a[i] = 0; for (auto j : e[i]) a[i].set(j); if (e[i].size() & 1) a[i].set(i), a[i].set(0); } memset(ans, 0, sizeof(ans)); gauss(); puts( 2 ); for (int i = (int)(1); i <= (int)(n); i++) printf( %d , ans[i] + 1); puts( ); } int main() { int T; scanf( %d , &T); while (T--) solve(); } |
/*
* ECP5 PicoRV32 demo
*
* Copyright (C) 2017 Clifford Wolf <>
* Copyright (C) 2018 David Shah <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifdef PICORV32_V
`error "attosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
module attosoc (
input clk,
input reset,
output reg [7:0] led
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
if (reset)
reset_cnt <= 0;
else
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
parameter integer ROM_WORDS = 64;
reg [31:0] rom [0:ROM_WORDS-1];
wire [31:0] rom_rdata = rom[mem_addr[31:2]];
initial $readmemh("firmware.hex", rom);
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;
wire iomem_valid;
wire iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_ready = 1'b1;
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire [31:0] spimemio_cfgreg_do;
always @(posedge clk)
if (iomem_valid && iomem_wstrb[0])
led <= iomem_wdata[7:0];
assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;
assign mem_rdata = rom_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0),
.ENABLE_COUNTERS(0),
.TWO_STAGE_SHIFT(0),
.ENABLE_REGS_16_31(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 55; const unsigned long long M = 1000000009LL; const int K = 3; const int LIT = 2500; const int INF = 1 << 30; const double eps = 1e-6; const unsigned long long MOD = 1000000007LL; const int dir[][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; unsigned long long n, m; unsigned long long pw2[N] = {0}; void init() { pw2[0] = 1; for (int i = 1; i < N; i++) { pw2[i] = pw2[i - 1] * 2; } } int getCP(int n, int m) { if (n == 3 && m == 1) return -1; if (n == 3 && m == 2) return -2; unsigned long long tot = pw2[n - 2]; unsigned long long mid = pw2[n - 3]; if (m > mid) { return getCP(n, m - mid) - 1; } else { return getCP(n - 1, m); } } vector<unsigned long long> getP(unsigned long long n, unsigned long long m) { vector<unsigned long long> ans; if (n == 1) { ans.push_back(1); return ans; } if (n == 2) { if (m == 1) { ans.push_back(1); ans.push_back(2); } if (m == 2) { ans.push_back(2); ans.push_back(1); } return ans; } unsigned long long tot = pw2[n - 1]; unsigned long long mid = pw2[n - 2]; if (m > mid) { ans = getP(n, tot + 1 - m); reverse(ans.begin(), ans.end()); return ans; } vector<unsigned long long> pre = getP(n - 1, (m + 1) / 2); int cp = n + getCP(n, m); for (int i = 0; i < cp; i++) { ans.push_back(pre[i]); } ans.push_back(n); for (int i = cp; i < n - 1; i++) { ans.push_back(pre[i]); } return ans; } void solve() { vector<unsigned long long> ans = getP(n, m); for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; cout << endl; } int main() { int T; while (cin >> n >> m) { init(); solve(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_PP_SYMBOL_V
`define SKY130_FD_SC_HS__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V |
//
// Copyright (c) 2000 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// force3.17A - Template 1 - force reg_lvalue = constant.
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
initial
begin
val2 = 0;
val1 = 2;
#50 ;
if(val2 !== 4'b0001)
$display("FAILED");
else
$display("PASSED");
end
initial
begin
#20;
force val2 = (val1 == 2);
end
endmodule
|
/*
This file was generated automatically by the Mojo IDE version B1.3.6.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
FACTOR = 5
*/
module serdes_n_to_1_22 (
input ioclk,
input strobe,
input rst,
input gclk,
input [4:0] data,
output reg iob_out
);
localparam FACTOR = 3'h5;
reg [7:0] padded_data;
integer i;
wire [1-1:0] M_mserdes_OQ;
wire [1-1:0] M_mserdes_TQ;
wire [1-1:0] M_mserdes_SHIFTOUT1;
wire [1-1:0] M_mserdes_SHIFTOUT2;
wire [1-1:0] M_mserdes_SHIFTOUT3;
wire [1-1:0] M_mserdes_SHIFTOUT4;
reg [1-1:0] M_mserdes_IOCE;
reg [1-1:0] M_mserdes_D1;
reg [1-1:0] M_mserdes_D2;
reg [1-1:0] M_mserdes_D3;
reg [1-1:0] M_mserdes_D4;
reg [1-1:0] M_mserdes_OCE;
reg [1-1:0] M_mserdes_T1;
reg [1-1:0] M_mserdes_T2;
reg [1-1:0] M_mserdes_T3;
reg [1-1:0] M_mserdes_T4;
reg [1-1:0] M_mserdes_TCE;
reg [1-1:0] M_mserdes_SHIFTIN1;
reg [1-1:0] M_mserdes_SHIFTIN2;
reg [1-1:0] M_mserdes_SHIFTIN3;
reg [1-1:0] M_mserdes_SHIFTIN4;
reg [1-1:0] M_mserdes_TRAIN;
OSERDES2 #(.DATA_WIDTH(5), .DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .SERDES_MODE("MASTER"), .OUTPUT_MODE("DIFFERENTIAL")) mserdes (
.CLK0(ioclk),
.CLK1(1'h0),
.RST(rst),
.CLKDIV(gclk),
.IOCE(M_mserdes_IOCE),
.D1(M_mserdes_D1),
.D2(M_mserdes_D2),
.D3(M_mserdes_D3),
.D4(M_mserdes_D4),
.OCE(M_mserdes_OCE),
.T1(M_mserdes_T1),
.T2(M_mserdes_T2),
.T3(M_mserdes_T3),
.T4(M_mserdes_T4),
.TCE(M_mserdes_TCE),
.SHIFTIN1(M_mserdes_SHIFTIN1),
.SHIFTIN2(M_mserdes_SHIFTIN2),
.SHIFTIN3(M_mserdes_SHIFTIN3),
.SHIFTIN4(M_mserdes_SHIFTIN4),
.TRAIN(M_mserdes_TRAIN),
.OQ(M_mserdes_OQ),
.TQ(M_mserdes_TQ),
.SHIFTOUT1(M_mserdes_SHIFTOUT1),
.SHIFTOUT2(M_mserdes_SHIFTOUT2),
.SHIFTOUT3(M_mserdes_SHIFTOUT3),
.SHIFTOUT4(M_mserdes_SHIFTOUT4)
);
wire [1-1:0] M_sserdes_OQ;
wire [1-1:0] M_sserdes_TQ;
wire [1-1:0] M_sserdes_SHIFTOUT1;
wire [1-1:0] M_sserdes_SHIFTOUT2;
wire [1-1:0] M_sserdes_SHIFTOUT3;
wire [1-1:0] M_sserdes_SHIFTOUT4;
reg [1-1:0] M_sserdes_IOCE;
reg [1-1:0] M_sserdes_D1;
reg [1-1:0] M_sserdes_D2;
reg [1-1:0] M_sserdes_D3;
reg [1-1:0] M_sserdes_D4;
reg [1-1:0] M_sserdes_OCE;
reg [1-1:0] M_sserdes_T1;
reg [1-1:0] M_sserdes_T2;
reg [1-1:0] M_sserdes_T3;
reg [1-1:0] M_sserdes_T4;
reg [1-1:0] M_sserdes_TCE;
reg [1-1:0] M_sserdes_SHIFTIN1;
reg [1-1:0] M_sserdes_SHIFTIN2;
reg [1-1:0] M_sserdes_SHIFTIN3;
reg [1-1:0] M_sserdes_SHIFTIN4;
reg [1-1:0] M_sserdes_TRAIN;
OSERDES2 #(.DATA_WIDTH(5), .DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .SERDES_MODE("SLAVE"), .OUTPUT_MODE("DIFFERENTIAL")) sserdes (
.CLK0(ioclk),
.CLK1(1'h0),
.RST(rst),
.CLKDIV(gclk),
.IOCE(M_sserdes_IOCE),
.D1(M_sserdes_D1),
.D2(M_sserdes_D2),
.D3(M_sserdes_D3),
.D4(M_sserdes_D4),
.OCE(M_sserdes_OCE),
.T1(M_sserdes_T1),
.T2(M_sserdes_T2),
.T3(M_sserdes_T3),
.T4(M_sserdes_T4),
.TCE(M_sserdes_TCE),
.SHIFTIN1(M_sserdes_SHIFTIN1),
.SHIFTIN2(M_sserdes_SHIFTIN2),
.SHIFTIN3(M_sserdes_SHIFTIN3),
.SHIFTIN4(M_sserdes_SHIFTIN4),
.TRAIN(M_sserdes_TRAIN),
.OQ(M_sserdes_OQ),
.TQ(M_sserdes_TQ),
.SHIFTOUT1(M_sserdes_SHIFTOUT1),
.SHIFTOUT2(M_sserdes_SHIFTOUT2),
.SHIFTOUT3(M_sserdes_SHIFTOUT3),
.SHIFTOUT4(M_sserdes_SHIFTOUT4)
);
always @* begin
padded_data = 8'h00;
for (i = 1'h0; i < 3'h5; i = i + 1) begin
padded_data[(i)*1+0-:1] = data[(i)*1+0-:1];
end
M_mserdes_OCE = 1'h1;
M_mserdes_IOCE = strobe;
M_mserdes_D4 = padded_data[7+0-:1];
M_mserdes_D3 = padded_data[6+0-:1];
M_mserdes_D2 = padded_data[5+0-:1];
M_mserdes_D1 = padded_data[4+0-:1];
M_mserdes_T1 = 1'h0;
M_mserdes_T2 = 1'h0;
M_mserdes_T3 = 1'h0;
M_mserdes_T4 = 1'h0;
M_mserdes_TRAIN = 1'h0;
M_mserdes_TCE = 1'h1;
M_mserdes_SHIFTIN1 = 1'h1;
M_mserdes_SHIFTIN2 = 1'h1;
M_mserdes_SHIFTIN3 = M_sserdes_SHIFTOUT3;
M_mserdes_SHIFTIN4 = M_sserdes_SHIFTOUT4;
M_sserdes_OCE = 1'h1;
M_sserdes_IOCE = strobe;
M_sserdes_D4 = padded_data[3+0-:1];
M_sserdes_D3 = padded_data[2+0-:1];
M_sserdes_D2 = padded_data[1+0-:1];
M_sserdes_D1 = padded_data[0+0-:1];
M_sserdes_T1 = 1'h0;
M_sserdes_T2 = 1'h0;
M_sserdes_T3 = 1'h0;
M_sserdes_T4 = 1'h0;
M_sserdes_TRAIN = 1'h0;
M_sserdes_TCE = 1'h1;
M_sserdes_SHIFTIN1 = M_mserdes_SHIFTOUT1;
M_sserdes_SHIFTIN2 = M_mserdes_SHIFTOUT2;
M_sserdes_SHIFTIN3 = 1'h1;
M_sserdes_SHIFTIN4 = 1'h1;
iob_out = M_mserdes_OQ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > v; vector<bool> vis; string ans = ; void dfs(int temp) { ans += temp + a ; for (auto it = v[temp].begin(); it != v[temp].end(); ++it) { if (!vis[*it]) { vis[*it] = true; dfs(*it); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { string s; cin >> s; v.resize(26); vis.resize(26); set<pair<char, char> > sc; for (int i = 0; i < s.size() - 1; i += 1) { pair<int, int> cc = {min(s[i], s[i + 1]), max(s[i], s[i + 1])}; if (sc.find(cc) == sc.end()) { sc.insert(cc); v[s[i] - a ].emplace_back(s[i + 1] - a ); v[s[i + 1] - a ].emplace_back(s[i] - a ); } } int cnt = 0, temp = 0; for (int i = 0; i < 26; i += 1) { if (v[i].size() == 1) { temp = i; cnt++; } else if (v[i].size() > 2) { cnt = -1; break; } } if (cnt != 2 && s.size() != 1) cout << NO n ; else { cout << YES n ; vis[temp] = true; dfs(temp); for (int i = 0; i < 26; i += 1) { if (!vis[i]) ans += i + a ; } cout << ans << n ; } ans = ; vis.clear(); for (int i = 0; i < 26; i += 1) v[i].clear(); v.clear(); } } |
#include <bits/stdc++.h> using namespace std; long long n, k; long long a[100010]; signed main() { scanf( %lld%lld , &n, &k); long long cnt = 1; long long l = 1; long long ans = 0; for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i]); cnt = cnt * a[i] % k; if (!cnt) { cnt = 1; long long j; for (j = i; j >= 1 && cnt * a[j] % k; j--) cnt = cnt * a[j] % k; ans += (n - i + 1) * (j - l + 1); l = j + 1; } } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_PP_SYMBOL_V
|
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
//wire [2*SW-1:0] FKOARES;
wire [2*SW-1:0] RKOARES;
//wire [2*SW-2:0] SimpleRES;
// wire [2*SW-2:0] HybridRES;
// wire [2*SW-1:0] Simple_KOA;
// wire [2*SW-1:0] Recursive_KOA;
reg clk;
parameter SW = 24;
// Bks26 inst_Bks26 (.a(a), .b(b), .d(BinaryRES));
// Sgf_Multiplication #(.SW(SW)) inst_Sgf_Multiplication (.clk(clk),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(FKOARES));
// Sks26 inst_Sks26 (.a(a), .b(b), .d(SimpleRES));
// Hks26 inst_Hks26 (.a(a), .b(b), .d(HybridRES));
RKOA #(.SW(SW)) inst_RKOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(RKOARES));
//Simple_KOA #(.SW(SW)) i_Simple_KOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(Simple_KOA));
//Recursive_KOA #(.SW(SW)) inst_Recursive_KOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(Recursive_KOA));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b, RKOARES);
end
initial begin
b = 1;
a = 1;
#100;
b = 2;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int a[2][200005]; int dp[2][200005][19]; void gao(int c) { for (int i = 1; i <= n; ++i) dp[c][i][0] = a[c][i]; for (int j = 1; (1 << j) <= n; ++j) { for (int i = 1; i + (1 << (j - 1)) <= n; ++i) { if (c == 0) dp[c][i][j] = max(dp[c][i][j - 1], dp[c][i + (1 << (j - 1))][j - 1]); if (c == 1) dp[c][i][j] = min(dp[c][i][j - 1], dp[c][i + (1 << (j - 1))][j - 1]); } } } int rmq(int l, int r, int c) { int k = (int)(log(r - l + 1) / log(2)); if (c == 0) return max(dp[c][l][k], dp[c][r - (1 << k) + 1][k]); return min(dp[c][l][k], dp[c][r - (1 << k) + 1][k]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[0][i]); for (int i = 1; i <= n; ++i) scanf( %d , &a[1][i]); gao(0), gao(1); long long ans = 0; for (int i = 1; i <= n; ++i) { int l = i, r = n, x, y; while (l < r) { int m = (l + r) >> 1; if (rmq(i, m, 0) < rmq(i, m, 1)) l = m + 1; else r = m; } x = l; l = i, r = n; while (l < r) { int m = (l + r + 1) >> 1; if (rmq(i, m, 0) > rmq(i, m, 1)) r = m - 1; else l = m; } y = l; if (x == y) ans += rmq(i, x, 0) == rmq(i, y, 1) ? 1 : 0; else ans += max(0, y - x + 1); } printf( %lld n , ans); return 0; } |
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2010,2011,2012
//
// decoding mode setup: which border, which modes in one-hot style coding
module video_modedecode(
input wire clk,
input wire [ 1:0] pent_vmode, // inputs as set by Z80 environment
input wire [ 2:0] atm_vmode, //
output reg mode_atm_n_pent, // =1 - atm modes, =0 - pentagon modes (mainly for border and visible area changing)
output reg mode_zx, // standard ZX mode
output reg mode_p_16c, // pentagon 16 colors
output reg mode_p_hmclr, // pentagon hardware multicolor
output reg mode_a_hmclr, // 640x200 atm hardware multicolor
output reg mode_a_16c, // 320x200 atm 16 colors
output reg mode_a_text, // 640x200 (80x25 symbols) atm text mode
output reg mode_a_txt_1page, // atm text mode in a single page (modifier for mode_a_text)
output reg mode_pixf_14, // =1: 14MHz pixelclock on (default is 7MHz).
output reg [ 1:0] mode_bw // required bandwidth: 2'b00 - 1/8, 2'b01 - 1/4,
// 2'b10 - 1/2, 2'b11 - 1
);
// values for pent_vmode and atm_vmode:
// pent:
// 2'b00 - standard ZX
// 2'b01 - hardware multicolor
// 2'b10 - pentagon 16 colors
// 2'b11 - not defined yet
// atm:
// 3'b011 - zx modes (pent_vmode is active)
// 3'b010 - 640x200 hardware multicolor
// 3'b000 - 320x200 16 colors
// 3'b110 - 80x25 text mode
// 3'b111 - 80x25 text mode (single page)
// 3'b??? (others) - not defined yet
always @(posedge clk)
begin
case( atm_vmode )
3'b010: mode_atm_n_pent <= 1'b1;
3'b000: mode_atm_n_pent <= 1'b1;
3'b110: mode_atm_n_pent <= 1'b1;
3'b111: mode_atm_n_pent <= 1'b1;
3'b011: mode_atm_n_pent <= 1'b0;
default: mode_atm_n_pent <= 1'b0;
endcase
case( atm_vmode )
3'b010: mode_zx <= 1'b0;
3'b000: mode_zx <= 1'b0;
3'b110: mode_zx <= 1'b0;
3'b111: mode_zx <= 1'b0;
default: begin
if( (pent_vmode==2'b00) || (pent_vmode==2'b11) )
mode_zx <= 1'b1;
else
mode_zx <= 1'b0;
end
endcase
if( (atm_vmode==3'b011) && (pent_vmode==2'b10) )
mode_p_16c <= 1'b1;
else
mode_p_16c <= 1'b0;
if( (atm_vmode==3'b011) && (pent_vmode==2'b01) )
mode_p_hmclr <= 1'b1;
else
mode_p_hmclr <= 1'b0;
if( atm_vmode==3'b010 )
mode_a_hmclr <= 1'b1;
else
mode_a_hmclr <= 1'b0;
if( atm_vmode==3'b000 )
mode_a_16c <= 1'b1;
else
mode_a_16c <= 1'b0;
if( (atm_vmode==3'b110) || (atm_vmode==3'b111) )
mode_a_text <= 1'b1;
else
mode_a_text <= 1'b0;
if( atm_vmode==3'b111 )
mode_a_txt_1page <= 1'b1;
else
mode_a_txt_1page <= 1'b0;
if( (atm_vmode==3'b010) || (atm_vmode==3'b110) || (atm_vmode==3'b111) )
mode_pixf_14 <= 1'b1;
else
mode_pixf_14 <= 1'b0;
if( (atm_vmode==3'b011) && (pent_vmode!=2'b10) )
mode_bw <= 2'b00; // 1/8
else
mode_bw <= 2'b01; // 1/4
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3E4 + 5; const int M = 500; int n, d, a[N], x, ans, r, L, w, f[N][M * 2 + 5]; int main() { cin >> n >> L; for (int i = 1; i <= n; i++) scanf( %d , &r), a[r]++; memset(f, -10, sizeof(f)); f[L][M] = a[L]; for (int i = 1; i <= r; i++) for (int j = L - M; j <= L + M; j++) if ((w = f[i][j - L + M]) >= 0) { ans = max(ans, w); for (int k = j - 1; k <= j + 1; k++) if (k > 0 && (x = i + k) <= r) { f[x][k - L + M] = max(f[x][k - L + M], w + a[x]); } } cout << ans; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate fork template 2
module main ;
reg [3:0] value1,value2 ;
reg [3:0] ret1,ret2 ;
reg error;
always @(value1 or value2)
begin
fork
#10 ret1 = value1;
@(ret1) #12 ret2 = value2;
join
end
initial
begin
error = 0;
#1;
value1 = 1;
value2 = 2;
ret1 = 0;
ret2 = 0;
#12;
if(ret1 !== 1)
begin
$display("FAILED - force3.19B first statement didn't execute(1)");
error = 1;
end
if(ret2 !== 0)
begin
$display("FAILED - force3.19B second stmt executed? is %d sb %d",
1'b0,ret2);
error = 1;
end
#10;
if(ret1 !== 1)
begin
$display("FAILED -fork3.19B First statement problem sb 1, is %d",ret1);
error = 1;
end
if(ret2 !== 2)
begin
$display("FAILED -fork3.19B First statement problem sb 2, is %d",ret1);
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; scanf( %d%d%d , &n, &a, &b); printf( %d n , ((a - 1) + b + 100 * n) % n + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int P = 1e9 + 7; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long qpow(long long a, long long n) { long long r = 1 % P; for (a %= P; n; a = a * a % P, n >>= 1) if (n & 1) r = r * a % P; return r; } long long inv(long long x) { return x <= 1 ? 1 : inv(P % x) * (P - P / x) % P; } const int N = 2e5 + 10; int a[N], h[N], f[N], n, m, k, p; struct _ { long long day, id; bool operator<(const _& rhs) const { return day > rhs.day; } }; priority_queue<_> q; bool check(long long x) { memset(f, 0, sizeof f); while (!q.empty()) q.pop(); for (int i = 1; i <= n; ++i) if (x - (long long)a[i] * m < h[i]) q.push({x / a[i], i}); for (int i = 1; i <= m; ++i) for (int j = 1; j <= k; ++j) { if (q.empty()) return 1; _ u = q.top(); q.pop(); if (u.day < i) return 0; if (x + (long long)p * ++f[u.id] - (long long)m * a[u.id] < h[u.id]) { q.push({(x + (long long)p * f[u.id]) / a[u.id], u.id}); } } return q.empty(); } int main() { scanf( %d%d%d%d , &n, &m, &k, &p); for (int i = 1; i <= n; ++i) scanf( %d%d , h + i, a + i); long long l = 0, r = 1e15, ans; while (l <= r) check((l + r >> 1)) ? ans = (l + r >> 1), r = (l + r >> 1) - 1 : l = (l + r >> 1) + 1; cout << ans << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LP__LSBUF_BEHAVIORAL_V
/**
* lsbuf: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , buf0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_LP_V
`define SKY130_FD_SC_LP__LSBUFISO0P_LP_V
/**
* lsbufiso0p: ????.
*
* Verilog wrapper for lsbufiso0p with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__lsbufiso0p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__lsbufiso0p_lp (
X ,
SLEEP ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
output X ;
input SLEEP ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
sky130_fd_sc_lp__lsbufiso0p base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.DESTPWR(DESTPWR),
.VPWR(VPWR),
.VGND(VGND),
.DESTVPB(DESTVPB),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__lsbufiso0p_lp (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__lsbufiso0p base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_LP_V
|
#include <bits/stdc++.h> using namespace std; int tree[270000 * 4]; int t; char opt; void insert(long long x) { if (x == 0) { ++tree[2]; return; } int num = x % 10; x /= 10; num = (num % 2 == 0 ? 0 : 1); int root = (num == 0 ? 2 : 3); ++tree[root]; while (x) { num = x % 10; x /= 10; num = (num % 2 == 0 ? 0 : 1); root = (num == 0 ? root * 2 : root * 2 + 1); ++tree[root]; } } void erase(long long x) { if (x == 0) { --tree[2]; return; } int num = x % 10; x /= 10; num = (num % 2 == 0 ? 0 : 1); int root = (num == 0 ? 2 : 3); --tree[root]; while (x) { num = x % 10; x /= 10; num = (num % 2 == 0 ? 0 : 1); root = (num == 0 ? root * 2 : root * 2 + 1); --tree[root]; } } void query(string s) { stack<int> stk; int lens = s.length(), beg = 0; for (int i = 0; i < lens; ++i) if (s[i] != 0 || i == lens - 1) { beg = i; break; } for (int i = beg; i < lens; ++i) stk.push(s[i] - 0 ); int now = stk.top(); stk.pop(); int root = (now == 0 ? 2 : 3); int ans = tree[root]; while (!stk.empty()) { now = stk.top(); stk.pop(); root = (now == 0 ? root * 2 : root * 2 + 1); ans = min(tree[root], ans); } while (beg) { root *= 2; ans -= tree[root + 1]; --beg; } while (tree[root * 2] || tree[root * 2 + 1]) { root *= 2; ans -= tree[root + 1]; } cout << ans << endl; } int main() { cin >> t; for (int i = 1; i <= t; ++i) { cin >> opt; if (opt == + ) { long long x; cin >> x; insert(x); } else if (opt == - ) { long long x; cin >> x; erase(x); } else { string s; cin >> s; query(s); } } } |
#include <bits/stdc++.h> using namespace std; int n, m, l[2001], s[2001], c[4001]; int f[4001][2001]; int main() { scanf( %d%d , &n, &m); m += n; for (int i = n; i >= 1; i -= 1) scanf( %d , &l[i]); for (int i = n; i >= 1; i -= 1) scanf( %d , &s[i]); for (int i = 1; i <= m; i += 1) scanf( %d , &c[i]); for (int i = 1; i <= m; i += 1) { for (int j = 1; j <= n; j += 1) f[i][j] = -1e9; } for (int i = 1; i <= n; i += 1) { for (int j = n; j >= 1; j -= 1) { f[l[i]][j] = max(f[l[i]][j], f[l[i]][j - 1] - s[i] + c[l[i]]); } for (int j = l[i]; j < m; j += 1) { for (int k = 0; k <= (n >> j - l[i]); k += 1) { f[j + 1][k >> 1] = max(f[j + 1][k >> 1], f[j][k] + c[j + 1] * (k >> 1)); } } } printf( %d n , f[m][0]); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.2
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module types_float_double_grp_fu_100_ACMP_dsqrt_4_io(
clk,
reset,
io_ce,
io_rdy,
io_a,
io_b,
io_result);
input clk;
input reset;
input io_ce;
output io_rdy;
input[64 - 1:0] io_a;
input[64 - 1:0] io_b;
output[64 - 1:0] io_result;
sqrt64fp m(
.clk(clk),
.ce(io_ce),
.rdy(io_rdy),
.a(io_a),
.result(io_result));
endmodule
module sqrt64fp(
clk,
ce,
rdy,
a,
result);
input clk;
input ce;
output rdy;
input[64 - 1:0] a;
output[64 - 1:0] result;
//assign result = a + b;
//ACMP_ddiv #(
//.ID( ID ),
//.NUM_STAGE( 59 ),
//.din0_WIDTH( din0_WIDTH ),
//.din1_WIDTH( din1_WIDTH ),
//.dout_WIDTH( dout_WIDTH ))
//ACMP_ddiv_U(
// .clk( clk ),
// .reset( reset ),
// .ce( ce ),
// .din0( din0 ),
// .din1( din1 ),
// .dout( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, kk; cin >> n >> kk; vector<string> v(n); unordered_map<string, int> mp; for (int i = 0; i < n; i++) { cin >> v[i]; mp[v[i]]++; } int ans = 0; string req; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { req = ; for (int k = 0; k < kk; k++) { if (v[i][k] == v[j][k]) req.push_back(v[i][k]); else { if (v[i][k] == T && v[j][k] == T ) req.push_back( T ); if (v[i][k] == S && v[j][k] == S ) req.push_back( S ); if (v[i][k] == E && v[j][k] == E ) req.push_back( E ); if (v[i][k] == T && v[j][k] == S ) req.push_back( E ); if (v[i][k] == S && v[j][k] == T ) req.push_back( E ); if (v[i][k] == T && v[j][k] == E ) req.push_back( S ); if (v[i][k] == E && v[j][k] == T ) req.push_back( S ); if (v[i][k] == S && v[j][k] == E ) req.push_back( T ); if (v[i][k] == E && v[j][k] == S ) req.push_back( T ); } } if (mp[req]) ans++; } } cout << ans / 3 << endl; } signed main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> Max[3005][3005]; struct ans { int a, b, c; int i, j, k; ans(int _a, int _b, int _c, int _i, int _j, int _k) { a = _a; b = _b; c = _c; i = _i; j = _j; k = _k; } }; bool operator<(const ans &a, const ans &b) { if (a.a != b.a) return a.a < b.a; else if (a.b != b.b) return a.b < b.b; else return a.c < b.c; } int main() { int n; scanf( %d , &n); pair<int, int> a[3005]; memset(Max, -1, sizeof(Max)); for (int i = 0; i < n; i++) { int first; scanf( %d , &first); a[i] = make_pair((first), (i)); } sort(a, a + n); reverse(a, a + n); a[n] = make_pair((0), (n)); for (int i = 0; i < n; i++) { for (int j = i + 1; j <= n; j++) { Max[i][j - 1] = max(Max[i][j - 2], make_pair((a[j - 1].first - a[j].first), (j))); } } ans aa = ans{-1, -1, -1, 0, 0, 0}; for (int i = 1; i <= n; i++) { for (int j = (i + 1) / 2; j <= i * 2 && i + j <= n; j++) { int l = max((i + 1) / 2, (j + 1) / 2), r = min(i * 2, j * 2); l += i + j; r += i + j; l--; r--; if (l >= n) continue; if (r >= n) r = n - 1; aa = max(aa, ans(a[i - 1].first - a[i].first, a[i + j - 1].first - a[i + j].first, Max[l][r].first, i, i + j, Max[l][r].second)); } } int ans[3005]; memset(ans, -1, sizeof(ans)); for (int i = 0; i < aa.i; i++) ans[a[i].second] = 1; for (int i = aa.i; i < aa.j; i++) ans[a[i].second] = 2; for (int i = aa.j; i < aa.k; i++) ans[a[i].second] = 3; for (int i = 0; i < n; i++) printf( %d , ans[i]); printf( n ); } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dec_table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dec_table (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "dec_table.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "dec_table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "dec_table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(0.0) * 2.0; const long double eps = 1e-10; const int step[8][2] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}, {-1, 1}, {1, 1}, {1, -1}, {-1, -1}}; template <class T> inline T abs1(T a) { return a < 0 ? -a : a; } template <typename t, typename t1> t min1(t a, t1 b) { return a < b ? a : b; } template <typename t, typename... arg> t min1(t a, arg... arr) { return min1(a, min1(arr...)); } template <typename t, typename t1> t max1(t a, t1 b) { return a > b ? a : b; } template <typename t, typename... arg> t max1(t a, arg... arr) { return max1(a, max1(arr...)); } inline int jud(double a, double b) { if (abs(a) < eps && abs(b) < eps) return 0; else if (abs1(a - b) / abs1(a) < eps) return 0; if (a < b) return -1; return 1; } template <typename t> inline int jud(t a, t b) { if (a < b) return -1; if (a == b) return 0; return 1; } template <typename it, typename t1> inline int find(t1 val, it a, int na, bool f_small = 1, bool f_lb = 1) { int be = 0, en = na - 1; if (*a <= *(a + na - 1)) { if (f_lb == 0) while (be < en) { int mid = (be + en + 1) / 2; if (jud(*(a + mid), val) != 1) be = mid; else en = mid - 1; } else while (be < en) { int mid = (be + en) / 2; if (jud(*(a + mid), val) != -1) en = mid; else be = mid + 1; } if (f_small && jud(*(a + be), val) == 1) be--; if (!f_small && jud(*(a + be), val) == -1) be++; } else { if (f_lb) while (be < en) { int mid = (be + en + 1) / 2; if (jud(*(a + mid), val) != -1) be = mid; else en = mid - 1; } else while (be < en) { int mid = (be + en) / 2; if (jud(*(a + mid), val) != 1) en = mid; else be = mid + 1; } if (!f_small && jud(*(a + be), val) == -1) be--; if (f_small && jud(*(a + be), val) == 1) be++; } return be; } template <class T> inline T lowb(T num) { return num & (-num); } inline int bitnum(unsigned int nValue) { return __builtin_popcount(nValue); } inline int bitnum(int nValue) { return __builtin_popcount(nValue); } inline int bitnum(unsigned long long nValue) { return __builtin_popcount(nValue) + __builtin_popcount(nValue >> 32); } inline int bitnum(long long nValue) { return __builtin_popcount(nValue) + __builtin_popcount(nValue >> 32); } inline int bitmaxl(unsigned int a) { if (a == 0) return 0; return 32 - __builtin_clz(a); } inline int bitmaxl(int a) { if (a == 0) return 0; return 32 - __builtin_clz(a); } inline int bitmaxl(unsigned long long a) { int temp = a >> 32; if (temp) return 32 - __builtin_clz(temp) + 32; return bitmaxl(int(a)); } inline int bitmaxl(long long a) { int temp = a >> 32; if (temp) return 32 - __builtin_clz(temp) + 32; return bitmaxl(int(a)); } long long pow(long long n, long long m, long long mod = 0) { if (m < 0) return 0; long long ans = 1; long long k = n; while (m) { if (m & 1) { ans *= k; if (mod) ans %= mod; } k *= k; if (mod) k %= mod; m >>= 1; } return ans; } template <class t1, class t2> inline void add(t1 &a, t2 b, int mod = -1) { if (mod == -1) mod = 1000000007; a += b; while (a >= mod) a -= mod; while (a < 0) a += mod; } template <class t> void output1(t arr) { for (int i = 0; i < (int)arr.size(); i++) cerr << arr[i] << ; cerr << endl; } template <class t> void output2(t arr) { for (int i = 0; i < (int)arr.size(); i++) output1(arr[i]); } const int maxn = 100100; struct edge { int to, nxt, val; } e[maxn * 2]; int head[maxn], le; int fa[maxn], anc[maxn], sz[maxn], hv[maxn], deep[maxn], loc[maxn]; int orig[maxn], lorig; int n, nq; int f[maxn]; pair<int, int> st[2][maxn]; int lst[2]; int ans[maxn]; struct node { int a, b, cate; int yul; bool operator<(const node &a) const { if (yul == a.yul) return cate < a.cate; return yul < a.yul; } } arr[maxn * 2]; int larr; struct segment_node { int be, en; int sumv, lef, rig; bool flag; }; struct segment_tree { int l; segment_node tree[maxn * 4]; inline int gleft(int no) { return no << 1; } inline int gright(int no) { return (no << 1) + 1; } inline int gfa(int no) { return no >> 1; } inline segment_tree() { l = 0; } void build(int no, int l, int r, int orig = 0, int *a = NULL) { if (l > r) r = l; if (l == r) { tree[no].be = tree[no].en = l; tree[no].sumv = 0; tree[no].lef = tree[no].rig = 0; tree[no].flag = 0; return; } tree[no].be = l; tree[no].en = r; int mid = (l + r) / 2; build(gleft(no), l, mid, orig, a); build(gright(no), mid + 1, r, orig, a); tree[no].sumv = 0; tree[no].lef = tree[no].rig = 0; } inline void pushup(segment_node *no, segment_node *nl, segment_node *nr) { if (nl->flag && nr->flag) { no->lef = no->rig = nr->lef + nl->rig; no->sumv = 0; no->flag = 1; return; } if (nl->flag && nl->lef == 0) { memcpy(no, nr, sizeof(segment_node)); return; } if (nr->flag && nr->lef == 0) { memcpy(no, nl, sizeof(segment_node)); return; } no->flag = 0; if (nl->flag) { no->lef = nr->lef + nl->rig; no->rig = nr->rig; no->sumv = nr->sumv; return; } if (nr->flag) { no->lef = nl->lef; no->rig = nl->rig + nr->lef; no->sumv = nl->sumv; return; } no->lef = nl->lef; no->rig = nr->rig; no->sumv = nl->sumv + nr->sumv + f[nl->rig + nr->lef]; } void down(int loc, int no) { if (loc <= tree[no].be && loc >= tree[no].en) { tree[no].rig = tree[no].lef = 1; tree[no].flag = 1; tree[no].sumv = 0; return; } int mid = (tree[no].be + tree[no].en) >> 1; if (loc <= mid) down(loc, gleft(no)); else down(loc, gright(no)); pushup(tree + no, tree + gleft(no), tree + gright(no)); } void getsum(int l, int r, int no, int pp1) { if (l > r) return; int pp2 = pp1 + 100; if (l <= tree[no].be && r >= tree[no].en) { pushup(tree + pp2, tree + pp1, tree + no); tree[pp1] = tree[pp2]; return; } int mid = (tree[no].be + tree[no].en) >> 1; if (r >= tree[no].be && l <= mid) getsum(l, r, gleft(no), pp1); if (r >= mid + 1 && l <= tree[no].en) getsum(l, r, gright(no), pp1); } } sgt; void dfs(int no) { sz[no] = 1; hv[no] = -1; for (int i = head[no]; i != -1; i = e[i].nxt) if (e[i].to != fa[no]) { fa[e[i].to] = no; deep[e[i].to] = deep[no] + 1; dfs(e[i].to); sz[no] += sz[e[i].to]; if (hv[no] == -1 || sz[hv[no]] < sz[e[i].to]) hv[no] = e[i].to; } } void dfs1(int no) { orig[lorig] = no; loc[no] = lorig++; if (hv[no] != -1) { anc[hv[no]] = anc[no]; dfs1(hv[no]); } for (int i = head[no]; i != -1; i = e[i].nxt) if (e[i].to != fa[no] && e[i].to != hv[no]) { anc[e[i].to] = e[i].to; dfs1(e[i].to); } } void addedge(int a, int b, int c) { e[le].to = b; e[le].nxt = head[a]; e[le].val = c; head[a] = le++; } int main() { ios_base::sync_with_stdio(0); memset(head, -1, sizeof(head)); scanf( %d%d , &n, &nq); for (int i = 1; i < n; i++) scanf( %d , f + i); for (int i = 0; i < n - 1; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); a--; b--; addedge(a, b, c); addedge(b, a, c); arr[i].a = a; arr[i].b = b; arr[i].yul = -c; arr[i].cate = -(i + 1); } sgt.build(1, 0, n); dfs(0); dfs1(0); for (int i = 0; i < nq; i++) { scanf( %d%d%d , &arr[i + n - 1].a, &arr[i + n - 1].b, &arr[i + n - 1].yul); arr[i + n - 1].cate = i; arr[i + n - 1].a--; arr[i + n - 1].b--; arr[i + n - 1].yul = -arr[i + n - 1].yul; } sort(arr, arr + nq + n - 1); for (int i = 0; i < nq + n - 1; i++) { if (arr[i].cate < 0) { int no = arr[i].a; if (deep[arr[i].b] > deep[no]) no = arr[i].b; sgt.down(loc[no], 1); } else { int a = arr[i].a, b = arr[i].b; int l = 0; lst[0] = lst[1] = 0; while (anc[a] != anc[b]) { int no = a, cate = 0; if (deep[anc[a]] < deep[anc[b]]) { no = b; cate = 1; } st[cate][lst[cate]++] = make_pair(loc[anc[no]], loc[no]); l += abs(loc[anc[no]] - loc[no]) + 1; if (deep[anc[a]] < deep[anc[b]]) b = fa[anc[no]]; else a = fa[anc[no]]; } if (a != b) { if (deep[a] > deep[b]) st[0][lst[0]++] = make_pair(loc[b] + 1, loc[a]); else st[1][lst[1]++] = make_pair(loc[a] + 1, loc[b]); l += abs(deep[a] - deep[b]); } int ff1 = 400000, ff2 = ff1 + 1, ff3 = ff1 + 2; sgt.tree[ff1].rig = sgt.tree[ff1].lef = sgt.tree[ff1].sumv = 0; sgt.tree[ff1].flag = 1; sgt.tree[ff2].rig = sgt.tree[ff2].lef = sgt.tree[ff2].sumv = 0; sgt.tree[ff2].flag = 1; for (int i = lst[0] - 1; i >= 0; i--) sgt.getsum(st[0][i].first, st[0][i].second, 1, ff1); for (int i = lst[1] - 1; i >= 0; i--) sgt.getsum(st[1][i].first, st[1][i].second, 1, ff2); swap(sgt.tree[ff1].lef, sgt.tree[ff1].rig); sgt.pushup(sgt.tree + ff3, sgt.tree + ff1, sgt.tree + ff2); int rans = sgt.tree[ff3].sumv + f[sgt.tree[ff3].lef]; if (!sgt.tree[ff3].flag) rans += f[sgt.tree[ff3].rig]; ans[arr[i].cate] = rans; } } for (int i = 0; i < nq; i++) printf( %d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; struct Node { string str; int pos; friend bool operator<(Node const& n1, Node const& n2) { return n2.str < n1.str; } }; priority_queue<Node> que; int main() { int k; string str; cin >> str; cin >> k; que.push({string{ z + 1}, INF}); for (int i = 0; i < str.size(); ++i) { que.push({string{str[i]}, i}); } Node i; while (k-- && !que.empty()) { i = que.top(); que.pop(); if (i.pos == str.size() - 1 || i.pos == INF) continue; que.push({i.str + str[i.pos + 1], i.pos + 1}); } if (k && que.empty()) cout << No such line. << endl; else cout << i.str << endl; } |
#include <bits/stdc++.h> using namespace std; void debug_out() { cerr << n ; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } const long long MAXN = 1e2 + 10, INF = 1e9; long long n, m, k, a, b, u, v, floyd[MAXN][MAXN], second[MAXN], t[MAXN], dp[2][MAXN]; bool bo[MAXN][MAXN]; vector<long long> h[MAXN]; void update(long long id) { if (floyd[second[id]][t[id]] == INF) return; for (long long i = 0; i <= floyd[second[id]][t[id]]; i++) h[i].clear(); for (long long i = 1; i <= n; i++) dp[1][i] = INF; for (long long i = 1; i <= n; i++) if (floyd[second[id]][i] + floyd[i][t[id]] == floyd[second[id]][t[id]]) h[floyd[second[id]][i]].push_back(i); dp[1][t[id]] = dp[0][t[id]]; for (long long i = floyd[second[id]][t[id]] - 1; i >= 0; i--) { for (auto u : h[i]) { dp[1][u] = -1; for (auto v : h[i + 1]) if (bo[u][v]) dp[1][u] = max(dp[1][u], dp[1][v]); if (dp[1][u] == -1) dp[1][u] = dp[0][u]; else dp[1][u] = min(dp[1][u], dp[0][u]); } if ((long long)h[i].size() == 1) dp[0][h[i][0]] = min(dp[0][h[i][0]], dp[1][h[i][0]] + 1); } return; } void pre_Floyd() { for (long long i = 1; i <= n; i++) for (long long j = 1; j <= n; j++) floyd[i][j] = INF, floyd[j][j] = 0; return; } void Floyd_update() { for (long long k = 1; k <= n; k++) for (long long i = 1; i <= n; i++) for (long long j = 1; j <= n; j++) floyd[i][j] = min(floyd[i][j], floyd[i][k] + floyd[k][j]); return; } int32_t main() { cin >> n >> m >> a >> b, pre_Floyd(); for (long long i = 1; i <= n; i++) dp[0][i] = INF; for (long long i = 1; i <= m; i++) cin >> u >> v, floyd[u][v] = 1, bo[u][v] = true; cin >> k; for (long long i = 1; i <= k; i++) cin >> second[i] >> t[i]; Floyd_update(), dp[0][b] = 0; for (long long i = 1; i <= n; i++) for (long long j = 1; j <= k; j++) update(j); if (dp[0][a] == INF) return cout << -1 << n , 0; return cout << dp[0][a] << n , 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 3 * 100002; int a[N], pr[N]; ll cnt[N]; map<int, int> s[N]; int main() { int q; cin >> q; while (q--) { ll ans = 0; int n; cin >> n; for (int i = 0; i <= n; i++) { pr[i] = -1; s[i].clear(); } for (int i = 1; i <= n; i++) { cnt[i] = 0; cin >> a[i]; if (i != 1) { if (pr[i - 1] != -1) { swap(s[i], s[pr[i - 1]]); s[i][a[pr[i - 1] - 1]] = pr[i - 1] - 1; } if (s[i][a[i]]) pr[i] = s[i][a[i]]; else pr[i] = -1; if (a[i] == a[i - 1]) pr[i] = i - 1; } if (pr[i] != -1) cnt[i] = cnt[pr[i] - 1] + 1; ans += cnt[i]; } cout << ans << n ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Driss Hafdi
// SPDX-License-Identifier: CC0-1.0
interface validData
(
input wire clk,
input wire rst
);
logic data;
logic valid;
modport sink
(
input data, valid, clk, rst
);
modport source
(
input clk, rst,
output data, valid
);
endinterface
module sinkMod
(
validData.sink ctrl,
output logic valid_data
);
always_ff @(posedge ctrl.clk) begin
if (ctrl.valid) valid_data <= ctrl.data;
end
endmodule
module sourceMod
(
validData.source ctrl
);
always_ff @(posedge ctrl.clk) begin
ctrl.data <= ~ctrl.data;
ctrl.valid <= ~ctrl.valid;
end
endmodule
module parentSourceMod
(
validData.sink ctrl
);
sourceMod source_i (.ctrl);
endmodule
module t (/*AUTOARG*/
// Outputs
data,
// Inputs
clk, rst
);
input clk;
input rst;
output logic data;
validData ctrl(.clk, .rst);
sinkMod sink_i (.ctrl, .valid_data(data));
parentSourceMod source_i (.ctrl);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A41O_FUNCTIONAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_FUNCTIONAL_V |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module performs a rounding of a floating-point number.
module acl_fp_custom_round(
clock, resetn, mantissa, exponent, sign, mantissa_out, exponent_out, sign_out,
valid_in, valid_out, stall_in, stall_out, enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [27:0] mantissa;
input [8:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [27:0] mantissa_out; // When mantissa_out[25] = 1 and exponent_out[8] == 1 then the number is NaN.
output [8:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
reg c1_valid;
reg c2_valid;
wire c1_stall;
wire c2_stall;
wire c1_enable;
wire c2_enable;
// Cycle 1 - first check for overflow. Shift data right by one bit if this is the case.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c1_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c1_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_rounding_required;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exponent_is_max;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exponent_is_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_input_man_27;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 27'dx;
c1_exponent <= 9'dx;
c1_sign <= 1'bx;
c1_rounding_required <= 1'bx;
c1_exponent_is_max <= 1'bx;
c1_exponent_is_nonzero <= 1'bx;
c1_input_man_27 <= 1'bx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent_is_max <= (&exponent[7:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[7:0];
c1_input_man_27 <= mantissa[27];
// Here is where we decide on when to round. In ROUND_TO_NEAREST mode, we need to round
// when shifting to the left does not move all of 1 out of guard, round and sticky bits.
if ((exponent[8]) || (~mantissa[27] && (mantissa[26:24] == 3'b000) && (exponent[7:0] >= 8'd4)) ||
(mantissa[27] && (&exponent[7:1])))
c1_rounding_required <= 1'b0;
else
c1_rounding_required <= 1'b1;
// I am going to split this computation over two clock cycles.
if (exponent[8] || ~mantissa[27])
c1_mantissa <= mantissa[26:0];
else
c1_mantissa <= {mantissa[27:2], |mantissa[1:0]};
if (mantissa[27] & &exponent[7:1] & ~exponent[8])
c1_exponent <= 9'h1ff;
else
c1_exponent <= exponent;
end
end
// Cycle 2 - Compute any necessary rounding and apply it.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] c2_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c2_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [2:0] rounding_value;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_sign;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
always@(*)
begin
if (c1_rounding_required)
begin
// If we need rounding then the nice thing is that we know a shift of at most 4 will take place.
if (c1_mantissa[26] && (c1_mantissa[2]) && (c1_mantissa[3] | (|c1_mantissa[1:0])))
begin
rounding_value = 3'b100;
end
else if (c1_mantissa[25] && (c1_mantissa[1]) && (c1_mantissa[2] | (c1_mantissa[0])))
begin
rounding_value = 3'b010;
end
else if (c1_mantissa[24] && (c1_mantissa[0] & c1_mantissa[1]))
begin
rounding_value = 3'b001;
end
else
begin
rounding_value = 3'b000;
end
end
else
begin
// If no rounding is needed, then we can shift the mantissa by 4 positions if it is possible.
rounding_value = 3'b000;
end
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_mantissa <= 28'dx;
c2_exponent <= 9'dx;
c2_sign <= 1'bx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
if (c1_exponent_is_max & c1_input_man_27)
c2_mantissa <= 28'd0;
else
c2_mantissa <= c1_mantissa + rounding_value;
if (c1_exponent[8])
c2_exponent <= c1_exponent;
else
c2_exponent <= c1_exponent + {1'b0, c1_input_man_27 & ~c1_exponent_is_nonzero,
c1_input_man_27 & c1_exponent_is_nonzero | ~c1_input_man_27 & c1_mantissa[26] & ~c1_exponent_is_nonzero};
end
end
assign mantissa_out = c2_mantissa;
assign exponent_out = c2_exponent;
assign sign_out = c2_sign;
assign valid_out = c2_valid;
assign c2_stall = stall_in;
endmodule
|
module computation(clk, asel, bsel, loadc, loads, shift, ALUop, A, B, sximm5, status, C);
parameter width= 1;
parameter statusWidth= 3;
input clk, asel, bsel, loadc, loads;
input [1:0] shift, ALUop;
input [15:0] A, B, sximm5;
output [2:0] status;
output [15:0] C;
wire [2:0] statusComputed;
wire overflow;
wire [15:0] Ain, Bin, BShift, ALUComputedValue;
//if asel= 0 set Ain= A value else set Ain= 0s
assign Ain= asel? {width{1'b0}}: A;
//if bsel= 0 set Bin= to shifted B value else set Bin= to 11bits 0s + first 5 bits of datapath_in
assign Bin= bsel? sximm5: BShift;
//Clock updates for status and C
DFlipFlopAllow #(statusWidth) loadStatusData(clk, loads, statusComputed, status); //status= running on a clock
DFlipFlopAllow #(width) loadCData(clk, loadc, ALUComputedValue, C); //C= running on a clock
//Shift Operations
shift #(width) instantiateShift(
.B(B),
.BShift(BShift),
.shift(shift)
);
//ALU Operations
ALU #(width) instantiateALU(
.ALUop(ALUop),
.Ain(Ain),
.Bin(Bin),
.ALUComputedValue(ALUComputedValue),
.overflow(overflow)
);
//status Update
status #(width) instantiateStatus(
.ALUComputedValue(ALUComputedValue),
.status(statusComputed),
.overflow(overflow)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int size(long long a) { int c = 0; while (a != 0) { c++; a /= 10; } return c; } int main() { long long a, b, c; cin >> a >> b; long long s = size(b), ns = 1; for (int i = 1; i <= s; i++) ns *= 10; s = ns; while (b != 0) { long long f = b % 10; b /= 10; s /= 10; a += s * f; } cout << a; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { if (j % i == 0 && i * j > n && j < n * i) return cout << j << << i, 0; } } cout << -1; } |
#include <bits/stdc++.h> using namespace std; int m, n, arr[200][200]; int color(int x, int y) { int col = 1; while (arr[x - 1][y] == col or arr[x][y - 1] == col or arr[x + 1][y] == col or arr[x][y + 1] == col) col++; return col; } int color2(int x, int y) { int col = 1; while (arr[x - 1][y] == col or arr[x + 1][y] == col or arr[x][y + 1] == col) col++; return col; } int fit(int x, int y, int col) { if (arr[x][y - 1] == col or arr[x + 1][y] == col or arr[x][y + 1] == col) return 0; return 1; } int main() { cin >> m >> n; int x = 1, y = 1; while (x <= m) { if (y == n + 1) { x++; y = 1; continue; } if (arr[x][y]) { y++; continue; } int xx = x, yy = y, col = color(x, y); arr[x][y] = col; while (xx + 1 <= m and yy + 1 <= n and !arr[xx + 1][y] and !arr[x][yy + 1] and fit(xx + 1, y, col) and color2(x, yy + 1) == col) xx++, yy++; for (int i = x; i <= xx; i++) for (int j = y; j <= yy; j++) arr[i][j] = col; } for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) printf( %c , (char)(arr[i][j] + A - 1)); puts( ); } } |
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult30_9.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mult30_9 (
clock,
dataa,
datab,
result);
input clock;
input [29:0] dataa;
input [8:0] datab;
output [38:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "30"
// Retrieval info: PRIVATE: WidthB NUMERIC "9"
// Retrieval info: PRIVATE: WidthP NUMERIC "39"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "30"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "39"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 30 0 INPUT NODEFVAL dataa[29..0]
// Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL datab[8..0]
// Retrieval info: USED_PORT: result 0 0 39 0 OUTPUT NODEFVAL result[38..0]
// Retrieval info: CONNECT: @dataa 0 0 30 0 dataa 0 0 30 0
// Retrieval info: CONNECT: result 0 0 39 0 @result 0 0 39 0
// Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult30_9_wave*.jpg FALSE
// Retrieval info: LIB_FILE: lpm
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module cf_adc_wr (
// adc interface (clk, data, over-range)
adc_clk_in,
adc_data_in,
adc_or_in,
// interface outputs
adc_clk,
adc_valid,
adc_data,
adc_or,
adc_pn_oos,
adc_pn_err,
// processor control signals
up_pn_type,
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
// delay control signals
delay_clk,
delay_ack,
delay_rdata,
delay_locked,
// adc debug and monitor signals (for chipscope)
adc_mon_valid,
adc_mon_data);
// This parameter controls the buffer type based on the target device.
parameter C_CF_BUFTYPE = 0;
// adc interface (clk, data, over-range)
input adc_clk_in;
input [13:0] adc_data_in;
input adc_or_in;
// interface outputs
output adc_clk;
output adc_valid;
output [63:0] adc_data;
output adc_or;
output adc_pn_oos;
output adc_pn_err;
// processor control signals
input up_pn_type;
input up_delay_sel;
input up_delay_rwn;
input [ 3:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
// delay control signals
input delay_clk;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
// adc debug and monitor signals (for chipscope)
output adc_mon_valid;
output [15:0] adc_mon_data;
reg [ 1:0] adc_count = 'd0;
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
wire [13:0] adc_data_if_s;
assign adc_mon_valid = 1'b1;
assign adc_mon_data = {2'd0, adc_data_if_s};
always @(posedge adc_clk) begin
adc_count <= adc_count + 1'b1;
adc_valid <= adc_count[0] & adc_count[1];
adc_data <= {2'd0, adc_data_if_s, adc_data[63:16]};
end
// PN sequence monitor
cf_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err),
.up_pn_type (up_pn_type));
// ADC data interface
cf_adc_if #(.C_CF_BUFTYPE (C_CF_BUFTYPE)) i_adc_if (
.adc_clk_in (adc_clk_in),
.adc_data_in (adc_data_in),
.adc_or_in (adc_or_in),
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_or (adc_or),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.delay_clk (delay_clk),
.delay_ack (delay_ack),
.delay_rdata (delay_rdata),
.delay_locked (delay_locked));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 6; int n, k, h[N]; long long p, m, t, a[N], b[N]; struct xd { int z, i; bool operator<(const xd &d) const { return z > d.z; } } tmp, nw; inline int read() { int T = 0, F = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) F = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) T = (T << 3) + (T << 1) + (ch - 48), ch = getchar(); return F * T; } bool check(long long x) { priority_queue<xd> q; memset(b, 0, sizeof(b)); for (int i = 1; i <= n; ++i) if (x - a[i] * m < h[i]) tmp.z = x / a[i], tmp.i = i, q.push(tmp); for (int i = 1; i <= m && !q.empty(); ++i) for (int j = 1; j <= k && !q.empty(); ++j) { tmp = q.top(), q.pop(); if (tmp.z < i) return 0; ++b[tmp.i]; if (x + b[tmp.i] * p - a[tmp.i] * m < h[tmp.i]) tmp.z = (x + b[tmp.i] * p) / a[tmp.i], q.push(tmp); } return q.empty(); } long long ef(long long l, long long r) { if (l == r) return l; long long mid = l + r >> 1ll; if (check(mid)) return ef(l, mid); return ef(mid + 1, r); } int main() { n = read(), m = read(), k = read(), p = read(); for (int i = 1; i <= n; ++i) h[i] = read(), a[i] = read(); printf( %lld n , ef(0, 5e12 + 1e9 + 1)); return 0; } |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_div.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU divider; building block used by several other APU components. Outputs a pulse every n input
* pulses, where n is the divider's period. It contains a counter which is decremented on the
* arrival of each pulse. When the counter reaches 0, it is reloaded with the period and an output
* pulse is generated. A divider can also be forced to reload its counter immediately, but this
* does not output a pulse. When a divider's period is changed, the current count is not affected.
*
* apu_div_const is a variation on apu_div that has an immutable period.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_div
#(
parameter PERIOD_BITS = 16
)
(
input clk_in, // system clock signal
input rst_in, // reset signal
input pulse_in, // input pulse
input reload_in, // reset counter to period_in (no pulse_out generated)
input [PERIOD_BITS-1:0] period_in, // new period value
output pulse_out // divided output pulse
);
reg [PERIOD_BITS-1:0] q_cnt;
wire [PERIOD_BITS-1:0] d_cnt;
always @(posedge clk_in)
begin
if (rst_in)
q_cnt <= 0;
else
q_cnt <= d_cnt;
end
assign d_cnt = (reload_in || (pulse_in && (q_cnt == 0))) ? period_in :
(pulse_in) ? q_cnt - 1'h1 : q_cnt;
assign pulse_out = pulse_in && (q_cnt == 0);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <typename T> void ckmn(T& a, T b) { a = min(a, b); } template <typename T> void ckmx(T& a, T b) { a = max(a, b); } void rd(int& x) { scanf( %i , &x); } void rd(long long& x) { scanf( %lld , &x); } void rd(char* x) { scanf( %s , x); } void rd(double& x) { scanf( %lf , &x); } void rd(string& x) { scanf( %s , &x); } template <typename T1, typename T2> void rd(pair<T1, T2>& x) { rd(x.first); rd(x.second); } template <typename T> void rd(vector<T>& x) { for (T& i : x) rd(i); } template <typename T, typename... A> void rd(T& x, A&... args) { rd(x); rd(args...); } template <typename T> void rd() { T x; rd(x); return x; } int ri() { int x; rd(x); return x; } template <typename T> vector<T> rv(int n) { vector<T> x(n); rd(x); return x; } template <typename T> void ra(T a[], int n, int st = 1) { for (int i = 0; i < n; ++i) rd(a[st + i]); } template <typename T1, typename T2> void ra(T1 a[], T2 b[], int n, int st = 1) { for (int i = 0; i < n; ++i) rd(a[st + i]), rd(b[st + i]); } template <typename T1, typename T2, typename T3> void ra(T1 a[], T2 b[], T3 c[], int n, int st = 1) { for (int i = 0; i < n; ++i) rd(a[st + i]), rd(b[st + i]), rd(c[st + i]); } void re(vector<int> E[], int m, bool dir = 0) { for (int i = 0, u, v; i < m; ++i) { rd(u, v); E[u].push_back(v); if (!dir) E[v].push_back(u); } } template <typename T> void re(vector<pair<int, T>> E[], int m, bool dir = 0) { for (int i = 0, u, v; i < m; ++i) { T w; rd(u, v, w); E[u].push_back({v, w}); if (!dir) E[v].push_back({u, w}); } } int main() { for (int t = ri(); t--;) { int n = ri(); vector<int> a(n + 1, 0); vector<vector<int>> ids(n + 1, vector<int>()); for (int i = 1; i <= n; i++) { rd(a[i]); ids[a[i]].push_back(i); } vector<vector<int>> dp(n + 1, vector<int>(n + 1, 0)); vector<vector<bool>> was(n + 1, vector<bool>(n + 1, false)); function<int(int, int)> Solve = [&](int l, int r) { if (l > r) return 0; if (was[l][r]) return dp[l][r]; was[l][r] = 1; if (l == r) return dp[l][r] = 1; dp[l][r] = Solve(l + 1, r) + 1; for (int i : ids[a[l]]) if (i > l && i <= r) { ckmn(dp[l][r], Solve(l + 1, i - 1) + Solve(i, r)); } return dp[l][r]; }; printf( %i n , Solve(1, n) - 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; string s, v; bool g(char k) { return (k == a || k == e || k == i || k == o || k == u ); } int main() { ios_base::sync_with_stdio(0); cin >> s; long long tek = 0; char t1 = - , t2 = - ; for (long long i = 0; i < s.size(); i++) { if (!g(s[i])) { if (t1 == - ) { t1 = s[i]; ++tek; v += s[i]; } else if (t2 == - ) { t2 = s[i]; ++tek; v += s[i]; } else if (s[i] == t1 && s[i] == t2) { ++tek; v += s[i]; } else { char k = s[i]; v += ; cout << v; t1 = k; t2 = - ; tek = 1; v = ; v += t1; } } else { t1 = - ; t2 = - ; tek = 0; v += s[i]; } } cout << v; } |
#include <bits/stdc++.h> using namespace std; int main() { int v0, v1, v2, vm, a0, a1, a2; bool err = true; scanf( %d%d%d%d , &v2, &v1, &v0, &vm); for (int i = v0; i <= v0 * 2; i++) { for (int j = v1; j <= v1 * 2; j++) { for (int k = v2; k <= v2 * 2; k++) { if (vm <= i && vm <= j && vm <= k && i < j && j < k && vm * 2 >= i && vm * 2 < j) { a0 = k; a1 = j; a2 = i; err = false; break; } } } } if (err) { printf( -1 n ); } else { printf( %d n%d n%d n , a0, a1, a2); } return 0; } |
#include <bits/stdc++.h> using namespace std; int sum[64]; long long a[200200]; long long calc() { long long ans = 0; for (int i = 0; i < 64; i++) { ans += (1LL << i) * (sum[i] > 0); } return ans; } int main() { int n, k, x; cin >> n >> k >> x; for (int i = 1; i <= n; i++) { scanf( %I64d , a + i); for (int j = 0; j < 32; j++) { sum[j] += ((a[i] >> j) & 1LL); } } long long ans = calc(); for (int i = 1; i <= n; i++) { for (int j = 0; j < 32; j++) { sum[j] -= ((a[i] >> j) & 1LL); } long long b = a[i]; for (int j = 0; j < k; j++) b *= x; for (int j = 0; j < 64; j++) { sum[j] += ((b >> j) & 1LL); } ans = max(ans, calc()); for (int j = 0; j < 32; j++) { sum[j] += ((a[i] >> j) & 1LL); } for (int j = 0; j < 64; j++) { sum[j] -= ((b >> j) & 1LL); } } cout << ans << endl; return 0; } |
module heater # (
parameter integer C_HEAT_VALUE_WIDTH = 12,
parameter integer C_HEAT_TIME_WIDTH = 32
) (
input wire clk,
input wire resetn,
input wire ext_autostart,
output wire power,
output wire en,
output wire fan,
input wire [15:0] s_axis_tdata,
input wire [4:0] s_axis_tid,
output wire s_axis_tready,
input wire s_axis_tvalid,
output wire [2-1 :0] run_state,
output wire [C_HEAT_VALUE_WIDTH-1:0] run_value,
input wire auto_start,
input wire auto_hold ,
input wire [C_HEAT_VALUE_WIDTH-1:0] holdv ,
input wire [C_HEAT_VALUE_WIDTH-1:0] keep_value,
input wire [C_HEAT_TIME_WIDTH-1 :0] keep_time ,
input wire [C_HEAT_VALUE_WIDTH-1:0] finishv ,
input wire start ,
input wire stop
);
localparam integer IDLE = 2'b00;
localparam integer RUNNING = 2'b01;
localparam integer WAITING = 2'b11;
localparam integer C_TEST = 1'b0;
reg[1:0] __state;
reg[C_HEAT_TIME_WIDTH-1:0] __time;
reg[C_HEAT_VALUE_WIDTH-1:0] __up_v;
reg[C_HEAT_VALUE_WIDTH-1:0] __low_v;
reg[C_HEAT_VALUE_WIDTH-1:0] __v;
reg __en;
always @ (posedge clk) begin
if (resetn == 1'b0)
__state <= IDLE;
else begin
case (__state)
IDLE: begin
if (start /* check auto_start */)
__state <= RUNNING;
end
RUNNING: begin
if (stop || (__time >= keep_time))
__state <= WAITING;
end
WAITING: begin
if (start)
__state <= RUNNING;
else if (__v < finishv)
__state <= IDLE;
/// @todo enable fan?
end
endcase
end
end
always @ (posedge clk) begin
if (resetn == 1'b0)
__time <= 0;
else if (__state != RUNNING)
__time <= 0;
else
__time <= __time + 1;
end
always @ (posedge clk) begin
case (__state)
IDLE: begin
if (auto_hold) begin
__up_v <= holdv + 5;
__low_v <= holdv;
end
else begin
__up_v <= 0;
__low_v <= 0;
end
end
RUNNING: begin
__up_v <= keep_value + 5;
__low_v <= keep_value;
end
default: begin
__up_v <= 0;
__low_v <= 0;
end
endcase
end
always @ (posedge clk) begin
if (resetn == 1'b0)
__en <= 1'b0;
else if (__v > __up_v)
__en <= 1'b0;
else if (__v < __low_v)
__en <= 1'b1;
end
assign en = __en;
assign power = (resetn && (__state != IDLE || auto_hold));
assign fan = (__state == WAITING);
assign run_state = __state;
assign run_value = __v;
if (C_TEST) begin
always @ (posedge clk) begin
if (resetn == 1'b0)
__v <= 0;
else if (__en) begin
if (__v != {C_HEAT_VALUE_WIDTH {1'b1}})
__v <= __v + 1;
end
else begin
if (__v != {C_HEAT_VALUE_WIDTH {1'b0}})
__v <= __v - 1;
end
end
end
else begin
/// @brief for stream interface
assign s_axis_tready = 1'b1;
always @ (posedge clk) begin
if (s_axis_tready && s_axis_tvalid) begin
if (s_axis_tid == 17) begin
__v <= s_axis_tdata[15:16-C_HEAT_VALUE_WIDTH];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100 + 7; int n, k; string second; string s2; string s1; int main() { cin >> n >> k; cin >> second; sort(second.begin(), second.end()); for (int i = 0; i < n; i++) { if (second[i] != second[i + 1]) { s2 += second[i]; } } second = ; second += s2; sort(second.begin(), second.end()); for (int i = 0; i < second.size(); i++) { s1 += second[i]; if (second[i] + 1 == second[i + 1] || second[i] == second[i + 1]) { i++; } } if (s1.size() >= k) { int cnt = 0; for (int i = 0; i < k; i++) { cnt += s1[i] - a + 1; } cout << cnt; } else { cout << -1; } } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; int ailgis, bilgis; cin >> a >> b; ailgis = a.length(); bilgis = b.length(); if (a == b) { cout << -1 ; return 0; } if (ailgis > bilgis) cout << ailgis; else cout << bilgis; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); ; long long i, j, k, l, r, m, n, o, t; cin >> n; cin >> l >> r; char str[100001]; cin >> str; long long len = strlen(str); l--; r--; if (str[l] == str[r]) { cout << 0 << endl; return 0; } cout << 1 << endl; } |
#include <bits/stdc++.h> using std::cin; using std::cout; using std::endl; using std::set; using std::swap; using std::vector; void TaskA() { vector<char> first; vector<char> second; char a; int f, s; for (int i = 0; i < 4; i++) { cin >> a; first.push_back(a); if (a == A ) f = i; } swap(first[2], first[3]); if (f == 2) f = 3; else if (f == 3) f = 2; for (int i = 0; i < 4; i++) { cin >> a; second.push_back(a); if (a == A ) s = i; } swap(second[2], second[3]); if (s == 2) s = 3; else if (s == 3) s = 2; if (first[(f + 1) % 4] == X ) f = (f + 1) % 4; if (second[(s + 1) % 4] == X ) s = (s + 1) % 4; if (first[(f + 1) % 4] == second[(s + 1) % 4]) cout << YES ; else cout << NO ; } int main() { TaskA(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i; cin >> n >> k; if (k == 1 || k == n) { cout << 3 * n << endl; return 0; } else { int sum = 0; if (k & 1) { if (k >= n / 2 + 1) { k = n - k + 1; } } else { if (k > n / 2) { k = n - k + 1; } } int cnt = 0; for (i = k; i >= 1; i--) { if (cnt == 1) { sum += 4; } else { sum += 3; } cnt++; } sum--; sum += k; for (i = k + 1; i <= n; i++) { sum += 3; } sum--; cout << sum << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_TB_V
`define SKY130_FD_SC_LS__DLRBP_TB_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrbp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2O_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A2BB2O_BEHAVIORAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2O_BEHAVIORAL_V |
// A register file module. 32 registers, each of it has 32 bit
// Supports 2 reading ports, 1 writing port
// ADDA: reading address of A, ADDB: reading addr of B
// ADDC: writing address of C
// clk: clock signal
// clr: clear signal
// WE: Write Enable
module registerfile(ADDA, DATAA, ADDB, DATAB, ADDC, DATAC, clk, clr, WE);
input [4:0] ADDA, ADDB, ADDC;
input [31:0] DATAC;
input clk, clr, WE;
output [31:0] DATAA, DATAB;
reg [31:0] register [31:0];
integer i;
//clear all the registers in the register file
initial begin
for (i=0; i<32; i=i+1)
register[i] = 0;
$readmemh("reg.dat", register);
end
//only when a positive(rising) edge occurs
always @(posedge clk or posedge clr)
begin
// clear signal will reset all register as well
if (clr)
for (i=0; i<32; i=i+1)
register[i] = 0;
else
// only when WE is 1, we write the register file
if (WE == 1)
begin
register[ADDC] = DATAC;
register[0] = 0;
end
end
// we always reading content of A and B
assign DATAA = register[ADDA];
assign DATAB = register[ADDB];
endmodule
module RegFileTestbench;
reg [31:0] data;
reg [4:0] addrA, addrB, addrC;
wire [31:0] outA;
wire [31:0] outB;
reg clks, clr, WE;
integer ctr;
registerfile UUT(addrA, outA, addrB, outB, addrC, data, clks, clr, WE);
initial begin
clks = 0;
#10 clr = 0;
WE = 0;
for (ctr=0; ctr<31; ctr = ctr+1)
begin
#25 addrA <= ctr;
addrB = ctr+1;
end
addrA = 2;
addrB = 3;
addrC = 3;
WE = 1;
for (ctr=0; ctr<10; ctr = ctr+1)
begin
#25 data <= ctr;
end
WE = 0;
end
initial
forever #20 clks = ~clks;
initial
#1100 $stop;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e5 + 21; long long n, m, a[maxN], cnt[maxN], ans; bool p[maxN], f = true; vector<long long> g[maxN]; int32_t main() { cin >> n >> m; for (long long i = 0; i < m; i++) { long long x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } queue<long long> q; for (long long i = 1; i <= n; i++) { cin >> a[i]; if (!a[i]) q.push(i); } while (!q.empty()) { long long i = q.front(); q.pop(); if (a[i] == cnt[i]) { cnt[i]++, p[i] = true, ans++; for (long long j = 0; j < g[i].size(); j++) { long long u = g[i][j]; cnt[u]++; if (a[u] == cnt[u]) q.push(u); } } } for (long long i = 1; i <= n; i++) if (a[i] == cnt[i]) f = false; if (!f) cout << -1 << endl; else { cout << ans << endl; for (long long i = 1; i <= n; i++) { if (p[i]) cout << i << ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_M_V
`define SKY130_FD_SC_LP__AND2_M_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_m (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_m (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_M_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 19:26:51 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_sim_netlist.v
// Design : system_inverter_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_1_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_1_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w32_d3_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd32;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w32_d3_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd32;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH+1){1'b0}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 3'd1;
if (mOutPtr == 3'd0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 3'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 3'd2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w32_d3_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w32_d3_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; double g[110][110], x[110]; int n, m, ues[110]; pair<pair<int, int>, int> p[5010]; bool vis[110]; void read(int &x) { char ch = getchar(); int mark = 1; for (; ch != - && (ch < 0 || ch > 9 ); ch = getchar()) ; if (ch == - ) mark = -1, ch = getchar(); for (x = 0; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 48; x *= mark; } double Abs(double x) { if (x < 0) return -x; return x; } int main() { read(n); read(m); g[1][1] = 1; g[n][n] = 1; g[n][n + 1] = 1; for (int i = 1; i <= m; i++) { read(p[i].first.first); read(p[i].first.second); read(p[i].second); g[p[i].first.first][p[i].first.first]++; g[p[i].first.first][p[i].first.second]--; g[p[i].first.second][p[i].first.second]++; g[p[i].first.second][p[i].first.first]--; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (Abs(g[i][j]) && !vis[j]) { vis[j] = 1; ues[i] = j; break; } for (int j = 1; j <= n; j++) if (ues[i] != j && Abs(g[j][i])) { double tmp = -g[j][i] / g[ues[i]][i]; for (int k = 1; k <= n + 1; k++) g[j][k] += g[ues[i]][k] * tmp; } } for (int i = 1; i <= n; i++) x[i] = g[ues[i]][n + 1] / g[ues[i]][i]; double Min = 1e20; for (int i = 1; i <= m; i++) { if (Abs(x[p[i].first.first] - x[p[i].first.second]) > 1e-6) Min = min(Min, p[i].second / Abs(x[p[i].first.first] - x[p[i].first.second])); } double ans = 0; for (int i = 1; i <= m; i++) if (p[i].first.first == 1) ans += Min * (x[p[i].first.second] - x[p[i].first.first]); else if (p[i].first.second == 1) ans -= Min * (x[p[i].first.second] - x[p[i].first.first]); printf( %.5lf n , ans); if (Abs(ans) < 1e-6) memset(x, 0, sizeof(x)); for (int i = 1; i <= m; i++) printf( %.5lf n , Min * (x[p[i].first.second] - x[p[i].first.first])); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } const int N = 55; int n, m, sw; char s[N][N], t[N]; vector<pair<int, int> > ret1, ret2; void gao(vector<pair<int, int> > &ret) { for (int j = 0; j < m; j++) { int i = 0; while (i < n) { if (s[i][j] == L ) { for (int k = 0; i + k < n && j + k < m; k++) { if (s[i + 1 + k][j + k] == L ) { for (int l = k; l >= 0; l--) { ret.push_back(make_pair(i + l, j + l)); s[i + l][j + l] = s[i + l][j + l + 1] = U ; s[i + l + 1][j + l] = s[i + l + 1][j + l + 1] = D ; if (l > 0) { ret.push_back(make_pair(i + l, j + l - 1)); s[i + l][j + l - 1] = s[i + l + 1][j + l - 1] = L ; s[i + l][j + l] = s[i + l + 1][j + l] = R ; } } break; } if (s[i + 1 + k][j + 1 + k] == U ) { for (int l = k; l >= 0; l--) { ret.push_back(make_pair(i + l + 1, j + l)); s[i + l + 1][j + l] = s[i + l + 2][j + l] = L ; s[i + l + 1][j + l + 1] = s[i + l + 2][j + l + 1] = R ; ret.push_back(make_pair(i + l, j + l)); s[i + l][j + l] = s[i + l][j + l + 1] = U ; s[i + l + 1][j + l] = s[i + l + 1][j + l + 1] = D ; } break; } } } i += 2; } } } int main() { scanf( %d%d , &n, &m); if (n % 2 == 1) { sw = 1; for (int i = 0; i < n; i++) { scanf( %s , t); for (int j = 0; j < m; j++) { if (t[j] == L ) s[j][i] = U ; else if (t[j] == R ) s[j][i] = D ; else if (t[j] == U ) s[j][i] = L ; else s[j][i] = R ; } } swap(n, m); } else { for (int i = 0; i < n; i++) scanf( %s , s[i]); } gao(ret1); if (sw == 1) { for (int i = 0; i < m; i++) { scanf( %s , t); for (int j = 0; j < n; j++) { if (t[j] == L ) s[j][i] = U ; else if (t[j] == R ) s[j][i] = D ; else if (t[j] == U ) s[j][i] = L ; else s[j][i] = R ; } } } else { for (int i = 0; i < n; i++) scanf( %s , s[i]); } gao(ret2); reverse((ret2).begin(), (ret2).end()); for (auto p : ret2) ret1.push_back(p); if (sw) { for (auto &p : ret1) swap(p.first, p.second); } printf( %d n , ((int)(ret1).size())); for (auto p : ret1) printf( %d %d n , p.first + 1, p.second + 1); } |
#include <bits/stdc++.h> using namespace std; vector<char> a; int x, y, n; void update(pair<int, int> &pos, int i, int d) { if (a[i] == U ) pos.second += d; else if (a[i] == D ) pos.second -= d; else if (a[i] == R ) pos.first += d; else pos.first -= d; } bool ok(pair<int, int> pos, int len) { int d = abs(x - pos.first) + abs(y - pos.second); if (d <= len && d % 2 == len % 2) return true; return false; } bool can(int len) { pair<int, int> pos = make_pair(0, 0); for (int i = len; i < a.size(); i++) update(pos, i, 1); int l = 0, r = len; while (1) { if (ok(pos, len)) return true; if (n == r) break; update(pos, l++, 1); update(pos, r++, -1); } return false; } int main() { cin >> n; cin.ignore(); for (int i = 0; i < n; i++) { char temp; cin >> temp; a.push_back(temp); } cin >> x >> y; if (!ok(make_pair(0, 0), n)) cout << -1 << endl; else { int l = -1, r = n; while (r - l > 1) { int len = (r + l) / 2; if (can(len)) r = len; else l = len; } cout << r << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_0_0(clk, rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_565[15:0],rgb_888[23:0]" */;
input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_fifo_index (clock, reset, enable, push, pop, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter depth = 1;
parameter push_width = 1;
parameter pop_width = 1;
parameter simultaneous_push_pop = 1; // Note: different position than in assert_fifo_index
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [push_width-1:0] push;
input [pop_width-1:0] pop;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_FIFO_INDEX";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (depth==0) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value for parameter depth which must be set to value greater than 0");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_fifo_index_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_fifo_index_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_fifo_index_psl_logic.v"
`else
`endmodule // ovl_fifo_index
`endif
|
#include <bits/stdc++.h> using namespace std; int i, h, j, w; string s, t, v; pair<string, int> k; stack<int> p; vector<pair<string, int>> a; int main() { cin >> s; v = s; t = s; for (i = 0; i < s.size(); i++) if (s[i] == ( || s[i] == [ ) p.push(i); while (!p.empty()) { j = p.top(); if (s[j] == ( && s[j + 1] == ) ) v[j] = 0 , v[v.find( ) , j)] = 0 , s.erase(j, 2); if (s[j] == [ && s[j + 1] == ] ) v[j] = 0 , v[v.find( ] , j)] = 0 , s.erase(j, 2); p.pop(); } for (i = 0; i < v.size(); i++) { if (v[i] == 0 ) { k.first += t[i]; if (t[i] == [ ) k.second++; } if (v[i] != 0 && k.first.size() || i == v.size() - 1 && k.first.size()) a.push_back(k), k.first.clear(), h = max(h, k.second), k.second = 0; } if (!h) cout << 0; else if (!a.size()) cout << k.second << endl << k.first; else { for (i = 0; i < a.size(); i++) if (a[i].second == h) { cout << h << endl << a[i].first; break; } } } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const int maxn = (1 << 11) + 100; int dp[maxn][maxn]; vector<int> g[15]; int n, m, k, u, v, mx, cc[maxn]; void init() { for (int i = 0; i < maxn; ++i) cc[i] = __builtin_popcount(i); } int main() { init(); cin >> n >> m >> k; for (int i = 0; i < m; ++i) { cin >> u >> v; u--; v--; g[v].push_back(u); g[u].push_back(v); } mx = (1 << n) - 1; for (int i = 1; i <= mx; i <<= 1) dp[i][i] = 1; for (int i = 1; i <= mx; ++i) { for (int j = i; j; --j &= i) { if (dp[i][j]) { for (int k = 0; k < n; ++k) { if (i & (1 << k)) { for (int u : g[k]) { if (~i & (1 << u)) { if (cc[i] == 1) v = i | (1 << u); else v = j & ~(1 << k) | (1 << u); if (!(v >> u + 1)) dp[i | (1 << u)][v] += dp[i][j]; } } } } } } } long long ans = 0; for (int i = 0; i < mx; ++i) if (cc[i] == k) ans += dp[mx][i]; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A222OI_PP_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const unsigned mod = 3853518419u; const unsigned base = 85429482u; int n; string s; basic_string<int> e[300005]; int p[19][300005], du[300005]; unsigned bp[300005]; unsigned hu[19][300005], hd[19][300005]; void dfs(int x, int par) { p[0][x] = par; hu[0][x] = hd[0][x] = s[x]; for (int i = 1; i < 19; i++) { int y = p[i - 1][x]; p[i][x] = p[i - 1][y]; hu[i][x] = (1ull * hu[i - 1][x] * bp[1 << (i - 1)] + hu[i - 1][y]) % mod; hd[i][x] = (1ull * hd[i - 1][y] * bp[1 << (i - 1)] + hd[i - 1][x]) % mod; } for (int y : e[x]) { if (y != par) { du[y] = du[x] + 1; dfs(y, x); } } } int dizi(int x, int k) { for (int i = 0; i < 19; i++) { if ((1 << i) & k) { x = p[i][x]; } } return x; } int lca(int x, int y) { if (du[x] > du[y]) swap(x, y); y = dizi(y, du[y] - du[x]); if (x == y) return x; for (int i = 18; i >= 0; i--) { int xx = p[i][x], yy = p[i][y]; if (xx != yy) { x = xx; y = yy; } } return p[0][x]; } int resi(int a, int b, int c, int d) { int p = lca(a, b), q = lca(c, d), l = 0; int h = min(du[a] - du[p], du[c] - du[q]); for (int i = 18; i >= 0; i--) { if ((1 << i) <= h) { if (hu[i][a] == hu[i][c]) { l += 1 << i; h -= 1 << i; a = ::p[i][a]; c = ::p[i][c]; } } } if (h > 0) return l; if (a != p) { swap(a, c); swap(b, d); swap(p, q); } h = min(du[c] - du[q], du[b] - du[p]); for (int i = 18; i >= 0; i--) { if ((1 << i) <= h) { int t = dizi(b, du[b] - du[p] - (1 << i)); if (hu[i][::p[0][t]] == hd[i][c]) { l += 1 << i; h -= 1 << i; p = t; c = ::p[i][c]; } } } if (h > 0) return l; if (b == p) return l + (s[p] == s[c]); h = min(du[d] - du[q], du[b] - du[p]); for (int i = 18; i >= 0; i--) { if ((1 << i) <= h) { int t1 = dizi(b, du[b] - du[p] - (1 << i)); int t2 = dizi(d, du[d] - du[q] - (1 << i)); if (hu[i][::p[0][t1]] == hu[i][::p[0][t2]]) { l += 1 << i; h -= 1 << i; p = t1; q = t2; } } } if (h > 0) return l; return l + (s[p] == s[q]); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); cin >> n >> s; s = string( ) + s; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; e[u] += v; e[v] += u; } bp[0] = 1; for (int i = 1; i < 300005; i++) bp[i] = bp[i - 1] * 1ull * base % mod; dfs(1, 1); int q; cin >> q; while (q--) { int a, b, c, d; cin >> a >> b >> c >> d; cout << resi(a, b, c, d) << n ; } } |
#include <bits/stdc++.h> using namespace std; int gi() { int f = 1, x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return f == 1 ? x : -x; } const int N = 1005; int n, m, r, c; double a[N][N], x[N]; void get_solution() { for (int i = (1); i <= (m); ++i) { double r = a[i + 1][i] / a[i][i]; a[i + 1][i] -= r * a[i][i]; a[i + 1][i + 1] -= r * a[i][i + 1]; a[i + 1][m + 1] -= r * a[i][m + 1]; } for (int i = (m); i >= (1); --i) { double r = a[i - 1][i] / a[i][i]; a[i - 1][i] = 0; a[i - 1][m + 1] -= r * a[i][m + 1]; x[i] = a[i][m + 1] / a[i][i]; } } int main() { n = gi(), m = gi(), r = gi(), c = gi(); if (m == 1) return cout << fixed << setprecision(10) << (n - r) * 2 << endl, 0; if (r == n) return puts( 0.0000000000 ), 0; for (int _ = (n - 1); _ >= (1); --_) { for (int i = (1); i <= (m); ++i) { if (i == 1) { a[i][i] = 2. / 3; a[i][i + 1] = -1. / 3; a[i][m + 1] = 1. / 3 * x[i] + 1; } else if (i == m) { a[i][i] = 2. / 3; a[i][i - 1] = -1. / 3; a[i][m + 1] = 1. / 3 * x[i] + 1; } else { a[i][i] = 3. / 4; a[i][i + 1] = -1. / 4; a[i][i - 1] = -1. / 4; a[i][m + 1] = 1. / 4 * x[i] + 1; } } get_solution(); if (_ == r) return cout << fixed << setprecision(10) << x[c] << endl, 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int sum1 = 0, sum2 = 0, sum3 = 0; int n; cin >> n; int a, b, c; for (int i = 0; i < n; i++) { cin >> a >> b >> c; sum1 += a; sum2 += b; sum3 += c; } if (sum1 == 0 && sum2 == 0 && sum3 == 0) cout << YES ; else cout << NO ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_4_V
`define SKY130_FD_SC_MS__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int a[2 * n]; for (int i = 0; i < 2 * n; i++) cin >> a[i]; sort(a, a + (2 * n)); long long int s = 2e19; ; for (int i = 1; i < n; i++) { s = min(s, (a[n * 2 - 1] - a[0]) * (a[n + i - 1] - a[i])); } s = min(s, (a[n - 1] - a[0]) * (a[n * 2 - 1] - a[n])); cout << s; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; char moves[4] = { L , U , R , D }; long long dx[4] = {-1, 0, 1, 0}; long long dy[4] = {0, -1, 0, 1}; const long long N = 1e3 + 1; bool visited[N]; vector<long long> adj[N]; long long n, k; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (long long i = 1; i < k + 1; i++) { cout << 2 * i << << 2 * i - 1 << ; } for (long long i = 2 * k + 1; i < 2 * n + 1; i++) cout << i << ; return 0; } |
#include <bits/stdc++.h> using namespace std; string str, queries[100010]; int n; unsigned long long values[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; unsigned long long length[10] = {10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; int main() { cin >> str >> n; queries[0] = 0-> + str; for (int i = 0; i < n; i++) { cin >> queries[i + 1]; } for (int i = n; i >= 0; i--) { unsigned long long len = 1, val = 0; for (int j = 3; j < queries[i].size(); ++j) { int d = queries[i][j] - 0 ; val = (val * length[d] + values[d]) % 1000000007; len = len * length[d] % 1000000007; } length[queries[i][0] - 0 ] = len; values[queries[i][0] - 0 ] = val; } cout << values[0] << endl; return 0; } |
`timescale 1ns/1ns
module usb_tx_token
(input c,
input [18:0] d,
input start,
output [7:0] sie_d,
output sie_dv);
localparam ST_IDLE = 3'd0;
localparam ST_CALC_CRC = 3'd1;
localparam ST_SYNC = 3'd2;
localparam ST_DATA = 3'd3;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire cnt_rst;
wire cnt_en = 1'b1;
wire [7:0] cnt; // counter used by many states
r #(8) cnt_r
(.c(c), .rst(cnt_rst | state == ST_IDLE), .en(cnt_en),
.d(cnt + 1'b1), .q(cnt));
// calculate the crc5 serially
wire [10:0] payload_shifter;
wire payload_shifter_load;
r #(11) payload_shifter_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(payload_shifter_load ? d[18:8] : {1'b0, payload_shifter[10:1]}),
.q(payload_shifter));
wire crc_dv;
wire [4:0] crc5;
usb_crc5_serial crc5_inst
(.c(c), .r(state == ST_IDLE), .d(payload_shifter[0]), .dv(crc_dv), .crc(crc5));
wire [31:0] shift;
wire shift_load;
r #(32) shift_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(shift_load ? {~crc5, d, 8'b10000000} : { 8'h0, shift[31:8] }),
.q(shift));
assign sie_d = shift[7:0];
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_CALC_CRC, 5'b00011 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_CALC_CRC:
if (cnt == 8'd10) ctrl = { ST_SYNC , 5'b00000 };
else ctrl = { ST_CALC_CRC, 5'b00000 };
ST_SYNC: ctrl = { ST_DATA , 5'b00101 };
ST_DATA:
if (cnt == 8'd3) ctrl = { ST_IDLE , 5'b01000 };
else ctrl = { ST_DATA , 5'b01000 };
default: ctrl = { ST_IDLE, 5'b00000 };
endcase
end
assign payload_shifter_load = ctrl[1];
assign cnt_rst = ctrl[0];
assign crc_dv = state == ST_CALC_CRC;
assign shift_load = ctrl[2];
assign sie_dv = ctrl[3];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 300005; pair<int, int> seg[2 * MAX]; void update(int l, int r, int fight, int value) { for (l += MAX, r += MAX; l < r; l >>= 1, r >>= 1) { if (l & 1) seg[l++] = make_pair(fight, value); if (r & 1) seg[--r] = make_pair(fight, value); } } int query(int p) { pair<int, int> res = make_pair(INT_MAX, 0); for (p += MAX; p > 1; p >>= 1) res = min(res, seg[p]); return res.second; } int main() { int n, m; cin >> n >> m; vector<pair<pair<int, int>, int> > v; for (int i = 0; i < 2 * MAX; i++) seg[i] = make_pair(INT_MAX, 0); for (int i = 0; i < m; i++) { int a, b, x; cin >> a >> b >> x; v.push_back(make_pair(make_pair(a, b), x)); } for (int i = m - 1; i >= 0; i--) { int l = v[i].first.first; int r = v[i].first.second; int win = v[i].second; update(l - 1, win - 1, i, win); update(win, r, i, win); } for (int i = 0; i < n; i++) cout << query(i) << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_SYMBOL_V
`define SKY130_FD_SC_HD__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_SYMBOL_V
|
// file: pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____57.500______0.000______50.0______547.826____150.000
// CLK_OUT2____57.500______0.000______50.0______547.826____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________50.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (23),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkfx));
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_eng_sim_in (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005], b[100005]; int main() { int n, m, k; map<int, int> f1; cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { cin >> b[i]; } bool f = false; sort(a, a + n); sort(b, b + m); reverse(a, a + n); reverse(b, b + m); if (n <= m) { for (int i = 0; i < n; i++) { if (a[i] > b[i]) { f = true; break; } } } else { f = true; } if (f) { cout << YES ; } else { cout << NO ; } } |
#include <bits/stdc++.h> using namespace std; int mp[100][100]; int cnt[100]; int main() { int n, x, y; cin >> n; while (cin >> x) { cin >> y; mp[x][y] = 1; mp[y][x] = 1; cnt[x]++; } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (!mp[i][j]) { if (cnt[i] > cnt[j]) cout << i << << j; else cout << j << << i; return 0; } } } } |
module gmii2fifo72 # (
parameter Gap = 4'h2
) (
input sys_rst,
input gmii_rx_clk,
input gmii_rx_dv,
input [7:0] gmii_rxd,
// FIFO
output [71:0] din,
input full,
output reg wr_en,
output wr_clk
);
assign wr_clk = gmii_rx_clk;
//-----------------------------------
// logic
//-----------------------------------
reg [2:0] count = 3'h0;
reg [63:0] rxd = 64'h00;
reg [7:0] rxc = 8'h0;
reg [3:0] gap_count = 4'h0;
always @(posedge gmii_rx_clk) begin
if (sys_rst) begin
count <= 3'h0;
gap_count <= 4'h0;
end else begin
wr_en <= 1'b0;
if (gmii_rx_dv == 1'b1) begin
count <= count + 3'h1;
gap_count <= Gap;
case (count)
3'h0: begin
rxd[63: 0] <= {56'h0, gmii_rxd[7:0]};
rxc[7:0] <= 8'b00000001;
end
3'h1: begin
rxd[15: 8] <= gmii_rxd[7:0];
rxc[1] <= 1'b1;
end
3'h2: begin
rxd[23:16] <= gmii_rxd[7:0];
rxc[2] <= 1'b1;
end
3'h3: begin
rxd[31:24] <= gmii_rxd[7:0];
rxc[3] <= 1'b1;
end
3'h4: begin
rxd[39:32] <= gmii_rxd[7:0];
rxc[4] <= 1'b1;
end
3'h5: begin
rxd[47:40] <= gmii_rxd[7:0];
rxc[5] <= 1'b1;
end
3'h6: begin
rxd[55:48] <= gmii_rxd[7:0];
rxc[6] <= 1'b1;
end
3'h7: begin
rxd[63:56] <= gmii_rxd[7:0];
rxc[7] <= 1'b1;
wr_en <= 1'b1;
end
endcase
end else begin
if (count != 3'h0) begin
wr_en <= 1'b1;
count <= 3'h0;
end else if (gap_count != 4'h0) begin
rxd[63: 0] <= 64'h0;
rxc[7:0] <= 8'h0;
wr_en <= 1'b1;
gap_count <= gap_count - 4'h1;
end
end
end
end
assign din[71:0] = {rxc[7:0], rxd[63:0]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_PP_V |
// divmmc
//
// Total refactoring. Made module synchroneous. (Sorgelig)
//
module divmmc
(
input clk_sys,
input [1:0] mode,
// CPU interface
input nWR,
input nRD,
input nMREQ,
input nIORQ,
input nM1,
input [15:0] addr,
input [7:0] din,
output [7:0] dout,
// control
input enable,
output active_io,
// SD/MMC SPI
output reg spi_ss,
output spi_clk,
input spi_di,
output spi_do
);
assign active_io = port_io;
wire io_we = ~nIORQ & ~nWR & nM1;
wire io_rd = ~nIORQ & ~nRD & nM1;
wire port_cs = ((mode == 2'b01) && (addr[7:0] == 8'hE7)) ||
((mode == 2'b10) && (addr[7:0] == 8'h1F));
wire port_io = ((mode == 2'b01) && (addr[7:0] == 8'hEB)) ||
((mode == 2'b10) && (addr[7:0] == 8'h3F));
reg tx_strobe;
reg rx_strobe;
always @(posedge clk_sys) begin
reg old_we, old_rd, old_m1;
reg m1_trigger;
rx_strobe <= 0;
tx_strobe <= 0;
if(enable) begin
old_we <= io_we;
old_rd <= io_rd;
if(io_we & ~old_we) begin
if (port_cs) spi_ss <= din[0]; // SPI enable
if (port_io) tx_strobe <= 1'b1; // SPI write
end
// SPI read
if(io_rd & ~old_rd & port_io) rx_strobe <= 1;
end else begin
spi_ss <= 1;
end
end
spi spi
(
.clk_sys(clk_sys),
.tx(tx_strobe),
.rx(rx_strobe),
.din(din),
.dout(dout),
.spi_clk(spi_clk),
.spi_di(spi_di),
.spi_do(spi_do)
);
endmodule
module spi
(
input clk_sys,
input tx, // Byte ready to be transmitted
input rx, // request to read one byte
input [7:0] din,
output [7:0] dout,
output spi_clk,
input spi_di,
output spi_do
);
assign spi_clk = counter[0];
assign spi_do = io_byte[7]; // data is shifted up during transfer
assign dout = data;
reg [4:0] counter = 5'b10000; // tx/rx counter is idle
reg [7:0] io_byte, data;
always @(negedge clk_sys) begin
if(counter[4]) begin
if(rx | tx) begin
counter <= 0;
data <= io_byte;
io_byte <= tx ? din : 8'hff;
end
end else begin
if(spi_clk) io_byte <= { io_byte[6:0], spi_di };
counter <= counter + 2'd1;
end
end
endmodule
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 16:26:29
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module RecursiveKOA_STAGE_2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW((SW/2)+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int BSZ1 = 1010; const int BSZ2 = 200; int N; char A[202020]; int B[40404040]; int C[202020]; long long ans; int R[202020]; void calc(int i, int r, int zero) { int t = (zero + R[r]) / i; int u = zero / i; if (zero % i != 0) u++; if (t > BSZ2) { u = max(u, BSZ2 + 1); ans += (t - u + 1); } } int main() { scanf( %s , A + 1); N = strlen(A + 1); for (int i = N - 1; i >= 1; i--) { if (A[i + 1] == 0 ) R[i] = R[i + 1] + 1; else R[i] = 0; } for (int i = 1; i <= BSZ1; i++) { int l = 1, r = 1; int zero = 0, cnt = 0; while (r <= N && cnt < i) { if (A[r] == 1 ) cnt++; else zero++; r++; } if (cnt < i) continue; r--; while (1) { while (A[l] == 0 ) { calc(i, r, zero); l++; zero--; } calc(i, r, zero); l++; r++; while (r <= N) { if (A[r] == 1 ) break; else zero++; r++; } if (r > N) break; } } for (int i = 0; i <= BSZ2; i++) { B[N]++; C[0] = N; int c = N; for (int j = 1; j <= N; j++) { if (A[j] == 1 ) c += i; else c--; ans += B[c]; B[c]++; C[j] = c; } for (int j = 0; j <= N; j++) B[C[j]] = 0; } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_SYMBOL_V
`define SKY130_FD_SC_HS__AND4B_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; char a[n][7]; for (int i = 0; i < n; i++) { for (int j = 0; j < 7; j++) cin >> a[i][j]; } int ans = 0, ct = 0; for (int j = 0; j < 7; j++) { ct = 0; for (int i = 0; i < n; i++) { if (a[i][j] == 1 ) ct++; } ans = max(ans, ct); } cout << ans; return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate parameter passing override in module declaration.
//
// Build a single line of storage - Note it's
//
module reg32 (clk,we, din, dout);
parameter WIDTH=32;
input we;
input clk;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
reg [WIDTH-1:0] store;
always @(posedge clk)
if(we)
store <= din;
assign dout = store ;
endmodule
module memory(clk, we, addr, din, dout);
parameter WIDTH=8;
input clk;
input we;
input [1:0] addr;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
reg [WIDTH-1:0] dout;
wire [WIDTH-1:0] dout0,dout1,dout2,dout3;
reg we0,we1,we2,we3;
reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]),
.dout(dout0[WIDTH-1:0]));
reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]),
.dout(dout1[WIDTH-1:0]));
reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]),
.dout(dout2[WIDTH-1:0]));
reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]),
.dout(dout3[WIDTH-1:0]));
//
// Build we decode
//
always @(addr or we)
case (addr)
2'b00: begin
we0 = we;
we1 = 0;
we2 = 0;
we3 = 0;
end
2'b01: begin
we0 = 0;
we1 = we;
we2 = 0;
we3 = 0;
end
2'b10: begin
we0 = 0;
we1 = 0;
we2 = we;
we3 = 0;
end
2'b11: begin
we0 = 0;
we1 = 0;
we2 = 0;
we3 = we;
end
endcase
//
// Connect dout to register output
//
always @(addr or dout0 or dout1 or dout2 or dout3)
case (addr)
2'b00: dout = dout0;
2'b01: dout = dout1;
2'b10: dout = dout2;
2'b11: dout = dout3;
endcase
endmodule
module top;
parameter WIDTH=8;
reg clk;
reg we;
reg [1:0] addr;
reg [WIDTH-1:0] din;
reg error;
wire [WIDTH-1:0] dout;
memory mem (clk, we, addr, din, dout);
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,top.mem.reg0);
clk = 0;
error =0;
#3;
we = 1;
addr = 0;
din = 32'b0_00;
#10;
addr = 1;
din = 32'h1;
#10;
addr = 2;
din = 32'h2;
#10;
addr = 3;
din = 32'h3;
#10;
we = 0;
addr = 0;
#1;
if(dout[7:0] !== 8'h00)
begin
$display("FAILED - Ram[0] not 0, is %h",dout[7:0]);
error = 1;
end
if(error == 0)
$display("PASSED");
$finish ;
end
always #(5) clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[26], l[26], n, k, x, se, t; char b; string s; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> b >> s; if (x == 1) { if (i == n - 1) break; if (b != . ) se++; continue; } if (b != ? ) for (int j = 0; j < s.size(); j++) l[s[j] - a ]++; if (b == ! ) { for (int j = 0; j < s.size(); j++) { a[s[j] - a ]++; } } if (b == . ) { for (int j = 0; j < s.size(); j++) { a[s[j] - a ]--; } } if (b == ? && i != n - 1) a[s[0] - a ]--; if (b != ? ) for (int j = 0; j < 26; j++) { if (l[j] > 1) a[j] = a[j] - l[j] + 1; l[j] = 0; } k = 0; for (int j = 0; j < 26; j++) k = max(a[j], k); for (int j = 0; j < 26; j++) if (a[j] == k) t++; if (t == 1) x = 1; t = 0; } cout << se; return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// Verilog module for X checker
//
// ====================================================================
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
module sirv_gnrl_xchecker # (
parameter DW = 32
) (
input [DW-1:0] i_dat,
input clk
);
CHECK_THE_X_VALUE:
assert property (@(posedge clk)
((^(i_dat)) !== 1'bx)
)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
endmodule
//synopsys translate_on
`endif//}
`endif//}
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
/**
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
*
* Verilog wrapper for lpflow_bleeder with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_bleeder.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_bleeder_1 (
SHORT,
VPWR ,
VGND ,
VPB ,
VNB
);
input SHORT;
inout VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_bleeder base (
.SHORT(SHORT),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_bleeder_1 (
SHORT
);
input SHORT;
// Voltage supply signals
wire VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_bleeder base (
.SHORT(SHORT)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FA_BEHAVIORAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire CIN or0_out ;
wire CIN and0_out ;
wire CIN and1_out ;
wire csi_opt_276, nor0_out ;
wire csi_opt_276, nor1_out ;
wire or1_out_COUT ;
wire u_vpwr_vgnd0_out_COUT;
wire and2_out ;
wire or2_out_SUM ;
wire u_vpwr_vgnd1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , u_vpwr_vgnd0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , u_vpwr_vgnd1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_BEHAVIORAL_V |
`timescale 1ns/100ps
module top;
parameter pdly = 1.2;
real rdly = 1.3;
integer idly = 1;
reg in = 1'b0;
wire gi, gf, gs, gt;
wire #idly int = in;
wire #1.1 first = in;
wire #pdly second = in;
wire #rdly third = in;
buf #idly (gi, in);
buf #1.1 (gf, in);
buf #pdly (gs, in);
buf #rdly (gt, in);
initial begin
$monitor($realtime,, int,, first,, second,, third,, gi,, gf,, gs,, gt);
#0 in = 1'b1;
#2 in = 1'b0;
#4;
rdly = -6.1; // Since we are at 6 this will not wrap.
in = 1'b1;
@(third or gt) $display("Large delay: ", $realtime);
end
initial #1.1 $display("Should be 1.1: ", $realtime); // This should be 1.1
initial #pdly $display("Should be 1.2: ", $realtime); // This should be 1.2
initial begin
#0; // We need this so that rdly has a defined value.
#rdly $display("Should be 1.3: ", $realtime); // This should be 1.3
end
initial begin
#0; // We need this so that rdly has a defined value.
#idly $display("Should be 1.0: ", $realtime); // This should be 1.0
end
endmodule
`timescale 1ns/1ps
module top2;
initial #1.001 $display("Should be 1.001: ", $realtime);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j, k, l; cin >> n >> m; k = (n - m) / 2; j = 1; while (j <= n) { if (j % (k + 1) == 0) { cout << 1 ; } else { cout << 0 ; } j++; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under The Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`timescale `time_scale_units / `time_scale_prec
import "DPI-C" function void dpii_check();
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
// verilator lint_off REALCVT
time digits = .543210ns; // Will round to time units
realtime rdigits = .543210ns; // Will round to time precision
time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double
// verilator lint_on REALCVT
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("- [%0t] tick\n", $time);
`endif
if ($time >= 60) begin
$write(":: In %m\n");
$printtimescale;
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
$timeformat(-9, 6, "ns", 16);
$write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123);
$write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits);
$write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits);
$write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc);
$write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n",
$time, $stime, $stime, $stime);
// verilator lint_off REALCVT
$write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n",
$time, $realtime, $realtime, $realtime);
// verilator lint_on REALCVT
dpii_check();
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND2_BEHAVIORAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_BEHAVIORAL_PP_V |
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