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hoangt/PoC | src/bus/stream/stream_Mirror.vhdl | 2 | 8,816 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_Mirror is
generic (
portS : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
META_BITS : T_POSVEC := (0 => 8);
META_LENGTH : T_POSVEC := (0 => 16)
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
In_Valid : in STD_LOGIC;
In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
In_SOF : in STD_LOGIC;
In_EOF : in STD_LOGIC;
In_Ack : out STD_LOGIC;
In_Meta_rst : out STD_LOGIC;
In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0);
In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0);
Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Meta_rst : in STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Meta_nxt : in T_SLM(portS - 1 downto 0, META_BITS'length - 1 downto 0);
Out_Meta_Data : out T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0)
);
end;
architecture rtl of Stream_Mirror is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
signal FifOGlue_put : STD_LOGIC;
signal FifOGlue_DataIn : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0);
signal FifOGlue_Full : STD_LOGIC;
signal FifOGlue_Valid : STD_LOGIC;
signal FifOGlue_DataOut : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0);
signal FifOGlue_got : STD_LOGIC;
signal Ack_i : STD_LOGIC;
signal Mask_r : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '1');
signal MetaOut_rst : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z'));
signal Out_Meta_Data_i : T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) := (others => (others => 'Z'));
begin
-- Data path
-- ==========================================================================================================================================================
FifOGlue_put <= In_Valid;
FifOGlue_DataIn(DATA_BITS - 1 downto 0) <= In_Data;
FifOGlue_DataIn(DATA_BITS + 0) <= In_SOF;
FifOGlue_DataIn(DATA_BITS + 1) <= In_EOF;
In_Ack <= not FifOGlue_Full;
FifOGlue : entity PoC.fifo_glue
generic map (
D_BITS => DATA_BITS + 2 -- Data Width
)
port map (
-- Control
clk => Clock, -- Clock
rst => Reset, -- Synchronous Reset
-- Input
put => FifOGlue_put, -- Put Value
di => FifOGlue_DataIn, -- Data Input
ful => FifOGlue_Full, -- Full
-- Output
vld => FifOGlue_Valid, -- Data Available
do => FifOGlue_DataOut, -- Data Output
got => FifOGlue_got -- Data Consumed
);
genPorts : for i in 0 to portS - 1 generate
assign_row(Out_Data_i, FifOGlue_DataOut(DATA_BITS - 1 downto 0), i);
end generate;
Ack_i <= slv_and(Out_Ack) or slv_and(not Mask_r or Out_Ack);
FifOGlue_got <= Ack_i ;
Out_Valid <= (portS - 1 downto 0 => FifOGlue_Valid) and Mask_r;
Out_Data <= Out_Data_i;
Out_SOF <= (portS - 1 downto 0 => FifOGlue_DataOut(DATA_BITS + 0));
Out_EOF <= (portS - 1 downto 0 => FifOGlue_DataOut(DATA_BITS + 1));
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or Ack_i ) = '1') then
Mask_r <= (others => '1');
else
Mask_r <= Mask_r and not Out_Ack;
end if;
end if;
end process;
-- Metadata path
-- ==========================================================================================================================================================
In_Meta_rst <= slv_and(MetaOut_rst);
genMeta : for i in 0 to META_BITS'length - 1 generate
subtype T_METAMEMORY is STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0);
type T_METAMEMORY_VECTOR is array(NATURAL range <>) of T_METAMEMORY;
begin
genReg : if (META_LENGTH(i) = 1) generate
signal MetaMemory_en : STD_LOGIC;
signal MetaMemory : T_METAMEMORY;
begin
MetaMemory_en <= In_Valid and In_SOF;
process(Clock)
begin
if rising_edge(Clock) then
if (MetaMemory_en = '1') then
MetaMemory <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I));
end if;
end if;
end process;
genReader : FOR J IN 0 to portS - 1 generate
assign_row(Out_Meta_Data_i, MetaMemory, J, high(META_BITS, I), low(META_BITS, I));
end generate;
end generate;
genMem : if (META_LENGTH(i) > 1) generate
signal MetaMemory_en : STD_LOGIC;
signal MetaMemory : T_METAMEMORY_VECTOR(META_LENGTH(i) - 1 downto 0);
signal Writer_CounterControl : STD_LOGIC := '0';
signal Writer_en : STD_LOGIC;
signal Writer_rst : STD_LOGIC;
signal Writer_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0');
begin
-- MetaMemory Write Pointer Control
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Writer_CounterControl <= '0';
else
if ((In_Valid and In_SOF) = '1') then
Writer_CounterControl <= '1';
ELSif (Writer_us = (META_LENGTH(i) - 1)) then
Writer_CounterControl <= '0';
end if;
end if;
end if;
end process;
Writer_en <= (In_Valid and In_SOF) or Writer_CounterControl;
In_Meta_nxt(i) <= Writer_en;
MetaMemory_en <= Writer_en;
MetaOut_rst(i) <= NOT Writer_en;
-- MetaMemory - Write Pointer
process(Clock)
begin
if rising_edge(Clock) then
if (Writer_en = '0') then
Writer_us <= (others => '0');
else
Writer_us <= Writer_us + 1;
end if;
end if;
end process;
-- MetaMemory
process(Clock)
begin
if rising_edge(Clock) then
if (MetaMemory_en = '1') then
MetaMemory(to_integer(Writer_us)) <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I));
end if;
end if;
end process;
genReader : for j in 0 to portS - 1 generate
signal Row : T_METAMEMORY;
signal Reader_en : STD_LOGIC;
signal Reader_rst : STD_LOGIC;
signal Reader_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0');
begin
Reader_rst <= Out_Meta_rst(j) or (In_Valid and In_SOF);
Reader_en <= Out_Meta_nxt(j, I);
process(Clock)
begin
if rising_edge(Clock) then
if (Reader_rst = '1') then
Reader_us <= (others => '0');
ELSif (Reader_en = '1') then
Reader_us <= Reader_us + 1;
end if;
end if;
end process;
Row <= MetaMemory(to_integer(Reader_us));
assign_row(Out_Meta_Data_i, Row, j, high(META_BITS, i), low(META_BITS, i));
end generate; -- for each port
end generate; -- if length > 1
end generate; -- for each metadata stream
Out_Meta_Data <= Out_Meta_Data_i;
end architecture;
| apache-2.0 | 3994948c28cbef4bcde52f7228fe3419 | 0.55524 | 3.145202 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/mem_state_machine.vhd | 4 | 91,651 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: mem_state_machine.vhd
-- Description: State machine controller for memory reads and writes
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
--
-- KSB 05/08/08 version v4_00_a
-- ^^^^^^^^
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Removed "elsif Bus2IP_Mem_CS = '1' and ..." and "WAIT_TEMP" from WRITE state.
-- 2. Added write_req_ack_cmb <= '1';
-- in WAIT_TEMP with (Synch_mem = '0' and single_trans = '0') condition
-- ~~~~~~~~
-- SK 24/11/10
-- ^^^^^^^^
-- 1. Added "ns_idle" signal to reset the address counter in mem_steer.vhd
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDR component
-- declaration
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- The signal list is aligned as per the port list in entity
-------------------------------------------------------------------------------
-- Bus2IP_RNW -- Processor read/write transfer control
-- Bus2IP_RdReq -- Processor Read Request
-- Bus2IP_WrReq -- Processor Write Request
-- Synch_mem -- Current transaction is for synchronous
-- memory
-- Two_pipe_delay -- Two pipe delay for synchronous memory
-- Cycle_End -- Current Cycle Complete
-- Read_data_en -- Enable for read data registers
-- Read_ack -- Read cycle data acknowledge
--
-- Address_strobe -- Address strobe signal
-- Data_strobe -- Data and BEs strobe signal
-- CS_Strobe -- Chip select strobe signal to store the
-- -- status of Bus2IP_CS
-- Addr_cnt_ce -- Address counter count enable
-- Addr_cnt_rst -- Address counter reset
-- Cycle_cnt_ld -- Cycle end counter count load
-- Cycle_cnt_en -- Cycle end counter count enable
--
-- Trd_cnt_en -- Read Cycle Count Enable
-- Twr_cnt_en -- Write Cycle Count Enable
-- Trd_load -- Read Cycle Timer Load
-- Twr_load -- Write Cycle Timer Load
-- Thz_load -- Read Recovery to Write Timer Load
-- Tlz_load -- Write Recovery to Read Timer Load
-- Trd_end -- Read Cycle Complete
-- Twr_end -- Write Cycle Complete
-- Thz_end -- Read Recovery Complete
-- Tlz_end -- Write Recovery Complete
-- Tpacc_end -- page access read end
--
-- Mem_CEN_cmb -- Memory Chip Enable
-- Mem_OEN_cmb -- Memory Output Enable
-- Mem_WEN_cmb -- Memory Write Enable
--
-- Write_req_ack -- Write address acknowledge
-- Read_req_ack -- Read address acknowledge
-- Transaction_done -- Operation complete indication for
-- -- current transaction
-- Mem_Addr_rst -- Memory address bus reset
--
-- Clk -- System Clock
-- Rst -- System Read
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity mem_state_machine is
port (
Clk : in std_logic;
Rst : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
Synch_mem : in std_logic;
Two_pipe_delay : in std_logic;
Cycle_End : in std_logic;
Bus2IP_Mem_CS : in std_logic;
Bus2IP_Burst : in std_logic;
Read_data_en : out std_logic;
Read_ack : out std_logic;
Address_strobe : out std_logic;
Data_strobe : out std_logic;
CS_Strobe : out std_logic;
Addr_cnt_ce : out std_logic;
Addr_cnt_rst : out std_logic;
Cycle_cnt_ld : out std_logic;
Cycle_cnt_en : out std_logic;
Trd_cnt_en : out std_logic;
Twr_cnt_en : out std_logic;
Twph_cnt_en : out std_logic;
Tpacc_cnt_en : out std_logic;
Trd_load : out std_logic;
Twr_load : out std_logic;
Twph_load : out std_logic;
Tpacc_load : out std_logic;
Thz_load : out std_logic;
Tlz_load : out std_logic;
Trd_end : in std_logic;
Twr_end : in std_logic;
Twph_end : in std_logic;
Thz_end : in std_logic;
Tlz_end : in std_logic;
Tpacc_end : in std_logic;
New_page_access : in std_logic;
Linear_flash_brst_rd_flag : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Bus2IP_RdReq_emc : in std_logic;
MSM_Mem_CEN : out std_logic;
MSM_Mem_OEN : out std_logic;
MSM_Mem_WEN : out std_logic;
CS_Strobe_par_addr : out std_logic;
Write_req_ack : out std_logic;
Read_req_ack : out std_logic;
Transaction_done : out std_logic;
single_trans : in std_logic;
Mem_Addr_rst : out std_logic;
Addr_align : in std_logic;
Addr_align_rd : out std_logic;
original_wrce : in std_logic;
last_burst_cnt : in std_logic;
Write_req_data_ack : out std_logic;
Write_req_addr_ack : out std_logic;
address_strobe_c : out std_logic;
be_strobe_c : out std_logic;
data_strobe_c : out std_logic;
ns_idle : out std_logic;
pr_idle : out std_logic; -- 11-12-2012
pr_state_wait_temp_cmb : out std_logic;
Twr_rec_load : out std_logic;
Twr_rec_cnt_en : out std_logic;
Twr_rec_end : in std_logic;
Flash_mem_access : in std_logic;
Flash_mem_access_disable : out std_logic;
Mem_WAIT: in std_logic;
Adv_L_N : out std_logic := '1';
last_addr1 : in std_logic;
stop_oen : in std_logic;
axi_wvalid : in std_logic;
axi_wlast : in std_logic;
bus2ip_ben_all_1 : in std_logic
);
end entity mem_state_machine;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of mem_state_machine is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
type MEM_SM_TYPE is (IDLE,
WRITE,
DASSERT_WEN,
WAIT_WRITE_ACK,
WRITE_WAIT,
WAIT_TEMP,
WR_REC_PERIOD, -- 9/6/2011
READ,
LINEAR_FLASH_SYNC_RD,
PAGE_READ,
WAIT_RDDATA_ACK --,
-- WRITE_SYNC,
-- READ_SYNC--,
--WRITE_ASYNC,
--READ_ASYNC
);
signal crnt_state : MEM_SM_TYPE := IDLE;
signal next_state : MEM_SM_TYPE;
--signal write_req_ack_cmb : std_logic;
signal read_req_ack_cmb : std_logic;
signal read_data_en_cmb : std_logic;
signal read_data_en_reg : std_logic;
signal read_ack_cmb : std_logic;
signal read_ack_reg : std_logic;
signal addr_cnt_ce_cmb : std_logic;
signal addr_cnt_rst_cmb : std_logic;
signal addr_cnt_ce_reg : std_logic;
signal addr_cnt_rst_reg : std_logic;
signal addressData_strobe_cmb : std_logic;
signal cs_strobe_cmb : std_logic;
signal cs_strobe_reg : std_logic;
signal cycle_cnt_ld_cmb : std_logic;
signal cycle_cnt_en_cmb : std_logic;
signal trd_cnt_en_cmb : std_logic;
signal twr_cnt_en_cmb : std_logic;
signal twph_cnt_en_cmb : std_logic;
signal tpacc_cnt_en_cmb : std_logic;
signal trd_load_cmb : std_logic;
signal twr_load_cmb : std_logic;
signal twph_load_cmb : std_logic;
signal thz_load_cmb : std_logic;
signal tlz_load_cmb : std_logic;
signal tpacc_load_cmb : std_logic;
signal new_page : std_logic;
signal new_page_d1 : std_logic;
signal mem_cen_cmb : std_logic;
signal mem_oen_cmb : std_logic;
signal mem_wen_cmb : std_logic;
signal mem_cen_reg : std_logic;
signal mem_oen_reg : std_logic;
signal mem_wen_reg : std_logic;
signal read_complete_cmb : std_logic;
signal read_complete_d : std_logic_vector(0 to 7);
signal read_complete : std_logic;
signal mem_Addr_rst_cmb : std_logic;
signal transaction_done_cmb : std_logic;
signal transaction_done_reg : std_logic;
signal transaction_complete_reg : std_logic;
signal read_break_reg_d1 : std_logic;
signal addr_align_reg : std_logic;
signal addr_align_rd_d1 : std_logic;
signal Bus2IP_Mem_CS_d1 : std_logic;
signal Bus2IP_Mem_CS_d2 : std_logic;
signal Bus2IP_RdReq_d1 : std_logic;
signal Bus2IP_RdReq_d2 : std_logic;
signal read_break : std_logic;
signal transaction_complete : std_logic;
signal read_break_reg : std_logic;
signal Load_address : std_logic;
signal Write_req_data_ack_cmb : std_logic;
signal Write_req_addr_ack_cmb : std_logic;
signal address_strobe_cmb : std_logic;
signal be_strobe_cmb : std_logic;
signal data_strobe_cmb : std_logic;
signal int_Flash_mem_access_en : std_logic;
signal int_Flash_mem_access_dis : std_logic;
signal wlast,wlast_reg : std_logic;
signal wvalid,wvalid_reg : std_logic;
attribute max_fanout : string;
attribute max_fanout of read_req_ack_cmb : signal is "30";
--attribute max_fanout of write_req_ack_cmb : signal is "30";
attribute max_fanout of Write_req_data_ack_cmb : signal is "30";
attribute max_fanout of Write_req_addr_ack_cmb : signal is "30";
signal twr_rec_cnt_en_cmb : std_logic;
signal twr_rec_load_cmb : std_logic;
signal last_addr1_d1, last_addr1_d2, last_addr1_d3: std_logic; -- 09-12-2012
constant NEW_LOGIC: integer := 1;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
ns_idle <= '1' when next_state=IDLE
else
'0';
pr_idle <= '1' when crnt_state=IDLE
else
'0';
--wlast <= '1' when axi_wlast = '1' else wlast;
pr_state_wait_temp_cmb <= '1' when (next_state = WAIT_TEMP)
else
'0';
Write_req_ack <= '0';-- write_req_ack_cmb; --
Write_req_data_ack <= Write_req_data_ack_cmb;
Write_req_addr_ack <= Write_req_addr_ack_cmb;
Read_req_ack <= read_req_ack_cmb;
Read_data_en <= read_data_en_reg;
Read_ack <= Read_ack_reg ;
Read_ack_cmb <= (read_data_en_cmb and Cycle_End) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);
Addr_cnt_ce <= addr_cnt_ce_cmb;
Addr_cnt_rst <= addr_cnt_rst_cmb;
Address_strobe <= addressData_strobe_cmb;
CS_Strobe <= cs_strobe_reg;
CS_Strobe_par_addr <= Load_address and Bus2IP_RNW;
Cycle_cnt_ld <= cycle_cnt_ld_cmb;
Cycle_cnt_en <= cycle_cnt_en_cmb;
Trd_cnt_en <= trd_cnt_en_cmb;
Tpacc_cnt_en <= tpacc_cnt_en_cmb;
Twr_cnt_en <= twr_cnt_en_cmb;
Twph_cnt_en <= twph_cnt_en_cmb;
Twr_rec_cnt_en <= Twr_rec_cnt_en_cmb;--9/6/2011
Trd_load <= trd_load_cmb;
Tpacc_load <= tpacc_load_cmb;
Twr_load <= twr_load_cmb;
Twph_load <= twph_load_cmb;
Thz_load <= thz_load_cmb;
Tlz_load <= tlz_load_cmb;
Twr_rec_load <= Twr_rec_load_cmb;--9/6/2011
MSM_Mem_CEN <= mem_cen_cmb;
MSM_Mem_OEN <= mem_oen_cmb;
MSM_Mem_WEN <= mem_wen_cmb;
Mem_Addr_rst <= mem_Addr_rst_cmb;
Transaction_done <= transaction_done_reg;
--ADDR_CNT_SYNCH_MODE : process(Clk)
-- begin
-- if(Clk'EVENT and Clk = '1')then
-- if(Rst = '1')then
-- addr_cnt_numonyx <= '0';
-- elsif(Linear_flash_brst_rd_flag = '1') then
-- if(Linear_flash_rd_data_ack = '1') then
-- addr_cnt_numonyx <= not(addr_cnt_numonyx);
-- end if;
-- end if;
-- end if;
-- end process ADDR_CNT_SYNCH_MODE;
-- -------------------------------------------------------------------------------
-- -- Controls the flow of Read and write transaction performed based on type of
-- -- memory (synchronous/asynchronous) connected.
-- -------------------------------------------------------------------------------
-- OLD_LOGIC_GEN: if NEW_LOGIC = 0 generate
-- begin
--
-- SM_COMB_PROCESS: process (
-- crnt_state,
-- Bus2IP_RdReq,
-- Bus2IP_WrReq,
-- Synch_mem,
-- Cycle_End,
-- Trd_end,
-- Tpacc_end,
-- Twr_end,
-- Twph_end,
-- Thz_end,
-- Bus2IP_Mem_CS_d2,
-- Bus2IP_Mem_CS_d1,
-- read_break,
-- transaction_complete,
-- read_break_reg,
-- Tlz_end,
-- addr_align_rd_d1,
-- new_page_d1,
-- Addr_align,
-- New_page_access,
-- Bus2IP_Mem_CS,
-- single_trans,
-- new_page,
-- read_complete,
-- original_wrce,
-- last_burst_cnt,
-- transaction_complete_reg,
-- read_break_reg_d1,
-- Bus2IP_Burst,
-- Twr_rec_end,
-- Flash_mem_access,
-- Linear_flash_brst_rd_flag,--8/18/2011
-- Linear_flash_rd_data_ack, --8/18/2011
-- Mem_WAIT , -- CR#662558
-- Bus2IP_RdReq_emc ,
-- last_addr1
-- )
--
-- begin
--
-- next_state <= crnt_state;
-- mem_cen_cmb <= '1';
-- mem_oen_cmb <= '1';
-- mem_wen_cmb <= '1';
--
-- write_req_ack_cmb <= '0';
-- Write_req_data_ack_cmb <= '0';
-- Write_req_addr_ack_cmb <= '0';
--
-- read_req_ack_cmb <= '0';
-- read_data_en_cmb <= '0';
-- addr_cnt_ce_cmb <= '0';
-- addr_cnt_rst_cmb <= '0';
--
-- addressData_strobe_cmb <= '0';
-- address_strobe_cmb <= '0';
-- be_strobe_cmb <= '0';
-- data_strobe_cmb <= '0';
--
-- cs_strobe_cmb <= '0';
-- cycle_cnt_ld_cmb <= '0';
-- cycle_cnt_en_cmb <= '0';
--
-- trd_cnt_en_cmb <= '0';
-- tpacc_cnt_en_cmb <= '0';
-- twr_cnt_en_cmb <= '0';
-- twph_cnt_en_cmb <= '0';
-- twr_rec_cnt_en_cmb <= '0';-- 9/6/2011
--
-- trd_load_cmb <= '0';
-- tpacc_load_cmb <= '0';
-- twr_load_cmb <= '0';
-- twph_load_cmb <= '0';
-- thz_load_cmb <= '0';
-- tlz_load_cmb <= '0';
-- twr_rec_load_cmb <= '0'; -- 9/6/2011
--
-- read_complete_cmb <= '0';
-- addr_align_reg <= addr_align_rd_d1;
-- new_page <= new_page_d1;
--
-- transaction_complete <= transaction_complete_reg;
-- read_break_reg <= read_break_reg_d1;
--
-- mem_Addr_rst_cmb <= '0';
-- transaction_done_cmb <= '0';
-- Flash_mem_access_disable <= '0';
-- Adv_L_N <= '1';
-- case crnt_state is
--
-- -------------------------------------------------------------------
-- -- IDLE STATE
-- -- Waits in this state untill read and write transaction is
-- -- initiated.
-- -- Loads the counters.
-- -- Generates appropriate gate signal (burst/single) which is used
-- -- to let read transfer ack pass to the IPIF.
-- -------------------------------------------------------------------
--
-- when IDLE =>
--
-- transaction_done_cmb <= '1';
--
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
-- cs_strobe_cmb <= '1';
-- mem_Addr_rst_cmb <= '1';
-- new_page <= '0';
-- addr_align_reg <= '0';
-- read_break_reg <= '0';
--
-- if (Bus2IP_WrReq = '1' and Thz_end = '1') then
-- if Synch_mem = '0' and single_trans = '0' then
-- write_req_ack_cmb <= '1';
-- Write_req_data_ack_cmb <= '1';
-- Write_req_addr_ack_cmb <= '1';
-- end if;
-- twr_load_cmb <= '1';
-- twph_load_cmb <= '1';
-- next_state <= WRITE;
-- transaction_done_cmb <= '0';
-- transaction_complete <= '0';
-- addr_align_reg <= '0';
--
-- elsif (Bus2IP_RdReq = '1' and Tlz_end = '1') then
-- read_req_ack_cmb <= '1';
-- trd_load_cmb <= '1';
-- if(Linear_flash_brst_rd_flag = '1')then
-- next_state <= LINEAR_FLASH_SYNC_RD;
-- Adv_L_N <= '0';
-- mem_cen_cmb <= '0';
-- mem_oen_cmb <= '0';
--
-- else
-- next_state <= READ;
-- end if;
-- transaction_done_cmb <= '0';
-- addr_align_reg <= Addr_align;
-- transaction_complete <= '0';
-- end if;
--
-- -------------------------------------------------------------------
-- -- WRITE STATE
-- -- Controls write operation to the memory.
-- -- Generates control signals for write, address, and cycle end
-- -- counters.
-- -------------------------------------------------------------------
--
-- when WRITE =>
--
--
-- mem_cen_cmb <= '0';
-- mem_wen_cmb <= '0';
--
-- if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
-- end if;
--
--
-- if (Twr_end = '1') then
-- if Synch_mem = '1' then
-- if (Cycle_End = '1') then
-- if (Bus2IP_WrReq = '1')then
-- write_req_ack_cmb <= '1';
-- Write_req_data_ack_cmb <= '1';
-- Write_req_addr_ack_cmb <= '1';
--
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
-- twr_load_cmb <= '1';
--
-- if(single_trans = '1')then--CR#606038 is fixed
-- next_state <= WAIT_WRITE_ACK;
-- else
-- next_state <= WRITE;
-- end if;--
-- else
-- twr_rec_load_cmb <= flash_mem_access;
-- next_state <= WAIT_WRITE_ACK;
-- end if;
-- else
-- twr_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1';
-- end if;
-- else
-- twph_cnt_en_cmb <= '1';
-- next_state <= DASSERT_WEN;
-- if single_trans = '1' then
-- write_req_ack_cmb <= '1';
-- if(flash_mem_access = '1') then
-- Write_req_data_ack_cmb <= '0';
-- else
-- Write_req_data_ack_cmb <= '1';
-- end if;
-- Write_req_addr_ack_cmb <= '1';
-- end if;
-- end if;
-- else
-- twr_cnt_en_cmb <= '1';
-- end if;
-- -----------------
-- when WAIT_TEMP =>
-- if (Bus2IP_WrReq = '1' and Thz_end = '1') then
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
-- cs_strobe_cmb <= '1';
-- mem_Addr_rst_cmb <= '1';
-- addr_align_reg <= '0';
-- twr_load_cmb <= '1';
-- next_state <= WRITE;
-- addr_align_reg <= '0';
-- twph_load_cmb <= '1';
-- if (last_burst_cnt = '0' and
-- Synch_mem = '0' and
-- single_trans = '0')then
-- write_req_ack_cmb <= '1';
-- Write_req_data_ack_cmb <= '1';
-- Write_req_addr_ack_cmb <= '1';
-- end if;
-- elsif (transaction_complete = '1') or
-- (Bus2IP_Mem_CS = '0' and Bus2IP_WrReq = '0') then
-- twr_rec_load_cmb <= flash_mem_access;
-- next_state <= WAIT_WRITE_ACK;
-- else
-- next_state <= WAIT_TEMP;
-- end if;
-- -------------------------------------------------------------------
-- -- DASSERT_WEN STATE
-- -- Comes to this state only when write operation is performed on
-- -- asynchronous memory.This state performs NOP cycle on memory side.
-- -- Generates control signals for write, address and cycle end
-- -- counters.
-- -------------------------------------------------------------------
--
-- when DASSERT_WEN =>
--
--
-- if (Cycle_End = '1') then
-- if (Bus2IP_WrReq = '1') then
-- if (twph_end = '1') then
-- write_req_ack_cmb <= '1';
-- Write_req_data_ack_cmb <= '1';
-- Write_req_addr_ack_cmb <= '1';
--
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
-- twr_load_cmb <= '1';
-- twph_load_cmb <= '1';
-- next_state <= WRITE;
-- else
-- next_state <= DASSERT_WEN;
-- twph_cnt_en_cmb <= '1';
-- end if;
-- elsif (Bus2IP_Mem_CS = '1' and
-- Bus2IP_WrReq = '0' and
-- Bus2IP_RdReq = '0')then
-- if(last_addr1 = '1') then
-- next_state <= WRITE;
-- else
-- next_state <= WAIT_TEMP;
-- end if;
-- address_strobe_cmb <= last_addr1;--
-- be_strobe_cmb <= last_addr1;-- '1';
-- data_strobe_cmb <= last_addr1;-- '1';
-- twr_rec_load_cmb <= flash_mem_access;
--
-- write_req_ack_cmb <= last_addr1;-- '0';
-- Write_req_data_ack_cmb <= last_addr1;-- '0';
-- Write_req_addr_ack_cmb <= last_addr1;-- '0';
--
-- addr_cnt_rst_cmb <= '0';
-- cycle_cnt_ld_cmb <= '0';
-- twr_load_cmb <= '0';
-- else
-- twr_rec_load_cmb <= flash_mem_access;
-- next_state <= WAIT_WRITE_ACK;
-- end if;
-- else
-- if (twph_end = '1') then
-- twr_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1';
-- twph_load_cmb <= '1';
-- next_state <= WRITE;
-- else
-- twph_cnt_en_cmb <= '1';
-- end if;
-- end if;
--
-- -------------------------------------------------------------------
-- -- WAIT_WRITE_ACK STATE
-- -------------------------------------------------------------------
--
-- when WAIT_WRITE_ACK =>
-- if(flash_mem_access = '1') then
-- twr_rec_cnt_en_cmb <= '1';
-- next_state <= WR_REC_PERIOD;
-- else
-- next_state <= IDLE;
-- end if;
-- tlz_load_cmb <= '1';
-- addr_cnt_rst_cmb <= '1';
-- transaction_done_cmb <= '1';
--
-- when WR_REC_PERIOD =>
-- if(Twr_rec_end = '1')then
-- Flash_mem_access_disable <= '1';
-- Write_req_data_ack_cmb <= '1';
-- next_state <= IDLE;
-- else
-- twr_rec_cnt_en_cmb <= '1';
-- next_state <= WR_REC_PERIOD;
-- end if;
--
--
--
-- -------------------------------------------------------------------
-- -- READ STATE
-- -- Controls read operation on memory.
-- -- Generates control signals for read, address and cycle end
-- -- counters
-- -------------------------------------------------------------------
-- -- when LINEAR_FLASH_SYNC_RD =>
-- -- mem_cen_cmb <= '0';
-- -- mem_oen_cmb <= '0';
-- --
-- -- if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- -- transaction_complete <= '1';
-- -- end if;
-- -- if (Linear_flash_rd_data_ack = '1') then
-- -- read_data_en_cmb <= '1';
-- -- addr_align_reg <= Addr_align;
-- -- if (Cycle_End = '1') then
-- -- if ((Bus2IP_RdReq='1' or single_trans = '1')and
-- -- read_break_reg = '0' and
-- -- transaction_complete = '0') then
-- -- read_req_ack_cmb <= '1';
-- -- addressData_strobe_cmb <= '1';
-- -- address_strobe_cmb <= '1';
-- -- be_strobe_cmb <= '1';
-- -- data_strobe_cmb <= '1';
-- -- addr_cnt_rst_cmb <= '1';
-- -- cycle_cnt_ld_cmb <= '1';
-- -- next_state <= LINEAR_FLASH_SYNC_RD;
-- -- else
-- -- next_state <= WAIT_RDDATA_ACK;
-- -- read_complete_cmb <= '1';
-- -- read_data_en_cmb <= '0';
-- -- end if;
-- -- else
-- -- trd_load_cmb <= '1';
-- -- cycle_cnt_en_cmb <= '1';
-- -- addr_cnt_ce_cmb <= '1';
-- -- end if;
-- -- end if;
--
-- when LINEAR_FLASH_SYNC_RD =>
-- if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
-- end if;
--
-- if (read_break= '1' and single_trans = '0') then
-- read_break_reg <= '1';
-- end if;
-- Adv_L_N <= '1';
-- mem_cen_cmb <= '0';
-- mem_oen_cmb <= '0';
-- new_page <= '0';
-- -- added for abort condition
-- if (Mem_WAIT = '1') then
-- read_data_en_cmb <= Linear_flash_rd_data_ack;
-- addr_align_reg <= Addr_align;
-- if (Cycle_End = '1') then
-- if ((Bus2IP_RdReq='1' or single_trans = '1')and
-- read_break_reg = '0' and
-- transaction_complete = '0') then
--
-- read_req_ack_cmb <= '1';
--
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
--
-- trd_load_cmb <= '1';
-- next_state <= LINEAR_FLASH_SYNC_RD;
-- else
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= '1';
-- read_data_en_cmb <= '0';
-- end if;
-- else
-- -- trd_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1';
-- end if;
-- else
-- trd_cnt_en_cmb <= '1';
-- end if;
--
--
--
--
-- -------------------------------------------------------------------
-- -- READ STATE
-- -- Controls read operation on memory.
-- -- Generates control signals for read, address and cycle end
-- -- counters
-- -------------------------------------------------------------------
--
-- when READ =>
-- if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
-- end if;
--
-- if (read_break= '1' and single_trans = '0') then
-- read_break_reg <= '1';
-- end if;
--
-- mem_cen_cmb <= '0';
-- mem_oen_cmb <= '0';
-- new_page <= '0';
-- -- added for abort condition
-- if (Trd_end = '1') then
-- read_data_en_cmb <= '1';
-- addr_align_reg <= Addr_align;
-- if (Cycle_End = '1') then
-- if ((Bus2IP_RdReq='1' or single_trans = '1')and
-- read_break_reg = '0' and
-- transaction_complete = '0') then
--
-- read_req_ack_cmb <= '1';
--
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= Bus2IP_RdReq_emc;-- '1';-- Bus2IP_RdReq_emc; -- '1';
-- cycle_cnt_ld_cmb <= '1';
--
-- if New_page_access = '0' then
-- next_state <= PAGE_READ;
-- tpacc_load_cmb <= '1';
-- else
-- trd_load_cmb <= '1';
-- next_state <= READ;
-- end if;
-- else
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= '1';
-- read_data_en_cmb <= '1';
-- end if;
-- else
-- trd_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1'; -- Bus2IP_RdReq; -- '1';
-- end if;
-- else
-- trd_cnt_en_cmb <= '1';
-- end if;
--
-- -------------------------------------------------------------------
-- -- PAGE_READ State =>
-- -- Will do a page read when ever there is a page aligned boundry
-- -------------------------------------------------------------------
-- when PAGE_READ =>
--
-- if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
-- end if;
--
-- mem_cen_cmb <= '0';
-- mem_oen_cmb <= '0';
--
-- if (read_break= '1' and single_trans = '0') then
-- read_break_reg <= '1';
-- end if;
-- -- added for abort condition
-- if (Tpacc_end = '1') then
-- addr_align_reg <= Addr_align;
-- read_data_en_cmb <= '1';
-- if (Cycle_End = '1') then
-- if (Bus2IP_RdReq = '1' and
-- read_break = '0' and
-- transaction_complete = '0') then
--
-- read_req_ack_cmb <= '1';
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
--
-- If new_page = '0' then
-- tpacc_load_cmb <= '1';
-- next_state <= PAGE_READ;
-- else
-- trd_load_cmb <= '1';
-- next_state <= READ;
-- end if;
-- else
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= '1';
-- read_data_en_cmb <= '1';
-- end if;
-- else
-- tpacc_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1';
-- end if;
-- else
-- tpacc_cnt_en_cmb <= '1';
-- if New_page_access = '1' then
-- new_page <= '1';
-- end if;
-- end if;
--
--
--
-- -------------------------------------------------------------------
-- -- WAIT_RDDATA_ACK STATE
-- -- Waits in this state till read data is received from memory.
-- -------------------------------------------------------------------
--
-- when WAIT_RDDATA_ACK =>
--
-- if read_complete = '1' then
-- next_state <= IDLE;
-- thz_load_cmb <= '1';
-- transaction_done_cmb <= '1';
-- end if;
-- addr_align_reg <= Addr_align;
-- new_page <= '0';
-- addr_cnt_rst_cmb <= '1';
-- read_data_en_cmb <= '0';
-- read_break_reg <= '0';
--
-- if (Bus2IP_Mem_CS_d2 = '1' and
-- Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
-- end if;
--
-- end case;
-- end process SM_COMB_PROCESS;
-- end generate OLD_LOGIC_GEN;
NEW_LOGIC_GEN: if NEW_LOGIC = 1 generate
-----
begin
-----
SM_COMB_PROCESS: process (
crnt_state,
Bus2IP_RdReq,
Bus2IP_WrReq,
Synch_mem,
Cycle_End,
Trd_end,
Tpacc_end,
Twr_end,
Twph_end,
Thz_end,
Bus2IP_Mem_CS_d2,
Bus2IP_Mem_CS_d1,
read_break,
transaction_complete,
read_break_reg,
Tlz_end,
addr_align_rd_d1,
new_page_d1,
Addr_align,
New_page_access,
Bus2IP_Mem_CS,
single_trans,
new_page,
read_complete,
original_wrce,
last_burst_cnt,
transaction_complete_reg,
read_break_reg_d1,
Bus2IP_Burst,
Twr_rec_end,
Flash_mem_access,
Linear_flash_brst_rd_flag,--8/18/2011
Linear_flash_rd_data_ack, --8/18/2011
Mem_WAIT , -- CR#662558
Bus2IP_RdReq_emc ,
last_addr1 ,
last_addr1_d1, -- 09-12-2012
last_addr1_d2, -- 09-12-2012
last_addr1_d3, -- 09-12-2012
stop_oen,
bus2ip_ben_all_1,
axi_wvalid,
wlast_reg,
wvalid_reg,
wlast,
wvalid,
axi_wlast
)
begin
next_state <= crnt_state;
mem_cen_cmb <= '1';
mem_oen_cmb <= '1';
mem_wen_cmb <= '1';
--write_req_ack_cmb <= '0';09-12-2012
Write_req_data_ack_cmb <= '0';
Write_req_addr_ack_cmb <= '0';
read_req_ack_cmb <= '0';
read_data_en_cmb <= '0';
addr_cnt_ce_cmb <= '0';
addr_cnt_rst_cmb <= '0';
--addressData_strobe_cmb <= '0';09-12-2012 not used in the logic
address_strobe_cmb <= '0';
be_strobe_cmb <= '0';
data_strobe_cmb <= '0';
cs_strobe_cmb <= '0';
cycle_cnt_ld_cmb <= '0';
cycle_cnt_en_cmb <= '0';
trd_cnt_en_cmb <= '0';
tpacc_cnt_en_cmb <= '0';
twr_cnt_en_cmb <= '0';
twph_cnt_en_cmb <= '0';
twr_rec_cnt_en_cmb <= '0';-- 9/6/2011
trd_load_cmb <= '0';
tpacc_load_cmb <= '0'; -- '0'; -- 1/4/2013
twr_load_cmb <= '0';
twph_load_cmb <= '0';
thz_load_cmb <= '0';
tlz_load_cmb <= '0';
twr_rec_load_cmb <= '0'; -- 9/6/2011
read_complete_cmb <= '0';
addr_align_reg <= addr_align_rd_d1;
new_page <= new_page_d1;
transaction_complete <= transaction_complete_reg;
read_break_reg <= read_break_reg_d1;
mem_Addr_rst_cmb <= '0';
transaction_done_cmb <= '0';
Flash_mem_access_disable <= '0';
Adv_L_N <= '1';
wlast <= wlast_reg;
wvalid <= wvalid_reg;
case crnt_state is
-------------------------------------------------------------------
-- IDLE STATE
-- Waits in this state untill read and write transaction is
-- initiated.
-- Loads the counters.
-- Generates appropriate gate signal (burst/single) which is used
-- to let read transfer ack pass to the IPIF.
-------------------------------------------------------------------
when IDLE =>
transaction_done_cmb <= '1';
--addressData_strobe_cmb <= '1';
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
addr_cnt_rst_cmb <= '1';
cycle_cnt_ld_cmb <= '1';
cs_strobe_cmb <= '1';
mem_Addr_rst_cmb <= '1';
new_page <= '0';
addr_align_reg <= '0';
read_break_reg <= '0';
if (Bus2IP_WrReq = '1' and Thz_end = '1' and Bus2IP_Mem_CS = '1') then
--if Synch_mem = '0' and single_trans = '0' then
--if single_trans = '0' and Synch_mem = '1' then
-- --write_req_ack_cmb <= '1';-- 09-12-2012
-- Write_req_data_ack_cmb <= '1';
-- Write_req_addr_ack_cmb <= '1';
--end if;
if single_trans = '1' and synch_mem = '1' then
--next_state <= WAIT_WRITE_ACK;
wlast <= '1';
else
--next_state <= WRITE;
wlast <= '0';
end if;
next_state <= WRITE;
twr_load_cmb <= '1';
twph_load_cmb <= '1';
transaction_done_cmb <= '0';
transaction_complete <= '0';
addr_align_reg <= '0';
wvalid <= '1';
elsif (Bus2IP_RdReq = '1' and Tlz_end = '1' and Bus2IP_Mem_CS = '1') then
-- read_req_ack_cmb <= '1';
trd_load_cmb <= '1';
mem_cen_cmb <= not single_trans; -- '0'; -- 1/3/2013
mem_oen_cmb <= not single_trans; -- '0'; -- 1/3/2013
if(Linear_flash_brst_rd_flag = '1')then
next_state <= LINEAR_FLASH_SYNC_RD;
Adv_L_N <= '0';
read_req_ack_cmb <= '0';
--mem_cen_cmb <= '0';-- 1/3/2013
--mem_oen_cmb <= '0';-- 1/3/2013
else
read_req_ack_cmb <= '1';
next_state <= READ;
end if;
transaction_done_cmb <= '0';
addr_align_reg <= Addr_align;
transaction_complete <= '0';
end if;
-------------------------------------------------------------------
-- WRITE STATE
-- Controls write operation to the memory.
-- Generates control signals for write, address, and cycle end
-- counters.
-------------------------------------------------------------------
when WRITE =>
if axi_wlast = '1' and axi_wvalid = '1' then
wlast <= '1';
end if;
mem_cen_cmb <= '0';
mem_wen_cmb <= '0';
if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
transaction_complete <= '1';
end if;
if (Twr_end = '1') then
-- sync mem starts
if Synch_mem = '1' then
if (Cycle_End = '1') then
if (Bus2IP_WrReq = '1' and axi_wvalid = '0' and wlast = '0') then
Write_req_data_ack_cmb <= '1';
Write_req_addr_ack_cmb <= '1';
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
addr_cnt_rst_cmb <= '1';
cycle_cnt_ld_cmb <= '1';
next_state <= WRITE_WAIT;
wvalid <= '0';
elsif (Bus2IP_WrReq = '1' and (wvalid = '1' or axi_wvalid = '1'))then
--write_req_ack_cmb <= '1';09-12-2012
--if axi_wvalid = '1' then
Write_req_data_ack_cmb <= '1';
Write_req_addr_ack_cmb <= '1';
--end if;
--addressData_strobe_cmb <= '1';09-12-2012
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
addr_cnt_rst_cmb <= '1';
cycle_cnt_ld_cmb <= '1';
--twr_load_cmb <= '1'; NOT required in Sync Write mode
elsif (Bus2IP_WrReq = '1' and wlast = '1') then
Write_req_data_ack_cmb <= '1';
Write_req_addr_ack_cmb <= '1';
next_state <= WAIT_WRITE_ACK;
elsif (Bus2IP_WrReq = '0') then
twr_rec_load_cmb <= flash_mem_access;-- this can be moved to idle state set to 1
next_state <= WAIT_WRITE_ACK;
else
next_state <= WRITE;
end if;
else
--twr_load_cmb <= '1'; -- not needed in sync write mode
cycle_cnt_en_cmb <= '1';
addr_cnt_ce_cmb <= '1';
end if;
-- sync mem ends
-- async mem starts
else
-- mem_cen_cmb <= '1'; -- 1/3/2013
-- mem_wen_cmb <= '1'; -- 1/3/2013
twph_cnt_en_cmb <= '1';
next_state <= DASSERT_WEN;
if single_trans = '1' then
--write_req_ack_cmb <= '1';09-12-2012
--if(flash_mem_access = '1') then
-- Write_req_data_ack_cmb <= '0';
-- --elsif (axi_wvalid = '1') then
-- -- Write_req_data_ack_cmb <= '1';
-- else
-- Write_req_data_ack_cmb <= '1';
--end if;
-- --if axi_wvalid = '1' then
--Write_req_addr_ack_cmb <= '1';
--end if;
end if;
end if;
-- async mem ends
else
twr_cnt_en_cmb <= '1';
end if;
-----------------
when WRITE_WAIT =>
if (Bus2IP_WrReq = '1' and axi_wvalid = '1' ) then
next_state <= WRITE;
wvalid <= '1';
if axi_wlast = '1' and axi_wvalid = '1' then
wlast <= '1';
end if;
else
next_state <= WRITE_WAIT;
end if;
when WAIT_TEMP =>
if axi_wlast = '1' and axi_wvalid = '1' then
wlast <= '1';
end if;
if (Bus2IP_WrReq = '1' and Thz_end = '1' ) then
--addressData_strobe_cmb <= '1'; 09-12-2012
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
addr_cnt_rst_cmb <= '1';
cycle_cnt_ld_cmb <= '1';
cs_strobe_cmb <= '1';
mem_Addr_rst_cmb <= '1';
addr_align_reg <= '0';
twr_load_cmb <= '1';
next_state <= WRITE;
addr_align_reg <= '0';
twph_load_cmb <= '1';
if (last_burst_cnt = '0' and
Synch_mem = '0' and
single_trans = '0') then
--single_trans = '0' and
--axi_wvalid = '1')then
--write_req_ack_cmb <= '1';09-12-2012
Write_req_data_ack_cmb <= '1';
Write_req_addr_ack_cmb <= '1';
end if;
elsif (transaction_complete = '1') or
(Bus2IP_Mem_CS = '0' and Bus2IP_WrReq = '0') then
twr_rec_load_cmb <= flash_mem_access;
next_state <= WAIT_WRITE_ACK;
else
next_state <= WAIT_TEMP;
end if;
-------------------------------------------------------------------
-- DASSERT_WEN STATE
-- Comes to this state only when write operation is performed on
-- asynchronous memory.This state performs NOP cycle on memory side.
-- Generates control signals for write, address and cycle end
-- counters.
-------------------------------------------------------------------
when DASSERT_WEN =>
if axi_wlast = '1' and axi_wvalid = '1' then
wlast <= '1';
end if;
if (Cycle_End = '1') then
if (Bus2IP_WrReq = '1') then
if (twph_end = '1') then
-- write_req_ack_cmb <= '1'; 09-12-2012
--if axi_wvalid = '1' then
Write_req_data_ack_cmb <= '1';
Write_req_addr_ack_cmb <= '1';
--end if;
--addressData_strobe_cmb <= '1';09-12-2012
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
addr_cnt_rst_cmb <= '1';
cycle_cnt_ld_cmb <= '1';
twr_load_cmb <= '1';
twph_load_cmb <= '1';
if (single_trans = '1') then
next_state <= WAIT_WRITE_ACK;
twr_rec_load_cmb <= flash_mem_access;
elsif (axi_wvalid = '1' or wlast = '1') then
next_state <= WRITE;
else
next_state <= WRITE_WAIT;
end if;
else
next_state <= DASSERT_WEN;
twph_cnt_en_cmb <= '1';
end if;
elsif (Bus2IP_Mem_CS = '1' and
Bus2IP_WrReq = '0' and
Bus2IP_RdReq = '0')then
if(last_addr1 = '1' and bus2ip_ben_all_1 = '1') then
next_state <= WRITE;
else
next_state <= WAIT_TEMP;
end if;
address_strobe_cmb <= last_addr1;--
be_strobe_cmb <= last_addr1;-- '1';
data_strobe_cmb <= last_addr1;-- '1';
twr_rec_load_cmb <= flash_mem_access;
-- write_req_ack_cmb <= last_addr1;-- '0';09-12-2012
--if axi_wvalid = '1' then
Write_req_data_ack_cmb <= last_addr1;-- '0';
Write_req_addr_ack_cmb <= last_addr1;-- '0';
--end if;
addr_cnt_rst_cmb <= '0';
cycle_cnt_ld_cmb <= '0';
twr_load_cmb <= '0';
else
twr_rec_load_cmb <= flash_mem_access;
next_state <= WAIT_WRITE_ACK;
end if;
else
if (twph_end = '1') then
twr_load_cmb <= '1';
cycle_cnt_en_cmb <= '1';
addr_cnt_ce_cmb <= '1';
twph_load_cmb <= '1';
next_state <= WRITE;
else
twph_cnt_en_cmb <= '1';
end if;
end if;
-------------------------------------------------------------------
-- WAIT_WRITE_ACK STATE
-------------------------------------------------------------------
when WAIT_WRITE_ACK =>
--if synch_mem = '1' then
-- Write_req_data_ack_cmb <= '1';
-- Write_req_addr_ack_cmb <= '1';
--end if;
if(flash_mem_access = '1') then
twr_rec_cnt_en_cmb <= '1';
next_state <= WR_REC_PERIOD;
else
next_state <= IDLE;
end if;
tlz_load_cmb <= '1';
addr_cnt_rst_cmb <= '1';
transaction_done_cmb <= '1';
wlast <= '0';
when WR_REC_PERIOD =>
if(Twr_rec_end = '1')then
Flash_mem_access_disable <= '1';
--Write_req_data_ack_cmb <= '1';
next_state <= IDLE;
else
twr_rec_cnt_en_cmb <= '1';
next_state <= WR_REC_PERIOD;
end if;
-------------------------------------------------------------------
-- READ STATE
-- Controls read operation on memory.
-- Generates control signals for read, address and cycle end
-- counters
-------------------------------------------------------------------
-- when LINEAR_FLASH_SYNC_RD =>
-- mem_cen_cmb <= '0';
-- mem_oen_cmb <= '0';
--
-- if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
-- end if;
-- if (Linear_flash_rd_data_ack = '1') then
-- read_data_en_cmb <= '1';
-- addr_align_reg <= Addr_align;
-- if (Cycle_End = '1') then
-- if ((Bus2IP_RdReq='1' or single_trans = '1')and
-- read_break_reg = '0' and
-- transaction_complete = '0') then
-- read_req_ack_cmb <= '1';
-- addressData_strobe_cmb <= '1';
-- address_strobe_cmb <= '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
-- addr_cnt_rst_cmb <= '1';
-- cycle_cnt_ld_cmb <= '1';
-- next_state <= LINEAR_FLASH_SYNC_RD;
-- else
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= '1';
-- read_data_en_cmb <= '0';
-- end if;
-- else
-- trd_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1';
-- end if;
-- end if;
when LINEAR_FLASH_SYNC_RD =>
if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
transaction_complete <= '1';
end if;
if (read_break= '1' and single_trans = '0') then
read_break_reg <= '1';
end if;
Adv_L_N <= '1';
mem_cen_cmb <= not Bus2IP_RdReq_emc; -- '0';
mem_oen_cmb <= not Bus2IP_RdReq_emc; -- '0';
new_page <= '0';
-- added for abort condition
if (Mem_WAIT = '1') then
read_data_en_cmb <= Linear_flash_rd_data_ack;
addr_align_reg <= Addr_align;
if (Cycle_End = '1') then
if (Bus2IP_RdReq='1') then -- or single_trans = '1')and
-- read_break_reg = '0' and
-- transaction_complete = '0') then
read_req_ack_cmb <= '1';
--addressData_strobe_cmb <= '1';09-12-2012
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
if (single_trans = '0') then
addr_cnt_rst_cmb <= '1';
end if;
cycle_cnt_ld_cmb <= '1';
trd_load_cmb <= '1';
next_state <= LINEAR_FLASH_SYNC_RD;
else
next_state <= WAIT_RDDATA_ACK;
read_complete_cmb <= '1';
read_data_en_cmb <= '0';
end if;
else
trd_load_cmb <= '1';
cycle_cnt_en_cmb <= '1';
if (Bus2IP_RdReq='1') then
addr_cnt_ce_cmb <= '1';
end if;
next_state <= LINEAR_FLASH_SYNC_RD;
end if;
else
if(Bus2IP_RdReq = '0') then
next_state <= WAIT_RDDATA_ACK;
read_complete_cmb <= '1';
else
next_state <= LINEAR_FLASH_SYNC_RD;
trd_cnt_en_cmb <= '1';
end if;
end if;
-------------------------------------------------------------------
-- READ STATE
-- Controls read operation on memory.
-- Generates control signals for read, address and cycle end
-- counters
-------------------------------------------------------------------
when READ =>
--if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
-- transaction_complete <= '1';
--end if;
if (read_break= '1' and single_trans = '0') then
read_break_reg <= '1';
end if;
-- mem_cen_cmb <= not (single_trans or Bus2IP_Burst); --'0';
-- mem_oen_cmb <= not(single_trans or Bus2IP_Burst); --'0';
mem_cen_cmb <= (synch_mem and stop_oen) or ((not synch_mem) and read_break_reg); --'0';
mem_oen_cmb <= (synch_mem and stop_oen) or ((not synch_mem) and read_break_reg); --'0';
new_page <= '0';
-- added for abort condition
if (Trd_end = '1') then
read_data_en_cmb <= '1'; -- generates are read data ack
addr_align_reg <= Addr_align;
if (Cycle_End = '1') then
if (Bus2IP_RdReq='1') then -- or single_trans = '1')and
-- read_break_reg = '0' and
-- transaction_complete = '0') then -- or (stop_oen = '0' and synch_mem = '1') then
read_req_ack_cmb <= '1';--not last_addr1_d2; -- '1';
--addressData_strobe_cmb <= '1';09-12-2012
address_strobe_cmb <= '1';--not last_addr1_d2; -- '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
if (single_trans='0' or synch_mem = '1') then
addr_cnt_rst_cmb <= '1'; -- Bus2IP_RdReq_emc;-- '1';-- Bus2IP_RdReq_emc; -- '1';
end if;
cycle_cnt_ld_cmb <= '1';
tpacc_load_cmb <= '1';
if New_page_access = '0' then
next_state <= PAGE_READ;
-- tpacc_cnt_en_cmb <= '1';
-- tpacc_load_cmb <= '1'; -- 1/4/2013
cycle_cnt_en_cmb <= '1';-- 1/12/2013
addr_cnt_ce_cmb <= '1';-- 1/12/2013
else
trd_load_cmb <= '1';
next_state <= READ;
end if;
else
next_state <= WAIT_RDDATA_ACK;
read_complete_cmb <= '1'; -- stop_oen; -- '1';
read_data_en_cmb <= '1';
end if;
else
--if(read_break_reg = '1' and synch_mem = '0')then
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= stop_oen;
--else
-- next_state <= READ;
--end if;
if (Bus2IP_RdReq='1' or synch_mem = '1') then
addr_cnt_ce_cmb <= '1';
end if;
if(New_page_access = '0') then
next_state <= PAGE_READ;
tpacc_load_cmb <= '1';
--tpacc_cnt_en_cmb <= '1';
cycle_cnt_en_cmb <= '1';-- 1/11/2013
--addr_cnt_ce_cmb <= '1';-- 1/11/2013
else
next_state <= READ;
trd_load_cmb <= '1';
cycle_cnt_en_cmb <= '1';
--addr_cnt_ce_cmb <= '1';-- not last_addr1_d3; -- '1'; -- Bus2IP_RdReq; -- '1';
-- addr_cnt_rst_cmb <= not Bus2IP_Burst; -- newly added
end if;
end if;
else
if(read_break_reg = '1' and synch_mem = '0')then
next_state <= WAIT_RDDATA_ACK;
read_complete_cmb <= '1';
-- read_complete_cmb <= stop_oen;
else
next_state <= READ;
end if;
--if(read_break = '1')then
--else
trd_cnt_en_cmb <= '1';
-- end if;
end if;
-- added for abort condition
-- if (Trd_end = '1') then
-- read_data_en_cmb <= '1'; -- generates are read data ack
-- addr_align_reg <= Addr_align;
-- if (Cycle_End = '1') then
-- if ((Bus2IP_RdReq='1' or single_trans = '1')and
-- read_break_reg = '0' and
-- transaction_complete = '0') then -- or (stop_oen = '0' and synch_mem = '1') then
--
-- read_req_ack_cmb <= '1';--not last_addr1_d2; -- '1';
--
-- --addressData_strobe_cmb <= '1';09-12-2012
-- address_strobe_cmb <= '1';--not last_addr1_d2; -- '1';
-- be_strobe_cmb <= '1';
-- data_strobe_cmb <= '1';
--
-- addr_cnt_rst_cmb <= Bus2IP_RdReq_emc;-- '1';-- Bus2IP_RdReq_emc; -- '1';
-- cycle_cnt_ld_cmb <= '1';
--
-- if New_page_access = '0' then
-- next_state <= PAGE_READ;
-- tpacc_load_cmb <= '1';
-- else
-- trd_load_cmb <= '1';
-- next_state <= READ;
-- end if;
-- else
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= '1'; -- stop_oen; -- '1';
-- read_data_en_cmb <= '1';
-- end if;
-- else
-- --if(read_break_reg = '1' and synch_mem = '0')then
-- -- next_state <= WAIT_RDDATA_ACK;
-- -- read_complete_cmb <= stop_oen;
-- --else
-- -- next_state <= READ;
-- --end if;
-- trd_load_cmb <= '1';
-- cycle_cnt_en_cmb <= '1';
-- addr_cnt_ce_cmb <= '1';-- not last_addr1_d3; -- '1'; -- Bus2IP_RdReq; -- '1';
-- -- addr_cnt_rst_cmb <= not Bus2IP_Burst; -- newly added
-- end if;
-- else
-- if(read_break_reg = '1' and synch_mem = '0')then
-- next_state <= WAIT_RDDATA_ACK;
-- read_complete_cmb <= stop_oen;
-- else
-- next_state <= READ;
-- end if;
-- --if(read_break = '1')then
-- --else
-- trd_cnt_en_cmb <= '1';
-- -- end if;
-- end if;
-------------------------------------------------------------------
-- PAGE_READ State =>
-- Will do a page read when ever there is a page aligned boundry
-------------------------------------------------------------------
when PAGE_READ =>
if (Bus2IP_Mem_CS_d2 = '1' and Bus2IP_Mem_CS_d1 = '0') then
transaction_complete <= '1';
end if;
mem_cen_cmb <= read_break_reg; -- not Bus2IP_Burst;-- read_break_reg; -- '0'; -- 1/4/2013
mem_oen_cmb <= read_break_reg; -- not Bus2IP_Burst;-- read_break_reg; -- '0'; -- 1/4/2013
if (read_break= '1' and single_trans = '0') then
read_break_reg <= '1';
end if;
-- added for abort condition
if (Tpacc_end = '1') then
addr_align_reg <= Addr_align;
read_data_en_cmb <= '1'; -- generates are read data ack
if (Cycle_End = '1') then
if (Bus2IP_RdReq = '1' --and
--read_break = '0' and
--transaction_complete = '0'
) then
read_req_ack_cmb <= '1';
-- addressData_strobe_cmb <= '1';09-12-2012
address_strobe_cmb <= '1';
be_strobe_cmb <= '1';
data_strobe_cmb <= '1';
if (single_trans = '0') then
addr_cnt_rst_cmb <= '1';-- Bus2IP_RdReq_emc;-- '1';
end if;
cycle_cnt_ld_cmb <= '1';
If new_page = '0' then
tpacc_load_cmb <= '1';
next_state <= PAGE_READ;
else
trd_load_cmb <= '1';
next_state <= READ;
end if;
else
next_state <= WAIT_RDDATA_ACK;
read_complete_cmb <= '1';
read_data_en_cmb <= '0';-- '1'; 09-12-2012
end if;
else
tpacc_load_cmb <= '1';
cycle_cnt_en_cmb <= '1';
if (Bus2IP_RdReq = '1') then
addr_cnt_ce_cmb <= '1';
end if;
end if;
else
tpacc_cnt_en_cmb <= '1';
if New_page_access = '1' then
new_page <= '1';
end if;
end if;
-------------------------------------------------------------------
-- WAIT_RDDATA_ACK STATE
-- Waits in this state till read data is received from memory.
-------------------------------------------------------------------
when WAIT_RDDATA_ACK =>
if read_complete = '1' then
next_state <= IDLE;
thz_load_cmb <= '1';
transaction_done_cmb <= '1';
end if;
addr_align_reg <= Addr_align;
new_page <= '0';
addr_cnt_rst_cmb <= '1';
read_data_en_cmb <= '0';
read_break_reg <= '0';
if (Bus2IP_Mem_CS_d2 = '1' and
Bus2IP_Mem_CS_d1 = '0') then
transaction_complete <= '1';
end if;
end case;
end process SM_COMB_PROCESS;
end generate NEW_LOGIC_GEN;
---------------------------------------------------------------------------
-- Read complete generation logic.
-- 2 pipe stages = read command delay from State machine to IO reg.
-- Delay require to get the data from memory.
-- 1 pipe stage = Data coming from memory is registered first in IO reg and
-- then goes to data steering logic.
-- 2 pipe stage = Async memory, 3 pipe stage = sync memory (PipeDelay=1),
-- 4 pipe stage = sync memory (PipeDelay=2).
---------------------------------------------------------------------------
read_complete <= read_complete_d(3) when Synch_mem = '0'
else
--read_complete_d(6) when (Synch_mem = '1' and --10-12-2012
-- Two_pipe_delay = '0')--10-12-2012
read_complete_d(4) when (Synch_mem = '1' and --10-12-2012
Two_pipe_delay = '0')--10-12-2012
else
read_complete_d(6); -- read_complete_d(7);
read_complete_d(0) <= read_complete_cmb or (stop_oen and synch_mem);
READ_COMPLETE_PIPE_GEN : for i in 0 to 6 generate
READ_COMPLETE_PIPE: FDR
port map (
Q => read_complete_d(i+1), --[out]
C => Clk, --[in]
D => read_complete_d(i), --[in]
R => Rst --[in]
);
end generate READ_COMPLETE_PIPE_GEN;
---------------------------------------------------------------------------
-- Register state_machine states.
---------------------------------------------------------------------------
REG_STATES_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
crnt_state <= IDLE;
else
crnt_state <= next_state;
end if;
end if;
end process REG_STATES_PROCESS;
REG_SIG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
wlast_reg <= '0';
wvalid_reg <= '0';
else
wlast_reg <= wlast;
wvalid_reg <= wvalid;
end if;
end if;
end process REG_SIG_PROCESS;
ADDR_ALLIGN_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
Addr_align_rd <= '0';
addr_align_rd_d1 <= '0';
new_page_d1 <= '0';
transaction_complete_reg <= '0';
read_break_reg_d1 <= '0';
else
new_page_d1 <= new_page;
addr_align_rd_d1 <= addr_align_reg;
Addr_align_rd <= addr_align_rd_d1;
transaction_complete_reg <= transaction_complete;
read_break_reg_d1 <= read_break_reg;
end if;
end if;
end process ADDR_ALLIGN_PROCESS ;
---------------------------------------------------------------------------
-- Register memory control signals.
---------------------------------------------------------------------------
MEM_SIGNALS_REG_PROCESS :process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if (Rst = '1') then
mem_cen_reg <='1';
mem_oen_reg <='1';
mem_wen_reg <='1';
else
mem_cen_reg <=mem_cen_cmb;
mem_oen_reg <=mem_oen_cmb;
mem_wen_reg <=mem_wen_cmb;
end if;
end if;
end process MEM_SIGNALS_REG_PROCESS;
---------------------------------------------------------------------------
-- Data strobe creation process. Used as strobe signal for Bus2Ip_Data and
-- Bus2IP_BE.
---------------------------------------------------------------------------
--DATA_STROBE_PROCESS :process(Clk)
-- begin
-- if(Clk'EVENT and Clk = '1')then
-- if (Rst = '1') then
-- -- Data_strobe <='0';
-- else
-- -- Data_strobe <= addressData_strobe_cmb;
-- end if;
-- end if;
-- end process DATA_STROBE_PROCESS;
--Data_strobe <= addressData_strobe_cmb;09-12-2012
Data_strobe <= '0';
address_strobe_c <= address_strobe_cmb;
be_strobe_c <= be_strobe_cmb ;
data_strobe_c <= data_strobe_cmb ;
---------------------------------------------------------------------------
-- Register Addr_cnt control signals.
---------------------------------------------------------------------------
ADDR_CNT_REG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
addr_cnt_ce_reg <= '0';
addr_cnt_rst_reg<= '0';
else
addr_cnt_ce_reg <= addr_cnt_ce_cmb;
addr_cnt_rst_reg<= addr_cnt_rst_cmb;
end if;
end if;
end process ADDR_CNT_REG_PROCESS;
---------------------------------------------------------------------------
-- Register cs_strobe_cmb signal.
---------------------------------------------------------------------------
CS_STROBE_REG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
cs_strobe_reg <= '0';
else
cs_strobe_reg <= cs_strobe_cmb;
end if;
end if;
end process CS_STROBE_REG_PROCESS;
---------------------------------------------------------------------------
-- Register read_data_en_cmb signal.
---------------------------------------------------------------------------
READ_DATA_EN_REG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
read_data_en_reg <= '0';
else
read_data_en_reg <= read_data_en_cmb;
end if;
end if;
end process READ_DATA_EN_REG_PROCESS;
---------------------------------------------------------------------------
-- Register Bus2IP_Mem_CS signal.
---------------------------------------------------------------------------
CS_REG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
Bus2IP_Mem_CS_d1 <= '0';
Bus2IP_Mem_CS_d2 <= '0';
Bus2IP_RdReq_d1 <= '0';
Bus2IP_RdReq_d2 <= '0';
else
Bus2IP_Mem_CS_d1 <= Bus2IP_Mem_CS;
Bus2IP_Mem_CS_d2 <= Bus2IP_Mem_CS_d1;
Bus2IP_RdReq_d1 <= Bus2IP_RdReq;
Bus2IP_RdReq_d2 <= Bus2IP_RdReq_d1;
end if;
end if;
end process CS_REG_PROCESS;
read_break <= (Bus2IP_RdReq_d1 and (not Bus2IP_RdReq));--(Bus2IP_RdReq_d2 and (not Bus2IP_RdReq_d1));
Load_address <= (Bus2IP_Mem_CS_d1 and (not Bus2IP_Mem_CS_d2));
---------------------------------------------------------------------------
-- Register transaction_done_cmb signal.
---------------------------------------------------------------------------
TRAN_DONE_REG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
transaction_done_reg <= '0';
else
transaction_done_reg <= transaction_done_cmb;
end if;
end if;
end process TRAN_DONE_REG_PROCESS;
---------------------------------------------------------------------------
-- Register read_ack_cmb signal.
---------------------------------------------------------------------------
READ_ACK_REG_PROCESS : process (Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
read_ack_reg <= '0';
else
read_ack_reg <= read_ack_cmb;
end if;
end if;
end process READ_ACK_REG_PROCESS;
LAST_ADDR_PROCESS : process (Clk) -- 09-12-2012 added to make sure that sync read doesnt generate extra read address ack
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
last_addr1_d1 <= '0';
last_addr1_d2 <= '0';
last_addr1_d3 <= '0';
else
last_addr1_d1 <= last_addr1;
last_addr1_d2 <= last_addr1_d1;
last_addr1_d3 <= last_addr1_d2;
end if;
end if;
end process LAST_ADDR_PROCESS;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File mem_state_machine.vhd
-------------------------------------------------------------------------------
| gpl-3.0 | 418490c3c8ce323d1c22f76c925220ac | 0.34292 | 4.399952 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_emc_0_0/synth/design_1_axi_emc_0_0.vhd | 2 | 25,551 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_emc:3.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_emc_v3_0;
USE axi_emc_v3_0.axi_emc;
ENTITY design_1_axi_emc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_axi_emc_0_0;
ARCHITECTURE design_1_axi_emc_0_0_arch OF design_1_axi_emc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_emc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_AXI_CLK_PERIOD_PS : INTEGER;
C_LFLASH_PERIOD_PS : INTEGER;
C_LINEAR_FLASH_SYNC_BURST : INTEGER;
C_S_AXI_REG_ADDR_WIDTH : INTEGER;
C_S_AXI_REG_DATA_WIDTH : INTEGER;
C_S_AXI_EN_REG : INTEGER;
C_S_AXI_MEM_ADDR_WIDTH : INTEGER;
C_S_AXI_MEM_DATA_WIDTH : INTEGER;
C_S_AXI_MEM_ID_WIDTH : INTEGER;
C_S_AXI_MEM0_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM0_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_HIGHADDR : STD_LOGIC_VECTOR;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_NUM_BANKS_MEM : INTEGER;
C_MEM0_TYPE : INTEGER;
C_MEM1_TYPE : INTEGER;
C_MEM2_TYPE : INTEGER;
C_MEM3_TYPE : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_PARITY_TYPE_MEM_0 : INTEGER;
C_PARITY_TYPE_MEM_1 : INTEGER;
C_PARITY_TYPE_MEM_2 : INTEGER;
C_PARITY_TYPE_MEM_3 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TWPH_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_WR_REC_TIME_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TWPH_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_WR_REC_TIME_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TWPH_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_WR_REC_TIME_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TWPH_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_WR_REC_TIME_MEM_3 : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_reg_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_awvalid : IN STD_LOGIC;
s_axi_reg_awready : OUT STD_LOGIC;
s_axi_reg_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_reg_wvalid : IN STD_LOGIC;
s_axi_reg_wready : OUT STD_LOGIC;
s_axi_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_bvalid : OUT STD_LOGIC;
s_axi_reg_bready : IN STD_LOGIC;
s_axi_reg_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_arvalid : IN STD_LOGIC;
s_axi_reg_arready : OUT STD_LOGIC;
s_axi_reg_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_rvalid : OUT STD_LOGIC;
s_axi_reg_rready : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_parity_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_emc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "axi_emc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_emc_0_0_arch : ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_emc,x_ipVersion=3.0,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_emc_inst,C_AXI_CLK_PERIOD_PS=10000,C_LFLASH_PERIOD_PS=10000,C_LINEAR_FLASH_SYNC_BURST=0,C_S_AXI_REG_ADDR_WIDTH=5,C_S_AXI_REG_DATA_WIDTH=32,C_S_AXI_EN_REG=0,C_S_AXI_MEM_ADDR_WIDTH=32,C_S_AXI_MEM_DATA_WIDTH=32,C_S_AXI_MEM_ID_WIDTH=1,C_S_AXI_MEM0_BASEADDR=0x60000000,C_S_AXI_MEM0_HIGHADDR=0x60FFFFFF,C_S_AXI_MEM1_BASEADDR=0xB0000000,C_S_AXI_MEM1_HIGHADDR=0xBFFFFFFF,C_S_AXI_MEM2_BASEADDR=0xC0000000,C_S_AXI_MEM2_HIGHADDR=0xCFFFFFFF,C_S_AXI_MEM3_BASEADDR=0xD0000000,C_S_AXI_MEM3_HIGHADDR=0xDFFFFFFF,C_INCLUDE_NEGEDGE_IOREGS=0,C_NUM_BANKS_MEM=1,C_MEM0_TYPE=1,C_MEM1_TYPE=0,C_MEM2_TYPE=0,C_MEM3_TYPE=0,C_MEM0_WIDTH=16,C_MEM1_WIDTH=16,C_MEM2_WIDTH=16,C_MEM3_WIDTH=16,C_MAX_MEM_WIDTH=16,C_PARITY_TYPE_MEM_0=0,C_PARITY_TYPE_MEM_1=0,C_PARITY_TYPE_MEM_2=0,C_PARITY_TYPE_MEM_3=0,C_INCLUDE_DATAWIDTH_MATCHING_0=1,C_INCLUDE_DATAWIDTH_MATCHING_1=1,C_INCLUDE_DATAWIDTH_MATCHING_2=1,C_INCLUDE_DATAWIDTH_MATCHING_3=1,C_SYNCH_PIPEDELAY_0=1,C_TCEDV_PS_MEM_0=70000,C_TAVDV_PS_MEM_0=70000,C_TPACC_PS_FLASH_0=70000,C_THZCE_PS_MEM_0=8000,C_THZOE_PS_MEM_0=8000,C_TWC_PS_MEM_0=85000,C_TWP_PS_MEM_0=55000,C_TWPH_PS_MEM_0=10000,C_TLZWE_PS_MEM_0=0,C_WR_REC_TIME_MEM_0=27000,C_SYNCH_PIPEDELAY_1=1,C_TCEDV_PS_MEM_1=15000,C_TAVDV_PS_MEM_1=15000,C_TPACC_PS_FLASH_1=25000,C_THZCE_PS_MEM_1=7000,C_THZOE_PS_MEM_1=7000,C_TWC_PS_MEM_1=15000,C_TWP_PS_MEM_1=12000,C_TWPH_PS_MEM_1=12000,C_TLZWE_PS_MEM_1=0,C_WR_REC_TIME_MEM_1=27000,C_SYNCH_PIPEDELAY_2=1,C_TCEDV_PS_MEM_2=15000,C_TAVDV_PS_MEM_2=15000,C_TPACC_PS_FLASH_2=25000,C_THZCE_PS_MEM_2=7000,C_THZOE_PS_MEM_2=7000,C_TWC_PS_MEM_2=15000,C_TWP_PS_MEM_2=12000,C_TWPH_PS_MEM_2=12000,C_TLZWE_PS_MEM_2=0,C_WR_REC_TIME_MEM_2=27000,C_SYNCH_PIPEDELAY_3=1,C_TCEDV_PS_MEM_3=15000,C_TAVDV_PS_MEM_3=15000,C_TPACC_PS_FLASH_3=25000,C_THZCE_PS_MEM_3=7000,C_THZOE_PS_MEM_3=7000,C_TWC_PS_MEM_3=15000,C_TWP_PS_MEM_3=12000,C_TWPH_PS_MEM_3=12000,C_TLZWE_PS_MEM_3=0,C_WR_REC_TIME_MEM_3=27000}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF rdclk: SIGNAL IS "xilinx.com:signal:clock:1.0 rdclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_i: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_I";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_o: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_O";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_t: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_T";
ATTRIBUTE X_INTERFACE_INFO OF mem_a: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF mem_ce: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE";
ATTRIBUTE X_INTERFACE_INFO OF mem_cen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE_N";
ATTRIBUTE X_INTERFACE_INFO OF mem_oen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF OEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_wen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_ben: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF BEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_qwen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF QWEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rpn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RPN";
ATTRIBUTE X_INTERFACE_INFO OF mem_adv_ldn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADV_LDN";
ATTRIBUTE X_INTERFACE_INFO OF mem_lbon: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF LBON";
ATTRIBUTE X_INTERFACE_INFO OF mem_cken: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CLKEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rnw: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF mem_cre: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CRE";
ATTRIBUTE X_INTERFACE_INFO OF mem_wait: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WAIT";
BEGIN
U0 : axi_emc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_emc_inst",
C_AXI_CLK_PERIOD_PS => 10000,
C_LFLASH_PERIOD_PS => 10000,
C_LINEAR_FLASH_SYNC_BURST => 0,
C_S_AXI_REG_ADDR_WIDTH => 5,
C_S_AXI_REG_DATA_WIDTH => 32,
C_S_AXI_EN_REG => 0,
C_S_AXI_MEM_ADDR_WIDTH => 32,
C_S_AXI_MEM_DATA_WIDTH => 32,
C_S_AXI_MEM_ID_WIDTH => 1,
C_S_AXI_MEM0_BASEADDR => X"60000000",
C_S_AXI_MEM0_HIGHADDR => X"60FFFFFF",
C_S_AXI_MEM1_BASEADDR => X"B0000000",
C_S_AXI_MEM1_HIGHADDR => X"BFFFFFFF",
C_S_AXI_MEM2_BASEADDR => X"C0000000",
C_S_AXI_MEM2_HIGHADDR => X"CFFFFFFF",
C_S_AXI_MEM3_BASEADDR => X"D0000000",
C_S_AXI_MEM3_HIGHADDR => X"DFFFFFFF",
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_NUM_BANKS_MEM => 1,
C_MEM0_TYPE => 1,
C_MEM1_TYPE => 0,
C_MEM2_TYPE => 0,
C_MEM3_TYPE => 0,
C_MEM0_WIDTH => 16,
C_MEM1_WIDTH => 16,
C_MEM2_WIDTH => 16,
C_MEM3_WIDTH => 16,
C_MAX_MEM_WIDTH => 16,
C_PARITY_TYPE_MEM_0 => 0,
C_PARITY_TYPE_MEM_1 => 0,
C_PARITY_TYPE_MEM_2 => 0,
C_PARITY_TYPE_MEM_3 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 1,
C_SYNCH_PIPEDELAY_0 => 1,
C_TCEDV_PS_MEM_0 => 70000,
C_TAVDV_PS_MEM_0 => 70000,
C_TPACC_PS_FLASH_0 => 70000,
C_THZCE_PS_MEM_0 => 8000,
C_THZOE_PS_MEM_0 => 8000,
C_TWC_PS_MEM_0 => 85000,
C_TWP_PS_MEM_0 => 55000,
C_TWPH_PS_MEM_0 => 10000,
C_TLZWE_PS_MEM_0 => 0,
C_WR_REC_TIME_MEM_0 => 27000,
C_SYNCH_PIPEDELAY_1 => 1,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TWPH_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_WR_REC_TIME_MEM_1 => 27000,
C_SYNCH_PIPEDELAY_2 => 1,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TWPH_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_WR_REC_TIME_MEM_2 => 27000,
C_SYNCH_PIPEDELAY_3 => 1,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TWPH_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_WR_REC_TIME_MEM_3 => 27000
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
rdclk => rdclk,
s_axi_reg_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_awvalid => '0',
s_axi_reg_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_reg_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_reg_wvalid => '0',
s_axi_reg_bready => '0',
s_axi_reg_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_arvalid => '0',
s_axi_reg_rready => '0',
s_axi_mem_awid => s_axi_mem_awid,
s_axi_mem_awaddr => s_axi_mem_awaddr,
s_axi_mem_awlen => s_axi_mem_awlen,
s_axi_mem_awsize => s_axi_mem_awsize,
s_axi_mem_awburst => s_axi_mem_awburst,
s_axi_mem_awlock => s_axi_mem_awlock,
s_axi_mem_awcache => s_axi_mem_awcache,
s_axi_mem_awprot => s_axi_mem_awprot,
s_axi_mem_awvalid => s_axi_mem_awvalid,
s_axi_mem_awready => s_axi_mem_awready,
s_axi_mem_wdata => s_axi_mem_wdata,
s_axi_mem_wstrb => s_axi_mem_wstrb,
s_axi_mem_wlast => s_axi_mem_wlast,
s_axi_mem_wvalid => s_axi_mem_wvalid,
s_axi_mem_wready => s_axi_mem_wready,
s_axi_mem_bid => s_axi_mem_bid,
s_axi_mem_bresp => s_axi_mem_bresp,
s_axi_mem_bvalid => s_axi_mem_bvalid,
s_axi_mem_bready => s_axi_mem_bready,
s_axi_mem_arid => s_axi_mem_arid,
s_axi_mem_araddr => s_axi_mem_araddr,
s_axi_mem_arlen => s_axi_mem_arlen,
s_axi_mem_arsize => s_axi_mem_arsize,
s_axi_mem_arburst => s_axi_mem_arburst,
s_axi_mem_arlock => s_axi_mem_arlock,
s_axi_mem_arcache => s_axi_mem_arcache,
s_axi_mem_arprot => s_axi_mem_arprot,
s_axi_mem_arvalid => s_axi_mem_arvalid,
s_axi_mem_arready => s_axi_mem_arready,
s_axi_mem_rid => s_axi_mem_rid,
s_axi_mem_rdata => s_axi_mem_rdata,
s_axi_mem_rresp => s_axi_mem_rresp,
s_axi_mem_rlast => s_axi_mem_rlast,
s_axi_mem_rvalid => s_axi_mem_rvalid,
s_axi_mem_rready => s_axi_mem_rready,
mem_dq_i => mem_dq_i,
mem_dq_o => mem_dq_o,
mem_dq_t => mem_dq_t,
mem_dq_parity_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
mem_a => mem_a,
mem_ce => mem_ce,
mem_cen => mem_cen,
mem_oen => mem_oen,
mem_wen => mem_wen,
mem_ben => mem_ben,
mem_qwen => mem_qwen,
mem_rpn => mem_rpn,
mem_adv_ldn => mem_adv_ldn,
mem_lbon => mem_lbon,
mem_cken => mem_cken,
mem_rnw => mem_rnw,
mem_cre => mem_cre,
mem_wait => mem_wait
);
END design_1_axi_emc_0_0_arch;
| gpl-3.0 | 511cbb5a0980f20247b7c5d10d3f1c20 | 0.658409 | 2.816468 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/mac_pkg.vhd | 4 | 24,101 | -------------------------------------------------------------------------------
-- mac_pkg - Package
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mac_pkg.vhd
-- Version : v2.0
-- Description : This file contains the constants used in the design of the
-- Ethernet MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mac_pkg is
type tx_state_name is
(idle,txEnCheck,loadByteCnt,checkByteCnt,checkByteCntOvrWrtSrcAdr,
requestFifoRd,requestFifoRdOvrWrtSrcAdr,waitFifoEmpty,decByteCnt,
decByteCntOvrWrtSrcAdr,checkBusFifoFull,checkBusFifoFullOvrWrtSrcAdr,
loadBusFifo,loadBusFifoOvrWrtSrcAdr,txDone,preamble,SFD,loadBusFifoSrcAdr,
loadBusFifoJam,checkBusFifoFullSrcAdr,loadBusFifoPad,checkBusFifoFullPad,
loadBusFifoCrc,checkBusFifoFullCrc,checkBusFifoFullJam,lateCollision,
excessDeferal,collisionRetry,cleanPacketCheckByteCnt,
cleanPacketRequestFifoRd,cleanPacketDecByteCnt,retryWaitFifoEmpty,
retryReset,tlrRead,checkBusFifoFullSFD,txDone2);
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant XEMAC_MAJOR_VERSION : std_logic_vector(0 to 3) := "0001"; -- 1
-- binary encoded major version number
constant XEMAC_MINOR_VERSION : std_logic_vector(0 to 6) := "0000000";-- 00
-- binary encoded minor version number
constant XEMAC_REVISION : std_logic_vector(0 to 4) := "00001";-- rev b
-- binary encoded revision letter. a = "00000" z = "11001"
constant XEMAC_BLOCK_TYPE : std_logic_vector(0 to 7) := "00000001";-- 1
-- value that indentifies this device as a 10/100 Ethernet IP
constant RESET_ACTIVE : std_logic := '1';
-- the RESET_ACTIVE constant should denote the
-- logic level of an active reset
constant MinimumPacketLength : std_logic_vector (0 to 15) := "0000000000111100";
-- 60 = 3c in hex
constant MAXENetPktLength : natural := 1500;
constant MINENetPktLength : natural := 46;
-------------------------------------------------------------------------------
-- these constants give data and address bus sizes for 3 widths of data
-- such that the largest ethernet frame will be addressable
-------------------------------------------------------------------------------
constant dbw4 : natural := 4;
constant abw4 : natural := 12;
constant dbw8 : natural := 8;
constant abw8 : natural := 11;
constant dbw16 : natural := 16;
constant abw16 : natural := 10;
constant CRCDataWidth : natural := 32; -- crc output data width
subtype UNSIGNED30BIT is std_logic_vector (0 to 29);
subtype UNSIGNED29BIT is std_logic_vector (0 to 28);
subtype UNSIGNED27BIT is std_logic_vector (0 to 26);
subtype UNSIGNED24BIT is std_logic_vector (0 to 23);
subtype UNSIGNED23BIT is std_logic_vector (0 to 22);
subtype UNSIGNED22BIT is std_logic_vector (0 to 21);
subtype UNSIGNED21BIT is std_logic_vector (0 to 20);
subtype UNSIGNED20BIT is std_logic_vector (0 to 19);
subtype UNSIGNED18BIT is std_logic_vector (0 to 17);
subtype UNSIGNED16BIT is std_logic_vector (0 to 15);
subtype UNSIGNED12BIT is std_logic_vector (0 to 11);
subtype UNSIGNED11BIT is std_logic_vector (0 to 10);
subtype UNSIGNED10BIT is std_logic_vector (0 to 9);
subtype UNSIGNED9BIT is std_logic_vector (0 to 8);
subtype UNSIGNED8BIT is std_logic_vector (0 to 7);
subtype UNSIGNED6BIT is std_logic_vector (0 to 5);
subtype ENetAddr is std_logic_vector (47 downto 0); -- ethernet address
subtype IPAddress is std_logic_vector(31 downto 0);
subtype TwoBit is std_logic_vector (1 downto 0); -- half a Nibble
subtype Nibble is std_logic_vector (3 downto 0); -- half a byte
subtype Byte is std_logic_vector (7 downto 0); -- single byte
subtype Monk is std_logic_vector (8 downto 0); -- monkey (500, for 512)
subtype Deck is std_logic_vector (9 downto 0); -- a 10 digit binary number
subtype Word is std_logic_vector (15 downto 0); -- double byte
subtype DWord is std_logic_vector (31 downto 0); -- quadruple byte
subtype CRCData is std_logic_vector(CRCDataWidth - 1 downto 0);
-------------------------------------------------------------------------------
-- these standard types are used for the address bus declarations
-------------------------------------------------------------------------------
subtype NibbleAddress is std_logic_vector(abw4 - 1 downto 0);
subtype ByteAddress is std_logic_vector(abw8 - 1 downto 0);
subtype WordAddress is std_logic_vector(abw16 - 1 downto 0);
function getENetAddr (eaddr : string) return ENetAddr;
function revBitOrder (arg : std_logic_vector) return std_logic_vector;
function convENetAddr(arg : ENetAddr) return bit_vector;
-- By ben 06/28/2000
function revNibOrder(arg : std_logic_vector) return std_logic_vector;
-- by ben 07/04/2000
function getIPAddr (ipaddr : string) return IPAddress;
function allZeroes (inp : std_logic_vector) return boolean;
function allOnes (inp : std_logic_vector) return boolean;
function zExtend (arg1 : std_logic_vector; size : natural)
return std_logic_vector;
function maxNat (arg1, arg2 : natural) return natural;
function netOrder (arg : Word) return Word; --by Ying
function netOrder (arg : bit_vector(15 downto 0)) return bit_vector;
function GetInitString4 ( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return string;
function GetInitVector4 ( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return bit_vector;
function to_string (bv : bit_vector) return string;
function to_string (b : bit) return string;
function to_character (bv : bit_vector(3 downto 0)) return character;
end mac_pkg;
package body mac_pkg is
-- coverage off
-- Convert 4-bit vector to a character
function to_character (
bv : bit_vector(3 downto 0))
return character is
begin -- to_character
case bv is
when b"0000" => return '0';
when b"0001" => return '1';
when b"0010" => return '2';
when b"0011" => return '3';
when b"0100" => return '4';
when b"0101" => return '5';
when b"0110" => return '6';
when b"0111" => return '7';
when b"1000" => return '8';
when b"1001" => return '9';
when b"1010" => return 'a';
when b"1011" => return 'b';
when b"1100" => return 'c';
when b"1101" => return 'd';
when b"1110" => return 'e';
when b"1111" => return 'f';
end case;
end to_character;
-- Convert n-bits vector to n/4-character string
function to_string (bv : bit_vector) return string is
constant strlen : integer := bv'length / 4;
variable str : string(1 to strlen);
begin -- to_string
for i in 0 to strlen - 1 loop
str(strlen-i) := to_character(bv((i * 4) + 3 downto (i * 4)));
end loop; -- i
return str;
end to_string;
-- Convert 1-bit to 1-character string
function to_string (b : bit) return string is
begin
case b is
when '0' => return "0";
when '1' => return "1";
when others => assert false report "unrecognised bit value" severity failure;
end case;
return "0";
end to_string;
function netOrder (arg : bit_vector(15 downto 0))
return bit_vector is
variable res : bit_vector(15 downto 0);
begin -- netOrder
res(15 downto 12) := arg(11 downto 8);
res(11 downto 8) := arg(15 downto 12);
res(7 downto 4) := arg(3 downto 0);
res(3 downto 0) := arg(7 downto 4);
return res;
end netOrder;
-- Generate the label string for LUT ROM 16x4 from the init strings
function GetInitString4 ( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return string is
variable bitvalue : bit_vector(15 downto 0) ;
begin
bitvalue(0) := INIT_00(idx+12); bitvalue(1) := INIT_00(idx+8);
bitvalue(2) := INIT_00(idx+4); bitvalue(3) := INIT_00(idx);
bitvalue(4) := INIT_01(idx+12); bitvalue(5) := INIT_01(idx+8);
bitvalue(6) := INIT_01(idx+4); bitvalue(7) := INIT_01(idx);
bitvalue(8) := INIT_02(idx+12); bitvalue(9) := INIT_02(idx+8);
bitvalue(10) := INIT_02(idx+4); bitvalue(11) := INIT_02(idx);
bitvalue(12) := INIT_03(idx+12); bitvalue(13) := INIT_03(idx+8);
bitvalue(14) := INIT_03(idx+4); bitvalue(15) := INIT_03(idx);
return to_string(bitvalue);
end function GetInitString4;
-- Generate the generic init vector for the LUT ROM 16x4 from the
-- init strings
function GetInitVector4( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return bit_vector is
variable bitvalue : bit_vector(15 downto 0) ;
begin
bitvalue(0) := INIT_00(idx+12); bitvalue(1) := INIT_00(idx+8);
bitvalue(2) := INIT_00(idx+4); bitvalue(3) := INIT_00(idx);
bitvalue(4) := INIT_01(idx+12); bitvalue(5) := INIT_01(idx+8);
bitvalue(6) := INIT_01(idx+4); bitvalue(7) := INIT_01(idx);
bitvalue(8) := INIT_02(idx+12); bitvalue(9) := INIT_02(idx+8);
bitvalue(10) := INIT_02(idx+4); bitvalue(11) := INIT_02(idx);
bitvalue(12) := INIT_03(idx+12); bitvalue(13) := INIT_03(idx+8);
bitvalue(14) := INIT_03(idx+4); bitvalue(15) := INIT_03(idx);
return bitvalue;
end function GetInitVector4;
function conv_std_logic_vector (ch : character) return std_logic_vector is
begin
case ch is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' => return "1010";
when 'b' => return "1011";
when 'c' => return "1100";
when 'd' => return "1101";
when 'e' => return "1110";
when 'f' => return "1111";
when others => assert false report "unrecognised character"
severity failure;
end case;
return "0000";
end conv_std_logic_vector;
function getENetAddr (eaddr : string) return ENetAddr is
variable tmp : ENetAddr := (others => '0');
variable bptr : natural := 0;
variable nptr : natural := 0;
variable indx : natural := 0;
begin -- getENetAddr
tmp := (others => '0');
bptr := 0;
nptr := 0;
indx := 0;
if eaddr'length = 17 then
lp0 : for i in eaddr'reverse_range loop
-- lsbyte first
if eaddr(i) = ':' then
bptr := bptr + 1;
nptr := 0;
else
indx := (bptr * 8) + (nptr * 4);
tmp(indx + 3 downto indx) := conv_std_logic_vector(eaddr(i));
nptr := nptr + 1;
end if;
end loop lp0;
else
assert false report "ethernet address format is 01 : 23 : 45 : 67 : 89 : ab msb- > lsb" severity failure;
end if;
return tmp;
end getENetAddr;
-------------------------------------------------------------------------------
-- A function which can change the order of ENetAddr to
-- the order of smallrom init -- BY ben 06/28
-------------------------------------------------------------------------------
function convENetAddr(arg: ENetAddr) return bit_vector is
variable tmp : std_logic_vector(63 downto 0) :=(others => '0');
begin
lp0: for i in 0 to 11 loop
tmp(59-i) := arg(3 + i*4);
tmp(43 -i) := arg(2 + i*4);
tmp(27 -i) := arg(1 + i*4);
tmp(11 -i) := arg(i*4);
end loop lp0;
return to_bitvector(tmp);
end convENetAddr;
-------------------------------------------------------------------------------
-- A function which can reverse the bit order
-- order -- BY ben 07/04
-------------------------------------------------------------------------------
function revBitOrder( arg : std_logic_vector) return std_logic_vector is -- By ben 07/04/2000
variable tmp : std_logic_vector(arg'range);
begin
lp0 : for i in arg'range loop
tmp(arg'high - i) := arg(i);
end loop lp0;
return tmp;
end revBitOrder;
-------------------------------------------------------------------------------
-- A function which can swap the Nibble order
-- order -- BY ben 07/04
-------------------------------------------------------------------------------
function swapNibbles (
arg : std_logic_vector)
return std_logic_vector is
variable tmp : std_logic_vector(arg'length -1 downto 0);
variable j : integer;
begin -- swapNibbles
for i in 0 to (arg'length / 8) - 1 loop
j := i * 8;
tmp(j + 3 downto j) := arg(j + 7 downto j + 4);
tmp(j + 7 downto j + 4) := arg(j + 3 downto j);
end loop; -- i
return tmp;
end swapNibbles;
-------------------------------------------------------------------------------
-- A function which can reverse the Nibble order
-- order -- BY ben 07/04
-------------------------------------------------------------------------------
function revNibOrder( arg : std_logic_vector) return std_logic_vector is -- By ben 07/04/2000
variable tmp : std_logic_vector(arg'high downto 0); -- length is numNubs
variable numNibs : integer;
begin
numNibs := arg'length/4;
lp0: for i in 0 to numNibs -1 loop
tmp( (4*(numNibs-i)-1) downto 4*(numNibs-i-1) ) := arg( (4*i+3) downto 4*i);
end loop lp0;
return tmp ;
end revNibOrder;
-------------------------------------------------------------------------------
-- Afunction to parse IP address
-------------------------------------------------------------------------------
function getIPAddr (ipaddr : string) return IPAddress is
variable tmp : IPAddress := (others => '0');
variable bptr : natural := 3;
variable nptr : natural := 2;
variable indx : natural := 0;
begin
bptr := 3;
nptr := 2;
indx := 0;
-- similar to above, take a fixed length string and parse it for
-- expected characters. We anticipate hex numbers if the format,
-- hh.hh.hh.hh
if ipaddr'length = 11 then
for i in ipaddr'range loop
if ipaddr(i) = '.' then
bptr := bptr - 1;
nptr := 2;
else
indx := (bptr * 8) + ((nptr - 1) * 4);
tmp(indx + 3 downto indx) := conv_std_logic_vector(ipaddr(i));
nptr := nptr - 1;
end if;
end loop; -- i
else
assert false report "IP address format is 01.23.45.67 msb- > lsb" severity failure;
end if;
return tmp;
end getIPAddr;
-------------------------------------------------------------------------------
-- couple of useful functions, move them to utils eventually
-------------------------------------------------------------------------------
function allZeroes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '1' then
t := false;
end if;
end loop;
return t;
end allZeroes;
function allOnes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '0' then
t := false;
end if;
end loop;
return t;
end allOnes;
-------------------------------------------------------------------------------
-- returns the maximum of two naturals
-------------------------------------------------------------------------------
function maxNat (arg1, arg2 : natural)
return natural is
begin -- maxNat
if arg1 >= arg2 then
return arg1;
else
return arg2;
end if;
end maxNat;
-------------------------------------------------------------------------------
-- zero extend a std_logic_vector
-------------------------------------------------------------------------------
function zExtend (
arg1 : std_logic_vector;
size : natural)
return std_logic_vector is
variable result : std_logic_vector(size - 1 downto 0);
begin -- extend
result := (others => '0');
result(arg1'length - 1 downto 0) := arg1;
return result;
end zExtend;
-------------------------------------------------------------------------------
-- Switch the word order between Correct-Word-Order and Net-Word-Order.
-- If arg is (Hex)1234,
-- then netOrder(arg) is (Hex)2143.
-------------------------------------------------------------------------------
function netOrder (arg : Word)
return Word is
begin -- netOrder
return arg(11 downto 8) & arg(15 downto 12) &
arg(3 downto 0) & arg(7 downto 4);
end netOrder;
-- coverage on
end mac_pkg; | gpl-3.0 | 837c3f0600478df9c899c9a1a88dee7a | 0.486868 | 4.325377 | false | false | false | false |
hoangt/PoC | src/misc/misc_FrequencyMeasurement.vhdl | 2 | 5,228 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: measures a input frequency relativ to a reference frequency
--
-- Description:
-- ------------------------------------
-- This module counts 1 second in a reference timer at reference clock. This
-- reference time is used to start and stop a timer at input clock. The counter
-- value is the measured frequency in Hz.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
entity misc_FrequencyMeasurement is
generic (
REFERENCE_CLOCK_FREQ : FREQ := 100 MHz
);
port (
Reference_Clock : in STD_LOGIC;
Input_Clock : in STD_LOGIC;
Start : in STD_LOGIC;
Done : out STD_LOGIC;
Result : out T_SLV_32
);
end entity;
architecture rtl of misc_FrequencyMeasurement is
constant TIMEBASE_COUNTER_MAX : POSITIVE := TimingToCycles(ite(SIMULATION, 10 us, 1 sec), REFERENCE_CLOCK_FREQ);
constant TIMEBASE_COUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASE_COUNTER_MAX);
signal TimeBase_Counter_rst : STD_LOGIC;
signal TimeBase_Counter_s : SIGNED(TIMEBASE_COUNTER_BITS downto 0) := to_signed(-1, TIMEBASE_COUNTER_BITS + 1);
signal TimeBase_Counter_nxt : SIGNED(TIMEBASE_COUNTER_BITS downto 0);
signal TimeBase_Counter_uf : STD_LOGIC;
signal Stop : STD_LOGIC;
signal sync_Start : STD_LOGIC;
signal sync_Stop : STD_LOGIC;
signal sync1_Busy : T_SLV_2;
signal Frequency_Counter_en_r : STD_LOGIC := '0';
signal Frequency_Counter_us : UNSIGNED(31 downto 0) := (others => '0');
signal CaptureResult : STD_LOGIC;
signal CaptureResult_d : STD_LOGIC := '0';
signal Result_en : STD_LOGIC;
signal Result_d : T_SLV_32 := (others => '0');
signal Done_r : STD_LOGIC := '0';
begin
TimeBase_Counter_rst <= Start;
TimeBase_Counter_nxt <= TimeBase_Counter_s - 1;
process(Reference_Clock)
begin
if rising_edge(Reference_Clock) then
if (TimeBase_Counter_rst = '1') then
TimeBase_Counter_s <= to_signed(TIMEBASE_COUNTER_MAX - 2, TimeBase_Counter_s'length);
elsif (TimeBase_Counter_uf = '0') then
TimeBase_Counter_s <= TimeBase_Counter_nxt;
end if;
end if;
end process;
TimeBase_Counter_uf <= TimeBase_Counter_s(TimeBase_Counter_s'high);
Stop <= not TimeBase_Counter_s(TimeBase_Counter_s'high) and TimeBase_Counter_nxt(TimeBase_Counter_nxt'high);
sync1 : entity poc.sync_Strobe
generic map (
BITS => 2 -- number of bit to be synchronized
)
port map (
Clock1 => Reference_Clock, -- <Clock> input clock
Clock2 => Input_Clock, -- <Clock> output clock
Input(0) => Start, -- @Clock1 input vector
Input(1) => Stop, --
Output(0) => sync_Start, -- @Clock2: output vector
Output(1) => sync_Stop, --
Busy => sync1_Busy
);
Frequency_Counter_en_r <= ffrs(q => Frequency_Counter_en_r, set => sync_Start, rst => sync_Stop) when rising_edge(Input_Clock);
process(Input_Clock)
begin
if rising_edge(Input_Clock) then
if (sync_Start = '1') then
Frequency_Counter_us <= to_unsigned(1, Frequency_Counter_us'length);
elsif (Frequency_Counter_en_r = '1') then
Frequency_Counter_us <= Frequency_Counter_us + 1;
end if;
end if;
end process;
CaptureResult <= sync1_Busy(1);
CaptureResult_d <= CaptureResult when rising_edge(Reference_Clock);
Result_en <= CaptureResult_d and not CaptureResult;
-- Result_d can becaptured from Frequency_Counter_us, because it's stable
-- for more than one clock cycle and will not change until the next Start
process(Reference_Clock)
begin
if rising_edge(Reference_Clock) then
if (Result_en = '1') then
Result_d <= std_logic_vector(Frequency_Counter_us);
Done_r <= '1';
elsif (Start = '1') then
Done_r <= '0';
end if;
end if;
end process;
Done <= Done_r;
Result <= Result_d;
end;
| apache-2.0 | 3577338525d335dee7e21f1455eab088 | 0.618018 | 3.321474 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/bufg/iobuf_tech.vhd | 2 | 1,642 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual IO buffer.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity iobuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end;
architecture rtl of iobuf_tech is
component iobuf_inferred is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
component iobuf_virtex6 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
component iobuf_micron180 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
begin
inf0 : if generic_tech = inferred generate
bufinf : iobuf_inferred port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
xv6 : if generic_tech = virtex6 or generic_tech = kintex7 or generic_tech = artix7 generate
bufv6 : iobuf_virtex6 port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
m180 : if generic_tech = micron180 generate
bufm : iobuf_micron180 port map
(
o => o,
io => io,
i => i,
t => t
);
end generate;
end;
| bsd-2-clause | ae35c7e57153e7c3bca6ab89310651bf | 0.510962 | 3.569565 | false | false | false | false |
hoangt/PoC | src/io/ddrio/ddrio_inout_xilinx.vhdl | 2 | 3,421 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Input/Output Registers for Xilinx FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.inout for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library UniSim;
use UniSim.vComponents.all;
entity ddrio_inout_xilinx is
generic (
NO_OUTPUT_ENABLE : BOOLEAN := false;
BITS : POSITIVE;
INIT_VALUE_OUT : BIT_VECTOR := "1";
INIT_VALUE_IN_HIGH : BIT_VECTOR := "1";
INIT_VALUE_IN_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_inout_xilinx is
begin
gen : for i in 0 to WIDTH - 1 generate
signal o : std_logic;
begin
off : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => INIT_VALUE_OUT(i),
SRTYPE => "SYNC"
)
port map (
Q => o,
C => Clock,
CE => ClockEnable,
D1 => DataOut_high(i),
D2 => DataOut_low(i),
R => '0',
S => '0'
);
iff : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT_Q1 => INIT_VALUE_IN_HIGH(i),
INIT_Q2 => INIT_VALUE_IN_LOW(i),
SRTYPE => "SYNC"
)
port map (
C => Clock,
CE => ClockEnable,
D => i,
Q1 => DataIn_high(i),
Q2 => DataIn_low(i),
R => '0',
S => '0'
);
genOE : if not NO_OE generate
signal oe_n : std_logic;
signal t : std_logic;
begin
oe_n <= not OutputEnable;
tff : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '1',
SRTYPE => "SYNC"
)
port map (
Q => t,
C => Clock,
CE => ClockEnable,
D1 => oe_n,
D2 => oe_n,
R => '0',
S => '0'
);
Pad(i) <= o when t = '0' else 'Z'; -- 't' is low-active!
end generate genOE;
genNoOE : if NO_OE generate
Pad(i) <= o;
end generate genNoOE;
end generate;
end architecture;
| apache-2.0 | 9e945cf7d88d694b38bf61ef2f21678e | 0.550424 | 3.054464 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/counters.vhd | 4 | 18,094 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: counters.vhd
-- Description: This file contains the counters for timing read/write
-- timing parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. Added TPACC counter
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Inputs
-- Synch_mem -- Synchronous Memory Flag
-- Twr_data -- Write cycle counter data
-- Twr_load -- Write cycle counter load
-- Twr_cnt_en -- Write cycle count enable
-- Tlz_data -- Write End to Low-Z counter data
-- Tlz_load -- Write End to Low-Z counter load
-- Trd_data -- Read cycle counter data
-- Trd_load -- Read cycle counter load
-- Trd_cnt_en -- Read cycle count enable
-- Thz_data -- Read End to High-Z counter data
-- Thz_load -- Read End to High-Z counter load
--
-- Outputs
-- Twr_end -- Write cycle count complete
-- Tlz_end -- Write Recover count complete
-- Trd_end -- Read cycle count complete
-- Thz_end -- Read Recover count complete
--
-- Clock and reset
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity counters is
port (
Synch_mem : in std_logic;
Twr_data : in std_logic_vector(0 to 4);
Twr_load : in std_logic;
Twr_cnt_en : in std_logic;
Twph_data : in std_logic_vector(0 to 4);
Twph_load : in std_logic;
Twph_cnt_en : in std_logic;
Tlz_data : in std_logic_vector(0 to 4);
Tlz_load : in std_logic;
Trd_data : in std_logic_vector(0 to 4);
Trd_load : in std_logic;
Trd_cnt_en : in std_logic;
Thz_data : in std_logic_vector(0 to 4);
Thz_load : in std_logic;
Tpacc_data : in std_logic_vector(0 to 4);
Tpacc_load : in std_logic;
Tpacc_cnt_en : in std_logic;
Twr_end : out std_logic;
Tlz_end : out std_logic;
Twph_end : out std_logic;
Trd_end : out std_logic;
Thz_end : out std_logic;
Tpacc_end : out std_logic;
--
Twr_rec_data : in std_logic_vector(0 to 15);
Twr_rec_load : in std_logic;
Twr_rec_cnt_en : in std_logic;
Twr_rec_end : out std_logic;
--
Clk : in std_logic;
Rst : in std_logic
);
end entity counters;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of counters is
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assigning zero values
-------------------------------------------------------------------------------
constant ZERO_TWRCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TWPHCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TLZCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TRDCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TPACCCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_THZCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TWR_REC_CNT : std_logic_vector(0 to 9) := (others => '0');
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal twr_cnt : std_logic_vector(0 to 4);
signal twph_cnt : std_logic_vector(0 to 4);
signal tlz_cnt : std_logic_vector(0 to 4);
signal trd_cnt : std_logic_vector(0 to 4);
signal thz_cnt : std_logic_vector(0 to 4);
signal tpacc_cnt : std_logic_vector(0 to 4);
signal twr_rec_cnt : std_logic_vector(0 to 15);--9/6/2011
signal thz_cnt_en : std_logic;
signal tlz_cnt_en : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Write Cycle Delay Counter
-------------------------------------------------------------------------------
TWRCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twr_cnt,
LD => Twr_data,
AD => "1",
LOAD => Twr_load,
OP => Twr_cnt_en
);
-------------------------------------------------------------------------------
-- Write Cycle High Time Counter
-------------------------------------------------------------------------------
TWPHCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_TWPHCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twph_cnt,
LD => Twph_data,
AD => "1",
LOAD => Twph_load,
OP => Twph_cnt_en
);
-------------------------------------------------------------------------------
-- Write End to Data Low Impedance Counter
-------------------------------------------------------------------------------
tlz_cnt_en <= '0' when tlz_cnt = ZERO_TLZCNT
else '1';
TLZCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_TLZCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => tlz_cnt,
LD => Tlz_data,
AD => "1",
LOAD => Tlz_load,
OP => tlz_cnt_en
);
-------------------------------------------------------------------------------
-- Read Cycle Delay Counter
-------------------------------------------------------------------------------
TRDCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => trd_cnt,
LD => Trd_data,
AD => "1",
LOAD => Trd_load,
OP => Trd_cnt_en
);
-------------------------------------------------------------------------------
-- Page Read Cycle Delay Counter
-------------------------------------------------------------------------------
TPACCCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => tpacc_cnt,
LD => Tpacc_data,
AD => "1",
LOAD => Tpacc_load,
OP => Tpacc_cnt_en
);
-------------------------------------------------------------------------------
-- Page Read Cycle Delay Counter
-------------------------------------------------------------------------------
T_WRREC_CNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 16,
C_RESET_VALUE => "1111111111111111",
C_LD_WIDTH => 16,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twr_rec_cnt,
LD => Twr_rec_data,
AD => "1",
LOAD => Twr_rec_load,
OP => Twr_rec_cnt_en
);
-------------------------------------------------------------------------------
-- Read End to High Impedance Delay Counter
-------------------------------------------------------------------------------
thz_cnt_en <= '0' when thz_cnt = ZERO_THZCNT else
'1';
THZCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_THZCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => thz_cnt,
LD => Thz_data,
AD => "1",
LOAD => Thz_load,
OP => thz_cnt_en
);
-------------------------------------------------------------------------------
-- Generation of Counter End Signals
-------------------------------------------------------------------------------
Twr_end <= '1' when twr_cnt = ZERO_TWRCNT or Synch_mem = '1' else
'0' ;
Twph_end <= '1' when twph_cnt = ZERO_TWPHCNT or Synch_mem = '1' else
'0' ;
Tlz_end <= '1' when tlz_cnt = ZERO_TLZCNT or Synch_mem = '1' else
'0' ;
Trd_end <= '1' when trd_cnt = ZERO_TRDCNT or Synch_mem = '1' else
'0' ;
thz_end <= '1' when thz_cnt = ZERO_THZCNT or Synch_mem = '1' else
'0' ;
Tpacc_end <= '1' when tpacc_cnt = ZERO_TPACCCNT or Synch_mem = '1' else
'0' ;
Twr_rec_end <= '1' when twr_rec_cnt = ZERO_TWR_REC_CNT or Synch_mem = '1' else
'0' ; -- 9/6/2011
end imp;
-------------------------------------------------------------------------------
-- End of File counters.vhd
-------------------------------------------------------------------------------
| gpl-3.0 | 5fd89bc09bfe55ea0c61be8009c7b9a4 | 0.387034 | 4.745345 | false | false | false | false |
hoangt/PoC | src/bus/stream/stream_FrameGenerator.vhdl | 2 | 8,765 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FIFO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.arith_prng;
entity Stream_FrameGenerator is
generic (
DATA_BITS : POSITIVE := 8;
WORD_BITS : POSITIVE := 16;
APPend : T_FRAMEGEN_APPend := FRAMEGEN_APP_NONE;
FRAMEGROUPS : T_FRAMEGEN_FRAMEGROUP_VECTOR_8 := (0 => C_FRAMEGEN_FRAMEGROUP_EMPTY)
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- CSE interface
Command : in T_FRAMEGEN_COMMAND;
Status : out T_FRAMEGEN_STATUS;
-- Control interface
Pause : in T_SLV_16;
FrameGroupIndex : in T_SLV_8;
FrameIndex : in T_SLV_8;
Sequences : in T_SLV_16;
FrameLength : in T_SLV_16;
-- OUT Port
Out_Valid : out STD_LOGIC;
Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC;
Out_EOF : out STD_LOGIC;
Out_Ack : in STD_LOGIC
);
end;
architecture rtl of Stream_FrameGenerator is
type T_STATE is (
ST_IDLE,
ST_SEQUENCE_SOF, ST_SEQUENCE_DATA, ST_SEQUENCE_EOF,
ST_RANDOM_SOF, ST_RANDOM_DATA, ST_RANDOM_EOF,
ST_ERROR
);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal FrameLengthCounter_rst : STD_LOGIC;
signal FrameLengthCounter_en : STD_LOGIC;
signal FrameLengthCounter_us : UNSIGNED(15 downto 0) := (others => '0');
signal SequencesCounter_rst : STD_LOGIC;
signal SequencesCounter_en : STD_LOGIC;
signal SequencesCounter_us : UNSIGNED(15 downto 0) := (others => '0');
signal ContentCounter_rst : STD_LOGIC;
signal ContentCounter_en : STD_LOGIC;
signal ContentCounter_us : UNSIGNED(WORD_BITS - 1 downto 0) := (others => '0');
signal PRNG_rst : STD_LOGIC;
signal PRNG_got : STD_LOGIC;
signal PRNG_Data : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, Command, Out_Ack,
Sequences, FrameLength,
FrameLengthCounter_us,
SequencesCounter_us, ContentCounter_us,
PRNG_Data)
begin
NextState <= State;
Status <= FRAMEGEN_STATUS_GENERATING;
Out_Valid <= '0';
Out_Data <= (others => '0');
Out_SOF <= '0';
Out_EOF <= '0';
FrameLengthCounter_rst <= '0';
FrameLengthCounter_en <= '0';
SequencesCounter_rst <= '0';
SequencesCounter_en <= '0';
ContentCounter_rst <= '0';
ContentCounter_en <= '0';
PRNG_rst <= '0';
PRNG_got <= '0';
case State is
when ST_IDLE =>
Status <= FRAMEGEN_STATUS_IDLE;
FrameLengthCounter_rst <= '1';
SequencesCounter_rst <= '1';
ContentCounter_rst <= '1';
PRNG_rst <= '1';
case Command is
when FRAMEGEN_CMD_NONE =>
NULL;
when FRAMEGEN_CMD_SEQUENCE =>
NextState <= ST_SEQUENCE_SOF;
when FRAMEGEN_CMD_RANDOM =>
NextState <= ST_RANDOM_SOF;
when FRAMEGEN_CMD_SINGLE_FRAME =>
NextState <= ST_ERROR;
when FRAMEGEN_CMD_SINGLE_FRAMEGROUP =>
NextState <= ST_ERROR;
when FRAMEGEN_CMD_ALL_FRAMES =>
NextState <= ST_ERROR;
when others =>
NextState <= ST_ERROR;
end case;
-- generate sequential numbers
-- ----------------------------------------------------------------------
when ST_SEQUENCE_SOF =>
Out_Valid <= '1';
Out_Data <= std_logic_vector(ContentCounter_us);
Out_SOF <= '1';
if (Out_Ack = '1') then
FrameLengthCounter_en <= '1';
ContentCounter_en <= '1';
NextState <= ST_SEQUENCE_DATA;
end if;
when ST_SEQUENCE_DATA =>
Out_Valid <= '1';
Out_Data <= std_logic_vector(ContentCounter_us);
if (Out_Ack = '1') then
FrameLengthCounter_en <= '1';
ContentCounter_en <= '1';
if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then
NextState <= ST_SEQUENCE_EOF;
end if;
end if;
when ST_SEQUENCE_EOF =>
Out_Valid <= '1';
Out_Data <= std_logic_vector(ContentCounter_us);
Out_EOF <= '1';
if (Out_Ack = '1') then
FrameLengthCounter_rst <= '1';
ContentCounter_en <= '1';
SequencesCounter_en <= '1';
-- if (Pause = (Pause'range => '0')) then
if (SequencesCounter_us = (unsigned(Sequences) - 1)) then
Status <= FRAMEGEN_STATUS_COMPLETE;
NextState <= ST_IDLE;
else
NextState <= ST_SEQUENCE_SOF;
end if;
-- end if;
end if;
-- generate random numbers
-- ----------------------------------------------------------------------
when ST_RANDOM_SOF =>
Out_Valid <= '1';
Out_Data <= PRNG_Data;
Out_SOF <= '1';
if (Out_Ack = '1') then
FrameLengthCounter_en <= '1';
PRNG_got <= '1';
NextState <= ST_RANDOM_DATA;
end if;
when ST_RANDOM_DATA =>
Out_Valid <= '1';
Out_Data <= PRNG_Data;
if (Out_Ack = '1') then
FrameLengthCounter_en <= '1';
PRNG_got <= '1';
if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then
NextState <= ST_RANDOM_EOF;
end if;
end if;
when ST_RANDOM_EOF =>
Out_Valid <= '1';
Out_Data <= PRNG_Data;
Out_EOF <= '1';
FrameLengthCounter_rst <= '1';
if (Out_Ack = '1') then
PRNG_rst <= '1';
NextState <= ST_IDLE;
end if;
when ST_ERROR =>
Status <= FRAMEGEN_STATUS_ERROR;
NextState <= ST_IDLE;
end case;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or FrameLengthCounter_rst) = '1') then
FrameLengthCounter_us <= (others => '0');
else
if (FrameLengthCounter_en = '1') then
FrameLengthCounter_us <= FrameLengthCounter_us + 1;
end if;
end if;
end if;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or SequencesCounter_rst) = '1') then
SequencesCounter_us <= (others => '0');
else
if (SequencesCounter_en = '1') then
SequencesCounter_us <= SequencesCounter_us + 1;
end if;
end if;
end if;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or ContentCounter_rst) = '1') then
ContentCounter_us <= (others => '0');
else
if (ContentCounter_en = '1') then
ContentCounter_us <= ContentCounter_us + 1;
end if;
end if;
end if;
end process;
PRNG : entity Poc.alu_prng
generic map (
BITS => DATA_BITS
)
port map (
clk => Clock,
rst => PRNG_rst,
got => PRNG_got,
val => PRNG_Data
);
end;
| apache-2.0 | 2f1a96c22071ffe378acdcabf4bf7ef7 | 0.532002 | 3.331433 | false | false | false | false |
s-kostyuk/vhdl_samples | cnt_jk_8/cnt_0_to_7_full_struct.vhd | 1 | 3,276 | library IEEE;
use ieee.std_logic_1164.all;
entity cnt_0_to_7 is
port (
R, C : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end entity;
-- Суммирующий синхронный счетчик на JK-триггерах
-- с коэффициентом пересчета 8.
-- Модель, описанная полностью в структурном стиле
architecture cnt_0_to_7_full_struct of cnt_0_to_7 is
-- декларативная часть архитектуры -
-- объявление сигналов и компонентов
-- Внутренние линии, которые соединяют триггера
-- и комбинационные схемы
-- выходы триггеров
signal s_Q : std_logic_vector(3 downto 0);
signal s_notQ : std_logic_vector(3 downto 0);
-- входы триггеров, сигнал переключения (переноса)
signal s_t : std_logic_vector(3 downto 0);
-- Внутренний сигнал сброса
signal s_reset : std_logic;
-- Объявление компонента - JK-триггера
-- (копия entity JK-триггера)
component jk_trig is
port (
R, S, C, J, K : in std_logic;
Q, notQ : out std_logic
);
end component;
-- Объявление компонента - элемента 2-И
-- (копия entity двухвходового И)
component and_2 is
port (
x1, x2 : in std_logic;
y : out std_logic
);
end component;
begin
-- тело архитектуры
-- Формируем сигналы переноса
-- нулевой триггер переключается с каждым импульсом
s_t(0) <= '1';
-- Перенос формируем тогда, когда на предудущем разряде была 1-ца
-- и был перенос из предыдущего разряда
and1 : and_2
port map(x1 => s_q(0), x2 => s_t(0), y => s_t(1));
and2 : and_2
port map(s_q(1), s_t(1), s_t(2));
and3 : and_2
port map(s_q(2), s_t(2), s_t(3));
-- Сброс происходит тогда, когда на выходе триггеров получаем Q >= 8
-- (Q больше либо равно 8-ми, 1000)
-- ЛИБО когда пришел сброс на вход
-- reset = not(s_q(3) or not R) = not s_q(3) and R
and_reset : and_2
port map(s_notQ(3), R, s_reset);
-- подключение триггеров
-- метка: название_компонента port map(внутр_порт => внешн_порт) generic map(переменная => переменная);
TR1 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(0), K => s_t(0), Q => s_q(0), notQ => s_notQ(0));
TR2 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(1), K => s_t(1), Q => s_q(1), notQ => s_notQ(1));
TR3 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(2), K => s_t(2), Q => s_q(2), notQ => s_notQ(2));
TR4 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(3), K => s_t(3), Q => s_q(3), notQ => s_notQ(3));
-- Последний оператор: устанавливаем значения на выходе
Q <= s_q;
end architecture;
| mit | 59d347579e28164ec0bb1286dc58f454 | 0.618363 | 1.958561 | false | false | false | false |
speters/mprfgen | test2.vhd | 1 | 2,302 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 1;
NRP : integer := 1;
AW : integer := 11;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
component regfile_core
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end component;
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : entity WORK.regfile_core(READ_FIRST)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(0),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0))
);
ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1)-1 downto DW*0);
end rtl;
| gpl-3.0 | 33c911bb178bdfbcadc3de1ab9a116e6 | 0.519983 | 3.123474 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/eth/greth_rx.vhd | 2 | 11,635 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
v.mcasthash := (others => '0');
v.dataout := (others => '0');
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
| bsd-2-clause | 6e0a578c49fcb323c5f8e3d1f9aaab76 | 0.499871 | 3.25 | false | false | false | false |
bpervan/uart | UARTTransmitter.vhd | 1 | 3,291 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:32 03/11/2014
-- Design Name:
-- Module Name: UARTTransmitter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTTransmitter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
d_in : in STD_LOGIC_VECTOR (7 downto 0);
tx_start : in STD_LOGIC;
tx_done : out STD_LOGIC;
tx : out STD_LOGIC);
end UARTTransmitter;
architecture Behavioral of UARTTransmitter is
type state_type is (idle, start, data, stop);
signal next_state, current_state : state_type;
signal tick_counter, tick_counter_next : unsigned (3 downto 0);
signal bit_counter, bit_counter_next : unsigned (2 downto 0);
signal reg, reg_next : std_logic_vector (7 downto 0);
signal tx_reg, tx_reg_next : std_logic;
begin
process (clk, rst)
begin
if (rst = '1') then
current_state <= idle;
tick_counter <= (others => '0');
bit_counter <= (others => '0');
reg <= (others => '0');
tx_reg <= '1';
else
if (rising_edge(clk)) then
current_state <= next_state;
tick_counter <= tick_counter_next;
bit_counter <= bit_counter_next;
reg <= reg_next;
tx_reg <= tx_reg_next;
end if;
end if;
end process;
process(current_state, tick_counter, bit_counter, reg, tick, tx_reg, tx_start, d_in)
begin
next_state <= current_state;
tick_counter_next <= tick_counter;
bit_counter_next <= bit_counter;
reg_next <= reg;
tx_reg_next <= tx_reg;
tx_done <= '0';
case current_state is
when idle =>
tx_reg_next <= '1';
if(tx_start = '1') then
next_state <= start;
tick_counter_next <= "0000";
reg_next <= d_in;
end if;
when start =>
tx_reg_next <= '0';
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
bit_counter_next <= "000";
next_state <= data;
end if;
end if;
when data =>
tx_reg_next <= reg(0);
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
reg_next <= '0' & reg(7 downto 1);
if (bit_counter = 7) then
next_state <= stop;
else
bit_counter_next <= bit_counter + 1;
end if;
end if;
end if;
when stop =>
tx_reg_next <= '1';
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
next_state <= idle;
tx_done <= '1';
end if;
end if;
end case;
end process;
tx <= tx_reg;
end Behavioral;
| mit | 30ae0fb0458b9b33e2502a9c66c8f7c6 | 0.567001 | 3.182785 | false | false | false | false |
BogdanArdelean/FPWAM | hardware/src/hdl/BindUnit.vhd | 1 | 4,172 | -------------------------------------------------------------------------------
-- FILE NAME : BindUnit.vhd
-- MODULE NAME : BindUnit
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that executes the bind(a1, a2) WAM ancillary operation
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity BindUnit is
generic
(
kAddressWidth : natural := kWamAddressWidth; -- 16
kWordWidth : natural := kWamWordWidth -- 18
);
port
(
clk : in std_logic;
rst : in std_logic;
start_bind : in std_logic;
start_word1 : in std_logic_vector(kWordWidth -1 downto 0);
start_word2 : in std_logic_vector(kWordWidth -1 downto 0);
mem_addr1 : out std_logic_vector(kAddressWidth -1 downto 0);
mem_out1 : out std_logic_vector(kWordWidth -1 downto 0);
mem_wr_1 : out std_logic;
mem_addr2 : out std_logic_vector(kAddressWidth -1 downto 0);
mem_out2 : out std_logic_vector(kWordWidth -1 downto 0);
mem_wr_2 : out std_logic;
trail_input : out std_logic_vector(kAddressWidth -1 downto 0);
trail : out std_logic;
bind_done : out std_logic
);
end BindUnit;
architecture Behavioral of BindUnit is
type state_t is (idle_t, bind_t, trail1_t, trail2_t);
signal cr_state, nx_state : state_t;
signal word1_reg : std_logic_vector(kWordWidth -1 downto 0);
signal word2_reg : std_logic_vector(kWordWidth -1 downto 0);
signal register_input : std_logic;
begin
REGINPUT: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
word1_reg <= (others => '0');
word2_reg <= (others => '0');
elsif register_input = '1' then
word1_reg <= start_word1;
word2_reg <= start_word2;
end if;
end if;
end process;
FSM: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cr_state <= idle_t;
else
cr_state <= nx_state;
end if;
end if;
end process;
NEXT_STATE: process(cr_state, start_bind, word2_reg, word1_reg)
begin
nx_state <= cr_state;
case cr_state is
when idle_t =>
if start_bind = '1' then
nx_state <= bind_t;
end if;
when bind_t =>
if fpwam_tag(word1_reg) = tag_ref_t
and ((fpwam_tag(word2_reg) /= tag_ref_t) or (unsigned(fpwam_value(word2_reg)) < unsigned(fpwam_value(word1_reg)))) then
nx_state <= trail1_t;
else
nx_state <= trail2_t;
end if;
when others =>
nx_state <= idle_t;
end case;
end process;
OUTPUT_DECODE: process(cr_state, start_bind, word1_reg, word2_reg)
begin
mem_addr1 <= (others => '0');
mem_out1 <= (others => '0');
mem_wr_1 <= '0';
mem_addr2 <= (others => '0');
mem_out2 <= (others => '0');
mem_wr_2 <= '0';
trail_input <= (others => '0');
trail <= '0';
bind_done <= '0';
register_input <= '0';
case cr_state is
when idle_t =>
if start_bind = '1' then
register_input <= '1';
end if;
when bind_t =>
null;
when trail1_t =>
bind_done <= '1';
trail <= '1';
trail_input <= fpwam_value(word1_reg);
mem_addr1 <= fpwam_value(word1_reg);
mem_wr_1 <= '1';
mem_out1 <= word2_reg;
when trail2_t =>
bind_done <= '1';
trail <= '1';
trail_input <= fpwam_value(word2_reg);
mem_addr2 <= fpwam_value(word2_reg);
mem_wr_2 <= '1';
mem_out2 <= word1_reg;
when others =>
null;
end case;
end process;
end Behavioral;
| apache-2.0 | 9c2c590d861d8acccb110fedaa6c1bbb | 0.512224 | 3.488294 | false | false | false | false |
olofk/oh | xilibs/ip/fifo_async_104x32/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd | 15 | 90,319 | `protect begin_protected
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| gpl-3.0 | e4268e899630488610183b3444bdfca4 | 0.953011 | 1.836088 | false | false | false | false |
s-kostyuk/vhdl_samples | cnt_jk_8/cnt_0_to_7.vhd | 1 | 2,912 | library IEEE;
use ieee.std_logic_1164.all;
entity cnt_0_to_7 is
port (
R, C : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end entity;
-- Суммирующий синхронный счетчик на JK-триггерах
-- с коэффициентом пересчета 8.
-- Модель со смесью стилей: структурного и потока данных
architecture cnt_0_to_7 of cnt_0_to_7 is
-- декларативная часть архитектуры -
-- объявление сигналов и компонентов
-- Внутренние линии, которые соединяют триггера
-- и комбинационные схемы
-- выходы триггеров
signal s_Q : std_logic_vector(3 downto 0);
signal s_notQ : std_logic_vector(3 downto 0);
-- входы триггеров, сигнал переключения (переноса)
signal s_t : std_logic_vector(3 downto 0);
-- Внутренний сигнал сброса
signal s_reset : std_logic;
-- Объявление компонента - JK-триггера
-- (копия entity JK-триггера)
component jk_trig is
port (
R, S, C, J, K : in std_logic;
Q, notQ : out std_logic
);
end component;
begin
-- тело архитектуры
-- Формируем сигналы переноса
-- нулевой триггер переключается с каждым импульсом
s_t(0) <= '1';
-- Перенос формируем тогда, когда на предудущем разряде была 1-ца
-- и был перенос из предыдущего разряда
s_t(1) <= s_q(0) and s_t(0);
s_t(2) <= s_q(1) and s_t(1);
s_t(3) <= s_q(2) and s_t(2);
-- Сброс происходит тогда, когда на выходе триггеров получаем Q >= 8
-- (Q больше либо равно 8-ми, 1000)
-- ЛИБО когда пришел сброс на вход
-- reset = not(s_q(3) or not R) = not s_q(3) and R
s_reset <= s_notQ(3) and R;
-- подключение триггеров
-- метка: название_компонента port map(внутр_порт => внешн_порт) generic map(переменная => переменная);
TR1 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(0), K => s_t(0), Q => s_q(0), notQ => s_notQ(0));
TR2 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(1), K => s_t(1), Q => s_q(1), notQ => s_notQ(1));
TR3 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(2), K => s_t(2), Q => s_q(2), notQ => s_notQ(2));
TR4 : jk_trig
port map(R => s_reset, S => '1', C => C, J => s_t(3), K => s_t(3), Q => s_q(3), notQ => s_notQ(3));
-- Последний оператор: устанавливаем значения на выходе
Q <= s_q;
end architecture;
| mit | 602dac8c9e8acebb06c2c86d6e056b5f | 0.628833 | 1.885246 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sim_1/new/SimALL.vhd | 1 | 1,830 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.02.2016 23:50:03
-- Design Name:
-- Module Name: SimALL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SimALL is
-- Port ( );
end SimALL;
architecture Behavioral of SimALL is
constant Clk_period : time := 10ns;
signal clk : STD_LOGIC;
signal SDA1 : STD_LOGIC;
signal SCL1 : STD_LOGIC;
signal RsTx : STD_LOGIC;
signal btnCpuReset : STD_LOGIC := '1';
begin
UUT: entity work.topmodule(Behavioral)
port map (
clk => clk,
btnCpuReset => btnCpuReset,
SDA1 => SDA1,
SCL1 => SCL1,
RsTx => RsTx
);
-- Clock process definitions
Clk_process :process
begin
clk <= '0';
wait for Clk_period/2;
clk <= '1';
wait for Clk_period/2;
end process;
-- random reset program
reset_process : process
begin
SDA1 <= 'H';
btnCpuReset <= '0';
wait for Clk_period * 200;
btnCpuReset <= '1';
wait for Clk_period * 2550;
SDA1 <= '0';
wait for Clk_period * 249;
SDA1 <= 'H';
wait for Clk_period * 999;
wait for Clk_period * 999;
wait;
end process;
SCL1 <= 'H';
end Behavioral;
| gpl-3.0 | 38c058bbed36649cf11a8bc5ff0c8346 | 0.561202 | 3.820459 | false | false | false | false |
hoangt/PoC | src/io/io_Debounce.vhdl | 2 | 5,080 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Module: Debounce module for BITS many bouncing input pins.
--
-- Description:
-- ------------------------------------
-- This module debounces several input pins preventing input changes
-- following a previous one within the configured BOUNCE_TIME to pass.
-- Internally, the forwarded state is locked for, at least, this BOUNCE_TIME.
-- As the backing timer is restarted on every input fluctuation, the next
-- passing input update must have seen a stabilized input.
--
-- The parameter COMMON_LOCK uses a single internal timer for all processed
-- inputs. Thus, all inputs must stabilize before any one may pass changed.
-- This option is usually fully acceptable for user inputs such as push buttons.
--
-- The parameter ADD_INPUT_SYNCHRONIZERS triggers the optional instantiation
-- of a two-FF input synchronizer on each input bit.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_Debounce is
generic (
CLOCK_FREQ : freq;
BOUNCE_TIME : time;
BITS : positive := 1;
ADD_INPUT_SYNCHRONIZERS : boolean := true;
COMMON_LOCK : boolean := false
);
port (
Clock : in std_logic;
Reset : in std_logic := '0';
Input : in std_logic_vector(BITS-1 downto 0);
Output : out std_logic_vector(BITS-1 downto 0)
);
end;
architecture rtl of io_Debounce is
-- Number of required locking cycles
constant LOCK_COUNT_X : integer := TimingToCycles(BOUNCE_TIME, CLOCK_FREQ) - 1;
-- Input Refinements
signal sync : std_logic_vector(Input'range); -- Synchronized
signal prev : std_logic_vector(Input'range) := (others => '0'); -- Delayed
signal active : std_logic_vector(Input'range); -- Allow Output Updates
begin
-----------------------------------------------------------------------------
-- Input Synchronization
genNoSync: if not ADD_INPUT_SYNCHRONIZERS generate
sync <= Input;
end generate;
genSync: if ADD_INPUT_SYNCHRONIZERS generate
sync_i : entity PoC.sync_Bits
generic map (
BITS => BITS
)
port map (
Clock => Clock, -- Clock to be synchronized to
Input => Input, -- Data to be synchronized
Output => sync -- synchronised data
);
end generate;
-----------------------------------------------------------------------------
-- Bounce Filter
process(Clock)
begin
if rising_edge(Clock) then
prev <= sync;
if (Reset = '1') then
Output <= sync;
else
for i in Output'range loop
if active(i) = '1' then
Output(i) <= sync(i);
end if;
end loop;
end if;
end if;
end process;
genNoLock: if LOCK_COUNT_X <= 0 generate
active <= (others => '1');
end generate genNoLock;
genLock: if LOCK_COUNT_X > 0 generate
constant LOCKS : positive := ite(COMMON_LOCK, 1, BITS);
signal toggle : std_logic_vector(LOCKS-1 downto 0);
signal locked : std_logic_vector(LOCKS-1 downto 0);
begin
genOneLock: if COMMON_LOCK generate
toggle(0) <= '1' when prev /= sync else '0';
active <= (others => not locked(0));
end generate genOneLock;
genManyLocks: if not COMMON_LOCK generate
toggle <= prev xor sync;
active <= not locked;
end generate genManyLocks;
genLocks: for i in 0 to LOCKS-1 generate
signal Lock : signed(log2ceil(LOCK_COUNT_X+1) downto 0) := (others => '0');
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Lock <= (others => '0');
else
if toggle(i) = '1' then
Lock <= to_signed(-LOCK_COUNT_X, Lock'length);
elsif locked(i) = '1' then
Lock <= Lock + 1;
end if;
end if;
end if;
end process;
locked(i) <= Lock(Lock'left);
end generate genLocks;
end generate genLock;
end;
| apache-2.0 | fe375ba53257204b89300c1e178a6767 | 0.596457 | 3.768546 | false | false | false | false |
hoangt/PoC | src/bus/stream/stream.pkg.vhdl | 2 | 17,984 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.bus.stream namespace
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
package stream is
-- single dataword for TestRAM
type T_SIM_STREAM_WORD_8 is record
Valid : STD_LOGIC;
Data : T_SLV_8;
SOF : STD_LOGIC;
EOF : STD_LOGIC;
Ready : STD_LOGIC;
EOFG : BOOLEAN;
end record;
type T_SIM_STREAM_WORD_32 is record
Valid : STD_LOGIC;
Data : T_SLV_32;
SOF : STD_LOGIC;
EOF : STD_LOGIC;
Ready : STD_LOGIC;
EOFG : BOOLEAN;
end record;
-- define array indices
constant C_SIM_STREAM_MAX_PATTERN_COUNT : POSITIVE := 128;-- * 1024; -- max data size per testcase
constant C_SIM_STREAM_MAX_FRAMEGROUP_COUNT : POSITIVE := 8;
constant C_SIM_STREAM_WORD_INDEX_BW : POSITIVE := log2ceilnz(C_SIM_STREAM_MAX_PATTERN_COUNT);
constant C_SIM_STREAM_FRAMEGROUP_INDEX_BW : POSITIVE := log2ceilnz(C_SIM_STREAM_MAX_FRAMEGROUP_COUNT);
subtype T_SIM_STREAM_WORD_INDEX is INTEGER range 0 to C_SIM_STREAM_MAX_PATTERN_COUNT - 1;
subtype T_SIM_STREAM_FRAMEGROUP_INDEX is INTEGER range 0 to C_SIM_STREAM_MAX_FRAMEGROUP_COUNT - 1;
subtype T_SIM_DELAY is T_UINT_16;
type T_SIM_DELAY_VECTOR is array (NATURAL range <>) of T_SIM_DELAY;
-- define array of datawords
type T_SIM_STREAM_WORD_VECTOR_8 is array (NATURAL range <>) of T_SIM_STREAM_WORD_8;
type T_SIM_STREAM_WORD_VECTOR_32 is array (NATURAL range <>) of T_SIM_STREAM_WORD_32;
-- define link layer directions
type T_SIM_STREAM_DIRECTION is (Send, RECEIVE);
-- define framegroup information
type T_SIM_STREAM_FRAMEGROUP_8 is record
Active : BOOLEAN;
Name : STRING(1 to 64);
PrePause : NATURAL;
PostPause : NATURAL;
DataCount : T_SIM_STREAM_WORD_INDEX;
Data : T_SIM_STREAM_WORD_VECTOR_8(0 to C_SIM_STREAM_MAX_PATTERN_COUNT - 1);
end record;
type T_SIM_STREAM_FRAMEGROUP_32 is record
Active : BOOLEAN;
Name : STRING(1 to 64);
PrePause : NATURAL;
PostPause : NATURAL;
DataCount : T_SIM_STREAM_WORD_INDEX;
Data : T_SIM_STREAM_WORD_VECTOR_32(T_SIM_STREAM_WORD_INDEX);
end record;
-- define array of framegroups
type T_SIM_STREAM_FRAMEGROUP_VECTOR_8 is array (NATURAL range <>) of T_SIM_STREAM_FRAMEGROUP_8;
type T_SIM_STREAM_FRAMEGROUP_VECTOR_32 is array (NATURAL range <>) of T_SIM_STREAM_FRAMEGROUP_32;
-- define constants (stored in RAMB36's parity-bits)
constant C_SIM_STREAM_WORD_8_EMPTY : T_SIM_STREAM_WORD_8 := (Valid => '0', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_32_EMPTY : T_SIM_STREAM_WORD_32 := (Valid => '0', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_8_INVALID : T_SIM_STREAM_WORD_8 := (Valid => '0', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_32_INVALID : T_SIM_STREAM_WORD_32 := (Valid => '0', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_8_ZERO : T_SIM_STREAM_WORD_8 := (Valid => '1', Data => (others => 'Z'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_32_ZERO : T_SIM_STREAM_WORD_32 := (Valid => '1', Data => (others => 'Z'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_8_UNDEF : T_SIM_STREAM_WORD_8 := (Valid => '1', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_WORD_32_UNDEF : T_SIM_STREAM_WORD_32 := (Valid => '1', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE);
constant C_SIM_STREAM_FRAMEGROUP_8_EMPTY : T_SIM_STREAM_FRAMEGROUP_8 := (
Active => FALSE,
Name => (others => C_POC_NUL),
PrePause => 0,
PostPause => 0,
DataCount => 0,
Data => (others => C_SIM_STREAM_WORD_8_EMPTY)
);
constant C_SIM_STREAM_FRAMEGROUP_32_EMPTY : T_SIM_STREAM_FRAMEGROUP_32 := (
Active => FALSE,
Name => (others => C_POC_NUL),
PrePause => 0,
PostPause => 0,
DataCount => 0,
Data => (others => C_SIM_STREAM_WORD_32_EMPTY)
);
function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL;
function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_32) return NATURAL;
function dat(slv : T_SLV_8) return T_SIM_STREAM_WORD_8;
function dat(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8;
function dat(slv : T_SLV_32) return T_SIM_STREAM_WORD_32;
function dat(slvv : T_SLVV_32) return T_SIM_STREAM_WORD_VECTOR_32;
function sof(slv : T_SLV_8) return T_SIM_STREAM_WORD_8;
function sof(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8;
function sof(slv : T_SLV_32) return T_SIM_STREAM_WORD_32;
function sof(slvv : T_SLVV_32) return T_SIM_STREAM_WORD_VECTOR_32;
function eof(slv : T_SLV_8) return T_SIM_STREAM_WORD_8;
function eof(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8;
function eof(slv : T_SLV_32) return T_SIM_STREAM_WORD_32;
function eof(slvv : T_SLVV_32) return T_SIM_STREAM_WORD_VECTOR_32;
function eof(stmw : T_SIM_STREAM_WORD_8) return T_SIM_STREAM_WORD_8;
function eof(stmwv : T_SIM_STREAM_WORD_VECTOR_8) return T_SIM_STREAM_WORD_VECTOR_8;
function eof(stmw : T_SIM_STREAM_WORD_32) return T_SIM_STREAM_WORD_32;
function eofg(stmw : T_SIM_STREAM_WORD_8) return T_SIM_STREAM_WORD_8;
function eofg(stmwv : T_SIM_STREAM_WORD_VECTOR_8) return T_SIM_STREAM_WORD_VECTOR_8;
function eofg(stmw : T_SIM_STREAM_WORD_32) return T_SIM_STREAM_WORD_32;
function to_string(stmw : T_SIM_STREAM_WORD_8) return STRING;
function to_string(stmw : T_SIM_STREAM_WORD_32) return STRING;
-- checksum functions
-- ================================================================
function sim_CRC8(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR;
-- function sim_CRC16(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR;
end;
package body stream is
function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is
begin
for i in 0 to Data'length - 1 loop
if (Data(i).EOFG = TRUE) then
return i + 1;
end if;
end loop;
return 0;
end;
function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_32) return NATURAL is
begin
for i in 0 to Data'length - 1 loop
if (Data(i).EOFG = TRUE) then
return i + 1;
end if;
end loop;
return 0;
end;
function dat(slv : T_SLV_8) return T_SIM_STREAM_WORD_8 is
variable result : T_SIM_STREAM_WORD_8;
begin
result := (Valid => '1', Data => slv, SOF => '0', EOF => '0', Ready => '-', EOFG => FALSE);
report "dat: " & to_string(result) severity NOTE;
return result;
end;
function dat(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8 is
variable result : T_SIM_STREAM_WORD_VECTOR_8(slvv'range);
begin
for i in slvv'range loop
result(i) := dat(slvv(i));
end loop;
return result;
end;
function dat(slv : T_SLV_32) return T_SIM_STREAM_WORD_32 is
variable result : T_SIM_STREAM_WORD_32;
begin
result := (Valid => '1', Data => slv, SOF => '0', EOF => '0', Ready => '-', EOFG => FALSE);
report "dat: " & to_string(result) severity NOTE;
return result;
end;
function dat(slvv : T_SLVV_32) return T_SIM_STREAM_WORD_VECTOR_32 is
variable result : T_SIM_STREAM_WORD_VECTOR_32(slvv'range);
begin
for i in slvv'range loop
result(i) := dat(slvv(i));
end loop;
return result;
end;
function sof(slv : T_SLV_8) return T_SIM_STREAM_WORD_8 is
variable result : T_SIM_STREAM_WORD_8;
begin
result := (Valid => '1', Data => slv, SOF => '1', EOF => '0', Ready => '-', EOFG => FALSE);
report "sof: " & to_string(result) severity NOTE;
return result;
end;
function sof(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8 is
variable result : T_SIM_STREAM_WORD_VECTOR_8(slvv'range);
begin
result(slvv'low) := sof(slvv(slvv'low));
for i in slvv'low + 1 to slvv'high loop
result(i) := dat(slvv(i));
end loop;
return result;
end;
function sof(slv : T_SLV_32) return T_SIM_STREAM_WORD_32 is
variable result : T_SIM_STREAM_WORD_32;
begin
result := (Valid => '1', Data => slv, SOF => '1', EOF => '0', Ready => '-', EOFG => FALSE);
report "sof: " & to_string(result) severity NOTE;
return result;
end;
function sof(slvv : T_SLVV_32) return T_SIM_STREAM_WORD_VECTOR_32 is
variable result : T_SIM_STREAM_WORD_VECTOR_32(slvv'range);
begin
result(slvv'low) := sof(slvv(slvv'low));
for i in slvv'low + 1 to slvv'high loop
result(i) := dat(slvv(i));
end loop;
return result;
end;
function eof(slv : T_SLV_8) return T_SIM_STREAM_WORD_8 is
variable result : T_SIM_STREAM_WORD_8;
begin
result := (Valid => '1', Data => slv, SOF => '0', EOF => '1', Ready => '-', EOFG => FALSE);
report "eof: " & to_string(result) severity NOTE;
return result;
end;
function eof(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8 is
variable result : T_SIM_STREAM_WORD_VECTOR_8(slvv'range);
begin
for i in slvv'low to slvv'high - 1 loop
result(i) := dat(slvv(i));
end loop;
result(slvv'high) := eof(slvv(slvv'high));
return result;
end;
function eof(slv : T_SLV_32) return T_SIM_STREAM_WORD_32 is
variable result : T_SIM_STREAM_WORD_32;
begin
result := (Valid => '1', Data => slv, SOF => '0', EOF => '1', Ready => '-', EOFG => FALSE);
report "eof: " & to_string(result) severity NOTE;
return result;
end;
function eof(slvv : T_SLVV_32) return T_SIM_STREAM_WORD_VECTOR_32 is
variable result : T_SIM_STREAM_WORD_VECTOR_32(slvv'range);
begin
for i in slvv'low to slvv'high - 1 loop
result(i) := dat(slvv(i));
end loop;
result(slvv'high) := eof(slvv(slvv'high));
return result;
end;
function eof(stmw : T_SIM_STREAM_WORD_8) return T_SIM_STREAM_WORD_8 is
begin
return T_SIM_STREAM_WORD_8'(
Valid => stmw.Valid,
Data => stmw.Data,
SOF => stmw.SOF,
EOF => '1',
Ready => '-',
EOFG => stmw.EOFG);
end function;
function eof(stmw : T_SIM_STREAM_WORD_32) return T_SIM_STREAM_WORD_32 is
begin
return T_SIM_STREAM_WORD_32'(
Valid => stmw.Valid,
Data => stmw.Data,
SOF => stmw.SOF,
EOF => '1',
Ready => '-',
EOFG => stmw.EOFG);
end function;
function eof(stmwv : T_SIM_STREAM_WORD_VECTOR_8) return T_SIM_STREAM_WORD_VECTOR_8 is
variable result : T_SIM_STREAM_WORD_VECTOR_8(stmwv'range);
begin
for i in stmwv'low to stmwv'high - 1 loop
result(i) := stmwv(i);
end loop;
result(stmwv'high) := eof(stmwv(stmwv'high));
return result;
end;
function eofg(stmw : T_SIM_STREAM_WORD_8) return T_SIM_STREAM_WORD_8 is
begin
return T_SIM_STREAM_WORD_8'(
Valid => stmw.Valid,
Data => stmw.Data,
SOF => stmw.SOF,
EOF => stmw.EOF,
Ready => stmw.Ready,
EOFG => TRUE);
end function;
function eofg(stmw : T_SIM_STREAM_WORD_32) return T_SIM_STREAM_WORD_32 is
begin
return T_SIM_STREAM_WORD_32'(
Valid => stmw.Valid,
Data => stmw.Data,
SOF => stmw.SOF,
EOF => stmw.EOF,
Ready => stmw.Ready,
EOFG => TRUE);
end function;
function eofg(stmwv : T_SIM_STREAM_WORD_VECTOR_8) return T_SIM_STREAM_WORD_VECTOR_8 is
variable result : T_SIM_STREAM_WORD_VECTOR_8(stmwv'range);
begin
for i in stmwv'low to stmwv'high - 1 loop
result(i) := stmwv(i);
end loop;
result(stmwv'high) := eofg(stmwv(stmwv'high));
return result;
end;
function to_flag1_string(stmw : T_SIM_STREAM_WORD_8) return STRING is
variable flag : STD_LOGIC_VECTOR(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF;
begin
case flag is
when "000" => return "";
when "001" => return "SOF";
when "010" => return "EOF";
when "011" => return "SOF+EOF";
when "100" => return "*";
when "101" => return "SOF*";
when "110" => return "EOF*";
when "111" => return "SOF+EOF*";
when others => return "ERROR";
end case;
end function;
function to_flag1_string(stmw : T_SIM_STREAM_WORD_32) return STRING is
variable flag : STD_LOGIC_VECTOR(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF;
begin
case flag is
when "000" => return "";
when "001" => return "SOF";
when "010" => return "EOF";
when "011" => return "SOF+EOF";
when "100" => return "*";
when "101" => return "SOF*";
when "110" => return "EOF*";
when "111" => return "SOF+EOF*";
when others => return "ERROR";
end case;
end function;
function to_flag2_string(stmw : T_SIM_STREAM_WORD_8) return STRING is
variable flag : STD_LOGIC_VECTOR(1 downto 0) := stmw.Ready & stmw.Valid;
begin
case flag is
when "00" => return " ";
when "01" => return " V";
when "10" => return "R ";
when "11" => return "RV";
when "-0" => return "- ";
when "-1" => return "-V";
when others => return "??";
end case;
end function;
function to_flag2_string(stmw : T_SIM_STREAM_WORD_32) return STRING is
variable flag : STD_LOGIC_VECTOR(1 downto 0) := stmw.Ready & stmw.Valid;
begin
case flag is
when "00" => return " ";
when "01" => return " V";
when "10" => return "R ";
when "11" => return "RV";
when "-0" => return "- ";
when "-1" => return "-V";
when others => return "??";
end case;
end function;
function to_string(stmw : T_SIM_STREAM_WORD_8) return STRING is
begin
return to_flag2_string(stmw) & " 0x" & to_string(stmw.Data, 'h') & " " & to_flag1_string(stmw);
end function;
function to_string(stmw : T_SIM_STREAM_WORD_32) return STRING is
begin
return to_flag2_string(stmw) & " 0x" & to_string(stmw.Data, 'h') & " " & to_flag1_string(stmw);
end function;
-- checksum functions
-- ================================================================
-- -- Private function to_01 copied from GlobalTypes
-- function to_01(slv : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- begin
-- return to_stdlogicvector(to_bitvector(slv));
-- end;
function sim_CRC8(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR is
constant CRC8_INIT : T_SLV_8 := x"FF";
constant CRC8_POLYNOMIAL : T_SLV_8 := x"31"; -- 0x131
variable CRC8_Value : T_SLV_8 := CRC8_INIT;
-- variable Pattern : T_DATAFifO_PATTERN;
variable Word : UNSIGNED(T_SLV_8'range);
begin
report "Computing CRC8 for Words " & to_string(words'low) & " to " & to_string(words'high) severity NOTE;
for i in words'range loop
if (words(i).Valid = '1') then
Word := to_01(unsigned(words(i).Data));
-- ASSERT (J > 9) report str_merge(" Word: 0x", hstr(Word), " CRC16_Value: 0x", hstr(CRC16_Value)) severity NOTE;
for j in Word'range loop
CRC8_Value := (CRC8_Value(CRC8_Value'high - 1 downto 0) & '0') xor (CRC8_POLYNOMIAL and (CRC8_POLYNOMIAL'range => (Word(J) xor CRC8_Value(CRC8_Value'high))));
end loop;
end if;
exit when (words(i).EOFG = TRUE);
end loop;
report " CRC8: 0x" & to_string(CRC8_Value, 'h') severity NOTE;
return CRC8_Value;
end;
-- function sim_CRC16(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR is
-- constant CRC16_INIT : T_SLV_16 := x"FFFF";
-- constant CRC16_POLYNOMIAL : T_SLV_16 := x"8005"; -- 0x18005
--
-- variable CRC16_Value : T_SLV_16 := CRC16_INIT;
--
-- variable Pattern : T_DATAFifO_PATTERN;
-- variable Word : T_SLV_32;
-- begin
-- report str_merge("Computing CRC16 for Frames ", str(Frames'low), " to ", str(Frames'high)) severity NOTE;
--
-- for i in Frames'range loop
-- NEXT when (NOT ((Frames(i).Direction = DEV_HOST) AND (Frames(i).DataFifOPatterns(0).Data(7 downto 0) = x"46")));
--
---- report Frames(i).Name severity NOTE;
--
-- FOR J IN 1 to Frames(i).Count - 1 loop
-- Pattern := Frames(i).DataFifOPatterns(J);
--
-- if (Pattern.Valid = '1') then
-- Word := to_01(Pattern.Data);
--
---- ASSERT (J > 9) report str_merge(" Word: 0x", hstr(Word), " CRC16_Value: 0x", hstr(CRC16_Value)) severity NOTE;
--
-- FOR K IN Word'range loop
-- CRC16_Value := (CRC16_Value(CRC16_Value'high - 1 downto 0) & '0') XOR (CRC16_POLYNOMIAL AND (CRC16_POLYNOMIAL'range => (Word(K) XOR CRC16_Value(CRC16_Value'high))));
-- end loop;
-- end if;
--
-- EXIT when (Pattern.EOTP = TRUE);
-- end loop;
-- end loop;
--
-- report str_merge(" CRC16: 0x", hstr(CRC16_Value)) severity NOTE;
--
-- return CRC16_Value;
-- end;
end package body;
| apache-2.0 | 300cdb1ab3ac8f8f74dfee21ca74303a | 0.613712 | 2.742718 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/receive.vhd | 4 | 14,925 | -------------------------------------------------------------------------------
-- receive - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : receive.vhd
-- Version : v2.0
-- Description : This is the receive path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
library unisim;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_rx_clk -- Ethernet receive clock
-- Phy_dv -- Ethernet receive enable
-- Phy_rx_data -- Ethernet receive data
-- Phy_rx_col -- Ethernet collision indicator
-- Phy_rx_er -- Ethernet receive error
-- Rx_addr_en -- RX buufer address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity receive is
generic
(
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_rx_clk : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_rx_col : in std_logic;
Phy_rx_er : in std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end receive;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of receive is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal fifo_empty_i : std_logic;
signal fifo_full_i : std_logic;
signal emac_rx_rd_i : std_logic;
signal emac_rx_rd_data_i : std_logic_vector(0 to 5);
signal emac_rx_rd_data_d1 : std_logic_vector(0 to 5); -- 03-26-04
signal rxAbortRst : std_logic;
signal rxChannelReset : std_logic;
signal rxBusFifoRdAck : std_logic;
signal rxComboCrcRst : std_logic;
signal rxComboCrcEn : std_logic;
signal crcOk_i : std_logic;
signal rxCrcRst : std_logic;
signal rxCrcEn : std_logic;
signal rxCrcEn_d1 : std_logic; -- 03-26-04
signal receive_enable : std_logic; -- 03-26-04
signal fifo_reset : std_logic; -- 03-26-04
begin
----------------------------------------------------------------------------
-- rx control state machine
----------------------------------------------------------------------------
INST_RX_STATE: entity axi_ethernetlite_v3_0.rx_statemachine
generic map (
C_DUPLEX => C_DUPLEX
)
port map (
Clk => Clk,
Rst => rxChannelReset,
Emac_rx_rd_data_d1 => emac_rx_rd_data_d1, -- 03-26-04
Receive_enable => receive_enable, -- 03-26-04
RxBusFifoRdAck => rxBusFifoRdAck,
BusFifoEmpty => fifo_empty_i,
Collision => Phy_rx_col,
DataValid => emac_rx_rd_data_i(4),
RxError => emac_rx_rd_data_i(5),
BusFifoData => emac_rx_rd_data_i(0 to 3),
CrcOk => crcOk_i,
BusFifoRd => emac_rx_rd_i,
RxAbortRst => rxAbortRst,
RxCrcRst => rxCrcRst,
RxCrcEn => rxCrcEn,
Rx_addr_en => Rx_addr_en,
Rx_start => Rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => Mac_addr_ram_addr_rd,
Mac_addr_ram_data => Mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
rxChannelReset <= Rst;
----------------------------------------------------------------------------
-- rx interface contains the ethernet rx fifo
----------------------------------------------------------------------------
INST_RX_INTRFCE: entity axi_ethernetlite_v3_0.rx_intrfce
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => fifo_reset,
Phy_rx_clk => Phy_rx_clk,
InternalWrapEn => '0',
Phy_rx_er => Phy_rx_er,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Rcv_en => receive_enable,
Fifo_empty => fifo_empty_i,
Fifo_full => fifo_full_i,
Emac_rx_rd => emac_rx_rd_i,
Emac_rx_rd_data => emac_rx_rd_data_i,
RdAck => rxBusFifoRdAck
);
--fifo_reset <= Rst or not(receive_enable); -- 03-26-04
fifo_reset <= Rst; -- removing cross clock passing of signal(receive_enable is genrated in lite_clock domain and going to fifo working in rx_clk domain)
----------------------------------------------------------------------------
-- crc checker
----------------------------------------------------------------------------
INST_CRCGENRX: entity axi_ethernetlite_v3_0.crcgenrx
port map(
Clk => Clk,
Rst => rxComboCrcRst,
Data => emac_rx_rd_data_i(0 to 3),
DataEn => rxComboCrcEn,
CrcOk => crcOk_i);
rxComboCrcRst <= Rst or rxCrcRst or rxAbortRst;
rxComboCrcEn <= rxCrcEn_d1;
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the received read data and receive CRC enable.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
emac_rx_rd_data_d1 <= "000000";
rxCrcEn_d1 <= '0';
else
emac_rx_rd_data_d1 <= emac_rx_rd_data_i;
rxCrcEn_d1 <= rxCrcEn;
end if;
end if;
end process REG_PROCESS;
end imp;
| gpl-3.0 | 8aa56837793087d64ea4cf50ca8009a2 | 0.392027 | 4.836358 | false | false | false | false |
wrousseau/a14-2-vhdl | Mask.vhd | 1 | 1,977 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:34:25 10/21/2014
-- Design Name:
-- Module Name: mask - arc1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mask is
Port ( ready : in STD_LOGIC;
k0, k1, k2, k3, k4, k5, k6, k7, k8 : in STD_LOGIC_VECTOR (7 downto 0);
result : out STD_LOGIC_VECTOR (7 downto 0));
end Mask;
ARCHITECTURE arc1 of Mask is
BEGIN
PROCESS(k8)
variable M0 : STD_LOGIC_VECTOR(7 downto 0):= "00000001";
variable M1 : STD_LOGIC_VECTOR(7 downto 0):= "00000001";
variable M2 : STD_LOGIC_VECTOR(7 downto 0):= "00000001";
variable M3 : STD_LOGIC_VECTOR(7 downto 0):= "00000001";
variable M4 : STD_LOGIC_VECTOR(7 downto 0):= "00000000";
variable M5 : STD_LOGIC_VECTOR(7 downto 0):= "10000001";
variable M6 : STD_LOGIC_VECTOR(7 downto 0):= "10000001";
variable M7 : STD_LOGIC_VECTOR(7 downto 0):= "10000001";
variable M8 : STD_LOGIC_VECTOR(7 downto 0):= "10000001";
variable tmpResult : STD_LOGIC_VECTOR(15 downto 0);
BEGIN
--if ready = '1' then
tmpResult := M0 * k0
+ M1 * k1
+ M2 * k2
+ M3 * k3
+ M4 * k4
+ M5 * k5
+ M6 * k6
+ M7 * k7
+ M8 * k8;
result <= tmpResult(7 downto 0);
--end if;
END PROCESS;
END arc1;
| apache-2.0 | 87b6163a2fda8559431d2f8dbab9dd76 | 0.587759 | 3.204214 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/tilelink/axibridge.vhd | 2 | 9,670 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief TileLink-to-AXI4 bridge implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity AxiBridge is
generic (
xindex : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_cached_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_cached_in_type
);
end;
architecture arch_AxiBridge of AxiBridge is
type tile_rstatetype is (rwait_acq, reading);
type tile_wstatetype is (wwait_acq, writting);
type registers is record
rstate : tile_rstatetype;
rd_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
rd_addr_incr : integer;
rd_beat_cnt : integer;
rd_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
rd_xact_id : std_logic_vector(1 downto 0);
rd_g_type : std_logic_vector(3 downto 0);
wstate : tile_wstatetype;
wr_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
wr_addr_incr : integer;
wr_beat_cnt : integer;
wr_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
wr_xact_id : std_logic_vector(1 downto 0);
wr_g_type : std_logic_vector(3 downto 0);
wmask : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
end record;
signal r, rin : registers;
function functionAxi4MetaData(
a : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
len : integer;
sz : std_logic_vector(2 downto 0)
) return nasti_metadata_type is
variable ret : nasti_metadata_type;
begin
ret.addr := a;
ret.len := conv_std_logic_vector(len,8);
ret.size := sz;
ret.burst := NASTI_BURST_INCR;
ret.lock := '0';
ret.cache := (others => '0');
ret.prot := (others => '0');
ret.qos := (others => '0');
ret.region := (others => '0');
return (ret);
end function;
begin
comblogic : process(tloi, msti, r)
variable v : registers;
variable vmsto : nasti_master_out_type;
variable vtlio : tile_cached_in_type;
variable addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable write : std_logic;
variable next_ena : std_logic;
variable wbAddr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable wWrite : std_logic;
variable wbWMask : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable wbAxiSize : std_logic_vector(2 downto 0);
variable wbByteAddr : std_logic_vector(3 downto 0);
variable wbBeatCnt : integer;
begin
v := r;
addr := (others => '0');
write := '0';
vmsto.aw_valid := '0';
vmsto.aw_bits := META_NONE;
vmsto.aw_id := (others => '0');
vmsto.w_valid := '0';
vmsto.w_data := (others => '0');
vmsto.w_last := '0';
vmsto.w_strb := (others => '0');
vmsto.ar_valid := '0';
vmsto.ar_bits := META_NONE;
vmsto.ar_id := (others => '0');
vmsto.r_ready := '0';
vmsto.ar_user := '0';
vmsto.aw_user := '0';
vmsto.w_user := '0';
vmsto.b_ready := '1';
vtlio.acquire_ready := '0';
vtlio.probe_valid := '0'; -- unused
vtlio.release_ready := '0'; -- unused
vtlio.grant_valid := '0';
vtlio.grant_bits_addr_beat := "00";
vtlio.grant_bits_client_xact_id := "00";
vtlio.grant_bits_manager_xact_id := "0000"; -- const
vtlio.grant_bits_is_builtin_type := '1'; -- const
vtlio.grant_bits_g_type := GRANT_ACK_RELEASE;
vtlio.grant_bits_data := (others => '0');
procedureDecodeTileAcquire(tloi.acquire_bits_a_type,--in
tloi.acquire_bits_is_builtin_type, --in
tloi.acquire_bits_union, --in
wWrite,
wbWMask,
wbAxiSize,
wbByteAddr,
wbBeatCnt);
wbAddr := tloi.acquire_bits_addr_block
& tloi.acquire_bits_addr_beat
& "0000";--wbByteAddr;
vmsto.aw_valid := tloi.acquire_valid and wWrite;
vmsto.ar_valid := tloi.acquire_valid and not wWrite;
case r.wstate is
when wwait_acq =>
if vmsto.aw_valid = '1' and msti.grant(xindex) = '1' and r.rstate = rwait_acq then
v.wr_addr := wbAddr;
v.wr_addr_incr := XSizeToBytes(conv_integer(wbAxiSize));
v.wr_beat_cnt := wbBeatCnt;
v.wr_xsize := opSizeToXSize(conv_integer(tloi.acquire_bits_union(8 downto 6)));
v.wr_xact_id := tloi.acquire_bits_client_xact_id;
if tloi.acquire_bits_is_builtin_type = '1' then
v.wr_g_type := GRANT_ACK_NON_PREFETCH_PUT;
else
v.wr_g_type := CACHED_GRANT_EXCLUSIVE_ACK;
end if;
v.wmask := wbWMask;
if msti.aw_ready = '1' then
v.wstate := writting;
v.wdata := tloi.acquire_bits_data;
end if;
vmsto.aw_bits := functionAxi4MetaData(wbAddr, wbBeatCnt, wbAxiSize);
vmsto.aw_id(1 downto 0) := tloi.acquire_bits_client_xact_id;
vmsto.aw_id(CFG_ROCKET_ID_BITS-1 downto 2) := (others => '0');
vtlio.acquire_ready := tloi.acquire_valid and msti.aw_ready;
end if;
when writting =>
if r.wr_beat_cnt = 0 and msti.w_ready = '1' then
vmsto.w_last := '1';
v.wstate := wwait_acq;
elsif msti.w_ready = '1' and tloi.acquire_valid = '1' then
v.wr_beat_cnt := r.wr_beat_cnt - 1;
v.wr_addr := r.wr_addr + r.wr_addr_incr;
v.wdata := tloi.acquire_bits_data;
end if;
vmsto.w_valid := '1';
vmsto.w_data := r.wdata;
vmsto.w_strb := r.wmask;
when others =>
end case;
case r.rstate is
when rwait_acq =>
if vmsto.ar_valid = '1' and msti.grant(xindex) = '1' and r.wstate = wwait_acq then
v.rd_addr := wbAddr;
v.rd_addr_incr := XSizeToBytes(conv_integer(wbAxiSize));
v.rd_beat_cnt := wbBeatCnt;
v.rd_xsize := opSizeToXSize(conv_integer(tloi.acquire_bits_union(8 downto 6)));
v.rd_xact_id := tloi.acquire_bits_client_xact_id;
if tloi.acquire_bits_is_builtin_type = '1' then
if wbBeatCnt = 0 then
v.rd_g_type := GRANT_SINGLE_BEAT_GET;
else
v.rd_g_type := GRANT_BLOCK_GET;
end if;
else
v.wr_g_type := CACHED_GRANT_SHARED;
--wbBeatCnt := 3;
--wbAxiSize := "100";
--v.rd_addr_incr := XSizeToBytes(conv_integer(wbAxiSize));
--v.rd_beat_cnt := wbBeatCnt;
--v.rd_xsize := wbAxiSize;
end if;
if msti.ar_ready = '1' then
v.rstate := reading;
end if;
vmsto.ar_bits := functionAxi4MetaData(wbAddr, wbBeatCnt, wbAxiSize);
vmsto.ar_id(1 downto 0) := tloi.acquire_bits_client_xact_id;
vmsto.ar_id(CFG_ROCKET_ID_BITS-1 downto 2) := (others => '0');
vtlio.acquire_ready := tloi.acquire_valid and msti.ar_ready;
end if;
when reading =>
next_ena := tloi.grant_ready and msti.r_valid;
if next_ena = '1' and r.rd_xact_id = msti.r_id(1 downto 0) then
v.rd_beat_cnt := r.rd_beat_cnt - 1;
v.rd_addr := r.rd_addr + r.rd_addr_incr;
if r.rd_beat_cnt = 0 then
v.rstate := rwait_acq;
end if;
end if;
vmsto.r_ready := tloi.grant_ready;
when others =>
end case;
if r.rstate = reading then
if r.rd_xact_id = msti.r_id(1 downto 0) then
vtlio.grant_valid := msti.r_valid;
else
vtlio.grant_valid := '0';
end if;
vtlio.grant_bits_addr_beat := r.rd_addr(5 downto 4);
vtlio.grant_bits_client_xact_id := r.rd_xact_id;
vtlio.grant_bits_g_type := r.rd_g_type;
vtlio.grant_bits_data := msti.r_data;
elsif r.wstate = writting then
vtlio.grant_valid := msti.w_ready;
vtlio.grant_bits_addr_beat := r.wr_addr(5 downto 4);
vtlio.grant_bits_client_xact_id := r.wr_xact_id;
vtlio.grant_bits_g_type := r.wr_g_type;
vtlio.grant_bits_data := (others => '0');
end if;
rin <= v;
tlio <= vtlio;
msto <= vmsto;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.rstate <= rwait_acq;
r.wstate <= wwait_acq;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 6eee006f0d1b142c15226c8ba3c91578 | 0.525543 | 3.497288 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/crcgentx.vhd | 4 | 16,071 | -------------------------------------------------------------------------------
-- crcgentx - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : crcgentx.vhd
-- Version : v4.00.a
-- Description : This module does an 4-bit parallel CRC generation.
-- The polynomial is that specified for IEEE 802.3 (ethernet)
-- LANs and other standards.
--
-- I. Functionality:
-- 1. The module does an 4-bit parallel CRC generation.
-- 2. The module provides a synchronous 4-bit per clock load and
-- unload function.
-- 3. The polynomial is that specified for 802.3 LANs and other
-- standards.
-- The polynomial computed is:
-- G(x)=X**32+X**26+X**23+X**22+X**16+X**12+X**11+X**10+X**8
-- +X**7+X**5+X**4+X** >2+X+1
--
-- II. Module I/O
-- Inputs: Clk, Clken, RESET, LOAD, COMPUTE, DATA_IN[3:0]
-- outputs: CRC_OK, DATA_OUT[3:0], CRC[31:0]
--
-- III.Truth Table:
--
-- Clken RESET COMPUTE LOAD | DATA_OUT
-- ------------------------------------------
-- 0 X X X | No change
-- 1 0 0 0 | No change
-- 1 1 X X | 0xFFFF (all ones)
-- 1 0 X 1 | load and shift 1 nibble of crc
-- 1 0 1 0 | Compute CRC
--
-- 0 0 1 1 | unload 4 byte crc
-- NOT IMPLEMENTED)
--
-- Loading and unloading of the 32-bit CRC register is done one
-- nibble at a time by asserting LOAD and Clken. The Data on
-- data_in is shifted into the the LSB of the CRC register. The
-- MSB of the CRC register is available on data_out.
--
-- Signals ending in _n are active low.
--
-- Copyright 1997 VAutomation Inc. Nashua NH USA (603) 882-2282.
-- Modification for 4 Bit done by Ronald Hecht @ Xilinx Inc.
-- This software is provided AS-IS and free of charge with the restriction that
-- this copyright notice remain in all copies of the Source Code at all times.
-- Visit HTTP://www.vautomation.com for more information on our cores.
-------------------------------------------------------------------------------
-- We add a nibble shift register into this module.
-- This module contains two parts.
--
-- 1. parallel_crc function which is a function will calculate the crc value.
-- 2. nibShitReg is a nibble shift register which has two operations
-- when DataEn goes high it will act as a normal register,
-- when OutEn goes high it will stop load new Data and shift out current
-- register Data by nibbles.
--
-- Some specification on module and port
--
-- 1. For nibShiftReg, give initial value to all zeros. This is because the initial
-- value for parallel_crc need to be all ones. Because we put a not on both
-- side of nibShiftReg, so we need to set it's value to all zeros at the
-- beginning.
-- 2. Don't shift the nibShiftReg at the first OutEn clock cycle, because the
-- first nibble is already there.
--
-- THE INTERFACE REQUIREMENTS OF THIS MODULE
--
-- Rst reset everything to initial value. We must give this reset
-- before we use crc module, otherwise the result will incorrect.
-- dataClk For use with mactx module, it will be 2.5 MHZ.
-- Data Input Data from other module in nibbles.
-- DataEn Enable crcgenrx. Make sure your enable and first Data can be
-- captured at the beginning of Data stream.
-- crcOk At the end of Data stream, this will go high if the crc is
-- correct.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- xemac.vhd
-- \
-- \-- axi_ipif_interface.vhd
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ ethernetlite_v3_0_dmem_v2.edn
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- ethernetlite_v3_0_dmem_v2.edn
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clke -- Clock enable
-- Data -- Data in
-- DataEn -- Data valid
-- OutEn -- Dataout enable
-- CrcNibs -- CRC nibble out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcgentx is
port
(
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic;
Data : in std_logic_vector(3 downto 0);
DataEn : in std_logic;
OutEn : in std_logic; -- NSR shift out enable
CrcNibs : out std_logic_vector(3 downto 0)
);
end crcgentx;
architecture arch1 of crcgentx is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of arch1 : architecture is "yes";
constant CRC_REMAINDER : std_logic_vector(31 downto 0) :=
"11000111000001001101110101111011"; -- 0xC704DD7B
function parallel_crc (crc_in : std_logic_vector(31 downto 0);
data_in : std_logic_vector(3 downto 0)
) return std_logic_vector is
variable c, crc_out : std_logic_vector(31 downto 0);
variable x : std_logic_vector (31 downto 28);
variable d : std_logic_vector (3 downto 0);
begin
-- Because the equations are long I am keeping the name of the incoming
-- CRC and the XOR vector short.
c := crc_in;
d := data_in;
-- the first thing that a parallel CRC needs to do is to develop the
-- vector formed by XORing the input vector by the current CRC. This
-- vector is then used during the CRC calculation.
x := (c(31) xor d(3)) & (c(30) xor d(2)) &
(c(29) xor d(1)) & (c(28) xor d(0));
-- The parellel CRC is a function of the X vector and the current CRC.
crc_out :=
(c(27) ) &
(c(26) ) &
(c(25) xor x(31) ) &
(c(24) xor x(30) ) &
(c(23) xor x(29) ) &
(c(22) xor x(31) xor x(28) ) &
(c(21) xor x(31) xor x(30) ) &
(c(20) xor x(30) xor x(29) ) &
(c(19) xor x(29) xor x(28) ) &
(c(18) xor x(28) ) &
(c(17) ) &
(c(16) ) &
(c(15) xor x(31) ) &
(c(14) xor x(30) ) &
(c(13) xor x(29) ) &
(c(12) xor x(28) ) &
(c(11) xor x(31) ) &
(c(10) xor x(31) xor x(30) ) &
(c(9 ) xor x(31) xor x(30) xor x(29) ) &
(c(8 ) xor x(30) xor x(29) xor x(28) ) &
(c(7 ) xor x(31) xor x(29) xor x(28) ) &
(c(6 ) xor x(31) xor x(30) xor x(28) ) &
(c(5 ) xor x(30) xor x(29) ) &
(c(4 ) xor x(31) xor x(29) xor x(28) ) &
(c(3 ) xor x(31) xor x(30) xor x(28) ) &
(c(2 ) xor x(30) xor x(29) ) &
(c(1 ) xor x(31) xor x(29) xor x(28) ) &
(c(0 ) xor x(31) xor x(30) xor x(28) ) &
( x(31) xor x(30) xor x(29) ) &
( x(30) xor x(29) xor x(28) ) &
( x(29) xor x(28) ) &
( x(28) );
return(crc_out);
end parallel_crc;
---------------------------------------------------------
-- A function which can reverse the bit order
-- order -- BY ben 07/04
---------------------------------------------------------
function revBitOrder( arg : std_logic_vector) return std_logic_vector is -- By ben 07/04/2000
variable tmp : std_logic_vector(arg'range);
begin
lp0 : for i in arg'range loop
tmp(arg'high - i) := arg(i);
end loop lp0;
return tmp;
end revBitOrder;
signal regDataIn, regDataOut, crcFuncIn, crcFuncOut: std_logic_vector(31 downto 0);
signal data_transpose : std_logic_vector(3 downto 0);
signal shiftEnable : std_logic;
-- component crcnibshiftreg
-- port (
-- Clk : in std_logic;
-- Clken : in std_logic;
-- Rst : in std_logic;
-- din : in std_logic_vector(31 downto 0);
-- load : in std_logic;
-- shift : in std_logic;
-- dout : out std_logic_vector(31 downto 0)
-- );
-- end component;
begin ----------------------------------------------------------------------
-----------------------------------------------------------------------------
-- This nibble shift register act as a normal register when DataEn is
-- high. When shiftEnable goes high, this register will stop load Data
-- and begin to shift Data out in nibbles.
-- Rember to check the initial value of this register which should be
-- all '0', otherwise the initial value for parallel_crc will not be
-- all '1'. This is related with the functions we put on input and output
-- of this register.
-----------------------------------------------------------------------------
NSR : entity axi_ethernetlite_v3_0.crcnibshiftreg
port map
(
Clk => Clk,
Clken => Clken,
Rst => Rst,
Din => regDataIn,
Load => DataEn,
Shift => shiftEnable,
Dout => regDataOut
);
shiftEnable <= OutEn and not DataEn;
crcFuncOut <= parallel_crc(crcFuncIn,data_transpose);
---------------------------------------------------------------------------------
-- These two sets of functions at input/output are balanced and the synthesis
-- tool will optimize them. The purpose is to let the register have all the Data
-- in right order before shift them.
---------------------------------------------------------------------------------
regDataIn <= not revBitOrder(crcFuncOut);
crcFuncIn <= not revBitOrder(regDataOut);
CrcNibs <= regDataOut(3 downto 0);
data_transpose <= Data(0) & Data(1) & Data(2) & Data(3);
end arch1;
| gpl-3.0 | e7cefc2e31025316caf2d000052e83b8 | 0.453861 | 4.27193 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm_core.vhd | 4 | 150,181 | -------------------------------------------------------------------------------
-- mdm_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm_core.vhd
-- jtag_control.vhd
-- arbiter.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2003-02-13 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity MDM_Core is
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer
);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG Signals
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM_Core;
library IEEE;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
architecture IMP of MDM_CORE is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant C_DRCK_FREQ_HZ : integer := 30000000;
constant C_CLOCK_BITS : integer := log2(C_S_AXI_ACLK_FREQ_HZ / C_DRCK_FREQ_HZ);
component JTAG_CONTROL
generic (
C_MB_DBG_PORTS : integer;
C_USE_CONFIG_RESET : integer;
C_DBG_REG_ACCESS : integer;
C_DBG_MEM_ACCESS : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_TRACE_OUTPUT : integer;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
Clk : in std_logic;
Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- Debug Register Access signals
DbgReg_Access_Lock : in std_logic;
DbgReg_Force_Lock : in std_logic;
DbgReg_Unlocked : in std_logic;
JTAG_Access_Lock : out std_logic;
JTAG_Force_Lock : out std_logic;
JTAG_AXIS_Overrun : in std_logic;
JTAG_Clear_Overrun : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- Bus Master signals
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 7);
Dbg_Capture : out std_logic;
Dbg_Shift : out std_logic;
Dbg_Update : out std_logic;
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
Trace_Clk : in std_logic;
Trace_Reset : in std_logic;
Trace_Test_Pattern : out std_logic_vector(0 to 3);
Trace_Test_Start : out std_logic;
Trace_Test_Stop : out std_logic;
Trace_Test_Timed : out std_logic;
Trace_Delay : out std_logic_vector(0 to 7);
Trace_Stopped : out std_logic
);
end component JTAG_CONTROL;
component Arbiter is
generic (
Size : natural;
Size_Log2 : natural);
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Requests : in std_logic_vector(Size-1 downto 0);
Granted : out std_logic_vector(Size-1 downto 0);
Valid_Sel : out std_logic;
Selected : out std_logic_vector(Size_Log2-1 downto 0)
);
end component Arbiter;
-- Returns the minimum value of the two parameters
function IntMin (a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
signal config_reset_i : std_logic;
signal clear_Ext_BRK : std_logic;
signal sel_n_reset : std_logic;
signal shift_n_reset : std_logic;
signal enable_interrupts : std_logic;
signal read_RX_FIFO : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal tx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal write_TX_FIFO : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal xfer_Ack : std_logic;
signal mdm_Dbus_i : std_logic_vector(0 to 31); -- Check!
signal mdm_CS : std_logic; -- Valid address in a address phase
signal mdm_CS_1 : std_logic; -- Active as long as mdm_CS is active
signal mdm_CS_2 : std_logic;
signal mdm_CS_3 : std_logic;
signal valid_access : std_logic; -- Active during the address phase (2 clock cycles)
signal valid_access_1 : std_logic; -- Will be a 1 clock delayed valid_access signal
signal valid_access_2 : std_logic; -- Active only 1 clock cycle
signal reading : std_logic; -- Valid reading access
signal valid_access_2_reading : std_logic; -- signal to drive out data bus on a read access
signal sl_rdDAck_i : std_logic;
signal sl_wrDAck_i : std_logic;
signal TDI : std_logic;
signal RESET : std_logic;
signal SHIFT : std_logic;
signal CAPTURE : std_logic;
signal TDO : std_logic;
signal mb_debug_enabled_i : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal Dbg_Clk : std_logic;
signal Dbg_TDI : std_logic;
signal Dbg_TDO : std_logic;
signal Dbg_Reg_En : std_logic_vector(0 to 7);
signal Dbg_Capture : std_logic;
signal Dbg_Shift : std_logic;
signal Dbg_Update : std_logic;
signal Debug_SYS_Rst_i : std_logic;
signal Debug_Rst_i : std_logic;
subtype Reg_En_TYPE is std_logic_vector(0 to 7);
type Reg_EN_ARRAY is array(0 to 31) of Reg_En_TYPE;
signal Dbg_TDO_I : std_logic_vector(0 to 31);
signal Dbg_Reg_En_I : Reg_EN_ARRAY;
signal Dbg_Rst_I : std_logic_vector(0 to 31);
signal Dbg_TrClk : std_logic;
signal Dbg_TrReady : std_logic_vector(0 to 31);
signal PORT_Selector : std_logic_vector(3 downto 0) := (others => '0');
signal PORT_Selector_1 : std_logic_vector(3 downto 0) := (others => '0');
signal TDI_Shifter : std_logic_vector(3 downto 0) := (others => '0');
signal Sl_rdDBus_int : std_logic_vector(0 to 31);
signal bus_clk : std_logic;
signal bus_rst : std_logic;
signal uart_ip2bus_rdack : std_logic;
signal uart_ip2bus_wrack : std_logic;
signal uart_ip2bus_error : std_logic;
signal uart_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_ip2bus_rdack : std_logic;
signal dbgreg_ip2bus_wrack : std_logic;
signal dbgreg_ip2bus_error : std_logic;
signal dbgreg_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_access_lock : std_logic;
signal dbgreg_force_lock : std_logic;
signal dbgreg_unlocked : std_logic;
signal jtag_access_lock : std_logic;
signal jtag_force_lock : std_logic;
signal jtag_axis_overrun : std_logic;
signal jtag_clear_overrun : std_logic;
-- Full frame synchronization packet
constant C_FF_SYNC_PACKET : std_logic_vector(31 downto 0) := (31 => '0', others => '1');
signal trace_clk_i : std_logic;
signal trace_reset : std_logic;
signal trace_word : std_logic_vector(31 downto 0);
signal trace_index : std_logic_vector(4 downto 0);
signal trace_trdata : std_logic_vector(35 downto 0);
signal trace_valid : std_logic;
signal trace_last_word : std_logic;
signal trace_started : std_logic;
signal trace_ready : std_logic;
signal trace_trready : std_logic;
signal trace_count_last : std_logic;
signal trace_test_pattern : std_logic_vector(0 to 3);
signal trace_test_start : std_logic;
signal trace_test_stop : std_logic;
signal trace_test_timed : std_logic;
signal trace_delay : std_logic_vector(0 to 7);
signal trace_stopped : std_logic;
-----------------------------------------------------------------------------
-- Register mapping
-----------------------------------------------------------------------------
-- Magic string "01000010" + "00000000" + No of Jtag peripheral units "0010"
-- + MDM Version no "00000110"
--
-- MDM Versions table:
-- 0,1,2,3: Not used
-- 4: opb_mdm v3
-- 5: mdm v1
-- 6: mdm v2
constant New_MDM_Config_Word : std_logic_vector(31 downto 0) :=
"01000010000000000000001000000110";
signal Config_Reg : std_logic_vector(31 downto 0) := New_MDM_Config_Word;
signal MDM_SEL : std_logic;
signal Old_MDM_DRCK : std_logic;
signal Old_MDM_TDI : std_logic;
signal Old_MDM_TDO : std_logic;
signal Old_MDM_SEL : std_logic;
signal Old_MDM_SEL_Mux : std_logic;
signal Old_MDM_SHIFT : std_logic;
signal Old_MDM_UPDATE : std_logic;
signal Old_MDM_RESET : std_logic;
signal Old_MDM_CAPTURE : std_logic;
signal JTAG_Dec_Sel : std_logic_vector(15 downto 0);
begin -- architecture IMP
config_reset_i <= Config_Reset when C_USE_CONFIG_RESET /= 0 else '0';
sel_n_reset <= not SEL or config_reset_i when Scan_Reset_Sel = '0' else
Scan_Reset;
shift_n_reset <= not SHIFT or config_reset_i when Scan_Reset_Sel = '0' else
Scan_Reset;
-----------------------------------------------------------------------------
-- TDI Shift Register
-----------------------------------------------------------------------------
-- Shifts data in when PORT 0 is selected. PORT 0 does not actually
-- exist externaly, but gets selected after asserting the SELECT signal.
-- The first value shifted in after SELECT goes high will select the new
-- PORT.
JTAG_Mux_Shifting : process (DRCK, sel_n_reset)
begin
if sel_n_reset = '1' then
TDI_Shifter <= (others => '0');
elsif DRCK'event and DRCK = '1' then
if MDM_SEL = '1' and SHIFT = '1' then
TDI_Shifter <= TDI & TDI_Shifter(3 downto 1);
end if;
end if;
end process JTAG_Mux_Shifting;
-----------------------------------------------------------------------------
-- PORT Selector Register
-----------------------------------------------------------------------------
-- Captures the shifted data when PORT 0 is selected. The data is captured at
-- the end of the BSCAN transaction (i.e. when the update signal goes low) to
-- prevent any other BSCAN signals to assert incorrectly.
-- Reference : XAPP 139
PORT_Selector_Updating : process (UPDATE, sel_n_reset)
begin
if sel_n_reset = '1' then
PORT_Selector <= (others => '0');
elsif Update'event and Update = '0' then
PORT_Selector <= Port_Selector_1;
end if;
end process PORT_Selector_Updating;
PORT_Selector_Updating_1 : process (UPDATE, sel_n_reset)
begin
if sel_n_reset = '1' then
PORT_Selector_1 <= (others => '0');
elsif Update'event and Update = '1' then
if MDM_SEL = '1' then
PORT_Selector_1 <= TDI_Shifter;
end if;
end if;
end process PORT_Selector_Updating_1;
-----------------------------------------------------------------------------
-- Configuration register
-----------------------------------------------------------------------------
-- TODO Can be replaced by SRLs
Config_Shifting : process (DRCK, shift_n_reset)
begin
if shift_n_reset = '1' then
Config_Reg <= New_MDM_Config_Word;
elsif DRCK'event and DRCK = '1' then -- rising clock edge
Config_Reg <= '0' & Config_Reg(31 downto 1);
end if;
end process Config_Shifting;
-----------------------------------------------------------------------------
-- Muxing and demuxing of JTAG Bscan User 1/2/3/4 signals
--
-- This block enables the older MDM/JTAG to co-exist with the newer
-- JTAG multiplexer block
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- TDO Mux
-----------------------------------------------------------------------------
with PORT_Selector select
TDO <=
Config_Reg(0) when "0000",
Old_MDM_TDO when "0001",
Ext_JTAG_TDO when "0010",
'1' when others;
-----------------------------------------------------------------------------
-- SELECT Decoder
-----------------------------------------------------------------------------
MDM_SEL <= SEL when PORT_Selector = "0000" else '0';
Old_MDM_SEL_Mux <= SEL when PORT_Selector = "0001" else '0';
Ext_JTAG_SEL <= SEL when PORT_Selector = "0010" else '0';
-----------------------------------------------------------------------------
-- Old MDM signals
-----------------------------------------------------------------------------
Old_MDM_DRCK <= DRCK;
Old_MDM_TDI <= TDI;
Old_MDM_CAPTURE <= CAPTURE;
Old_MDM_SHIFT <= SHIFT;
Old_MDM_UPDATE <= UPDATE;
Old_MDM_RESET <= RESET;
-----------------------------------------------------------------------------
-- External JTAG signals
-----------------------------------------------------------------------------
Ext_JTAG_DRCK <= DRCK;
Ext_JTAG_TDI <= TDI;
Ext_JTAG_CAPTURE <= CAPTURE;
Ext_JTAG_SHIFT <= SHIFT;
Ext_JTAG_UPDATE <= UPDATE;
Ext_JTAG_RESET <= RESET;
-----------------------------------------------------------------------------
-- AXI bus interface
-----------------------------------------------------------------------------
ip2bus_rdack <= uart_ip2bus_rdack or dbgreg_ip2bus_rdack;
ip2bus_wrack <= uart_ip2bus_wrack or dbgreg_ip2bus_wrack;
ip2bus_error <= uart_ip2bus_error or dbgreg_ip2bus_error;
ip2bus_data <= uart_ip2bus_data or dbgreg_ip2bus_data;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
bus_clk <= bus2ip_clk;
bus_rst <= not bus2ip_resetn;
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
bus_clk <= '0';
bus_rst <= '0';
end generate No_AXI_IPIF;
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
Use_Uart : if (C_USE_UART = 1) generate
-- Read Only
signal status_Reg : std_logic_vector(7 downto 0);
-- bit 4 enable_interrupts
-- bit 3 tx_Buffer_Full
-- bit 2 tx_Buffer_Empty
-- bit 1 rx_Buffer_Full
-- bit 0 rx_Data_Present
-- Write Only
-- Control Register
-- bit 7-5 Dont'Care
-- bit 4 enable_interrupts
-- bit 3 Dont'Care
-- bit 2 Clear Ext BRK signal
-- bit 1 Reset_RX_FIFO
-- bit 0 Reset_TX_FIFO
signal tx_Buffer_Empty_Pre : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
uart_ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
uart_ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
uart_ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
---------------------------------------------------------------------------
-- Status register
---------------------------------------------------------------------------
status_Reg(0) <= rx_Data_Present;
status_Reg(1) <= rx_Buffer_Full;
status_Reg(2) <= tx_Buffer_Empty;
status_Reg(3) <= tx_Buffer_Full;
status_Reg(4) <= enable_interrupts;
status_Reg(7 downto 5) <= "000";
---------------------------------------------------------------------------
-- Control Register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '1';
reset_TX_FIFO <= '1';
elsif (bus2ip_wrce(3) = '1') then -- Control Register is reg 3
enable_interrupts <= bus2ip_data(4); -- Bit 4 in control reg
clear_Ext_BRK <= bus2ip_data(2); -- Bit 2 in control reg
reset_RX_FIFO <= bus2ip_data(1); -- Bit 1 in control reg
reset_TX_FIFO <= bus2ip_data(0); -- Bit 0 in control reg
else
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '0';
reset_TX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin
uart_ip2bus_data <= (others => '0');
if (bus2ip_rdce(2) = '1') then -- Status register is reg 2
uart_ip2bus_data(status_reg'length-1 downto 0) <= status_reg;
elsif (bus2ip_rdce(0) = '1') then -- RX FIFO is reg 0
uart_ip2bus_data(C_UART_WIDTH-1 downto 0) <= rx_Data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Write bus interface
---------------------------------------------------------------------------
tx_Data <= bus2ip_data(C_UART_WIDTH-1 downto 0);
---------------------------------------------------------------------------
-- Read and write pulses to the FIFOs
---------------------------------------------------------------------------
write_TX_FIFO <= bus2ip_wrce(1); -- TX FIFO is reg 1
read_RX_FIFO <= bus2ip_rdce(0); -- RX FIFO is reg 0
-- Sample the tx_Buffer_Empty signal in order to detect a rising edge
TX_Buffer_Empty_FDRE : FDRE
port map (
Q => tx_Buffer_Empty_Pre,
C => bus_clk,
CE => '1',
D => tx_Buffer_Empty,
R => write_TX_FIFO);
---------------------------------------------------------------------------
-- Interrupt handling
---------------------------------------------------------------------------
Interrupt <= enable_interrupts and ( rx_Data_Present or
( tx_Buffer_Empty and
not tx_Buffer_Empty_Pre ) );
end generate Use_UART;
No_UART : if (C_USE_UART = 0) generate
begin
uart_ip2bus_rdack <= '0';
uart_ip2bus_wrack <= '0';
uart_ip2bus_error <= '0';
uart_ip2bus_data <= (others => '0');
Interrupt <= '0';
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
tx_Data <= (others => '0');
write_TX_FIFO <= '0';
read_RX_FIFO <= '0';
end generate No_UART;
-----------------------------------------------------------------------------
-- Debug Register Access
-----------------------------------------------------------------------------
Use_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 1) generate
type state_type is
(idle, select_dr, capture_dr, shift_dr, exit1, pause, exit2, update_dr, cmd_done, data_done);
signal bit_size : std_logic_vector(8 downto 0);
signal cmd_val : std_logic_vector(7 downto 0);
signal type_lock : std_logic_vector(1 downto 0);
signal use_mdm : std_logic;
signal reg_data : std_logic_vector(31 downto 0);
signal bit_cnt : std_logic_vector(0 to 8);
signal clk_cnt : std_logic_vector(0 to C_CLOCK_BITS / 2);
signal clk_fall : boolean;
signal clk_rise : boolean;
signal shifting : boolean;
signal data_shift : boolean;
signal direction : std_logic;
signal rd_wr_n : boolean;
signal rdack_data : std_logic;
signal selected : std_logic := '0';
signal shift_index : std_logic_vector(0 to 4);
signal state : state_type;
signal unlocked : boolean;
signal wrack_data : std_logic;
signal dbgreg_TDI : std_logic;
signal dbgreg_RESET : std_logic;
signal dbgreg_SHIFT : std_logic;
signal dbgreg_CAPTURE : std_logic;
signal dbgreg_SEL : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
dbgreg_ip2bus_rdack <= bus2ip_rdce(4) or rdack_data;
dbgreg_ip2bus_wrack <= bus2ip_wrce(4) or bus2ip_wrce(6) or wrack_data;
dbgreg_ip2bus_error <= (bus2ip_rdce(5) or bus2ip_wrce(5)) and not dbgreg_access_lock;
---------------------------------------------------------------------------
-- Control register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
use_mdm <= '0';
type_lock <= (others => '0');
cmd_val <= (others => '0');
bit_size <= (others => '0');
elsif (bus2ip_wrce(4) = '1') and unlocked then -- Control Register is reg 4
type_lock <= bus2ip_data(19 downto 18);
use_mdm <= bus2ip_data(17);
cmd_val <= bus2ip_data(16 downto 9);
bit_size <= bus2ip_data(8 downto 0);
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Data register and TAP state machine
---------------------------------------------------------------------------
DATA_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
reg_data <= (others => '0');
rdack_data <= '0';
wrack_data <= '0';
state <= idle;
shifting <= false;
data_shift <= false;
direction <= '1';
rd_wr_n <= false;
clk_rise <= false;
clk_fall <= false;
clk_cnt <= (others => '0');
bit_cnt <= "000000111";
shift_index <= "00000";
dbgreg_TDI <= '0';
dbgreg_RESET <= '0';
dbgreg_SHIFT <= '0';
dbgreg_CAPTURE <= '0';
dbgreg_SEL <= '0';
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
selected <= '0';
else
rdack_data <= '0';
wrack_data <= '0';
if unlocked and dbgreg_access_lock = '1' and not shifting then
if bus2ip_wrce(5) = '1' then
reg_data <= bus2ip_data;
shifting <= true;
rd_wr_n <= false;
end if;
if bus2ip_rdce(5) = '1' then
shifting <= true;
rd_wr_n <= true;
end if;
end if;
if clk_rise then
case state is
when idle =>
-- Idle - Start when data access occurs
if shifting then
state <= select_dr;
end if;
bit_cnt <= "000000111";
shift_index <= "00000";
selected <= '0';
when select_dr =>
-- TAP state Select DR - Set SEL
state <= capture_dr;
dbgreg_SEL <= '1';
selected <= '1';
when capture_dr =>
-- TAP state Capture DR - Set CAPTURE and pulse DRCK
state <= shift_dr;
dbgreg_CAPTURE <= '1';
DbgReg_DRCK <= '1';
when shift_dr =>
-- TAP state Shift DR - Set SHIFT and pulse DRCK until done or pause
if bit_cnt = (bit_cnt'range => '0') then
state <= exit2; -- Shift done
elsif shift_index = (shift_index'range => direction) then
state <= exit1; -- Acknowledge and pause until next word
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
end if;
if data_shift then
dbgreg_TDI <= reg_data(to_integer(unsigned(shift_index)));
reg_data(to_integer(unsigned(shift_index))) <= Old_MDM_TDO;
else
dbgreg_TDI <= cmd_val(to_integer(unsigned(shift_index)));
end if;
dbgreg_CAPTURE <= '0';
dbgreg_SHIFT <= '1';
DbgReg_DRCK <= '1';
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
if direction = '1' then
shift_index <= std_logic_vector(unsigned(shift_index) + 1);
else
shift_index <= std_logic_vector(unsigned(shift_index) - 1);
end if;
when exit1 =>
-- TAP state Exit1 DR - End shift and go to pause
state <= pause;
shifting <= false;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when pause =>
-- TAP state Pause DR - Pause until new data access or abort
if dbgreg_access_lock = '0' then
state <= exit2; -- Abort shift
elsif shifting then
state <= shift_dr; -- Continue with next word
end if;
DbgReg_DRCK <= '0';
when exit2 =>
-- TAP state Exit2 DR - Delay before update
state <= update_dr;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when update_dr =>
-- TAP state Update DR - Pulse UPDATE and acknowledge data access
if data_shift then
state <= data_done;
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
else
state <= cmd_done;
end if;
DbgReg_UPDATE <= '1';
when cmd_done =>
-- Command phase done - Continue with data phase
state <= select_dr;
data_shift <= true;
bit_cnt <= bit_size;
if use_mdm = '1' then
shift_index <= (others => '0');
else
shift_index <= bit_size(shift_index'length - 1 downto 0);
end if;
direction <= use_mdm;
DbgReg_UPDATE <= '0';
when data_done =>
-- Data phase done - End shifting and go back to idle
state <= idle;
data_shift <= false;
shifting <= false;
direction <= '1';
DbgReg_UPDATE <= '0';
end case;
elsif clk_fall then
DbgReg_DRCK <= '0';
end if;
if clk_cnt(clk_cnt'left + 1 to clk_cnt'right) = (clk_cnt'left + 1 to clk_cnt'right => '0') then
clk_rise <= (clk_cnt(clk_cnt'left) = '0');
clk_fall <= (clk_cnt(clk_cnt'left) = '1');
else
clk_rise <= false;
clk_fall <= false;
end if;
clk_cnt <= std_logic_vector(unsigned(clk_cnt) - 1);
end if;
end if;
end process DATA_REG_DFF;
---------------------------------------------------------------------------
-- Lock register
---------------------------------------------------------------------------
LOCK_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
unlocked <= false;
elsif (bus2ip_wrce(6) = '1') then -- Lock Register is reg 6
unlocked <= (bus2ip_data(15 downto 0) = X"EBAB") and (not unlocked);
end if;
end if;
end process LOCK_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (bus2ip_rdce(4), rdack_data, dbgreg_access_lock, reg_data) is
begin
dbgreg_ip2bus_data <= (others => '0');
if (bus2ip_rdce(4) = '1') then -- Status register is reg 4
dbgreg_ip2bus_data(0) <= dbgreg_access_lock;
elsif rdack_data = '1' then -- Data register is reg 5
dbgreg_ip2bus_data <= reg_data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Access lock handling
---------------------------------------------------------------------------
Handle_Access_Lock : process (bus2ip_clk) is
variable jtag_access_lock_1 : std_logic;
variable jtag_force_lock_1 : std_logic;
variable jtag_clear_overrun_1 : std_logic;
variable jtag_busy_1 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of jtag_access_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_force_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_clear_overrun_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_busy_1 : variable is "TRUE";
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axis_overrun <= '0';
jtag_access_lock_1 := '0';
jtag_force_lock_1 := '0';
jtag_clear_overrun_1 := '0';
jtag_busy_1 := '0';
else
-- Unlock after last access for type "01"
if state = data_done and type_lock = "01" then
dbgreg_access_lock <= '0';
end if;
-- Write to Debug Access Control Register
if bus2ip_wrce(4) = '1' then
case bus2ip_data(19 downto 18) is
when "00" => -- Release lock to abort atomic sequence
dbgreg_access_lock <= '0';
when "01" | "10" => -- Lock before first access
if dbgreg_access_lock = '0' and jtag_busy_1 = '0' and jtag_access_lock_1 = '0' then
dbgreg_access_lock <= '1';
end if;
when "11" => -- Force access lock
dbgreg_access_lock <= '1';
dbgreg_force_lock <= '1';
-- coverage off
when others =>
null;
-- coverage on
end case;
else
dbgreg_force_lock <= '0';
end if;
jtag_access_lock_1 := JTAG_Access_Lock;
-- JTAG force lock
if jtag_force_lock_1 = '1' then
dbgreg_access_lock <= '0';
dbgreg_unlocked <= '1';
else
dbgreg_unlocked <= '0';
end if;
jtag_force_lock_1 := jtag_force_lock;
-- JTAG overrun detection
if selected = '1' and jtag_busy_1 = '1' then
jtag_axis_overrun <= '1';
elsif jtag_clear_overrun_1 = '1' then
jtag_axis_overrun <= '0';
end if;
jtag_clear_overrun_1 := jtag_clear_overrun;
jtag_busy_1 := jtag_busy;
end if;
end if;
end process;
DbgReg_Select <= selected;
Old_MDM_SEL <= dbgreg_SEL when selected = '1' else Old_MDM_SEL_Mux;
TDI <= dbgreg_TDI when selected = '1' else JTAG_TDI;
RESET <= dbgreg_RESET when selected = '1' else JTAG_RESET;
SHIFT <= dbgreg_SHIFT when selected = '1' else JTAG_SHIFT;
CAPTURE <= dbgreg_CAPTURE when selected = '1' else JTAG_CAPTURE;
JTAG_TDO <= '0' when selected = '1' else TDO;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 0) generate
begin
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
DbgReg_Select <= '0';
dbgreg_ip2bus_rdack <= '0';
dbgreg_ip2bus_wrack <= '0';
dbgreg_ip2bus_error <= '0';
dbgreg_ip2bus_data <= (others => '0');
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axis_overrun <= '0';
Old_MDM_SEL <= Old_MDM_SEL_Mux;
TDI <= JTAG_TDI;
RESET <= JTAG_RESET;
SHIFT <= JTAG_SHIFT;
CAPTURE <= JTAG_CAPTURE;
JTAG_TDO <= TDO;
end generate No_Dbg_Reg_Access;
-----------------------------------------------------------------------------
-- Trace: External Output, AXI Stream Output and AXI Master Output
-----------------------------------------------------------------------------
Use_Trace : if (C_TRACE_OUTPUT > 0) generate
type TrData_Type is array(0 to 31) of std_logic_vector(0 to 35);
signal Dbg_TrData : TrData_Type;
signal Dbg_TrValid : std_logic_vector(31 downto 0);
begin
More_Than_One_MB : if (C_MB_DBG_PORTS > 1) generate
constant C_LOG2_MB_DBG_PORTS : natural := log2(C_MB_DBG_PORTS);
signal index : std_logic_vector(C_LOG2_MB_DBG_PORTS-1 downto 0);
signal valid : std_logic;
signal idle : std_logic;
begin
Arbiter_i : Arbiter
generic map (
Size => C_MB_DBG_PORTS, -- [natural]
Size_Log2 => C_LOG2_MB_DBG_PORTS) -- [natural]
port map (
Clk => trace_clk_i, -- [in std_logic]
Reset => trace_reset, -- [in std_logic]
Enable => '0', -- [in std_logic]
Requests => Dbg_TrValid(C_MB_DBG_PORTS-1 downto 0), -- [in std_logic_vector(Size-1 downto 0)]
Granted => open, -- [out std_logic_vector(Size-1 downto 0)]
Valid_Sel => valid, -- [out std_logic]
Selected => index -- [out std_logic_vector(Size_Log2-1 downto 0)]
);
Arbiter_Keep: process (trace_clk_i) is
begin -- process Arbiter_Keep
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_index(C_LOG2_MB_DBG_PORTS-1 downto 0) <= (others => '0');
trace_valid <= '0';
idle <= '1';
else
if idle = '1' or trace_last_word = '1' then
trace_index(C_LOG2_MB_DBG_PORTS-1 downto 0) <= index;
trace_valid <= valid;
idle <= not valid;
end if;
end if;
end if;
end process Arbiter_Keep;
trace_index(4 downto C_LOG2_MB_DBG_PORTS) <= (others => '0');
trace_trdata <= Dbg_TrData(to_integer(unsigned(trace_index)));
Assign_Ready: process (trace_trready, trace_index) is
begin -- process Assign_Ready
Dbg_TrReady <= (others => '0');
Dbg_TrReady(to_integer(unsigned(trace_index))) <= trace_trready;
end process Assign_Ready;
end generate More_Than_One_MB;
Only_One_MB : if (C_MB_DBG_PORTS = 1) generate
begin
trace_index <= "00000";
trace_trdata <= Dbg_TrData(0);
trace_valid <= Dbg_TrValid(0);
Dbg_TrReady(0) <= trace_trready;
Dbg_TrReady(1 to 31) <= (others => '0');
end generate Only_One_MB;
No_MB : if (C_MB_DBG_PORTS = 0) generate
begin
trace_index <= "00000";
trace_trdata <= (others => '0');
trace_valid <= '0';
Dbg_TrReady <= (others => '0');
end generate No_MB;
Dbg_TrData(0) <= Dbg_TrData_0;
Dbg_TrData(1) <= Dbg_TrData_1;
Dbg_TrData(2) <= Dbg_TrData_2;
Dbg_TrData(3) <= Dbg_TrData_3;
Dbg_TrData(4) <= Dbg_TrData_4;
Dbg_TrData(5) <= Dbg_TrData_5;
Dbg_TrData(6) <= Dbg_TrData_6;
Dbg_TrData(7) <= Dbg_TrData_7;
Dbg_TrData(8) <= Dbg_TrData_8;
Dbg_TrData(9) <= Dbg_TrData_9;
Dbg_TrData(10) <= Dbg_TrData_10;
Dbg_TrData(11) <= Dbg_TrData_11;
Dbg_TrData(12) <= Dbg_TrData_12;
Dbg_TrData(13) <= Dbg_TrData_13;
Dbg_TrData(14) <= Dbg_TrData_14;
Dbg_TrData(15) <= Dbg_TrData_15;
Dbg_TrData(16) <= Dbg_TrData_16;
Dbg_TrData(17) <= Dbg_TrData_17;
Dbg_TrData(18) <= Dbg_TrData_18;
Dbg_TrData(19) <= Dbg_TrData_19;
Dbg_TrData(20) <= Dbg_TrData_20;
Dbg_TrData(21) <= Dbg_TrData_21;
Dbg_TrData(22) <= Dbg_TrData_22;
Dbg_TrData(23) <= Dbg_TrData_23;
Dbg_TrData(24) <= Dbg_TrData_24;
Dbg_TrData(25) <= Dbg_TrData_25;
Dbg_TrData(26) <= Dbg_TrData_26;
Dbg_TrData(27) <= Dbg_TrData_27;
Dbg_TrData(28) <= Dbg_TrData_28;
Dbg_TrData(29) <= Dbg_TrData_29;
Dbg_TrData(30) <= Dbg_TrData_30;
Dbg_TrData(31) <= Dbg_TrData_31;
Dbg_TrValid(0) <= Dbg_TrValid_0;
Dbg_TrValid(1) <= Dbg_TrValid_1;
Dbg_TrValid(2) <= Dbg_TrValid_2;
Dbg_TrValid(3) <= Dbg_TrValid_3;
Dbg_TrValid(4) <= Dbg_TrValid_4;
Dbg_TrValid(5) <= Dbg_TrValid_5;
Dbg_TrValid(6) <= Dbg_TrValid_6;
Dbg_TrValid(7) <= Dbg_TrValid_7;
Dbg_TrValid(8) <= Dbg_TrValid_8;
Dbg_TrValid(9) <= Dbg_TrValid_9;
Dbg_TrValid(10) <= Dbg_TrValid_10;
Dbg_TrValid(11) <= Dbg_TrValid_11;
Dbg_TrValid(12) <= Dbg_TrValid_12;
Dbg_TrValid(13) <= Dbg_TrValid_13;
Dbg_TrValid(14) <= Dbg_TrValid_14;
Dbg_TrValid(15) <= Dbg_TrValid_15;
Dbg_TrValid(16) <= Dbg_TrValid_16;
Dbg_TrValid(17) <= Dbg_TrValid_17;
Dbg_TrValid(18) <= Dbg_TrValid_18;
Dbg_TrValid(19) <= Dbg_TrValid_19;
Dbg_TrValid(20) <= Dbg_TrValid_20;
Dbg_TrValid(21) <= Dbg_TrValid_21;
Dbg_TrValid(22) <= Dbg_TrValid_22;
Dbg_TrValid(23) <= Dbg_TrValid_23;
Dbg_TrValid(24) <= Dbg_TrValid_24;
Dbg_TrValid(25) <= Dbg_TrValid_25;
Dbg_TrValid(26) <= Dbg_TrValid_26;
Dbg_TrValid(27) <= Dbg_TrValid_27;
Dbg_TrValid(28) <= Dbg_TrValid_28;
Dbg_TrValid(29) <= Dbg_TrValid_29;
Dbg_TrValid(30) <= Dbg_TrValid_30;
Dbg_TrValid(31) <= Dbg_TrValid_31;
end generate Use_Trace;
Use_Trace_External_AXI_Master : if (C_TRACE_OUTPUT = 1 or C_TRACE_OUTPUT = 3) generate
type ID_Type is array(boolean, integer range 1 to 4) of std_logic_vector(2 downto 0);
constant C_ID : ID_Type :=
(false => ("010", "001", "011", "100"), -- C_USE_BSCAN = 0
true => ("001", "001", "001", "001")); -- C_USE_BSCAN = 2
-- 16 x 32 bit LUTROM
type Mux_Select_Type is (Extra, Final, ID, D0, D1, D2, D3, S1, S2, S3);
type Mux_Select_Array_Type is array (3 downto 0) of Mux_Select_Type;
type Output_Select_Type is array(0 to 31) of Mux_Select_Array_Type;
constant output_select : Output_Select_Type := (
0 => (D2, D1, D0, ID),
1 => (D2, D1, D0, S3),
2 => (D1, D0, Extra, S3),
3 => (Final, D0, S3, S2),
4 => (Extra, S3, S2, S1), -- Only saved, block trready
5 => (D3, D2, D1, D0),
6 => (D3, D2, D1, D0),
7 => (Final, D1, D0, Extra),
8 => (D0, S3, S2, ID),
9 => (Extra, S3, S2, S1), -- Only saved, block trready
10 => (D3, D2, D1, D0),
11 => (Final, D2, D1, D0),
12 => (D1, D0, Extra, S3),
13 => (D1, D0, S3, S2),
14 => (D0, Extra, S3, S2),
15 => (Final, S3, S2, S1), -- Only saved, block trready
16 => (D2, D1, D0, ID),
17 => (D1, D0, Extra, S3),
18 => (D1, D0, S3, S2),
19 => (Final, Extra, S3, S2), -- Only saved, block trready
others => (D2, D1, D0, ID)
);
attribute rom_style : string;
attribute rom_style of output_select : constant is "distributed";
constant block_trready : std_logic_vector(0 to 31) := "00001000010000010001000000000000";
type Mux_Data_Select_Type is array(Mux_Select_Type) of std_logic_vector(7 downto 0);
signal dbg_trdata_mux : Mux_Data_Select_Type;
signal frame_word_index : std_logic_vector(0 to 4);
signal frame_word_first : std_logic;
signal frame_word_last : boolean;
signal frame_word_next_last : boolean;
signal output_select_data : Mux_Select_Array_Type;
signal block_trready_val : std_logic;
signal trace_data_0 : std_logic_vector(7 downto 0);
signal trace_data_1 : std_logic_vector(7 downto 0);
signal trace_data_2 : std_logic_vector(7 downto 0);
signal trace_data_3 : std_logic_vector(7 downto 0);
signal saved_extra : std_logic_vector(7 downto 0);
signal final_byte : std_logic_vector(7 downto 0);
signal saved_final : std_logic_vector(5 downto 0);
signal saved_trdata : std_logic_vector(31 downto 8);
signal trace_id : std_logic_vector(7 downto 0);
begin
output_select_data <= output_select(to_integer(unsigned(frame_word_index)));
block_trready_val <= block_trready(to_integer(unsigned(frame_word_index)));
dbg_trdata_mux <= (
ID => trace_id,
Extra => saved_extra,
Final => final_byte,
D0 => trace_trdata(7 downto 0),
D1 => trace_trdata(15 downto 8),
D2 => trace_trdata(25 downto 18),
D3 => trace_trdata(33 downto 26),
S1 => saved_trdata(15 downto 8),
S2 => saved_trdata(23 downto 16),
S3 => saved_trdata(31 downto 24)
);
trace_data_0 <= dbg_trdata_mux(output_select_data(0));
trace_data_1 <= dbg_trdata_mux(output_select_data(1));
trace_data_2 <= dbg_trdata_mux(output_select_data(2));
trace_data_3 <= dbg_trdata_mux(output_select_data(3));
final_byte <= trace_data_2(0) & trace_data_0(0) & saved_final;
Mux_Output: process (trace_clk_i) is
variable trace_data_0_lsb : std_logic;
begin -- process Mux_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_word <= C_FF_SYNC_PACKET;
saved_extra <= (others => '0');
saved_final <= (others => '0');
saved_trdata <= (others => '0');
frame_word_index <= (others => '0');
frame_word_first <= '0';
frame_word_last <= false;
trace_started <= '0';
trace_last_word <= '0';
else
if (trace_valid = '1' and trace_stopped = '0' and trace_count_last = '1') or (trace_started = '1') then
trace_last_word <= '0';
trace_started <= '1';
if trace_ready = '1' or trace_started = '0' then
if output_select_data(0) = ID then
trace_data_0_lsb := '1';
else
trace_data_0_lsb := '0';
end if;
trace_word(7 downto 0) <= trace_data_0(7 downto 1) & trace_data_0_lsb;
trace_word(15 downto 8) <= trace_data_1;
trace_word(23 downto 16) <= trace_data_2(7 downto 1) & '0';
trace_word(31 downto 24) <= trace_data_3;
if block_trready_val = '0' then
saved_extra <= trace_trdata(35 downto 34) & trace_trdata(17 downto 16) & saved_extra(7 downto 4);
end if;
saved_final <= trace_data_2(0) & trace_data_0(0) & saved_final(5 downto 2);
saved_trdata <= trace_trdata(33 downto 18) & trace_trdata(15 downto 8);
if frame_word_last then
frame_word_index <= (others => '0');
frame_word_first <= '1';
else
frame_word_index <= std_logic_vector(unsigned(frame_word_index) + 1);
frame_word_first <= '0';
end if;
if frame_word_next_last then
trace_last_word <= '1';
end if;
frame_word_last <= frame_word_next_last;
end if;
if trace_ready = '1' and frame_word_first = '1' then
trace_word <= C_FF_SYNC_PACKET;
frame_word_index <= (others => '0');
frame_word_first <= '0';
frame_word_last <= false;
trace_started <= '0';
end if;
else
trace_word <= C_FF_SYNC_PACKET;
saved_extra <= (others => '0');
saved_final <= (others => '0');
saved_trdata <= (others => '0');
frame_word_index <= (others => '0');
frame_word_first <= '0';
frame_word_last <= false;
trace_started <= '0';
trace_last_word <= '0';
end if;
end if;
end if;
end process Mux_Output;
frame_word_next_last <= frame_word_index = "10010"; -- 20 32-bit words per packet = 16 36-bit words
trace_id <= C_ID(C_USE_BSCAN = 2, C_JTAG_CHAIN) & trace_index;
trace_trready <=
(trace_valid and not trace_stopped and not trace_started) or -- first word
(trace_ready and trace_started and not block_trready_val and not frame_word_first); -- remaining words
end generate Use_Trace_External_AXI_Master;
Use_Trace_External : if (C_TRACE_OUTPUT = 1) generate
type pattern_select_type is (ZERO, IDLE, ONE, PAT_FE, SHIFT, PAT_55, PAT_AA);
type trig_type is array (natural range <>) of std_logic_vector(2 to 3);
signal pattern_sel : pattern_select_type := ZERO;
signal pattern : std_logic_vector(C_TRACE_DATA_WIDTH - 1 downto 0);
signal next_pattern : std_logic_vector(C_TRACE_DATA_WIDTH - 1 downto 0) := (others => '0');
signal delay_count : std_logic_vector(0 to 7) := (others => '0');
signal next_delay_count : std_logic_vector(0 to 7);
signal delay_count_zero : boolean;
signal sync_packet : std_logic := '0';
signal sync_count : std_logic_vector(0 to 4) := (others => '0');
signal testing : std_logic := '0';
signal test_ctl : std_logic := '1';
signal trace_clk_div2 : std_logic := '0';
signal trace_data_i : std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0) := (others => '0');
signal trace_ctl_i : std_logic := '1';
signal trace_ctl_o : std_logic := '1';
signal trace_ctl_next : std_logic;
signal trace_trig : trig_type(0 to 31);
signal trig_on : std_logic := '0';
signal trig_pending : std_logic := '0';
signal trig_counting : std_logic := '0';
signal trig_count : std_logic_vector(0 to 16) := (0 => '1', others => '0');
signal trig_count_init : std_logic_vector(0 to 16);
attribute dont_touch : string;
attribute dont_touch of trace_ctl_i : signal is "true"; -- Keep FF for internal use
attribute dont_touch of trace_ctl_o : signal is "true"; -- Keep FF for IOB insertion
begin
-- Generate test patterns
pattern(0) <= next_pattern(C_TRACE_DATA_WIDTH - 1) when pattern_sel = SHIFT else
'1' when pattern_sel = IDLE or
pattern_sel = ONE or
pattern_sel = PAT_55 else
'0';
Gen_Test_Pattern: for I in 1 to C_TRACE_DATA_WIDTH - 1 generate
begin
pattern(I) <= next_pattern(I-1) when (pattern_sel = SHIFT) else
'1' when (pattern_sel = ONE) or
(pattern_sel = PAT_FE) or
(pattern_sel = PAT_55 and (I mod 2) = 0) or
(pattern_sel = PAT_AA and (I mod 2) = 1) else
'0';
end generate Gen_Test_Pattern;
Pattern_DFF: process (trace_clk_i) is
type state_type is (IDLE, STARTING, WALKING_1, WALKING_0, PAT_AA, PAT_55, PAT_FF, PAT_00);
variable state : state_type := IDLE;
begin -- process Pattern_DFF
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
pattern_sel <= ZERO;
delay_count <= trace_delay;
testing <= '0';
test_ctl <= '1';
state := IDLE;
next_pattern <= (others => '0');
else
case state is
when IDLE =>
pattern_sel <= ZERO;
delay_count <= trace_delay;
testing <= '0';
test_ctl <= '1';
if trace_test_start = '1' then
state := STARTING;
end if;
when STARTING =>
pattern_sel <= ZERO;
delay_count <= trace_delay;
if trace_started = '0' and trace_count_last = '1' then
if trace_test_pattern(3) = '1' then -- Alternating FF/00
pattern_sel <= ONE;
state := PAT_FF;
elsif trace_test_pattern(2) = '1' then -- Alternating AA/55
pattern_sel <= PAT_55;
state := PAT_55;
elsif trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
end if;
testing <= '1';
test_ctl <= '0';
end if;
when PAT_FF =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(2) = '1' then -- Alternating AA/55
pattern_sel <= PAT_55;
state := PAT_55;
elsif trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= ZERO;
state := PAT_00;
end if;
when PAT_00 =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(2) = '1' then -- Alternating AA/55
pattern_sel <= PAT_55;
state := PAT_55;
elsif trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= ONE;
state := PAT_FF;
end if;
when PAT_55 =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= PAT_AA;
state := PAT_AA;
end if;
when PAT_AA =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= PAT_55;
state := PAT_55;
end if;
when WALKING_0 =>
delay_count <= next_delay_count;
pattern_sel <= SHIFT;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
pattern_sel <= IDLE;
if trace_test_pattern(0) = '1' then -- Walking 1s
state := WALKING_1;
else
test_ctl <= '1';
state := IDLE;
end if;
end if;
when WALKING_1 =>
delay_count <= next_delay_count;
pattern_sel <= SHIFT;
if delay_count_zero or trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
next_pattern <= pattern;
end if;
end if;
end process Pattern_DFF;
next_delay_count <= std_logic_vector(unsigned(delay_count) - 1);
delay_count_zero <= delay_count = (delay_count'range => '0') and trace_test_timed = '1';
-- Output data or test pattern according to width
Has_Full_Width: if C_TRACE_DATA_WIDTH = 32 generate
begin
Data_Output: process (trace_clk_i) is
begin -- process Data_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_data_i <= (others => '0');
trace_data_i(0) <= '1';
trace_ctl_i <= '1';
trace_ctl_o <= '1';
else
if testing = '0' then
trace_ctl_i <= trace_ctl_next;
trace_ctl_o <= trace_ctl_next;
trace_data_i <= trace_word;
if trace_ctl_next = '1' then
trace_data_i <= (others => '0');
trace_data_i(0) <= '1'; -- Indicates trace disable when TRACE_CTL = '1'
if trig_on = '1' and sync_packet = '0' then
trace_data_i(1 downto 0) <= "10"; -- Indicates trigger when TRACE_CTL = '1'
end if;
end if;
else
trace_ctl_i <= test_ctl;
trace_ctl_o <= test_ctl;
trace_data_i <= pattern(C_TRACE_DATA_WIDTH - 1 downto 0);
end if;
end if;
end if;
end process Data_Output;
trace_ready <= not testing;
trace_count_last <= '1';
end generate Has_Full_Width;
Not_Full_Width: if C_TRACE_DATA_WIDTH < 32 generate
constant C_COUNTER_WIDTH : integer := log2(32 / C_TRACE_DATA_WIDTH);
signal data_count : std_logic_vector(0 to C_COUNTER_WIDTH - 1) := (others => '0');
signal data_count_next : std_logic_vector(0 to C_COUNTER_WIDTH - 1);
signal last_word_keep : std_logic := '0';
signal last_word_next : std_logic := '0';
begin
Data_Output: process (trace_clk_i) is
variable data_index : integer range 0 to 32 / C_TRACE_DATA_WIDTH - 1;
begin -- process Data_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_data_i <= (others => '0');
trace_data_i(0) <= '1';
data_count <= (others => '0');
trace_ctl_i <= '1';
trace_ctl_o <= '1';
last_word_keep <= '0';
last_word_next <= '0';
else
if testing = '0' then
trace_ctl_i <= trace_ctl_next;
trace_ctl_o <= trace_ctl_next;
data_index := to_integer(unsigned(data_count));
trace_data_i <= trace_word(data_index * C_TRACE_DATA_WIDTH + C_TRACE_DATA_WIDTH - 1 downto
data_index * C_TRACE_DATA_WIDTH);
if trace_last_word = '1' then
last_word_keep <= '1';
end if;
if trace_count_last = '1' then
data_count <= (others => '0');
last_word_next <= last_word_keep;
last_word_keep <= '0';
else
data_count <= data_count_next;
end if;
if trace_ctl_next = '1' then
trace_data_i <= (others => '0');
trace_data_i(0) <= '1'; -- Indicates trace disable when TRACE_CTL = '1'
if trig_on = '1' and sync_packet = '0' then
trace_data_i(1 downto 0) <= "10"; -- Indicates trigger when TRACE_CTL = '1'
end if;
end if;
else
trace_ctl_i <= test_ctl;
trace_ctl_o <= test_ctl;
trace_data_i <= pattern(C_TRACE_DATA_WIDTH - 1 downto 0);
data_count <= (others => '0');
end if;
end if;
end if;
end process Data_Output;
data_count_next <= std_logic_vector(unsigned(data_count) + 1);
trace_count_last <= '1' when data_count = (data_count'range => '1') else '0';
trace_ready <= (not trace_ctl_i) and trace_count_last;
end generate Not_Full_Width;
trace_ctl_next <= not (trace_started or sync_packet);
-- Synchronize reset
Reset_DFF: process (trace_clk_i) is
variable sample : std_logic_vector(0 to 1) := "11";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
begin -- process Sync_Reset
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
trace_reset <= sample(1);
sample(1) := sample(0);
sample(0) := Debug_SYS_Rst_i or config_reset_i;
end if;
end process Reset_DFF;
-- Generate half frequency output clock
Use_PLL: if C_TRACE_CLK_OUT_PHASE /= 0 generate
constant C_CLKFBOUT_MULT : integer := (800000000 + C_TRACE_CLK_FREQ_HZ - 1000000) / C_TRACE_CLK_FREQ_HZ;
constant C_CLKIN_PERIOD : real := 1000000000.0 / real(C_TRACE_CLK_FREQ_HZ);
constant C_CLKOUT0_DIVIDE : integer := C_CLKFBOUT_MULT * 2;
constant C_CLKOUT0_PHASE : real := real(C_TRACE_CLK_OUT_PHASE);
signal trace_clk_o : std_logic;
signal trace_clk_fbin : std_logic;
signal trace_clk_fbout : std_logic;
begin
PLL_TRACE_CLK : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => C_CLKIN_PERIOD,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_PHASE => C_CLKOUT0_PHASE,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_PHASE => 0.000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_PHASE => 0.000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_PHASE => 0.000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_PHASE => 0.000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKOUT5_PHASE => 0.000,
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBOUT => trace_clk_fbout,
CLKOUT0 => trace_clk_div2,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
CLKFBIN => trace_clk_fbin,
CLKIN1 => trace_clk_i,
PWRDWN => '0',
RST => trace_reset
);
BUFG_TRACE_CLK_FB : BUFG
port map (
O => trace_clk_fbin,
I => trace_clk_fbout
);
BUFG_TRACE_CLK : BUFG
port map (
O => trace_clk_o,
I => trace_clk_div2
);
TRACE_CLK_OUT <= trace_clk_o;
end generate Use_PLL;
No_PLL: if C_TRACE_CLK_OUT_PHASE = 0 generate
signal trace_clk_div2 : std_logic := '0';
signal trace_clk_o : std_logic := '0';
attribute dont_touch : string;
attribute dont_touch of trace_clk_o : signal is "true"; -- Keep FF for IOB insertion
begin
TRACE_CLK_OUT_DFF: process (trace_clk_i) is
begin -- process TRACE_CLK_OUT_DFF
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
trace_clk_div2 <= not trace_clk_div2;
trace_clk_o <= trace_clk_div2;
end if;
end process TRACE_CLK_OUT_DFF;
TRACE_CLK_OUT <= trace_clk_o; -- Any clock delay, phase shift or buffering is done outside MDM
end generate No_PLL;
TRACE_CTL <= trace_ctl_o;
TRACE_DATA <= trace_data_i;
trace_clk_i <= TRACE_CLK; -- Any clock doubling from external port is done outside MDM
-- Generate synchronization packets
Sync_Gen: process (trace_clk_i) is
begin -- process Sync_Gen
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
sync_packet <= '0';
sync_count <= (others => '0');
else
if sync_count(0) = '1' then
sync_count <= (others => '0');
sync_packet <= '1';
elsif trace_last_word = '1' then
sync_count <= std_logic_vector(unsigned(sync_count) + 1);
end if;
if trace_started = '0' and sync_packet = '1' and trace_count_last = '1' then
sync_packet <= '0';
end if;
end if;
end if;
end process Sync_Gen;
-- Generate trigger
Tigger_Detect: process (trace_clk_i) is
variable sample : trig_type(0 to C_MB_DBG_PORTS - 1) := (others => (others => '0'));
variable sample_1 : trig_type(0 to C_MB_DBG_PORTS - 1) := (others => (others => '0'));
variable sample_2 : trig_type(0 to C_MB_DBG_PORTS - 1) := (others => (others => '0'));
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
attribute ASYNC_REG of sample_1 : variable is "TRUE";
begin -- process Tigger_Detect
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trig_on <= '0';
trig_pending <= '0';
trig_counting <= '0';
trig_count <= trig_count_init;
sample_2 := (others => (others => '0'));
sample_1 := (others => (others => '0'));
sample := (others => (others => '0'));
else
-- Sample and edge-detect triggers
for I in 0 to C_MB_DBG_PORTS - 1 loop
if sample_2(I)(2) = '0' and sample_1(I)(2) = '1' then
-- Trigger on trace stop, or start counting on trace stop
trig_pending <= trig_pending or trace_test_pattern(0);
trig_counting <= trig_counting or trace_test_pattern(1);
end if;
if sample_2(I)(3) = '0' and sample_1(I)(3) = '1' then
-- Trigger on trace start, or start counting on trace start
trig_pending <= trig_pending or trace_test_pattern(2);
trig_counting <= trig_counting or trace_test_pattern(3);
end if;
end loop;
sample_2 := sample_1;
sample_1 := sample;
sample := trace_trig(0 to C_MB_DBG_PORTS - 1);
-- Decrement trigger count
if trig_counting = '1' then
if trig_count(0) = '0' then
trig_count <= trig_count_init;
trig_counting <= '0';
trig_pending <= '1';
else
trig_count <= std_logic_vector(unsigned(trig_count) - 1);
end if;
else
trig_count <= trig_count_init;
end if;
-- Pending trigger output
if testing = '0' and trace_ctl_i = '1' and sync_packet = '0' and trace_count_last = '1' then
trig_on <= trig_pending;
trig_pending <= '0';
else
trig_on <= '0';
end if;
end if;
end if;
end process Tigger_Detect;
trig_count_init <= '1' & trace_delay & "00000000";
trace_trig(0) <= Dbg_Trig_In_0(2 to 3);
trace_trig(1) <= Dbg_Trig_In_1(2 to 3);
trace_trig(2) <= Dbg_Trig_In_2(2 to 3);
trace_trig(3) <= Dbg_Trig_In_3(2 to 3);
trace_trig(4) <= Dbg_Trig_In_4(2 to 3);
trace_trig(5) <= Dbg_Trig_In_5(2 to 3);
trace_trig(6) <= Dbg_Trig_In_6(2 to 3);
trace_trig(7) <= Dbg_Trig_In_7(2 to 3);
trace_trig(8) <= Dbg_Trig_In_8(2 to 3);
trace_trig(9) <= Dbg_Trig_In_9(2 to 3);
trace_trig(10) <= Dbg_Trig_In_10(2 to 3);
trace_trig(11) <= Dbg_Trig_In_11(2 to 3);
trace_trig(12) <= Dbg_Trig_In_12(2 to 3);
trace_trig(13) <= Dbg_Trig_In_13(2 to 3);
trace_trig(14) <= Dbg_Trig_In_14(2 to 3);
trace_trig(15) <= Dbg_Trig_In_15(2 to 3);
trace_trig(16) <= Dbg_Trig_In_16(2 to 3);
trace_trig(17) <= Dbg_Trig_In_17(2 to 3);
trace_trig(18) <= Dbg_Trig_In_18(2 to 3);
trace_trig(19) <= Dbg_Trig_In_19(2 to 3);
trace_trig(20) <= Dbg_Trig_In_20(2 to 3);
trace_trig(21) <= Dbg_Trig_In_21(2 to 3);
trace_trig(22) <= Dbg_Trig_In_22(2 to 3);
trace_trig(23) <= Dbg_Trig_In_23(2 to 3);
trace_trig(24) <= Dbg_Trig_In_24(2 to 3);
trace_trig(25) <= Dbg_Trig_In_25(2 to 3);
trace_trig(26) <= Dbg_Trig_In_26(2 to 3);
trace_trig(27) <= Dbg_Trig_In_27(2 to 3);
trace_trig(28) <= Dbg_Trig_In_28(2 to 3);
trace_trig(29) <= Dbg_Trig_In_29(2 to 3);
trace_trig(30) <= Dbg_Trig_In_30(2 to 3);
trace_trig(31) <= Dbg_Trig_In_31(2 to 3);
-- Unused
M_AXIS_TDATA <= (others => '0');
M_AXIS_TID <= (others => '0');
M_AXIS_TVALID <= '0';
Master_dwr_data <= (others => '0');
Master_dwr_start <= '0';
end generate Use_Trace_External;
Use_Trace_AXI_Stream : if (C_TRACE_OUTPUT = 2) generate
type ID_Type is array(boolean, integer range 1 to 4) of std_logic_vector(1 downto 0);
constant C_ID : ID_Type :=
(false => ("01", "00", "10", "11"), -- C_USE_BSCAN = 0
true => ("00", "00", "00", "00")); -- C_USE_BSCAN = 2
-- 12 x 32 bit LUTROM
type Mux_Select_Type is (Extra, D0, D1, D2, D3, S1, S2, S3);
type Mux_Select_Array_Type is array (3 downto 0) of Mux_Select_Type;
type Output_Select_Type is array(0 to 31) of Mux_Select_Array_Type;
constant output_select : Output_Select_Type := (
0 => (D3, D2, D1, D0),
1 => (D3, D2, D1, D0),
2 => (D2, D1, D0, Extra),
3 => (D2, D1, D0, S3),
4 => (D1, D0, Extra, S3),
5 => (D1, D0, S3, S2),
6 => (D0, Extra, S3, S2),
7 => (D0, S3, S2, S1),
8 => (Extra, S3, S2, S1), -- Only saved, block trready
9 => (D3, D2, D1, D0),
10 => (D3, D2, D1, D0),
11 => (D2, D1, D0, Extra),
12 => (D2, D1, D0, S3),
13 => (D1, D0, Extra, S3),
14 => (D1, D0, S3, S2),
15 => (D0, Extra, S3, S2),
16 => (D0, S3, S2, S1),
17 => (Extra, S3, S2, S1), -- Only saved, block trready
others => (Extra, Extra, Extra, Extra)
);
attribute rom_style : string;
attribute rom_style of output_select : constant is "distributed";
constant block_trready : std_logic_vector(0 to 31) := "00000000100000000100000000000000";
type Mux_Data_Select_Type is array(Mux_Select_Type) of std_logic_vector(7 downto 0);
signal dbg_trdata_mux : Mux_Data_Select_Type;
signal frame_word_index : std_logic_vector(0 to 4);
signal frame_word_first : std_logic;
signal output_select_data : Mux_Select_Array_Type;
signal block_trready_val : std_logic;
signal trace_data_0 : std_logic_vector(7 downto 0);
signal trace_data_1 : std_logic_vector(7 downto 0);
signal trace_data_2 : std_logic_vector(7 downto 0);
signal trace_data_3 : std_logic_vector(7 downto 0);
signal saved_extra : std_logic_vector(7 downto 0);
signal saved_trdata : std_logic_vector(31 downto 8);
signal delay_count : std_logic_vector(0 to 7);
signal delay_zero : std_logic;
signal trace_id : std_logic_vector(6 downto 0);
signal trace_tvalid : std_logic;
begin
output_select_data <= output_select(to_integer(unsigned(frame_word_index)));
block_trready_val <= block_trready(to_integer(unsigned(frame_word_index)));
dbg_trdata_mux <= (
Extra => saved_extra,
D0 => trace_trdata(7 downto 0),
D1 => trace_trdata(15 downto 8),
D2 => trace_trdata(25 downto 18),
D3 => trace_trdata(33 downto 26),
S1 => saved_trdata(15 downto 8),
S2 => saved_trdata(23 downto 16),
S3 => saved_trdata(31 downto 24)
);
trace_data_0 <= dbg_trdata_mux(output_select_data(0));
trace_data_1 <= dbg_trdata_mux(output_select_data(1));
trace_data_2 <= dbg_trdata_mux(output_select_data(2));
trace_data_3 <= dbg_trdata_mux(output_select_data(3));
Mux_Output: process (trace_clk_i) is
begin -- process Mux_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_word <= (others => '0');
saved_extra <= (others => '0');
saved_trdata <= (others => '0');
trace_started <= '0';
trace_last_word <= '0';
trace_tvalid <= '0';
frame_word_index <= (others => '0');
frame_word_first <= '0';
else
if (trace_valid = '1' or trace_started = '1') and (delay_zero = '1') then
trace_last_word <= '0';
trace_started <= '1';
trace_tvalid <= '1';
if trace_ready = '1' or trace_started = '0' then
trace_word(7 downto 0) <= trace_data_0;
trace_word(15 downto 8) <= trace_data_1;
trace_word(23 downto 16) <= trace_data_2;
trace_word(31 downto 24) <= trace_data_3;
saved_extra <= trace_trdata(35 downto 34) & trace_trdata(17 downto 16) & saved_extra(7 downto 4);
saved_trdata <= trace_trdata(33 downto 18) & trace_trdata(15 downto 8);
if (frame_word_index = "10001") then -- 18 32-bit words per packet = 16 36-bit words
frame_word_index <= (others => '0');
trace_started <= '0';
frame_word_first <= '1';
else
frame_word_index <= std_logic_vector(unsigned(frame_word_index) + 1);
frame_word_first <= '0';
end if;
if frame_word_index = "10000" then -- 18 32-bit words per packet = 16 36-bit words
trace_last_word <= '1';
end if;
end if;
if trace_ready = '1' and frame_word_first = '1' then
frame_word_first <= '0';
end if;
else
trace_tvalid <= '0';
frame_word_first <= '0';
end if;
end if;
end if;
end process Mux_Output;
Delay_Counter: process (trace_clk_i) is
begin -- process Delay_Counter
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
delay_count <= trace_delay;
delay_zero <= '1';
else
if trace_delay = (trace_delay'range => '0') then
delay_count <= trace_delay;
delay_zero <= '1';
elsif (trace_valid = '1' or trace_started = '1') and (delay_zero = '1') and
(trace_ready = '1' or trace_started = '0') then
delay_count <= trace_delay;
delay_zero <= '0';
elsif delay_count = (delay_count'range => '0') then
delay_zero <= '1';
else
delay_count <= std_logic_vector(unsigned(delay_count) - 1);
delay_zero <= '0';
end if;
end if;
end if;
end process Delay_Counter;
Trace_ID_Output: process (trace_clk_i) is
begin -- process Trace_ID_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_id <= (others => '0');
else
trace_id <= C_ID(C_USE_BSCAN = 2, C_JTAG_CHAIN) & trace_index;
end if;
end if;
end process Trace_ID_Output;
M_AXIS_TDATA <= trace_word;
M_AXIS_TVALID <= trace_tvalid;
M_AXIS_TID <= trace_id(C_M_AXIS_ID_WIDTH-1 downto 0);
trace_clk_i <= M_AXIS_ACLK;
trace_reset <= not M_AXIS_ARESETN;
trace_ready <= M_AXIS_TREADY;
trace_trready <=
(trace_valid and not trace_started and delay_zero) or -- first word
(trace_ready and trace_started and not block_trready_val and not frame_word_first and delay_zero); -- remaining
-- Unused
TRACE_CLK_OUT <= '0';
TRACE_CTL <= '1';
TRACE_DATA <= (others => '0');
Master_dwr_data <= (others => '0');
Master_dwr_start <= '0';
trace_count_last <= '0';
end generate Use_Trace_AXI_Stream;
Use_Trace_AXI_Master : if (C_TRACE_OUTPUT = 3) generate
begin
Master_dwr_data <= trace_word;
Master_dwr_start <= (trace_valid and not trace_stopped) or trace_started;
trace_clk_i <= M_AXI_ACLK;
trace_reset <= not M_AXI_ARESETN;
trace_ready <= Master_dwr_next;
trace_count_last <= '1';
-- Unused
M_AXIS_TDATA <= (others => '0');
M_AXIS_TID <= (others => '0');
M_AXIS_TVALID <= '0';
TRACE_CLK_OUT <= '0';
TRACE_CTL <= '1';
TRACE_DATA <= (others => '0');
end generate Use_Trace_AXI_Master;
No_Trace : if (C_TRACE_OUTPUT = 0) generate
begin
Dbg_TrReady <= (others => '0');
trace_clk_i <= '0';
trace_reset <= '0';
trace_word <= (others => '0');
trace_index <= (others => '0');
trace_trdata <= (others => '0');
trace_valid <= '0';
trace_last_word <= '0';
trace_ready <= '0';
trace_trready <= '0';
trace_started <= '0';
trace_count_last <= '0';
M_AXIS_TDATA <= (others => '0');
M_AXIS_TID <= (others => '0');
M_AXIS_TVALID <= '0';
TRACE_CLK_OUT <= '0';
TRACE_CTL <= '1';
TRACE_DATA <= (others => '0');
Master_dwr_data <= (others => '0');
Master_dwr_start <= '0';
end generate No_Trace;
Dbg_TrClk <= trace_clk_i;
---------------------------------------------------------------------------
-- Instantiating the receive and transmit modules
---------------------------------------------------------------------------
JTAG_CONTROL_I : JTAG_CONTROL
generic map (
C_MB_DBG_PORTS => C_MB_DBG_PORTS,
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET,
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS,
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER,
C_USE_UART => C_USE_UART,
C_UART_WIDTH => C_UART_WIDTH,
C_TRACE_OUTPUT => C_TRACE_OUTPUT,
C_EN_WIDTH => C_EN_WIDTH
)
port map (
Config_Reset => config_reset_i, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
Clk => bus_clk, -- [in std_logic]
Rst => bus_rst, -- [in std_logic]
Clear_Ext_BRK => clear_Ext_BRK, -- [in std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst_i, -- [out std_logic]
Debug_Rst => Debug_Rst_i, -- [out std_logic]
Read_RX_FIFO => read_RX_FIFO, -- [in std_logic]
Reset_RX_FIFO => reset_RX_FIFO, -- [in std_logic]
RX_Data => rx_Data, -- [out std_logic_vector(0 to 7)]
RX_Data_Present => rx_Data_Present, -- [out std_logic]
RX_Buffer_Full => rx_Buffer_Full, -- [out std_logic]
Write_TX_FIFO => write_TX_FIFO, -- [in std_logic]
Reset_TX_FIFO => reset_TX_FIFO, -- [in std_logic]
TX_Data => tx_Data, -- [in std_logic_vector(0 to 7)]
TX_Buffer_Full => tx_Buffer_Full, -- [out std_logic]
TX_Buffer_Empty => tx_Buffer_Empty, -- [out std_logic]
-- Debug Register Access signals
DbgReg_Access_Lock => dbgreg_access_lock, -- [in std_logic]
DbgReg_Force_Lock => dbgreg_force_lock, -- [in std_logic]
DbgReg_Unlocked => dbgreg_unlocked, -- [in std_logic]
JTAG_Access_Lock => jtag_access_lock, -- [out std_logic]
JTAG_Force_Lock => jtag_force_lock, -- [out std_logic]
JTAG_AXIS_Overrun => jtag_axis_overrun, -- [in std_logic]
JTAG_Clear_Overrun => jtag_clear_overrun, -- [out std_logic]
-- MDM signals
TDI => Old_MDM_TDI, -- [in std_logic]
RESET => Old_MDM_RESET, -- [in std_logic]
UPDATE => Old_MDM_UPDATE, -- [in std_logic]
SHIFT => Old_MDM_SHIFT, -- [in std_logic]
CAPTURE => Old_MDM_CAPTURE, -- [in std_logic]
SEL => Old_MDM_SEL, -- [in std_logic]
DRCK => Old_MDM_DRCK, -- [in std_logic]
TDO => Old_MDM_TDO, -- [out std_logic]
-- AXI Master signals
M_AXI_ACLK => M_AXI_ACLK, -- [in std_logic]
M_AXI_ARESETn => M_AXI_ARESETn, -- [in std_logic]
Master_rd_start => Master_rd_start, -- [out std_logic]
Master_rd_addr => Master_rd_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_rd_len => Master_rd_len, -- [out std_logic_vector(4 downto 0)]
Master_rd_size => Master_rd_size, -- [out std_logic_vector(1 downto 0)]
Master_rd_excl => Master_rd_excl, -- [out std_logic]
Master_rd_idle => Master_rd_idle, -- [out std_logic]
Master_rd_resp => Master_rd_resp, -- [out std_logic_vector(1 downto 0)]
Master_wr_start => Master_wr_start, -- [out std_logic]
Master_wr_addr => Master_wr_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_wr_len => Master_wr_len, -- [out std_logic_vector(4 downto 0)]
Master_wr_size => Master_wr_size, -- [out std_logic_vector(1 downto 0)]
Master_wr_excl => Master_wr_excl, -- [out std_logic]
Master_wr_idle => Master_wr_idle, -- [out std_logic]
Master_wr_resp => Master_wr_resp, -- [out std_logic_vector(1 downto 0)]
Master_data_rd => Master_data_rd, -- [out std_logic]
Master_data_out => Master_data_out, -- [in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_exists => Master_data_exists, -- [in std_logic]
Master_data_wr => Master_data_wr, -- [out std_logic]
Master_data_in => Master_data_in, -- [out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_empty => Master_data_empty, -- [in std_logic]
Master_dwr_addr => Master_dwr_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_dwr_len => Master_dwr_len, -- [out std_logic_vector(4 downto 0)]
Master_dwr_done => Master_dwr_done, -- [in std_logic]
Master_dwr_resp => Master_dwr_resp, -- [in std_logic]
-- MicroBlaze Debug Signals
MB_Debug_Enabled => mb_debug_enabled_i, -- [out std_logic_vector(7 downto 0)]
Dbg_Clk => Dbg_Clk, -- [out std_logic]
Dbg_TDI => Dbg_TDI, -- [in std_logic]
Dbg_TDO => Dbg_TDO, -- [out std_logic]
Dbg_Reg_En => Dbg_Reg_En, -- [out std_logic_vector(0 to 7)]
Dbg_Capture => Dbg_Capture, -- [out std_logic]
Dbg_Shift => Dbg_Shift, -- [out std_logic]
Dbg_Update => Dbg_Update, -- [out std_logic]
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Ext_Trig_In => Ext_Trig_In, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => Ext_Trig_Ack_In, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => Ext_Trig_Out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => Ext_Trig_Ack_Out, -- [in std_logic_vector(0 to 3)]
Trace_Clk => trace_clk_i, -- [in std_logic]
Trace_Reset => trace_reset, -- [in std_logic]
Trace_Test_Pattern => trace_test_pattern, -- [out std_logic_vector(0 to 3)]
Trace_Test_Start => trace_test_start, -- [out std_logic]
Trace_Test_Stop => trace_test_stop, -- [out std_logic]
Trace_Test_Timed => trace_test_timed, -- [out std_logic]
Trace_Delay => trace_delay, -- [out std_logic_vector(0 to 7)]
Trace_Stopped => trace_stopped -- [out std_logic]
);
-----------------------------------------------------------------------------
-- Enables for each debug port
-----------------------------------------------------------------------------
Generate_Dbg_Port_Signals : process (mb_debug_enabled_i, Dbg_Reg_En,
Dbg_TDO_I, Debug_Rst_I)
variable dbg_tdo_or : std_logic;
begin -- process Generate_Dbg_Port_Signals
dbg_tdo_or := '0';
for I in 0 to C_EN_WIDTH-1 loop
if (mb_debug_enabled_i(I) = '1') then
Dbg_Reg_En_I(I) <= Dbg_Reg_En;
Dbg_Rst_I(I) <= Debug_Rst_i;
else
Dbg_Reg_En_I(I) <= (others => '0');
Dbg_Rst_I(I) <= '0';
end if;
dbg_tdo_or := dbg_tdo_or or Dbg_TDO_I(I);
end loop; -- I
for I in C_EN_WIDTH to 31 loop
Dbg_Reg_En_I(I) <= (others => '0');
Dbg_Rst_I(I) <= '0';
end loop; -- I
Dbg_TDO <= dbg_tdo_or;
end process Generate_Dbg_Port_Signals;
Debug_SYS_Rst <= Debug_SYS_Rst_i;
MB_Debug_Enabled <= mb_debug_enabled_i;
Dbg_Clk_0 <= Dbg_Clk;
Dbg_TDI_0 <= Dbg_TDI;
Dbg_Reg_En_0 <= Dbg_Reg_En_I(0);
Dbg_Capture_0 <= Dbg_Capture;
Dbg_Shift_0 <= Dbg_Shift;
Dbg_Update_0 <= Dbg_Update;
Dbg_Rst_0 <= Dbg_Rst_I(0);
Dbg_TDO_I(0) <= Dbg_TDO_0;
Dbg_TrClk_0 <= Dbg_TrClk;
Dbg_TrReady_0 <= Dbg_TrReady(0);
Dbg_Clk_1 <= Dbg_Clk;
Dbg_TDI_1 <= Dbg_TDI;
Dbg_Reg_En_1 <= Dbg_Reg_En_I(1);
Dbg_Capture_1 <= Dbg_Capture;
Dbg_Shift_1 <= Dbg_Shift;
Dbg_Update_1 <= Dbg_Update;
Dbg_Rst_1 <= Dbg_Rst_I(1);
Dbg_TDO_I(1) <= Dbg_TDO_1;
Dbg_TrClk_1 <= Dbg_TrClk;
Dbg_TrReady_1 <= Dbg_TrReady(1);
Dbg_Clk_2 <= Dbg_Clk;
Dbg_TDI_2 <= Dbg_TDI;
Dbg_Reg_En_2 <= Dbg_Reg_En_I(2);
Dbg_Capture_2 <= Dbg_Capture;
Dbg_Shift_2 <= Dbg_Shift;
Dbg_Update_2 <= Dbg_Update;
Dbg_Rst_2 <= Dbg_Rst_I(2);
Dbg_TDO_I(2) <= Dbg_TDO_2;
Dbg_TrClk_2 <= Dbg_TrClk;
Dbg_TrReady_2 <= Dbg_TrReady(2);
Dbg_Clk_3 <= Dbg_Clk;
Dbg_TDI_3 <= Dbg_TDI;
Dbg_Reg_En_3 <= Dbg_Reg_En_I(3);
Dbg_Capture_3 <= Dbg_Capture;
Dbg_Shift_3 <= Dbg_Shift;
Dbg_Update_3 <= Dbg_Update;
Dbg_Rst_3 <= Dbg_Rst_I(3);
Dbg_TDO_I(3) <= Dbg_TDO_3;
Dbg_TrClk_3 <= Dbg_TrClk;
Dbg_TrReady_3 <= Dbg_TrReady(3);
Dbg_Clk_4 <= Dbg_Clk;
Dbg_TDI_4 <= Dbg_TDI;
Dbg_Reg_En_4 <= Dbg_Reg_En_I(4);
Dbg_Capture_4 <= Dbg_Capture;
Dbg_Shift_4 <= Dbg_Shift;
Dbg_Update_4 <= Dbg_Update;
Dbg_Rst_4 <= Dbg_Rst_I(4);
Dbg_TDO_I(4) <= Dbg_TDO_4;
Dbg_TrClk_4 <= Dbg_TrClk;
Dbg_TrReady_4 <= Dbg_TrReady(4);
Dbg_Clk_5 <= Dbg_Clk;
Dbg_TDI_5 <= Dbg_TDI;
Dbg_Reg_En_5 <= Dbg_Reg_En_I(5);
Dbg_Capture_5 <= Dbg_Capture;
Dbg_Shift_5 <= Dbg_Shift;
Dbg_Update_5 <= Dbg_Update;
Dbg_Rst_5 <= Dbg_Rst_I(5);
Dbg_TDO_I(5) <= Dbg_TDO_5;
Dbg_TrClk_5 <= Dbg_TrClk;
Dbg_TrReady_5 <= Dbg_TrReady(5);
Dbg_Clk_6 <= Dbg_Clk;
Dbg_TDI_6 <= Dbg_TDI;
Dbg_Reg_En_6 <= Dbg_Reg_En_I(6);
Dbg_Capture_6 <= Dbg_Capture;
Dbg_Shift_6 <= Dbg_Shift;
Dbg_Update_6 <= Dbg_Update;
Dbg_Rst_6 <= Dbg_Rst_I(6);
Dbg_TDO_I(6) <= Dbg_TDO_6;
Dbg_TrClk_6 <= Dbg_TrClk;
Dbg_TrReady_6 <= Dbg_TrReady(6);
Dbg_Clk_7 <= Dbg_Clk;
Dbg_TDI_7 <= Dbg_TDI;
Dbg_Reg_En_7 <= Dbg_Reg_En_I(7);
Dbg_Capture_7 <= Dbg_Capture;
Dbg_Shift_7 <= Dbg_Shift;
Dbg_Update_7 <= Dbg_Update;
Dbg_Rst_7 <= Dbg_Rst_I(7);
Dbg_TDO_I(7) <= Dbg_TDO_7;
Dbg_TrClk_7 <= Dbg_TrClk;
Dbg_TrReady_7 <= Dbg_TrReady(7);
Dbg_Clk_8 <= Dbg_Clk;
Dbg_TDI_8 <= Dbg_TDI;
Dbg_Reg_En_8 <= Dbg_Reg_En_I(8);
Dbg_Capture_8 <= Dbg_Capture;
Dbg_Shift_8 <= Dbg_Shift;
Dbg_Update_8 <= Dbg_Update;
Dbg_Rst_8 <= Dbg_Rst_I(8);
Dbg_TDO_I(8) <= Dbg_TDO_8;
Dbg_TrClk_8 <= Dbg_TrClk;
Dbg_TrReady_8 <= Dbg_TrReady(8);
Dbg_Clk_9 <= Dbg_Clk;
Dbg_TDI_9 <= Dbg_TDI;
Dbg_Reg_En_9 <= Dbg_Reg_En_I(9);
Dbg_Capture_9 <= Dbg_Capture;
Dbg_Shift_9 <= Dbg_Shift;
Dbg_Update_9 <= Dbg_Update;
Dbg_Rst_9 <= Dbg_Rst_I(9);
Dbg_TDO_I(9) <= Dbg_TDO_9;
Dbg_TrClk_9 <= Dbg_TrClk;
Dbg_TrReady_9 <= Dbg_TrReady(9);
Dbg_Clk_10 <= Dbg_Clk;
Dbg_TDI_10 <= Dbg_TDI;
Dbg_Reg_En_10 <= Dbg_Reg_En_I(10);
Dbg_Capture_10 <= Dbg_Capture;
Dbg_Shift_10 <= Dbg_Shift;
Dbg_Update_10 <= Dbg_Update;
Dbg_Rst_10 <= Dbg_Rst_I(10);
Dbg_TDO_I(10) <= Dbg_TDO_10;
Dbg_TrClk_10 <= Dbg_TrClk;
Dbg_TrReady_10 <= Dbg_TrReady(10);
Dbg_Clk_11 <= Dbg_Clk;
Dbg_TDI_11 <= Dbg_TDI;
Dbg_Reg_En_11 <= Dbg_Reg_En_I(11);
Dbg_Capture_11 <= Dbg_Capture;
Dbg_Shift_11 <= Dbg_Shift;
Dbg_Update_11 <= Dbg_Update;
Dbg_Rst_11 <= Dbg_Rst_I(11);
Dbg_TDO_I(11) <= Dbg_TDO_11;
Dbg_TrClk_11 <= Dbg_TrClk;
Dbg_TrReady_11 <= Dbg_TrReady(11);
Dbg_Clk_12 <= Dbg_Clk;
Dbg_TDI_12 <= Dbg_TDI;
Dbg_Reg_En_12 <= Dbg_Reg_En_I(12);
Dbg_Capture_12 <= Dbg_Capture;
Dbg_Shift_12 <= Dbg_Shift;
Dbg_Update_12 <= Dbg_Update;
Dbg_Rst_12 <= Dbg_Rst_I(12);
Dbg_TDO_I(12) <= Dbg_TDO_12;
Dbg_TrClk_12 <= Dbg_TrClk;
Dbg_TrReady_12 <= Dbg_TrReady(12);
Dbg_Clk_13 <= Dbg_Clk;
Dbg_TDI_13 <= Dbg_TDI;
Dbg_Reg_En_13 <= Dbg_Reg_En_I(13);
Dbg_Capture_13 <= Dbg_Capture;
Dbg_Shift_13 <= Dbg_Shift;
Dbg_Update_13 <= Dbg_Update;
Dbg_Rst_13 <= Dbg_Rst_I(13);
Dbg_TDO_I(13) <= Dbg_TDO_13;
Dbg_TrClk_13 <= Dbg_TrClk;
Dbg_TrReady_13 <= Dbg_TrReady(13);
Dbg_Clk_14 <= Dbg_Clk;
Dbg_TDI_14 <= Dbg_TDI;
Dbg_Reg_En_14 <= Dbg_Reg_En_I(14);
Dbg_Capture_14 <= Dbg_Capture;
Dbg_Shift_14 <= Dbg_Shift;
Dbg_Update_14 <= Dbg_Update;
Dbg_Rst_14 <= Dbg_Rst_I(14);
Dbg_TDO_I(14) <= Dbg_TDO_14;
Dbg_TrClk_14 <= Dbg_TrClk;
Dbg_TrReady_14 <= Dbg_TrReady(14);
Dbg_Clk_15 <= Dbg_Clk;
Dbg_TDI_15 <= Dbg_TDI;
Dbg_Reg_En_15 <= Dbg_Reg_En_I(15);
Dbg_Capture_15 <= Dbg_Capture;
Dbg_Shift_15 <= Dbg_Shift;
Dbg_Update_15 <= Dbg_Update;
Dbg_Rst_15 <= Dbg_Rst_I(15);
Dbg_TDO_I(15) <= Dbg_TDO_15;
Dbg_TrClk_15 <= Dbg_TrClk;
Dbg_TrReady_15 <= Dbg_TrReady(15);
Dbg_Clk_16 <= Dbg_Clk;
Dbg_TDI_16 <= Dbg_TDI;
Dbg_Reg_En_16 <= Dbg_Reg_En_I(16);
Dbg_Capture_16 <= Dbg_Capture;
Dbg_Shift_16 <= Dbg_Shift;
Dbg_Update_16 <= Dbg_Update;
Dbg_Rst_16 <= Dbg_Rst_I(16);
Dbg_TDO_I(16) <= Dbg_TDO_16;
Dbg_TrClk_16 <= Dbg_TrClk;
Dbg_TrReady_16 <= Dbg_TrReady(16);
Dbg_Clk_17 <= Dbg_Clk;
Dbg_TDI_17 <= Dbg_TDI;
Dbg_Reg_En_17 <= Dbg_Reg_En_I(17);
Dbg_Capture_17 <= Dbg_Capture;
Dbg_Shift_17 <= Dbg_Shift;
Dbg_Update_17 <= Dbg_Update;
Dbg_Rst_17 <= Dbg_Rst_I(17);
Dbg_TDO_I(17) <= Dbg_TDO_17;
Dbg_TrClk_17 <= Dbg_TrClk;
Dbg_TrReady_17 <= Dbg_TrReady(17);
Dbg_Clk_18 <= Dbg_Clk;
Dbg_TDI_18 <= Dbg_TDI;
Dbg_Reg_En_18 <= Dbg_Reg_En_I(18);
Dbg_Capture_18 <= Dbg_Capture;
Dbg_Shift_18 <= Dbg_Shift;
Dbg_Update_18 <= Dbg_Update;
Dbg_Rst_18 <= Dbg_Rst_I(18);
Dbg_TDO_I(18) <= Dbg_TDO_18;
Dbg_TrClk_18 <= Dbg_TrClk;
Dbg_TrReady_18 <= Dbg_TrReady(18);
Dbg_Clk_19 <= Dbg_Clk;
Dbg_TDI_19 <= Dbg_TDI;
Dbg_Reg_En_19 <= Dbg_Reg_En_I(19);
Dbg_Capture_19 <= Dbg_Capture;
Dbg_Shift_19 <= Dbg_Shift;
Dbg_Update_19 <= Dbg_Update;
Dbg_Rst_19 <= Dbg_Rst_I(19);
Dbg_TDO_I(19) <= Dbg_TDO_19;
Dbg_TrClk_19 <= Dbg_TrClk;
Dbg_TrReady_19 <= Dbg_TrReady(19);
Dbg_Clk_20 <= Dbg_Clk;
Dbg_TDI_20 <= Dbg_TDI;
Dbg_Reg_En_20 <= Dbg_Reg_En_I(20);
Dbg_Capture_20 <= Dbg_Capture;
Dbg_Shift_20 <= Dbg_Shift;
Dbg_Update_20 <= Dbg_Update;
Dbg_Rst_20 <= Dbg_Rst_I(20);
Dbg_TDO_I(20) <= Dbg_TDO_20;
Dbg_TrClk_20 <= Dbg_TrClk;
Dbg_TrReady_20 <= Dbg_TrReady(20);
Dbg_Clk_21 <= Dbg_Clk;
Dbg_TDI_21 <= Dbg_TDI;
Dbg_Reg_En_21 <= Dbg_Reg_En_I(21);
Dbg_Capture_21 <= Dbg_Capture;
Dbg_Shift_21 <= Dbg_Shift;
Dbg_Update_21 <= Dbg_Update;
Dbg_Rst_21 <= Dbg_Rst_I(21);
Dbg_TDO_I(21) <= Dbg_TDO_21;
Dbg_TrClk_21 <= Dbg_TrClk;
Dbg_TrReady_21 <= Dbg_TrReady(21);
Dbg_Clk_22 <= Dbg_Clk;
Dbg_TDI_22 <= Dbg_TDI;
Dbg_Reg_En_22 <= Dbg_Reg_En_I(22);
Dbg_Capture_22 <= Dbg_Capture;
Dbg_Shift_22 <= Dbg_Shift;
Dbg_Update_22 <= Dbg_Update;
Dbg_Rst_22 <= Dbg_Rst_I(22);
Dbg_TDO_I(22) <= Dbg_TDO_22;
Dbg_TrClk_22 <= Dbg_TrClk;
Dbg_TrReady_22 <= Dbg_TrReady(22);
Dbg_Clk_23 <= Dbg_Clk;
Dbg_TDI_23 <= Dbg_TDI;
Dbg_Reg_En_23 <= Dbg_Reg_En_I(23);
Dbg_Capture_23 <= Dbg_Capture;
Dbg_Shift_23 <= Dbg_Shift;
Dbg_Update_23 <= Dbg_Update;
Dbg_Rst_23 <= Dbg_Rst_I(23);
Dbg_TDO_I(23) <= Dbg_TDO_23;
Dbg_TrClk_23 <= Dbg_TrClk;
Dbg_TrReady_23 <= Dbg_TrReady(23);
Dbg_Clk_24 <= Dbg_Clk;
Dbg_TDI_24 <= Dbg_TDI;
Dbg_Reg_En_24 <= Dbg_Reg_En_I(24);
Dbg_Capture_24 <= Dbg_Capture;
Dbg_Shift_24 <= Dbg_Shift;
Dbg_Update_24 <= Dbg_Update;
Dbg_Rst_24 <= Dbg_Rst_I(24);
Dbg_TDO_I(24) <= Dbg_TDO_24;
Dbg_TrClk_24 <= Dbg_TrClk;
Dbg_TrReady_24 <= Dbg_TrReady(24);
Dbg_Clk_25 <= Dbg_Clk;
Dbg_TDI_25 <= Dbg_TDI;
Dbg_Reg_En_25 <= Dbg_Reg_En_I(25);
Dbg_Capture_25 <= Dbg_Capture;
Dbg_Shift_25 <= Dbg_Shift;
Dbg_Update_25 <= Dbg_Update;
Dbg_Rst_25 <= Dbg_Rst_I(25);
Dbg_TDO_I(25) <= Dbg_TDO_25;
Dbg_TrClk_25 <= Dbg_TrClk;
Dbg_TrReady_25 <= Dbg_TrReady(25);
Dbg_Clk_26 <= Dbg_Clk;
Dbg_TDI_26 <= Dbg_TDI;
Dbg_Reg_En_26 <= Dbg_Reg_En_I(26);
Dbg_Capture_26 <= Dbg_Capture;
Dbg_Shift_26 <= Dbg_Shift;
Dbg_Update_26 <= Dbg_Update;
Dbg_Rst_26 <= Dbg_Rst_I(26);
Dbg_TDO_I(26) <= Dbg_TDO_26;
Dbg_TrClk_26 <= Dbg_TrClk;
Dbg_TrReady_26 <= Dbg_TrReady(26);
Dbg_Clk_27 <= Dbg_Clk;
Dbg_TDI_27 <= Dbg_TDI;
Dbg_Reg_En_27 <= Dbg_Reg_En_I(27);
Dbg_Capture_27 <= Dbg_Capture;
Dbg_Shift_27 <= Dbg_Shift;
Dbg_Update_27 <= Dbg_Update;
Dbg_Rst_27 <= Dbg_Rst_I(27);
Dbg_TDO_I(27) <= Dbg_TDO_27;
Dbg_TrClk_27 <= Dbg_TrClk;
Dbg_TrReady_27 <= Dbg_TrReady(27);
Dbg_Clk_28 <= Dbg_Clk;
Dbg_TDI_28 <= Dbg_TDI;
Dbg_Reg_En_28 <= Dbg_Reg_En_I(28);
Dbg_Capture_28 <= Dbg_Capture;
Dbg_Shift_28 <= Dbg_Shift;
Dbg_Update_28 <= Dbg_Update;
Dbg_Rst_28 <= Dbg_Rst_I(28);
Dbg_TDO_I(28) <= Dbg_TDO_28;
Dbg_TrClk_28 <= Dbg_TrClk;
Dbg_TrReady_28 <= Dbg_TrReady(28);
Dbg_Clk_29 <= Dbg_Clk;
Dbg_TDI_29 <= Dbg_TDI;
Dbg_Reg_En_29 <= Dbg_Reg_En_I(29);
Dbg_Capture_29 <= Dbg_Capture;
Dbg_Shift_29 <= Dbg_Shift;
Dbg_Update_29 <= Dbg_Update;
Dbg_Rst_29 <= Dbg_Rst_I(29);
Dbg_TDO_I(29) <= Dbg_TDO_29;
Dbg_TrClk_29 <= Dbg_TrClk;
Dbg_TrReady_29 <= Dbg_TrReady(29);
Dbg_Clk_30 <= Dbg_Clk;
Dbg_TDI_30 <= Dbg_TDI;
Dbg_Reg_En_30 <= Dbg_Reg_En_I(30);
Dbg_Capture_30 <= Dbg_Capture;
Dbg_Shift_30 <= Dbg_Shift;
Dbg_Update_30 <= Dbg_Update;
Dbg_Rst_30 <= Dbg_Rst_I(30);
Dbg_TDO_I(30) <= Dbg_TDO_30;
Dbg_TrClk_30 <= Dbg_TrClk;
Dbg_TrReady_30 <= Dbg_TrReady(30);
Dbg_Clk_31 <= Dbg_Clk;
Dbg_TDI_31 <= Dbg_TDI;
Dbg_Reg_En_31 <= Dbg_Reg_En_I(31);
Dbg_Capture_31 <= Dbg_Capture;
Dbg_Shift_31 <= Dbg_Shift;
Dbg_Update_31 <= Dbg_Update;
Dbg_Rst_31 <= Dbg_Rst_I(31);
Dbg_TDO_I(31) <= Dbg_TDO_31;
Dbg_TrClk_31 <= Dbg_TrClk;
Dbg_TrReady_31 <= Dbg_TrReady(31);
end architecture IMP;
| gpl-3.0 | 5d8187d1698a3ef5ce366f67363670f5 | 0.514885 | 3.19242 | false | false | false | false |
IAIK/ascon_hardware | asconv1/ascon_fast.vhdl | 1 | 19,449 | -------------------------------------------------------------------------------
-- Title : A naturally fast implementation of Ascon
-- Project : Ascon
-------------------------------------------------------------------------------
-- File : ascon_fast.vhdl
-- Author : Erich Wenger <[email protected]>
-- Company : Graz University of Technology
-- Created : 2014-03-21
-- Last update: 2014-08-22
-- Platform : ASIC design
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-21 1.0 Erich Wenger Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon is
generic (
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic; -- active-high chip select
WExSI : in std_logic; -- active-high write enable
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity ascon;
architecture structural of ascon is
constant CONTROL_STATE_SIZE : integer := 4;
constant STATE_WORD_SIZE : integer := 64;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
signal KeyxDP, KeyxDN : std_logic_vector(KEY_SIZE-1 downto 0);
signal IODataxDP, IODataxDN : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
signal State0xDP, State0xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State1xDP, State1xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State2xDP, State2xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State3xDP, State3xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State4xDP, State4xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal ControlStatexDP, ControlStatexDN : std_logic_vector(CONTROL_STATE_SIZE-1 downto 0);
signal StatexDP : std_logic_vector(5*STATE_WORD_SIZE-1 downto 0);
signal DP_WriteNoncexS : std_logic;
signal DP_WriteIODataxS : std_logic;
signal CP_InitxSP, CP_InitxSN : std_logic;
signal CP_AssociatexSP, CP_AssociatexSN : std_logic;
signal CP_EncryptxSP, CP_EncryptxSN : std_logic;
signal CP_DecryptxSP, CP_DecryptxSN : std_logic;
signal CP_FinalAssociatedDataxSP, CP_FinalAssociatedDataxSN : std_logic;
signal CP_FinalEncryptxSP, CP_FinalEncryptxSN : std_logic;
signal CP_FinalDecryptxSP, CP_FinalDecryptxSN : std_logic;
signal CP_DonexS : std_logic;
signal CP_ScheduledAssociatexSP, CP_ScheduledAssociatexSN : std_logic;
signal CP_ScheduledEncryptxSP, CP_ScheduledEncryptxSN : std_logic;
signal CP_ScheduledDecryptxSP, CP_ScheduledDecryptxSN : std_logic;
signal DP_InitxS : std_logic;
signal DP_RoundxS : std_logic;
signal DP_XorZKeyxS : std_logic;
signal DP_XorKeyZxS : std_logic;
signal DP_XorZOnexS : std_logic;
signal DP_EncryptxS : std_logic;
signal DP_DecryptxS : std_logic;
signal DP_AssociatexS : std_logic;
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
variable x : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- ROTATE_STATE_WORD
x := word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
return x;
end ROTATE_STATE_WORD;
begin -- architecture structural
StatexDP <= State4xDP & State3xDP & State2xDP & State1xDP & State0xDP;
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
KeyxDP <= (others => '0');
IODataxDP <= (others => '0');
State0xDP <= (others => '0');
State1xDP <= (others => '0');
State2xDP <= (others => '0');
State3xDP <= (others => '0');
State4xDP <= (others => '0');
ControlStatexDP <= (others => '0');
CP_InitxSP <= '0';
CP_AssociatexSP <= '0';
CP_EncryptxSP <= '0';
CP_DecryptxSP <= '0';
CP_FinalAssociatedDataxSP <= '0';
CP_FinalEncryptxSP <= '0';
CP_FinalDecryptxSP <= '0';
CP_ScheduledAssociatexSP <= '0';
CP_ScheduledEncryptxSP <= '0';
CP_ScheduledDecryptxSP <= '0';
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
KeyxDP <= KeyxDN;
IODataxDP <= IODataxDN;
State0xDP <= State0xDN;
State1xDP <= State1xDN;
State2xDP <= State2xDN;
State3xDP <= State3xDN;
State4xDP <= State4xDN;
ControlStatexDP <= ControlStatexDN;
CP_InitxSP <= CP_InitxSN;
CP_AssociatexSP <= CP_AssociatexSN;
CP_EncryptxSP <= CP_EncryptxSN;
CP_DecryptxSP <= CP_DecryptxSN;
CP_FinalAssociatedDataxSP <= CP_FinalAssociatedDataxSN;
CP_FinalEncryptxSP <= CP_FinalEncryptxSN;
CP_FinalDecryptxSP <= CP_FinalDecryptxSN;
CP_ScheduledAssociatexSP <= CP_ScheduledAssociatexSN;
CP_ScheduledEncryptxSP <= CP_ScheduledEncryptxSN;
CP_ScheduledDecryptxSP <= CP_ScheduledDecryptxSN;
end if;
end process RegisterProc;
-- purpose: Glue the internal registers with the bus
-- type : combinational
DataBusLogicProc : process (AddressxDI, CP_AssociatexSP, CP_DecryptxSP, CP_DonexS, CP_EncryptxSP, CP_FinalDecryptxSP, CP_FinalEncryptxSP, CP_InitxSP, CP_ScheduledAssociatexSP, CP_ScheduledDecryptxSP, CP_ScheduledEncryptxSP, CSxSI, DataWritexDI, IODataxDP, KeyxDP, State3xDP, State4xDP, WExSI) is
variable AddressxDV : integer;
variable index : integer;
begin -- process DataBusLogicProc
KeyxDN <= KeyxDP;
AddressxDV := to_integer(unsigned(AddressxDI));
index := 0;
DataReadxDO <= (others => '0');
DP_WriteNoncexS <= '0';
DP_WriteIODataxS <= '0';
CP_InitxSN <= CP_InitxSP;
CP_AssociatexSN <= CP_AssociatexSP;
CP_EncryptxSN <= CP_EncryptxSP;
CP_DecryptxSN <= CP_DecryptxSP;
CP_FinalEncryptxSN <= CP_FinalEncryptxSP;
CP_FinalDecryptxSN <= CP_FinalDecryptxSP;
CP_ScheduledAssociatexSN <= CP_ScheduledAssociatexSP;
CP_ScheduledEncryptxSN <= CP_ScheduledEncryptxSP;
CP_ScheduledDecryptxSN <= CP_ScheduledDecryptxSP;
if CP_DonexS = '1' then
CP_InitxSN <= '0';
CP_AssociatexSN <= CP_ScheduledAssociatexSP;
CP_EncryptxSN <= CP_ScheduledEncryptxSP;
CP_DecryptxSN <= CP_ScheduledDecryptxSP;
CP_FinalEncryptxSN <= '0';
CP_FinalDecryptxSN <= '0';
CP_ScheduledAssociatexSN <= '0';
CP_ScheduledEncryptxSN <= '0';
CP_ScheduledDecryptxSN <= '0';
end if;
-- TODO: only designed for DATA_BUS_WIDTH=32
if CSxSI = '1' then
if WExSI = '1' then
-- synchronous write
if AddressxDV = 2 then
-- command register
CP_InitxSN <= DataWritexDI(0);
CP_FinalEncryptxSN <= DataWritexDI(4);
CP_FinalDecryptxSN <= DataWritexDI(5);
if CP_AssociatexSP = '1' then
CP_ScheduledAssociatexSN <= DataWritexDI(1);
else
CP_AssociatexSN <= DataWritexDI(1);
end if;
if CP_EncryptxSP = '1' then
CP_ScheduledEncryptxSN <= DataWritexDI(2);
else
CP_EncryptxSN <= DataWritexDI(2);
end if;
if CP_DecryptxSP = '1' then
CP_ScheduledDecryptxSN <= DataWritexDI(3);
else
CP_DecryptxSN <= DataWritexDI(3);
end if;
elsif (AddressxDV >= 4) and (AddressxDV < 8) then
-- write the key
index := to_integer(unsigned(AddressxDI(1 downto 0)));
KeyxDN((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH) <= DataWritexDI;
elsif (AddressxDV >= 8) and (AddressxDV < 12) then
-- write the nonce
DP_WriteNoncexS <= '1';
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- write the data to de/encrypt and associated data
DP_WriteIODataxS <= '1';
if (AddressxDV = 13) and ((CP_AssociatexSP = '1') or (CP_EncryptxSP = '1') or (CP_DecryptxSP = '1')) then
-- automatically enable association/encryption/decryption of next block as the new data is already ready
CP_ScheduledAssociatexSN <= CP_AssociatexSP;
CP_ScheduledEncryptxSN <= CP_EncryptxSP;
CP_ScheduledDecryptxSN <= CP_DecryptxSP;
end if;
end if;
else
-- asynchronous read
if AddressxDV = 0 then
DataReadxDO <= x"deadbeef";
elsif AddressxDV = 1 then
-- status register
-- returns 1 if busy
DataReadxDO(0) <= CP_InitxSP or CP_AssociatexSP or CP_EncryptxSP or CP_DecryptxSP or CP_FinalEncryptxSP or CP_FinalDecryptxSP;
elsif AddressxDV = 3 then
-- returns 1 if something is scheduled
DataReadxDO(0) <= CP_ScheduledAssociatexSP or CP_ScheduledEncryptxSP or CP_ScheduledDecryptxSP;
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- read the de/encrypted data and associated data
index := to_integer(unsigned(AddressxDI(0 downto 0)));
DataReadxDO <= IODataxDP((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH);
elsif (AddressxDV >= 16) and (AddressxDV < 20) then
-- read the tag
if AddressxDI(1 downto 0) = "00" then
DataReadxDO <= State4xDP(31 downto 0);
elsif AddressxDI(1 downto 0) = "01" then
DataReadxDO <= State4xDP(63 downto 32);
elsif AddressxDI(1 downto 0) = "10" then
DataReadxDO <= State3xDP(31 downto 0);
else
DataReadxDO <= State3xDP(63 downto 32);
end if;
end if;
end if;
end if;
end process DataBusLogicProc;
-- purpose: Controlpath of Ascon
-- type : combinational
ControlProc : process (CP_AssociatexSP, CP_DecryptxSP, CP_EncryptxSP,
CP_FinalAssociatedDataxSP, CP_FinalDecryptxSP,
CP_FinalEncryptxSP, CP_InitxSP, ControlStatexDP) is
variable ControlStatexDV : integer;
begin -- process ControlProc
CP_FinalAssociatedDataxSN <= CP_FinalAssociatedDataxSP;
DP_InitxS <= '0';
DP_RoundxS <= '0';
DP_XorZKeyxS <= '0';
DP_XorKeyZxS <= '0';
DP_XorZOnexS <= '0';
DP_EncryptxS <= '0';
DP_DecryptxS <= '0';
CP_DonexS <= '0';
DP_AssociatexS <= '0';
ControlStatexDV := to_integer(unsigned(ControlStatexDP));
ControlStatexDN <= ControlStatexDP;
if ControlStatexDV = 0 then
DP_InitxS <= CP_InitxSP;
DP_AssociatexS <= CP_AssociatexSP;
DP_EncryptxS <= CP_EncryptxSP or CP_FinalEncryptxSP;
DP_DecryptxS <= CP_DecryptxSP or CP_FinalDecryptxSP;
DP_XorKeyZxS <= CP_FinalEncryptxSP or CP_FinalDecryptxSP;
if CP_InitxSP = '1' then
CP_FinalAssociatedDataxSN <= '0';
end if;
if (CP_EncryptxSP = '1') or (CP_DecryptxSP = '1') or (CP_FinalEncryptxSP = '1') or (CP_FinalDecryptxSP = '1') then
CP_FinalAssociatedDataxSN <= '1';
if CP_FinalAssociatedDataxSP = '0' then
DP_XorZOnexS <= '1';
end if;
end if;
end if;
if (CP_InitxSP = '1') or (CP_AssociatexSP = '1') or (CP_EncryptxSP = '1') or (CP_DecryptxSP = '1') or (CP_FinalEncryptxSP = '1') or (CP_FinalDecryptxSP = '1') then
ControlStatexDN <= std_logic_vector(unsigned(ControlStatexDP) + 1);
DP_RoundxS <= '1';
end if;
if ((CP_InitxSP = '1') or (CP_FinalEncryptxSP = '1') or (CP_FinalDecryptxSP = '1')) and (ControlStatexDV = ROUNDS_A-1) then
ControlStatexDN <= (others => '0');
DP_XorZKeyxS <= '1';
CP_DonexS <= '1';
end if;
if ((CP_AssociatexSP = '1') or (CP_EncryptxSP = '1') or (CP_DecryptxSP = '1')) and (ControlStatexDV = ROUNDS_B-1) then
ControlStatexDN <= (others => '0');
CP_DonexS <= '1';
end if;
end process ControlProc;
-- purpose: Datapath of Ascon
-- type : combinational
DatapathProc : process (AddressxDI, ControlStatexDP, DP_AssociatexS,
DP_DecryptxS, DP_EncryptxS, DP_InitxS, DP_RoundxS,
DP_WriteIODataxS, DP_WriteNoncexS, DP_XorKeyZxS,
DP_XorZKeyxS, DP_XorZOnexS, DataWritexDI, IODataxDP,
KeyxDP, State0xDP, State1xDP, State2xDP, State3xDP,
State4xDP) is
variable P0xDV, P1xDV, P2xDV, P3xDV, P4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable R0xDV, R1xDV, R2xDV, R3xDV, R4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable S0xDV, S1xDV, S2xDV, S3xDV, S4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable T0xDV, T1xDV, T2xDV, T3xDV, T4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable U0xDV, U1xDV, U2xDV, U3xDV, U4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable RoundConstxDV : std_logic_vector(63 downto 0);
variable State0XorIODataxDV : std_logic_vector(63 downto 0);
begin -- process DatapathProc
RoundConstxDV := ZEROS(64-8) & not ControlStatexDP(3 downto 0) & ControlStatexDP(3 downto 0);
State0XorIODataxDV := State0xDP xor IODataxDP;
IODataxDN <= IODataxDP;
State0xDN <= State0xDP;
State1xDN <= State1xDP;
State2xDN <= State2xDP;
State3xDN <= State3xDP;
State4xDN <= State4xDP;
P0xDV := State0xDP;
P1xDV := State1xDP;
P2xDV := State2xDP;
P3xDV := State3xDP;
P4xDV := State4xDP;
if DP_InitxS = '1' then
P0xDV := CONST_KEY_SIZE & CONST_ROUNDS_A & CONST_ROUNDS_B & ZEROS(64-3*8);
P1xDV := KeyxDP(127 downto 64);
P2xDV := KeyxDP(63 downto 0);
-- State3xDP and State4xDP were already initialized with the NONCE
end if;
if DP_XorKeyZxS = '1' then
P1xDV := State1xDP xor KeyxDP(127 downto 64);
P2xDV := State2xDP xor KeyxDP(63 downto 0);
end if;
P4xDV(0) := P4xDV(0) xor DP_XorZOnexS;
if (DP_EncryptxS = '1') or (DP_AssociatexS = '1') then
P0xDV := State0XorIODataxDV;
end if;
if (DP_EncryptxS = '1') then
IODataxDN <= P0xDV;
end if;
if DP_DecryptxS = '1' then
P0xDV := IODataxDP;
IODataxDN <= State0XorIODataxDV;
end if;
R0xDV := P0xDV xor P4xDV;
R1xDV := P1xDV;
R2xDV := P2xDV xor P1xDV xor RoundConstxDV;
R3xDV := P3xDV;
R4xDV := P4xDV xor P3xDV;
S0xDV := R0xDV xor (not R1xDV and R2xDV);
S1xDV := R1xDV xor (not R2xDV and R3xDV);
S2xDV := R2xDV xor (not R3xDV and R4xDV);
S3xDV := R3xDV xor (not R4xDV and R0xDV);
S4xDV := R4xDV xor (not R0xDV and R1xDV);
T0xDV := S0xDV xor S4xDV;
T1xDV := S1xDV xor S0xDV;
T2xDV := not S2xDV;
T3xDV := S3xDV xor S2xDV;
T4xDV := S4xDV;
U0xDV := T0xDV xor ROTATE_STATE_WORD(T0xDV, 19) xor ROTATE_STATE_WORD(T0xDV, 28);
U1xDV := T1xDV xor ROTATE_STATE_WORD(T1xDV, 61) xor ROTATE_STATE_WORD(T1xDV, 39);
U2xDV := T2xDV xor ROTATE_STATE_WORD(T2xDV, 1) xor ROTATE_STATE_WORD(T2xDV, 6);
U3xDV := T3xDV xor ROTATE_STATE_WORD(T3xDV, 10) xor ROTATE_STATE_WORD(T3xDV, 17);
U4xDV := T4xDV xor ROTATE_STATE_WORD(T4xDV, 7) xor ROTATE_STATE_WORD(T4xDV, 41);
if DP_XorZKeyxS = '1' then
U3xDV := U3xDV xor KeyxDP(127 downto 64);
U4xDV := U4xDV xor KeyxDP(63 downto 0);
end if;
if DP_RoundxS = '1' then
State0xDN <= U0xDV;
State1xDN <= U1xDV;
State2xDN <= U2xDV;
State3xDN <= U3xDV;
State4xDN <= U4xDV;
end if;
---------------------------------------------------------------------------
-- part of bus interface
---------------------------------------------------------------------------
if DP_WriteNoncexS = '1' then
if DATA_BUS_WIDTH = 32 then
if AddressxDI(1 downto 0) = "00" then
State4xDN(31 downto 0) <= DataWritexDI;
elsif AddressxDI(1 downto 0) = "01" then
State4xDN(63 downto 32) <= DataWritexDI;
elsif AddressxDI(1 downto 0) = "10" then
State3xDN(31 downto 0) <= DataWritexDI;
else
State3xDN(63 downto 32) <= DataWritexDI;
end if;
elsif DATA_BUS_WIDTH = 64 then
if AddressxDI(0) = '0' then
State3xDN <= DataWritexDI;
else
State4xDN <= DataWritexDI;
end if;
else
-- TODO: implement for 16-bit, and 8-bit bus width
end if;
end if;
if DP_WriteIODataxS = '1' then
if DATA_BUS_WIDTH = 32 then
if AddressxDI(0) = '0' then
IODataxDN(31 downto 0) <= DataWritexDI;
else
IODataxDN(63 downto 32) <= DataWritexDI;
end if;
elsif DATA_BUS_WIDTH = 64 then
IODataxDN <= DataWritexDI;
else
-- TODO: implement for 16-bit, and 8-bit bus width
end if;
end if;
end process DatapathProc;
end architecture structural;
| apache-2.0 | 28ca86ac930a3c8e5e82dd27bd51bf9e | 0.583269 | 4.013413 | false | false | false | false |
IAIK/ascon_hardware | generic_implementation/ascon_fast_core.vhdl | 1 | 14,372 | -------------------------------------------------------------------------------
-- Title : A generic implementation of Ascon
-- Project :
-------------------------------------------------------------------------------
-- File :
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2016-05-25
-- Last update: 2016-06-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-25 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon_core is
generic (
UNROLED_ROUNDS : integer := 1; --1,2,3,6
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8;
STATE_WORD_SIZE : integer := 64);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
KeyxDI : in std_logic_vector(KEY_SIZE-1 downto 0);
CP_InitxSI : in std_logic;
CP_AssociatexSI : in std_logic;
CP_EncryptxSI : in std_logic;
CP_DecryptxSI : in std_logic;
CP_FinalEncryptxSI : in std_logic;
CP_FinalDecryptxSI : in std_logic;
DP_WriteNoncexSI : in std_logic;
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DP_WriteIODataxSI : in std_logic;
IODataxDO : out std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
CP_DonexSO : out std_logic;
StatexDO : out std_logic_vector(5*STATE_WORD_SIZE-1 downto 0)
);
end entity ascon_core;
architecture structural of ascon_core is
constant CONTROL_STATE_SIZE : integer := 4;
constant CONST_UNROLED_R : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(UNROLED_ROUNDS, 8));
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
constant CONST_RATE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(DATA_BLOCK_SIZE, 8));
signal State0xDP, State0xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State1xDP, State1xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State2xDP, State2xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State3xDP, State3xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State4xDP, State4xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal ControlStatexDP, ControlStatexDN : std_logic_vector(CONTROL_STATE_SIZE-1 downto 0);
signal StatexDP : std_logic_vector(5*STATE_WORD_SIZE-1 downto 0);
signal DP_InitxS : std_logic;
signal DP_XorZKeyxS : std_logic;
signal DP_XorKeyZxS : std_logic;
signal DP_XorZOnexS : std_logic;
signal DP_EncryptxS : std_logic;
signal DP_DecryptxS : std_logic;
signal DP_AssociatexS : std_logic;
signal CP_DonexS : std_logic;
signal DP_RoundxSN, DP_RoundxSP : std_logic;
signal CP_FinalAssociatedDataxSN, CP_FinalAssociatedDataxSP : std_logic;
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
variable x : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- ROTATE_STATE_WORD
x := word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
return x;
end ROTATE_STATE_WORD;
begin -- architecture structural
CP_DonexSO <= CP_DonexS;
StatexDP <= State4xDP & State3xDP & State2xDP & State1xDP & State0xDP;
StatexDO <= StatexDP;
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
State0xDP <= (others => '0');
State1xDP <= (others => '0');
State2xDP <= (others => '0');
State3xDP <= (others => '0');
State4xDP <= (others => '0');
ControlStatexDP <= (others => '0');
CP_FinalAssociatedDataxSP <= '0';
DP_RoundxSP <= '0';
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
State0xDP <= State0xDN;
State1xDP <= State1xDN;
State2xDP <= State2xDN;
State3xDP <= State3xDN;
State4xDP <= State4xDN;
ControlStatexDP <= ControlStatexDN;
CP_FinalAssociatedDataxSP <= CP_FinalAssociatedDataxSN;
DP_RoundxSP <= DP_RoundxSN;
end if;
end process RegisterProc;
-- purpose: Controlpath of Ascon
-- type : combinational
ControlProc : process (CP_AssociatexSI, CP_DecryptxSI, CP_EncryptxSI,
CP_FinalAssociatedDataxSP, CP_FinalDecryptxSI, DP_RoundxSP,
CP_FinalEncryptxSI, CP_InitxSI, ControlStatexDP) is
variable ControlStatexDV : integer;
begin -- process ControlProc
CP_FinalAssociatedDataxSN <= CP_FinalAssociatedDataxSP;
DP_InitxS <= '0';
DP_RoundxSN <= '0';
DP_XorZKeyxS <= '0';
DP_XorKeyZxS <= '0';
DP_XorZOnexS <= '0';
DP_EncryptxS <= '0';
DP_DecryptxS <= '0';
CP_DonexS <= '0';
DP_AssociatexS <= '0';
ControlStatexDV := to_integer(unsigned(ControlStatexDP));
ControlStatexDN <= ControlStatexDP;
if ControlStatexDV = 0 then
DP_InitxS <= CP_InitxSI;
DP_AssociatexS <= CP_AssociatexSI;
DP_EncryptxS <= CP_EncryptxSI or CP_FinalEncryptxSI;
DP_DecryptxS <= CP_DecryptxSI or CP_FinalDecryptxSI;
DP_XorKeyZxS <= CP_FinalEncryptxSI or CP_FinalDecryptxSI;
if CP_InitxSI = '1' then
CP_FinalAssociatedDataxSN <= '0';
end if;
if (CP_EncryptxSI = '1') or (CP_DecryptxSI = '1') or (CP_FinalEncryptxSI = '1') or (CP_FinalDecryptxSI = '1') then
CP_FinalAssociatedDataxSN <= '1';
if CP_FinalAssociatedDataxSP = '0' then
DP_XorZOnexS <= '1';
end if;
end if;
end if;
if (CP_InitxSI = '1') or (CP_AssociatexSI = '1') or (CP_EncryptxSI = '1') or (CP_DecryptxSI = '1') or (CP_FinalEncryptxSI = '1') or (CP_FinalDecryptxSI = '1') then
ControlStatexDN <= std_logic_vector(unsigned(ControlStatexDP) + UNROLED_ROUNDS);
DP_RoundxSN <= '1';
end if;
if ((CP_InitxSI = '1') or (CP_FinalEncryptxSI = '1') or (CP_FinalDecryptxSI = '1')) and (ControlStatexDV = ROUNDS_A-UNROLED_ROUNDS) then
ControlStatexDN <= (others => '0');
DP_XorZKeyxS <= '1';
CP_DonexS <= '1';
end if;
if ((CP_AssociatexSI = '1') or (CP_EncryptxSI = '1') or (CP_DecryptxSI = '1')) and (ControlStatexDV = ROUNDS_B-UNROLED_ROUNDS) then
ControlStatexDN <= (others => '0');
CP_DonexS <= '1';
end if;
end process ControlProc;
-- purpose: Datapath of Ascon
-- type : combinational
DatapathProc : process (AddressxDI,
ControlStatexDP, DP_AssociatexS,
DP_DecryptxS, DP_EncryptxS, DP_InitxS, DP_RoundxSN,
DP_WriteIODataxSI, DP_WriteNoncexSI, DP_XorKeyZxS,
DP_XorZKeyxS, DP_XorZOnexS, DataWritexDI,
KeyxDI, DataWritexDI,
State0xDP, State1xDP, State2xDP, State3xDP,
State4xDP) is
variable P0xDV, P1xDV, P2xDV, P3xDV, P4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable R0xDV, R1xDV, R2xDV, R3xDV, R4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable S0xDV, S1xDV, S2xDV, S3xDV, S4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable T0xDV, T1xDV, T2xDV, T3xDV, T4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable U0xDV, U1xDV, U2xDV, U3xDV, U4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable RoundConstxDV : std_logic_vector(63 downto 0);
variable State0XorIODataxDV : std_logic_vector(63 downto 0);
variable State1XorIODataxDV : std_logic_vector(63 downto 0);
begin -- process DatapathProc
-- default
State0xDN <= State0xDP;
State1xDN <= State1xDP;
State2xDN <= State2xDP;
State3xDN <= State3xDP;
State4xDN <= State4xDP;
P0xDV := State0xDP;
P1xDV := State1xDP;
P2xDV := State2xDP;
P3xDV := State3xDP;
P4xDV := State4xDP;
if DP_InitxS = '1' then
P0xDV := CONST_KEY_SIZE & CONST_RATE & CONST_ROUNDS_A & CONST_ROUNDS_B & ZEROS(32);
P1xDV := KeyxDI(127 downto 64);
P2xDV := KeyxDI(63 downto 0);
-- State3xDP and State4xDP were already initialized with the NONCE
end if;
--- for 128 variant
if DATA_BLOCK_SIZE = 64 then
State0XorIODataxDV := State0xDP xor DataWritexDI(63 downto 0);
IODataxDO <= State0XorIODataxDV;
-- finalization
if DP_XorKeyZxS = '1' then
P1xDV := State1xDP xor KeyxDI(127 downto 64);
P2xDV := State2xDP xor KeyxDI(63 downto 0);
end if;
if (DP_EncryptxS = '1') or (DP_AssociatexS = '1') then
P0xDV := State0XorIODataxDV;
end if;
-- for 128a variant
elsif DATA_BLOCK_SIZE = 128 then
State0XorIODataxDV := State0xDP xor DataWritexDI(127 downto 64);
State1XorIODataxDV := State1xDP xor DataWritexDI(63 downto 0);
IODataxDO <= State0XorIODataxDV & State1XorIODataxDV;
-- finalization
if DP_XorKeyZxS = '1' then
P2xDV := State2xDP xor KeyxDI(127 downto 64);
P3xDV := State3xDP xor KeyxDI(63 downto 0);
end if;
if (DP_EncryptxS = '1') or (DP_AssociatexS = '1') then
P0xDV := State0XorIODataxDV;
P1xDV := State1XorIODataxDV;
end if;
end if;
P4xDV(0) := P4xDV(0) xor DP_XorZOnexS;
if DP_DecryptxS = '1' then
P0xDV := DataWritexDI;
end if;
-- Unrole combinatorial path
for r in 0 to UNROLED_ROUNDS-1 loop
RoundConstxDV := ZEROS(64-8) & not std_logic_vector(unsigned(ControlStatexDP(3 downto 0)) + r) & std_logic_vector(unsigned(ControlStatexDP(3 downto 0)) + r);
R0xDV := P0xDV xor P4xDV;
R1xDV := P1xDV;
R2xDV := P2xDV xor P1xDV xor RoundConstxDV;
R3xDV := P3xDV;
R4xDV := P4xDV xor P3xDV;
S0xDV := R0xDV xor (not R1xDV and R2xDV);
S1xDV := R1xDV xor (not R2xDV and R3xDV);
S2xDV := R2xDV xor (not R3xDV and R4xDV);
S3xDV := R3xDV xor (not R4xDV and R0xDV);
S4xDV := R4xDV xor (not R0xDV and R1xDV);
T0xDV := S0xDV xor S4xDV;
T1xDV := S1xDV xor S0xDV;
T2xDV := not S2xDV;
T3xDV := S3xDV xor S2xDV;
T4xDV := S4xDV;
U0xDV := T0xDV xor ROTATE_STATE_WORD(T0xDV, 19) xor ROTATE_STATE_WORD(T0xDV, 28);
U1xDV := T1xDV xor ROTATE_STATE_WORD(T1xDV, 61) xor ROTATE_STATE_WORD(T1xDV, 39);
U2xDV := T2xDV xor ROTATE_STATE_WORD(T2xDV, 1) xor ROTATE_STATE_WORD(T2xDV, 6);
U3xDV := T3xDV xor ROTATE_STATE_WORD(T3xDV, 10) xor ROTATE_STATE_WORD(T3xDV, 17);
U4xDV := T4xDV xor ROTATE_STATE_WORD(T4xDV, 7) xor ROTATE_STATE_WORD(T4xDV, 41);
P0xDV := U0xDV;
P1xDV := U1xDV;
P2xDV := U2xDV;
P3xDV := U3xDV;
P4xDV := U4xDV;
end loop;
if DP_XorZKeyxS = '1' then
U3xDV := U3xDV xor KeyxDI(127 downto 64);
U4xDV := U4xDV xor KeyxDI(63 downto 0);
end if;
if DP_RoundxSN = '1' then
State0xDN <= U0xDV;
State1xDN <= U1xDV;
State2xDN <= U2xDV;
State3xDN <= U3xDV;
State4xDN <= U4xDV;
end if;
if DP_WriteNoncexSI = '1' then
if DATA_BUS_WIDTH = 32 then
if AddressxDI(1 downto 0) = "00" then
State4xDN(31 downto 0) <= DataWritexDI;
elsif AddressxDI(1 downto 0) = "01" then
State4xDN(63 downto 32) <= DataWritexDI;
elsif AddressxDI(1 downto 0) = "10" then
State3xDN(31 downto 0) <= DataWritexDI;
else
State3xDN(63 downto 32) <= DataWritexDI;
end if;
elsif DATA_BUS_WIDTH = 64 then
if AddressxDI(0) = '0' then
State4xDN <= DataWritexDI;
else
State3xDN <= DataWritexDI;
end if;
elsif DATA_BUS_WIDTH = 128 then
if AddressxDI(0) = '0' then
State4xDN <= DataWritexDI(63 downto 0);
State3xDN <= DataWritexDI(127 downto 64);
end if;
else
-- TODO: implement for 16-bit, and 8-bit bus width
end if;
end if;
end process DatapathProc;
end architecture structural;
| apache-2.0 | f9d272d15ebd813d4311cf240c1d594e | 0.5828 | 3.692703 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rx_fifo.vhd | 4 | 8,495 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
-- synopsys translate_off
-- synopsys translate_on
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_fifo_wr_en : in std_logic;
Rx_fifo_rd_en : in std_logic;
Rx_fifo_input : in std_logic_vector(15 downto 0);
Rx_fifo_mt_n : out std_logic;
Rx_fifo_full : out std_logic;
Rx_fifo_output : out std_logic_vector(15 downto 0)
);
end rx_fifo;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE --
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as C_RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply lene this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No constants in this architecture.
------------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------------
signal srl_fifo_reset : std_logic;
signal rx_fifo_output_i : std_logic_vector(15 downto 0);
------------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------------
component srl_fifo
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end component;
begin
------------------------------------------------------------------------------
-- Component Instantiations
------------------------------------------------------------------------------
-- Lene the function the component is performing with comments
-- Component instantiation names are all uppercase and are of the form:
-- <ENTITY_>I_<#|FUNC>
-- If no components are required, delete this section from the file
------------------------------------------------------------------------------
I_SRL_FIFO : srl_fifo
generic map (
C_DATA_BITS => 16,
C_DEPTH => 16,
C_XON => false
)
port map (
Clk => Ref_Clk,
Reset => srl_fifo_reset,
FIFO_Write => Rx_fifo_wr_en,
Data_In => Rx_fifo_input,
FIFO_Read => Rx_fifo_rd_en,
Data_Out => rx_fifo_output_i,
FIFO_Full => Rx_fifo_full,
Data_Exists => Rx_fifo_mt_n,
Addr => open
);
------------------------------------------------------------------------------
-- RESET_PROCESS
------------------------------------------------------------------------------
RESET_PROCESS : process (Sync_rst_n)
begin
if (Sync_rst_n = C_RESET_ACTIVE) then
srl_fifo_reset <= '1';
else
srl_fifo_reset <= '0';
end if;
end process;
------------------------------------------------------------------------------
-- FIFO_REGISTER_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
FIFO_REGISTER_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rx_fifo_output <= (others => '0');
elsif (Rx_fifo_rd_en = '1') then
Rx_fifo_output <= rx_fifo_output_i;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- NONE
end simulation;
| gpl-3.0 | 277a55e28d6b91608e0ce49e10f3363b | 0.465568 | 5.09904 | false | false | false | false |
hoangt/PoC | tb/common/my_config_DE4.vhdl | 2 | 1,745 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "DE4"; -- Stratix II GX Audio Video Development Kit
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
| apache-2.0 | ae6ba2e5fc6ecda0a896f491a98bfb03 | 0.578223 | 4.485861 | false | true | false | false |
MikhailKoslowski/Variax | Quartus/DataGenerator.vhd | 1 | 1,164 | -----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY DataGenerator IS
PORT (
clk : IN STD_LOGIC;
nxt : IN STD_LOGIC;
data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END ENTITY;
-----------------------------------------------------------
ARCHITECTURE structure OF DataGenerator IS
SIGNAL running : STD_LOGIC := '0';
SIGNAL s_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL rd1 : STD_LOGIC;
SIGNAL rd2 : STD_LOGIC;
SIGNAL lastNxt : STD_LOGIC := '0';
BEGIN
PROCESS (clk)
VARIABLE value : INTEGER RANGE 0 to 255 := 31;
BEGIN
IF clk'EVENT AND clk='1' THEN
IF nxt='1' AND lastNxt='0' THEN
-- Rising edge
value := value + 1;
IF value >= 127 THEN
value := 32;
END IF;
s_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(value, 8));
rdy <= '1';
ELSIF nxt='0' THEN
-- Steady
rdy <= '0';
END IF;
lastNxt <= nxt;
END IF;
END PROCESS;
data <= s_data;
END ARCHITECTURE structure; | mit | 2326b028361133f6b87083e344ad699d | 0.524055 | 3.454006 | false | false | false | false |
hoangt/PoC | src/io/ddrio/ddrio_out_altera.vhdl | 2 | 2,231 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Output Registers for Altera FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.out for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library Altera_mf;
use Altera_mf.Altera_MF_Components.all;
entity ddrio_out_altera is
generic (
BITS : POSITIVE
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_out_altera is
begin
off : altddio_out
generic map (
WIDTH => BITS,
INTENDED_DEVICE_FAMILY => "STRATIXII" -- TODO: built device string from PoC.config information
)
port map (
outclock => Clock,
outclocken => ClockEnable,
oe => OutputEnable,
datain_h => DataOut_high,
datain_l => DataOut_low,
dataout => Pad
);
end architecture;
| apache-2.0 | 05ebef0ed0b34305c581cc777318a10f | 0.59749 | 3.755892 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/PreProcessor.vhd | 1 | 38,179 | -------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features activation
G_ENABLE_PAD : boolean := False; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
--! Padding options
G_PAD_STYLE : integer := 0; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! CipherCore
--! Key
key : out std_logic_vector(G_KEY_SIZE -1 downto 0);
key_ready : in std_logic;
key_valid : out std_logic;
key_update : out std_logic;
--! BDI
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
decrypt : out std_logic;
bdi_ready : in std_logic;
bdi_valid : out std_logic;
bdi_type : out std_logic_vector(3 -1 downto 0);
bdi_partial : out std_logic;
bdi_eot : out std_logic;
bdi_eoi : out std_logic;
bdi_size : out std_logic_vector(G_LBS_BYTES+1-1 downto 0);
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
--! CMD FIFO
cmd : out std_logic_vector(24 -1 downto 0);
cmd_ready : in std_logic;
cmd_valid : out std_logic
);
end entity PreProcessor;
architecture structure of PreProcessor is
constant DSIZE : integer := G_DBLK_SIZE;
constant ASIZE : integer := G_ABLK_SIZE;
constant WB : integer := G_W/8; --! Word bytes
constant LOG2_WB : integer := log2_ceil(WB);
constant LOG2_KEYBYTES : integer := log2_ceil(512/8);
constant CNT_AWORDS : integer := (G_ABLK_SIZE+(G_W-1))/G_W;
constant CNT_DWORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W;
constant CNT_KWORDS : integer := (G_KEY_SIZE+(G_SW-1))/G_SW;
constant A_EQ_D : boolean := (DSIZE = ASIZE);
constant P_IS_BUFFER : boolean := not (G_W = DSIZE);
constant S_IS_BUFFER : boolean := not (G_SW = G_KEY_SIZE);
--! =======================================================================
type t_lookup is array (0 to (WB-1))
of std_logic_vector(WB-1 downto 0);
function getVbytesLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
if (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
function getPlocLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
ret(i) := (others => '0');
ret(i)((size/8-i)-1) := '1';
--ret(i) := (((size/8-i)-1) => '1', others => '0');
end loop;
return ret;
end function getPlocLookup;
constant VBYTES_LOOKUP : t_lookup := getVbytesLookup(G_W);
constant PLOC_LOOKUP : t_lookup := getPlocLookup(G_W);
--! =======================================================================
--! Control status registers
--! Public
signal sgmt_type : std_logic_vector(4 -1 downto 0);
signal sgmt_pt : std_logic;
signal sgmt_eoi : std_logic;
signal sgmt_eot : std_logic;
signal sgmt_lst : std_logic;
signal sgmt_len : std_logic_vector(16 -1 downto 0);
signal is_decrypt : std_logic;
--! Secret
signal reg_key_update : std_logic;
signal reg_key_valid : std_logic;
--! =======================================================================
--! Control signals
--! Pad
signal set_extra : std_logic;
signal set_req_pad : std_logic;
signal req_pad : std_logic;
signal is_extra : std_logic;
signal sel_pad : std_logic;
signal is_pad : std_logic;
signal en_len : std_logic;
signal en_zero : std_logic;
signal reg_sel_zero : std_logic;
--! Public
signal pdi_rdy : std_logic;
signal bdi_vld : std_logic;
signal set_key_upd : std_logic;
signal ld_sgmt_info : std_logic;
signal ld_ctr : std_logic;
signal en_ctr : std_logic;
signal en_ps : std_logic;
signal en_data : std_logic;
signal ctr : std_logic_vector
(log2_ceil(CNT_DWORDS)-1 downto 0);
signal sel_end : std_logic;
signal ld_end : std_logic;
--! (unused)
signal sel_last_word : std_logic;
--! Secret
signal sdi_rdy : std_logic;
signal ld_ctr2 : std_logic;
signal ld_slen : std_logic;
signal en_ctr2 : std_logic;
signal en_slen : std_logic;
signal en_ss : std_logic;
signal en_key : std_logic;
signal slen : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
signal ctr2 : std_logic_vector
(log2_ceil(CNT_KWORDS)-1 downto 0);
--! Cmd
signal wr_cmd : std_logic;
--! =======================================================================
--! State
type t_ps is (S_WAIT_INSTR, S_WAIT_HDR, S_PREP, S_DATA, S_WAIT_READY);
type t_ss is (S_WAIT_INSTR, S_WAIT_HDR, S_DATA, S_WAIT_READY);
signal ps : t_ps; --! Public State
signal nps : t_ps; --! Next Public State
signal ss : t_ss; --! Next Secret State
signal nss : t_ss; --! Next Secret State
--! =======================================================================
--! Data padding
signal word_size : std_logic_vector(LOG2_WB -1 downto 0);
signal data : std_logic_vector(G_W -1 downto 0);
--! Incoming data word
signal pdata : std_logic_vector(G_W -1 downto 0);
signal vbytes : std_logic_vector(WB -1 downto 0);
signal ploc : std_logic_vector(WB -1 downto 0);
--! Additional padding selection when ASIZE /= DSIZE
signal pdata2 : std_logic_vector(G_W -1 downto 0);
signal vbytes2 : std_logic_vector(WB -1 downto 0);
signal ploc2 : std_logic_vector(WB -1 downto 0);
--! Output regs
--! Prep status
signal mux_vbytes : std_logic_vector(WB -1 downto 0);
signal mux_ploc : std_logic_vector(WB -1 downto 0);
signal mux_size : std_logic_vector(LOG2_WB+1 -1 downto 0);
signal size : std_logic_vector(LOG2_WB+1 -1 downto 0);
--! Status
signal reg_bdi_valid : std_logic;
signal reg_size : std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! Data / info
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! =======================================================================
--! Signal aliases
signal p_instr_opcode : std_logic_vector(4 -1 downto 0);
signal p_sgmt_type : std_logic_vector(4 -1 downto 0);
signal p_sgmt_pt : std_logic;
signal p_sgmt_eoi : std_logic;
signal p_sgmt_eot : std_logic;
signal p_sgmt_lst : std_logic;
signal p_sgmt_len : std_logic_vector(16 -1 downto 0);
signal s_instr_opcode : std_logic_vector(4 -1 downto 0);
signal s_sgmt_type : std_logic_vector(4 -1 downto 0);
signal s_sgmt_eot : std_logic;
signal s_sgmt_lst : std_logic;
signal s_sgmt_len : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
begin
--! =======================================================================
--! Datapath (Core)
--! =======================================================================
data <= pdi_data when reg_sel_zero = '0' else (others => '0');
gPad0: if (not G_ENABLE_PAD) generate
pdata <= data;
end generate;
gPad1: if (G_ENABLE_PAD) generate
begin
gPadMode0: if (G_PAD_STYLE = 0) generate
pdata <= data;
end generate;
gPadMode1: if (G_PAD_STYLE = 1) generate
gLoop: for i in WB-1 downto 0 generate
pdata(i*8+7)
<= ploc(i) or data(i*8+7);
pdata(i*8+6 downto i*8)
<= data(i*8+6 downto i*8);
end generate;
end generate;
gPadMode2: if (G_PAD_STYLE = 2) generate
signal add_pad : std_logic;
begin
add_pad <= '1' when (sgmt_type(3 downto 2) = ST_A
and sgmt_eot = '1')
or (sgmt_type(3 downto 2) /= ST_A
and sgmt_eot = '0')
else '0';
gLoop: for i in WB-1 downto 0 generate
pdata(i*8+7 downto i*8+2) <= data(i*8+7 downto i*8+2);
pdata(i*8+1) <= ploc(i) or data(i*8+1);
pdata(i*8+0) <= data(i*8+0) or (ploc(i) and add_pad);
end generate;
end generate;
end generate;
mux_vbytes <= VBYTES_LOOKUP(to_integer(unsigned(word_size)))
when sel_pad = '1'
else (others => '1');
mux_ploc <= PLOC_LOOKUP(to_integer(unsigned(word_size)))
when (sel_pad = '1' and req_pad = '1')
else (others => '0');
mux_size <= '0' & word_size
when sel_pad = '1'
else (LOG2_WB => '1', others => '0');
process(clk)
begin
if rising_edge(clk) then
if (en_len = '1') then
vbytes <= mux_vbytes;
ploc <= mux_ploc;
size <= mux_size;
end if;
if (en_data = '1') then
if ((DSIZE > G_W) and (DSIZE MOD G_W) = 0) then
reg_data <= reg_data(DSIZE-G_W-1 downto 0) & pdata;
reg_vbytes<= reg_vbytes(DSIZE/8-WB-1 downto 0) & vbytes;
reg_ploc <= reg_ploc (DSIZE/8-WB-1 downto 0) & ploc;
elsif ((DSIZE MOD G_W) /= 0) then
if (sel_last_word = '0') then
reg_data (DSIZE-1 downto (DSIZE MOD G_W )) <=
reg_data(DSIZE-G_W-1 downto (DSIZE MOD G_W))
& pdata2;
reg_vbytes(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_vbytes(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& vbytes2;
reg_ploc(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_ploc(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& ploc2;
else
reg_data ((DSIZE mod G_W)-1 downto 0) <=
pdata2(G_W -1 downto G_W /2);
reg_vbytes(((DSIZE/8) mod WB)-1 downto 0) <=
vbytes(WB-1 downto WB/2);
reg_ploc(((DSIZE/8) mod WB)-1 downto 0) <=
ploc2(WB-1 downto WB/2);
end if;
end if;
end if;
if (en_key = '1') then
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi_data;
end if;
end if;
end if;
end process;
--! =======================================================================
--! Registers with rst for controller and datapath
--! =======================================================================
gSyncRst:
if (not G_ASYNC_RSTN) generate
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
else
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end if;
end process;
end generate;
gAsyncRstn:
if (G_ASYNC_RSTN) generate
process(clk, rst)
begin
if (rst = '0') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
elsif rising_edge(clk) then
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end process;
end generate;
--! =======================================================================
--! Datapath (Output)
--! =======================================================================
pdi_ready <= pdi_rdy;
sdi_ready <= sdi_rdy;
--! Public
decrypt <= is_decrypt;
gDsizeEq:
if (not P_IS_BUFFER) generate
bdi <= pdata;
bdi_vld <= pdi_valid when (ps = S_DATA) else '0';
bdi_type <= sgmt_type(3 downto 1);
gNotCiph:
if (not G_CIPH_EXP) generate
bdi_eot <= sgmt_eot
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
end generate;
gCiph:
if (G_CIPH_EXP) generate
bdi_eot <= sgmt_eot or sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_lst
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= size;
bdi_valid_bytes <= vbytes;
bdi_pad_loc <= ploc;
end generate;
gDsizeNeq:
if (P_IS_BUFFER) generate
signal en_eoi_last : std_logic;
signal en_eot_last : std_logic;
begin
bdi <= reg_data;
bdi_vld <= reg_bdi_valid;
bdi_type <= sgmt_type(3 downto 1);
pEnd:
process(clk)
begin
if rising_edge(clk) then
if (ld_end = '1') then
if (not G_CIPH_EXP) then
bdi_eot <= sgmt_eot and sel_end;
bdi_eoi <= sgmt_eoi and sel_end;
else
bdi_eot <= (sgmt_eot or en_eot_last) and sel_end;
bdi_eoi <= (sgmt_eoi or en_eoi_last) and sel_end;
end if;
end if;
end if;
end process;
gCiph:
if (G_CIPH_EXP) generate
en_eot_last <= '1' when
((sgmt_eoi = '1' and sgmt_type = ST_NPUB)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_A
and G_PAD_AD /= 2 and G_PAD_AD /= 4)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_D
and G_PAD_D /= 2 and G_PAD_D /= 4))
else '0';
en_eoi_last <= '1' when en_eot_last = '1' and is_decrypt = '0'
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= reg_size;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
end generate;
bdi_valid <= bdi_vld;
--! Secret
gTsizeEq:
if (S_IS_BUFFER) generate
key_valid <= reg_key_valid;
key <= reg_key;
end generate;
gTsizeNeq:
if (not S_IS_BUFFER) generate
key_valid <= sdi_valid when (ss = S_DATA) else '0';
key <= sdi_data;
end generate;
key_update <= reg_key_update;
--! CMD FIFO
cmd <= pdi_data(G_W-1 downto G_W-5) & '0'
& pdi_data(G_W-7 downto G_W-8)
& pdi_data(G_W-17 downto G_W-32);
cmd_valid <= wr_cmd;
--! =======================================================================
--! Control
--! =======================================================================
process(clk)
begin
if rising_edge(clk) then
--! Operation register
if (ps = S_WAIT_INSTR) then
is_decrypt <= p_instr_opcode(0);
end if;
--! Length register
if (ld_sgmt_info = '1') then
sgmt_type <= p_sgmt_type;
if (G_CIPH_EXP) then
sgmt_pt <= p_sgmt_pt;
end if;
sgmt_eoi <= p_sgmt_eoi;
sgmt_eot <= p_sgmt_eot;
sgmt_lst <= p_sgmt_lst;
sgmt_len <= p_sgmt_len;
else
if (en_len = '1') then
if (sel_pad = '1') then
sgmt_len <= (others => '0');
else
sgmt_len <= std_logic_vector(unsigned(sgmt_len)-WB);
end if;
end if;
end if;
--! Padding activation register
if (en_len = '1') then
is_pad <= sel_pad;
end if;
--! Select zero register
if (ld_sgmt_info = '1')
or (P_IS_BUFFER and not A_EQ_D
and bdi_ready = '1' and unsigned(sgmt_len) > 0)
then
reg_sel_zero <= '0';
elsif (unsigned(sgmt_len) = 0 and en_len = '1')
or (not A_EQ_D and en_zero = '1')
then
reg_sel_zero <= '1';
end if;
--! Secret length register
if (ld_slen = '1') then
slen <= s_sgmt_len;
elsif (en_slen = '1') then
slen <= std_logic_vector(unsigned(slen)-G_KEY_SIZE/8);
end if;
--! Extra block register
if (ld_sgmt_info = '1' or (bdi_ready = '1' and bdi_vld = '1')) then
is_extra <= '0';
elsif (set_extra = '1') then
is_extra <= '1';
end if;
--! Public data input counter register
if (ld_ctr = '1') then
ctr <= (others => '0');
elsif (en_ctr = '1') then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
--! Secret data input counter register
if (ld_ctr2 = '1') then
ctr2 <= (others => '0');
elsif (en_ctr2 = '1') then
ctr2 <= std_logic_vector(unsigned(ctr2) + 1);
end if;
end if;
end process;
sel_pad <= '1' when (unsigned(sgmt_len) < WB) else '0';
word_size <= sgmt_len(LOG2_WB-1 downto 0);
--! HDR Dissection
p_instr_opcode <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_type <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_pt <= pdi_data(G_W-5);
p_sgmt_eoi <= pdi_data(G_W-6);
p_sgmt_eot <= pdi_data(G_W-7);
p_sgmt_lst <= pdi_data(G_W-8);
p_sgmt_len <= pdi_data(G_W-17 downto G_W-32);
s_instr_opcode <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_type <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_eot <= sdi_data(G_SW-7);
s_sgmt_lst <= sdi_data(G_SW-8);
s_sgmt_len <= sdi_data(G_SW-32+LOG2_KEYBYTES downto G_SW-32);
gPdiComb:
process(ps, p_instr_opcode, pdi_valid,
sgmt_len, sgmt_type, sgmt_eot, sgmt_lst,
p_sgmt_eot, p_sgmt_type,
bdi_ready, cmd_ready, reg_sel_zero,
is_extra, ctr)
begin
nps <= ps;
pdi_rdy <= '1';
set_key_upd <= '0';
set_req_pad <= '0';
ld_sgmt_info <= '0';
if (P_IS_BUFFER) then
ld_end <= '0';
set_extra <= '0';
end if;
ld_ctr <= '0';
en_data <= '0';
en_ps <= '0';
en_len <= '0';
en_ctr <= '0';
en_zero <= '0';
wr_cmd <= '0';
case ps is
when S_WAIT_INSTR =>
ld_ctr <= '1';
if (p_instr_opcode(3 downto 1) = OP_ENCDEC) then
nps <= S_WAIT_HDR;
end if;
if (p_instr_opcode = OP_ACTKEY) then
set_key_upd <= '1';
end if;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1') then
en_ps <= '1';
wr_cmd <= '1';
end if;
when S_WAIT_HDR =>
ld_sgmt_info <= '1';
nps <= S_PREP;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1' and cmd_ready = '1') then
en_ps <= '1';
if (p_sgmt_type(3 downto 2) = ST_D
or p_sgmt_type(3 downto 1) = ST_NSEC)
then
wr_cmd <= '1';
end if;
end if;
if (G_ENABLE_PAD) then
if (p_sgmt_eot = '1') then
if (p_sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 0)
or (p_sgmt_type(3 downto 2) = ST_D and G_PAD_D > 0)
then
set_req_pad <= '1';
end if;
end if;
end if;
when S_PREP =>
pdi_rdy <= '0';
--! state transition
if (unsigned(sgmt_len) = 0) then
if (G_ENABLE_PAD) and
--! Add a new block based on padding behavior
((sgmt_type(3 downto 2) = ST_A
and (G_PAD_AD = 2 or G_PAD_AD = 4))
or (sgmt_type(3 downto 2) = ST_D
and (G_PAD_D = 2 or G_PAD_D = 4)))
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
en_len <= '1';
en_ps <= '1';
when S_DATA =>
if (not P_IS_BUFFER) then
--! Without buffer
if (reg_sel_zero = '1'
or (not P_IS_BUFFER
and (pdi_valid = '0' or bdi_ready = '0')))
then
pdi_rdy <= '0';
end if;
if (unsigned(sgmt_len) = 0)
and not (req_pad = '1' and G_ENABLE_PAD
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D and G_PAD_D > 2)))
then
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
--! With buffer
if (reg_sel_zero = '1') then
pdi_rdy <= '0';
end if;
if (unsigned(ctr) = CNT_DWORDS-1) then
nps <= S_WAIT_READY;
end if;
if (unsigned(ctr) = CNT_DWORDS-2) then
ld_end <= '1';
end if;
if (unsigned(sgmt_len) = WB and G_ENABLE_PAD
and sgmt_eot = '1'
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D
and G_PAD_D > 2
and (not G_CIPH_EXP
or (G_CIPH_EXP and is_decrypt = '0')))))
then
if (A_EQ_D) then
if unsigned(ctr) = CNT_DWORDS-2 then
set_extra <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) = CNT_AWORDS-2)
or (sgmt_type(3 downto 2) = ST_D
and unsigned(ctr) = CNT_DWORDS-2))
then
set_extra <= '1';
end if;
end if;
end if;
--! if ASIZE < DSIZE
if (not A_EQ_D) then
if (sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) >= CNT_AWORDS-1)
then
en_zero <= '1';
end if;
end if;
end if;
if (reg_sel_zero = '1'
or (pdi_valid = '1'
and (P_IS_BUFFER
or (not P_IS_BUFFER and bdi_ready = '1'))))
then
if (sgmt_type(3 downto 2) /= ST_A
and sgmt_type(3 downto 2) /= ST_D)
then
--! Not AD or D segment
if (P_IS_BUFFER) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
en_len <= '1';
end if;
else
--! AD or D segment
if (P_IS_BUFFER) then
if (A_EQ_D) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) < CNT_AWORDS-1)
or (sgmt_type(3 downto 2) /= ST_A
and unsigned(ctr) /= CNT_DWORDS-1))
then
en_len <= '1';
end if;
end if;
else
en_len <= '1';
end if;
end if;
if (P_IS_BUFFER) then
en_ctr <= '1';
en_data <= '1';
end if;
en_ps <= '1';
end if;
when S_WAIT_READY =>
pdi_rdy <= '0';
ld_ctr <= '1';
if (unsigned(sgmt_len) = 0) then
if ((G_ENABLE_PAD and (G_PAD_AD > 2 or G_PAD_D > 2))
and is_extra = '1')
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
if (bdi_ready = '1') then
en_len <= '1';
en_ps <= '1';
end if;
end case;
end process;
sel_end <= '1' when (unsigned(sgmt_len) <= WB
and (is_extra = '0' and set_extra = '0'))
else '0';
gSdiComb:
process(ss, s_instr_opcode, sdi_valid, ctr2, key_ready, slen)
begin
nss <= ss;
sdi_rdy <= '0';
en_key <= '0';
ld_ctr2 <= '0';
ld_slen <= '0';
en_ctr2 <= '0';
en_slen <= '0';
en_ss <= '0';
case ss is
when S_WAIT_INSTR =>
ld_ctr2 <= '1';
sdi_rdy <= '1';
if (s_instr_opcode = OP_LDKEY) then
nss <= S_WAIT_HDR;
end if;
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_WAIT_HDR =>
nss <= S_DATA;
ld_slen <= '1';
sdi_rdy <= '1';
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_DATA =>
if (not S_IS_BUFFER) then
nss <= S_WAIT_INSTR;
if (sdi_valid = '1' and key_ready = '1') then
en_slen <= '1';
sdi_rdy <= '1';
if (unsigned(slen) = G_KEY_SIZE/8) then
en_ss <= '1';
end if;
end if;
else
sdi_rdy <= '1';
nss <= S_WAIT_READY;
if (sdi_valid = '1') then
en_ctr2 <= '1';
en_key <= '1';
if (unsigned(ctr2) = CNT_KWORDS-1) then
en_ss <= '1';
end if;
end if;
end if;
when S_WAIT_READY =>
if (unsigned(slen) = G_KEY_SIZE/8) then
nss <= S_WAIT_INSTR;
else
nss <= S_DATA;
end if;
ld_ctr2 <= '1';
if (key_ready = '1') then
en_ss <= '1';
en_slen <= '1';
end if;
end case;
end process;
end architecture structure;
| apache-2.0 | 3e54e13cccee78b98e7b5b3f7a77374d | 0.381127 | 4.107942 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/synth/design_1_axi_timer_0_0.vhd | 2 | 9,267 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_timer_0_0_arch : ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "artix7",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
| gpl-3.0 | 1e9001c6147113fd55af1cef0bf9d55e | 0.691162 | 3.276874 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/msh_cnt.vhd | 4 | 15,466 | -------------------------------------------------------------------------------
-- msh_cnt - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : msh_cnt.vhd
-- Version : v2.0
-- Description : A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the Rst signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_ADD_SUB_NOT -- 1 = Arith Add, 0 = Arith Substract
-- C_REG_WIDTH -- Width of data
-- C_RESET_VALUE -- Default value for the operation. Must be specified.
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Q -- Counter data out
-- Z -- Indicates '0' when decrementing
-- LD -- Counter load data
-- AD -- Counter load arithmatic data
-- LOAD -- Counter load enable
-- OP -- Counter arith operation enable
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity msh_cnt is
generic
(
-----------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
-----------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
-----------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector
-----------------------------------------------------------------------
);
port
(
Clk : in std_logic;
Rst : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
Z : out std_logic; -- indicates 0 when decrementing
LD : in std_logic_vector(0 to C_REG_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_REG_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end msh_cnt;
architecture imp of msh_cnt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MULT_AND
port
(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXCY_L is
port
(
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component MUXCY_L;
component XORCY is
port
(
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component XORCY;
component FDRE is
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i : std_logic_vector(0 to C_REG_WIDTH-1);
signal q_i_ns : std_logic_vector(0 to C_REG_WIDTH-1);
signal xorcy_out : std_logic_vector(0 to C_REG_WIDTH-1);
signal gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
signal z_i : std_logic;
begin
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, ClkEn : std_logic;
begin
-----------------------------------------------------------------------
-- Assign to load_bit the bit from input port LD.
-----------------------------------------------------------------------
load_bit <= LD(j);
-----------------------------------------------------------------------
-- Assign to arith_bit the bit from input port AD.
-----------------------------------------------------------------------
arith_bit <= AD(j);
-----------------------------------------------------------------------
-- LUT output generation.
-- Adder case
-----------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
-----------------------------------------------------------------------
-- Subtractor case
-----------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
-----------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
-----------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map
(
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
-----------------------------------------------------------------------
-- Propagate the carry (borrow) out.
-----------------------------------------------------------------------
MUXCY_L_i1: MUXCY_L
port map
(
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
LO => cry(j)
);
-----------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
-----------------------------------------------------------------------
XORCY_i1: XORCY
port map
(
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
STOP_AT_0_SUB: if not C_ADD_SUB_NOT generate
ClkEn <= (LOAD or OP) when (not (conv_integer(q_i) = 0)) else '0';
end generate STOP_AT_0_SUB;
STOP_AT_MSB_ADD : if C_ADD_SUB_NOT generate
ClkEn <= LOAD or OP;
end generate STOP_AT_MSB_ADD;
-----------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
-----------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map
(
Q => q_i(j),
C => Clk,
CE => ClkEn,
D => xorcy_out(j),
R => Rst
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map
(
Q => q_i(j),
C => Clk,
CE => ClkEn,
D => xorcy_out(j),
S => Rst
);
end generate;
end generate;
z_i <= '1' when ((conv_integer(q_i) = 1)) else '0';
z_ff: FDSE
port map
(
Q => Z,
C => Clk,
CE => '1',
D => z_i,
S => Rst
);
end imp;
| gpl-3.0 | 2e32030544525a1f0c7ccb013713d98c | 0.363442 | 5.06252 | false | false | false | false |
hoangt/PoC | src/comm/comm_crc.vhdl | 2 | 4,020 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Computes the Cyclic Redundancy Check (CRC)
--
-- Description:
-- ------------------------------------
-- Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder
-- of the polynomial division of the message by the given generator
-- polynomial (GEN).
--
-- The computation is unrolled so as to process an arbitrary number of
-- message bits per step. The generated CRC is independent from the chosen
-- processing width.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity comm_crc is
generic (
GEN : bit_vector; -- Generator Polynomial
BITS : positive; -- Number of Bits to be processed in parallel
STARTUP_RMD : std_logic_vector := "0";
OUTPUT_REGS : boolean := true
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Parallel Preload of Remainder
init : in std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); --
step : in std_logic; -- Process Input Data (MSB first)
din : in std_logic_vector(BITS-1 downto 0); --
rmd : out std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- Remainder
zero : out std_logic -- Remainder is Zero
);
end comm_crc;
architecture rtl of comm_crc is
-----------------------------------------------------------------------------
-- Normalizes the generator representation:
-- - into a 'downto 0' index range and
-- - truncating it just below the most significant and so hidden '1'.
function normalize(G : bit_vector) return bit_vector is
variable GN : bit_vector(G'length-1 downto 0);
begin
GN := G;
for i in GN'left downto 1 loop
if GN(i) = '1' then
return GN(i-1 downto 0);
end if;
end loop;
report "Cannot use absolute constant as generator."
severity failure;
return GN;
end normalize;
-- Normalized Generator
constant GN : std_logic_vector := to_stdlogicvector(normalize(GEN));
-- LFSR Value
signal lfsr : std_logic_vector(GN'range) := resize(descend(STARTUP_RMD), GN'length);
signal lfsn : std_logic_vector(GN'range); -- Next Value
signal lfso : std_logic_vector(GN'range); -- Output
begin
-- Compute next combinational Value
process(lfsr, din)
variable v : std_logic_vector(lfsr'range);
begin
v := lfsr;
for i in BITS-1 downto 0 loop
v := (v(v'left-1 downto 0) & '0') xor
(GN and (GN'range => (din(i) xor v(v'left))));
end loop;
lfsn <= v;
end process;
-- Remainder Register
process(clk)
begin
if rising_edge(clk) then
if set = '1' then
lfsr <= init(lfsr'range);
elsif step = '1' then
lfsr <= lfsn;
end if;
end if;
end process;
-- Provide Outputs
lfso <= lfsr when OUTPUT_REGS else lfsn;
rmd <= lfso;
zero <= '1' when lfso = (lfso'range => '0') else '0';
end rtl;
| apache-2.0 | ad7e5739f725aef02df456da96227508 | 0.601741 | 3.523225 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/synth/design_1_microblaze_0_xlconcat_0.vhd | 2 | 8,971 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY design_1_microblaze_0_xlconcat_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END design_1_microblaze_0_xlconcat_0;
ARCHITECTURE design_1_microblaze_0_xlconcat_0_arch OF design_1_microblaze_0_xlconcat_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_xlconcat_0_arch : ARCHITECTURE IS "design_1_microblaze_0_xlconcat_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "design_1_microblaze_0_xlconcat_0,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 2,
NUM_PORTS => 2
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END design_1_microblaze_0_xlconcat_0_arch;
| gpl-3.0 | 70cab0c0969aeb23f38d281e8d5fdae4 | 0.650541 | 3.245658 | false | false | false | false |
hoangt/PoC | tb/misc/sync/sync_Flag_tb.vhdl | 2 | 3,109 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a flag signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Flag_tb is
end;
architecture test of sync_Flag_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal Sync_out : STD_LOGIC_VECTOR(0 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "X";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncFlag : entity PoC.sync_Flag
generic map (
BITS => 1, -- number of bit to be synchronized
INIT => "0" --
)
port map (
Clock => Clock2, -- input clock domain
Input => Sync_in, -- input bits
Output => Sync_out -- output bits
);
end;
| apache-2.0 | f07addfcfe2bc7a119f72c766b73feaa | 0.556449 | 3.248694 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/misc/nasti_dsu.vhd | 2 | 7,746 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of nasti_dsu (Debug Support Unit).
--! @details DSU provides access to the internal CPU registers (CSRs) via
--! 'Rocket-chip' specific bus HostIO.
-----------------------------------------------------------------------------
--!
--! @page dsu_link Debug Support Unit (DSU)
--!
--! @par Overview
--! Debug Support Unit (DSU) was developed to simplify debugging on target
--! hardware and provide access to the "Rocket-chip" specific HostIO bus
--! interface. This bus provides access to the internal CPU control registers
--! (CSRs) that store information about Core configuration, current operational
--! mode (Machine, Hypervisor, Supervisor or User) and allows to change
--! processor run-time behaviour by injecting interrupts for an example.
--! General CSR registers are described in RISC-V privileged ISA
--! specification. Take into account that CPU can have any number of platform
--! specific CSRs that usually not entirely documented.
--!
--! @par Operation
--! DSU acts like a slave AMBA AXI4 device that is directly mapped into
--! physical memory. Default address location for our implementation
--! is 0x80020000. DSU directly transforms device offset address
--! into CSR index by removing last 4 bits of address.
--! All CSR values is always 64-bits width.
--!
--! @par Example:
--! Bus transaction at address <em>0x80027820</em>
--! will be redirected to HostIO bus with CSR index <em>0x782</em>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! RISCV specific funcionality.
library rocketlib;
use rocketlib.types_rocket.all;
entity nasti_dsu is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type;
o_soft_reset : out std_logic
);
end;
architecture arch_nasti_dsu of nasti_dsu is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_DSU,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
constant CSR_MRESET : std_logic_vector(11 downto 0) := X"782";
type state_type is (wait_grant, writting, wait_resp, skip1);
type registers is record
bank_axi : nasti_slave_bank_type;
--! Message multiplexer to form 128 request message of writting into CSR
state : state_type;
addr16_sel : std_logic;
waddr : std_logic_vector(11 downto 0);
wdata : std_logic_vector(63 downto 0);
rdata : std_logic_vector(63 downto 0);
-- Soft reset via CSR 0x782 MRESET doesn't work
-- so here I implement special register that will reset CPU via 'rst' input.
-- Otherwise I cannot load elf-file while CPU is not halted.
soft_reset : std_logic;
end record;
signal r, rin: registers;
begin
comblogic : process(i_axi, i_host, r)
variable v : registers;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable vhost : host_out_type;
begin
v := r;
vhost := host_out_none;
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
--! redefine value 'always ready' inserting waiting states.
v.bank_axi.rwaitready := '0';
if r.bank_axi.wstate = wtrans then
-- 32-bits burst transaction
v.addr16_sel := r.bank_axi.waddr(0)(16);
v.waddr := r.bank_axi.waddr(0)(15 downto 4);
if r.bank_axi.wburst = NASTI_BURST_INCR and r.bank_axi.wsize = 4 then
if r.bank_axi.waddr(0)(2) = '1' then
v.state := writting;
v.wdata(63 downto 32) := i_axi.w_data(31 downto 0);
else
v.wdata(31 downto 0) := i_axi.w_data(31 downto 0);
end if;
else
-- Write data on next clock.
if i_axi.w_strb(7 downto 0) /= X"00" then
v.wdata := i_axi.w_data(63 downto 0);
else
v.wdata := i_axi.w_data(127 downto 64);
end if;
v.state := writting;
end if;
end if;
case r.state is
when wait_grant =>
vhost.csr_req_bits_addr := r.bank_axi.raddr(0)(15 downto 4);
if r.bank_axi.rstate = rtrans then
if r.bank_axi.raddr(0)(16) = '1' then
-- Control registers (not implemented)
v.bank_axi.rwaitready := '1';
v.rdata := (others => '0');
v.state := skip1;
elsif r.bank_axi.raddr(0)(15 downto 4) = CSR_MRESET then
v.bank_axi.rwaitready := '1';
v.rdata(0) := r.soft_reset;
v.rdata(63 downto 1) := (others => '0');
v.state := skip1;
else
vhost.csr_req_valid := '1';
if (i_host.grant(htif_index) and i_host.csr_req_ready) = '1' then
v.state := wait_resp;
end if;
end if;
end if;
when writting =>
if r.addr16_sel = '1' then
-- Bank with control register (not implemented by CPU)
v.bank_axi.rwaitready := '1';
v.state := skip1;
elsif r.waddr = CSR_MRESET then
-- Soft Reset
v.bank_axi.rwaitready := '1';
v.soft_reset := r.wdata(0);
v.state := skip1;
else
vhost.csr_req_valid := '1';
vhost.csr_req_bits_rw := '1';
vhost.csr_req_bits_addr := r.waddr;
vhost.csr_req_bits_data := r.wdata;
if (i_host.grant(htif_index) and i_host.csr_req_ready) = '1' then
v.state := wait_resp;
end if;
end if;
when wait_resp =>
vhost.csr_resp_ready := '1';
if i_host.csr_resp_valid = '1' then
v.state := skip1;
v.rdata := i_host.csr_resp_bits;
v.bank_axi.rwaitready := '1';
end if;
when skip1 =>
v.state := wait_grant;
when others =>
end case;
if r.bank_axi.raddr(0)(2) = '0' then
rdata(31 downto 0) := r.rdata(31 downto 0);
else
-- 32-bits aligned access (can be generated by MAC)
rdata(31 downto 0) := r.rdata(63 downto 32);
end if;
rdata(63 downto 32) := r.rdata(63 downto 32);
if CFG_NASTI_DATA_BITS = 128 then
rdata(95 downto 64) := rdata(31 downto 0);
rdata(127 downto 96) := rdata(63 downto 32);
end if;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
o_host <= vhost;
rin <= v;
end process;
o_cfg <= xconfig;
o_soft_reset <= r.soft_reset;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
r.state <= wait_grant;
r.addr16_sel <= '0';
r.waddr <= (others => '0');
r.wdata <= (others => '0');
r.rdata <= (others => '0');
r.soft_reset <= '0';
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 4c3ee39c6df8d94ef30f6ec3ea99a898 | 0.572941 | 3.624708 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_rtl_hs/PreProcessor.vhd | 1 | 37,499 | -------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features activation
G_ENABLE_PAD : boolean := False; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
--! Padding options
G_PAD_STYLE : integer := 0; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! CipherCore
--! Key
key : out std_logic_vector(G_KEY_SIZE -1 downto 0);
key_ready : in std_logic;
key_valid : out std_logic;
key_update : out std_logic;
--! BDI
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
decrypt : out std_logic;
bdi_ready : in std_logic;
bdi_valid : out std_logic;
bdi_type : out std_logic_vector(3 -1 downto 0);
bdi_partial : out std_logic;
bdi_eot : out std_logic;
bdi_eoi : out std_logic;
bdi_size : out std_logic_vector(G_LBS_BYTES+1-1 downto 0);
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
--! CMD FIFO
cmd : out std_logic_vector(24 -1 downto 0);
cmd_ready : in std_logic;
cmd_valid : out std_logic
);
end entity PreProcessor;
architecture structure of PreProcessor is
constant DSIZE : integer := G_DBLK_SIZE;
constant ASIZE : integer := G_ABLK_SIZE;
constant WB : integer := G_W/8; --! Word bytes
constant LOG2_WB : integer := log2_ceil(WB);
constant LOG2_KEYBYTES : integer := log2_ceil(512/8);
constant CNT_AWORDS : integer := (G_ABLK_SIZE+(G_W-1))/G_W;
constant CNT_DWORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W;
constant CNT_KWORDS : integer := (G_KEY_SIZE+(G_SW-1))/G_SW;
constant A_EQ_D : boolean := (DSIZE = ASIZE);
constant P_IS_BUFFER : boolean := not (G_W = DSIZE);
constant S_IS_BUFFER : boolean := not (G_SW = G_KEY_SIZE);
--! =======================================================================
type t_lookup is array (0 to (WB-1))
of std_logic_vector(WB-1 downto 0);
function getVbytesLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
if (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
function getPlocLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
ret(i) := (others => '0');
ret(i)((size/8-i)-1) := '1';
--ret(i) := (((size/8-i)-1) => '1', others => '0');
end loop;
return ret;
end function getPlocLookup;
constant VBYTES_LOOKUP : t_lookup := getVbytesLookup(G_W);
constant PLOC_LOOKUP : t_lookup := getPlocLookup(G_W);
--! =======================================================================
--! Control status registers
--! Public
signal sgmt_type : std_logic_vector(4 -1 downto 0);
signal sgmt_pt : std_logic;
signal sgmt_eoi : std_logic;
signal sgmt_eot : std_logic;
signal sgmt_lst : std_logic;
signal sgmt_len : std_logic_vector(16 -1 downto 0);
signal is_decrypt : std_logic;
--! Secret
signal reg_key_update : std_logic;
signal reg_key_valid : std_logic;
--! =======================================================================
--! Control signals
--! Pad
signal set_extra : std_logic;
signal set_req_pad : std_logic;
signal req_pad : std_logic;
signal is_extra : std_logic;
signal sel_pad : std_logic;
signal is_pad : std_logic;
signal en_len : std_logic;
signal en_zero : std_logic;
signal reg_sel_zero : std_logic;
--! Public
signal pdi_rdy : std_logic;
signal bdi_vld : std_logic;
signal set_key_upd : std_logic;
signal ld_sgmt_info : std_logic;
signal ld_ctr : std_logic;
signal en_ctr : std_logic;
signal en_ps : std_logic;
signal en_data : std_logic;
signal ctr : std_logic_vector
(log2_ceil(CNT_DWORDS)-1 downto 0);
signal sel_end : std_logic;
signal ld_end : std_logic;
--! (unused)
signal en_last_word : std_logic;
--! Secret
signal sdi_rdy : std_logic;
signal ld_ctr2 : std_logic;
signal ld_slen : std_logic;
signal en_ctr2 : std_logic;
signal en_slen : std_logic;
signal en_ss : std_logic;
signal en_key : std_logic;
signal slen : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
signal ctr2 : std_logic_vector
(log2_ceil(CNT_KWORDS)-1 downto 0);
--! Cmd
signal wr_cmd : std_logic;
--! =======================================================================
--! State
type t_ps is (S_WAIT_INSTR, S_WAIT_HDR, S_PREP, S_DATA, S_WAIT_READY);
type t_ss is (S_WAIT_INSTR, S_WAIT_HDR, S_DATA, S_WAIT_READY);
signal ps : t_ps; --! Public State
signal nps : t_ps; --! Next Public State
signal ss : t_ss; --! Next Secret State
signal nss : t_ss; --! Next Secret State
--! =======================================================================
--! Data padding
signal word_size : std_logic_vector(LOG2_WB -1 downto 0);
signal data : std_logic_vector(G_W -1 downto 0);
--! Incoming data word
signal pdata : std_logic_vector(G_W -1 downto 0);
signal vbytes : std_logic_vector(WB -1 downto 0);
signal ploc : std_logic_vector(WB -1 downto 0);
--! Additional padding selection when ASIZE /= DSIZE
signal pdata2 : std_logic_vector(G_W -1 downto 0);
signal vbytes2 : std_logic_vector(WB -1 downto 0);
signal ploc2 : std_logic_vector(WB -1 downto 0);
--! Output regs
--! Prep status
signal mux_vbytes : std_logic_vector(WB -1 downto 0);
signal mux_ploc : std_logic_vector(WB -1 downto 0);
signal mux_size : std_logic_vector(LOG2_WB+1 -1 downto 0);
signal size : std_logic_vector(LOG2_WB+1 -1 downto 0);
--! Status
signal reg_bdi_valid : std_logic;
signal reg_size : std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! Data / info
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! =======================================================================
--! Signal aliases
signal p_instr_opcode : std_logic_vector(4 -1 downto 0);
signal p_sgmt_type : std_logic_vector(4 -1 downto 0);
signal p_sgmt_pt : std_logic;
signal p_sgmt_eoi : std_logic;
signal p_sgmt_eot : std_logic;
signal p_sgmt_lst : std_logic;
signal p_sgmt_len : std_logic_vector(16 -1 downto 0);
signal s_instr_opcode : std_logic_vector(4 -1 downto 0);
signal s_sgmt_type : std_logic_vector(4 -1 downto 0);
signal s_sgmt_eot : std_logic;
signal s_sgmt_lst : std_logic;
signal s_sgmt_len : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
begin
--! =======================================================================
--! Datapath (Core)
--! =======================================================================
data <= pdi_data when reg_sel_zero = '0' else (others => '0');
gPad0: if (not G_ENABLE_PAD) generate
pdata <= data;
end generate;
gPad1: if (G_ENABLE_PAD) generate
begin
gPadMode0: if (G_PAD_STYLE = 0) generate
pdata <= data;
end generate;
gPadMode1: if (G_PAD_STYLE = 1) generate
gLoop: for i in WB-1 downto 0 generate
pdata(i*8+7)
<= ploc(i) or data(i*8+7);
pdata(i*8+6 downto i*8)
<= data(i*8+6 downto i*8);
end generate;
end generate;
end generate;
mux_vbytes <= VBYTES_LOOKUP(to_integer(unsigned(word_size)))
when sel_pad = '1'
else (others => '1');
mux_ploc <= PLOC_LOOKUP(to_integer(unsigned(word_size)))
when (sel_pad = '1' and req_pad = '1')
else (others => '0');
mux_size <= '0' & word_size
when sel_pad = '1'
else (LOG2_WB => '1', others => '0');
process(clk)
begin
if rising_edge(clk) then
if (en_len = '1') then
vbytes <= mux_vbytes;
ploc <= mux_ploc;
size <= mux_size;
end if;
if (en_data = '1') then
if ((DSIZE > G_W) and (DSIZE MOD G_W) = 0) then
reg_data <= reg_data(DSIZE-G_W-1 downto 0) & pdata;
reg_vbytes<= reg_vbytes(DSIZE/8-WB-1 downto 0) & vbytes;
reg_ploc <= reg_ploc (DSIZE/8-WB-1 downto 0) & ploc;
elsif ((DSIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (DSIZE-1 downto (DSIZE MOD G_W )) <=
reg_data(DSIZE-G_W-1 downto (DSIZE MOD G_W))
& pdata2;
reg_vbytes(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_vbytes(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& vbytes2;
reg_ploc(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_ploc(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& ploc2;
else
reg_data ((DSIZE mod G_W)-1 downto 0) <=
pdata2(G_W -1 downto G_W /2);
reg_vbytes(((DSIZE/8) mod WB)-1 downto 0) <=
vbytes(WB-1 downto WB/2);
reg_ploc(((DSIZE/8) mod WB)-1 downto 0) <=
ploc2(WB-1 downto WB/2);
end if;
end if;
end if;
if (en_key = '1') then
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi_data;
end if;
end if;
end if;
end process;
--! =======================================================================
--! Registers with rst for controller and datapath
--! =======================================================================
gSyncRst:
if (not G_ASYNC_RSTN) generate
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
else
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end if;
end process;
end generate;
gAsyncRstn:
if (G_ASYNC_RSTN) generate
process(clk, rst)
begin
if (rst = '0') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
elsif rising_edge(clk) then
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end process;
end generate;
--! =======================================================================
--! Datapath (Output)
--! =======================================================================
pdi_ready <= pdi_rdy;
sdi_ready <= sdi_rdy;
--! Public
decrypt <= is_decrypt;
gDsizeEq:
if (not P_IS_BUFFER) generate
bdi <= pdata;
bdi_vld <= pdi_valid when (ps = S_DATA) else '0';
bdi_type <= sgmt_type(3 downto 1);
gNotCiph:
if (not G_CIPH_EXP) generate
bdi_eot <= sgmt_eot
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
end generate;
gCiph:
if (G_CIPH_EXP) generate
bdi_eot <= sgmt_eot or sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_lst
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= size;
bdi_valid_bytes <= vbytes;
bdi_pad_loc <= ploc;
end generate;
gDsizeNeq:
if (P_IS_BUFFER) generate
signal en_eoi_last : std_logic;
signal en_eot_last : std_logic;
begin
bdi <= reg_data;
bdi_vld <= reg_bdi_valid;
bdi_type <= sgmt_type(3 downto 1);
pEnd:
process(clk)
begin
if rising_edge(clk) then
if (ld_end = '1') then
if (not G_CIPH_EXP) then
bdi_eot <= sgmt_eot and sel_end;
bdi_eoi <= sgmt_eoi and sel_end;
else
bdi_eot <= (sgmt_eot or en_eot_last) and sel_end;
bdi_eoi <= (sgmt_eoi or en_eoi_last) and sel_end;
end if;
end if;
end if;
end process;
gCiph:
if (G_CIPH_EXP) generate
en_eot_last <= '1' when
((sgmt_eoi = '1' and sgmt_type = ST_NPUB)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_A
and G_PAD_AD /= 2 and G_PAD_AD /= 4)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_D
and G_PAD_D /= 2 and G_PAD_D /= 4))
else '0';
en_eoi_last <= '1' when en_eot_last = '1' and is_decrypt = '0'
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= reg_size;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
end generate;
bdi_valid <= bdi_vld;
--! Secret
gTsizeEq:
if (S_IS_BUFFER) generate
key_valid <= reg_key_valid;
key <= reg_key;
end generate;
gTsizeNeq:
if (not S_IS_BUFFER) generate
key_valid <= sdi_valid when (ss = S_DATA) else '0';
key <= sdi_data;
end generate;
key_update <= reg_key_update;
--! CMD FIFO
cmd <= pdi_data(G_W-1 downto G_W-5) & '0'
& pdi_data(G_W-7 downto G_W-8)
& pdi_data(G_W-17 downto G_W-32);
cmd_valid <= wr_cmd;
--! =======================================================================
--! Control
--! =======================================================================
process(clk)
begin
if rising_edge(clk) then
--! Operation register
if (ps = S_WAIT_INSTR) then
is_decrypt <= p_instr_opcode(0);
end if;
--! Length register
if (ld_sgmt_info = '1') then
sgmt_type <= p_sgmt_type;
if (G_CIPH_EXP) then
sgmt_pt <= p_sgmt_pt;
end if;
sgmt_eoi <= p_sgmt_eoi;
sgmt_eot <= p_sgmt_eot;
sgmt_lst <= p_sgmt_lst;
sgmt_len <= p_sgmt_len;
else
if (en_len = '1') then
if (sel_pad = '1') then
sgmt_len <= (others => '0');
else
sgmt_len <= std_logic_vector(unsigned(sgmt_len)-WB);
end if;
end if;
end if;
--! Padding activation register
if (en_len = '1') then
is_pad <= sel_pad;
end if;
--! Select zero register
if (ld_sgmt_info = '1')
or (P_IS_BUFFER and not A_EQ_D
and bdi_ready = '1' and unsigned(sgmt_len) > 0)
then
reg_sel_zero <= '0';
elsif (unsigned(sgmt_len) = 0 and en_len = '1')
or (not A_EQ_D and en_zero = '1')
then
reg_sel_zero <= '1';
end if;
--! Secret length register
if (ld_slen = '1') then
slen <= s_sgmt_len;
elsif (en_slen = '1') then
slen <= std_logic_vector(unsigned(slen)-G_KEY_SIZE/8);
end if;
--! Extra block register
if (ld_sgmt_info = '1' or (bdi_ready = '1' and bdi_vld = '1')) then
is_extra <= '0';
elsif (set_extra = '1') then
is_extra <= '1';
end if;
--! Public data input counter register
if (ld_ctr = '1') then
ctr <= (others => '0');
elsif (en_ctr = '1') then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
--! Secret data input counter register
if (ld_ctr2 = '1') then
ctr2 <= (others => '0');
elsif (en_ctr2 = '1') then
ctr2 <= std_logic_vector(unsigned(ctr2) + 1);
end if;
end if;
end process;
sel_pad <= '1' when (unsigned(sgmt_len) < WB) else '0';
word_size <= sgmt_len(LOG2_WB-1 downto 0);
--! HDR Dissection
p_instr_opcode <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_type <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_pt <= pdi_data(G_W-5);
p_sgmt_eoi <= pdi_data(G_W-6);
p_sgmt_eot <= pdi_data(G_W-7);
p_sgmt_lst <= pdi_data(G_W-8);
p_sgmt_len <= pdi_data(G_W-17 downto G_W-32);
s_instr_opcode <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_type <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_eot <= sdi_data(G_SW-7);
s_sgmt_lst <= sdi_data(G_SW-8);
s_sgmt_len <= sdi_data(G_SW-32+LOG2_KEYBYTES downto G_SW-32);
gPdiComb:
process(ps, p_instr_opcode, pdi_valid,
sgmt_len, sgmt_type, sgmt_eot, sgmt_lst,
p_sgmt_eot, p_sgmt_type,
bdi_ready, cmd_ready, reg_sel_zero,
is_extra, ctr)
begin
nps <= ps;
pdi_rdy <= '1';
set_key_upd <= '0';
set_req_pad <= '0';
ld_sgmt_info <= '0';
if (P_IS_BUFFER) then
ld_end <= '0';
set_extra <= '0';
end if;
ld_ctr <= '0';
en_data <= '0';
en_ps <= '0';
en_len <= '0';
en_ctr <= '0';
en_zero <= '0';
wr_cmd <= '0';
case ps is
when S_WAIT_INSTR =>
ld_ctr <= '1';
if (p_instr_opcode(3 downto 1) = OP_ENCDEC) then
nps <= S_WAIT_HDR;
end if;
if (p_instr_opcode = OP_ACTKEY) then
set_key_upd <= '1';
end if;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1') then
en_ps <= '1';
wr_cmd <= '1';
end if;
when S_WAIT_HDR =>
ld_sgmt_info <= '1';
nps <= S_PREP;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1' and cmd_ready = '1') then
en_ps <= '1';
if (p_sgmt_type(3 downto 2) = ST_D
or p_sgmt_type(3 downto 1) = ST_NSEC)
then
wr_cmd <= '1';
end if;
end if;
if (G_ENABLE_PAD) then
if (p_sgmt_eot = '1') then
if (p_sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 0)
or (p_sgmt_type(3 downto 2) = ST_D and G_PAD_D > 0)
then
set_req_pad <= '1';
end if;
end if;
end if;
when S_PREP =>
pdi_rdy <= '0';
--! state transition
if (unsigned(sgmt_len) = 0) then
if (G_ENABLE_PAD) and
--! Add a new block based on padding behavior
((sgmt_type(3 downto 2) = ST_A
and (G_PAD_AD = 2 or G_PAD_AD = 4))
or (sgmt_type(3 downto 2) = ST_D
and (G_PAD_D = 2 or G_PAD_D = 4)))
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
en_len <= '1';
en_ps <= '1';
when S_DATA =>
if (not P_IS_BUFFER) then
--! Without buffer
if (reg_sel_zero = '1'
or (not P_IS_BUFFER
and (pdi_valid = '0' or bdi_ready = '0')))
then
pdi_rdy <= '0';
end if;
if (unsigned(sgmt_len) = 0)
and not (req_pad = '1' and G_ENABLE_PAD
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D and G_PAD_D > 2)))
then
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
--! With buffer
if (reg_sel_zero = '1') then
pdi_rdy <= '0';
end if;
if (unsigned(ctr) = CNT_DWORDS-1) then
nps <= S_WAIT_READY;
end if;
if (unsigned(ctr) = CNT_DWORDS-2) then
ld_end <= '1';
end if;
if (unsigned(sgmt_len) = WB and G_ENABLE_PAD
and sgmt_eot = '1'
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D
and G_PAD_D > 2
and (not G_CIPH_EXP
or (G_CIPH_EXP and is_decrypt = '0')))))
then
if (A_EQ_D) then
if unsigned(ctr) = CNT_DWORDS-2 then
set_extra <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) = CNT_AWORDS-2)
or (sgmt_type(3 downto 2) = ST_D
and unsigned(ctr) = CNT_DWORDS-2))
then
set_extra <= '1';
end if;
end if;
end if;
--! if ASIZE < DSIZE
if (not A_EQ_D) then
if (sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) >= CNT_AWORDS-1)
then
en_zero <= '1';
end if;
end if;
end if;
if (reg_sel_zero = '1'
or (pdi_valid = '1'
and (P_IS_BUFFER
or (not P_IS_BUFFER and bdi_ready = '1'))))
then
if (sgmt_type(3 downto 2) /= ST_A
and sgmt_type(3 downto 2) /= ST_D)
then
--! Not AD or D segment
if (P_IS_BUFFER) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
en_len <= '1';
end if;
else
--! AD or D segment
if (P_IS_BUFFER) then
if (A_EQ_D) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) < CNT_AWORDS-1)
or (sgmt_type(3 downto 2) /= ST_A
and unsigned(ctr) /= CNT_DWORDS-1))
then
en_len <= '1';
end if;
end if;
else
en_len <= '1';
end if;
end if;
if (P_IS_BUFFER) then
en_ctr <= '1';
en_data <= '1';
end if;
en_ps <= '1';
end if;
when S_WAIT_READY =>
pdi_rdy <= '0';
ld_ctr <= '1';
if (unsigned(sgmt_len) = 0) then
if ((G_ENABLE_PAD and (G_PAD_AD > 2 or G_PAD_D > 2))
and is_extra = '1')
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
if (bdi_ready = '1') then
en_len <= '1';
en_ps <= '1';
end if;
end case;
end process;
sel_end <= '1' when (unsigned(sgmt_len) <= WB
and (is_extra = '0' and set_extra = '0'))
else '0';
gSdiComb:
process(ss, s_instr_opcode, sdi_valid, ctr2, key_ready, slen)
begin
nss <= ss;
sdi_rdy <= '0';
en_key <= '0';
ld_ctr2 <= '0';
ld_slen <= '0';
en_ctr2 <= '0';
en_slen <= '0';
en_ss <= '0';
case ss is
when S_WAIT_INSTR =>
ld_ctr2 <= '1';
sdi_rdy <= '1';
if (s_instr_opcode = OP_LDKEY) then
nss <= S_WAIT_HDR;
end if;
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_WAIT_HDR =>
nss <= S_DATA;
ld_slen <= '1';
sdi_rdy <= '1';
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_DATA =>
if (not S_IS_BUFFER) then
nss <= S_WAIT_INSTR;
if (sdi_valid = '1' and key_ready = '1') then
en_slen <= '1';
sdi_rdy <= '1';
if (unsigned(slen) = G_KEY_SIZE/8) then
en_ss <= '1';
end if;
end if;
else
sdi_rdy <= '1';
nss <= S_WAIT_READY;
if (sdi_valid = '1') then
en_ctr2 <= '1';
en_key <= '1';
if (unsigned(ctr2) = CNT_KWORDS-1) then
en_ss <= '1';
end if;
end if;
end if;
when S_WAIT_READY =>
if (unsigned(slen) = G_KEY_SIZE/8) then
nss <= S_WAIT_INSTR;
else
nss <= S_DATA;
end if;
ld_ctr2 <= '1';
if (key_ready = '1') then
en_ss <= '1';
en_slen <= '1';
end if;
end case;
end process;
end architecture structure;
| apache-2.0 | 899462ab3615c2fe994f1556dbdac33b | 0.380811 | 4.119437 | false | false | false | false |
hoangt/PoC | tb/arith/arith_prefix_or_tb.vhdl | 2 | 2,308 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for arith_prefix_or.
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith.prefix_or
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity arith_prefix_or_tb is
end arith_prefix_or_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.simulation.ALL;
architecture tb of arith_prefix_or_tb is
-- component generics
constant N : positive := 8;
-- component ports
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic_vector(N-1 downto 0);
begin -- tb
-- component instantiation
DUT: entity PoC.arith_prefix_or
generic map (
N => N
)
port map (
x => x,
y => y
);
-- Stimuli
process
begin
-- Exhaustive Testing
for i in NATURAL range 0 to 2**N-1 loop
x <= std_logic_vector(to_unsigned(i, N));
wait for 10 ns;
for j in 0 to N-1 loop
tbAssert((y(j) = '1') = (x(j downto 0) /= (j downto 0 => '0')),
"Wrong result for "&integer'image(i)&" / "&integer'image(j));
end loop;
end loop;
-- Report overall result
tbPrintResult;
wait; -- forever
end process;
end tb;
| apache-2.0 | bdfaacf74aed60aa9e0f3d9bc53d6a63 | 0.577556 | 3.821192 | false | false | false | false |
hoangt/PoC | src/misc/sync/sync_Reset_Xilinx.vhdl | 2 | 3,581 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Reset_Xilinx
--
-- Description:
-- ------------------------------------
-- This is a clock-domain-crossing circuit for reset signals optimized for
-- Xilinx FPGAs. It utilizes two 'FDP' instances from UniSim.vComponents. If
-- you need a platform independent version of this synchronizer, please use
-- 'PoC.misc.sync.sync_Reset', which internally instantiates this module if
-- a Xilinx FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for reset signals.
--
-- CONSTRAINTS:
-- This relative placement of the internal sites is constrained by RLOCs.
--
-- Xilinx ISE UCF or XCF file:
-- NET "*_async" TIG;
-- INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS";
-- TIMESPEC "TS_MetaStability" = FROM FFS TO "METASTABILITY_FFS" TIG;
--
-- Xilinx Vivado xdc file:
-- TODO
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UniSim;
use UniSim.VComponents.all;
entity sync_Reset_Xilinx is
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC; -- high active asynchronous reset
Output : out STD_LOGIC -- "Synchronised" reset signal
);
end entity;
architecture rtl of sync_Reset_Xilinx is
attribute ASYNC_REG : STRING;
attribute SHREG_EXTRACT : STRING;
attribute RLOC : STRING;
signal Reset_async : STD_LOGIC;
signal Reset_meta : STD_LOGIC;
signal Reset_sync : STD_LOGIC;
-- Mark register "Reset_meta" and "Output" as asynchronous
attribute ASYNC_REG of Reset_meta : signal is "TRUE";
attribute ASYNC_REG of Reset_sync : signal is "TRUE";
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of Reset_meta : signal is "NO";
attribute SHREG_EXTRACT of Reset_sync : signal is "NO";
-- Assign synchronization FF pairs to the same slice -> minimal routing delay
attribute RLOC of Reset_meta : signal is "X0Y0";
attribute RLOC of Reset_sync : signal is "X0Y0";
begin
Reset_async <= Input;
FF2_METASTABILITY_FFS : FDP
generic map (
INIT => '1'
)
port map (
C => Clock,
PRE => Reset_async,
D => '0',
Q => Reset_meta
);
FF3_METASTABILITY_FFS : FDP
generic map (
INIT => '1'
)
port map (
C => Clock,
PRE => Reset_async,
D => Reset_meta,
Q => Reset_sync
);
Output <= Reset_sync;
end architecture;
| apache-2.0 | 43a601c547b12407a38bd27a28ab0ec6 | 0.614912 | 3.563184 | false | false | false | false |
hoangt/PoC | src/misc/stat/stat_Minimum.vhdl | 2 | 5,264 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Counts the least significant data words
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
entity stat_Minimum is
generic (
DEPTH : POSITIVE := 8;
DATA_BITS : POSITIVE := 16;
COUNTER_BITS : POSITIVE := 16
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Valids : out STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
Minimums : out T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0);
Counts : out T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0)
);
end entity;
architecture rtl of stat_Minimum is
type T_TAG_MEMORY is array(NATURAL range <>) of UNSIGNED(DATA_BITS - 1 downto 0);
type T_COUNTER_MEMORY is array(NATURAL range <>) of UNSIGNED(COUNTER_BITS - 1 downto 0);
-- create matrix from vector-vector
function to_slm(usv : T_TAG_MEMORY) return t_slm is
variable slm : t_slm(usv'range, DATA_BITS - 1 downto 0);
begin
for i in usv'range loop
for j in DATA_BITS - 1 downto 0 loop
slm(i, j) := usv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(usv : T_COUNTER_MEMORY) return t_slm is
variable slm : t_slm(usv'range, COUNTER_BITS - 1 downto 0);
begin
for i in usv'range loop
for j in COUNTER_BITS - 1 downto 0 loop
slm(i, j) := usv(i)(j);
end loop;
end loop;
return slm;
end function;
signal DataIn_us : UNSIGNED(DataIn'range);
signal TagHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal MinimumHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal TagMemory : T_TAG_MEMORY(DEPTH - 1 downto 0) := (others => (others => '1'));
signal CounterMemory : T_COUNTER_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0'));
signal MinimumIndex : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := ((DEPTH - 1) => '1', others => '0');
signal ValidMemory : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := (others => '0');
begin
DataIn_us <= unsigned(DataIn);
genTagHit : for i in 0 to DEPTH - 1 generate
TagHit(i) <= to_sl(TagMemory(i) = DataIn_us);
MinimumHit(i) <= to_sl(TagMemory(i) > DataIn_us);
end generate;
process(Clock)
variable NewMinimum_nxt : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
variable NewMinimum_idx : NATURAL;
variable TagHit_idx : NATURAL;
begin
NewMinimum_nxt := MinimumIndex(MinimumIndex'high - 1 downto 0) & MinimumIndex(MinimumIndex'high);
NewMinimum_idx := to_index(onehot2bin(NewMinimum_nxt));
TagHit_idx := to_index(onehot2bin(TagHit));
if rising_edge(Clock) then
if (Reset = '1') then
ValidMemory <= (others => '0');
elsif ((slv_nand(ValidMemory) and slv_nor(TagHit) and Enable) = '1') then
for i in DEPTH - 1 downto 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= TagMemory(i - 1);
ValidMemory(i) <= ValidMemory(i - 1);
CounterMemory(i) <= CounterMemory(i - 1);
end if;
end loop;
for i in 0 to DEPTH - 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= DataIn_us;
ValidMemory(i) <= '1';
CounterMemory(i) <= to_unsigned(1, COUNTER_BITS);
exit;
end if;
end loop;
elsif ((slv_or(MinimumHit) and slv_nor(TagHit) and Enable) = '1') then
for i in DEPTH - 1 downto 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= TagMemory(i - 1);
ValidMemory(i) <= ValidMemory(i - 1);
CounterMemory(i) <= CounterMemory(i - 1);
end if;
end loop;
for i in 0 to DEPTH - 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= DataIn_us;
ValidMemory(i) <= '1';
CounterMemory(i) <= to_unsigned(1, COUNTER_BITS);
exit;
end if;
end loop;
elsif ((slv_or(TagHit) and Enable)= '1') then
CounterMemory(TagHit_idx) <= CounterMemory(TagHit_idx) + 1;
end if;
end if;
end process;
Valids <= ValidMemory;
Minimums <= to_slm(TagMemory);
Counts <= to_slm(CounterMemory);
end architecture;
| apache-2.0 | c8c67262923c35024c2f32a7ebc91553 | 0.605813 | 3.138939 | false | false | false | false |
IAIK/ascon_hardware | asconv1/ascon_128_xlow_area/ascon_shift_register_w_overwrite.vhdl | 1 | 3,013 | -------------------------------------------------------------------------------
-- Title : Ascon Shift Register
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_shift_register.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2014-05-20
-- Last update: 2014-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-20 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon_shift_register_w_overwrite is
generic (
RESET_VALUE : std_logic_vector(63 downto 0) := x"0000000000000000";
DATA_WIDTH : integer := 64);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
OverwriteENxSI : in std_logic;
OverwriteDataxSI : in std_logic_vector(DATA_WIDTH-1 downto 0);
ShiftEnablexSI : in std_logic;
ShiftRegINxDI : in std_logic;
ShiftRegOUTxDO : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity ascon_shift_register_w_overwrite;
architecture structural of ascon_shift_register_w_overwrite is
signal DataxDP : std_logic_vector(DATA_WIDTH-1 downto 0);
begin -- architecture structural
ShiftRegOUTxDO <= DataxDP;
-- purpose: Left shift each cycle
-- type : sequential
-- inputs : ClkxCI, RstxRBI
-- outputs: DataOUTxDO
shift_p: process (ClkxCI, RstxRBI) is
begin -- process shift_p
if RstxRBI = '0' then -- asynchronous reset (active low)
DataxDP <= RESET_VALUE;
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if OverwriteENxSI = '1' then -- Overwrite register
DataxDP <= OverwriteDataxSI;
elsif ShiftEnablexSI = '1' then
DataxDP <= DataxDP(DATA_WIDTH-2 downto 0) & ShiftRegINxDI; -- shift left
end if;
end if;
end process shift_p;
end architecture structural;
| apache-2.0 | 950f94702fa8e29cae48faad2bb5693d | 0.549286 | 4.579027 | false | false | false | false |
hoangt/PoC | src/common/strings.vhdl | 1 | 30,106 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
| apache-2.0 | fa6297be53ef78b023ff14ebdd7fcbf4 | 0.631701 | 3.224376 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_addr_gen.vhd | 4 | 23,323 | -------------------------------------------------------------------------------
-- axi_emc_addr_gen - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_addr_gen.vhd
-- Version: v2.0
-- Description: This file includes the logic for address generataion on
-- IP interface based upon the AXI transactions.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10
-- ~~~~~~
-- -- Created the new version v1.01.a
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_misc.and_reduce;
-------------------------------------------------------------------------------
entity axi_emc_addr_gen is
generic(
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer range 32 to 64 := 32
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Cre_reg_en : in std_logic;
-- combo I/P signals
stop_addr_incr : in std_logic;
Store_addr_info_cmb : in std_logic;
Addr_int_cmb : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack : in std_logic;
Fifo_full_1 : in std_logic;
derived_len_reg : in std_logic_vector(3 downto 0);
Rst_Rd_CE : in std_logic;
-- registered signals
Derived_burst_reg : in std_logic_vector(1 downto 0);
Derived_size_reg : in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0)
);
end entity axi_emc_addr_gen;
-----------------------
------------------------------------
architecture imp of axi_emc_addr_gen is
------------------------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant ACTIVE_LOW_RESET : integer := 0;
signal bus2ip_addr_i : std_logic_vector
((C_S_AXI_MEM_ADDR_WIDTH-1) downto ((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1)) := (OTHERS => '0');
signal int_addr_enable_11_2 : std_logic;
signal addr_sel_0 : std_logic;
signal addr_sel_1 : std_logic;
signal addr_sel_2 : std_logic;
signal addr_sel_3 : std_logic;
signal Bus2IP_Addr_lower_bits_reg_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits_cmb_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
-----
begin
-----
---====================---
--*** axi_emc_addr_gen logic ***--
---====================---
--bus2ip_addr_i (0) <= '0';
--bus2ip_addr_i (1) <= '0';
Bus2IP_Addr <= bus2ip_addr_i((C_S_AXI_MEM_ADDR_WIDTH-1) downto (clog2(C_S_AXI_MEM_DATA_WIDTH/8))) & Bus2IP_Addr_lower_bits;
Bus2IP_Addr_lower_bits <= Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0)
when Cre_reg_en = '0'
else
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
----------- all addresses are word/dword aligned addresses, only the BE decide
-- which byte lane to be accessed
Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
---------------------------------------------------------------------------------
-- ADDR_BITS_LAST_3_OR_3_BITS_REG_P: Address registering for lower 3 or 2 bits
---------------------
ADDR_BITS_LAST_3_OR_3_BITS_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= Addr_int_cmb(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
end if;
end if;
end process ADDR_BITS_LAST_3_OR_3_BITS_REG_P;
----------------------------------
-- ADDR_BITS_31_12_REG_P: Address registering for upper order address bits
---------------------
ADDR_BITS_31_12_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(31 downto 12) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
bus2ip_addr_i(31 downto 12) <= Addr_int_cmb(31 downto 12);
end if;
end if;
end process ADDR_BITS_31_12_REG_P;
----------------------------------
int_addr_enable_11_2 <= ( Store_addr_info_cmb
or
(Ip2Bus_Addr_ack and
(not Fifo_full_1) and (not stop_addr_incr)
)
);
----------- Below are the select line for MUX operation
addr_sel_0 <= (derived_len_reg(0) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_1 <= (derived_len_reg(1) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_2 <= (derived_len_reg(2) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_3 <= (derived_len_reg(3) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
-----------
--------------------------------------
--BUS2IP_ADDR_GEN_DATA_WDTH_32:Address geenration for logic for 32 bit data bus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_32: if C_S_AXI_MEM_DATA_WIDTH = 32 generate
----------------------------
-- address(2) calculation
signal calc_addr_2: std_logic_vector(1 downto 0);
signal addr_2_int : std_logic;
signal addr_2_cmb : std_logic;
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(11:6) calculation
signal calc_addr_11_6: std_logic_vector(6 downto 0);
signal addr_11_6_int : std_logic_vector(5 downto 0);
signal addr_11_6_cmb : std_logic_vector(5 downto 0);
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic_vector(1 downto 0);
signal addr_6_cmb : std_logic_vector(1 downto 0);
signal address_carry : std_logic;
signal internal_count : std_logic_vector(2 downto 0) :=(others => '0');
-----
begin
-----
-------------------
-- INT_COUNTER_P32: to store the the internal address lower bits
-------------------
INT_COUNTER_P32: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb='1') then
internal_count <= '0' & Addr_int_cmb(1 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end process INT_COUNTER_P32;
-------------------
address_Carry <= Derived_size_reg(1) or
(Derived_size_reg(0) and internal_count(1))or
(internal_count(0) and internal_count(1));
calc_addr_2 <= ('0' & bus2ip_addr_i(2)) + ('0' & address_Carry);
addr_2_int <= calc_addr_2(0) when (addr_sel_0='1') else bus2ip_addr_i(2);
addr_2_cmb <= Addr_int_cmb(2) when (Store_addr_info_cmb='1') else addr_2_int;
-- ADDR_BITS_2_REG_P: store the 2nd address bit
------------------
ADDR_BITS_2_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(2) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(2) <= addr_2_cmb;
end if;
end if;
end process ADDR_BITS_2_REG_P;
------------------
calc_addr_3 <= ('0' & bus2ip_addr_i(3)) + ('0' & calc_addr_2(1));
addr_3_int <= calc_addr_3(0) when (addr_sel_1='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the third address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_2='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store the 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & bus2ip_addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_3='1') else bus2ip_addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P:store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_11_6 <= ('0'& bus2ip_addr_i(11 downto 6)) +
("000000" & calc_addr_5(1));
addr_11_6_int <= calc_addr_11_6(5 downto 0) when (Derived_burst_reg(0)='1')
else
bus2ip_addr_i(11 downto 6);
addr_11_6_cmb <= Addr_int_cmb(11 downto 6) when(Store_addr_info_cmb='1')
else
addr_11_6_int(5 downto 0);
-- ADDR_BITS_11_6_REG_P: store the 11 to 6 address bits
--------------------
ADDR_BITS_11_6_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(11 downto 6) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 6) <= addr_11_6_cmb(5 downto 0);
end if;
end if;
end process ADDR_BITS_11_6_REG_P;
---------------------------------
------------------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_32;
------------------------------------------
-- BUS2IP_ADDR_GEN_DATA_WDTH_64: below address logic is used for 64 bit dbus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_64: if C_S_AXI_MEM_DATA_WIDTH = 64 generate
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic;
signal addr_6_cmb : std_logic;
-- address(7) calculation
signal calc_addr_7: std_logic_vector(1 downto 0);
signal addr_7_int : std_logic;
signal addr_7_cmb : std_logic;
-- address(11:7) calculation
signal calc_addr_11_7: std_logic_vector(5 downto 0);
signal addr_11_7_int : std_logic_vector(4 downto 0);
signal addr_11_7_cmb : std_logic_vector(4 downto 0);
signal address_carry : std_logic;
signal internal_count: std_logic_vector(3 downto 0):=(others => '0');
-----
begin
-----
--------------------
-- INT_COUNTER_P64: to store the internal address bits
--------------------
INT_COUNTER_P64: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb = '1') then
internal_count <= '0' & Addr_int_cmb(2 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
if(Derived_size_reg(1) = '1') then
internal_count <= internal_count + "100";
else
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end if;
end process INT_COUNTER_P64;
----------------------------
address_Carry<=(Derived_size_reg(1) and Derived_size_reg(0)) or -- for double word
(Derived_size_reg(1) and internal_count(2) ) or -- for word
(Derived_size_reg(0) and
internal_count(2) and
internal_count(1)
)or -- for half word
(internal_count(2) and
internal_count(1) and
internal_count(0)
); -- for byte
calc_addr_3 <= ('0' & Bus2IP_Addr_i(3)) + ('0' & address_Carry);
addr_3_int <= calc_addr_3(0) when (addr_sel_0='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the 3rd address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0'))) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_1='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store teh 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & Bus2IP_Addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_2='1') else Bus2IP_Addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P: store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_6 <= ('0' & Bus2IP_Addr_i(6)) + ('0' & calc_addr_5(1));
addr_6_int <= calc_addr_6(0) when (addr_sel_3='1') else Bus2IP_Addr_i(6);
addr_6_cmb <= Addr_int_cmb(6) when (Store_addr_info_cmb='1') else addr_6_int;
-- ADDR_BITS_6_REG_P: store the 6th address bit
------------------
ADDR_BITS_6_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(6) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(6) <= addr_6_cmb;
end if;
end if;
end process ADDR_BITS_6_REG_P;
------------------
calc_addr_11_7 <= ('0' & Bus2IP_Addr_i(11 downto 7))
+ ("00000" & calc_addr_6(1));
addr_11_7_int <= calc_addr_11_7(4 downto 0) when (Derived_burst_reg(0)='1')
else
Bus2IP_Addr_i(11 downto 7);
addr_11_7_cmb <= Addr_int_cmb(11 downto 7) when(Store_addr_info_cmb='1')
else
addr_11_7_int(4 downto 0);
-- ADDR_BITS_11_7_REG_P: store the 11 to 7 address bits
--------------------
ADDR_BITS_11_7_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(11 downto 7) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 7) <= addr_11_7_cmb(4 downto 0);
end if;
end if;
end process ADDR_BITS_11_7_REG_P;
---------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_64;
-------------------------------------------------------------------------------
end imp;
| gpl-3.0 | c63f1aba9d6ed11cd109d1774c9fe7eb | 0.523518 | 3.363086 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/bufg/bufgmux_fpga.vhd | 2 | 993 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Clock multiplexer with buffered output for Xilinx FPGA.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufgmux_fpga is
generic (
tmode_always_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of bufgmux_fpga is
begin
good : if not tmode_always_ena generate
mux_buf : BUFGMUX
port map (
O => O,
I0 => I1,
I1 => I2,
S => S
);
end generate;
bad : if tmode_always_ena generate
mux_buf : BUFG
port map (
O => O,
I => I2
);
end generate;
end;
| bsd-2-clause | bd16c260118bb2b8e4aed44657644952 | 0.48137 | 4.020243 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/pll/clkp90_tech.vhd | 2 | 2,149 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Virtual clock phase offset generator (90 deg)
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkp90_tech is
generic (
tech : integer range 0 to NTECH := 0;
--! clock frequency in KHz
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_tech;
architecture rtl of clkp90_tech is
component clkp90_virtex6 is
port (
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic
);
end component;
component clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end component;
begin
xv6 : if tech = virtex6 generate
v1 : clkp90_virtex6 port map (
i_clk => i_clk,
o_clk => o_clk,
o_clkp90 => o_clkp90
);
o_clk2x <= '0';
o_lock <= '0';
end generate;
xl7 : if tech = kintex7 or tech = artix7 or tech = zynq7000 generate
v1 : clkp90_kintex7 generic map (
freq => freq
) port map (
i_rst => i_rst,
i_clk => i_clk,
o_clk => o_clk,
o_clkp90 => o_clkp90,
o_clk2x => o_clk2x,
o_lock => o_lock
);
end generate;
inf : if tech = inferred generate
o_clk <= i_clk;
o_clkp90 <= i_clk;
o_clk2x <= '0';
o_lock <= '0';
end generate;
m180 : if tech = micron180 generate
end generate;
end;
| bsd-2-clause | 22ec3f47ba7d3a1a92922e529c83f8ca | 0.503955 | 3.427432 | false | false | false | false |
hoangt/PoC | src/io/ddrio/ddrio_in_altera.vhdl | 2 | 2,240 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Input Registers for Altera FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.in for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library Altera_mf;
use Altera_mf.Altera_MF_Components.all;
entity ddrio_in_xilinx is
generic (
BITS : POSITIVE;
INIT_VALUE_HIGH : BIT_VECTOR := "1";
INIT_VALUE_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_in_xilinx is
begin
iff : altddio_in
generic map (
WIDTH => BITS,
INTENDED_DEVICE_FAMILY => "STRATIXII" -- TODO: built device string from PoC.config information
)
port map (
inclock => Clock,
inclocken => ClockEnable,
dataout_h => DataIn_high,
dataout_l => DataIn_low,
datain => Pad
);
end architecture;
| apache-2.0 | d5dc99655c2a5f05603c0d2204535ad1 | 0.595089 | 3.666121 | false | false | false | false |
BogdanArdelean/FPWAM | hardware/src/hdl/GPR.vhd | 1 | 1,976 | -------------------------------------------------------------------------------
-- FILE NAME : GPR.vhd
-- MODULE NAME : GPR
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : General Purpose Registers
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity GPR is
generic
(
kAddressWidth : natural := 4;
kWordWidth : natural := 16
);
port
(
--Common
clk : in std_logic;
address1 : in std_logic_vector(kAddressWidth - 1 downto 0);
wr1 : in std_logic;
input_word1 : in std_logic_vector(kWordWidth - 1 downto 0);
output_word1 : out std_logic_vector(kWordWidth - 1 downto 0);
address2 : in std_logic_vector(kAddressWidth - 1 downto 0);
wr2 : in std_logic;
input_word2 : in std_logic_vector(kWordWidth - 1 downto 0);
output_word2 : out std_logic_vector(kWordWidth - 1 downto 0)
);
end GPR;
architecture Behavioral of GPR is
type sram is array (0 to 2**kAddressWidth) of std_logic_vector(kWordWidth - 1 downto 0);
signal RAM : sram := (others => (others => '0'));
begin
WRITE_PROCESS: process(clk)
begin
if rising_edge(clk) then
if wr1 = '1' then
RAM(to_integer(unsigned(address1))) <= input_word1;
end if;
if wr2 = '1' then
RAM(to_integer(unsigned(address2))) <= input_word2;
end if;
end if;
end process;
output_word1 <= RAM(to_integer(unsigned(address1)));
output_word2 <= RAM(to_integer(unsigned(address2)));
end Behavioral;
| apache-2.0 | 9276d9aafcfddf4d61c9f3d2a7f5e22b | 0.529352 | 4.02444 | false | false | false | false |
hoangt/PoC | src/arith/arith_counter_ring.vhdl | 2 | 2,530 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: TODO
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY PoC;
USE PoC.utils.ALL;
ENTITY arith_counter_ring IS
GENERIC (
BITS : POSITIVE;
INVERT_FEEDBACK : BOOLEAN := FALSE -- FALSE -> ring counter; TRUE -> johnson counter
);
PORT (
Clock : IN STD_LOGIC; -- Clock
Reset : IN STD_LOGIC; -- Reset
seed : IN STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0'); -- initial counter vector / load value
inc : IN STD_LOGIC := '0'; -- increment counter
dec : IN STD_LOGIC := '0'; -- decrement counter
value : OUT STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) -- counter value
);
END;
ARCHITECTURE rtl OF arith_counter_ring IS
CONSTANT INVERT : STD_LOGIC := to_sl(INVERT_FEEDBACK);
SIGNAL counter : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS(Clock)
BEGIN
IF rising_edge(Clock) THEN
IF (Reset = '1') THEN
counter <= seed;
ELSE
IF (inc = '1') THEN
counter <= counter(counter'high - 1 DOWNTO 0) & (counter(counter'high) XOR INVERT);
ELSIF (dec = '1') THEN
counter <= (counter(0) XOR INVERT) & counter(counter'high DOWNTO 1);
END IF;
END IF;
END IF;
END PROCESS;
value <= counter;
END;
| apache-2.0 | c56475d441b2b3c113fbe3f1789df462 | 0.56087 | 3.635057 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/pulse_synchronizer.vhd | 4 | 6,428 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
| gpl-3.0 | e6f29fa8905f425ff34a098fd02765e8 | 0.55336 | 4.215082 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/mux_onehot_f.vhd | 4 | 12,287 | -- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| gpl-3.0 | 69290c0b1b6c088961a110910280dc8c | 0.437373 | 4.792122 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_mii_to_rmii_0_0/synth/design_1_mii_to_rmii_0_0.vhd | 2 | 7,547 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mii_to_rmii:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mii_to_rmii_v2_0;
USE mii_to_rmii_v2_0.mii_to_rmii;
ENTITY design_1_mii_to_rmii_0_0 IS
PORT (
rst_n : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
mac2rmii_tx_en : IN STD_LOGIC;
mac2rmii_txd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mac2rmii_tx_er : IN STD_LOGIC;
rmii2mac_tx_clk : OUT STD_LOGIC;
rmii2mac_rx_clk : OUT STD_LOGIC;
rmii2mac_col : OUT STD_LOGIC;
rmii2mac_crs : OUT STD_LOGIC;
rmii2mac_rx_dv : OUT STD_LOGIC;
rmii2mac_rx_er : OUT STD_LOGIC;
rmii2mac_rxd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy2rmii_crs_dv : IN STD_LOGIC;
phy2rmii_rx_er : IN STD_LOGIC;
phy2rmii_rxd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_txd : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_tx_en : OUT STD_LOGIC
);
END design_1_mii_to_rmii_0_0;
ARCHITECTURE design_1_mii_to_rmii_0_0_arch OF design_1_mii_to_rmii_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT mii_to_rmii IS
GENERIC (
C_INSTANCE : STRING;
C_FIXED_SPEED : STD_LOGIC;
C_SPEED_100 : STD_LOGIC
);
PORT (
rst_n : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
mac2rmii_tx_en : IN STD_LOGIC;
mac2rmii_txd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mac2rmii_tx_er : IN STD_LOGIC;
rmii2mac_tx_clk : OUT STD_LOGIC;
rmii2mac_rx_clk : OUT STD_LOGIC;
rmii2mac_col : OUT STD_LOGIC;
rmii2mac_crs : OUT STD_LOGIC;
rmii2mac_rx_dv : OUT STD_LOGIC;
rmii2mac_rx_er : OUT STD_LOGIC;
rmii2mac_rxd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy2rmii_crs_dv : IN STD_LOGIC;
phy2rmii_rx_er : IN STD_LOGIC;
phy2rmii_rxd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_txd : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_tx_en : OUT STD_LOGIC
);
END COMPONENT mii_to_rmii;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "mii_to_rmii,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mii_to_rmii_0_0_arch : ARCHITECTURE IS "design_1_mii_to_rmii_0_0,mii_to_rmii,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "design_1_mii_to_rmii_0_0,mii_to_rmii,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mii_to_rmii,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_INSTANCE=design_1_mii_to_rmii_0_0,C_FIXED_SPEED=1,C_SPEED_100=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
ATTRIBUTE X_INTERFACE_INFO OF ref_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_txd: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_tx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_ER";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rxd: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_crs_dv: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M CRS_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_rx_er: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_rxd: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M RXD";
ATTRIBUTE X_INTERFACE_INFO OF rmii2phy_txd: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M TXD";
ATTRIBUTE X_INTERFACE_INFO OF rmii2phy_tx_en: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M TX_EN";
BEGIN
U0 : mii_to_rmii
GENERIC MAP (
C_INSTANCE => "design_1_mii_to_rmii_0_0",
C_FIXED_SPEED => '1',
C_SPEED_100 => '1'
)
PORT MAP (
rst_n => rst_n,
ref_clk => ref_clk,
mac2rmii_tx_en => mac2rmii_tx_en,
mac2rmii_txd => mac2rmii_txd,
mac2rmii_tx_er => mac2rmii_tx_er,
rmii2mac_tx_clk => rmii2mac_tx_clk,
rmii2mac_rx_clk => rmii2mac_rx_clk,
rmii2mac_col => rmii2mac_col,
rmii2mac_crs => rmii2mac_crs,
rmii2mac_rx_dv => rmii2mac_rx_dv,
rmii2mac_rx_er => rmii2mac_rx_er,
rmii2mac_rxd => rmii2mac_rxd,
phy2rmii_crs_dv => phy2rmii_crs_dv,
phy2rmii_rx_er => phy2rmii_rx_er,
phy2rmii_rxd => phy2rmii_rxd,
rmii2phy_txd => rmii2phy_txd,
rmii2phy_tx_en => rmii2phy_tx_en
);
END design_1_mii_to_rmii_0_0_arch;
| gpl-3.0 | c83a9d61ec25c9e2f4641ec89b671480 | 0.707566 | 3.15642 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_emc_0_0/synth/design_1_axi_emc_0_0.vhd | 2 | 25,548 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_emc:3.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_emc_v3_0;
USE axi_emc_v3_0.axi_emc;
ENTITY design_1_axi_emc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_axi_emc_0_0;
ARCHITECTURE design_1_axi_emc_0_0_arch OF design_1_axi_emc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_emc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_AXI_CLK_PERIOD_PS : INTEGER;
C_LFLASH_PERIOD_PS : INTEGER;
C_LINEAR_FLASH_SYNC_BURST : INTEGER;
C_S_AXI_REG_ADDR_WIDTH : INTEGER;
C_S_AXI_REG_DATA_WIDTH : INTEGER;
C_S_AXI_EN_REG : INTEGER;
C_S_AXI_MEM_ADDR_WIDTH : INTEGER;
C_S_AXI_MEM_DATA_WIDTH : INTEGER;
C_S_AXI_MEM_ID_WIDTH : INTEGER;
C_S_AXI_MEM0_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM0_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_HIGHADDR : STD_LOGIC_VECTOR;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_NUM_BANKS_MEM : INTEGER;
C_MEM0_TYPE : INTEGER;
C_MEM1_TYPE : INTEGER;
C_MEM2_TYPE : INTEGER;
C_MEM3_TYPE : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_PARITY_TYPE_MEM_0 : INTEGER;
C_PARITY_TYPE_MEM_1 : INTEGER;
C_PARITY_TYPE_MEM_2 : INTEGER;
C_PARITY_TYPE_MEM_3 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TWPH_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_WR_REC_TIME_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TWPH_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_WR_REC_TIME_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TWPH_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_WR_REC_TIME_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TWPH_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_WR_REC_TIME_MEM_3 : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_reg_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_awvalid : IN STD_LOGIC;
s_axi_reg_awready : OUT STD_LOGIC;
s_axi_reg_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_reg_wvalid : IN STD_LOGIC;
s_axi_reg_wready : OUT STD_LOGIC;
s_axi_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_bvalid : OUT STD_LOGIC;
s_axi_reg_bready : IN STD_LOGIC;
s_axi_reg_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_arvalid : IN STD_LOGIC;
s_axi_reg_arready : OUT STD_LOGIC;
s_axi_reg_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_rvalid : OUT STD_LOGIC;
s_axi_reg_rready : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_parity_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_emc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "axi_emc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_emc_0_0_arch : ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_emc,x_ipVersion=3.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_emc_inst,C_AXI_CLK_PERIOD_PS=10000,C_LFLASH_PERIOD_PS=10000,C_LINEAR_FLASH_SYNC_BURST=0,C_S_AXI_REG_ADDR_WIDTH=5,C_S_AXI_REG_DATA_WIDTH=32,C_S_AXI_EN_REG=0,C_S_AXI_MEM_ADDR_WIDTH=32,C_S_AXI_MEM_DATA_WIDTH=32,C_S_AXI_MEM_ID_WIDTH=1,C_S_AXI_MEM0_BASEADDR=0x60000000,C_S_AXI_MEM0_HIGHADDR=0x60FFFFFF,C_S_AXI_MEM1_BASEADDR=0xB0000000,C_S_AXI_MEM1_HIGHADDR=0xBFFFFFFF,C_S_AXI_MEM2_BASEADDR=0xC0000000,C_S_AXI_MEM2_HIGHADDR=0xCFFFFFFF,C_S_AXI_MEM3_BASEADDR=0xD0000000,C_S_AXI_MEM3_HIGHADDR=0xDFFFFFFF,C_INCLUDE_NEGEDGE_IOREGS=0,C_NUM_BANKS_MEM=1,C_MEM0_TYPE=1,C_MEM1_TYPE=0,C_MEM2_TYPE=0,C_MEM3_TYPE=0,C_MEM0_WIDTH=16,C_MEM1_WIDTH=16,C_MEM2_WIDTH=16,C_MEM3_WIDTH=16,C_MAX_MEM_WIDTH=16,C_PARITY_TYPE_MEM_0=0,C_PARITY_TYPE_MEM_1=0,C_PARITY_TYPE_MEM_2=0,C_PARITY_TYPE_MEM_3=0,C_INCLUDE_DATAWIDTH_MATCHING_0=1,C_INCLUDE_DATAWIDTH_MATCHING_1=1,C_INCLUDE_DATAWIDTH_MATCHING_2=1,C_INCLUDE_DATAWIDTH_MATCHING_3=1,C_SYNCH_PIPEDELAY_0=1,C_TCEDV_PS_MEM_0=70000,C_TAVDV_PS_MEM_0=70000,C_TPACC_PS_FLASH_0=70000,C_THZCE_PS_MEM_0=8000,C_THZOE_PS_MEM_0=8000,C_TWC_PS_MEM_0=85000,C_TWP_PS_MEM_0=55000,C_TWPH_PS_MEM_0=10000,C_TLZWE_PS_MEM_0=0,C_WR_REC_TIME_MEM_0=27000,C_SYNCH_PIPEDELAY_1=1,C_TCEDV_PS_MEM_1=15000,C_TAVDV_PS_MEM_1=15000,C_TPACC_PS_FLASH_1=25000,C_THZCE_PS_MEM_1=7000,C_THZOE_PS_MEM_1=7000,C_TWC_PS_MEM_1=15000,C_TWP_PS_MEM_1=12000,C_TWPH_PS_MEM_1=12000,C_TLZWE_PS_MEM_1=0,C_WR_REC_TIME_MEM_1=27000,C_SYNCH_PIPEDELAY_2=1,C_TCEDV_PS_MEM_2=15000,C_TAVDV_PS_MEM_2=15000,C_TPACC_PS_FLASH_2=25000,C_THZCE_PS_MEM_2=7000,C_THZOE_PS_MEM_2=7000,C_TWC_PS_MEM_2=15000,C_TWP_PS_MEM_2=12000,C_TWPH_PS_MEM_2=12000,C_TLZWE_PS_MEM_2=0,C_WR_REC_TIME_MEM_2=27000,C_SYNCH_PIPEDELAY_3=1,C_TCEDV_PS_MEM_3=15000,C_TAVDV_PS_MEM_3=15000,C_TPACC_PS_FLASH_3=25000,C_THZCE_PS_MEM_3=7000,C_THZOE_PS_MEM_3=7000,C_TWC_PS_MEM_3=15000,C_TWP_PS_MEM_3=12000,C_TWPH_PS_MEM_3=12000,C_TLZWE_PS_MEM_3=0,C_WR_REC_TIME_MEM_3=27000}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF rdclk: SIGNAL IS "xilinx.com:signal:clock:1.0 rdclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_i: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_I";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_o: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_O";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_t: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_T";
ATTRIBUTE X_INTERFACE_INFO OF mem_a: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF mem_ce: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE";
ATTRIBUTE X_INTERFACE_INFO OF mem_cen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE_N";
ATTRIBUTE X_INTERFACE_INFO OF mem_oen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF OEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_wen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_ben: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF BEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_qwen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF QWEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rpn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RPN";
ATTRIBUTE X_INTERFACE_INFO OF mem_adv_ldn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADV_LDN";
ATTRIBUTE X_INTERFACE_INFO OF mem_lbon: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF LBON";
ATTRIBUTE X_INTERFACE_INFO OF mem_cken: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CLKEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rnw: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF mem_cre: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CRE";
ATTRIBUTE X_INTERFACE_INFO OF mem_wait: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WAIT";
BEGIN
U0 : axi_emc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_emc_inst",
C_AXI_CLK_PERIOD_PS => 10000,
C_LFLASH_PERIOD_PS => 10000,
C_LINEAR_FLASH_SYNC_BURST => 0,
C_S_AXI_REG_ADDR_WIDTH => 5,
C_S_AXI_REG_DATA_WIDTH => 32,
C_S_AXI_EN_REG => 0,
C_S_AXI_MEM_ADDR_WIDTH => 32,
C_S_AXI_MEM_DATA_WIDTH => 32,
C_S_AXI_MEM_ID_WIDTH => 1,
C_S_AXI_MEM0_BASEADDR => X"60000000",
C_S_AXI_MEM0_HIGHADDR => X"60FFFFFF",
C_S_AXI_MEM1_BASEADDR => X"B0000000",
C_S_AXI_MEM1_HIGHADDR => X"BFFFFFFF",
C_S_AXI_MEM2_BASEADDR => X"C0000000",
C_S_AXI_MEM2_HIGHADDR => X"CFFFFFFF",
C_S_AXI_MEM3_BASEADDR => X"D0000000",
C_S_AXI_MEM3_HIGHADDR => X"DFFFFFFF",
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_NUM_BANKS_MEM => 1,
C_MEM0_TYPE => 1,
C_MEM1_TYPE => 0,
C_MEM2_TYPE => 0,
C_MEM3_TYPE => 0,
C_MEM0_WIDTH => 16,
C_MEM1_WIDTH => 16,
C_MEM2_WIDTH => 16,
C_MEM3_WIDTH => 16,
C_MAX_MEM_WIDTH => 16,
C_PARITY_TYPE_MEM_0 => 0,
C_PARITY_TYPE_MEM_1 => 0,
C_PARITY_TYPE_MEM_2 => 0,
C_PARITY_TYPE_MEM_3 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 1,
C_SYNCH_PIPEDELAY_0 => 1,
C_TCEDV_PS_MEM_0 => 70000,
C_TAVDV_PS_MEM_0 => 70000,
C_TPACC_PS_FLASH_0 => 70000,
C_THZCE_PS_MEM_0 => 8000,
C_THZOE_PS_MEM_0 => 8000,
C_TWC_PS_MEM_0 => 85000,
C_TWP_PS_MEM_0 => 55000,
C_TWPH_PS_MEM_0 => 10000,
C_TLZWE_PS_MEM_0 => 0,
C_WR_REC_TIME_MEM_0 => 27000,
C_SYNCH_PIPEDELAY_1 => 1,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TWPH_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_WR_REC_TIME_MEM_1 => 27000,
C_SYNCH_PIPEDELAY_2 => 1,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TWPH_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_WR_REC_TIME_MEM_2 => 27000,
C_SYNCH_PIPEDELAY_3 => 1,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TWPH_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_WR_REC_TIME_MEM_3 => 27000
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
rdclk => rdclk,
s_axi_reg_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_awvalid => '0',
s_axi_reg_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_reg_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_reg_wvalid => '0',
s_axi_reg_bready => '0',
s_axi_reg_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_arvalid => '0',
s_axi_reg_rready => '0',
s_axi_mem_awid => s_axi_mem_awid,
s_axi_mem_awaddr => s_axi_mem_awaddr,
s_axi_mem_awlen => s_axi_mem_awlen,
s_axi_mem_awsize => s_axi_mem_awsize,
s_axi_mem_awburst => s_axi_mem_awburst,
s_axi_mem_awlock => s_axi_mem_awlock,
s_axi_mem_awcache => s_axi_mem_awcache,
s_axi_mem_awprot => s_axi_mem_awprot,
s_axi_mem_awvalid => s_axi_mem_awvalid,
s_axi_mem_awready => s_axi_mem_awready,
s_axi_mem_wdata => s_axi_mem_wdata,
s_axi_mem_wstrb => s_axi_mem_wstrb,
s_axi_mem_wlast => s_axi_mem_wlast,
s_axi_mem_wvalid => s_axi_mem_wvalid,
s_axi_mem_wready => s_axi_mem_wready,
s_axi_mem_bid => s_axi_mem_bid,
s_axi_mem_bresp => s_axi_mem_bresp,
s_axi_mem_bvalid => s_axi_mem_bvalid,
s_axi_mem_bready => s_axi_mem_bready,
s_axi_mem_arid => s_axi_mem_arid,
s_axi_mem_araddr => s_axi_mem_araddr,
s_axi_mem_arlen => s_axi_mem_arlen,
s_axi_mem_arsize => s_axi_mem_arsize,
s_axi_mem_arburst => s_axi_mem_arburst,
s_axi_mem_arlock => s_axi_mem_arlock,
s_axi_mem_arcache => s_axi_mem_arcache,
s_axi_mem_arprot => s_axi_mem_arprot,
s_axi_mem_arvalid => s_axi_mem_arvalid,
s_axi_mem_arready => s_axi_mem_arready,
s_axi_mem_rid => s_axi_mem_rid,
s_axi_mem_rdata => s_axi_mem_rdata,
s_axi_mem_rresp => s_axi_mem_rresp,
s_axi_mem_rlast => s_axi_mem_rlast,
s_axi_mem_rvalid => s_axi_mem_rvalid,
s_axi_mem_rready => s_axi_mem_rready,
mem_dq_i => mem_dq_i,
mem_dq_o => mem_dq_o,
mem_dq_t => mem_dq_t,
mem_dq_parity_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
mem_a => mem_a,
mem_ce => mem_ce,
mem_cen => mem_cen,
mem_oen => mem_oen,
mem_wen => mem_wen,
mem_ben => mem_ben,
mem_qwen => mem_qwen,
mem_rpn => mem_rpn,
mem_adv_ldn => mem_adv_ldn,
mem_lbon => mem_lbon,
mem_cken => mem_cken,
mem_rnw => mem_rnw,
mem_cre => mem_cre,
mem_wait => mem_wait
);
END design_1_axi_emc_0_0_arch;
| gpl-3.0 | 86c306d8c82573192536d10e3f69b90b | 0.658369 | 2.816138 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.vhd | 2 | 4,910 | -- file: design_1_clk_wiz_1_0.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2____50.000______0.000______50.0______151.636_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity design_1_clk_wiz_1_0 is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end design_1_clk_wiz_1_0;
architecture xilinx of design_1_clk_wiz_1_0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "design_1_clk_wiz_1_0,clk_wiz_v5_1,{component_name=design_1_clk_wiz_1_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component design_1_clk_wiz_1_0_clk_wiz
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
begin
U0: design_1_clk_wiz_1_0_clk_wiz
port map (
-- Clock in ports
clk_in1 => clk_in1,
-- Clock out ports
clk_out1 => clk_out1,
clk_out2 => clk_out2,
-- Status and control signals
resetn => resetn,
locked => locked
);
end xilinx;
| gpl-3.0 | 98e4ebcba0b30d7b9b48fdc4cb210e37 | 0.621792 | 3.97893 | false | false | false | false |
h397wang/Lab2 | Fanzhe/Lab2.vhd | 1 | 5,337 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- 7-segment display driver. It displays a 4-bit number on 7-segments
-- This is created as an entity so that it can be reused many times easily
--
entity SevenSegment is port (
dataIn : in std_logic_vector(3 downto 0); -- The 4 bit data to be displayed
blanking : in std_logic; -- This bit turns off all segments
segmentsOut : out std_logic_vector(6 downto 0) -- 7-bit outputs to a 7-segment
);
end SevenSegment;
architecture Behavioral of SevenSegment is
--
-- The following statements convert a 4-bit input, called dataIn to a pattern of 7 bits
-- The segment turns on when it is '0' otherwise '1'
-- The blanking input is added to turns off the all segments
--
begin
with blanking & dataIn select -- gfedcba b3210 -- D7S
segmentsOut(6 downto 0) <= "1000000" when "00000", -- [0]
"1111001" when "00001", -- [1]
"0100100" when "00010", -- [2] +---- a ----+
"0110000" when "00011", -- [3] | |
"0011001" when "00100", -- [4] | |
"0010010" when "00101", -- [5] f b
"0000010" when "00110", -- [6] | |
"1111000" when "00111", -- [7] | |
"0000000" when "01000", -- [8] +---- g ----+
"0010000" when "01001", -- [9] | |
"0001000" when "01010", -- [A] | |
"0000011" when "01011", -- [b] e c
"1000110" when "01100", -- [c] | |
"0100001" when "01101", -- [d] | |
"0000110" when "01110", -- [E] +---- d ----+
"0001110" when "01111", -- [F]
"1111111" when others; -- [ ]
end Behavioral;
--------------------------------------------------------------------------------
-- Main entity
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Lab2 is port (
sw : in std_logic_vector(17 downto 0); -- 18 dip switches
ledr : out std_logic_vector(17 downto 0); -- 18 red LEDs
hex0, hex1, hex2, hex4, hex5, hex6, hex7 : out std_logic_vector( 6 downto 0) -- 7-segment displays
);
end Lab2;
architecture SimpleCircuit of Lab2 is
--
-- In order to use the "SevenSegment" entity, we should declare it first
--
component SevenSegment port (
dataIn : in std_logic_vector(3 downto 0);
blanking : in std_logic;
segmentsOut : out std_logic_vector(6 downto 0)
);
end component;
-- Create any signals, or temporary variables to be used
--
-- Note that there are two basic types and mixing them is difficult
-- unsigned is a signal which can be used to perform math operations such as +, -, *
-- std_logic_vector is a signal which can be used for logic operations such as OR, AND, NOT, XOR
--
signal A, B: std_logic_vector(7 downto 0);
signal R: std_logic_vector(11 downto 0);
signal S: std_logic_vector(1 downto 0);
-- Here the circuit begins
begin
-- intermediate signal assignments
A <= sw(7 downto 0); -- connect the lowest 8 switches to A
B <= sw(15 downto 8); -- connect the next 8 switches to B
S <= sw(17 downto 16); -- connect the highest 2 switches to S
-- multiplexer
with S select
R <= "0000"&A and "0000"&B when "00",
"0000"&A or "0000"&B when "01",
"0000"&A xor "0000"&B when "10",
std_logic_vector(unsigned("0000"&A)+unsigned("0000"&B)) when others;
-- signal is assigned to LED
ledr(8 downto 0) <= R(8 downto 0);
ledr(17 downto 16) <= S;
-- signal is sidplayed on seven-segment. '0' is concatenated with signal to make a 4-bit input
D7SH0: SevenSegment port map(R(3 downto 0), '0', hex0 ); -- R(3 downto 0) is diplayed on HEX0, blanking is disabled
D7SH1: SevenSegment port map(R(7 downto 4), '0', hex1 ); -- R(7 downto 4) is diplayed on HEX1, blanking is disabled
D7SH2: SevenSegment port map(R(11 downto 8), not R(8), hex2); -- R(11 downto 8) is displayed on HEX2, blanking is disabled when no carry
D7SH4: SevenSegment port map(A(3 downto 0), '0', hex4 ); -- A(3 downto 0) is diplayed on HEX4, blanking is disabled
D7SH5: SevenSegment port map(A(7 downto 4), '0', hex5 ); -- A(7 downto 4) is diplayed on HEX5, blanking is disabled
D7SH6: SevenSegment port map(B(3 downto 0), '0', hex6 ); -- B(3 downto 0) is diplayed on HEX6, blanking is disabled
D7SH7: SevenSegment port map(B(7 downto 4), '0', hex7 ); -- B(7 downto 4) is diplayed on HEX7, blanking is disabled
end SimpleCircuit;
| apache-2.0 | 991f7eea020b0cb3112cdf0913a7317d | 0.508151 | 3.881455 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/pselect.vhd | 4 | 9,592 | -------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MB_MUXCY
generic map (
C_TARGET => C_TARGET)
port map (
LO => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
| gpl-3.0 | 6016e6acb7d02df2e5065a6533c44b7f | 0.464137 | 4.878942 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/mii_to_rmii.vhd | 4 | 19,556 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Im_SP1
-- Updated Release For V5 Porting
-- @END_CHANGELOG
------------------------------------------------------------------------------
-- Filename: mii_to_rmii.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
use mii_to_rmii_v2_0.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INSTANCE -- Instance name in the system.
-- C_FIXED_SPEED -- selects a fixed data throughput or agile RX
-- -- side, TX side is will be fixed either way
-- C_SPEED_100 -- selects speed for TX, RX if C_FIXED_SPEED is
-- -- selected
--
-- Definition of Ports:
-- rst_n -- active low reset
-- ref_clk -- clk, must be 50 MHz
-- mac2rmii_tx_en -- active high transmit enable, valid txd
-- mac2rmii_txd -- 4 bits of tx data from MAC
-- mac2rmii_tx_er -- active high tx error indicator
-- rmii2mac_tx_clk -- 25 or 2.5 MHz clock to MAC
-- rmii2mac_rx_clk -- 25 or 2.5 MHz clock to MAC
-- rmii2mac_col -- active high colision indicator
-- rmii2mac_crs -- active high carrier sense
-- rmii2mac_rx_dv -- active high rx data valid
-- rmii2mac_rx_er -- acitve high rx error indicator
-- rmii2mac_rxd -- 4 bits of rx data to MAC
-- phy2rmii_crs_dv -- active high carrier sense / data valid to rmii
-- phy2rmii_rx_er -- active high rx error indicator
-- phy2rmii_rxd -- 2 bits of rx data to rmii
-- rmii2phy_txd -- 2 bits of tx data to phy
-- rmii2phy_tx_en -- active high tx enable, valid tx to phy
--
------------------------------------------------------------------------------
entity mii_to_rmii is
generic (
C_INSTANCE : string := "mii_to_rmii_inst";
C_FIXED_SPEED : std_logic := '1';
C_SPEED_100 : std_logic := '1'
);
port (
------------------ System Signals ----------------------
rst_n : in std_logic;
ref_clk : in std_logic;
------------------ Speed Setting -----------------------
--Tx_speed_100 : in std_logic; -- add if ever
--Rx_speed_100 : in std_logic; -- auto speed
------------------ MAC <--> RMII -----------------------
mac2rmii_tx_en : in std_logic;
mac2rmii_txd : in std_logic_vector(3 downto 0);
mac2rmii_tx_er : in std_logic;
rmii2mac_tx_clk : out std_logic;
rmii2mac_rx_clk : out std_logic;
rmii2mac_col : out std_logic;
rmii2mac_crs : out std_logic;
rmii2mac_rx_dv : out std_logic;
rmii2mac_rx_er : out std_logic;
rmii2mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY -----------------------
phy2rmii_crs_dv : in std_logic;
phy2rmii_rx_er : in std_logic;
phy2rmii_rxd : in std_logic_vector(1 downto 0);
rmii2phy_txd : out std_logic_vector(1 downto 0);
rmii2phy_tx_en : out std_logic
);
attribute HDL : string;
attribute IMP_NETLIST : string;
attribute IPTYPE : string;
attribute IP_GROUP : string;
attribute SIGIS : string;
attribute STYLE : string;
attribute XRANGE : string;
attribute HDL of mii_to_rmii:entity is "VHDL";
attribute IMP_NETLIST of mii_to_rmii:entity is "TRUE";
attribute IPTYPE of mii_to_rmii:entity is "IP";
attribute IP_GROUP of mii_to_rmii:entity is "LOGICORE";
attribute SIGIS of ref_clk:signal is "CLK";
-- attribute SIGIS of rmii2mac_tx_clk:signal is "CLK";
-- attribute SIGIS of rmii2mac_rx_clk:signal is "CLK";
attribute SIGIS of rst_n:signal is "RST";
attribute STYLE of mii_to_rmii:entity is "HDL";
attribute XRANGE of C_FIXED_SPEED:constant is "('0':'1')";
attribute XRANGE of C_SPEED_100:constant is "('0':'1')";
end mii_to_rmii;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of mii_to_rmii is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",mii_to_rmii,{"
& "c_instance = " & C_INSTANCE
& ",c_fixed_speed = " & str(C_FIXED_SPEED)
& ",c_speed_100 = " & str(C_SPEED_100)
& "}";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of simulation : architecture is C_CORE_GENERATION_INFO;
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '0';
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
signal tx_speed_100_i : std_logic;
signal rx_speed_100_i : std_logic;
signal sync_rst_n : std_logic;
signal rst_n_d : std_logic_vector(1 downto 0);
signal mac2Rmii_tx_en_d2 : std_logic;
signal mac2Rmii_tx_en_d1 : std_logic;
signal mac2Rmii_txd_d2 : std_logic_vector(3 downto 0);
signal mac2Rmii_txd_d1 : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d2 : std_logic;
signal mac2Rmii_tx_er_d1 : std_logic;
signal rmii2Mac_tx_clk_i : std_logic;
signal rmii2Mac_rx_clk_i : std_logic;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_dv_i : std_logic;
signal rmii2Mac_rx_er_i : std_logic;
signal rmii2Mac_rxd_i : std_logic_vector(3 downto 0);
signal phy2Rmii_crs_dv_d2 : std_logic;
signal phy2Rmii_crs_dv_d1 : std_logic;
signal phy2Rmii_rx_er_d2 : std_logic;
signal phy2Rmii_rx_er_d1 : std_logic;
signal phy2Rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal rmii2Phy_txd_i : std_logic_vector(1 downto 0);
signal rmii2Phy_tx_en_i : std_logic;
begin
------------------------------------------------------------------------------
-- SYNC_RST_N_PROCESS
------------------------------------------------------------------------------
SYNC_RST_N_PROCESS : process (
ref_clk,
rst_n,
rst_n_d
)
begin
sync_rst_n <= rst_n_d(1);
if (ref_clk'event and ref_clk = '1') then
rst_n_d <= rst_n_d(0) & rst_n;
end if;
end process;
------------------------------------------------------------------------------
-- INPUT_PIPELINE_PROCESS
------------------------------------------------------------------------------
INPUT_PIPELINE_PROCESS : process ( ref_clk )
begin
if (ref_clk'event and ref_clk = '1') then
if ( sync_rst_n = '0' ) then
mac2Rmii_tx_en_d2 <= '0';
mac2Rmii_tx_en_d1 <= '0';
mac2Rmii_txd_d2 <= "0000";
mac2Rmii_txd_d1 <= "0000";
mac2Rmii_tx_er_d2 <= '0';
mac2Rmii_tx_er_d1 <= '0';
phy2Rmii_crs_dv_d2 <= '0';
phy2Rmii_crs_dv_d1 <= '0';
phy2Rmii_rx_er_d2 <= '0';
phy2Rmii_rx_er_d1 <= '0';
phy2Rmii_rxd_d2 <= "00";
phy2Rmii_rxd_d1 <= "00";
else
mac2Rmii_tx_en_d2 <= mac2Rmii_tx_en_d1;
mac2Rmii_tx_en_d1 <= mac2rmii_tx_en;
mac2Rmii_txd_d2 <= mac2Rmii_txd_d1;
mac2Rmii_txd_d1 <= mac2rmii_txd;
mac2Rmii_tx_er_d2 <= mac2Rmii_tx_er_d1;
mac2Rmii_tx_er_d1 <= mac2rmii_tx_er;
phy2Rmii_crs_dv_d2 <= phy2Rmii_crs_dv_d1;
phy2Rmii_crs_dv_d1 <= phy2rmii_crs_dv;
phy2Rmii_rx_er_d2 <= phy2Rmii_rx_er_d1;
phy2Rmii_rx_er_d1 <= phy2rmii_rx_er;
phy2Rmii_rxd_d2 <= phy2Rmii_rxd_d1;
phy2Rmii_rxd_d1 <= phy2rmii_rxd;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- OUTPUT_PIPELINE_PROCESS
------------------------------------------------------------------------------
OUTPUT_PIPELINE_PROCESS : process ( ref_clk )
begin
if (ref_clk'event and ref_clk = '1') then
if ( sync_rst_n = '0' ) then
rmii2mac_tx_clk <= '0';
rmii2mac_rx_clk <= '0';
rmii2mac_col <= '0';
rmii2mac_crs <= '0';
rmii2mac_rx_dv <= '0';
rmii2mac_rx_er <= '0';
rmii2mac_rxd <= "0000";
rmii2phy_txd <= "00";
rmii2phy_tx_en <= '0';
else
rmii2mac_tx_clk <= rmii2Mac_tx_clk_i;
rmii2mac_rx_clk <= rmii2Mac_rx_clk_i;
rmii2mac_col <= rmii2Mac_crs_i and mac2Rmii_tx_en_d2;
rmii2mac_crs <= rmii2Mac_crs_i;
rmii2mac_rx_dv <= rmii2Mac_rx_dv_i;
rmii2mac_rx_er <= rmii2Mac_rx_er_i;
rmii2mac_rxd <= rmii2Mac_rxd_i;
rmii2phy_txd <= rmii2Phy_txd_i;
rmii2phy_tx_en <= rmii2Phy_tx_en_i;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Concurrent signal assignments
------------------------------------------------------------------------------
tx_speed_100_i <= C_SPEED_100;
rx_speed_100_i <= C_SPEED_100;
------------------------------------------------------------------------------
--
-- Conditional Generate for AGILE speed throughput
--
------------------------------------------------------------------------------
RMII_AGILE : if (C_FIXED_SPEED = '0') generate
begin
--------------------------------------------------------------------------
-- Component Instatiations
--------------------------------------------------------------------------
I_TX : entity mii_to_rmii_v2_0.rmii_tx_agile(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Tx_speed_100 => tx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
mac2rmii_tx_en => mac2Rmii_tx_en_d2, -- in
mac2rmii_txd => mac2Rmii_txd_d2, -- in
mac2rmii_tx_er => mac2Rmii_tx_er_d2, -- in
rmii2mac_tx_clk => rmii2Mac_tx_clk_i, -- out
------------------ RMII <--> PHY ------------
rmii2phy_txd => rmii2Phy_txd_i, -- out
rmii2phy_tx_en => rmii2Phy_tx_en_i -- out
);
I_RX : entity mii_to_rmii_v2_0.rmii_rx_agile(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Rx_speed_100 => rx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
rmii2mac_rx_clk => rmii2Mac_rx_clk_i, -- out
rmii2mac_crs => rmii2Mac_crs_i, -- out
rmii2mac_rx_dv => rmii2Mac_rx_dv_i, -- out
rmii2mac_rx_er => rmii2Mac_rx_er_i, -- out
rmii2mac_rxd => rmii2Mac_rxd_i, -- out
------------------ RMII <--> PHY ------------
phy2rmii_crs_dv => phy2Rmii_crs_dv_d2, -- in
phy2rmii_rx_er => phy2Rmii_rx_er_d2, -- in
phy2rmii_rxd => phy2Rmii_rxd_d2 -- in
);
end generate RMII_AGILE;
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput
--
------------------------------------------------------------------------------
RMII_FIXED : if (C_FIXED_SPEED = '1') generate
begin
--------------------------------------------------------------------------
-- Component Instatiations
--------------------------------------------------------------------------
I_TX : entity mii_to_rmii_v2_0.rmii_tx_fixed(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Tx_speed_100 => tx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
mac2rmii_tx_en => mac2Rmii_tx_en_d2, -- in
mac2rmii_txd => mac2Rmii_txd_d2, -- in
mac2rmii_tx_er => mac2Rmii_tx_er_d2, -- in
rmii2mac_tx_clk => rmii2Mac_tx_clk_i, -- out
------------------ RMII <--> PHY ------------
rmii2phy_txd => rmii2Phy_txd_i, -- out
rmii2phy_tx_en => rmii2Phy_tx_en_i -- out
);
I_RX : entity mii_to_rmii_v2_0.rmii_rx_fixed(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE,
C_SPEED_100 => C_SPEED_100
)
port map (
Rx_speed_100 => rx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
rmii2mac_rx_clk => rmii2Mac_rx_clk_i, -- out
rmii2mac_crs => rmii2Mac_crs_i, -- out
rmii2mac_rx_dv => rmii2Mac_rx_dv_i, -- out
rmii2mac_rx_er => rmii2Mac_rx_er_i, -- out
rmii2mac_rxd => rmii2Mac_rxd_i, -- out
------------------ RMII <--> PHY ------------
phy2rmii_crs_dv => phy2Rmii_crs_dv_d2, -- in
phy2rmii_rx_er => phy2Rmii_rx_er_d2, -- in
phy2rmii_rxd => phy2Rmii_rxd_d2 -- in
);
end generate RMII_FIXED;
end simulation;
| gpl-3.0 | 5cfb026ee12d553a7a598f09191928a4 | 0.429178 | 3.969955 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sources_1/new/DataSequencer.vhd | 1 | 18,482 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.02.2016 21:28:53
-- Design Name:
-- Module Name: DataSequencer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataSequencer is
Port (
clk :in STD_LOGIC;
reset : in STD_LOGIC;
S_FIFO_WriteEn : out STD_LOGIC;
S_FIFO_DataIn : out STD_LOGIC_VECTOR ( 7 downto 0);
S_FIFO_Full : in STD_LOGIC;
--sensor 1
I2C1_FIFO_ReadEn : out STD_LOGIC;
I2C1_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C1_FIFO_Empty : in STD_LOGIC;
--sensor 2
I2C2_FIFO_ReadEn : out STD_LOGIC;
I2C2_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C2_FIFO_Empty : in STD_LOGIC;
--sensor 3
I2C3_FIFO_ReadEn : out STD_LOGIC;
I2C3_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C3_FIFO_Empty : in STD_LOGIC;
--sensor 4
I2C4_FIFO_ReadEn : out STD_LOGIC;
I2C4_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C4_FIFO_Empty : in STD_LOGIC;
--sensor 5
I2C5_FIFO_ReadEn : out STD_LOGIC;
I2C5_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C5_FIFO_Empty : in STD_LOGIC;
--sensor 6
I2C6_FIFO_ReadEn : out STD_LOGIC;
I2C6_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C6_FIFO_Empty : in STD_LOGIC;
--sensor 7
I2C7_FIFO_ReadEn : out STD_LOGIC;
I2C7_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C7_FIFO_Empty : in STD_LOGIC;
--sensor 8
I2C8_FIFO_ReadEn : out STD_LOGIC;
I2C8_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C8_FIFO_Empty : in STD_LOGIC;
--sensor 9
I2C9_FIFO_ReadEn : out STD_LOGIC;
I2C9_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C9_FIFO_Empty : in STD_LOGIC;
--sensor 10
I2C10_FIFO_ReadEn : out STD_LOGIC;
I2C10_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C10_FIFO_Empty : in STD_LOGIC
);
end DataSequencer;
architecture Behavioral of DataSequencer is
type state_type is ( STATE_WAIT, STATE_STARTREAD, STATE_ENDREAD, STATE_WAITFULL, STATE_STARTWRITE, STATE_FINISHWRITE,STATE_CLOCKIN, STATE_UPDATEMUX, STATE_EOL);
signal state_reg: state_type := STATE_WAIT;
constant Maxtimeout : positive := 4000;
signal multiplexerState : INTEGER RANGE 0 to 9 := 0;
signal timeoutCount : INTEGER RANGE 0 to Maxtimeout +5:= 0; -- wait 1ms before a timeout.
signal currentByteCount : INTEGER RANGE 0 to 8:= 0; --6 bytes of data per sensor.
begin
process (clk, S_FIFO_Full, reset) -- process to handle the next state
begin
if (reset = '1') then
--reset state:
S_FIFO_WriteEn <= '0';
state_reg <= STATE_WAIT;
multiplexerState <= 0;
timeoutCount <= 0;
I2C1_FIFO_ReadEn <= '0';
I2C2_FIFO_ReadEn <= '0';
I2C3_FIFO_ReadEn <= '0';
I2C4_FIFO_ReadEn <= '0';
I2C5_FIFO_ReadEn <= '0';
I2C6_FIFO_ReadEn <= '0';
I2C7_FIFO_ReadEn <= '0';
I2C8_FIFO_ReadEn <= '0';
I2C9_FIFO_ReadEn <= '0';
I2C10_FIFO_ReadEn <= '0';
else
if rising_edge (clk) then
case state_reg is
when STATE_WAIT =>
case multiplexerState is
when 0 =>
if (I2C1_FIFO_Empty = '1') then
if (currentByteCount = 0) then
-- timeoutCount <= timeoutCount + 1; -- increase the timeout count.
-- if (timeoutCount = Maxtimeout) then
-- state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
-- else
state_reg <= STATE_WAIT; -- else carry on waiting.
-- end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 1 =>
if (I2C2_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 2 =>
if (I2C3_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 3 =>
if (I2C4_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 4 =>
if (I2C5_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 5 =>
if (I2C6_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 6 =>
if (I2C7_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 7 =>
if (I2C8_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 8 =>
if (I2C9_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 9 =>
if (I2C10_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when others =>
end case;
when STATE_STARTREAD =>
-- request the data
case (multiplexerState) is
when 0 =>
I2C1_FIFO_ReadEn <= '1';
when 1 =>
I2C2_FIFO_ReadEn <= '1';
when 2 =>
I2C3_FIFO_ReadEn <= '1';
when 3 =>
I2C4_FIFO_ReadEn <= '1';
when 4 =>
I2C5_FIFO_ReadEn <= '1';
when 5 =>
I2C6_FIFO_ReadEn <= '1';
when 6 =>
I2C7_FIFO_ReadEn <= '1';
when 7 =>
I2C8_FIFO_ReadEn <= '1';
when 8 =>
I2C9_FIFO_ReadEn <= '1';
when 9 =>
I2C10_FIFO_ReadEn <= '1';
when others =>
end case;
state_reg <= STATE_ENDREAD;
when STATE_ENDREAD =>
--finish the request
case (multiplexerState) is
when 0 =>
I2C1_FIFO_ReadEn <= '0';
when 1 =>
I2C2_FIFO_ReadEn <= '0';
when 2 =>
I2C3_FIFO_ReadEn <= '0';
when 3 =>
I2C4_FIFO_ReadEn <= '0';
when 4 =>
I2C5_FIFO_ReadEn <= '0';
when 5 =>
I2C6_FIFO_ReadEn <= '0';
when 6 =>
I2C7_FIFO_ReadEn <= '0';
when 7 =>
I2C8_FIFO_ReadEn <= '0';
when 8 =>
I2C9_FIFO_ReadEn <= '0';
when 9 =>
I2C10_FIFO_ReadEn <= '0';
when others =>
end case;
state_reg <= STATE_CLOCKIN;
when STATE_CLOCKIN =>
--clock the data out
case (multiplexerState) is
when 0 =>
S_FIFO_DataIn <= I2C1_FIFO_DataOut;
when 1 =>
S_FIFO_DataIn <= I2C2_FIFO_DataOut;
when 2 =>
S_FIFO_DataIn <= I2C3_FIFO_DataOut;
when 3 =>
S_FIFO_DataIn <= I2C4_FIFO_DataOut;
when 4 =>
S_FIFO_DataIn <= I2C5_FIFO_DataOut;
when 5 =>
S_FIFO_DataIn <= I2C6_FIFO_DataOut;
when 6 =>
S_FIFO_DataIn <= I2C7_FIFO_DataOut;
when 7 =>
S_FIFO_DataIn <= I2C8_FIFO_DataOut;
when 8 =>
S_FIFO_DataIn <= I2C9_FIFO_DataOut;
when 9 =>
S_FIFO_DataIn <= I2C10_FIFO_DataOut;
when others =>
end case;
if ('0' = S_FIFO_Full) then
state_reg <= STATE_STARTWRITE;
else
state_reg <= STATE_WAITFULL;
end if;
when STATE_WAITFULL =>
if (S_FIFO_Full = '0') then
state_reg <= STATE_STARTWRITE;
else
state_reg <= STATE_WAITFULL;
end if;
when STATE_STARTWRITE =>
S_FIFO_WriteEn <= '1';
state_reg <= STATE_FINISHWRITE;
currentByteCount <= currentByteCount +1; --- update the byte count.
when STATE_FINISHWRITE =>
S_FIFO_WriteEn <= '0';
state_reg <= STATE_UPDATEMUX;
when STATE_UPDATEMUX => -- when a read has just completed or a timeout has occured.
-- this is called when one of these things have happened:
--> TIMEOUT - reading a sensor has timed out -->
--> IF A TIMEOUT HAS HAPPENED ON SENSOR 10 --> WRITE EOL
--> ELSE just move onto next sensor
--> FINISH BYTE WRITE --> A byte has just finished writing
--> FINISH EOL - an EOL has just been written --> an EOL has just been written
--> FINISH SENSOR READ - 6 bytes have been read --> move onto the next sensor
--> FINISH BYTE READ - a byte has just been read --> read the next one
if (timeoutCount >= (MaxTimeout) AND CurrentByteCount = 0) then -- this has been called by a timeout.
if (multiplexerState = 9) then -- sensor 10 timeout, write the EOL.
state_reg <= STATE_EOL; -- write the EOL.
else
timeoutCount <= 0; -- reset the timeout counter
multiplexerState <= multiplexerState +1; -- move onto the next sensor.
state_reg <= STATE_WAIT;
end if;
else
-- a byte was just written.
if ((multiplexerState = 9 AND timeoutCount >= (MaxTimeout)) OR (currentByteCount = 7)) then -- the EOL was just written, start the read all over again.
timeoutCount<=0;
multiplexerState <= 0;
currentByteCount <=0;
state_reg <= STATE_WAIT;
elsif (currentByteCount = 6) then -- the final byte of a sensor read was written
if (multiplexerState = 9) then
timeoutCount <=0;
state_reg <= STATE_EOL;
else
timeoutCount<=0;
multiplexerState <= multiplexerState +1;
currentByteCount<=0;
end if;
else -- a byte has been read
state_reg <= STATE_WAIT;--don't need to do anything, just continue.
end if;
end if;
when STATE_EOL =>
S_FIFO_DataIn <= "11111111";
state_reg <= STATE_STARTWRITE;
when others =>
state_reg <= STATE_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 0527e66108f5950d893a7bfd3c2a5508 | 0.41581 | 5.087256 | false | false | false | false |
h397wang/Lab2 | Lab2.vhd | 1 | 6,117 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- 7-segment display driver. It displays a 4-bit number on 7-segments
-- This is created as an entity so that it can be reused many times easily
--
entity SevenSegment is port (
dataIn : in std_logic_vector(3 downto 0); -- The 4 bit data to be displayed
blanking : in std_logic; -- This bit turns off all segments
segmentsOut : out std_logic_vector(6 downto 0) -- 7-bit outputs to a 7-segment
);
end SevenSegment;
architecture Behavioral of SevenSegment is
--
-- The following statements convert a 4-bit input, called dataIn to a pattern of 7 bits
-- The segment turns on when it is '0' otherwise '1'
-- The blanking input is added to turns off the all segments
--
begin
with blanking & dataIn select -- gfedcba b3210 -- D7S
segmentsOut(6 downto 0) <= "1000000" when "00000", -- [0]
"1111001" when "00001", -- [1]
"0100100" when "00010", -- [2] +---- a ----+
"0110000" when "00011", -- [3] | |
"0011001" when "00100", -- [4] | |
"0010010" when "00101", -- [5] f b
"0000010" when "00110", -- [6] | |
"1111000" when "00111", -- [7] | |
"0000000" when "01000", -- [8] +---- g ----+
"0010000" when "01001", -- [9] | |
"0001000" when "01010", -- [A] | |
"0000011" when "01011", -- [b] e c
"1000110" when "01100", -- [c] | |
"0100001" when "01101", -- [d] | |
"0000110" when "01110", -- [E] +---- d ----+
"0001110" when "01111", -- [F]
"1111111" when others; -- [ ]
end Behavioral;
--------------------------------------------------------------------------------
-- Main entity
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Lab2 is port (
ledr : out std_logic_vector(17 downto 0); -- displays the operator and result on the other end
sw : in std_logic_vector(17 downto 0); -- 18 dip switches
hex6,hex7 : out std_logic_vector(6 downto 0); -- display for operand 2
hex4,hex5 : out std_logic_vector(6 downto 0); -- display for operand 1
hex0, hex1, hex2 : out std_logic_vector(6 downto 0) -- display for the result
);
end Lab2;
architecture SimpleCircuit of Lab2 is
--
-- In order to use the "SevenSegment" entity, we have to use this declaration
-- It's signals have to correspond to the entity declared above
--
component SevenSegment port (
dataIn : in std_logic_vector(3 downto 0);
blanking : in std_logic;
segmentsOut : out std_logic_vector(6 downto 0)
);
end component;
-- Create any signals, or temporary variables to be used
-- Unsigned is a signal which can be used to perform math operations such as +, -, *
-- std_logic_vector is a signal which can be used for logic operations such as OR, AND, NOT, XOR
--
signal operand1, operand2: std_logic_vector(7 downto 0); -- 8-bit intermediate signals (wires)
signal operand1_mod, operand2_mod: std_logic_vector(11 downto 0);
signal result: std_logic_vector(11 downto 0); -- output signal for the three 7segment displays
signal operator: std_logic_vector(1 downto 0); -- input signal represents operator
begin
-- Intermediate signal assignments
operand1 <= sw(7 downto 0); -- connect the lowest 8 switches to operand1
operand2 <= sw(15 downto 8); -- connect the highest 8 switches to operand2
operator <= sw(17 downto 16); -- connect 2 switches to input operator signal
-- concatenate for 12 bits
-- apparently you can't just re-assign the signal variable in this case because the signal vector
-- is declared to be a fixed length
operand1_mod <= "0000"&operand1;
operand2_mod <= "0000"&operand2;
-- implementing a multiplexer, dependent on the operator input signal
with operator select
result <= operand1_mod and operand2_mod when "00",
operand1_mod or operand2_mod when "01",
operand1_mod xor operand2_mod when "10",
std_logic_vector(unsigned(operand1_mod) + unsigned(operand2_mod)) when "11";
-- note that the + operator only supports unsigned vector types
-- the input signals are cast to type, then cast back to std_logic_vector
-- light up LED to display operator
ledr(17 downto 16) <= operator;
-- light up the 9 red LEDs to display the result
ledr(11 downto 0) <= result(11 downto 0); -- s was the source of error
-- Instantiate instants of each SevenSegment components
-- Think of the instantiation as a constructor that takes in signal inputs and maps it to the corresponding
-- "member" signals within that component
Operand1_MSD_display: SevenSegment port map(operand1(7 downto 4), '0', hex5);
Operand1_LSD_display: SevenSegment port map(operand1(3 downto 0), '0', hex4);
Operand2_MSD_display: SevenSegment port map(operand2(7 downto 4), '0', hex7);
Operand2_LSD_display: SevenSegment port map(operand2(3 downto 0), '0', hex6);
result_MSD: SevenSegment port map(result(11 downto 8), not result(8), hex2 ); --
result_2ndD: SevenSegment port map(result(7 downto 4), '0', hex1 ); -- display the second digit
result_LSD: SevenSegment port map(result(3 downto 0), '0', hex0 ); -- dispaly the least significant digit
end SimpleCircuit;
| apache-2.0 | ab8445391247197696b05b79e13cc770 | 0.561059 | 4.11642 | false | false | false | false |
MikhailKoslowski/Variax | Quartus/FlashController.vhd | 1 | 1,112 | -----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY FlashController IS
GENERIC( freq : NATURAL := 50_000_000 );
PORT ( clk : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END FlashController;
--------------------------------------------------------
ARCHITECTURE structure OF FlashController IS
SIGNAL s_addr : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL s_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(clk)
VARIABLE count: NATURAL RANGE 0 TO freq := 0;
BEGIN
-- clk rising edge.
IF clk'EVENT AND clk='1' THEN
IF count = 0 THEN
s_addr <= addr;
ELSIF count = freq THEN
data <= s_data;
rdy <= '1';
ELSE
s_data <= s_addr(7 DOWNTO 0);
rdy <= '0';
END IF;
count := count + 1;
END IF;
END PROCESS;
END structure;
-------------------------------------------------------- | mit | bca3376a44f0da022da08b20206cd1b9 | 0.505396 | 3.694352 | false | false | false | false |
hoangt/PoC | src/arith/arith_scaler.vhdl | 2 | 8,554 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Description: A flexible scaler for fixed-point values.
-- The scaler is implemented for a set of multiplier and
-- divider values. Each individual scaling operation can
-- arbitrarily select one value from each these sets.
--
-- Authors: Thomas B. Preusser
-- ===========================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library poc;
use poc.utils.all;
entity arith_scaler is
generic (
-- The set of multipliers to choose from in scaling operations.
MULS : T_POSVEC := (0 => 1);
-- The set of divisors to choose from in scaling operations.
DIVS : T_POSVEC := (0 => 1)
);
port (
---------------------------------------------------------------------------
-- System Control
clk : in std_logic;
rst : in std_logic;
---------------------------------------------------------------------------
-- Start of Computation
-- Strobe 'start'. If a computation is running, it will be canceled.
-- The initiated computation calculates:
--
-- unsigned(arg)*MULS(msel)/DIVS(dsel)
--
-- rounded to the nearest (tie upwards) fixed-point result of the same
-- precision as 'arg'.
start : in std_logic;
arg : in std_logic_vector;
msel : in std_logic_vector(log2ceil(MULS'length)-1 downto 0) := (others => '0');
dsel : in std_logic_vector(log2ceil(DIVS'length)-1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- Completion
-- 'done' is '1' when no computation is in progress. The result of the
-- last scaling operation is stable and can be read from 'res'. The weight
-- of the LSB of 'res' is the same as the LSB of 'arg'. Make sure to tap
-- a sufficient number of result bits in accordance to the highest scaling
-- ratio to be used in order to avoid a truncation overflow.
done : out std_logic;
res : out std_logic_vector
);
end arith_scaler;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of arith_scaler is
-- Derived Constants
constant N : positive := arg'length;
constant X : positive := log2ceil(imax(imax(MULS), imax(DIVS)/2+1));
constant R : positive := log2ceil(imax(DIVS)+1);
-- Division Properties
type tDivProps is
record -- Properties of the operation for a divisor
steps : T_POSVEC(DIVS'range); -- Steps to perform
align : T_POSVEC(DIVS'range); -- Left-aligned divisor
end record;
function computeProps return tDivProps is
variable res : tDivProps;
variable min_steps : positive;
begin
for i in DIVS'range loop
res.steps(i) := N+X - log2ceil(DIVS(i)+1) + 1;
end loop;
min_steps := imin(res.steps);
for i in DIVS'range loop
res.align(i) := DIVS(i) * 2**(res.steps(i) - min_steps);
end loop;
return res;
end computeProps;
constant DIV_PROPS : tDivProps := computeProps;
constant MAX_MUL_STEPS : positive := N;
constant MAX_DIV_STEPS : positive := imax(DIV_PROPS.steps);
constant MAX_ANY_STEPS : positive := imax(MAX_MUL_STEPS, MAX_DIV_STEPS);
subtype tResMask is std_logic_vector(MAX_DIV_STEPS-1 downto 0);
type tResMasks is array(natural range<>) of tResMask;
function computeMasks return tResMasks is
variable res : tResMasks(DIVS'range);
begin
for i in DIVS'range loop
res(i) := (others => '0');
res(i)(DIV_PROPS.steps(i)-1 downto 0) := (others => '1');
end loop;
return res;
end computeMasks;
constant RES_MASKS : tResMasks(DIVS'range) := computeMasks;
-- Values computed for the selected multiplier/divisor pair.
signal muloffset : unsigned(X-1 downto 0); -- Offset for correct rounding.
signal multiplier : unsigned(X downto 0); -- The actual multiplier value.
signal divisor : unsigned(R-1 downto 0); -- The actual divisor value.
signal divcini : unsigned(log2ceil(MAX_ANY_STEPS)-1 downto 0); -- Count for division steps.
signal divmask : tResMask; -- Result Mask
begin
-----------------------------------------------------------------------------
-- Compute Parameters according to selected Multiplier/Divisor Pair.
-- Selection of Multiplier
genMultiMul: if MULS'length > 1 generate
signal MS : unsigned(msel'range) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
MS <= (others => '-');
elsif start = '1' then
MS <= unsigned(msel);
end if;
end if;
end process;
multiplier <= (others => 'X') when Is_X(std_logic_vector(MS)) else
to_unsigned(MULS(to_integer(MS)), multiplier'length);
end generate genMultiMul;
genSingleMul: if MULS'length = 1 generate
multiplier <= to_unsigned(MULS(0), multiplier'length);
end generate genSingleMul;
-- Selection of Divisor
genMultiDiv: if DIVS'length > 1 generate
signal DS : unsigned(dsel'range) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
DS <= (others => '-');
elsif start = '1' then
DS <= unsigned(dsel);
end if;
end if;
end process;
muloffset <= (others => 'X') when Is_X(dsel) else
to_unsigned(DIVS(to_integer(unsigned(dsel)))/2, muloffset'length);
divisor <= (others => 'X') when Is_X(std_logic_vector(DS)) else
to_unsigned(DIV_PROPS.align(to_integer(DS)), divisor'length);
divcini <= (others => 'X') when Is_X(std_logic_vector(DS)) else
to_unsigned(DIV_PROPS.steps(to_integer(DS))-1, divcini'length);
divmask <= (others => 'X') when Is_X(std_logic_vector(DS)) else
RES_MASKS(to_integer(DS));
end generate genMultiDiv;
genSingleDiv: if DIVS'length = 1 generate
muloffset <= to_unsigned(DIVS(0)/2, muloffset'length);
divisor <= to_unsigned(DIV_PROPS.align(0), divisor'length);
divcini <= to_unsigned(DIV_PROPS.steps(0)-1, divcini'length);
divmask <= RES_MASKS(0);
end generate genSingleDiv;
-----------------------------------------------------------------------------
-- Implementation of Scaling Operation
blkMain : block
signal C : unsigned(1+log2ceil(MAX_ANY_STEPS) downto 0) := ('0', others => '-');
signal Q : unsigned(X+N downto 0) := (others => '-');
begin
process(clk)
variable cnxt : unsigned(C'range);
variable d : unsigned(R downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
C <= ('0', others => '-');
Q <= (others => '-');
else
if start = '1' then
C <= "11" & to_unsigned(MAX_MUL_STEPS-1, C'length-2);
Q <= '0' & muloffset & unsigned(arg);
elsif C(C'left) = '1' then
cnxt := C - 1;
if C(C'left-1) = '1' then
-- MUL Phase
Q <= "00" & Q(X+N-1 downto 1);
if Q(0) = '1' then
Q(X+N-1 downto N-1) <= ('0' & Q(X+N-1 downto N)) + multiplier;
end if;
-- Transition to DIV
if cnxt(cnxt'left-1) = '0' then
cnxt(cnxt'left-2 downto 0) := divcini;
end if;
else
-- DIV Phase
d := Q(Q'left downto Q'left-R) - divisor;
Q <= Q(Q'left-1 downto 0) & not d(d'left);
if d(d'left) = '0' then
Q(Q'left downto Q'left-R+1) <= d(d'left-1 downto 0);
end if;
end if;
C <= cnxt;
end if;
end if;
end if;
end process;
done <= not C(C'left);
process(Q, divmask)
variable r : std_logic_vector(res'length-1 downto 0);
begin
r := (others => '0');
r(imin(r'left, tResMask'left) downto 0) :=
std_logic_vector(Q(imin(r'left, tResMask'left) downto 0)) and
divmask(imin(r'left, tResMask'left) downto 0);
res <= r;
end process;
end block blkMain;
end rtl;
| apache-2.0 | 03d7f41e05a0522c85d8fd1e51490535 | 0.599018 | 3.278651 | false | false | false | false |
hoangt/PoC | src/common/components.vhdl | 1 | 11,439 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives described as a function
--
-- Description:
-- ------------------------------------
-- This packages describes common primitives like flip flops and multiplexers
-- as a function to use them as one-liners.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
PACKAGE components IS
-- FlipFlop functions
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with reset and enable
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function sr_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- compare
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allzero(value : UNSIGNED) return STD_LOGIC;
function comp_allzero(value : SIGNED) return STD_LOGIC;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allone(value : UNSIGNED) return STD_LOGIC;
function comp_allone(value : SIGNED) return STD_LOGIC;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED;
end;
package body components is
-- d-flipflop with reset and enable
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) and not rst;
end function;
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is
begin
return ((d and (q'range => en)) or (q and not (q'range => en))) and not (q'range => rst);
end function;
-- d-flipflop with set and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) or set;
end function;
-- t-flipflop with reset and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((not q and en) or (q and not en)) and not rst;
end function;
-- rs-flipflop with dominant rst
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q or set) and not rst;
end function;
-- rs-flipflop with dominant set
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q and not rst) or set;
end function;
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(value), increment));
end function;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED is
begin
return value + increment;
end function;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED is
begin
return value + increment;
end function;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(dec(unsigned(value), decrement));
end function;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED is
begin
return value + decrement;
end function;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED is
begin
return value + decrement;
end function;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(not value))); -- 2's complement
end function;
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED is
begin
if (rst = '1') then
return to_unsigned(init, cnt'length);
elsif (en = '1') then
return cnt + 1;
else
return cnt;
end if;
end function;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is
begin
-- optimized comparison for only up counting values
return to_sl((cnt and to_unsigned(value, cnt'length)) = value);
end function;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED is
begin
if (rst = '1') then
return to_signed(init, cnt'length);
elsif (en = '1') then
return cnt - 1;
else
return cnt;
end if;
end function;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is
begin
-- optimized comparison for only down counting values
return to_sl((cnt nor to_signed(value, cnt'length)) /= value);
end function;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC is
begin
return cnt(cnt'high);
end function;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & i;
end function;
function sr_right(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return i & q(q'left downto q'right - 1);
end function;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & q(q'left);
end function;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'right) & q(q'left downto q'right - 1);
end function;
-- compare functions
-- return value 1- => value1 < value2 (difference is negative)
-- return value 00 => value1 = value2 (difference is zero)
-- return value -1 => value1 > value2 (difference is positive)
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING;
return std_logic_vector(comp(unsigned(value1), unsigned(value2)));
end function;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allzero(unsigned(value));
end function;
function comp_allzero(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allzero(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allone(unsigned(value));
end function;
function comp_allone(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
function comp_allone(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is
begin
return (sl0 and not sel) or (sl1 and sel);
end function;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is
begin
return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel));
end function;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is
begin
return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel));
end function;
end package body;
| apache-2.0 | 5dc0afec0fa5ade437fe1dd26fe94cdd | 0.670601 | 3.288014 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_mii_to_rmii_0_0/synth/design_1_mii_to_rmii_0_0.vhd | 2 | 7,550 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mii_to_rmii:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mii_to_rmii_v2_0;
USE mii_to_rmii_v2_0.mii_to_rmii;
ENTITY design_1_mii_to_rmii_0_0 IS
PORT (
rst_n : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
mac2rmii_tx_en : IN STD_LOGIC;
mac2rmii_txd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mac2rmii_tx_er : IN STD_LOGIC;
rmii2mac_tx_clk : OUT STD_LOGIC;
rmii2mac_rx_clk : OUT STD_LOGIC;
rmii2mac_col : OUT STD_LOGIC;
rmii2mac_crs : OUT STD_LOGIC;
rmii2mac_rx_dv : OUT STD_LOGIC;
rmii2mac_rx_er : OUT STD_LOGIC;
rmii2mac_rxd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy2rmii_crs_dv : IN STD_LOGIC;
phy2rmii_rx_er : IN STD_LOGIC;
phy2rmii_rxd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_txd : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_tx_en : OUT STD_LOGIC
);
END design_1_mii_to_rmii_0_0;
ARCHITECTURE design_1_mii_to_rmii_0_0_arch OF design_1_mii_to_rmii_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT mii_to_rmii IS
GENERIC (
C_INSTANCE : STRING;
C_FIXED_SPEED : STD_LOGIC;
C_SPEED_100 : STD_LOGIC
);
PORT (
rst_n : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
mac2rmii_tx_en : IN STD_LOGIC;
mac2rmii_txd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mac2rmii_tx_er : IN STD_LOGIC;
rmii2mac_tx_clk : OUT STD_LOGIC;
rmii2mac_rx_clk : OUT STD_LOGIC;
rmii2mac_col : OUT STD_LOGIC;
rmii2mac_crs : OUT STD_LOGIC;
rmii2mac_rx_dv : OUT STD_LOGIC;
rmii2mac_rx_er : OUT STD_LOGIC;
rmii2mac_rxd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy2rmii_crs_dv : IN STD_LOGIC;
phy2rmii_rx_er : IN STD_LOGIC;
phy2rmii_rxd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_txd : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_tx_en : OUT STD_LOGIC
);
END COMPONENT mii_to_rmii;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "mii_to_rmii,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mii_to_rmii_0_0_arch : ARCHITECTURE IS "design_1_mii_to_rmii_0_0,mii_to_rmii,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "design_1_mii_to_rmii_0_0,mii_to_rmii,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mii_to_rmii,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_INSTANCE=design_1_mii_to_rmii_0_0,C_FIXED_SPEED=1,C_SPEED_100=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
ATTRIBUTE X_INTERFACE_INFO OF ref_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_txd: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_tx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_ER";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rxd: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_crs_dv: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M CRS_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_rx_er: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_rxd: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M RXD";
ATTRIBUTE X_INTERFACE_INFO OF rmii2phy_txd: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M TXD";
ATTRIBUTE X_INTERFACE_INFO OF rmii2phy_tx_en: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M TX_EN";
BEGIN
U0 : mii_to_rmii
GENERIC MAP (
C_INSTANCE => "design_1_mii_to_rmii_0_0",
C_FIXED_SPEED => '1',
C_SPEED_100 => '1'
)
PORT MAP (
rst_n => rst_n,
ref_clk => ref_clk,
mac2rmii_tx_en => mac2rmii_tx_en,
mac2rmii_txd => mac2rmii_txd,
mac2rmii_tx_er => mac2rmii_tx_er,
rmii2mac_tx_clk => rmii2mac_tx_clk,
rmii2mac_rx_clk => rmii2mac_rx_clk,
rmii2mac_col => rmii2mac_col,
rmii2mac_crs => rmii2mac_crs,
rmii2mac_rx_dv => rmii2mac_rx_dv,
rmii2mac_rx_er => rmii2mac_rx_er,
rmii2mac_rxd => rmii2mac_rxd,
phy2rmii_crs_dv => phy2rmii_crs_dv,
phy2rmii_rx_er => phy2rmii_rx_er,
phy2rmii_rxd => phy2rmii_rxd,
rmii2phy_txd => rmii2phy_txd,
rmii2phy_tx_en => rmii2phy_tx_en
);
END design_1_mii_to_rmii_0_0_arch;
| gpl-3.0 | cb8c100b8aa5ca1da9028acc1d1df174 | 0.707682 | 3.157675 | false | false | false | false |
speters/mprfgen | useful_functions_pkg.vhd | 1 | 4,233 | --
-- VHDL package with some useful functions.
-- Milestones:
-- Date: 14 Feb 2002 07:13:55 (GW+02:00)
-- Author: Nick Kavvadias
-- Comments:
-- Revision History:
-- 26/04/02: Added LOG2 function proposed by Ray Andraka.
-- 26/04/02: Not correct (rounds at +1 int), corrected by Nick Kavvadias.
-- 26/04/02: LOGN function proposed by Nick Kavvadias.
-- 27/04/02: int_to_str, hex_str_to_int, Shrink_line functs/procs
-- added. Originally proposed in various LPM codes (of Altera).
-- 10/05/02: bin_str_to_int added for ROM Memory "Initialization".
-- ??/??/??: int_to_str, hex_str_to_int, Shrink_line, bin_str_to_int
-- removed.
--
library IEEE;
use IEEE.std_logic_1164.all;
package useful_functions_pkg is
function LOG2F(input: INTEGER) return INTEGER;
function LOG2C(input: INTEGER) return INTEGER;
function LOG2CTAB(input: INTEGER) return INTEGER;
function NUMBITS(input: INTEGER) return INTEGER;
function LOGNF(input: INTEGER; N: INTEGER) return INTEGER;
function LOGNC(input: INTEGER; N: INTEGER) return INTEGER;
end useful_functions_pkg;
package body useful_functions_pkg is
----------------------------------------------------------------------------
-- Base-2 logarithm function (LOG2F(x)) [rounds to floor]
----------------------------------------------------------------------------
function LOG2F(input: INTEGER) return INTEGER is
variable temp,log: INTEGER;
begin
temp := input;
log := 0;
while (temp > 1) loop
temp := temp/2;
log := log+1;
end loop;
return log;
end function LOG2F;
----------------------------------------------------------------------------
-- Base-2 logarithm function (LOG2C(x)) [rounds to ceiling]
-- Adopted from Reto Zimmermann's "arith_lib" (was: log2ceil)
----------------------------------------------------------------------------
function LOG2C(input: INTEGER) return INTEGER is
variable temp,log: INTEGER;
begin
log := 0;
temp := 1;
for i in 0 to input loop
if temp < input then
log := log + 1;
temp := temp * 2;
end if;
end loop;
return (log);
end function LOG2C;
function LOG2CTAB(input: INTEGER) return INTEGER is
variable log: INTEGER;
begin
case input is
when 0 to 1 => log := 0;
when 2 => log := 1;
when 3 to 4 => log := 2;
when 5 to 8 => log := 3;
when 9 to 16 => log := 4;
when 17 to 32 => log := 5;
when 33 to 64 => log := 6;
when 65 to 128 => log := 7;
when others => log := 0;
end case;
return (log);
end function LOG2CTAB;
function NUMBITS(input: INTEGER) return INTEGER is
variable temp : INTEGER := input;
variable result : INTEGER := 1;
begin
loop
temp := temp/2;
exit when temp = 0;
result := result + 1;
end loop;
return result;
end NUMBITS;
----------------------------------------------------------------------------
-- Base-N logarithm function (LOGNF(x,N)) [rounds to floor]
----------------------------------------------------------------------------
function LOGNF(input: INTEGER; N: INTEGER) return INTEGER is
variable temp,log: INTEGER;
begin
temp := input;
log := 0;
while (temp >= N) loop
temp := temp / N;
log := log + 1;
end loop;
return log;
end function LOGNF;
----------------------------------------------------------------------------
-- Base-N logarithm function (LOGNC(x,N)) [rounds to ceiling]
----------------------------------------------------------------------------
function LOGNC(input: INTEGER; N: INTEGER) return INTEGER is
variable temp,log: INTEGER;
begin
temp := 1;
log := 0;
for i in 0 to input-1 loop
exit when temp >= input;
log := log + 1;
temp := temp * N;
end loop;
return log;
end function LOGNC;
end useful_functions_pkg;
--
-- "The more i want something done, the less i call it work."
-- Richard Bach
--
| gpl-3.0 | c47bd819acf6409cfaf58ce9fcbc5d76 | 0.495393 | 4.054598 | false | false | false | false |
bpervan/uart | UARTReciever.vhd | 1 | 3,296 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:12 03/11/2014
-- Design Name:
-- Module Name: UARTReciever - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTReciever is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
rx : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0);
rx_done : out STD_LOGIC;
led : out std_logic_vector (6 downto 0));
end UARTReciever;
architecture Behavioral of UARTReciever is
type state_type is (idle, start, data, stop);
signal next_state, current_state : state_type;
signal tick_counter, tick_counter_next : unsigned (3 downto 0);
signal bit_counter, bit_counter_next : unsigned (2 downto 0);
signal reg, reg_next : std_logic_vector (7 downto 0);
signal ledReg, ledRegNext : std_logic_vector (6 downto 0);
begin
process (clk, rst)
begin
if (rst = '1') then
current_state <= idle;
tick_counter <= "0000";
bit_counter <= "000";
ledReg <= "0000000";
reg <= (others => '0');
else
if (clk'event and clk = '1') then
current_state <= next_state;
tick_counter <= tick_counter_next;
bit_counter <= bit_counter_next;
ledReg <= ledRegNext;
reg <= reg_next;
end if;
end if;
end process;
process(current_state, tick_counter, bit_counter, reg, tick, rx)
begin
next_state <= current_state;
tick_counter_next <= tick_counter;
bit_counter_next <= bit_counter;
reg_next <= reg;
rx_done <= '0';
ledRegNext <= ledReg;
case current_state is
when idle =>
if(rx = '0') then
next_state <= start;
ledRegNext <= "0000001";
tick_counter_next <= "0000";
end if;
when start =>
if(tick = '1') then
if(tick_counter < 7) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
bit_counter_next <= "000";
ledRegNext <= "0000010";
next_state <= data;
end if;
end if;
when data =>
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
tick_counter_next <= "0000";
reg_next <= rx & reg (7 downto 1);
if (bit_counter = 7) then
ledRegNext <= "0000011";
next_state <= stop;
else
bit_counter_next <= bit_counter + 1;
end if;
end if;
end if;
when stop =>
if(tick = '1') then
if(tick_counter < 15) then
tick_counter_next <= tick_counter + 1;
else
next_state <= idle;
ledRegNext <= "0000100";
rx_done <= '1';
end if;
end if;
end case;
end process;
led <= ledReg;
d_out <= reg;
end Behavioral;
| mit | 7fc65e35b8ad0b19ccb3a571c78a076f | 0.574636 | 3.296 | false | false | false | false |
lowRISC/greth-library | greth_library/ambalib/axictrl.vhd | 2 | 6,052 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details Implementation of the axictrl device.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
--! @brief AXI (NASTI) bus controller.
--! @details Simplified version with the hardcoded priorities to bus access.
--! Lower master index has a higher priority.
--! @todo Round-robin algorithm for the master selection.
entity axictrl is
generic (
rdslave_with_waitstate : boolean := false
);
port (
clk : in std_logic;
nrst : in std_logic;
slvoi : in nasti_slaves_out_vector;
mstoi : in nasti_master_out_vector;
slvio : out nasti_slave_in_type;
mstio : out nasti_master_in_type
);
end;
architecture arch_axictrl of axictrl is
constant MSTZERO : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0) := (others => '0');
type reg_type is record
mstidx : integer range 0 to CFG_NASTI_MASTER_TOTAL-1;
mstsel : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
cur_slave : nasti_slave_out_type; -- 1 clock wait state
end record;
signal rin, r : reg_type;
begin
comblogic : process(mstoi, slvoi, r)
variable v : reg_type;
variable busreq : std_logic;
variable mstsel : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
variable n, mstidx, mstidx_cur : integer range 0 to CFG_NASTI_MASTER_TOTAL-1;
variable cur_master : nasti_master_out_type;
variable cur_slave : nasti_slave_out_type;
variable busy : std_logic;
begin
v := r;
mstsel := r.mstsel;
busreq := '0';
mstidx := 0;
v.cur_slave := nasti_slave_out_none;
cur_master := nasti_master_out_none;
-- Select master bus:
for n in 0 to CFG_NASTI_MASTER_TOTAL-1 loop
if (mstoi(n).ar_valid or mstoi(n).aw_valid) = '1' then
mstidx := n;
busreq := '1';
end if;
cur_master.b_ready := cur_master.b_ready or mstoi(n).b_ready;
cur_master.r_ready := cur_master.r_ready or mstoi(n).r_ready;
end loop;
busy := mstoi(r.mstidx).w_valid or mstoi(r.mstidx).r_ready;
if (r.mstsel = MSTZERO) or ((busreq and not busy) = '1') then
mstsel(r.mstidx) := '0';
mstsel(mstidx) := busreq;
v.mstidx := mstidx;
mstidx_cur := mstidx;
else
mstidx_cur := r.mstidx;
end if;
if mstoi(mstidx_cur).aw_valid = '1' then
cur_master.aw_valid := mstoi(mstidx_cur).aw_valid;
cur_master.aw_bits := mstoi(mstidx_cur).aw_bits;
cur_master.aw_id := mstoi(mstidx_cur).aw_id;
cur_master.aw_user := mstoi(mstidx_cur).aw_user;
end if;
if mstoi(mstidx_cur).w_valid = '1' then
cur_master.w_valid := mstoi(mstidx_cur).w_valid;
cur_master.w_data := mstoi(mstidx_cur).w_data;
cur_master.w_last := mstoi(mstidx_cur).w_last;
cur_master.w_strb := mstoi(mstidx_cur).w_strb;
cur_master.w_user := mstoi(mstidx_cur).w_user;
end if;
if mstoi(mstidx_cur).ar_valid = '1' then
cur_master.ar_valid := mstoi(mstidx_cur).ar_valid;
cur_master.ar_bits := mstoi(mstidx_cur).ar_bits;
cur_master.ar_id := mstoi(mstidx_cur).ar_id;
cur_master.ar_user := mstoi(mstidx_cur).ar_user;
end if;
-- Select slave bus:
for n in 0 to CFG_NASTI_SLAVES_TOTAL-1 loop
v.cur_slave.ar_ready := v.cur_slave.ar_ready or slvoi(n).ar_ready;
v.cur_slave.aw_ready := v.cur_slave.aw_ready or slvoi(n).aw_ready;
v.cur_slave.w_ready := v.cur_slave.w_ready or slvoi(n).w_ready;
if v.cur_slave.b_valid = '0' and slvoi(n).b_valid = '1' then
v.cur_slave.b_valid := '1';
v.cur_slave.b_resp := slvoi(n).b_resp;
v.cur_slave.b_id := slvoi(n).b_id;
v.cur_slave.b_user := slvoi(n).b_user;
end if;
if v.cur_slave.r_valid = '0' and slvoi(n).r_valid = '1' then
v.cur_slave.r_valid := '1';
v.cur_slave.r_resp := slvoi(n).r_resp;
v.cur_slave.r_data := slvoi(n).r_data;
v.cur_slave.r_last := slvoi(n).r_last;
v.cur_slave.r_id := slvoi(n).r_id;
v.cur_slave.r_user := slvoi(n).r_user;
end if;
end loop;
v.mstsel := mstsel;
if rdslave_with_waitstate then
cur_slave := r.cur_slave;
else
cur_slave := v.cur_slave;
end if;
rin <= v;
mstio.grant <= mstsel;
mstio.aw_ready <= cur_slave.aw_ready;
mstio.w_ready <= cur_slave.w_ready;
mstio.b_valid <= cur_slave.b_valid;
mstio.b_resp <= cur_slave.b_resp;
mstio.b_id <= cur_slave.b_id;
mstio.b_user <= cur_slave.b_user;
mstio.ar_ready <= cur_slave.ar_ready;
mstio.r_valid <= cur_slave.r_valid;
mstio.r_resp <= cur_slave.r_resp;
mstio.r_data <= cur_slave.r_data;
mstio.r_last <= cur_slave.r_last;
mstio.r_id <= cur_slave.r_id;
mstio.r_user <= cur_slave.r_user;
slvio.aw_valid <= cur_master.aw_valid;
slvio.aw_bits <= cur_master.aw_bits;
slvio.aw_id <= cur_master.aw_id;
slvio.aw_user <= cur_master.aw_user;
slvio.w_valid <= cur_master.w_valid;
slvio.w_data <= cur_master.w_data;
slvio.w_last <= cur_master.w_last;
slvio.w_strb <= cur_master.w_strb;
slvio.w_user <= cur_master.w_user;
slvio.b_ready <= cur_master.b_ready;
slvio.ar_valid <= cur_master.ar_valid;
slvio.ar_bits <= cur_master.ar_bits;
slvio.ar_id <= cur_master.ar_id;
slvio.ar_user <= cur_master.ar_user;
slvio.r_ready <= cur_master.r_ready;
end process;
reg0 : process(clk, nrst) begin
if nrst = '0' then
r.mstidx <= 0;
r.mstsel <= (others =>'0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 171e050262c14d829a157cde7d19a06c | 0.583278 | 3.041206 | false | false | false | false |
MikhailKoslowski/Variax | Quartus/flashreader.vhd | 1 | 2,009 | -----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY FlashReader IS
PORT (
KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
UART_TXD : OUT STD_LOGIC
);
END FlashReader;
--------------------------------------------------------
ARCHITECTURE structure OF FlashReader IS
COMPONENT FlashController
PORT (
clk : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT BaudGenerator IS
PORT ( clk : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT UartTransmitter IS
PORT (
clk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
send : IN STD_LOGIC;
rdy : OUT STD_LOGIC;
TXD : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DataGenerator IS
PORT (
clk : IN STD_LOGIC;
nxt : IN STD_LOGIC;
data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL uart_send : STD_LOGIC;
SIGNAL uart_clk : STD_LOGIC;
SIGNAL uart_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL uart_rdy : STD_LOGIC := '1';
SIGNAL s_addr : STD_LOGIC_VECTOR(18 DOWNTO 0);
BEGIN
controller : FlashController PORT MAP ( clk => CLOCK_50, addr=>s_addr, data=>LEDG(7 DOWNTO 0), rdy=>LEDG(9));
baudgen : BaudGenerator PORT MAP ( clk => CLOCK_50, clk_out => uart_clk);
transmitter : UartTransmitter PORT MAP (clk => uart_clk, data => uart_data, send => uart_send, rdy=>uart_rdy, TXD => UART_TXD);
datagen : DataGenerator PORT MAP ( clk=> CLOCK_50, nxt => uart_rdy, data => uart_data, rdy => uart_send);
s_addr(9 DOWNTO 0) <= SW;
s_addr(18 DOWNTO 10) <= "000000000";
END structure;
-------------------------------------------------------- | mit | 0f7f846818248ed05b7f85d5576a6767 | 0.58885 | 3.475779 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_pkg.vhd | 4 | 2,913 | library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package emc_pkg is
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
end emc_pkg;
package body emc_pkg is
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
end package body emc_pkg;
| gpl-3.0 | 286f9189c6e7c426e714bacde1936351 | 0.559217 | 4.43379 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/rx_intrfce.vhd | 4 | 13,504 | -------------------------------------------------------------------------------
-- rx_intrfce - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_intrfce.vhd
-- Version : v2.0
-- Description : This is the ethernet receive interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.all;
--library fifo_generator_v11_0; -- FIFO HIER
--use fifo_generator_v11_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
library unisim;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_rx_clk -- PHY RX Clock
-- InternalWrapEn -- Internal wrap enable
-- Phy_rx_er -- Receive error
-- Phy_dv -- Ethernet receive enable
-- Phy_rx_data -- Ethernet receive data
-- Rcv_en -- Receive enable
-- Fifo_empty -- RX FIFO empty
-- Fifo_full -- RX FIFO full
-- Emac_rx_rd -- RX FIFO Read enable
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- RdAck -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_intrfce is
generic
(
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_rx_clk : in std_logic;
InternalWrapEn : in std_logic;
Phy_rx_er : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Rcv_en : in std_logic;
Fifo_empty : out std_logic;
Fifo_full : out std_logic;
Emac_rx_rd : in std_logic;
Emac_rx_rd_data : out std_logic_vector (0 to 5);
RdAck : out std_logic
);
end rx_intrfce;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of rx_intrfce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal rxBusCombo : std_logic_vector (0 to 5);
signal rx_wr_en : std_logic;
signal rx_data : std_logic_vector (0 to 5);
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_rd_ack : std_logic;
signal rst_s : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
-------------------------------------------------------------------------------
--FIFI HIER
--component async_fifo_eth
-- port (
-- rst : in std_logic;
-- wr_clk : in std_logic;
-- rd_clk : in std_logic;
-- din : in std_logic_vector(5 downto 0);
-- wr_en : in std_logic;
-- rd_en : in std_logic;
-- dout : out std_logic_vector(5 downto 0);
-- full : out std_logic;
-- empty : out std_logic;
-- valid : out std_logic
-- );
--end component;
begin
----------------------------------------------------------------------------
-- CDC module for syncing reset in wr clk domain
----------------------------------------------------------------------------
CDC_FIFO_RST: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Rst,
prmry_ack => open,
scndry_out => rst_s,
scndry_aclk => Phy_rx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
I_RX_FIFO: entity lib_fifo_v1_0.async_fifo_fg
generic map(
C_ALLOW_2N_DEPTH => 0, -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY, -- new for FIFO Gen
C_DATA_WIDTH => 6,
C_ENABLE_RLOCS => 0, -- not supported in FG
C_FIFO_DEPTH => 15,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 2,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0, -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 2,
C_WR_ERR_LOW => 0
)
port map(
Din => rxBusCombo,
Wr_en => rx_wr_en,
Wr_clk => Phy_rx_clk,
Rd_en => Emac_rx_rd,
Rd_clk => Clk,
Ainit => rst_s,
Dout => rx_data,
Full => rx_fifo_full,
Empty => rx_fifo_empty,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => rx_rd_ack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
-- FIFO HIER
-- I_RX_FIFO : async_fifo_eth
-- port map(
-- din => rxBusCombo,
-- wr_en => rx_wr_en,
-- wr_clk => Phy_rx_clk,
-- rd_en => Emac_rx_rd,
-- rd_clk => Clk,
-- rst => Rst,
-- dout => rx_data,
-- full => rx_fifo_full,
-- empty => rx_fifo_empty,
-- valid => rx_rd_ack
-- );
rxBusCombo <= (Phy_rx_data & Phy_dv & Phy_rx_er);
Emac_rx_rd_data <= rx_data;
RdAck <= rx_rd_ack;
Fifo_full <= rx_fifo_full;
Fifo_empty <= rx_fifo_empty;
--rx_wr_en <= Rcv_en;
rx_wr_en <= not(rx_fifo_full); -- having this as Rcv_en is generated in lite_clock domain and passing to FIFO working in rx_clk domain
end implementation;
| gpl-3.0 | 2e634c1d71f2e9a4900d94d4806d46d6 | 0.3867 | 4.540686 | false | false | false | false |
hoangt/PoC | src/io/uart/uart_fifo.vhdl | 1 | 9,997 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: UART Wrapper with Embedded FIFOs and Optional Flow Control
--
-- Description:
-- ------------------------------------
-- Small FIFOs are included in this module, if larger or asynchronous
-- transmit / receive FIFOs are required, then they must be connected
-- externally.
--
-- old comments:
-- UART BAUD rate generator
-- bclk = bit clock is rising
-- bclk_x8 = bit clock times 8 is rising
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.uart.all;
entity uart_fifo is
generic (
-- Communication Parameters
CLOCK_FREQ : FREQ;
BAUDRATE : BAUD;
-- Buffer Dimensioning
TX_MIN_DEPTH : positive := 16;
TX_ESTATE_BITS : natural := 0;
RX_MIN_DEPTH : positive := 16;
RX_FSTATE_BITS : natural := 0;
-- Flow Control
FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE;
SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q
SWFC_XON_TRIGGER : real := 0.0625;
SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S
SWFC_XOFF_TRIGGER : real := 0.75
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- FIFO interface
TX_put : in STD_LOGIC;
TX_Data : in STD_LOGIC_VECTOR(7 downto 0);
TX_Full : out STD_LOGIC;
TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0);
RX_Valid : out STD_LOGIC;
RX_Data : out STD_LOGIC_VECTOR(7 downto 0);
RX_got : in STD_LOGIC;
RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0);
RX_Overflow : out std_logic;
-- External pins
UART_TX : out std_logic;
UART_RX : in std_logic
);
end entity;
architecture rtl of uart_fifo is
signal FC_TX_Strobe : STD_LOGIC;
signal FC_TX_Data : T_SLV_8;
signal FC_TX_got : STD_LOGIC;
signal FC_RX_put : STD_LOGIC;
signal FC_RX_Data : T_SLV_8;
signal TXFIFO_Valid : STD_LOGIC;
signal TXFIFO_Data : T_SLV_8;
signal RXFIFO_Full : STD_LOGIC;
signal TXUART_Full : STD_LOGIC;
signal RXUART_Strobe : STD_LOGIC;
signal RXUART_Data : T_SLV_8;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX_sync : STD_LOGIC;
begin
assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE;
-- ===========================================================================
-- Transmit and Receive FIFOs
-- ===========================================================================
TXFIFO : entity PoC.fifo_cc_got
generic map (
D_BITS => 8, -- Data Width
MIN_DEPTH => TX_MIN_DEPTH, -- Minimum FIFO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FIFO Output
ESTATE_WR_BITS => TX_ESTATE_BITS, -- Empty State Bits
FSTATE_RD_BITS => 0 -- Full State Bits
)
port map (
rst => Reset,
clk => Clock,
put => TX_put,
din => TX_Data,
full => TX_Full,
estate_wr => TX_EmptyState,
valid => TXFIFO_Valid,
dout => TXFIFO_Data,
got => FC_TX_got,
fstate_rd => open
);
RXFIFO : entity PoC.fifo_cc_got
generic map (
D_BITS => 8, -- Data Width
MIN_DEPTH => RX_MIN_DEPTH, -- Minimum FIFO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FIFO Output
ESTATE_WR_BITS => 0, -- Empty State Bits
FSTATE_RD_BITS => RX_FSTATE_BITS -- Full State Bits
)
port map (
rst => Reset,
clk => Clock,
put => FC_RX_put,
din => FC_RX_Data,
full => RXFIFO_Full,
estate_wr => open,
valid => RX_Valid,
dout => RX_Data,
got => RX_got,
fstate_rd => RX_FullState
);
genNOFC : if (FLOWCONTROL = UART_FLOWCONTROL_NONE) generate
signal Overflow_r : std_logic := '0';
begin
FC_TX_Strobe <= TXFIFO_Valid and not TXUART_Full;
FC_TX_Data <= TXFIFO_Data;
FC_TX_got <= FC_TX_Strobe;
FC_RX_put <= RXUART_Strobe;
FC_RX_Data <= RXUART_Data;
Overflow_r <= ffrs(q => Overflow_r, rst => Reset, set => (RXUART_Strobe and RXFIFO_Full)) when rising_edge(Clock);
RX_Overflow <= Overflow_r;
end generate;
-- ===========================================================================
-- Software Flow Control
-- ===========================================================================
genSWFC : if (FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF) generate
constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q
constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S
constant XON_TRIG : integer := integer(SWFC_XON_TRIGGER * real(2**RX_FSTATE_BITS));
constant XOFF_TRIG : integer := integer(SWFC_XOFF_TRIGGER * real(2**RX_FSTATE_BITS));
signal send_xoff : std_logic;
signal send_xon : std_logic;
signal set_xoff_transmitted : std_logic;
signal clr_xoff_transmitted : std_logic;
signal discard_user : std_logic;
signal set_overflow : std_logic;
-- registers
signal xoff_transmitted : std_logic;
begin
-- -- send XOFF only once when fill state goes above trigger level
-- send_xoff <= (not xoff_transmitted) when (rf_fs >= XOFF_TRIG) else '0';
-- set_xoff_transmitted <= tx_rdy when (rf_fs >= XOFF_TRIG) else '0';
--
-- -- send XON only once when receive FIFO is almost empty
-- send_xon <= xoff_transmitted when (rf_fs = XON_TRIG) else '0';
-- clr_xoff_transmitted <= tx_rdy when (rf_fs = XON_TRIG) else '0';
--
-- -- discard any user supplied XON/XOFF
-- discard_user <= '1' when (tf_dout = SWFC_XON_CHAR) or (tf_dout = SWFC_XOFF_CHAR) else '0';
--
-- -- tx / tf control
-- tx_din <= SWFC_XOFF_CHAR when (send_xoff = '1') else
-- SWFC_XON_CHAR when (send_xon = '1') else
-- tf_dout;
--
-- tx_stb <= send_xoff or send_xon or (tf_valid and (not discard_user));
-- tf_got <= (send_xoff nor send_xon) and
-- tf_valid and tx_rdy; -- always check tf_valid
--
-- -- rx / rf control
-- rf_put <= (not rf_full) and rx_dos; -- always check rf_full
-- rf_din <= rx_dout;
--
-- set_overflow <= rf_full and rx_dos;
--
-- -- registers
-- process (Clock)
-- begin -- process
-- if rising_edge(Clock) then
-- if (rst or set_xoff_transmitted) = '1' then
-- -- send a XON after reset
-- xoff_transmitted <= '1';
-- elsif clr_xoff_transmitted = '1' then
-- xoff_transmitted <= '0';
-- end if;
--
-- if rst = '1' then
-- overflow <= '0';
-- elsif set_overflow = '1' then
-- overflow <= '1';
-- end if;
-- end if;
-- end process;
end generate;
-- ===========================================================================
-- Hardware Flow Control
-- ===========================================================================
genHWFC1 : if (FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS) generate
begin
end generate;
-- ===========================================================================
-- Hardware Flow Control
-- ===========================================================================
genHWFC2 : if (FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS) generate
begin
end generate;
-- ===========================================================================
-- BitClock, Transmitter, Receiver
-- ===========================================================================
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
UART_RX_sync <= UART_RX;
end generate;
genSync: if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => UART_RX, -- Data to be synchronized
Output(0) => UART_RX_sync -- synchronised data
);
end generate;
-- ===========================================================================
-- BitClock, Transmitter, Receiver
-- ===========================================================================
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
TX : entity PoC.uart_tx
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
tx => UART_TX
di => FC_TX_Data,
put => FC_TX_Strobe,
ful => TXUART_Full
);
RX : entity PoC.uart_rx
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
rx => UART_RX_sync,
do => RXUART_Data,
stb => RXUART_Strobe
);
end architecture;
| apache-2.0 | 2d89ee5eb68153249b33182b63d36432 | 0.535961 | 3.262728 | false | false | false | false |
bpervan/uart | Echo.vhd | 1 | 2,161 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:36:02 03/13/2014
-- Design Name:
-- Module Name: Echo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Echo is
Port ( d_in : in STD_LOGIC_VECTOR (7 downto 0);
r_done : in STD_LOGIC;
w_done : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
w_start : out STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0));
end Echo;
architecture Behavioral of Echo is
type state_type is (idle, send);
signal current_state, next_state : state_type;
signal w_start_reg, w_start_reg_next : std_logic;
signal d_out_reg, d_out_reg_next : std_logic_vector (7 downto 0);
begin
process(clk, rst)
begin
if(rst = '1') then
w_start_reg <= '0';
d_out_reg <= "00000000";
current_state <= idle;
else
if(rising_edge(clk)) then
w_start_reg <= w_start_reg_next;
d_out_reg <= d_out_reg_next;
current_state <= next_state;
end if;
end if;
end process;
process (r_done, d_in, w_start_reg, d_out_reg)
begin
w_start_reg_next <= w_start_reg;
d_out_reg_next <= d_out_reg;
next_state <= current_state;
case current_state is
when idle =>
if(r_done = '1') then
w_start_reg_next <= '1';
d_out_reg_next <= d_in;
next_state <= send;
end if;
when send =>
if (w_done = '1') then
next_state <= idle;
w_start_reg_next <= '0';
end if;
end case;
end process;
d_out <= d_out_reg;
w_start <= w_start_reg;
end Behavioral;
| mit | bf8788a871d5717d714b03b9c029dcb7 | 0.570569 | 3.087143 | false | false | false | false |
hoangt/PoC | tb/misc/sync/sync_Reset_tb.vhdl | 2 | 2,877 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a reset signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Reset_tb is
end;
architecture test of sync_Reset_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC := '0';
signal Sync_out : STD_LOGIC;
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= 'X';
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= '0';
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= '1';
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= '0';
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= '1';
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= '0';
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= '1';
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= '0';
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= '1';
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= '0';
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncReset : entity PoC.sync_Reset
port map (
Clock => Clock2, -- input clock domain
Input => Sync_in, -- input bits
Output => Sync_out -- output bits
);
end;
| apache-2.0 | ee96a9ebb0b12e69c1c52dd2ab9048f2 | 0.570038 | 3.218121 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/deferral.vhd | 4 | 10,729 | -------------------------------------------------------------------------------
-- deferral - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : deferral.vhd
-- Version : v2.0
-- Description : This file contains the transmit deferral control.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxEn -- Transmit enable
-- Txrst -- Transmit reset
-- Tx_clk_en -- Transmit clock enable
-- BackingOff -- Backing off
-- Crs -- Carrier sense
-- Full_half_n -- Full/Half duplex indicator
-- Ifgp1 -- Interframe gap delay
-- Ifgp2 -- Interframe gap delay
-- Deferring -- Deffering for the tx data
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity deferral is
port
(
Clk : in std_logic;
Rst : in std_logic;
TxEn : in std_logic;
Txrst : in std_logic;
Tx_clk_en : in std_logic;
BackingOff : in std_logic;
Crs : in std_logic;
Full_half_n : in std_logic;
Ifgp1 : in std_logic_vector(0 to 4);
Ifgp2 : in std_logic_vector(0 to 4);
Deferring : out std_logic
);
end deferral;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of deferral is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal cntrLd_i : std_logic;
signal cntrEn : std_logic;
signal comboCntrEn : std_logic;
signal comboCntrEn2 : std_logic;
signal ifgp1_zero : std_logic;
signal ifgp2_zero : std_logic;
signal comboRst : std_logic;
begin
comboRst <= Rst or Txrst;
comboCntrEn <= Tx_clk_en and cntrEn;
comboCntrEn2 <= Tx_clk_en and cntrEn and ifgp1_zero;
-------------------------------------------------------------------------------
-- Ifgp1 counter
-------------------------------------------------------------------------------
inst_ifgp1_count: entity axi_ethernetlite_v3_0.cntr5bit
port map
(
Clk => Clk,
Rst => comboRst,
En => comboCntrEn,
Ld => cntrLd_i,
Load_in => Ifgp1,
Zero => ifgp1_zero
);
-------------------------------------------------------------------------------
-- Ifgp2 counter
-------------------------------------------------------------------------------
inst_ifgp2_count: entity axi_ethernetlite_v3_0.cntr5bit
port map
(
Clk => Clk,
Rst => comboRst,
En => comboCntrEn2,
Ld => cntrLd_i,
Load_in => Ifgp2,
Zero => ifgp2_zero
);
-------------------------------------------------------------------------------
-- deferral state machine
-------------------------------------------------------------------------------
inst_deferral_state: entity axi_ethernetlite_v3_0.defer_state
port map
(
Clk => Clk,
Rst => Rst,
TxEn => TxEn,
Txrst => Txrst,
Ifgp2Done => ifgp2_zero,
Ifgp1Done => ifgp1_zero,
BackingOff => BackingOff,
Crs => Crs,
Full_half_n => Full_half_n,
Deferring => Deferring,
CntrEnbl => cntrEn,
CntrLd => cntrLd_i
);
end implementation;
| gpl-3.0 | fd0acea8051e68cd5c790b97c9a50a97 | 0.373847 | 5.31665 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/axi_ethernetlite.vhd | 4 | 41,624 | -------------------------------------------------------------------------------
-- axi_ethernetlite - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename : axi_ethernetlite.vhd
-- Version : v2.0
-- Description : This is the top level wrapper file for the Ethernet
-- Lite function It provides a 10 or 100 Mbs full or half
-- duplex Ethernet bus with an interface to an AXI Interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/29/2010 First Version
-- ^^^^^^
-- Removed ARLOCK and AWLOCK, AWPROT, ARPROT signals from the list.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.axi_interface;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
--
-- C_FAMILY -- Target device family
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 or 64 only
-- C_S_AXI_ID_WIDTH -- AXI Identification TAG width - 1 to 16
-- C_S_AXI_PROTOCOL -- AXI protocol type
--
-- C_DUPLEX -- 1 = Full duplex, 0 = Half duplex
-- C_TX_PING_PONG -- 1 = Ping-pong memory used for transmit buffer
-- 0 = Pong memory not used for transmit buffer
-- C_RX_PING_PONG -- 1 = Ping-pong memory used for receive buffer
-- 0 = Pong memory not used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface,
-- 0 = No MDIO Interface
-- C_INCLUDE_INTERNAL_LOOPBACK -- 1 = Include Internal Loopback logic,
-- 0 = Internal Loopback logic disabled
-- C_INCLUDE_GLOBAL_BUFFERS -- 1 = Include global buffers for PHY clocks
-- 0 = Use normal input buffers for PHY clocks
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - active low
-- -- interrupts
-- ip2intc_irpt -- Interrupt to processor
--==================================
-- axi write address Channel Signals
--==================================
-- s_axi_awid -- AXI Write Address ID
-- s_axi_awaddr -- AXI Write address - 32 bit
-- s_axi_awlen -- AXI Write Data Length
-- s_axi_awsize -- AXI Burst Size - allowed values
-- -- 000 - byte burst
-- -- 001 - half word
-- -- 010 - word
-- -- 011 - double word
-- -- NA for all remaining values
-- s_axi_awburst -- AXI Burst Type
-- -- 00 - Fixed
-- -- 01 - Incr
-- -- 10 - Wrap
-- -- 11 - Reserved
-- s_axi_awcache -- AXI Cache Type
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
--===============================
-- axi write data channel Signals
--===============================
-- s_axi_wdata -- AXI Write data width
-- s_axi_wstrb -- AXI Write strobes
-- s_axi_wlast -- AXI Last write indicator signal
-- s_axi_wvalid -- AXI Write valid
-- s_axi_wready -- AXI Write ready
--================================
-- axi write data response Signals
--================================
-- s_axi_bid -- AXI Write Response channel number
-- s_axi_bresp -- AXI Write response
-- -- 00 - Okay
-- -- 01 - ExOkay
-- -- 10 - Slave Error
-- -- 11 - Decode Error
-- s_axi_bvalid -- AXI Write response valid
-- s_axi_bready -- AXI Response ready
--=================================
-- axi read address Channel Signals
--=================================
-- s_axi_arid -- AXI Read ID
-- s_axi_araddr -- AXI Read address
-- s_axi_arlen -- AXI Read Data length
-- s_axi_arsize -- AXI Read Size
-- s_axi_arburst -- AXI Read Burst length
-- s_axi_arcache -- AXI Read Cache
-- s_axi_arprot -- AXI Read Protection
-- s_axi_rvalid -- AXI Read valid
-- s_axi_rready -- AXI Read ready
--==============================
-- axi read data channel Signals
--==============================
-- s_axi_rid -- AXI Read Channel ID
-- s_axi_rdata -- AXI Read data
-- s_axi_rresp -- AXI Read response
-- s_axi_rlast -- AXI Read Data Last signal
-- s_axi_rvalid -- AXI Read address valid
-- s_axi_rready -- AXI Read address ready
--
-- -- ethernet
-- phy_tx_clk -- Ethernet tranmit clock
-- phy_rx_clk -- Ethernet receive clock
-- phy_crs -- Ethernet carrier sense
-- phy_dv -- Ethernet receive data valid
-- phy_rx_data -- Ethernet receive data
-- phy_col -- Ethernet collision indicator
-- phy_rx_er -- Ethernet receive error
-- phy_rst_n -- Ethernet PHY Reset
-- phy_tx_en -- Ethernet transmit enable
-- phy_tx_data -- Ethernet transmit data
-- phy_mdio_i -- Ethernet PHY MDIO data input
-- phy_mdio_o -- Ethernet PHY MDIO data output
-- phy_mdio_t -- Ethernet PHY MDIO data 3-state control
-- phy_mdc -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity axi_ethernetlite is
generic
(
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_ethernetlite_inst";
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ID_WIDTH : integer := 4;
C_S_AXI_PROTOCOL : string := "AXI4";
C_INCLUDE_MDIO : integer := 1;
C_INCLUDE_INTERNAL_LOOPBACK : integer := 0;
C_INCLUDE_GLOBAL_BUFFERS : integer := 1;
C_DUPLEX : integer range 0 to 1:= 1;
C_TX_PING_PONG : integer range 0 to 1:= 0;
C_RX_PING_PONG : integer range 0 to 1:= 0
);
port
(
-- -- AXI Slave signals ------------------------------------------------------
-- -- AXI Global System Signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ip2intc_irpt : out std_logic;
-- -- axi slave burst Interface
-- -- axi write address Channel Signals
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(12 downto 0); -- (C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- -- axi write data Channel Signals
s_axi_wdata : in std_logic_vector(31 downto 0); -- (C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
--(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(12 downto 0); -- (C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0); -- (C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- -- Ethernet Interface
phy_tx_clk : in std_logic;
phy_rx_clk : in std_logic;
phy_crs : in std_logic;
phy_dv : in std_logic;
phy_rx_data : in std_logic_vector (3 downto 0);
phy_col : in std_logic;
phy_rx_er : in std_logic;
phy_rst_n : out std_logic;
phy_tx_en : out std_logic;
phy_tx_data : out std_logic_vector (3 downto 0);
phy_mdio_i : in std_logic;
phy_mdio_o : out std_logic;
phy_mdio_t : out std_logic;
phy_mdc : out std_logic
);
-- XST attributes
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
--Psfutil attributes
attribute ASSIGNMENT : string;
attribute ADDRESS : string;
attribute PAIR : string;
end axi_ethernetlite;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_ethernetlite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Parameters captured for webtalk
-- C_FAMILY
-- C_S_AXI_ACLK_PERIOD_PS
-- C_S_AXI_DATA_WIDTH
-- C_S_AXI_PROTOCOL
-- C_INCLUDE_MDIO
-- C_INCLUDE_INTERNAL_LOOPBACK
-- C_INCLUDE_GLOBAL_BUFFERS
-- C_DUPLEX
-- C_TX_PING_PONG
-- C_RX_PING_PONG
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_ethernetlite,{"
-- & "c_family=" & C_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",c_s_axi_protocol=" & C_S_AXI_PROTOCOL
-- & ",c_s_axi_aclk_period_ps=" & integer'image(C_S_AXI_ACLK_PERIOD_PS)
-- & ",c_s_axi_data_width=" & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",c_include_mdio=" & integer'image(C_INCLUDE_MDIO)
-- & ",c_include_internal_loopback=" & integer'image(C_INCLUDE_INTERNAL_LOOPBACK)
-- & ",c_include_global_buffers=" & integer'image(C_INCLUDE_GLOBAL_BUFFERS)
-- & ",c_duplex=" & integer'image(C_DUPLEX)
-- & ",c_tx_ping_pong=" & integer'image(C_TX_PING_PONG)
-- & ",c_rx_ping_pong=" & integer'image(C_RX_PING_PONG)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant NODE_MAC : bit_vector := x"00005e00FACE";
-------------------------------------------------------------------------------
-- Signal declaration Section
-------------------------------------------------------------------------------
signal phy_rx_clk_i : std_logic;
signal phy_tx_clk_i : std_logic;
signal phy_rx_clk_ib : std_logic;
signal phy_tx_clk_ib : std_logic;
signal phy_rx_data_i : std_logic_vector(3 downto 0);
signal phy_tx_data_i : std_logic_vector(3 downto 0);
signal phy_tx_data_i_cdc : std_logic_vector(3 downto 0);
signal phy_dv_i : std_logic;
signal phy_rx_er_i : std_logic;
signal phy_tx_en_i : std_logic;
signal phy_tx_en_i_cdc : std_logic;
signal Loopback : std_logic;
signal phy_rx_data_in : std_logic_vector (3 downto 0);
signal phy_rx_data_in_cdc : std_logic_vector (3 downto 0);
signal phy_dv_in : std_logic;
signal phy_dv_in_cdc : std_logic;
signal phy_rx_data_reg : std_logic_vector(3 downto 0);
signal phy_rx_er_reg : std_logic;
signal phy_dv_reg : std_logic;
signal phy_tx_clk_core : std_logic;
signal phy_rx_clk_core : std_logic;
-- IPIC Signals
signal temp_Bus2IP_Addr: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal Bus2IP_Data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal ip2bus_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_burst : std_logic;
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal bus_rst_tx_sync_core : std_logic;
--signal bus_rst_rx_sync : std_logic;
signal bus_rst_rx_sync_core : std_logic;
signal bus_rst : std_logic;
signal ip2bus_errack : std_logic;
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic := '0'
);
end component;
component BUFGMUX
port (
O : out std_ulogic;
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic
);
end component;
component BUF
port(
O : out std_ulogic;
I : in std_ulogic
);
end component;
COMPONENT IBUF
PORT(i : IN std_logic;
o : OUT std_logic);
END COMPONENT;
-- attribute IOB : string;
begin -- this is the begin between declarations and architecture body
-- PHY Reset
PHY_rst_n <= S_AXI_ARESETN ;
-- Bus Reset
bus_rst <= not S_AXI_ARESETN ;
BUS_RST_RX_SYNC_CORE_I: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => bus_rst,
prmry_ack => open,
scndry_out => bus_rst_rx_sync_core,
scndry_aclk => phy_rx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
BUS_RST_TX_SYNC_CORE_I: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => bus_rst,
prmry_ack => open,
scndry_out => bus_rst_tx_sync_core,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- LOOPBACK_GEN :- Include MDIO interface if the parameter
-- C_INCLUDE_INTERNAL_LOOPBACK = 1
----------------------------------------------------------------------------
LOOPBACK_GEN: if C_INCLUDE_INTERNAL_LOOPBACK = 1 generate
begin
-------------------------------------------------------------------------
-- INCLUDE_BUFG_GEN :- Include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 1
-------------------------------------------------------------------------
INCLUDE_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 1 generate
begin
-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF
port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);
RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
-------------------------------------------------------------------------
-- BUFG for TX clock
-------------------------------------------------------------------------
CLOCK_BUFG_TX: BUFG
port map (
O => phy_tx_clk_core, --[out]
I => PHY_tx_clk_ib --[in]
);
-------------------------------------------------------------------------
-- BUFGMUX for clock muxing in Loopback mode
-------------------------------------------------------------------------
CLOCK_MUX: BUFGMUX
port map (
O => phy_rx_clk_core, --[out]
I0 => PHY_rx_clk_ib, --[in]
I1 => phy_tx_clk_ib, --[in]
S => Loopback --[in]
);
end generate INCLUDE_BUFG_GEN;
-------------------------------------------------------------------------
-- NO_BUFG_GEN :- Dont include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 0
-------------------------------------------------------------------------
NO_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 0 generate
begin
phy_tx_clk_core <= PHY_tx_clk;
-------------------------------------------------------------------------
-- BUFGMUX for clock muxing in Loopback mode
-------------------------------------------------------------------------
CLOCK_MUX: BUFGMUX
port map (
O => phy_rx_clk_core, --[out]
I0 => PHY_rx_clk, --[in]
I1 => phy_tx_clk_core, --[in]
S => Loopback --[in]
);
end generate NO_BUFG_GEN;
-------------------------------------------------------------------------
-- Internal Loopback generation logic
-------------------------------------------------------------------------
phy_rx_data_in <= phy_tx_data_i when Loopback = '1' else
phy_rx_data_reg;
phy_dv_in <= phy_tx_en_i when Loopback = '1' else
phy_dv_reg;
-- No receive error is generated in internal loopback
phy_rx_er_i <= '0' when Loopback = '1' else
phy_rx_er_reg;
-- Transmit and Receive clocks
phy_tx_clk_i <= phy_tx_clk_core;--not(phy_tx_clk_core);
phy_rx_clk_i <= phy_rx_clk_core;--not(phy_rx_clk_core);
----------------------------------------------------------------------------
-- CDC module for syncing phy_dv_in in rx_clk domain
----------------------------------------------------------------------------
CDC_PHY_DV_IN: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => phy_dv_in,
prmry_ack => open,
scndry_out => phy_dv_in_cdc,
scndry_aclk => phy_rx_clk_i,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
--BUS_RST_RX_SYNC_I: entity lib_cdc_v1_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => bus_rst,
-- prmry_ack => open,
-- scndry_out => bus_rst_rx_sync,
-- scndry_aclk => phy_rx_clk_i,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
-------------------------------------------------------------------------
-- Registering RX signal
-------------------------------------------------------------------------
DV_FF: FDR
port map (
Q => phy_dv_i, --[out]
C => phy_rx_clk_i, --[in]
D => phy_dv_in_cdc, --[in]
R => bus_rst_rx_sync_core); --[in]
----------------------------------------------------------------------------
-- CDC module for syncing phy_rx_data_in in rx_clk domain
----------------------------------------------------------------------------
CDC_PHY_RX_DATA_IN: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => '1',
prmry_ack => open,
scndry_out => open,
scndry_aclk => phy_rx_clk_i,
scndry_resetn => '1',
prmry_vect_in => phy_rx_data_in,
scndry_vect_out => phy_rx_data_in_cdc
);
-------------------------------------------------------------------------
-- Registering RX data input with clock mux output
-------------------------------------------------------------------------
RX_REG_GEN: for i in 3 downto 0 generate
begin
RX_FF_LOOP: FDRE
port map (
Q => phy_rx_data_i(i), --[out]
C => phy_rx_clk_i, --[in]
CE => '1', --[in]
D => phy_rx_data_in_cdc(i), --[in]
R => bus_rst_rx_sync_core); --[in]
end generate RX_REG_GEN;
end generate LOOPBACK_GEN;
----------------------------------------------------------------------------
-- NO_LOOPBACK_GEN :- Include MDIO interface if the parameter
-- C_INCLUDE_INTERNAL_LOOPBACK = 0
----------------------------------------------------------------------------
NO_LOOPBACK_GEN: if C_INCLUDE_INTERNAL_LOOPBACK = 0 generate
begin
-------------------------------------------------------------------------
-- INCLUDE_BUFG_GEN :- Include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 1
-------------------------------------------------------------------------
INCLUDE_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 1 generate
begin
-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF
port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);
RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
-------------------------------------------------------------------------
-- BUFG for clock muxing
-------------------------------------------------------------------------
CLOCK_BUFG_TX: BUFG
port map (
O => phy_tx_clk_core, --[out]
I => PHY_tx_clk_ib --[in]
);
-------------------------------------------------------------------------
-- BUFG for clock muxing
-------------------------------------------------------------------------
CLOCK_BUFG_RX: BUFG
port map (
O => phy_rx_clk_core, --[out]
I => PHY_rx_clk_ib --[in]
);
end generate INCLUDE_BUFG_GEN;
-------------------------------------------------------------------------
-- NO_BUFG_GEN :- Dont include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 0
-------------------------------------------------------------------------
NO_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 0 generate
begin
phy_tx_clk_core <= PHY_tx_clk;
phy_rx_clk_core <= PHY_rx_clk;
end generate NO_BUFG_GEN;
-- Transmit and Receive clocks for core
phy_tx_clk_i <= phy_tx_clk_core;--not(phy_tx_clk_core);
phy_rx_clk_i <= phy_rx_clk_core;--not(phy_rx_clk_core);
-- TX/RX internal signals
phy_rx_data_i <= phy_rx_data_reg;
phy_rx_er_i <= phy_rx_er_reg;
phy_dv_i <= phy_dv_reg;
end generate NO_LOOPBACK_GEN;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_en in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_EN_O: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => PHY_tx_en_i,
prmry_ack => open,
scndry_out => PHY_tx_en_i_cdc,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_data_out in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_DATA_OUT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => '1',
prmry_ack => open,
scndry_out => open,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => phy_tx_data_i,
scndry_vect_out => phy_tx_data_i_cdc
);
----------------------------------------------------------------------------
-- Registering the Ethernet data signals
----------------------------------------------------------------------------
IOFFS_GEN: for i in 3 downto 0 generate
-- attribute IOB of RX_FF_I : label is "true";
-- attribute IOB of TX_FF_I : label is "true";
begin
RX_FF_I: FDRE
port map (
Q => phy_rx_data_reg(i), --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_rx_data(i), --[in]
R => bus_rst_rx_sync_core); --[in]
TX_FF_I: FDRE
port map (
Q => PHY_tx_data(i), --[out]
C => phy_tx_clk_core, --[in]
CE => '1', --[in]
D => phy_tx_data_i_cdc(i), --[in]
R => bus_rst_tx_sync_core); --[in]
end generate IOFFS_GEN;
----------------------------------------------------------------------------
-- Registering the Ethernet control signals
----------------------------------------------------------------------------
IOFFS_GEN2: if(true) generate
-- attribute IOB of DVD_FF : label is "true";
-- attribute IOB of RER_FF : label is "true";
-- attribute IOB of TEN_FF : label is "true";
begin
DVD_FF: FDRE
port map (
Q => phy_dv_reg, --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_dv, --[in]
R => bus_rst_rx_sync_core); --[in]
RER_FF: FDRE
port map (
Q => phy_rx_er_reg, --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_rx_er, --[in]
R => bus_rst_rx_sync_core); --[in]
TEN_FF: FDRE
port map (
Q => PHY_tx_en, --[out]
C => phy_tx_clk_core, --[in]
CE => '1', --[in]
D => PHY_tx_en_i_cdc, --[in]
R => bus_rst_tx_sync_core); --[in]
end generate IOFFS_GEN2;
----------------------------------------------------------------------------
-- XEMAC Module
----------------------------------------------------------------------------
XEMAC_I : entity axi_ethernetlite_v3_0.xemac
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ACLK_PERIOD_PS => C_S_AXI_ACLK_PERIOD_PS,
C_DUPLEX => C_DUPLEX,
C_RX_PING_PONG => C_RX_PING_PONG,
C_TX_PING_PONG => C_TX_PING_PONG,
C_INCLUDE_MDIO => C_INCLUDE_MDIO,
NODE_MAC => NODE_MAC
)
port map
(
Clk => S_AXI_ACLK,
Rst => bus_rst,
IP2INTC_Irpt => IP2INTC_Irpt,
-- Bus2IP Signals
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Bus2IP_Burst => bus2ip_burst,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
-- IP2Bus Signals
IP2Bus_Data => ip2bus_data,
IP2Bus_Error => ip2bus_errack,
-- EMAC Signals
PHY_tx_clk => phy_tx_clk_i,
PHY_rx_clk => phy_rx_clk_i,
PHY_crs => PHY_crs,
PHY_dv => phy_dv_i,
PHY_rx_data => phy_rx_data_i,
PHY_col => PHY_col,
PHY_rx_er => phy_rx_er_i,
PHY_tx_en => PHY_tx_en_i,
PHY_tx_data => PHY_tx_data_i,
PHY_MDIO_I => phy_mdio_i,
PHY_MDIO_O => phy_mdio_o,
PHY_MDIO_T => phy_mdio_t,
PHY_MDC => phy_mdc,
Loopback => Loopback
);
I_AXI_NATIVE_IPIF: entity axi_ethernetlite_v3_0.axi_interface
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWID => s_axi_awid,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data => ip2bus_data,
IP2Bus_Error => ip2bus_errack,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Bus2IP_Burst => bus2ip_burst,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
------------------------------------------------------------------------------------------
end imp;
| gpl-3.0 | 61f888ba4ca8b06c507aec617b6cef03 | 0.398424 | 4.201474 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/mem/bootrom_inferred.vhd | 2 | 2,310 | ----------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: [email protected]
-- DESCRIPTION: This file contains copy of the firmware image
------------------------------------------------------------------------------
-- WARNING:
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity BootRom_inferred is
generic (
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture rtl of BootRom_inferred is
constant ROM_ADDR_WIDTH : integer := 13;
constant ROM_LENGTH : integer := 2**(ROM_ADDR_WIDTH - log2(CFG_NASTI_DATA_BYTES));
type rom_block is array (0 to ROM_LENGTH-1) of std_logic_vector(31 downto 0);
type rom_type is array (0 to CFG_WORDS_ON_BUS-1) of rom_block;
type local_addr_arr is array (0 to CFG_WORDS_ON_BUS-1) of integer;
impure function init_rom(file_name : in string) return rom_type is
file rom_file : text open read_mode is file_name;
variable rom_line : line;
variable temp_bv : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable temp_mem : rom_type;
begin
for i in 0 to (ROM_LENGTH-1) loop
readline(rom_file, rom_line);
hread(rom_line, temp_bv);
for n in 0 to (CFG_WORDS_ON_BUS-1) loop
temp_mem(n)(i) := temp_bv((n+1)*32-1 downto 32*n);
end loop;
end loop;
return temp_mem;
end function;
constant rom : rom_type := init_rom(hex_filename);
begin
reg : process (clk)
variable t_adr : local_addr_arr;
begin
if rising_edge(clk) then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
t_adr(n) := conv_integer(address(n)(ROM_ADDR_WIDTH-1 downto log2(CFG_NASTI_DATA_BYTES)));
data(32*(n+1)-1 downto 32*n) <= rom(n)(t_adr(n));
end loop;
end if;
end process;
end;
| bsd-2-clause | 1bb7378bf0b513cb5e32c504c2d86d93 | 0.591775 | 3.397059 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/eth/greth_tx.vhd | 2 | 17,424 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
| bsd-2-clause | b8e00f07284da4f477162cc83eb1f344 | 0.516242 | 3.204119 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/PostProcessor.vhd | 2 | 20,769 | -------------------------------------------------------------------------------
--! @file PostProcessor.vhd
--! @brief Post-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! PISO used within this unit follows the following convention:
--! > Order at the PISO input (left to right) : A(0) A(1) A(2) … A(N-1)
--! > Order at the PISO output (time 0 to time N-1): A(0) A(1) A(2) … A(N-1)
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PostProcessor is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features activation
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_TAG_SIZE : integer := 128; --! Key
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic;
--! Header ports
cmd : in std_logic_vector(24 -1 downto 0);
cmd_valid : in std_logic;
cmd_ready : out std_logic;
--! CipherCore
bdo : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : in std_logic;
bdo_ready : out std_logic;
bdo_size : in std_logic_vector(G_LBS_BYTES+1-1 downto 0);
msg_auth_done : in std_logic;
msg_auth_valid : in std_logic
);
end PostProcessor;
architecture structure of PostProcessor is
constant IS_BUFFER : boolean := not (G_W = G_DBLK_SIZE);
constant WB : integer := G_W/8; --! Word bytes
constant LOG2_WB : integer := log2_ceil(WB);
constant CNT_DWORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W;
constant ZEROS : std_logic_vector(G_W -1 downto 0)
:= (others => '0');
--! =======================================================================
type t_lookup is array (0 to (WB-1))
of std_logic_vector(WB-1 downto 0);
function getVbytesLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
if (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : t_lookup := getVbytesLookup(G_W);
--! =======================================================================
--! Control
signal en_len : std_logic;
signal en_s : std_logic;
signal en_ctr : std_logic;
signal ld_tag : std_logic;
signal ld_stat : std_logic;
signal ld_ctr : std_logic;
signal ld_sgmt_info : std_logic;
signal ld_ciph_exp_len : std_logic;
signal sel_last : std_logic;
signal sel_do : std_logic;
signal set_first : std_logic;
signal clr_first : std_logic;
--! Status
signal is_decrypt : std_logic;
signal is_first : std_logic; --! is first block status
signal is_ciph_exp_len : std_logic; --! is ciph_exp len status
signal cpl_tag : std_logic; --! Completed tag header
signal cpl_stat : std_logic; --! Completed status header
signal sgmt_type : std_logic_vector(4 -1 downto 0);
signal sgmt_len : std_logic_vector(16 -1 downto 0);
signal sgmt_partial : std_logic;
signal sgmt_eot : std_logic;
signal sgmt_eoi : std_logic;
--! =======================================================================
--! Datapath'
--! Signals
signal word_size : std_logic_vector(LOG2_WB -1 downto 0);
signal vbytes : std_logic_vector(WB -1 downto 0);
signal out_word : std_logic_vector(G_W -1 downto 0);
signal out_hdr : std_logic_vector(G_W -1 downto 0);
signal is_eoi : std_logic;
--! Registers
signal msg_auth_done_r : std_logic;
signal msg_auth_valid_r : std_logic;
signal reg_bdo : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal reg_bdo_ready : std_logic;
signal reg_vbits : std_logic_vector(G_W -1 downto 0);
signal reg_vbytes : std_logic_vector(WB -1 downto 0);
signal ctr : std_logic_vector
(log2_ceil(CNT_DWORDS)-1 downto 0);
--! =======================================================================
--! aliases
--! Signal
signal cmd_instr_opcode : std_logic_vector(4 -1 downto 0);
signal cmd_sgmt_type : std_logic_vector(4 -1 downto 0);
signal cmd_sgmt_partial : std_logic;
signal cmd_sgmt_eot : std_logic;
signal cmd_sgmt_eoi : std_logic;
signal cmd_sgmt_len : std_logic_vector(16 -1 downto 0);
--! Global
signal cmd_rdy : std_logic;
signal do_vld : std_logic;
signal bdo_rdy : std_logic;
--! =======================================================================
type t_state is (S_WAIT_INSTR, S_WAIT_HDR, S_PREP,
S_OUT, S_GEN_TAG_HDR, S_GEN_STAT_HDR, S_WAIT_BDO, S_WAIT_BDO_CIPH);
signal cs : t_state; --! Current state
signal ns : t_state; --! Next state
begin
--! =======================================================================
--! Datapath registers and control status registers
--! =======================================================================
process(clk)
begin
if rising_edge(clk) then
if (cs = S_WAIT_INSTR) then
is_decrypt <= cmd_instr_opcode(0);
end if;
if (cs = S_WAIT_INSTR) then
cpl_tag <= '0';
elsif (ld_tag = '1') then
cpl_tag <= '1';
end if;
if (cs = S_WAIT_INSTR) then
cpl_stat <= '0';
elsif (ld_stat = '1') then
cpl_stat <= '1';
end if;
if (cs = S_WAIT_INSTR) then
msg_auth_done_r <= '0';
elsif (msg_auth_done = '1') then
msg_auth_done_r <= '1';
msg_auth_valid_r <= msg_auth_valid;
end if;
if (en_len = '1') then
if (unsigned(sgmt_len) < WB) then
reg_vbytes <= vbytes;
else
reg_vbytes <= (others => '1');
end if;
end if;
--! Keeping track of first data block (Only for special mode)
if (G_CIPH_EXP) then
if (ld_ciph_exp_len = '1') then
is_ciph_exp_len <= '1';
elsif (en_len = '1' or cs = S_WAIT_INSTR) then
is_ciph_exp_len <= '0';
end if;
if (G_REVERSE_CIPH) then
if (set_first = '1') then
is_first <= '1';
elsif (clr_first = '1') then
clr_first <= '0';
end if;
end if;
end if;
if (ld_sgmt_info = '1') then
sgmt_type(3 downto 2) <= cmd_sgmt_type(3 downto 2);
if (G_MERGE_TAG) then
sgmt_type(1 downto 0) <= not is_decrypt & '0';
else
sgmt_type(1 downto 0) <= '0' & not is_decrypt;
end if;
sgmt_partial <= cmd_sgmt_partial;
sgmt_len <= cmd_sgmt_len;
sgmt_eot <= cmd_sgmt_eot;
sgmt_eoi <= cmd_sgmt_eoi;
elsif (ld_tag = '1') then
sgmt_type <= ST_TAG;
sgmt_partial <= '0';
sgmt_eot <= '1';
sgmt_eoi <= '1';
sgmt_len <= std_logic_vector(
to_unsigned(G_TAG_SIZE/8, sgmt_len'length));
elsif (ld_stat = '1') then
sgmt_type <= STAT_SUCCESS(3 downto 1)
& (not msg_auth_valid_r and is_decrypt);
sgmt_partial <= '0';
sgmt_eot <= '0';
sgmt_eoi <= '0';
sgmt_len <= (others => '0');
elsif (en_len = '1') then
if (sel_last = '1') then
sgmt_len <= (others => '0');
else
sgmt_len <= std_logic_vector(unsigned(sgmt_len)-WB);
end if;
elsif (G_CIPH_EXP and ld_ciph_exp_len = '1') then
sgmt_len <= ZEROS(15 downto G_LBS_BYTES+1) & bdo_size;
end if;
if (ld_ctr = '1') then
ctr <= (others => '0');
elsif (en_ctr = '1') then
ctr <= std_logic_vector(unsigned(ctr)+1);
end if;
if (bdo_rdy = '1' and bdo_valid = '1') then
reg_bdo <= bdo;
elsif (en_ctr = '1') then
reg_bdo <= reg_bdo(G_DBLK_SIZE-G_W-1 downto 0)
& ZEROS(G_W-1 downto 0);
end if;
end if;
end process;
--! Combinational logic of datapath
gVbits:
for i in WB-1 downto 0 generate
reg_vbits(i*8+7 downto i*8) <= (others => reg_vbytes(i));
end generate;
word_size <= sgmt_len(LOG2_WB-1 downto 0);
vbytes <= VBYTES_LOOKUP(to_integer(unsigned(word_size)))
when sel_last = '1'
else (others => '1');
sel_last <= '1' when (unsigned(sgmt_len) < WB) else '0';
is_eoi <= '1' when (is_decrypt = '1'
and sgmt_type(3 downto 1) /= ST_NSEC
and sgmt_eot = '1')
or (is_decrypt = '0' and sgmt_type = ST_TAG)
else '0';
out_hdr(G_W-1 downto G_W-32) <= sgmt_type
& sgmt_partial & '0' & sgmt_eot & is_eoi
& x"00" & sgmt_len;
g_mt32:
if (G_W > 32) generate
out_hdr(G_W-33 downto 0) <= (others => '0');
end generate;
gBuffer: if (IS_BUFFER) generate
out_word <= reg_bdo(G_DBLK_SIZE-1 downto G_DBLK_SIZE-G_W) and reg_vbits;
end generate;
gNotBuffer: if (not IS_BUFFER) generate
out_word <= bdo and reg_vbits;
end generate;
do_data <= out_hdr when sel_do = '1' else out_word;
--! Output communication
cmd_ready <= cmd_rdy;
gOutBuffer:
if (IS_BUFFER) generate
bdo_ready <= reg_bdo_ready;
end generate;
gOutNotBuffer:
if (not IS_BUFFER) generate
bdo_ready <= bdo_rdy;
end generate;
do_valid <= do_vld;
--! Command FIFO dissection
cmd_instr_opcode <= cmd(24-1 downto 24-4);
cmd_sgmt_type <= cmd(24-1 downto 24-4);
gCiphExp:
if (G_CIPH_EXP) generate
cmd_sgmt_partial <= cmd(24-5);
end generate;
gNotCiphExp:
if (not G_CIPH_EXP) generate
is_ciph_exp_len <= '0';
ld_ciph_exp_len <= '0';
cmd_sgmt_partial <= '0';
end generate;
cmd_sgmt_eot <= cmd(24-7);
cmd_sgmt_eoi <= cmd(24-8);
cmd_sgmt_len <= cmd(24-9 downto 24-24);
--! =======================================================================
--! Control
--! =======================================================================
--! State transition
gNotAsync:
if (not G_ASYNC_RSTN) generate
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
cs <= S_WAIT_INSTR;
reg_bdo_ready <= '0';
else
if (en_s = '1') then
cs <= ns;
end if;
--! BDO ready register
if (en_s = '1'
and (ns = S_WAIT_BDO
or (G_CIPH_EXP and ns = S_WAIT_BDO_CIPH)))
then
reg_bdo_ready <= '1';
elsif (bdo_valid = '1' and reg_bdo_ready = '1') then
reg_bdo_ready <= '0';
end if;
end if;
end if;
end process;
end generate;
gAsync:
if (G_ASYNC_RSTN) generate
process(clk, rst)
begin
if (rst = '0') then
cs <= S_WAIT_INSTR;
reg_bdo_ready <= '0';
elsif rising_edge(clk) then
if (en_s = '1') then
cs <= ns;
end if;
--! BDO ready register
if (en_s = '1'
and (ns = S_WAIT_BDO
or (G_CIPH_EXP and ns = S_WAIT_BDO_CIPH)))
then
reg_bdo_ready <= '1';
elsif (bdo_valid = '1' and reg_bdo_ready = '1') then
reg_bdo_ready <= '0';
end if;
end if;
end process;
end generate;
--! Combinational logic
gPdiComb:
process(cs, cmd_instr_opcode,
cmd_sgmt_type, cmd_sgmt_eot, cmd_sgmt_eoi, cmd_sgmt_len,
is_decrypt, do_ready, bdo_valid,
cmd_valid, ctr, sgmt_len, sgmt_eoi, sgmt_eot,
is_first, is_ciph_exp_len,
cpl_tag, cpl_stat, msg_auth_done_r)
begin
ns <= cs;
cmd_rdy <= '0';
bdo_rdy <= '0';
do_vld <= '0';
en_ctr <= '0';
en_len <= '0';
en_s <= '0';
ld_ctr <= '0';
ld_sgmt_info <= '0';
ld_stat <= '0';
ld_tag <= '0';
sel_do <= '0';
if (G_CIPH_EXP) then
ld_ciph_exp_len <= '0';
if (G_REVERSE_CIPH) then
clr_first <= '1';
end if;
end if;
case cs is
when S_WAIT_INSTR =>
ns <= S_WAIT_HDR;
cmd_rdy <= '1';
if (cmd_valid = '1'
and cmd_instr_opcode(3 downto 1) = OP_ENCDEC)
then
en_s <= '1';
end if;
if (G_CIPH_EXP and G_REVERSE_CIPH) then
set_first <= '1';
end if;
when S_WAIT_HDR =>
ld_sgmt_info <= '1';
cmd_rdy <= '1';
if (G_CIPH_EXP) then
if (cmd_sgmt_type(3 downto 2) = ST_D
and ((G_REVERSE_CIPH and is_first = '1')
or (cmd_sgmt_eot = '1')))
then
ns <= S_WAIT_BDO_CIPH;
if (G_REVERSE_CIPH) then
clr_first <= '1';
end if;
else
ns <= S_PREP;
end if;
else
ns <= S_PREP;
end if;
if (cmd_valid = '1') then
en_s <= '1';
end if;
--! Prepare appropriate flags and generate output header/status
when S_PREP =>
do_vld <= '1';
if (do_ready = '1') then
if (cpl_stat = '1') then
ns <= S_WAIT_INSTR;
else
if (unsigned(sgmt_len) > 0)
or G_MERGE_TAG
then
if (not IS_BUFFER) then
ns <= S_OUT;
else
if (G_CIPH_EXP and is_ciph_exp_len = '1') then
ns <= S_OUT;
else
ns <= S_WAIT_BDO;
end if;
end if;
else
if (sgmt_eot = '1'
and sgmt_type(3 downto 2) = ST_D)
then
if (is_decrypt = '0') then
ns <= S_GEN_TAG_HDR;
else
ns <= S_GEN_STAT_HDR;
end if;
end if;
end if;
end if;
en_s <= '1';
en_len <= '1';
end if;
sel_do <= '1';
--! Output data
when S_OUT =>
if (not IS_BUFFER) then
bdo_rdy <= '1';
if (do_ready = '1' and bdo_valid = '1') then
do_vld <= '1';
en_len <= '1';
en_s <= '1';
end if;
else
do_vld <= '1';
if (do_ready = '1') then
en_len <= '1';
en_ctr <= '1';
en_s <= '1';
end if;
end if;
if (unsigned(sgmt_len) = 0) then
if (sgmt_eot = '1') then
if (is_decrypt = '0' and cpl_tag = '0') then
ns <= S_GEN_TAG_HDR;
else
ns <= S_GEN_STAT_HDR;
end if;
else
ns <= S_WAIT_HDR;
end if;
elsif (G_W /= G_DBLK_SIZE
and unsigned(ctr) = CNT_DWORDS-1)
then
ns <= S_WAIT_BDO;
end if;
when S_GEN_TAG_HDR =>
ld_tag <= '1';
ns <= S_PREP;
en_s <= '1';
when S_GEN_STAT_HDR =>
ld_stat <= '1';
ns <= S_PREP;
if (is_decrypt = '0' or msg_auth_done_r = '1') then
en_s <= '1';
end if;
when S_WAIT_BDO =>
ns <= S_OUT;
bdo_rdy <= '1';
ld_ctr <= '1';
if (bdo_valid = '1') then
en_s <= '1';
end if;
when S_WAIT_BDO_CIPH =>
ns <= S_PREP;
ld_ciph_exp_len <= '1';
bdo_rdy <= '1';
ld_ctr <= '1';
if (bdo_valid = '1') then
en_s <= '1';
end if;
end case;
end process;
end structure;
| apache-2.0 | 6685778085d981f76d82685db4e18372 | 0.397669 | 4.07318 | false | false | false | false |
hoangt/PoC | src/comm/remote/remote_terminal_control.vhdl | 2 | 19,045 | -- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: Simple terminal interface to monitor and manipulate
-- basic IO components such as buttons, slide switches, LED
-- and hexadecimal displays.
--
-- A typical transport would be a UART connection using a terminal application.
-- A command line starts with a single letter identifying the addressed
-- resource type:
--
-- R .. Reset - strobed input to the design
-- P .. Pulse - strobed input to the design
-- S .. Switch - stateful input to the design
-- L .. Light - (bit) output from the design
-- D .. Digit - (hex) output from the design
--
-- This letter may be followed by a hexadecimal input vector, which triggers
--
-- R - a strobe on the corresponding inputs,
-- P - a strobe on the corresponding inputs, and
-- S - a state toggle of the corresponding inputs.
--
-- The input vector is ignored for outputs from the design.
-- The command line may contain an arbitrary amount of spaces.
--
-- The terminal interface will echo with:
--
-- <resource character>[<bit count>'<hex output vector>]
--
-- The <bit count> and <hex output vector> will only be present if, at least,
-- a single instance of the addressed resource type is available.
-- In particular, the resource characters of lines starting with other than
-- the listed resource types will simply be echoed.
-- The <bit count> describes how many bits of the addressed resource are
-- available, which may be used to explore the resources using a command line
-- with no or a zero input argument. The <bit count> is typically provided in
-- decimal (default) but may be changed to hexadecimal through the generic
-- parameter COUNT_DECIMAL.
-- The <hex output vector> acknowledges the input (R and P) and informs about
-- the current state (S, L and D).
--
-- Example:
-- > L
-- L10'21D
-- > D
-- D8'5E
-- > A
-- A
-- > S
-- S6'00
-- > S3A
-- S6'3A
-- > S 1
-- S6'3B
-- > P8
-- P4'8
-- > P
-- P4'0
-- Authors: Thomas B. Preußer <[email protected]>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library poc;
use poc.functions.all;
entity remote_terminal_control is
generic (
RESET_COUNT : natural;
PULSE_COUNT : natural;
SWITCH_COUNT : natural;
LIGHT_COUNT : natural;
DIGIT_COUNT : natural;
COUNT_DECIMAL : boolean := true
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- UART Connectivity
idat : in std_logic_vector(6 downto 0);
istb : in std_logic;
odat : out std_logic_vector(6 downto 0);
ordy : in std_logic;
oput : out std_logic;
-- Control Outputs
resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0);
pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0);
switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0);
-- Monitor Inputs
lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0);
digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0)
);
end remote_terminal_control;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of remote_terminal_control is
type tKind is (KIND_NONE,
KIND_RESET, KIND_PULSE, KIND_SWITCH,
KIND_LIGHT, KIND_DIGIT);
--constant KIND_NONE : natural := 0;
--constant KIND_RESET : natural := 1;
--constant KIND_PULSE : natural := 2;
--constant KIND_SWITCH : natural := 3;
--constant KIND_LIGHT : natural := 4;
--constant KIND_DIGIT : natural := 5;
--subtype tKind is natural range KIND_NONE to KIND_DIGIT;
subtype tActual is tKind range KIND_RESET to KIND_DIGIT;
subtype tInput is tActual range KIND_RESET to KIND_SWITCH;
subtype tOutput is tActual range KIND_LIGHT to KIND_DIGIT;
-----------------------------------------------------------------------------
-- Counts
type tCounts is array(tKind range<>) of natural;
constant COUNTS : tCounts := (0,
RESET_COUNT, PULSE_COUNT, SWITCH_COUNT,
LIGHT_COUNT, 4*DIGIT_COUNT);
function max_count(arr : tCounts) return natural is
-- Without this copy of arr, ISE (as of version 14.7) will choke.
variable a : tCounts(arr'range) := (others => 0);
variable res : natural;
begin
a(arr'range) := arr;
res := 0;
for i in a'range loop
if a(i) > res then
res := a(i);
end if;
end loop;
return res;
end max_count;
constant PAR_BITS : natural := max_count(COUNTS(tInput));
constant RES_BITS : natural := max_count(COUNTS(tActual));
constant ECO_BITS : natural := 4*((RES_BITS+3)/4);
function log10ceil(x : natural) return positive is
variable scale, res : positive;
begin
scale := 10;
res := 1;
while x >= scale loop
scale := 10*scale;
res := res+1;
end loop;
return res;
end log10ceil;
function makeCntBits return positive is
begin
if COUNT_DECIMAL then
return 4*log10ceil(RES_BITS);
end if;
return log2ceil(RES_BITS);
end makeCntBits;
constant CNT_BITS : positive := makeCntBits;
subtype tOutCount is unsigned(CNT_BITS-1 downto 0);
type tOutCounts is array(tKind range<>) of tOutCount;
function makeOutCounts return tOutCounts is
variable res : tOutCounts(COUNTS'range);
variable ele : tOutCount;
variable rmd : natural;
begin
for i in COUNTS'range loop
if COUNT_DECIMAL then
rmd := COUNTS(i);
for j in 0 to ele'length/4-1 loop
ele(4*j+3 downto 4*j) := to_unsigned(rmd mod 10, 4);
rmd := rmd/10;
end loop;
else
ele := to_unsigned(COUNTS(i), CNT_BITS);
end if;
res(i) := ele;
end loop;
return res;
end;
constant OUT_COUNTS : tOutCounts(COUNTS'range) := makeOutCounts;
subtype tCode is std_logic_vector(4 downto 0);
type tCodes is array(tKind range<>) of tCode;
constant CODES : tCodes(tActual) := ("10010", "10000", "10011", "01100", "00100");
type tStrobes is array(tKind range<>) of boolean;
constant STROBES : tStrobes(tInput) := (true, true, false);
signal BufVld : std_logic := '0';
signal BufCmd : std_logic_vector(4 downto 0) := (others => '-');
signal BufCnt : unsigned(CNT_BITS-1 downto 0) := (others => '-');
signal BufEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal BufAck : std_logic;
begin
-- Reading the UART input stream
blkReader: block
type tState is (Idle, Command);
signal State : tState := Idle;
signal NextState : tState;
signal Cmd : std_logic_vector(4 downto 0) := (others => '-');
signal Arg : std_logic_vector(PAR_BITS-1 downto 0) := (others => '-');
signal Sel : tKind := KIND_NONE;
signal Load : std_logic;
signal Shift : std_logic;
signal Commit : std_logic;
subtype tEcho is std_logic_vector(0 to ECO_BITS-1);
type tEchos is array(tKind range<>) of tEcho;
signal echos : tEchos(tKind);
function leftAlignedBCD(x : std_logic_vector) return tEcho is
constant MY_BITS : positive := 4*((x'length+3)/4);
variable res : tEcho;
begin
res := (others => '-');
res(0 to 3) := x"0";
res(MY_BITS-x'length to MY_BITS-1) := x;
return res;
end leftAlignedBCD;
begin
-- State Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
Cmd <= (others => '-');
Arg <= (others => '-');
else
State <= NextState;
if Load = '1' then
Cmd <= idat(4 downto 0);
Arg <= (others => '0');
Sel <= KIND_NONE;
for i in CODES'range loop
if CODES(i) = idat(4 downto 0) then
Sel <= i;
end if;
end loop;
elsif Shift = '1' then
Arg <= Arg(Arg'left-4 downto 0) &
std_logic_vector(unsigned(idat(3 downto 0)) + (idat(6)&"00"&idat(6)));
end if;
end if;
end if;
end process;
-- Common Reader State Machine
process(State, istb, idat)
begin
NextState <= State;
Load <= '0';
Shift <= '0';
Commit <= '0';
if istb = '1' then
case State is
when Idle =>
if idat(6) = '1' then
Load <= '1';
NextState <= Command;
end if;
when Command =>
if idat(6) = '1' or (idat(5) = '1' and idat(4) = '1') then
Shift <= '1';
elsif idat(6) = '0' and idat(5) = '0' and idat(4) = '0' then
Commit <= '1';
NextState <= Idle;
end if;
end case;
end if;
end process;
echos(KIND_NONE) <= (others => '-');
-- Generate Control Inputs
genInputs: for i in tInput generate
-- Control not used
genNone: if COUNTS(i) = 0 generate
genReset: if i = KIND_RESET generate
resets <= "X";
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= "X";
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= "X";
end generate genSwitch;
echos(i) <= (others => '-');
end generate genNone;
-- Controls available
genAvail: if COUNTS(i) > 0 generate
signal Outputs : std_logic_vector(COUNTS(i)-1 downto 0) := (others => '0');
signal onxt : std_logic_vector(Outputs'range);
begin
-- Output Computation: Strobed
genStrobed: if STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Outputs <= (others => '0');
else
if Commit = '1' and Sel = i then
Outputs <= onxt;
else
Outputs <= (others => '0');
end if;
end if;
end if;
end process;
onxt <= Arg(Outputs'range);
end generate genStrobed;
-- Output Computation: State
genState: if not STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if Commit = '1' and Sel = i then
Outputs <= onxt;
end if;
end if;
end process;
onxt <= Outputs xor Arg(Outputs'range);
end generate genState;
echos(i) <= leftAlignedBCD(onxt);
-- Assign to Output Pins
genReset: if i = KIND_RESET generate
resets <= Outputs;
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= Outputs;
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= Outputs;
end generate genSwitch;
end generate genAvail;
end generate genInputs;
process(lights, digits)
begin
echos(KIND_LIGHT) <= (others => '-');
echos(KIND_DIGIT) <= (others => '-');
if LIGHT_COUNT > 0 then
echos(KIND_LIGHT) <= leftAlignedBCD(lights);
end if;
if DIGIT_COUNT > 0 then
echos(KIND_DIGIT) <= leftAlignedBCD(digits);
end if;
end process;
-- Build Data Record for Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
else
if Commit = '1' then
BufVld <= '1';
BufCmd <= Cmd;
BufCnt <= OUT_COUNTS(Sel);
BufEco <= echos(Sel);
elsif BufAck = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
end if;
end if;
end if;
end process;
end block blkReader;
blkWrite: block
type tState is (Idle, OutCommand, OutCount, OutTick, OutEcho, OutEOL);
signal State : tState := Idle;
signal NextState : tState;
signal OutCmd : std_logic_vector(4 downto 0) := (others => '-');
signal OutCnt : unsigned(4*((BufCnt'length+3)/4)-1 downto 0) := (others => '-');
signal OutEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal Locked : std_logic := '-';
signal NextLocked : std_logic;
signal OutCntDone : std_logic;
signal OutCntDecr : unsigned(2 downto 0);
signal NextOutCnt : unsigned(OutCnt'length downto 0);
signal ShiftCnt : std_logic;
signal ShiftEco : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
OutCmd <= (others => '-');
OutCnt <= (others => '-');
OutEco <= (others => '-');
Locked <= '-';
else
State <= NextState;
if BufAck = '1' then
OutCmd <= BufCmd;
OutCnt <= (others => '0');
OutCnt(BufCnt'length-1 downto 0) <= unsigned(BufCnt);
OutEco <= BufEco;
Locked <= '0';
else
-- OutCnt Register
if OutCnt'length > 4 and ShiftCnt = '1' then
OutCnt <= OutCnt(OutCnt'left-4 downto 0) & OutCnt(OutCnt'left downto OutCnt'left-3);
else
OutCnt <= NextOutCnt(OutCnt'range);
end if;
Locked <= NextLocked;
-- OutEco Register
if ShiftEco = '1' then
OutEco <= OutEco(4 to OutEco'right) & "----";
end if;
end if;
end if;
end if;
end process;
NextLocked <= 'X' when Is_x(std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3))) else
'1' when OutCnt(OutCnt'left downto OutCnt'left-3) /= x"0" else
Locked;
genSingleDig: if OutCnt'length = 4 generate
OutCntDone <= '1';
end generate;
genMultiDig: if OutCnt'length > 4 generate
signal Cnt : unsigned(log2ceil(OutCnt'length/4)-1 downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if BufAck = '1' then
Cnt <= (others => '0');
elsif ShiftCnt = '1' then
Cnt <= Cnt + 1;
end if;
end if;
end if;
end process;
OutCntDone <= 'X' when Is_X(std_logic_vector(Cnt)) else
'1' when (Cnt or not to_unsigned(OutCnt'length/4-1, Cnt'length)) = (Cnt'range => '1') else
'0';
end generate;
genDec: if COUNT_DECIMAL generate
process(OutCnt, OutCntDecr)
variable sub : unsigned(2 downto 0);
variable d : unsigned(4 downto 0);
begin
sub := OutCntDecr;
for i in 0 to OutCnt'length/4-1 loop
d := ('0'&OutCnt(4*i+3 downto 4*i)) - sub;
if d(4) = '0' then
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0);
sub := to_unsigned(0, sub'length);
else
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0) - 6;
sub := to_unsigned(1, sub'length);
end if;
end loop;
NextOutCnt(OutCnt'length) <= sub(0);
end process;
end generate genDec;
genHex: if not COUNT_DECIMAL generate
NextOutCnt <= ('0'&OutCnt) - OutCntDecr;
end generate genHex;
process(State, ordy, BufVld, OutCmd, OutCnt, OutEco, OutCntDone, NextLocked, NextOutCnt)
begin
NextState <= State;
BufAck <= '0';
ShiftCnt <= '0';
ShiftEco <= '0';
OutCntDecr <= (others => '0');
odat <= (others => '-');
oput <= '0';
case State is
when Idle =>
if BufVld = '1' then
BufAck <= '1';
NextState <= OutCommand;
end if;
when OutCommand =>
odat <= "10" & OutCmd;
oput <= '1';
if ordy = '1' then
NextState <= OutCount;
end if;
when OutCount =>
if COUNT_DECIMAL or OutCnt(OutCnt'left downto OutCnt'left-3) < 10 then
odat <= "011" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3));
else
odat <= "100" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)+7);
end if;
oput <= NextLocked;
if ordy = '1' then
ShiftCnt <= '1';
if OutCntDone = '1' then
if NextLocked = '1' then
NextState <= OutTick;
else
NextState <= OutEOL;
end if;
end if;
end if;
when OutTick =>
odat <= "0100111";
oput <= '1';
if ordy = '1' then
OutCntDecr <= to_unsigned(1, OutCntDecr'length);
NextState <= OutEcho;
end if;
when OutEcho =>
if unsigned(OutEco(0 to 3)) < 10 then
odat <= "011" & OutEco(0 to 3);
else
odat <= "100" & std_logic_vector(unsigned(OutEco(0 to 3))+7);
end if;
oput <= '1';
if ordy = '1' then
ShiftEco <= '1';
OutCntDecr <= "100";
if NextOutCnt(OutCnt'length) = '1' then
NextState <= OutEOL;
end if;
end if;
when OutEOL =>
odat <= "0001010";
oput <= '1';
if ordy = '1' then
NextState <= Idle;
end if;
end case;
end process;
end block blkWrite;
end rtl;
| apache-2.0 | bd77d10f3d81b700247a4907c20e11b1 | 0.532952 | 3.929633 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/rocket_l1only.vhd | 2 | 10,538 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief RockeTile top level.
--! @details RISC-V "RocketTile" without Uncore subsystem.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! TileLink interface description.
use rocketlib.types_rocket.all;
library work;
use work.all;
--! @brief RocketTile entity declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
entity rocket_l1only is
generic (
--! Cached Tile AXI master index
xindex1 : integer := 0;
--! Uncached Tile AXI master index
xindex2 : integer := 1
);
port (
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
--! @}
end;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_l1only of rocket_l1only is
constant xmstconfig1 : nasti_master_config_type := (
xindex => xindex1,
vid => VENDOR_GNSSSENSOR,
did => RISCV_CACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xindex2,
vid => VENDOR_GNSSSENSOR,
did => RISCV_UNCACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
signal nrst : std_logic;
signal cpu_rst : std_logic;
signal cto : tile_cached_out_type;
signal cti : tile_cached_in_type;
signal uto : tile_cached_out_type;
signal uti : tile_cached_in_type;
component AxiBridge is generic (
xindex : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_cached_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_cached_in_type
);
end component;
COMPONENT RocketTile
PORT(
clk : IN std_logic;
reset : IN std_logic;
io_cached_0_acquire_ready : IN std_logic;
io_cached_0_grant_valid : IN std_logic;
io_cached_0_grant_bits_addr_beat : IN std_logic_vector(1 downto 0);
io_cached_0_grant_bits_client_xact_id : IN std_logic_vector(1 downto 0);
io_cached_0_grant_bits_manager_xact_id : IN std_logic_vector(3 downto 0);
io_cached_0_grant_bits_is_builtin_type : IN std_logic;
io_cached_0_grant_bits_g_type : IN std_logic_vector(3 downto 0);
io_cached_0_grant_bits_data : IN std_logic_vector(127 downto 0);
io_cached_0_probe_valid : IN std_logic;
io_cached_0_probe_bits_addr_block : IN std_logic_vector(25 downto 0);
io_cached_0_probe_bits_p_type : IN std_logic_vector(1 downto 0);
io_cached_0_release_ready : IN std_logic;
io_uncached_0_acquire_ready : IN std_logic;
io_uncached_0_grant_valid : IN std_logic;
io_uncached_0_grant_bits_addr_beat : IN std_logic_vector(1 downto 0);
io_uncached_0_grant_bits_client_xact_id : IN std_logic_vector(1 downto 0);
io_uncached_0_grant_bits_manager_xact_id : IN std_logic_vector(3 downto 0);
io_uncached_0_grant_bits_is_builtin_type : IN std_logic;
io_uncached_0_grant_bits_g_type : IN std_logic_vector(3 downto 0);
io_uncached_0_grant_bits_data : IN std_logic_vector(127 downto 0);
io_host_reset : IN std_logic;
io_host_id : IN std_logic;
io_host_csr_req_valid : IN std_logic;
io_host_csr_req_bits_rw : IN std_logic;
io_host_csr_req_bits_addr : IN std_logic_vector(11 downto 0);
io_host_csr_req_bits_data : IN std_logic_vector(63 downto 0);
io_host_csr_resp_ready : IN std_logic;
io_cached_0_acquire_valid : OUT std_logic;
io_cached_0_acquire_bits_addr_block : OUT std_logic_vector(25 downto 0);
io_cached_0_acquire_bits_client_xact_id : OUT std_logic_vector(1 downto 0);
io_cached_0_acquire_bits_addr_beat : OUT std_logic_vector(1 downto 0);
io_cached_0_acquire_bits_is_builtin_type : OUT std_logic;
io_cached_0_acquire_bits_a_type : OUT std_logic_vector(2 downto 0);
io_cached_0_acquire_bits_union : OUT std_logic_vector(16 downto 0);
io_cached_0_acquire_bits_data : OUT std_logic_vector(127 downto 0);
io_cached_0_grant_ready : OUT std_logic;
io_cached_0_probe_ready : OUT std_logic;
io_cached_0_release_valid : OUT std_logic;
io_cached_0_release_bits_addr_beat : OUT std_logic_vector(1 downto 0);
io_cached_0_release_bits_addr_block : OUT std_logic_vector(25 downto 0);
io_cached_0_release_bits_client_xact_id : OUT std_logic_vector(1 downto 0);
io_cached_0_release_bits_voluntary : OUT std_logic;
io_cached_0_release_bits_r_type : OUT std_logic_vector(2 downto 0);
io_cached_0_release_bits_data : OUT std_logic_vector(127 downto 0);
io_uncached_0_acquire_valid : OUT std_logic;
io_uncached_0_acquire_bits_addr_block : OUT std_logic_vector(25 downto 0);
io_uncached_0_acquire_bits_client_xact_id : OUT std_logic_vector(1 downto 0);
io_uncached_0_acquire_bits_addr_beat : OUT std_logic_vector(1 downto 0);
io_uncached_0_acquire_bits_is_builtin_type : OUT std_logic;
io_uncached_0_acquire_bits_a_type : OUT std_logic_vector(2 downto 0);
io_uncached_0_acquire_bits_union : OUT std_logic_vector(16 downto 0);
io_uncached_0_acquire_bits_data : OUT std_logic_vector(127 downto 0);
io_uncached_0_grant_ready : OUT std_logic;
io_host_csr_req_ready : OUT std_logic;
io_host_csr_resp_valid : OUT std_logic;
io_host_csr_resp_bits : OUT std_logic_vector(63 downto 0);
io_host_debug_stats_csr : OUT std_logic
);
END COMPONENT;
begin
mstcfg1 <= xmstconfig1;
mstcfg2 <= xmstconfig2;
nrst <= not rst;
cpu_rst <= rst or soft_rst;
inst_tile: RocketTile PORT MAP(
clk => clk_sys,
reset => cpu_rst,
io_cached_0_acquire_ready => cti.acquire_ready,
io_cached_0_acquire_valid => cto.acquire_valid,
io_cached_0_acquire_bits_addr_block => cto.acquire_bits_addr_block,
io_cached_0_acquire_bits_client_xact_id => cto.acquire_bits_client_xact_id,
io_cached_0_acquire_bits_addr_beat => cto.acquire_bits_addr_beat,
io_cached_0_acquire_bits_is_builtin_type => cto.acquire_bits_is_builtin_type,
io_cached_0_acquire_bits_a_type => cto.acquire_bits_a_type,
io_cached_0_acquire_bits_union => cto.acquire_bits_union,
io_cached_0_acquire_bits_data => cto.acquire_bits_data,
io_cached_0_grant_ready => cto.grant_ready,
io_cached_0_grant_valid => cti.grant_valid,
io_cached_0_grant_bits_addr_beat => cti.grant_bits_addr_beat,
io_cached_0_grant_bits_client_xact_id => cti.grant_bits_client_xact_id,
io_cached_0_grant_bits_manager_xact_id => cti.grant_bits_manager_xact_id,
io_cached_0_grant_bits_is_builtin_type => cti.grant_bits_is_builtin_type,
io_cached_0_grant_bits_g_type => cti.grant_bits_g_type,
io_cached_0_grant_bits_data => cti.grant_bits_data,
io_cached_0_probe_ready => cto.probe_ready,
io_cached_0_probe_valid => cti.probe_valid,
io_cached_0_probe_bits_addr_block => cti.probe_bits_addr_block,
io_cached_0_probe_bits_p_type => cti.probe_bits_p_type,
io_cached_0_release_ready => cti.release_ready,
io_cached_0_release_valid => cto.release_valid,
io_cached_0_release_bits_addr_beat => cto.release_bits_addr_beat,
io_cached_0_release_bits_addr_block => cto.release_bits_addr_block,
io_cached_0_release_bits_client_xact_id => cto.release_bits_client_xact_id,
io_cached_0_release_bits_voluntary => cto.release_bits_voluntary,
io_cached_0_release_bits_r_type => cto.release_bits_r_type,
io_cached_0_release_bits_data => cto.release_bits_data,
io_uncached_0_acquire_ready => uti.acquire_ready,
io_uncached_0_acquire_valid => uto.acquire_valid,
io_uncached_0_acquire_bits_addr_block => uto.acquire_bits_addr_block,
io_uncached_0_acquire_bits_client_xact_id => uto.acquire_bits_client_xact_id,
io_uncached_0_acquire_bits_addr_beat => uto.acquire_bits_addr_beat,
io_uncached_0_acquire_bits_is_builtin_type => uto.acquire_bits_is_builtin_type,
io_uncached_0_acquire_bits_a_type => uto.acquire_bits_a_type,
io_uncached_0_acquire_bits_union => uto.acquire_bits_union,
io_uncached_0_acquire_bits_data => uto.acquire_bits_data,
io_uncached_0_grant_ready => uto.grant_ready,
io_uncached_0_grant_valid => uti.grant_valid,
io_uncached_0_grant_bits_addr_beat => uti.grant_bits_addr_beat,
io_uncached_0_grant_bits_client_xact_id => uti.grant_bits_client_xact_id,
io_uncached_0_grant_bits_manager_xact_id => uti.grant_bits_manager_xact_id,
io_uncached_0_grant_bits_is_builtin_type => uti.grant_bits_is_builtin_type,
io_uncached_0_grant_bits_g_type => uti.grant_bits_g_type,
io_uncached_0_grant_bits_data => uti.grant_bits_data,
io_host_reset => htifoi.reset,
io_host_id => htifoi.id,
io_host_csr_req_ready => htifio.csr_req_ready,
io_host_csr_req_valid => htifoi.csr_req_valid,
io_host_csr_req_bits_rw => htifoi.csr_req_bits_rw,
io_host_csr_req_bits_addr => htifoi.csr_req_bits_addr,
io_host_csr_req_bits_data => htifoi.csr_req_bits_data,
io_host_csr_resp_ready => htifoi.csr_resp_ready,
io_host_csr_resp_valid => htifio.csr_resp_valid,
io_host_csr_resp_bits => htifio.csr_resp_bits,
io_host_debug_stats_csr => htifio.debug_stats_csr
);
cbridge0 : AxiBridge
generic map (
xindex => xindex1
) port map (
clk => clk_sys,
nrst => nrst,
--! Tile-to-AXI direction
tloi => cto,
msto => msto1,
--! AXI-to-Tile direction
msti => msti,
tlio => cti
);
ubridge0 : AxiBridge
generic map (
xindex => xindex2
) port map (
clk => clk_sys,
nrst => nrst,
--! Tile-to-AXI direction
tloi => uto,
msto => msto2,
--! AXI-to-Tile direction
msti => msti,
tlio => uti
);
end arch_rocket_l1only;
| bsd-2-clause | 8fb06495b5a0af716108b9d6af15489e | 0.682957 | 2.895055 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/ram16x4.vhd | 4 | 12,011 | -------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
| gpl-3.0 | 22f422e3177054838c5b4d751a02c807 | 0.408625 | 4.829513 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/AEAD_pkg.vhd | 1 | 4,852 | -------------------------------------------------------------------------------
--! @file AEAD_pkg.vhd
--! @brief Package used for authenticated encyryption
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package AEAD_pkg is
--! =======================================================================
--! BDI Type Encoding for CipherCore (based on SegmentType(3 downto 1))
constant BDI_TYPE_ASS : std_logic_vector(3 -1 downto 1) := "00";
constant BDI_TYPE_ASS0 : std_logic_vector(3 -1 downto 0) := "000";
constant BDI_TYPE_ASS1 : std_logic_vector(3 -1 downto 0) := "001";
constant BDI_TYPE_DAT : std_logic_vector(3 -1 downto 1) := "01";
constant BDI_TYPE_DAT0 : std_logic_vector(3 -1 downto 0) := "010";
constant BDI_TYPE_DAT1 : std_logic_vector(3 -1 downto 0) := "011";
constant BDI_TYPE_TAG : std_logic_vector(3 -1 downto 0) := "100";
constant BDI_TYPE_LEN : std_logic_vector(3 -1 downto 0) := "101";
constant BDI_TYPE_NPUB : std_logic_vector(3 -1 downto 0) := "110";
constant BDI_TYPE_NSEC : std_logic_vector(3 -1 downto 0) := "111";
--! =======================================================================
--! Opcode (used by Pre- and Post-Processors)
constant OP_ENCDEC : std_logic_vector(3 -1 downto 0) := "001";
constant OP_ENC : std_logic_vector(4 -1 downto 0) := "0010";
constant OP_DEC : std_logic_vector(4 -1 downto 0) := "0011";
constant OP_LDKEY : std_logic_vector(4 -1 downto 0) := "0100";
constant OP_ACTKEY : std_logic_vector(4 -1 downto 0) := "0111";
--! =======================================================================
--! Status (used by Pre- and Post-Processors)
constant STAT_SUCCESS : std_logic_vector(4 -1 downto 0) := "1110";
constant STAT_FAILURE : std_logic_vector(4 -1 downto 0) := "1111";
--! =======================================================================
--! Segment Type Encoding (used by Pre- and Post-Processors)
--! 00XX
constant ST_A : std_logic_vector(2 -1 downto 0) := "00";
constant ST_AD : std_logic_vector(4 -1 downto 0) := "0001";
constant ST_NPUB_AD : std_logic_vector(4 -1 downto 0) := "0010";
constant ST_AD_NPUB : std_logic_vector(4 -1 downto 0) := "0011";
--! 01XX
constant ST_D : std_logic_vector(2 -1 downto 0) := "01";
constant ST_PT : std_logic_vector(4 -1 downto 0) := "0100";
constant ST_CT : std_logic_vector(4 -1 downto 0) := "0101";
constant ST_CT_TAG : std_logic_vector(4 -1 downto 0) := "0110";
--! 10XX
constant ST_TAG : std_logic_vector(4 -1 downto 0) := "1000";
constant ST_LEN : std_logic_vector(4 -1 downto 0) := "1010";
--! 11XX
constant ST_KEY : std_logic_vector(4 -1 downto 0) := "1100";
constant ST_NPUB : std_logic_vector(4 -1 downto 0) := "1101";
constant ST_NSEC : std_logic_vector(3 -1 downto 0) := "111";
constant ST_NSEC_PT : std_logic_vector(4 -1 downto 0) := "1110";
constant ST_NSEC_CT : std_logic_vector(4 -1 downto 0) := "1111";
--! =======================================================================
--! Maximum supported length
constant SINGLE_PASS_MAX : integer := 32;
constant TWO_PASS_MAX : integer := 11;
--! =======================================================================
--! Functions
function log2_ceil (N: natural) return natural; --! Log(2) ceil
end AEAD_pkg;
package body AEAD_pkg is
--! Log of base 2
function log2_ceil (N: natural) return natural is
begin
if ( N = 0 ) then
return 0;
elsif N <= 2 then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
end package body AEAD_pkg;
| apache-2.0 | 40e7242721e985a52bf2b70968c5bd78 | 0.506186 | 3.765528 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sources_1/new/topmodule.vhd | 1 | 3,822 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.12.2015 15:39:44
-- Design Name:
-- Module Name: topmodule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity topmodule is
Port (
clk : IN STD_LOGIC;
JA0 : INOUT STD_LOGIC;
JA1 : INOUT STD_LOGIC;
JA2 : OUT STD_LOGIC;
JA3 : OUT STD_LOGIC;
--RsRx : IN STD_LOGIC;
RsTx : OUT STD_LOGIC;
--RsCts :
--RsRts :
btnCpuReset : IN STD_LOGIC
);
end topmodule;
architecture Behavioral of topmodule is
-- internal reset
signal resetin, reset, reset_n: std_logic;
-- serial to serialLoader signals
signal txd, ready, send: std_logic;
signal serialData: std_logic_vector (7 downto 0);
-- FIFO Signals serial loader to FIFO signals
signal FIFO_Empty, FIFO_Full, FIFO_ReadEn, FIFO_WriteEn: std_logic;
signal FIFO_DataOut, FIFO_DataIn: std_logic_vector (7 downto 0);
-- i2c internal signals
signal sda,scl :std_logic;
-- i2c control signal
signal ena,rw,busy,ack_error : std_logic;
signal addr : std_logic_vector (6 downto 0);
signal data_rd : std_logic_vector (7 downto 0);
signal data_wr : std_logic_vector (7 downto 0):= "00000000";
begin
--wire up the global reset
resetDebounce_unit: entity work.debouncer(Behavioral)
port map(
resetin => resetin,
resetout => reset,
resetout_n => reset_n
);
resetin <= btnCpuReset;
serial_unit: entity work.UART_TX_CTRL(Behavioral)
port map(
SEND => send,
DATA => serialData,
CLK => clk,
READY => ready,
UART_TX => txd
);
RsTx <= txd;
serialLoader_unit: entity work.serialLoader(Behavioral)
port map (
-- global clock
clk => clk,
reset => reset,
--serial control signals
S_Send => send,
S_DataOut => serialData,
S_Ready => ready,
--FIFO DATA
FIFO_Empty => FIFO_Empty,
FIFO_Data => FIFO_DataOut,
FIFO_ReadEn => FIFO_ReadEn
);
serialFIFObuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => FIFO_WriteEn,
DataIn => FIFO_DataIn,
ReadEn => FIFO_ReadEn,
DataOut => FIFO_DataOut,
Empty => FIFO_Empty,
Full => FIFO_Full
);
i2cControl_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => FIFO_WriteEn,
FIFO_DataIn => FIFO_DataIn,
FIFO_Full => FIFO_Full,
ena => ena,
addr => addr,
rw => rw,
busy => busy,
data_rd => data_rd,
ack_error => ack_error
);
i2ccomms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => ena,
addr => addr,
rw => rw,
data_wr => data_wr,
busy => busy,
data_rd => data_rd,
ack_error => ack_error,
sda => JA1,-- sda,
scl => JA0 --scl
);
JA2 <= ack_error;
JA3 <= ena;
end Behavioral;
| gpl-3.0 | 8ba298a8fbe7de1aceb3357b89eac16e | 0.543956 | 3.717899 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/crcnibshiftreg.vhd | 4 | 8,788 | -------------------------------------------------------------------------------
-- crcnibshiftreg - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : crcnibshiftreg.vhd
-- Version : v2.0
-- Description : CRC Nible Shift Register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clke -- Clock enable
-- Din -- Data in
-- Load -- Data load
-- Shift -- Data shift enable
-- Dout -- data out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcnibshiftreg is
port (
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic;
Din : in std_logic_vector(31 downto 0);
Load : in std_logic;
Shift : in std_logic;
Dout : out std_logic_vector(31 downto 0)
);
end crcnibshiftreg;
architecture implementation of crcnibshiftreg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal nibData : std_logic_vector (31 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS : SHIFTER
----------------------------------------------------------------------------
-- The process shifts the nibble data when shift is enabled.
----------------------------------------------------------------------------
SHIFTER : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if Rst = '1' then
nibData <= (others => '0');
elsif (Clken = '1') then
if (Load = '1') then
nibData <= Din;
elsif (Shift = '1') then
nibData(3 downto 0) <= nibData(7 downto 4);
nibData(7 downto 4) <= nibData(11 downto 8);
nibData(11 downto 8) <= nibData(15 downto 12);
nibData(15 downto 12) <= nibData(19 downto 16);
nibData(19 downto 16) <= nibData(23 downto 20);
nibData(23 downto 20) <= nibData(27 downto 24);
nibData(27 downto 24) <= nibData(31 downto 28);
nibData(31 downto 28) <= (others => '0');
end if;
end if;
end if;
end process SHIFTER;
Dout <= nibData;
end implementation;
| gpl-3.0 | 6a96856c4c6dde32e17eea9750743d84 | 0.378129 | 5.428042 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_tb/AEAD_TB.vhd | 1 | 22,868 | -------------------------------------------------------------------------------
--! @file AEAD_TB.vhd
--! @brief Testbench for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @version 1.0b1
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity AEAD_TB IS
generic (
G_ASYNC_RSTN : boolean := False;
--! Test parameters
G_STOP_AT_FAULT : boolean := True;
G_TEST_MODE : integer := 0;
G_TEST_ISTALL : integer := 10;
G_TEST_OSTALL : integer := 10;
G_LOG2_FIFODEPTH : integer := 8;
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_PERIOD : time := 10 ns;
G_FNAME_PDI : string := "pdi.txt";
G_FNAME_SDI : string := "sdi.txt";
G_FNAME_DO : string := "do.txt";
G_FNAME_LOG : string := "log.txt";
G_FNAME_RESULT : string := "result.txt"
);
end AEAD_TB;
architecture behavior of AEAD_TB is
--! =================== --
--! SIGNALS DECLARATION --
--! =================== --
--! simulation signals (used by ATHENa script, ignore if not used)
signal simulation_fails : std_logic := '0';
signal stop_clock : boolean := False;
--! error check signal
signal global_stop : std_logic := '1';
--! globals
signal clk : std_logic := '0';
signal io_clk : std_logic := '0';
signal rst : std_logic := '0';
--! pdi
signal fpdi_din : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
signal fpdi_din_valid : std_logic := '0';
signal fpdi_din_ready : std_logic;
signal fpdi_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal fpdi_dout_valid : std_logic;
signal fpdi_dout_ready : std_logic;
signal pdi_delayed : std_logic_vector(G_PWIDTH-1 downto 0);
signal pdi_valid : std_logic;
signal pdi_valid_selected : std_logic;
signal pdi_ready : std_logic;
--! sdi
signal fsdi_din : std_logic_vector(G_SWIDTH-1 downto 0)
:= (others=>'0');
signal fsdi_din_valid : std_logic := '0';
signal fsdi_din_ready : std_logic;
signal fsdi_dout : std_logic_vector(G_SWIDTH-1 downto 0);
signal fsdi_dout_valid : std_logic;
signal fsdi_dout_ready : std_logic;
signal sdi_delayed : std_logic_vector(G_SWIDTH-1 downto 0);
signal sdi_valid : std_logic;
signal sdi_valid_selected : std_logic;
signal sdi_ready : std_logic;
--! do
signal do : std_logic_vector(G_PWIDTH-1 downto 0);
signal do_valid : std_logic;
signal do_ready : std_logic;
signal do_ready_selected : std_logic;
signal fdo_din_ready : std_logic;
signal fdo_din_valid : std_logic;
signal fdo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal fdo_dout_valid : std_logic;
signal fdo_dout_ready : std_logic := '0';
--! Verification signals
signal stall_pdi_valid : std_logic := '0';
signal stall_sdi_valid : std_logic := '0';
signal stall_do_full : std_logic := '0';
------------- clock constant ------------------
constant clk_period : time := G_PERIOD;
constant io_clk_period : time := clk_period;
----------- end of clock constant -------------
------------- string constant ------------------
--! constant
constant cons_ins_out : string(1 to 6) := "# INS:";
constant cons_ins : string(1 to 6) := "INS = ";
constant cons_hdr : string(1 to 6) := "HDR = ";
constant cons_dat : string(1 to 6) := "DAT = ";
constant cons_stt : string(1 to 6) := "STT = ";
--! Shared constant
constant cons_eof : string(1 to 6) := "###EOF";
----------- end of string constant -------------
------------- debug constant ------------------
constant debug_input : boolean := False;
constant debug_output : boolean := False;
----------- end of clock constant -------------
-- ================= --
-- FILES DECLARATION --
-- ================= --
--------------- input / output files -------------------
file pdi_file : text open read_mode is G_FNAME_PDI;
file sdi_file : text open read_mode is G_FNAME_SDI;
file do_file : text open read_mode is G_FNAME_DO;
file log_file : text open write_mode is G_FNAME_LOG;
file result_file : text open write_mode is G_FNAME_RESULT;
------------- end of input files --------------------
begin
genClk: process
begin
if (not stop_clock and global_stop = '1') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process genClk;
genIOclk: process
begin
if ((not stop_clock) and (global_stop = '1')) then
io_clk <= '1';
wait for io_clk_period/2;
io_clk <= '0';
wait for io_clk_period/2;
else
wait;
end if;
end process genIOclk;
--! ============ --
--! PORT MAPPING --
--! ============ --
genPDIfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => fpdi_din,
din_valid => fpdi_din_valid,
din_ready => fpdi_din_ready,
dout => fpdi_dout,
dout_valid => fpdi_dout_valid,
dout_ready => fpdi_dout_ready
);
fpdi_dout_ready <= '0' when stall_pdi_valid = '1' else pdi_ready;
pdi_valid_selected <= '1' when stall_pdi_valid = '1' else fpdi_dout_valid;
pdi_valid <= pdi_valid_selected after 1/4*clk_period;
pdi_delayed <= fpdi_dout after 1/4*clk_period;
genSDIfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_SWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => fsdi_din,
din_valid => fsdi_din_valid,
din_ready => fsdi_din_ready,
dout => fsdi_dout,
dout_valid => fsdi_dout_valid,
dout_ready => fsdi_dout_ready
);
fsdi_dout_ready <= '0' when stall_sdi_valid = '1' else sdi_ready;
sdi_valid_selected <= '1' when stall_sdi_valid = '1' else fsdi_dout_valid;
sdi_valid <= sdi_valid_selected after 1/4*clk_period;
sdi_delayed <= fsdi_dout after 1/4*clk_period;
genDOfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => do,
din_valid => fdo_din_valid,
din_ready => fdo_din_ready,
dout => fdo_dout,
dout_valid => fdo_dout_valid,
dout_ready => fdo_dout_ready
);
fdo_din_valid <= '0' when stall_do_full = '1' else do_valid;
do_ready_selected <= '1' when stall_do_full = '1' else fdo_din_ready;
do_ready <= do_ready_selected after 1/4*clk_period;
uut: entity work.AEAD(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_SW => G_SWIDTH
)
port map (
rst => rst,
clk => clk,
pdi_data => pdi_delayed,
pdi_ready => pdi_ready,
pdi_valid => pdi_valid,
sdi_data => sdi_delayed,
sdi_ready => sdi_ready,
sdi_valid => sdi_valid,
do_data => do,
do_valid => do_valid,
do_ready => do_ready
);
--! =================== --
--! END OF PORT MAPPING --
--! =================== --
--! =======================================================================
--! ==================== DATA POPULATION FOR PUBLIC DATA ==================
tb_read_pdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
if (not G_ASYNC_RSTN) then
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
else
rst <= '0'; wait for 5*clk_period;
rst <= '1'; wait for clk_period;
end if;
--! read header
while ( not endfile (pdi_file)) and ( loop_enable = '1' ) loop
if endfile (pdi_file) then
loop_enable := '0';
end if;
readline(pdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( pdi_file ) loop
--! if the fifo is full, wait ...
fpdi_din_valid <= '1';
if ( fpdi_din_ready = '0' ) then
fpdi_din_valid <= '0';
wait until fpdi_din_ready <= '1';
wait for io_clk_period/2; --! write in the rising edge
fpdi_din_valid <= '1';
end if;
hreadnew( line_data, word_block, read_result );
while (((read_result = False) or (valid_line = False))
and (not endfile( pdi_file )))
loop
readline(pdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
fpdi_din_valid <= '1';
else
valid_line := False;
fpdi_din_valid <= '0';
end if;
hreadnew( line_data, word_block, read_result ); --! read data
end loop;
fpdi_din <= word_block;
wait for io_clk_period;
end loop;
fpdi_din_valid <= '0';
wait;
end process;
--! =======================================================================
--! ==================== DATA POPULATION FOR SECRET DATA ==================
tb_read_sdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_SWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
--! Wait until reset is done
wait for 7*clk_period;
--! read header
while (not endfile (sdi_file)) and (loop_enable = '1') loop
if endfile (sdi_file) then
loop_enable := '0';
end if;
readline(sdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( sdi_file ) loop
--! if the fifo is full, wait ...
fsdi_din_valid <= '1';
if ( fsdi_din_ready = '0' ) then
fsdi_din_valid <= '0';
wait until fsdi_din_ready <= '1';
wait for io_clk_period/2; --! write in the rising edge
fsdi_din_valid <= '1';
end if;
hreadnew(line_data, word_block, read_result);
while (((read_result = False) or (valid_line = False))
and (not endfile(sdi_file)))
loop
readline(sdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_ins or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
fsdi_din_valid <= '1';
else
valid_line := False;
fsdi_din_valid <= '0';
end if;
hreadnew( line_data, word_block, read_result ); --! read data
end loop;
fsdi_din <= word_block;
wait for io_clk_period;
end loop;
fsdi_din_valid <= '0';
wait;
end process;
--! =======================================================================
--! =======================================================================
--! =================== DATA VERIFICATION =================================
tb_verifydata : process
variable line_no : integer := 0;
variable line_data : line;
variable logMsg : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
variable word_count : integer := 1;
variable word_pass : integer := 1;
variable instr : boolean := False;
variable force_exit : boolean := False;
variable msgid : integer;
variable keyid : integer ;
variable isEncrypt : boolean := False;
variable opcode : std_logic_vector(3 downto 0);
variable my_line : line; -- type 'line' comes from textio
begin
wait for 6*clk_period;
while (not endfile (do_file) and valid_line and (not force_exit)) loop
--! Keep reading new line until a valid line is found
hreadnew( line_data, word_block, read_result );
while ((read_result = False or valid_line = False)
and (not endfile(do_file)))
loop
readline(do_file, line_data);
line_no := line_no + 1;
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_hdr
or temp_read = cons_dat
or temp_read = cons_stt)
then
valid_line := True;
word_count := 1;
else
valid_line := False;
if (temp_read = cons_ins_out) then
instr := True;
end if;
end if;
if (temp_read = cons_eof) then
force_exit := True;
end if;
hreadnew(line_data, word_block, read_result); --! read data
if (instr = True) then
instr := False;
read_result := False;
opcode := word_block(G_PWIDTH-1 downto G_PWIDTH-4);
keyid := to_integer(unsigned(
word_block(G_PWIDTH+5-10 downto G_PWIDTH-10)));
msgid := to_integer(unsigned(
word_block(G_PWIDTH+5-16 downto G_PWIDTH-16)));
isEncrypt := False;
if ((opcode = OP_DEC or opcode = OP_ENC)
or (opcode = STAT_SUCCESS or opcode = STAT_FAILURE))
then
write(logMsg, string'("[Log] == Verifying msg ID #")
& integer'image(msgid)
& string'(" with key ID #") & integer'image(keyid));
if (opcode = OP_ENC) then
isEncrypt := True;
write(logMsg, string'(" for ENC"));
else
write(logMsg, string'(" for DEC"));
end if;
writeline(log_file,logMsg);
end if;
report "---------Started verifying message number "
& integer'image(msgid) & " at "
& time'image(now) severity note;
end if;
end loop;
--! if the core is slow in outputting the digested message, wait ...
if ( valid_line ) then
fdo_dout_ready <= '1';
if ( fdo_dout_valid = '0') then
fdo_dout_ready <= '0';
wait until fdo_dout_valid = '1';
wait for io_clk_period/2;
fdo_dout_ready <= '1';
end if;
word_pass := 1;
for i in G_PWIDTH-1 downto 0 loop
if fdo_dout(i) /= word_block(i)
and word_block(i) /= 'X'
then
word_pass := 0;
end if;
end loop;
if word_pass = 0 then
simulation_fails <= '1';
write(logMsg, string'("[Log] Msg ID #")
& integer'image(msgid)
& string'(" fails at line #") & integer'image(line_no)
& string'(" word #") & integer'image(word_count));
writeline(log_file,logMsg);
write(logMsg, string'("[Log] Expected: ")
& to_hstring(word_block)
& string'(" Received: ") & to_hstring(fdo_dout));
writeline(log_file,logMsg);
--! Stop the simulation right away when an error is detected
report "---------Data line #" & integer'image(line_no)
& " Msg ID #" & integer'image(msgid)
& " Key ID #" & integer'image(keyid)
& " Word #" & integer'image(word_count)
& " at " & time'image(now) & " FAILS T_T --------"
severity note;
report "Expected: " & to_hstring(word_block)
& " Actual: " & to_hstring(fdo_dout) severity note;
write(result_file, "fail");
if (G_STOP_AT_FAULT = True) then
force_exit := True;
else
if isEncrypt = False then
report "---------Skip to the next instruction"
& " at " & time'image(now) severity note;
write(logMsg,
string'("[Log] ...skips to next message ID"));
writeline(log_file, logMsg);
end if;
end if;
else
write(logMsg, string'("[Log] Expected: ")
& to_hstring(word_block)
& string'(" Received: ") & to_hstring(fdo_dout));
writeline(log_file,logMsg);
end if;
wait for io_clk_period;
word_count := word_count + 1;
end if;
end loop;
fdo_dout_ready <= '0';
wait for io_clk_period;
if (simulation_fails = '1') then
report "FAIL (1): SIMULATION FINISHED || Input/Output files :: T_T"
& G_FNAME_PDI & "/" & G_FNAME_SDI
& "/" & G_FNAME_DO severity error;
write(result_file, "1");
else
report "PASS (0): SIMULATION FINISHED || Input/Output files :: ^0^"
& G_FNAME_PDI & "/" & G_FNAME_SDI
& "/" & G_FNAME_DO severity note;
write(result_file, "0");
end if;
write(logMsg, string'("[Log] Done"));
writeline(log_file,logMsg);
stop_clock <= True;
wait;
end process;
--! =======================================================================
--! =======================================================================
--! =================== Test MODE =========================================
genInputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
wait until rising_edge( pdi_ready );
wait for io_clk_period;
stall_pdi_valid <= '1';
stall_sdi_valid <= '1';
wait for io_clk_period*G_TEST_ISTALL;
stall_pdi_valid <= '0';
stall_sdi_valid <= '0';
else
wait;
end if;
end process;
genOutputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 3 then
wait until rising_edge( do_valid );
wait for io_clk_period;
stall_do_full <= '1';
wait for io_clk_period*G_TEST_OSTALL;
stall_do_full <= '0';
else
wait;
end if;
end process;
end;
| apache-2.0 | dfac5691d2329dd1a009a52aaba6ef3a | 0.44459 | 4.261275 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/AEAD.vhd | 1 | 2,280 | -------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @author Hannes Gross
--! @brief Generic Ascon-128(a) implementation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity AEAD is
generic (
--! I/O width (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features parameters
G_ENABLE_PAD : boolean := True; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data 128 or 64
G_DBLK_SIZE : integer := 128; --! Data 128 or 64
G_KEY_SIZE : integer := 32; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! Padding options
G_PAD_STYLE : integer := 1; --! Pad style
G_PAD_AD : integer := 3; --! Padding behavior for AD
G_PAD_D : integer := 4; --! Padding behavior for Data
--! Maximum supported AD/message/ciphertext length = 2^G_MAX_LEN-1
G_MAX_LEN : integer := SINGLE_PASS_MAX
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
| apache-2.0 | 6b295b895b23c6d6f96af517c69d4e2b | 0.457456 | 4.153005 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/synth/design_1_ilmb_bram_if_cntlr_0.vhd | 2 | 13,330 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_ilmb_bram_if_cntlr_0;
ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"20000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_ilmb_bram_if_cntlr_0_arch;
| gpl-3.0 | 43705266c0a8b26464f80907e825e3e6 | 0.66159 | 3.149067 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernetlite_0_0/synth/design_1_axi_ethernetlite_0_0.vhd | 2 | 13,337 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0;
USE axi_ethernetlite_v3_0.axi_ethernetlite;
ENTITY design_1_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END design_1_axi_ethernetlite_0_0;
ARCHITECTURE design_1_axi_ethernetlite_0_0_arch OF design_1_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_PING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END design_1_axi_ethernetlite_0_0_arch;
| gpl-3.0 | 83249c1442b56ce005b984b0ebdfa6b5 | 0.679913 | 3.136642 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/lfsr16.vhd | 4 | 11,229 | -------------------------------------------------------------------------------
-- lfsr16 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : lfsr16.vhd
-- Version : v2.0
-- Description : This is a 15 bit random number generator.
-- In simulation we need to reset first, then give the enable signal.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- This is a 15 bit random number generator.
-- In simulation we need to reset first, then give the enable signal.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clken -- Clock enable
-- Enbl -- LFSR enable
-- Shftout -- Shift data output
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity lfsr16 is
port
(
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic; -- tx Clk based. Assumed to be 2.5 or 25 MHz
Enbl : in std_logic;
Shftout : out std_logic
);
end lfsr16;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture imp of lfsr16 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Bit1 : std_logic;
signal Bit15 : std_logic;
signal Bit14 : std_logic;
signal XNORGateOutput : std_logic;
signal zero : std_logic;
signal one : std_logic;
signal combo_enbl : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the 16 bit lfsr
component SRL16E
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (
Q : out std_logic;
A0 : in std_logic; -- Set the address to 12.
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
Clk : in std_logic;
CE : in std_logic);
end component;
begin
zero <= '0';
one <= '1';
SHREG0 : SRL16E
-- synthesis translate_off
generic map (INIT => X"5a5a")
-- synthesis translate_on
port map(
Q => Bit14,
A0 => zero,
A1 => zero,
A2 => one,
A3 => one,
D => Bit1,
CE => combo_enbl,
Clk => Clk);
combo_enbl <= Enbl and Clken;
-------------------------------------------------------------------------------
-- determine bit 15 value
-------------------------------------------------------------------------------
REG0_PROCESS:process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Bit15 <= '0';
elsif combo_enbl = '1' then
Bit15 <= Bit14;
end if;
end if;
end process REG0_PROCESS;
-------------------------------------------------------------------------------
-- determine bit 1 value
-------------------------------------------------------------------------------
REG1_PROCESS:process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Bit1 <= '0';
elsif combo_enbl = '1' then
Bit1 <= XNORGateOutput;
end if;
end if;
end process REG1_PROCESS;
XNORGateOutput <= Bit14 XNOR Bit15;
Shftout <= Bit1;
end imp;
| gpl-3.0 | 13cc949f09d8026a65a3a36f29721f03 | 0.379197 | 5.321801 | false | false | false | false |
hoangt/PoC | tb/misc/stat/stat_Maximum_tb.vhdl | 2 | 6,190 | -- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Authors: Patrick Lehmann
--
-- Description: Testbench for stat_Maximum.
--
-------------------------------------------------------------------------------
-- Copyright 2007-2015 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use poC.utils.all;
use poC.vectors.all;
entity stat_Maximum_tb is
end entity;
architecture tb of stat_Maximum_tb is
-- component generics
constant VALUES : T_NATVEC := (
113, 106, 126, 239, 146, 72, 51, 210, 44, 56, 10, 126, 7, 7, 22, 18,
128, 217, 106, 210, 58, 71, 213, 206, 169, 213, 90, 27, 166, 159, 83, 116,
246, 208, 105, 64, 112, 12, 110, 10, 5, 100, 12, 231, 191, 235, 27, 143,
162, 178, 136, 149, 92, 221, 122, 44, 143, 169, 72, 182, 232, 26, 46, 135,
223, 144, 129, 48, 148, 208, 156, 119, 109, 98, 207, 208, 62, 232, 17, 183,
189, 197, 115, 237, 25, 183, 27, 27, 89, 64, 170, 192, 189, 177, 28, 228,
56, 127, 10, 49, 108, 229, 244, 204, 25, 20, 42, 243, 16, 163, 232, 161,
154, 139, 243, 38, 160, 59, 113, 42, 120, 104, 208, 87, 40, 213, 179, 181,
73, 228, 155, 184, 224, 218, 77, 210, 202, 161, 215, 7, 143, 34, 13, 175,
81, 12, 40, 53, 184, 240, 71, 247, 17, 218, 179, 7, 23, 159, 166, 61,
90, 111, 172, 37, 11, 50, 186, 186, 64, 36, 85, 249, 93, 108, 148, 89,
93, 35, 7, 30, 175, 129, 247, 83, 160, 157, 170, 9, 41, 73, 189, 45,
244, 157, 166, 35, 111, 226, 167, 34, 76, 104, 239, 151, 157, 71, 156, 159,
72, 93, 163, 237, 153, 139, 135, 211, 113, 92, 126, 103, 130, 180, 147, 240,
96, 42, 7, 185, 191, 115, 227, 117, 118, 224, 204, 74, 140, 98, 176, 92,
3, 13, 187, 198, 160, 201, 141, 108, 24, 205, 171, 22, 102, 66, 153, 146,
206, 248, 58, 117, 67, 220, 217, 206, 115, 48, 122, 179, 184, 63, 74, 18,
166, 37, 103, 119, 242, 198, 82, 144, 151, 149, 164, 235, 193, 207, 18, 55,
74, 61, 118, 141, 42, 61, 28, 32, 46, 230, 85, 114, 82, 212, 173, 210,
134, 156, 106, 67, 212, 36, 153, 10, 168, 164, 216, 168, 59, 231, 15, 157,
33, 69, 107, 126, 195, 182, 225, 107, 12, 73, 76, 15, 116, 218, 64, 188,
225, 203, 104, 40, 104, 200, 92, 40, 158, 110, 222, 128, 95, 110, 223, 64,
218, 178, 84, 16, 108, 50, 18, 202, 180, 249, 58, 142, 210, 141, 144, 200,
102, 30, 192, 106, 130, 224, 56, 82, 226, 69, 218, 88, 209, 100, 15, 152,
100, 14, 46, 188, 136, 51, 83, 178, 188, 152, 110, 105, 145, 199, 80, 19,
215, 25, 29, 67, 167, 119, 184, 243, 124, 5, 39, 41, 81, 179, 242, 83,
236, 155, 45, 198, 97, 206, 67, 54, 197, 17, 168, 227, 117, 200, 186, 29,
239, 201, 122, 187, 74, 197, 234, 230, 80, 53, 66, 133, 14, 44, 99, 11,
160, 29, 118, 239, 157, 131, 172, 12, 207, 224, 119, 153, 201, 206, 128, 173,
69, 12, 51, 129, 60, 57, 12, 42, 171, 64, 121, 46, 143, 184, 42, 156,
167, 160, 70, 91, 85, 196, 122, 110, 32, 113, 229, 99, 81, 84, 32, 123,
174, 142, 66, 5, 242, 220, 200, 105, 20, 79, 71, 95, 13, 128, 119, 26
);
type T_RESULT is record
Maximum : NATURAL;
Count : POSITIVE;
end record;
type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT;
constant RESULT : T_RESULT_VECTOR := (
(Maximum => 249, Count => 2),
(Maximum => 248, Count => 1),
(Maximum => 247, Count => 2),
(Maximum => 246, Count => 1),
(Maximum => 244, Count => 2),
(Maximum => 243, Count => 3),
(Maximum => 242, Count => 3),
(Maximum => 240, Count => 2)
);
constant DEPTH : POSITIVE := RESULT'length;
constant DATA_BITS : POSITIVE := 8;
constant COUNTER_BITS : POSITIVE := 4;
-- component ports
signal Clock : STD_LOGIC := '1';
signal Reset : STD_LOGIC := '0';
signal Enable : STD_LOGIC := '0';
signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal Maximums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0);
signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0);
signal Maximums_slvv : T_SLVV_8(DEPTH - 1 downto 0);
signal Counts_slvv : T_SLVV_4(DEPTH - 1 downto 0);
begin
-- component instantiation
DUT: entity PoC.stat_Maximum
generic map (
DEPTH => DEPTH,
DATA_BITS => DATA_BITS,
COUNTER_BITS => COUNTER_BITS
)
port map (
Clock => Clock,
Reset => Reset,
Enable => Enable,
DataIn => DataIn,
Valids => Valids,
Maximums => Maximums,
Counts => Counts
);
Maximums_slvv <= to_slvv_8(Maximums);
Counts_slvv <= to_slvv_4(Counts);
process
procedure cycle is
begin
Clock <= '1';
wait for 5 ns;
Clock <= '0';
wait for 5 ns;
end cycle;
variable good : BOOLEAN;
begin
cycle;
Reset <= '1';
cycle;
Reset <= '0';
cycle;
cycle;
Enable <= '1';
for i in VALUES'range loop
--Enable <= to_sl(VALUES(i) /= 35);
DataIn <= to_slv(VALUES(i), DataIn'length);
cycle;
end loop;
cycle;
-- test result after all cycles
good := (slv_and(Valids) = '1');
for i in RESULT'range loop
good := good and (RESULT(i).Maximum = unsigned(Maximums_slvv(i))) and (RESULT(i).Count = unsigned(Counts_slvv(i)));
end loop;
assert (good = TRUE)
report "Test failed."
severity note;
assert (good = FALSE)
report "Test passed."
severity note;
wait;
end process;
end;
| apache-2.0 | d79ab8175c6a9bf5f1c25052844e8c36 | 0.575214 | 2.766652 | false | false | false | false |
IAIK/ascon_hardware | generic_implementation/ascon_fast_bus.vhdl | 1 | 10,795 | -------------------------------------------------------------------------------
-- Title : Bus logic of Ascon module
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_fast_bus.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2016-05-25
-- Last update: 2016-06-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-25 1.0 Hannes Gross created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon is
generic (
UNROLED_ROUNDS : integer := 1; --1,2,3,6
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic; -- active-high chip select
WExSI : in std_logic; -- active-high write enable
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity ascon;
architecture structural of ascon is
constant CONTROL_STATE_SIZE : integer := 4;
constant STATE_WORD_SIZE : integer := 64;
constant CONST_UNROLED_R : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(UNROLED_ROUNDS, 8));
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
signal CP_InitxSP, CP_InitxSn : std_logic;
signal CP_AssociatexSP, CP_AssociatexSN : std_logic;
signal CP_EncryptxSP, CP_EncryptxSN : std_logic;
signal CP_DecryptxSP, CP_DecryptxSN : std_logic;
signal CP_FinalEncryptxSP, CP_FinalEncryptxSN : std_logic;
signal CP_FinalDecryptxSP, CP_FinalDecryptxSN : std_logic;
signal KeyxDP, KeyxDN : std_logic_vector(KEY_SIZE-1 downto 0);
signal DP_WriteNoncexS : std_logic;
signal DP_WriteIODataxS : std_logic;
signal CP_DonexS, CP_InitxS, CP_AssociatexSI : std_logic;
signal CP_EncryptxS, CP_DecryptxS, CP_FinalEncryptxS : std_logic;
signal CP_FinalDecryptxS : std_logic;
signal IODataxD : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
signal StatexD : std_logic_vector(5*STATE_WORD_SIZE-1 downto 0);
alias State0xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*1 -1 downto 64*0);
alias State1xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*2 -1 downto 64*1);
alias State2xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*3 -1 downto 64*2);
alias State3xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*4 -1 downto 64*3);
alias State4xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*5 -1 downto 64*4);
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
variable x : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- ROTATE_STATE_WORD
x := word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
return x;
end ROTATE_STATE_WORD;
begin -- architecture structural
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
KeyxDP <= (others => '0');
CP_InitxSP <= '0';
CP_AssociatexSP <= '0';
CP_EncryptxSP <= '0';
CP_DecryptxSP <= '0';
CP_FinalEncryptxSP <= '0';
CP_FinalDecryptxSP <= '0';
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
KeyxDP <= KeyxDN;
CP_InitxSP <= CP_InitxSN;
CP_AssociatexSP <= CP_AssociatexSN;
CP_EncryptxSP <= CP_EncryptxSN;
CP_DecryptxSP <= CP_DecryptxSN;
CP_FinalEncryptxSP <= CP_FinalEncryptxSN;
CP_FinalDecryptxSP <= CP_FinalDecryptxSN;
end if;
end process RegisterProc;
-- purpose: Glue the internal registers with the bus
-- type : combinational
DataBusLogicProc : process (AddressxDI, CP_AssociatexSP,
CP_DecryptxSP, CP_DonexS, CP_EncryptxSP,
CP_FinalDecryptxSP, CP_FinalEncryptxSP,
CP_InitxSP, CSxSI, DataWritexDI, DataWritexDI(0),
DataWritexDI, IODataxD, KeyxDP,
State3xD,
State4xD,
WExSI) is
variable AddressxDV : integer;
variable index : integer;
begin -- process DataBusLogicProc
KeyxDN <= KeyxDP;
AddressxDV := to_integer(unsigned(AddressxDI));
index := 0;
DataReadxDO <= (others => '0');
DP_WriteNoncexS <= '0';
DP_WriteIODataxS <= '0';
CP_InitxSN <= CP_InitxSP;
CP_AssociatexSN <= CP_AssociatexSP;
CP_EncryptxSN <= CP_EncryptxSP;
CP_DecryptxSN <= CP_DecryptxSP;
CP_FinalEncryptxSN <= CP_FinalEncryptxSP;
CP_FinalDecryptxSN <= CP_FinalDecryptxSP;
if CP_DonexS = '1' then
CP_InitxSN <= '0';
CP_AssociatexSN <= '0';
CP_EncryptxSN <= '0';
CP_DecryptxSN <= '0';
CP_FinalEncryptxSN <= '0';
CP_FinalDecryptxSN <= '0';
end if;
if CSxSI = '1' then
if WExSI = '1' then
-- synchronous write
if AddressxDV = 2 then
-- command register
CP_InitxSN <= DataWritexDI(0);
CP_AssociatexSN <= DataWritexDI(1);
CP_EncryptxSN <= DataWritexDI(2);
CP_DecryptxSN <= DataWritexDI(3);
CP_FinalEncryptxSN <= DataWritexDI(4);
CP_FinalDecryptxSN <= DataWritexDI(5);
elsif (AddressxDV >= 4) and (AddressxDV < 8) then
-- write the key
index := to_integer(unsigned(AddressxDI(1 downto 0)));
KeyxDN((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH) <= DataWritexDI;
elsif (AddressxDV >= 8) and (AddressxDV < 12) then
-- write the nonce
DP_WriteNoncexS <= '1';
--elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- -- write the data to de/encrypt and associated data
-- DP_WriteIODataxS <= '1';
end if;
else
-- asynchronous read
if AddressxDV = 0 then
DataReadxDO <= x"deadbeef";
elsif AddressxDV = 1 then
-- status register
-- returns 1 if busy
DataReadxDO(0) <= CP_InitxSP or CP_AssociatexSP or CP_EncryptxSP or CP_DecryptxSP or CP_FinalEncryptxSP or CP_FinalDecryptxSP;
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- read the de/encrypted data and associated data
index := to_integer(unsigned(AddressxDI(0 downto 0)));
DataReadxDO <= IODataxD((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH);
elsif (AddressxDV >= 16) and (AddressxDV < 20) then
-- read the tag
if DATA_BUS_WIDTH = 64 then
if AddressxDI(1 downto 0) = "00" then
DataReadxDO <= State4xD;
elsif AddressxDI(1 downto 0) = "01" then
DataReadxDO <= State3xD;
end if;
else -- 128 bit variant
DataReadxDO <= State3xD & State4xD;
end if;
end if;
end if;
end if;
end process DataBusLogicProc;
ascon_core_1: entity work.ascon_core
generic map (
UNROLED_ROUNDS => UNROLED_ROUNDS,
KEY_SIZE => KEY_SIZE,
DATA_BLOCK_SIZE => DATA_BLOCK_SIZE,
ROUNDS_A => ROUNDS_A,
ROUNDS_B => ROUNDS_B,
DATA_BUS_WIDTH => DATA_BUS_WIDTH,
ADDR_BUS_WIDTH => ADDR_BUS_WIDTH)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
AddressxDI => AddressxDI,
DP_WriteNoncexSI => DP_WriteNoncexS,
DataWritexDI => DataWritexDI,
KeyxDI => KeyxDP,
DP_WriteIODataxSI => DP_WriteIODataxS,
IODataxDO => IODataxD,
CP_DonexSO => CP_DonexS,
CP_InitxSI => CP_InitxSP,
CP_AssociatexSI => CP_AssociatexSP,
CP_EncryptxSI => CP_EncryptxSP,
CP_DecryptxSI => CP_DecryptxSP,
CP_FinalEncryptxSI => CP_FinalEncryptxSP,
CP_FinalDecryptxSI => CP_FinalDecryptxSP,
StatexDO => StatexD);
end architecture structural;
| apache-2.0 | 7136a5419608abed49b9af446b8dc15d | 0.540899 | 4.340571 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/cntr5bit.vhd | 4 | 9,577 | -------------------------------------------------------------------------------
-- cntr5bit - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : cntr5bit.vhd
-- Version : v2.0
--
-- Description : This file contains the a 5 bit resetable, loadable
-- down counter by 1.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Cntout -- Counter output
-- En -- Counter enable
-- Ld -- Counter load enable
-- Load_in -- Counter load data
-- Zero -- Terminal count
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity cntr5bit is
port (
Clk : in std_logic; -- input clock
Rst : in std_logic; -- reset counter
Cntout : out std_logic_vector (0 to 4);
En : in std_logic; -- counter down enable by 1
Ld : in std_logic; -- load enable
Load_in : in std_logic_vector (0 to 4); -- load input value
Zero : out std_logic -- terminal count
);
end cntr5bit;
architecture implementation of cntr5bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal count : std_logic_vector(0 to 4);
signal zero_i : std_logic;
begin
Cntout <= count;
-------------------------------------------------------------------------------
-- INT_count_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal control register signals to the out port
-------------------------------------------------------------------------------
INT_COUNT_PROCESS1: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
count <= (others => '1');
elsif (Ld = '1') then
count <= Load_in;
elsif (En = '1' and zero_i = '0') then
count <= count - 1;
else
null;
end if;
end if;
end process INT_COUNT_PROCESS1;
INT_COUNT_PROCESS2: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
zero_i <= '1';
else
if (count = "00001") then
zero_i <= '1';
else
zero_i <= '0';
end if;
end if;
end if;
end process INT_COUNT_PROCESS2;
Zero <= zero_i;
end implementation;
| gpl-3.0 | 2896619ec4b99517d54abdab86f02298 | 0.380599 | 5.29116 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/bufg/igdsbuf_tech.vhd | 2 | 1,873 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual Gigabits buffer with the differential signals.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end;
architecture rtl of igdsbuf_tech is
component igdsbuf_kintex7 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
component igdsbuf_virtex6 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
component igdsbuf_artix7 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
begin
infer : if generic_tech = inferred generate
o_clk <= gclk_p;
end generate;
xv6 : if generic_tech = virtex6 generate
x1 : igdsbuf_virtex6 port map (
gclk_p => gclk_p,
gclk_n => gclk_n,
o_clk => o_clk
);
end generate;
xk7 : if generic_tech = kintex7 generate
x1 : igdsbuf_kintex7 port map (
gclk_p => gclk_p,
gclk_n => gclk_n,
o_clk => o_clk
);
end generate;
xa7 : if generic_tech = artix7 generate
x1 : igdsbuf_artix7 port map (
gclk_p => gclk_p,
gclk_n => gclk_n,
o_clk => o_clk
);
end generate;
end;
| bsd-2-clause | dd9c6174d9aee0040cab89511c38b744 | 0.531233 | 3.636893 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/bufg/obuf_tech.vhd | 2 | 1,073 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple output buffer.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity obuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of obuf_tech is
component obuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component obuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = micron180 generate
bufm : obuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= micron180 generate
bufinf : obuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
| bsd-2-clause | 6c105e8e0f8e944e057775b8021f1eb5 | 0.513514 | 3.887681 | false | false | false | false |
hoangt/PoC | src/io/io_7SegmentMux_HEX.vhdl | 2 | 3,202 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: time multiplexed 7 Segment Display Controller for HEX chars
--
-- Description:
-- ------------------------------------
-- This module is a 7 segment display controller that uses time multiplexing
-- to control a common anode for each digit in the display. The shown characters
-- are HEX encoded. A dot per digit is optional.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity io_7SegmentMux_HEX is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
REFRESH_RATE : FREQ := 1 kHz;
DIGITS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
HexDigits : in T_SLVV_4(DIGITS - 1 downto 0);
HexDots : in STD_LOGIC_VECTOR(DIGITS - 1 downto 0);
SegmentControl : out STD_LOGIC_VECTOR(7 downto 0);
DigitControl : out STD_LOGIC_VECTOR(DIGITS - 1 downto 0)
);
end;
architecture rtl of io_7SegmentMux_HEX is
signal DigitCounter_rst : STD_LOGIC;
signal DigitCounter_en : STD_LOGIC;
signal DigitCounter_us : UNSIGNED(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0');
begin
Strobe : entity PoC.misc_StrobeGenerator
generic map (
STROBE_PERIOD_CYCLES => TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ),
INITIAL_STROBE => FALSE
)
port map (
Clock => Clock,
O => DigitCounter_en
);
--
DigitCounter_rst <= counter_eq(DigitCounter_us, DIGITS - 1) and DigitCounter_en;
DigitCounter_us <= counter_inc(DigitCounter_us, DigitCounter_rst, DigitCounter_en) when rising_edge(Clock);
DigitControl <= resize(bin2onehot(std_logic_vector(DigitCounter_us)), DigitControl'length);
process(BCDDigits, BCDDots, DigitCounter_us)
variable HexDigit : T_SLV_4;
variable HexDot : STD_LOGIC;
begin
HexDigit := HexDigits(to_index(DigitCounter_us, HexDigits'length));
HexDot := HexDots(to_index(DigitCounter_us, HexDigits'length));
SegmentControl <= io_7SegmentDisplayEncoding(HexDigit, HexDot);
end process;
end;
| apache-2.0 | 0a8146162ef3c3933e22692139a8a9e0 | 0.642411 | 3.53032 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/correct_one_bit.vhd | 4 | 6,567 | -------------------------------------------------------------------------------
-- correct_one_bit.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- correct_one_bit
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Correct_One_Bit is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
| gpl-3.0 | a24c986f4f3a63b8b4a88a986edd6413 | 0.553068 | 4.261518 | false | false | false | false |
speters/mprfgen | test4.vhd | 1 | 15,412 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity regfile is
generic (
NWP : integer := 1;
NRP : integer := 2;
AW : integer := 10;
DW : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : RAMB16_S36_S36
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DIA => input_data_v(DW*(0+1)-1 downto DW*0),
DIPA => (others => '0'),
ADDRA => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
ENA => enable,
WEA => we_v(0),
SSRA => reset,
CLKA => clock,
DOA => open,
DOPA => open,
DIB => (others => '0'),
DIPB => (others => '0'),
ADDRB => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
ENB => enable,
WEB => '0',
SSRB => reset,
CLKB => clock,
DOB => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0)),
DOPB => open
);
nwp_nrp_bram_instance_1 : RAMB16_S36_S36
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DIA => input_data_v(DW*(0+1)-1 downto DW*0),
DIPA => (others => '0'),
ADDRA => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
ENA => enable,
WEA => we_v(0),
SSRA => reset,
CLKA => clock,
DOA => open,
DOPA => open,
DIB => (others => '0'),
DIPB => (others => '0'),
ADDRB => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
ENB => enable,
WEB => '0',
SSRB => reset,
CLKB => clock,
DOB => ram_output_i(DW*((0*NRP+1)+1)-1 downto DW*(0*NRP+1)),
DOPB => open
);
ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1)-1 downto DW*0);
ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+1)-1 downto DW*1);
end rtl;
| gpl-3.0 | a217fc2721e46bc285ad3408bd4f37b9 | 0.756294 | 6.724258 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sources_1/new/i2c_controller.vhd | 1 | 4,047 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.01.2016 19:23:03
-- Design Name:
-- Module Name: i2c_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_controller is
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
--fifo pins
FIFO_WriteEn : out STD_LOGIC;
FIFO_DataIn: out std_logic_vector ( 7 downto 0);
FIFO_Full : in STD_LOGIC;
ena : out STD_LOGIC := '0'; --latch in command
addr : out STD_LOGIC_VECTOR(6 DOWNTO 0):= "0101000"; --address of target slave
rw : out STD_LOGIC; --'0' is write, '1' is read
busy : in STD_LOGIC; --indicates transaction in progress
data_rd : in STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : in STD_LOGIC --flag if improper acknowledge from slave
);
end i2c_controller;
architecture Behavioral of i2c_controller is
-- state control signals
type state_type is (STATE_WAITREADY, STATE_STARTREAD, STATE_WAIT_RX, STATE_GETBYTE, STATE_WRITEBYTE, STATE_FINISHWRITE, STATE_FINISHREAD, STATE_SLEEPCHK, STATE_SLEEPINC);
signal state_reg: state_type := STATE_WAITREADY;
-- recd. byte counter
signal finishFlag :STD_LOGIC;
signal delay : INTEGER RANGE 0 to 200 := 0;
begin
-- state control
process (clk, FIFO_Full, busy, ack_error) -- process to handle the next state
begin
if rising_edge (clk) then
case state_reg is
when STATE_WAITREADY =>
--reset the timers & counters
delay <= 0;
finishFlag<='0';
-- make sure not enabled
ena <= '0';
if (busy = '0') then
state_reg <= STATE_STARTREAD;
end if;
when STATE_STARTREAD =>
-- load the address and start a read
ena <= '1';
rw <= '1';
if (busy = '1') then
state_reg <= STATE_WAIT_RX;
end if;
when STATE_WAIT_RX =>
if (busy = '0' and ack_error = '0') then
state_reg <= STATE_GETBYTE;
else
if (ack_error = '1') then
state_reg <= STATE_WAITREADY;
end if;
end if;
when STATE_GETBYTE =>
FIFO_DataIn <= data_rd;
state_reg <= STATE_WRITEBYTE;
when STATE_WRITEBYTE =>
FIFO_WriteEn <= '1';
state_reg <= STATE_FINISHWRITE;
when STATE_FINISHWRITE =>
FIFO_WriteEn <= '0';
if (finishFlag = '1') then
state_reg <= STATE_SLEEPCHK;
else
state_reg <= STATE_FINISHREAD;
end if;
when STATE_FINISHREAD =>
finishFlag <= '1';
if (busy ='1') then
state_reg <= STATE_WAIT_RX;
end if;
when STATE_SLEEPCHK =>
ena <= '0';
if (delay = 200) then
state_reg <= STATE_WAITREADY;
else
state_reg <= STATE_SLEEPINC;
end if;
when STATE_SLEEPINC =>
delay <= delay + 1;
state_reg <= STATE_SLEEPCHK;
when others =>
state_reg <= STATE_WAITREADY;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7f2434d4e19f8cf85af3b2239d323ad8 | 0.516185 | 4.237696 | false | false | false | false |
hoangt/PoC | src/misc/sync/sync_Reset.vhdl | 2 | 3,835 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Synchronizes a reset signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes one reset signal from clock-domain 'Clock1' to
-- clock-domain 'Clock'. The clock-domain boundary crossing is done by two
-- synchronizer D-FFs. If a known vendor like Altera or Xilinx are
-- recognized, a vendor specific implementation is choosen.
--
-- ATTENTION:
-- Use this synchronizer only for reset signals.
--
-- CONSTRAINTS:
-- General:
-- Please add constraints for meta stability to all '_meta' signals and
-- timing ignore constraints to all '_async' signals.
--
-- Xilinx:
-- In case of a Xilinx device, this module will instantiate the optimized
-- module xil_SyncReset. Please attend to the notes of xil_SyncReset.
--
-- Altera sdc file:
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.sync.all;
entity sync_Reset is
port (
Clock : in STD_LOGIC; -- <Clock> output clock domain
Input : in STD_LOGIC; -- @async: reset input
Output : out STD_LOGIC -- @Clock: reset output
);
end entity;
architecture rtl of sync_Reset is
begin
genGeneric : if ((VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX)) generate
attribute ASYNC_REG : STRING;
attribute SHREG_EXTRACT : STRING;
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := '0';
signal Data_sync : STD_LOGIC := '0';
-- Mark registers as asynchronous
attribute ASYNC_REG of Data_meta : signal is "TRUE";
attribute ASYNC_REG of Data_sync : signal is "TRUE";
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of Data_meta : signal is "NO";
attribute SHREG_EXTRACT of Data_sync : signal is "NO";
begin
Data_async <= Input;
process(Clock, Input)
begin
if (Data_async = '1') then
Data_meta <= '1';
Data_sync <= '1';
elsif rising_edge(Clock) then
Data_meta <= '0';
Data_sync <= Data_meta;
end if;
end process;
Output <= Data_sync;
end generate;
-- use dedicated and optimized 2 D-FF synchronizer for Altera FPGAs
genAltera : if (VENDOR = VENDOR_ALTERA) generate
sync : sync_Reset_Altera
port map (
Clock => Clock,
Input => Input,
Output => Output
);
end generate;
-- use dedicated and optimized 2 D-FF synchronizer for Xilinx FPGAs
genXilinx : if (VENDOR = VENDOR_XILINX) generate
sync : sync_Reset_Xilinx
port map (
Clock => Clock,
Input => Input,
Output => Output
);
end generate;
end architecture;
| apache-2.0 | ed85c8ffc87c3a3e9eadef11665c7bc1 | 0.621643 | 3.617925 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/checkbit_handler.vhd | 4 | 22,860 | -------------------------------------------------------------------------------
-- checkbit_handler.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (
C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_TARGET => C_TARGET) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_FPGA: if (C_TARGET /= RTL) generate
UE_MUXF7 : MB_MUXF7
generic map (
C_TARGET => C_TARGET)
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_FPGA;
Use_RTL: if (C_TARGET = RTL) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
| gpl-3.0 | 18b6ef7fa7ba2ee325d1c2dd6d2b6346 | 0.450175 | 3.823382 | false | false | false | false |
hoangt/PoC | src/misc/sync/sync_Vector.vhdl | 2 | 5,355 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Steffen Koehler
-- Patrick Lehmann
--
-- Module: Synchronizes a signal vector across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes a vector of bits from clock-domain 'Clock1' to
-- clock-domain 'Clock2'. The clock-domain boundary crossing is done by a
-- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive
-- XOR indicating a value change on the input. This changed signal is used
-- to capture the input for the new output. A busy flag is additionally
-- calculated for the input clock domain.
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrainted. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Vector IS
generic (
MASTER_BITS : POSITIVE := 8; -- number of bit to be synchronized
SLAVE_BITS : NATURAL := 0;
INIT : STD_LOGIC_VECTOR := x"00000000" --
);
PORT (
Clock1 : in STD_LOGIC; -- <Clock> input clock
Clock2 : in STD_LOGIC; -- <Clock> output clock
Input : in STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0); -- @Clock1: input vector
Output : out STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0); -- @Clock2: output vector
Busy : out STD_LOGIC; -- @Clock1: busy bit
Changed : out STD_LOGIC -- @Clock2: changed bit
);
end;
architecture rtl of sync_Vector is
attribute SHREG_EXTRACT : STRING;
constant INIT_I : STD_LOGIC_VECTOR := descend(INIT)((MASTER_BITS + SLAVE_BITS) - 1 downto 0);
signal D0 : STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0) := INIT_I;
signal T1 : STD_LOGIC := '0';
signal D2 : STD_LOGIC := '0';
signal D3 : STD_LOGIC := '0';
signal D4 : STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0) := INIT_I;
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of D0 : signal IS "NO";
attribute SHREG_EXTRACT of T1 : signal IS "NO";
attribute SHREG_EXTRACT of D2 : signal IS "NO";
attribute SHREG_EXTRACT of D3 : signal IS "NO";
attribute SHREG_EXTRACT of D4 : signal IS "NO";
signal syncClk1_In : STD_LOGIC;
signal syncClk1_Out : STD_LOGIC;
signal syncClk2_In : STD_LOGIC;
signal syncClk2_Out : STD_LOGIC;
begin
-- input D-FF @Clock1 -> changed detection
process(Clock1)
begin
if rising_edge(Clock1) then
if (Busy_i = '0') then
D0 <= Input; -- delay input vector for change detection; gated by busy flag
T1 <= T1 xor Changed_Clk1; -- toggle T1 if input vector has changed
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
process(Clock2)
begin
if rising_edge(Clock2) then
D2 <= syncClk2_Out;
D3 <= Changed_Clk2;
if (Changed_Clk2 = '1') then
D4 <= D0;
end if;
end if;
end process;
-- assign syncClk*_In signals
syncClk2_In <= T1;
syncClk1_In <= D2;
Changed_Clk1 <='0' when (D0(MASTER_BITS - 1 downto 0) = Input(MASTER_BITS - 1 downto 0)) else '1'; -- input change detection
Changed_Clk2 <= syncClk2_Out xor D2; -- level change detection; restore strobe signal from flag
Busy_i <= T1 xor syncClk1_Out; -- calculate busy signal
-- output signals
Output <= D4;
Busy <= Busy_i;
Changed <= D3;
syncClk2 : entity PoC.sync_Bits
port map (
Clock => Clock2, -- <Clock> output clock domain
Input(0) => syncClk2_In, -- @async: input bits
Output(0) => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
port map (
Clock => Clock1, -- <Clock> output clock domain
Input(0) => syncClk1_In, -- @async: input bits
Output(0) => syncClk1_Out -- @Clock: output bits
);
end; | apache-2.0 | d6ad749c4bb549013e74dce0ebdb92fd | 0.594771 | 3.332296 | false | false | false | false |
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