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AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/srl_fifo.vhd | 4 | 9,004 | -------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2001-06-12 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added support for depth 32
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture IMP of SRL_FIFO is
constant C_ADDR_BITS : integer := 4 + boolean'pos(C_DEPTH = 32);
signal Addr : std_logic_vector(0 to C_ADDR_BITS - 1);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic := '0';
signal data_Exists_I : std_logic := '0';
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal sum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal addr_cy : std_logic_vector(0 to C_ADDR_BITS - 1);
begin -- architecture IMP
assert (C_DEPTH = 16) or (C_DEPTH = 32) report "SRL FIFO: C_DEPTH must be 16 or 32" severity FAILURE;
buffer_Full <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '1')) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '0')) else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to C_ADDR_BITS - 1 generate
begin
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(C_ADDR_BITS) is not used anywhere
Used_MuxCY: if I < C_ADDR_BITS - 1 generate
begin
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS - 1 generate
begin
D16 : if C_DEPTH = 16 generate
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D16;
D32 : if C_DEPTH = 32 generate
begin
SRLC32E_I : SRLC32E
-- pragma translate_off
generic map (
INIT => x"00000000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
CLK => Clk, -- [in std_logic]
A(4) => Addr(4), -- [in std_logic]
A(3) => Addr(3), -- [in std_logic]
A(2) => Addr(2), -- [in std_logic]
A(1) => Addr(1), -- [in std_logic]
A(0) => Addr(0), -- [in std_logic]
Q31 => open, -- [out std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D32;
end generate FIFO_RAM;
end architecture IMP;
| gpl-3.0 | badfd3c979f5caa363bcfe2c2c1f16ac | 0.511217 | 3.947391 | false | false | false | false |
hoangt/PoC | src/xil/xil_ChipScopeICON.vhdl | 2 | 7,863 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic Xilinx ChipScope ICON wrapper
--
-- Description:
-- ------------------------------------
-- This module wraps 15 ChipScope ICON IPCore netlists generated from ChipScope
-- ICON xco files. The generic parameter PORTS selects the apropriate ICON
-- instance with 1 to 15 ICON ControlBus ports. Each ControlBus port is of type
-- T_XIL_CHIPSCOPE_CONTROL and of mode 'inout'.
--
-- PoC IPCore compiler:
-- ------------------------------------
-- Please use the provided PoC netlist compiler tool to recreate the needed source
-- and netlist files on your computer.
--
-- cd <PoCRoot>\netlist
-- .\netlist.ps1 -rl --coregen PoC.xil.ChipScopeICON_1 --board KC705
-- [...]
-- .\netlist.ps1 -rl --coregen PoC.xil.ChipScopeICON_15 --board KC705
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.xil.all;
entity xil_ChipScopeICON is
generic (
PORTS : POSITIVE
);
port (
ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0)
);
end entity;
architecture rtl of xil_ChipScopeICON is
begin
assert (PORTS < 16) report "To many ICON control ports." severity failure;
genICON1 : if (PORTS = 1) generate
ICON : entity PoC.xil_ChipScopeICON_1
port map (
control0 => ControlBus(0)
);
end generate;
genICON2 : if (PORTS = 2) generate
ICON : entity PoC.xil_ChipScopeICON_2
port map (
control0 => ControlBus(0),
control1 => ControlBus(1)
);
end generate;
genICON3 : if (PORTS = 3) generate
ICON : entity PoC.xil_ChipScopeICON_3
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2)
);
end generate;
genICON4 : if (PORTS = 4) generate
ICON : entity PoC.xil_ChipScopeICON_4
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3)
);
end generate;
genICON5 : if (PORTS = 5) generate
ICON : entity PoC.xil_ChipScopeICON_5
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4)
);
end generate;
genICON6 : if (PORTS = 6) generate
ICON : entity PoC.xil_ChipScopeICON_6
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5)
);
end generate;
genICON7 : if (PORTS = 7) generate
ICON : entity PoC.xil_ChipScopeICON_7
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6)
);
end generate;
genICON8 : if (PORTS = 8) generate
ICON : entity PoC.xil_ChipScopeICON_8
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7)
);
end generate;
genICON9 : if (PORTS = 9) generate
ICON : entity PoC.xil_ChipScopeICON_9
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8)
);
end generate;
genICON10 : if (PORTS = 10) generate
ICON : entity PoC.xil_ChipScopeICON_10
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9)
);
end generate;
genICON11 : if (PORTS = 11) generate
ICON : entity PoC.xil_ChipScopeICON_11
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10)
);
end generate;
genICON12 : if (PORTS = 12) generate
ICON : entity PoC.xil_ChipScopeICON_12
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11)
);
end generate;
genICON13 : if (PORTS = 13) generate
ICON : entity PoC.xil_ChipScopeICON_13
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11),
control12 => ControlBus(12)
);
end generate;
genICON14 : if (PORTS = 14) generate
ICON : entity PoC.xil_ChipScopeICON_14
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11),
control12 => ControlBus(12),
control13 => ControlBus(13)
);
end generate;
genICON15 : if (PORTS = 15) generate
ICON : entity PoC.xil_ChipScopeICON_15
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11),
control12 => ControlBus(12),
control13 => ControlBus(13),
control14 => ControlBus(14)
);
end generate;
end architecture;
| apache-2.0 | a701f00d9a8fa9b29907373887447637 | 0.614905 | 3.234471 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc.vhd | 4 | 163,491 | -------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc.vhd
-- Version: v2.0
-- Description: This is the top-level design file for the AXI External
-- Memory Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 10/02/10 -- created v1.01.a version
-- ^^^^^^
-- 1. Replaced the AXI Lite IPIF interface with AXI4 lite native interface
-- 2. Replaced the AXI Slave Burst interface with AXI4 full native interface
-- 3. Reduced the core utilization to resolve CR 573074
-- ~~~~~~
-- SK 12/02/10
-- ^^^^^^
-- 1. Added NO_REG_EN_GEN section to drive all the output signals in the register
-- interface to '0' when not selected.
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-- SK 04/14/13
-- ^^^^^^
-- -- Fixed CR 723506 - Fixed issues with the signal driven X when parity is enabled.
-- -- Fixed CR 721840 - Fixed issues in linear sync flash memory mode, parameter ordering is updated
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library emc_common_v3_0;
use emc_common_v3_0.all;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_MEM0_TYPE -- Type of Memory
-- 0-> Sync SRAM
-- 1-> Async SRAM
-- 2-> Nor Flash
-- 3-> Page Mode Nor Flash
-- 4-> Cellar RAM/PSRAM
-- C_PARITY_TYPE_MEM_0 -- Type of Parity
-- 0-> No Parity
-- 1-> Odd Parity
-- 2-> Even Parity
-- C_INCLUDE_NEGEDGE_IOREGS -- Include negative edge IO registers
-- C_NUM_MASTERS -- Number of axi masters
-- C_MEM(0:3)_BASEADDR -- Memory bank (0:3) base address
-- C_MEM(0:3)_HIGHADDR -- Memory bank (0:3) high address
-- C_MEM(0:3)_WIDTH -- Memory bank (0:3) data width
-- C_MAX_MEM_WIDTH -- Maximum data width of all memory banks
--
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3) -- Support data width matching for
-- memory bank (0:3)
-- C_SYNCH_MEM_(0:3) -- Memory bank (0:3) type
-- C_SYNCH_PIPEDELAY_(0:3) -- Memory bank (0:3) synchronous pipedelay
-- C_TCEDV_PS_MEM_(0:3) -- Chip Enable to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TAVDV_PS_MEM_(0:3) -- Address Valid to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_THZCE_PS_MEM_(0:3) -- Chip Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_THZOE_PS_MEM_(0:3) -- Output Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_TWC_PS_MEM_(0:3) -- Write Cycle Time
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TWP_PS_MEM_(0:3) -- Write Enable Minimum Pulse Width
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TLZWE_PS_MEM_(0:3) -- Write Enable High to Data Bus Low
-- Impedance (Applied as Write Recovery
-- before Read)
-- C_WR_REC_TIME_MEM_0 -- Write recovery time between the write
-- -- and next consecutive read transaction
-- C_S_AXI_MEM_DWIDTH -- axi Data Bus Width
-- C_S_AXI_MEM_AWIDTH -- axi Address Width
-- C_AXI_CLK_PERIOD_PS -- axi clock period to calculate wait
-- state pulse widths.
--
--
-- Definition of Ports:
-- Memory Signals
-- mem_a -- Memory address inputs
-- mem_dq_i -- Memory Input Data Bus
-- mem_dq_o -- Memory Output Data Bus
-- mem_dq_t -- Memory Data Output Enable
-- mem_dq_parity_i -- Memory Parity Input Data Bus
-- mem_dq_parity_o -- Memory Parity Output Data Bus
-- mem_dq_parity_t -- Memory Parity Output Enable
-- mem_cen -- Memory Chip Select
-- mem_oen -- Memory Output Enable
-- mem_wen -- Memory Write Enable
-- mem_qwen -- Memory Qualified Write Enable
-- mem_ben -- Memory Byte Enables
-- mem_rpn -- Memory Reset/Power Down
-- mem_ce -- Memory chip enable
-- mem_adv_ldn -- Memory counter advance/load (=0)
-- mem_lbon -- Memory linear/interleaved burst order (=0)
-- mem_cken -- Memory clock enable (=0)
-- mem_rnw -- Memory read not write
-------------------------------------------------------------------------------
entity axi_emc is
-- Generics to be set by user
generic (
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_emc_inst";
C_AXI_CLK_PERIOD_PS : integer := 10000;
C_LFLASH_PERIOD_PS : integer := 20000;
C_LINEAR_FLASH_SYNC_BURST : integer range 0 to 1 := 0;
---- AXI REG Parameters
C_S_AXI_REG_ADDR_WIDTH : integer range 5 to 5 := 5;
C_S_AXI_REG_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_EN_REG : integer range 0 to 1 := 0;
----C_S_AXI_REG_BASEADDR : std_logic_vector := x"FFFFFFFF";
----C_S_AXI_REG_HIGHADDR : std_logic_vector := x"00000000";
---- AXI MEM Parameters
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer := 32;--8,16,32,64
C_S_AXI_MEM_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_MEM0_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM0_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM1_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM1_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM2_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM2_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM3_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM3_HIGHADDR : std_logic_vector := x"00000000";
-- EMC generics
C_INCLUDE_NEGEDGE_IOREGS : integer range 0 to 1 := 0;
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_MEM0_TYPE : integer range 0 to 5 := 0;
C_MEM1_TYPE : integer range 0 to 5 := 0;
C_MEM2_TYPE : integer range 0 to 5 := 0;
C_MEM3_TYPE : integer range 0 to 5 := 0;
C_MEM0_WIDTH : integer := 32;--8,16,32,64 allowed
C_MEM1_WIDTH : integer := 32;--8,16,32,64
C_MEM2_WIDTH : integer := 32;--8,16,32,64
C_MEM3_WIDTH : integer := 32;--8,16,32,64
C_MAX_MEM_WIDTH : integer := 32;--8,16,32,64
-- parity type of memory 0-no parity, 1-odd parity, 2-even parity
C_PARITY_TYPE_MEM_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_3 : integer range 0 to 2 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer range 0 to 1 := 0;
-- Memory read and write access times for all memory banks
C_SYNCH_PIPEDELAY_0 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_0 : integer := 15000;
C_TAVDV_PS_MEM_0 : integer := 15000;
C_TPACC_PS_FLASH_0 : integer := 25000;
C_THZCE_PS_MEM_0 : integer := 7000;
C_THZOE_PS_MEM_0 : integer := 7000;
C_TWC_PS_MEM_0 : integer := 15000;
C_TWP_PS_MEM_0 : integer := 12000;
C_TWPH_PS_MEM_0 : integer := 12000;
C_TLZWE_PS_MEM_0 : integer := 0;
C_WR_REC_TIME_MEM_0 : integer := 270000000;
C_SYNCH_PIPEDELAY_1 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_1 : integer := 15000;
C_TAVDV_PS_MEM_1 : integer := 15000;
C_TPACC_PS_FLASH_1 : integer := 25000;
C_THZCE_PS_MEM_1 : integer := 7000;
C_THZOE_PS_MEM_1 : integer := 7000;
C_TWC_PS_MEM_1 : integer := 15000;
C_TWP_PS_MEM_1 : integer := 12000;
C_TWPH_PS_MEM_1 : integer := 12000;
C_TLZWE_PS_MEM_1 : integer := 0;
C_WR_REC_TIME_MEM_1 : integer := 270000000;
C_SYNCH_PIPEDELAY_2 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_2 : integer := 15000;
C_TAVDV_PS_MEM_2 : integer := 15000;
C_TPACC_PS_FLASH_2 : integer := 25000;
C_THZCE_PS_MEM_2 : integer := 7000;
C_THZOE_PS_MEM_2 : integer := 7000;
C_TWC_PS_MEM_2 : integer := 15000;
C_TWP_PS_MEM_2 : integer := 12000;
C_TWPH_PS_MEM_2 : integer := 12000;
C_TLZWE_PS_MEM_2 : integer := 0;
C_WR_REC_TIME_MEM_2 : integer := 270000000;
C_SYNCH_PIPEDELAY_3 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_3 : integer := 15000;
C_TAVDV_PS_MEM_3 : integer := 15000;
C_TPACC_PS_FLASH_3 : integer := 25000;
C_THZCE_PS_MEM_3 : integer := 7000;
C_THZOE_PS_MEM_3 : integer := 7000;
C_TWC_PS_MEM_3 : integer := 15000;
C_TWP_PS_MEM_3 : integer := 12000;
C_TWPH_PS_MEM_3 : integer := 12000;
C_TLZWE_PS_MEM_3 : integer := 0 ;
C_WR_REC_TIME_MEM_3 : integer := 270000000
);
port (
-- -- AXI Slave signals ------------------------------------------------------
-- AXI Global System Signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
rdclk : in std_logic;
-- axi lite interface
-- -- axi write address Channel Signals
s_axi_reg_awaddr : in std_logic_vector
(4 downto 0);
s_axi_reg_awvalid : in std_logic;
s_axi_reg_awready : out std_logic;
-- -- axi write channel Signals
s_axi_reg_wdata : in std_logic_vector
(31 downto 0);
s_axi_reg_wstrb : in std_logic_vector
(3 downto 0);
s_axi_reg_wvalid : in std_logic;
s_axi_reg_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_reg_bresp : out std_logic_vector(1 downto 0);
s_axi_reg_bvalid : out std_logic;
s_axi_reg_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_reg_araddr : in std_logic_vector
(4 downto 0);
s_axi_reg_arvalid : in std_logic;
s_axi_reg_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_reg_rdata : out std_logic_vector
(31 downto 0);
s_axi_reg_rresp : out std_logic_vector(1 downto 0);
s_axi_reg_rvalid : out std_logic;
s_axi_reg_rready : in std_logic;
-- -- axi full interface
-- -- axi write address Channel Signals
s_axi_mem_awid : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_awaddr : in std_logic_vector(31 downto 0);
s_axi_mem_awlen : in std_logic_vector(7 downto 0);
s_axi_mem_awsize : in std_logic_vector(2 downto 0);
s_axi_mem_awburst : in std_logic_vector(1 downto 0);
s_axi_mem_awlock : in std_logic;
s_axi_mem_awcache : in std_logic_vector(3 downto 0);
s_axi_mem_awprot : in std_logic_vector(2 downto 0);
s_axi_mem_awvalid : in std_logic;
s_axi_mem_awready : out std_logic;
-- -- axi write channel Signals
s_axi_mem_wdata : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
s_axi_mem_wstrb : in std_logic_vector
(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
s_axi_mem_wlast : in std_logic;
s_axi_mem_wvalid : in std_logic;
s_axi_mem_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_mem_bid : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_bresp : out std_logic_vector(1 downto 0);
s_axi_mem_bvalid : out std_logic;
s_axi_mem_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_mem_arid : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1) downto 0);
s_axi_mem_araddr : in std_logic_vector(31 downto 0);
s_axi_mem_arlen : in std_logic_vector(7 downto 0);
s_axi_mem_arsize : in std_logic_vector(2 downto 0);
s_axi_mem_arburst : in std_logic_vector(1 downto 0);
s_axi_mem_arlock : in std_logic;
s_axi_mem_arcache : in std_logic_vector(3 downto 0);
s_axi_mem_arprot : in std_logic_vector(2 downto 0);
s_axi_mem_arvalid : in std_logic;
s_axi_mem_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_mem_rid : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_rdata : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
s_axi_mem_rresp : out std_logic_vector(1 downto 0);
s_axi_mem_rlast : out std_logic;
s_axi_mem_rvalid : out std_logic;
s_axi_mem_rready : in std_logic;
-- memory signals
mem_dq_i : in std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_o : out std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_t : out std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_parity_i : in std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_dq_parity_o : out std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_dq_parity_t : out std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_a : out std_logic_vector(31 downto 0);
-- chip selects
mem_ce : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
mem_cen : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-- read enable
mem_oen : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-- write enable
mem_wen : out std_logic;-- write enable
-- byte enables
mem_ben : out std_logic_vector((C_MAX_MEM_WIDTH/8-1) downto 0);
mem_qwen : out std_logic_vector((C_MAX_MEM_WIDTH/8-1) downto 0);
-- reset or power down
mem_rpn : out std_logic;
-- address valid active low
mem_adv_ldn : out std_logic;
-- interleaved burst order
mem_lbon : out std_logic;
-- clock enable
mem_cken : out std_logic;
-- synch mem read not write signal
mem_rnw : out std_logic;
--
mem_cre : out std_logic;
mem_wait : in std_logic_vector(C_NUM_BANKS_MEM -1 downto 0)
);
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
attribute MAX_FANOUT of rdclk : signal is "10000";
-- Added attribute to FIX CR CR204317. The following attribute prevent
-- the tools from optimizing the tristate control down to a single
-- registered signal and to pack input, output, and tri-state registers
-- into the IOB.
attribute EQUIVALENT_REGISTER_REMOVAL : string;
attribute EQUIVALENT_REGISTER_REMOVAL of Mem_DQ_T: signal is "no";
attribute EQUIVALENT_REGISTER_REMOVAL of MEM_DQ_PARITY_T: signal is "no";
-- SIGIS attribute for specifying clocks,interrrupts,resets for EDK
attribute SIGIS : string;
attribute SIGIS of s_axi_aclk : signal is "Clk" ;
attribute SIGIS of s_axi_aresetn : signal is "Rst" ;
attribute SIGIS of rdclk : signal is "Clk" ;
-- Minimum size attribute for EDK
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_S_AXI_MEM0_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM1_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM2_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM3_BASEADDR : constant is "0x08";
-- Assignment attribute for EDK
attribute ASSIGNMENT : string;
attribute ASSIGNMENT of C_S_AXI_MEM0_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM0_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM1_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM1_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM2_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM2_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM3_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM3_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM_ADDR_WIDTH : constant is "CONSTANT";
-- ADDR_TYPE attribute for EDK
attribute ADDR_TYPE : string;
attribute ADDR_TYPE of C_S_AXI_MEM0_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM0_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM1_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM1_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM2_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM2_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM3_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM3_HIGHADDR : constant is "MEMORY";
------------------------------------------------------------------------------
-- end of PSFUtil MPD attributes
------------------------------------------------------------------------------
end axi_emc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_emc is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
--constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_emc,{"
-- & "c_family=" & C_FAMILY
-- & ",c_instance=" & C_INSTANCE
-- & ",c_axi_clk_period_ps=" & integer'image(C_AXI_CLK_PERIOD_PS)
-- & ",c_lflash_period_ps=" & integer'image(C_LFLASH_PERIOD_PS)
-- & ",c_linear_flash_sync_burst=" & integer'image(C_LINEAR_FLASH_SYNC_BURST)
-- & ",c_s_axireg_addr_width=" & integer'image(C_S_AXI_REG_ADDR_WIDTH)
-- & ",c_s_axi_reg_data_width=" & integer'image(C_S_AXI_REG_DATA_WIDTH)
-- & ",c_s_axi_en_reg=" & integer'image(C_S_AXI_EN_REG)
-- & ",c_s_axi_mem_addr_width=" & integer'image(C_S_AXI_MEM_ADDR_WIDTH)
-- & ",c_s_axi_mem_data_width=" & integer'image(C_S_AXI_MEM_DATA_WIDTH)
-- & ",c_s_axi_mem_id_width=" & integer'image(C_S_AXI_MEM_ID_WIDTH)
-- & ",c_include_negedge_ioregs=" & integer'image(C_INCLUDE_NEGEDGE_IOREGS)
-- & ",c_num_banks_mem=" & integer'image(C_NUM_BANKS_MEM)
-- & ",c_mem0_type=" & integer'image(C_MEM0_TYPE)
-- & ",c_mem1_type=" & integer'image(C_MEM1_TYPE)
-- & ",c_mem2_type=" & integer'image(C_MEM2_TYPE)
-- & ",c_mem3_type=" & integer'image(C_MEM3_TYPE)
-- & ",c_mem0_width=" & integer'image(C_MEM0_WIDTH)
-- & ",c_mem1_width=" & integer'image(C_MEM1_WIDTH)
-- & ",c_mem2_width=" & integer'image(C_MEM2_WIDTH)
-- & ",c_mem3_width=" & integer'image(C_MEM3_WIDTH)
-- & ",c_max_mem_width=" & integer'image(C_MAX_MEM_WIDTH)
-- & ",c_parity_type_mem_0=" & integer'image(C_PARITY_TYPE_MEM_0)
-- & ",c_parity_type_mem_1=" & integer'image(C_PARITY_TYPE_MEM_1)
-- & ",c_parity_type_mem_2=" & integer'image(C_PARITY_TYPE_MEM_2)
-- & ",c_parity_type_mem_3=" & integer'image(C_PARITY_TYPE_MEM_3)
-- & ",c_include_datawidth_matching_0=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_0)
-- & ",c_include_datawidth_matching_1=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_1)
-- & ",c_include_datawidth_matching_2=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_2)
-- & ",c_include_datawidth_matching_3=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_3)
-- & ",c_synch_pipedelay_0=" & integer'image(C_SYNCH_PIPEDELAY_0)
-- & ",c_synch_pipedelay_1=" & integer'image(C_SYNCH_PIPEDELAY_1)
-- & ",c_synch_pipedelay_2=" & integer'image(C_SYNCH_PIPEDELAY_2)
-- & ",c_synch_pipedelay_3=" & integer'image(C_SYNCH_PIPEDELAY_3)
-- & ",c_tcedv_ps_mem_0=" & integer'image(C_TCEDV_PS_MEM_0)
-- & ",c_tcedv_ps_mem_1=" & integer'image(C_TCEDV_PS_MEM_1)
-- & ",c_tcedv_ps_mem_2=" & integer'image(C_TCEDV_PS_MEM_2)
-- & ",c_tcedv_ps_mem_=3" & integer'image(C_TCEDV_PS_MEM_3)
-- & ",c_tavdv_ps_mem_0=" & integer'image(C_TAVDV_PS_MEM_0)
-- & ",c_tavdv_ps_mem_1=" & integer'image(C_TAVDV_PS_MEM_1)
-- & ",c_tavdv_ps_mem_2=" & integer'image(C_TAVDV_PS_MEM_2)
-- & ",c_tavdv_ps_mem_3=" & integer'image(C_TAVDV_PS_MEM_3)
-- & ",c_tpacc_ps_flash_0=" & integer'image(C_TPACC_PS_FLASH_0)
-- & ",c_tpacc_ps_flash_1=" & integer'image(C_TPACC_PS_FLASH_1)
-- & ",c_tpacc_ps_flash_2=" & integer'image(C_TPACC_PS_FLASH_2)
-- & ",c_tpacc_ps_flash_3=" & integer'image(C_TPACC_PS_FLASH_3)
-- & ",c_thzce_ps_mem_0=" & integer'image(C_THZCE_PS_MEM_0)
-- & ",c_thzce_ps_mem_1=" & integer'image(C_THZCE_PS_MEM_1)
-- & ",c_thzce_ps_mem_2=" & integer'image(C_THZCE_PS_MEM_2)
-- & ",c_thzce_ps_mem_3=" & integer'image(C_THZCE_PS_MEM_3)
-- & ",c_thzoe_ps_mem_0=" & integer'image(C_THZOE_PS_MEM_0)
-- & ",c_thzoe_ps_mem_1=" & integer'image(C_THZOE_PS_MEM_1)
-- & ",c_thzoe_ps_mem_2=" & integer'image(C_THZOE_PS_MEM_2)
-- & ",c_thzoe_ps_mem_3=" & integer'image(C_THZOE_PS_MEM_3)
-- & ",c_twc_ps_mem_0=" & integer'image(C_TWC_PS_MEM_0)
-- & ",c_twc_ps_mem_1=" & integer'image(C_TWC_PS_MEM_1)
-- & ",c_twc_ps_mem_2=" & integer'image(C_TWC_PS_MEM_2)
-- & ",c_twc_ps_mem_3=" & integer'image(C_TWC_PS_MEM_3)
-- & ",c_twp_ps_mem_0=" & integer'image(C_TWP_PS_MEM_0)
-- & ",c_twp_ps_mem_1=" & integer'image(C_TWP_PS_MEM_1)
-- & ",c_twp_ps_mem_2=" & integer'image(C_TWP_PS_MEM_2)
-- & ",c_twp_ps_mem_3=" & integer'image(C_TWP_PS_MEM_3)
-- & ",c_twph_ps_mem_0=" & integer'image(C_TWPH_PS_MEM_0)
-- & ",c_twph_ps_mem_1=" & integer'image(C_TWPH_PS_MEM_1)
-- & ",c_twph_ps_mem_2=" & integer'image(C_TWPH_PS_MEM_2)
-- & ",c_twph_ps_mem_3=" & integer'image(C_TWPH_PS_MEM_3)
-- & ",c_tlzwe_ps_mem_0=" & integer'image(C_TLZWE_PS_MEM_0)
-- & ",c_tlzwe_ps_mem_1=" & integer'image(C_TLZWE_PS_MEM_1)
-- & ",c_tlzwe_ps_mem_2=" & integer'image(C_TLZWE_PS_MEM_2)
-- & ",c_tlzwe_ps_mem_3=" & integer'image(C_TLZWE_PS_MEM_3)
-- & ",c_wr_rec_time_mem_0=" & integer'image(C_WR_REC_TIME_MEM_0)
-- & ",c_wr_rec_time_mem_1=" & integer'image(C_WR_REC_TIME_MEM_1)
-- & ",c_wr_rec_time_mem_2=" & integer'image(C_WR_REC_TIME_MEM_2)
-- & ",c_wr_rec_time_mem_3=" & integer'image(C_WR_REC_TIME_MEM_3)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of implementation : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- addresses for axi_slave_burst are 64-bits wide - create constants to
-- zero the most significant address bits
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_MEM_ADDR_WIDTH-1)
:= (others => '0');
-- four banks with SRAM, ASYNC SRAM, PSRAM, Cellular RAM, Flash memory
type MEM_TYPE_ARRAY_TYPE is array (0 to 3) of integer range 0 to 5;
type MEM_PARITY_ARRAY_TYPE is array (0 to 3) of integer range 0 to 2;
-----------------------------------------------------------------------------
-- Function: get_AXI_ARD_ADDR_RANGE_ARRAY
-- Purpose: Fill AXI_ARD_ADDR_RANGE_ARRAY based on input parameters
-----------------------------------------------------------------------------
function get_AXI_ARD_ADDR_RANGE_ARRAY return SLV64_ARRAY_TYPE is
variable axi_ard_addr_range_array_v : SLV64_ARRAY_TYPE
(0 to C_NUM_BANKS_MEM*2-1);
begin
if (C_NUM_BANKS_MEM = 1) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
elsif (C_NUM_BANKS_MEM = 2) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
elsif (C_NUM_BANKS_MEM = 3) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
axi_ard_addr_range_array_v(4) := ZERO_ADDR_PAD&C_S_AXI_MEM2_BASEADDR;
axi_ard_addr_range_array_v(5) := ZERO_ADDR_PAD&C_S_AXI_MEM2_HIGHADDR;
else
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
axi_ard_addr_range_array_v(4) := ZERO_ADDR_PAD&C_S_AXI_MEM2_BASEADDR;
axi_ard_addr_range_array_v(5) := ZERO_ADDR_PAD&C_S_AXI_MEM2_HIGHADDR;
axi_ard_addr_range_array_v(6) := ZERO_ADDR_PAD&C_S_AXI_MEM3_BASEADDR;
axi_ard_addr_range_array_v(7) := ZERO_ADDR_PAD&C_S_AXI_MEM3_HIGHADDR;
end if;
return axi_ard_addr_range_array_v;
end function get_AXI_ARD_ADDR_RANGE_ARRAY;
constant AXI_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= get_AXI_ARD_ADDR_RANGE_ARRAY;
-----------------------------------------------------------------------------
-- Function: get_axi_ard_num_ce_array
-- Purpose: Fill AXI_NUM_CE_ARRAY based on input parameters
-----------------------------------------------------------------------------
function get_axi_ard_num_ce_array return INTEGER_ARRAY_TYPE is
variable axi_ard_num_ce_array_v : INTEGER_ARRAY_TYPE(0 to C_NUM_BANKS_MEM-1);
begin
if (C_NUM_BANKS_MEM = 1) then
axi_ard_num_ce_array_v(0) := 1; -- memories have only 1 CE
elsif (C_NUM_BANKS_MEM = 2) then
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
elsif (C_NUM_BANKS_MEM = 3) then
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
axi_ard_num_ce_array_v(2) := 1;
else
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
axi_ard_num_ce_array_v(2) := 1;
axi_ard_num_ce_array_v(3) := 1;
end if;
return axi_ard_num_ce_array_v;
end function get_axi_ard_num_ce_array;
-------------------------------------------------------------------------------
-- constant declaration
-----------------------
constant AXI_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= get_axi_ard_num_ce_array;
-- axi full read/write interconnect related parameters
constant C_S_AXI_MEM_SUPPORTS_WRITE : integer := 1;
constant C_S_AXI_MEM_SUPPORTS_READ : integer := 1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
--IPIC request qualifier signals
signal ip2bus_rdack : std_logic;
signal ip2bus_wrack : std_logic;
signal ip2bus_addrack : std_logic;
signal ip2bus_errack : std_logic;
-- IPIC address, data signals
signal ip2bus_data : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH-1));
signal bus2ip_addr : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal bus2ip_addr_temp : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
-- lower two bits address to generate the byte level address
signal bus2ip_addr_reg : std_logic_vector(0 to 2);
-- Bus2IP_* Signals
signal bus2ip_data : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH-1));
-- below little endian signals are for data & BE swapping
signal temp_bus2ip_data : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal temp_ip2bus_data : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal temp_bus2ip_be : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
--
signal bus2ip_rnw : std_logic;
signal bus2ip_rdreq_i : std_logic;
signal bus2ip_wrreq_i : std_logic;
--
signal bus2ip_cs_i : std_logic;
----
signal bus2ip_cs : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
-- big endian bus2ip_cs is used for EMC to maintain its big-endian structure
----
signal temp_bus2ip_cs : std_logic_vector
(((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
----
signal bus2ip_rdce : std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
--
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH/8)-1);
signal bus2ip_burst : std_logic;
-- External memory signals
signal mem_dq_o_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_i_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_t_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_parity_o_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_dq_parity_t_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_dq_parity_i_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
--
signal parity_error_adrss : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal parity_error_MEM : std_logic_vector(1 downto 0);
signal err_parity_bits : std_logic_vector(2 downto 0);
--
signal mem_cen_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_oen_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_wen_i : std_logic;
signal mem_qwen_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_ben_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_adv_ldn_i : std_logic;
signal mem_cken_i : std_logic;
signal mem_ce_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_a_i : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal bus2ip_burstlength : std_logic_vector(0 to 7);
signal Type_of_xfer : std_logic;
signal psram_page_mode : std_logic;
signal bus2ip_reset : std_logic;
signal temp_single_0 : std_logic;
signal temp_single_1 : std_logic;
signal temp_single_2 : std_logic;
signal or_reduced_rdce_d1 : std_logic;
signal or_reduced_wrce : std_logic;
signal bus2ip_wrreq_reg : std_logic;
signal original_wrce : std_logic;
signal Bus2IP_RdReq_emc : std_logic;
signal Bus2IP_WrReq_emc : std_logic;
signal synch_mem, last_addr1 : std_logic;
signal axi_trans_size_reg_int : std_logic_vector(1 downto 0); -- 1/3/2013
signal axi_lite_ip2bus_wrack_d1: std_logic;
signal axi_arsize : std_logic_vector(2 downto 0) := (OTHERS => '0');
--*
--**
-------------------------------------------------------------------------------
-- not_all_psram: checks if any of the memory is of PSRAM type. PSRAM is assigned
---------------- with value 4, so check if MEM_TYPE = 4 and return 0 or 1.
function not_all_psram(input_array : MEM_TYPE_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 4 := 0;
begin
for i in 0 to num_real_elements -1 loop
if input_array(i) = 4 then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_psram;
-------------------------------------------------------------------------------
-- not_all_parity : check if any of the memory is assigned with PARITY bit
------------------ if any of the memory is assigned with parity, return 1.
function not_all_parity(input_array : MEM_PARITY_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 4 := 0;
begin
for i in 0 to num_real_elements -1 loop
if input_array(i) /= 0 then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_parity;
-------------------------------------------------------------------------------
-- sync_get_val: Check if the memory is SYNC memory type, if yes return 1.
---------------
function sync_get_val(x: integer; y: integer) return integer is
begin
if x = 0 then
return 1;
else
return 0;
end if;
end function sync_get_val;
-------------------------------------------------------------------------------
-- page_get_val: If Page Mode Flash or PSRAM, then return 1.
---------------
function page_get_val(x: integer) return integer is
begin
if x = 3 or x = 4 then
return 1;
else
return 0;
end if;
end function page_get_val;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- psram_or_lflash_sync: If PSRAM or Linear Flash sync burst, then return 1.
---------------
function psram_or_lflash_sync(x: integer; y: integer) return integer is
begin
if ((x = 1) or (y = 1)) then
return 1;
else
return 0;
end if;
end function psram_or_lflash_sync;
-------------------------------------------------------------------------------
constant MEM_TYPE_ARRAY : MEM_TYPE_ARRAY_TYPE :=
(
C_MEM0_TYPE,
C_MEM1_TYPE,
C_MEM2_TYPE,
C_MEM3_TYPE
);
constant MEM_PARITY_ARRAY : MEM_PARITY_ARRAY_TYPE :=
(
C_PARITY_TYPE_MEM_0,
C_PARITY_TYPE_MEM_1,
C_PARITY_TYPE_MEM_2,
C_PARITY_TYPE_MEM_3
);
constant GLOBAL_PSRAM_MEM : integer range 0 to 1
:= not_all_psram(MEM_TYPE_ARRAY,
C_NUM_BANKS_MEM);
constant GLOBAL_PSRAM_FLASH_MEM : integer range 0 to 1
:= psram_or_lflash_sync(C_LINEAR_FLASH_SYNC_BURST,
GLOBAL_PSRAM_MEM);
constant GLOBAL_PARITY_MEM : integer range 0 to 1
:= not_all_parity(MEM_PARITY_ARRAY,
C_NUM_BANKS_MEM);
-- if SYNC memories are configured, then below parameter will be = 1
constant C_SYNCH_MEM_0 : integer :=sync_get_val(C_MEM0_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_1 : integer :=sync_get_val(C_MEM1_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_2 : integer :=sync_get_val(C_MEM2_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_3 : integer :=sync_get_val(C_MEM3_TYPE, C_LINEAR_FLASH_SYNC_BURST);
-- if Page Mode or PSRAM memories are configured,then below parameter will be= 1
constant C_PAGEMODE_FLASH_0 : integer :=page_get_val(C_MEM0_TYPE);
constant C_PAGEMODE_FLASH_1 : integer :=page_get_val(C_MEM1_TYPE);
constant C_PAGEMODE_FLASH_2 : integer :=page_get_val(C_MEM2_TYPE);
constant C_PAGEMODE_FLASH_3 : integer :=page_get_val(C_MEM3_TYPE);
--signal Mem_CRE_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
signal bus2ip_ce_lite_cmb : std_logic_vector(7 downto 0);
signal sync_mode : std_logic_vector(C_NUM_BANKS_MEM-1 downto 0):= (others => '0');
signal Cre_reg_en : std_logic_vector(C_NUM_BANKS_MEM-1 downto 0):= (others => '0');-- := '0';
signal Cre_reg_en_reduced : std_logic:= '0';
signal CTRL_REG : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal Linear_flash_brst_rd_flag : std_logic := '0';
signal Linear_flash_rd_data_ack: std_logic := '0';
signal mem_a_io : std_logic_vector(31 downto 0);
signal mem_wait_io : std_logic_vector(C_NUM_BANKS_MEM -1 downto 0);
signal Mem_WAIT_reg : std_logic := '0';
signal Mem_WAIT_reg_d1,
Mem_WAIT_reg_d2,
Mem_WAIT_reg_one_hot : std_logic := '0';
signal CTRL_REG_DATA: std_logic_vector(15 downto 0);
signal CTRL_REG_ADDR: std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0) := (others => '0');
signal sync_burst_data_ack : std_logic;
signal sync_data_select : std_logic;
constant FREQ_FACT_INT : integer range 0 to 15
:= (C_LFLASH_PERIOD_PS/C_AXI_CLK_PERIOD_PS);
constant FLASH_FREQ_FACTOR : std_logic_vector(3 downto 0)
:= conv_std_logic_vector(FREQ_FACT_INT - 1, 4);
signal test_rd : std_logic;
signal ADDR_PROGRAM : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_PROGRAM_D : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_SYNCH_BURST_RD : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_SYNCH_BURST_RD_D : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal Addr_select : std_logic := '0';
signal S_AXI_MEM_BVALID1 : std_logic;
signal S_AXI_MEM_WREADY1 : std_logic;
signal S_AXI_MEM_ARREADY1 : std_logic;
signal temp_strb : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0) := (others => '1');
signal temp_prog_cmd_data : std_logic_vector(15 downto 0) := X"0040";
signal Mem_WAIT_temp0 : std_logic := '0';
signal Mem_WAIT_temp1 : std_logic := '0';
signal Mem_WAIT_temp2 : std_logic := '0';
signal Mem_WAIT_temp3 : std_logic := '0';
signal Mem_WAIT_cmb_delay: std_logic := '0';
signal Parity_err_i : std_logic;
signal s_axi_reg_bvalid_i : std_logic;
signal s_axi_reg_awready_i : std_logic;
signal pr_idle, axi_sm_ns_IDLE : std_logic; -- 11-12-2012
signal mem_cre_int : std_logic;
signal mem_a_int : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
attribute IOB : string;
attribute IOB of Mem_WAIT_io : signal is "true";
attribute IOB of Mem_cre_int : signal is "true";
attribute IOB of Mem_a_int : signal is "true";
-----
begin -- architecture IMP
-----
s_axi_mem_bvalid <= S_AXI_MEM_BVALID1;
s_axi_mem_wready <= S_AXI_MEM_WREADY1;
s_axi_mem_arready <= S_AXI_MEM_ARREADY1;
-- EMC memory read/write access times assignments
-- CMD_ADDR_LOGIC_LFLASH : if (C_LINEAR_FLASH_SYNC_BURST = 1) generate
-- Mem_A <= mem_a_i when Cre_reg_en = '0' else CTRL_REG_ADDR ;
-- end generate CMD_ADDR_LOGIC_LFLASH;
-- ADDR_LOGIC_NO_LFLASH : if (C_LINEAR_FLASH_SYNC_BURST = 0) generate
mem_a_io <= ADDR_PROGRAM when Addr_select = '1' else
ADDR_SYNCH_BURST_RD when Linear_flash_brst_rd_flag = '1' else mem_a_i ;
-- end generate ADDR_LOGIC_NO_LFLASH;
mem_wen <= mem_wen_i ;
mem_adv_ldn <= mem_adv_ldn_i;
mem_cken <= mem_cken_i ;
err_parity_bits <= parity_error_MEM & Parity_err_i;
--axi_arsize <= S_AXI_MEM_ARSIZE when (S_AXI_MEM_ARVALID = '1' and S_AXI_MEM_ARREADY1 = '1') else axi_arsize;
mem_a <= mem_a_int;
mem_cre <= mem_cre_int;
INPUT_MEM_A_REG_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
mem_a_int <= mem_a_io;
end if;
end process INPUT_MEM_A_REG_PROCESS;
INPUT_MEM_WAIT_REG_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_io(C_NUM_BANKS_MEM -1 downto 0) <= Mem_WAIT(C_NUM_BANKS_MEM -1 downto 0);
end if;
end process INPUT_MEM_WAIT_REG_PROCESS;
process (s_axi_aclk) begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if S_AXI_MEM_ARVALID = '1' and S_AXI_MEM_ARREADY1 = '1' then
axi_arsize <= S_AXI_MEM_ARSIZE;
else
axi_arsize <= axi_arsize;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- AXI EMC is little endian and EMC COMMON is still big endian, to make
-- this interface work normally, we need to swap the Write and read data
-- bytes comming from and going to external memory interface
---------------------------------------------------------------------------
ENDIAN_CEN_BANKS_1 : if (C_NUM_BANKS_MEM = 1) generate
mem_cen(0) <= mem_cen_i(0);
mem_ce(0) <= mem_ce_i(0);
end generate ENDIAN_CEN_BANKS_1;
ENDIAN_CEN_BANKS_2 : if (C_NUM_BANKS_MEM = 2) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
end generate ENDIAN_CEN_BANKS_2;
ENDIAN_CEN_BANKS_3 : if (C_NUM_BANKS_MEM = 3) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_cen(2) <= mem_cen_i(2);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
mem_ce(2) <= mem_ce_i(2);
end generate ENDIAN_CEN_BANKS_3;
ENDIAN_CEN_BANKS_4 : if (C_NUM_BANKS_MEM = 4) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_cen(2) <= mem_cen_i(2);
mem_cen(3) <= mem_cen_i(3);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
mem_ce(2) <= mem_ce_i(2);
mem_ce(3) <= mem_ce_i(3);
end generate ENDIAN_CEN_BANKS_4;
-- assign OutPut Enable signals (Read Enable Signals)
ENDIAN_OEN_BANKS_1 : if (C_NUM_BANKS_MEM = 1) generate
mem_oen(0) <= mem_oen_i(0);
end generate ENDIAN_OEN_BANKS_1;
ENDIAN_OEN_BANKS_2 : if (C_NUM_BANKS_MEM = 2) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
end generate ENDIAN_OEN_BANKS_2;
ENDIAN_OEN_BANKS_3 : if (C_NUM_BANKS_MEM = 3) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
mem_oen(2) <= mem_oen_i(2);
end generate ENDIAN_OEN_BANKS_3;
ENDIAN_OEN_BANKS_4 : if (C_NUM_BANKS_MEM = 4) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
mem_oen(2) <= mem_oen_i(2);
mem_oen(3) <= mem_oen_i(3);
end generate ENDIAN_OEN_BANKS_4;
-- data byte swapping for 8 bit memory
ENDIAN_MEM_CONVERSION_8 : if (C_MAX_MEM_WIDTH = 8) generate
-- output from memory core
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
-- input to memory core
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_qwen <= mem_qwen_i;
mem_ben <= mem_ben_i;
-- o/p from memory
mem_dq_parity_o <= mem_dq_parity_o_i;
mem_dq_parity_t <= mem_dq_parity_t_i;
-- i/p to memory
mem_dq_parity_i_i <= MEM_DQ_PARITY_I;
end generate ENDIAN_MEM_CONVERSION_8;
-- data byte swapping for 16 bit memory
-- ENDIAN_MEM_CONVERSION_16: byte -by -byte swapping for 16 bit memory
---------------------------
ENDIAN_MEM_CONVERSION_16 : if (C_MAX_MEM_WIDTH = 16) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
-- i/p from memory
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_dq_i_i (8 to 15) <= Mem_DQ_I (15 downto 8);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
-- parity bits from memory
mem_dq_parity_i_i(0) <= MEM_DQ_PARITY_I(0);
mem_dq_parity_i_i(1) <= MEM_DQ_PARITY_I(1);
end generate ENDIAN_MEM_CONVERSION_16;
-- data byte swapping for 32 bit memory
-- ENDIAN_MEM_CONVERSION_32: byte -by -byte swapping for 32 bit memory
ENDIAN_MEM_CONVERSION_32 : if (C_MAX_MEM_WIDTH = 32) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_o(23 downto 16) <= mem_dq_o_i (16 to 23);
mem_dq_o(31 downto 24) <= mem_dq_o_i (24 to 31);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
mem_dq_t(23 downto 16) <= mem_dq_t_i (16 to 23);
mem_dq_t(31 downto 24) <= mem_dq_t_i (24 to 31);
-- i/p from memory
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_dq_i_i (8 to 15) <= Mem_DQ_I (15 downto 8);
mem_dq_i_i (16 to 23) <= Mem_DQ_I (23 downto 16);
mem_dq_i_i (24 to 31) <= Mem_DQ_I (31 downto 24);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
mem_qwen(2) <= mem_qwen_i(2);
mem_qwen(3) <= mem_qwen_i(3);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
mem_ben(2) <= mem_ben_i(2);
mem_ben(3) <= mem_ben_i(3);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_o(2) <= mem_dq_parity_o_i(2);
mem_dq_parity_o(3) <= mem_dq_parity_o_i(3);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
mem_dq_parity_t(2) <= mem_dq_parity_t_i(2);
mem_dq_parity_t(3) <= mem_dq_parity_t_i(3);
-- parity bits from memory
mem_dq_parity_i_i(0) <= mem_dq_parity_i(0);
mem_dq_parity_i_i(1) <= mem_dq_parity_i(1);
mem_dq_parity_i_i(2) <= mem_dq_parity_i(2);
mem_dq_parity_i_i(3) <= mem_dq_parity_i(3);
end generate ENDIAN_MEM_CONVERSION_32;
-- data byte swapping for 64 bit memory
-- ENDIAN_MEM_CONVERSION_64: byte -by -byte swapping for 64 bit memory
ENDIAN_MEM_CONVERSION_64 : if (C_MAX_MEM_WIDTH = 64) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_o(23 downto 16) <= mem_dq_o_i (16 to 23);
mem_dq_o(31 downto 24) <= mem_dq_o_i (24 to 31);
mem_dq_o(39 downto 32) <= mem_dq_o_i (32 to 39);
mem_dq_o(47 downto 40) <= mem_dq_o_i (40 to 47);
mem_dq_o(55 downto 48) <= mem_dq_o_i (48 to 55);
mem_dq_o(63 downto 56) <= mem_dq_o_i (56 to 63);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
mem_dq_t(23 downto 16) <= mem_dq_t_i (16 to 23);
mem_dq_t(31 downto 24) <= mem_dq_t_i (24 to 31);
mem_dq_t(39 downto 32) <= mem_dq_t_i (32 to 39);
mem_dq_t(47 downto 40) <= mem_dq_t_i (40 to 47);
mem_dq_t(55 downto 48) <= mem_dq_t_i (48 to 55);
mem_dq_t(63 downto 56) <= mem_dq_t_i (56 to 63);
-- o/p from memory
mem_dq_i_i (0 to 7) <= mem_dq_i (7 downto 0);
mem_dq_i_i (8 to 15) <= mem_dq_i (15 downto 8);
mem_dq_i_i (16 to 23) <= mem_dq_i (23 downto 16);
mem_dq_i_i (24 to 31) <= mem_dq_i (31 downto 24);
mem_dq_i_i (32 to 39) <= mem_dq_i (39 downto 32);
mem_dq_i_i (40 to 47) <= mem_dq_i (47 downto 40);
mem_dq_i_i (48 to 55) <= mem_dq_i (55 downto 48);
mem_dq_i_i (56 to 63) <= mem_dq_i (63 downto 56);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
mem_qwen(2) <= mem_qwen_i(2);
mem_qwen(3) <= mem_qwen_i(3);
mem_qwen(4) <= mem_qwen_i(4);
mem_qwen(5) <= mem_qwen_i(5);
mem_qwen(6) <= mem_qwen_i(6);
mem_qwen(7) <= mem_qwen_i(7);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
mem_ben(2) <= mem_ben_i(2);
mem_ben(3) <= mem_ben_i(3);
mem_ben(4) <= mem_ben_i(4);
mem_ben(5) <= mem_ben_i(5);
mem_ben(6) <= mem_ben_i(6);
mem_ben(7) <= mem_ben_i(7);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_o(2) <= mem_dq_parity_o_i(2);
mem_dq_parity_o(3) <= mem_dq_parity_o_i(3);
mem_dq_parity_o(4) <= mem_dq_parity_o_i(4);
mem_dq_parity_o(5) <= mem_dq_parity_o_i(5);
mem_dq_parity_o(6) <= mem_dq_parity_o_i(6);
mem_dq_parity_o(7) <= mem_dq_parity_o_i(7);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
mem_dq_parity_t(2) <= mem_dq_parity_t_i(2);
mem_dq_parity_t(3) <= mem_dq_parity_t_i(3);
mem_dq_parity_t(4) <= mem_dq_parity_t_i(4);
mem_dq_parity_t(5) <= mem_dq_parity_t_i(5);
mem_dq_parity_t(6) <= mem_dq_parity_t_i(6);
mem_dq_parity_t(7) <= mem_dq_parity_t_i(7);
-- parity bits from memory
mem_dq_parity_i_i(0) <= mem_dq_parity_i(0);
mem_dq_parity_i_i(1) <= mem_dq_parity_i(1);
mem_dq_parity_i_i(2) <= mem_dq_parity_i(2);
mem_dq_parity_i_i(3) <= mem_dq_parity_i(3);
mem_dq_parity_i_i(4) <= mem_dq_parity_i(4);
mem_dq_parity_i_i(5) <= mem_dq_parity_i(5);
mem_dq_parity_i_i(6) <= mem_dq_parity_i(6);
mem_dq_parity_i_i(7) <= mem_dq_parity_i(7);
end generate ENDIAN_MEM_CONVERSION_64;
-------------------------------------------------------------------------------
-- NO_REG_EN_GEN: the below instantion is to make the output signals for
-- register interface driving '0'.
--------------
NO_REG_EN_GEN : if (C_S_AXI_EN_REG = 0) generate
-------------
begin
-------------------------------------
s_axi_reg_awready <= '0';
s_axi_reg_wready <= '0';
s_axi_reg_bresp <= (others => '0');
s_axi_reg_bvalid <= '0';
s_axi_reg_arready <= '0';
s_axi_reg_rdata <= (others => '0');
s_axi_reg_rresp <= (others => '0');
s_axi_reg_rvalid <= '0';
-- PSRAM_CONFIG_REG_DIS: if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
psram_page_mode <= '0';-- Default value is psram in async mode
-- end generate PSRAM_CONFIG_REG_DIS;
-------------------------------------
end generate NO_REG_EN_GEN;
-------------------------------------------------------------------------------
-- EMC REGISTER MODULE Instantiations
-------------------------------------------------------------------------------
-- REG_EN_GEN: Include the AXI Lite IPIF and register module
--------------
REG_EN_GEN : if (C_S_AXI_EN_REG = 1) generate
-------------
-- IPIC Used Sgnals
constant RST_ACTIVE : std_logic := '0';
type MEM_PARITY_REG_ARRAY_TYPE is array(3 downto 0) of
std_logic_vector((C_S_AXI_REG_DATA_WIDTH -1) downto 0);
type MEM_PSRAM_REG_ARRAY_TYPE is array(3 downto 0) of
std_logic_vector((C_S_AXI_REG_DATA_WIDTH -1) downto 0);
signal PEAR_REG : MEM_PARITY_REG_ARRAY_TYPE;-- 4 parity regs of each 32 bit
signal PCR_REG : MEM_PSRAM_REG_ARRAY_TYPE ; -- 4 psram regs of each 32 bit
signal axi_lite_ip2bus_data_i : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal axi_lite_ip2bus_data1 : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal axi_lite_ip2bus_data2 : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal bus2ip_addr_lite_reg : std_logic_vector(4 downto 2);--((3+GLOBAL_PSRAM_FLASH_MEM)
-- downto 2);
signal arready_i : std_logic;
signal awready_i : std_logic;
signal rvalid : std_logic;
signal axi_lite_ip2bus_wrack_i : std_logic;
signal axi_lite_ip2bus_rdack_i : std_logic;
signal axi_lite_ip2bus_rdack1 : std_logic;
signal axi_lite_ip2bus_rdack2 : std_logic;
signal axi_lite_ip2bus_wrack1 : std_logic;
signal axi_lite_ip2bus_wrack2 : std_logic;
signal read_reg_req : std_logic;
signal write_reg_req : std_logic;
signal bus2ip_rdce_lite_cmb : std_logic_vector(7 downto 0);-- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM)) downto 0);
signal bus2ip_wrce_lite_cmb : std_logic_vector(7 downto 0);-- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM)) downto 0);
signal s_axi_reg_rresp_reg: std_logic_vector(1 downto 0);
signal s_axi_reg_bresp_reg: std_logic_vector(1 downto 0);
signal s_axi_reg_bvalid_i : std_logic;
------------------------
-----
begin
-------------------------------------------------------------------------------
-- *
-------------------------------------------------------------------------------
PSRAM_FLASH_PARITY_CE_LOCAL_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 1)generate
-------------------------------
--signal bus2ip_ce_lite_cmb : std_logic_vector(7 downto 0);
-----
begin-- *
-----
--* to generate the WRCE and RDCE for register access.
PSRAM_PARITY_NUM_BANKS_4_GEN: if (C_NUM_BANKS_MEM=4) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
when "000" => bus2ip_ce_lite_cmb <= "00000001";
when "001" => bus2ip_ce_lite_cmb <= "00000010";
when "010" => bus2ip_ce_lite_cmb <= "00000100";
when "011" => bus2ip_ce_lite_cmb <= "00001000";
when "100" => bus2ip_ce_lite_cmb <= "00010000";
when "101" => bus2ip_ce_lite_cmb <= "00100000";
when "110" => bus2ip_ce_lite_cmb <= "01000000";
when "111" => bus2ip_ce_lite_cmb <= "10000000";
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_4_GEN;
------------------------------------------
PSRAM_PARITY_NUM_BANKS_3_GEN: if (C_NUM_BANKS_MEM=3) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
-- when "000" => bus2ip_ce_lite_cmb <= "00000001";
-- when "001" => bus2ip_ce_lite_cmb <= "00000010";
-- when "010" => bus2ip_ce_lite_cmb <= "00000100";
-- when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
-- -- psram configuration registers
-- when "100" => bus2ip_ce_lite_cmb <= "00010000";
-- when "101" => bus2ip_ce_lite_cmb <= "00100000";
-- when "110" => bus2ip_ce_lite_cmb <= "01000000";
-- -- coverage off
-- when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- -- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
-- end if;
-- end if;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_3_GEN;
------------------------------------------
PSRAM_PARITY_NUM_BANKS_2_GEN: if (C_NUM_BANKS_MEM=2) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
--when "000" => bus2ip_ce_lite_cmb <= "00000001";
--when "001" => bus2ip_ce_lite_cmb <= "00000010";
--when "010" => bus2ip_ce_lite_cmb <= "00000100"; -- this will complete the transaction without any updates
--when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
---- psram configuration registers
--when "100" => bus2ip_ce_lite_cmb <= "00010000";
--when "101" => bus2ip_ce_lite_cmb <= "00100000";
--when "110" => bus2ip_ce_lite_cmb <= "01000000"; -- this will complete the transaction without any updates
--when "111" => bus2ip_ce_lite_cmb <= "10000000"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= (others=> '0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- REGISTER HOLE - provide only ack
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- REGISTER HOLE - provide only ack
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_2_GEN;
PSRAM_PARITY_NUM_BANKS_1_GEN: if (C_NUM_BANKS_MEM=1) generate
begin
BUS2IP_CE_GEN_P: process--(s_axi_aclk) is
(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
--when "000" => bus2ip_ce_lite_cmb <= "00000001";
--when "001" => bus2ip_ce_lite_cmb <= "00000010";-- this will complete the transaction without any updates
--when "010" => bus2ip_ce_lite_cmb <= "00000100";-- this will complete the transaction without any updates
--when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
-- psram configuration registers
--when "100" => bus2ip_ce_lite_cmb <= "00010000";
--when "101" => bus2ip_ce_lite_cmb <= "00100000"; -- this will complete the transaction without any updates
--when "110" => bus2ip_ce_lite_cmb <= "01000000"; -- this will complete the transaction without any updates
--when "111" => bus2ip_ce_lite_cmb <= "10000000"; -- this will complete the transaction without any updates
-- coverage off
--when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- REGISTER HOLE - provide only ack
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- REGISTER HOLE - provide only ack
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- REGISTER HOLE - provide only ack
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- REGISTER HOLE - provide only ack
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_1_GEN;
end generate PSRAM_FLASH_PARITY_CE_LOCAL_REG_GEN;
-------------------------------------------------------------------------------
NO_LFLASH_PSRAM_CE_LOCAL_REG_GEN: if (GLOBAL_PSRAM_FLASH_MEM = 0)generate
-----
begin-- *
-----
--* to generate the WRCE and RDCE for register access.
NUM_BANKS_4_GEN: if (C_NUM_BANKS_MEM=4) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);--9/14/2013
-----
begin
-----
BUS2IP_CE_GEN_P: process
(
bus2ip_addr_lite_reg(4 downto 2) -- (3 downto 2)
) is
--------
--variable bus2ip_addr_reg_3_2 : std_logic_vector(1 downto 0);
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "0001";
--when "01" => bus2ip_ce_lite_cmb <= "0010";
--when "10" => bus2ip_ce_lite_cmb <= "0100";
--when "11" => bus2ip_ce_lite_cmb <= "1000";
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "0001";--(others => '0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen, else hole
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- bank 3 present if SRAM is chosen, else hole
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen, else hole
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- bank 3 present if PSRAM/Flash is chosen, else hole
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate --C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_4_GEN;
------------------------------------------
NUM_BANKS_3_GEN: if (C_NUM_BANKS_MEM=3) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)-- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "001";
--when "01" => bus2ip_ce_lite_cmb <= "010";
--when "10" => bus2ip_ce_lite_cmb <= "100";
--when "11" => bus2ip_ce_lite_cmb <= "001"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "001";--(others=>'0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen, else hole
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen, else hole
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_3_GEN;
------------------------------------------
NUM_BANKS_2_GEN: if (C_NUM_BANKS_MEM=2) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)-- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "01";
--when "01" => bus2ip_ce_lite_cmb <= "10";
--when "10" => bus2ip_ce_lite_cmb <= "01"; -- this will complete the transaction without any updates
--when "11" => bus2ip_ce_lite_cmb <= "01"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "01";-- (others=>'0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- hole, provide ack in any case
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- hole, provide ack in any case
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_2_GEN;
------------------------------------------
NUM_BANKS_1_GEN: if (C_NUM_BANKS_MEM=1) generate
--signal bus2ip_ce_lite_cmb : std_logic;
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2) -- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= '1';
--when "01" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
--when "10" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
--when "11" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= '1';-- '0';
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- hole, provide ack in any case
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- hole, provide ack in any case
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- hole, provide ack in any case
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- hole, provide ack in any case
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_1_GEN;
--------------------------------------
end generate NO_LFLASH_PSRAM_CE_LOCAL_REG_GEN;
--*
s_axi_reg_awready <= axi_lite_ip2bus_wrack_i; -- awready_i;
s_axi_reg_wready <= axi_lite_ip2bus_wrack_i; -- write_reg_req;
s_axi_reg_bresp <= s_axi_reg_bresp_reg;
s_axi_reg_arready <= arready_i;
s_axi_reg_rvalid <= rvalid;
s_axi_reg_rresp <= s_axi_reg_rresp_reg;
-- AWREADY is enabled only if valid write request and no read request
awready_i <= (not write_reg_req) and
not ( s_axi_reg_arvalid or read_reg_req or rvalid ) and
s_axi_aresetn;
-- ARREADY is enabled only if valid read request and no current write request
arready_i <= not(rvalid or read_reg_req) and
not (write_reg_req)
and s_axi_aresetn;
-- WRITE_AWREADY_P: process (s_axi_aclk) is
-- begin
-- if (s_axi_aclk'event and s_axi_aclk = '1') then
-- if (s_axi_aresetn=RST_ACTIVE) then
-- s_axi_reg_awready_i <= '0';
-- --elsif (s_axi_reg_awvalid = '0') and (axi_lite_ip2bus_wrack_i = '1') then
-- -- s_axi_reg_awready_i <= '1';
-- elsif (s_axi_reg_awvalid = '1') and (s_axi_reg_awready_i = '1') then
-- s_axi_reg_awready_i <= '0';
-- else
-- s_axi_reg_awready_i <= axi_lite_ip2bus_wrack_i;
-- end if;
-- end if;
-- end process WRITE_AWREADY_P;
-- ---------------------------------------------------------------------------------
-- s_axi_reg_awready <= s_axi_reg_awready_i;
-------------------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-------------------------------------------------------------------------------
READ_REQUEST_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
read_reg_req <= '0';
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
read_reg_req <= '1';
elsif (axi_lite_ip2bus_rdack_i = '1') then
read_reg_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-------------------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-------------------------------------------------------------------------------
WRITE_REQUEST_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
write_reg_req <= '0';
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
write_reg_req <= '1';
elsif (axi_lite_ip2bus_wrack_i = '1') then
write_reg_req <= '0';
end if;
end if;
end process WRITE_REQUEST_P;
-------------------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-------------------------------------------------------------------------------
PSRAM_PARITY_ADDR_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 1) generate
------------------------
-----
begin-- *
-----
ADDR_GEN_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
bus2ip_addr_lite_reg(4 downto 2) <= (others=>'0');
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_araddr(4 downto 2);
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_awaddr(4 downto 2);
end if;
end if;
end process ADDR_GEN_P;
end generate PSRAM_PARITY_ADDR_REG_GEN;
---------------------------------------
NO_PSRAM_PARITY_ADDR_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
------------------------
-----
begin-- *
-----
ADDR_GEN_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
bus2ip_addr_lite_reg(4 downto 2) <= (others=>'0');
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_araddr(4 downto 2);
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_awaddr(4 downto 2);
end if;
end if;
end process ADDR_GEN_P;
end generate NO_PSRAM_PARITY_ADDR_REG_GEN;
---------------------------------------
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_READ_OUTPUT_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
s_axi_reg_rdata <= (others =>'0');
elsif (axi_lite_ip2bus_rdack_i = '1') then
s_axi_reg_rdata <= axi_lite_ip2bus_data_i;
elsif(rvalid='0')then
s_axi_reg_rdata <= (others =>'0');
end if;
end if;
end process AXI_READ_OUTPUT_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
s_axi_reg_rresp_reg <= "00";
if (s_axi_aresetn=RST_ACTIVE) then
rvalid <= '0';
elsif (axi_lite_ip2bus_rdack_i = '1') then
rvalid <= '1';
elsif (s_axi_reg_rready='1') then
rvalid <= '0';
end if;
end if;
end process READ_RVALID_P;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
s_axi_reg_bresp_reg <= "00";
if (s_axi_aresetn=RST_ACTIVE) then
s_axi_reg_bvalid_i <= '0';
--elsif (axi_lite_ip2bus_wrack_i = '1') then
-- s_axi_reg_bvalid <= '1';
--elsif (s_axi_reg_bready='1') then
-- s_axi_reg_bvalid <= '0';
--elsif(s_axi_reg_bready='1')then
--else
--s_axi_reg_bvalid <= axi_lite_ip2bus_wrack_i;
elsif ((axi_lite_ip2bus_wrack_i and (not axi_lite_ip2bus_wrack_d1)) = '1') then
s_axi_reg_bvalid_i <= '1';
elsif (s_axi_reg_bready = '0') and (s_axi_reg_bvalid_i = '1') then
s_axi_reg_bvalid_i <= '1';
elsif (s_axi_reg_bready = '1') and (s_axi_reg_bvalid_i = '1') then
s_axi_reg_bvalid_i <= '0';
end if;
end if;
end process WRITE_BVALID_P;
LOCK_BVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
axi_lite_ip2bus_wrack_d1 <= '0';
else -- if (axi_lite_ip2bus_wrack_i = '1') then
axi_lite_ip2bus_wrack_d1 <= axi_lite_ip2bus_wrack_i;
end if;
end if;
end process LOCK_BVALID_P;
---------------------------------------------------------------------------------
s_axi_reg_bvalid <= s_axi_reg_bvalid_i;
-----------------------------------------------------------------------------
axi_lite_ip2bus_data_i <= axi_lite_ip2bus_data1 or
axi_lite_ip2bus_data2;
axi_lite_ip2bus_rdack_i <= axi_lite_ip2bus_rdack1 or
axi_lite_ip2bus_rdack2;
axi_lite_ip2bus_wrack_i <= axi_lite_ip2bus_wrack1 or
axi_lite_ip2bus_wrack2;
-----------------------------------------------------------------------------
-- PEAR_X_RD, Byte Parity Register Read Process
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
NO_PARITY_ENABLED_REG_GEN : if (MEM_PARITY_ARRAY(0) = 0 and -- if all mentioned meories are not having
MEM_PARITY_ARRAY(1) = 0 and -- parity included, then there wont be any
MEM_PARITY_ARRAY(2) = 0 and -- local registers
MEM_PARITY_ARRAY(3) = 0) generate
-----
begin
------
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= '0';
axi_lite_ip2bus_wrack1 <= '0';
end generate NO_PARITY_ENABLED_REG_GEN;
---------------------------------------
-- PEAR_X_RD : If any of the memories are having parity enabled then local register may be
-- needed. 1-odd parity, 2-even parity
--------------
PARITY_ENABLED_REG_GEN : if ( MEM_PARITY_ARRAY(0) /= 0 or -- if any of the memories are of
MEM_PARITY_ARRAY(1) /= 0 or -- having parity enables, then there
MEM_PARITY_ARRAY(2) /= 0 or -- is need of local registers
MEM_PARITY_ARRAY(3) /= 0
) generate
-----
begin
-----
-- PARITY_REG_DUMMY_WR_ACK_P : Parity registers are read only registers. write to these registers is not allowed or should come
-- out safely. Below logic generates ACK and write transactions are come out safely.
PARITY_REG_DUMMY_WR_ACK_P :process(s_axi_aclk)is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
axi_lite_ip2bus_wrack1 <= '0';
else--if(or_reduce(bus2ip_wrce_lite_cmb) = '1') then
axi_lite_ip2bus_wrack1 <= or_reduce(bus2ip_wrce_lite_cmb); -- '1';
end if;
end if;
end process PARITY_REG_DUMMY_WR_ACK_P;
----------------------------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_4_GEN: if C_NUM_BANKS_MEM = 4 generate
------------------
begin
-----
FOUR_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1),
PEAR_REG(2),
PEAR_REG(3)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0); -- 9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack(7 downto 0) is -- (3 downto 0) is
--when "0001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "0010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
--when "0100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
--when "1000" => axi_lite_ip2bus_data1 <= PEAR_REG(3);
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
when "00000100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
when "00001000" => axi_lite_ip2bus_data1 <= PEAR_REG(3);
-- hole returns data 0
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
-- coverage off
when others => axi_lite_ip2bus_data1 <= (others=> '0');
-- coverage on
end case;
end process FOUR_BANKS_PARITY_REG_RD_P;
----------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
--err_parity_bits := ip2bus_errack & parity_error_MEM;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
when "101" => PEAR_REG(2) <= parity_error_adrss;
when "111" => PEAR_REG(3) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
PEAR_REG(2) <= PEAR_REG(2);
PEAR_REG(3) <= PEAR_REG(3);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_4_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_3_GEN: if C_NUM_BANKS_MEM = 3 generate
------------------
begin
-----
THREE_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1),
PEAR_REG(2)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0);--9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
-- axi_lite_ip2bus_data1 <= (others => '0');
case internal_bus2ip_rdack(7 downto 0) is -- (2 downto 0) is
--when "001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
--when "100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
---- coverage off
--when others => null;
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
when "00000100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
-- hole returns data 0
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process THREE_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i ) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
when "101" => PEAR_REG(2) <= parity_error_adrss;
-- coverage off
when others => null; -- axi_lite_ip2bus_data1 <= (others => '0');
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
PEAR_REG(2) <= PEAR_REG(2);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_3_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_2_GEN: if C_NUM_BANKS_MEM = 2 generate
------------------
begin
-----
TWO_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0); -- 9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack(7 downto 0) is -- (1 downto 0) is
--when "01" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "10" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
---- coverage off
--when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
-- hole returns data 0
when "00000100" => axi_lite_ip2bus_data1 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process TWO_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_2_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_1_GEN: if C_NUM_BANKS_MEM = 1 generate
------------------
begin
-----
ONE_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;-- or_reduce(bus2ip_rdce_lite_cmb);
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack is
--when '1' => axi_lite_ip2bus_data1 <= PEAR_REG(0);
---- coverage off
--when others => axi_lite_ip2bus_data1 <= (others=> '0'); -- null;
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
-- hole returns data 0
when "00000010" => axi_lite_ip2bus_data1 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data1 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process ONE_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_1_GEN;
------------------------------------------------------
end generate PARITY_ENABLED_REG_GEN;
------------------------------------
-----------------------------------------------------------------------------
-- PCR_X_RD, Byte Parity Register Read Process
-----------------------------------------------------------------------------
LINEAR_FLASH_CONFIG_REG_GEN: if (C_LINEAR_FLASH_SYNC_BURST = 1) generate
--------------------
begin
-----
PCR_FOUR_GEN: if C_NUM_BANKS_MEM = 4 generate
LFLASH_CONFIG_REG_RD_PROCESS_4 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= PCR_REG(3);
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_4;
end generate PCR_FOUR_GEN;
PCR_THREE_GEN: if C_NUM_BANKS_MEM = 3 generate
LFLASH_CONFIG_REG_RD_PROCESS_3 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_3;
end generate PCR_THREE_GEN;
PCR_TWO_GEN: if C_NUM_BANKS_MEM = 2 generate
LFLASH_CONFIG_REG_RD_PROCESS_2 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_2;
end generate PCR_TWO_GEN;
PCR_ONE_GEN: if C_NUM_BANKS_MEM = 1 generate
LFLASH_CONFIG_REG_RD_PROCESS_1 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_1;
end generate PCR_ONE_GEN;
-----------------------------------------
axi_lite_ip2bus_wrack2 <= or_reduce(bus2ip_wrce_lite_cmb);-- ((C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
-----------------------------------------
LFLASH_CONFIG_REG_WR_PROCESS : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PCR_REG (i) <= X"0000_0024";
end loop;
else
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if((bus2ip_wrce_lite_cmb(4+i)='1') and
(MEM_TYPE_ARRAY(i) = 2 or MEM_TYPE_ARRAY(i) = 5 )
)then
PCR_REG(i)(31 downto 30) <= s_axi_reg_wdata(31 downto 30);
PCR_REG(i)(6 downto 0) <= s_axi_reg_wdata(6 downto 0);
else
PCR_REG(i) <= PCR_REG(i);
end if;
end loop;
end if;
end if;
end process LFLASH_CONFIG_REG_WR_PROCESS;
----------------------------------------
MEM_WAIT_TEMP_1_GEN: if C_NUM_BANKS_MEM = 1 generate
------------------
begin
-------------------------------------------------------------------------------
-- Registers the input memory wait signal.
-------------------------------------------------------------------------------
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= sync_mode(0) and
(not Cre_reg_en(0))and
temp_bus2ip_cs(0); -- 4/2/2013
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
-----------------------------------------
end generate MEM_WAIT_TEMP_1_GEN;
MEM_WAIT_TEMP_2_GEN: if C_NUM_BANKS_MEM = 2 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or Mem_WAIT_io(1) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk) is
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
----------------------------------------
end generate MEM_WAIT_TEMP_2_GEN;
MEM_WAIT_TEMP_3_GEN: if C_NUM_BANKS_MEM = 3 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or Mem_WAIT_io(1) = '1' or Mem_WAIT_io(2) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
-----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
-----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
(sync_mode(2) and (not Cre_reg_en(2)))
when (temp_bus2ip_cs(2) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
-----------------------------------------
end generate MEM_WAIT_TEMP_3_GEN;
MEM_WAIT_TEMP_4_GEN: if C_NUM_BANKS_MEM = 4 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or
Mem_WAIT_io(1) = '1' or
Mem_WAIT_io(2) = '1' or
Mem_WAIT_io(3) = '1'
)then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
(sync_mode(2) and (not Cre_reg_en(2)))
when (temp_bus2ip_cs(2) = '1')
else
(sync_mode(3) and (not Cre_reg_en(3)))
when (temp_bus2ip_cs(3) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
----------------------------------------
end generate MEM_WAIT_TEMP_4_GEN;
Linear_flash_rd_data_ack <= Mem_WAIT_reg;
WR_PROGRAM_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_select <= '0';
--ADDR_PROGRAM <= (others => '0');
elsif(S_AXI_MEM_WREADY1 = '1' and S_AXI_MEM_WVALID = '1') then
if(signed(S_AXI_MEM_WDATA(15 downto 0)) = signed(temp_prog_cmd_data)) then
ADDR_select <= '1';
-- ADDR_PROGRAM <= S_AXI_MEM_AWADDR;
end if;
elsif(S_AXI_MEM_BREADY = '1' and S_AXI_MEM_BVALID1 = '1') then
ADDR_select <= '0';
--ADDR_PROGRAM <= (others => '0');
end if;
end if;
end process WR_PROGRAM_PROCESS;
WR_PROGRAM_PROCESS_N : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_PROGRAM_D <= (others => '0');
else
ADDR_PROGRAM_D <= ADDR_PROGRAM;
end if;
end if;
end process WR_PROGRAM_PROCESS_N;
ADDR_PROGRAM <= (others => '0') when (s_axi_aresetn = '0')
else S_AXI_MEM_AWADDR when ((S_AXI_MEM_WREADY1 = '1' and S_AXI_MEM_WVALID = '1') and (signed(S_AXI_MEM_WDATA(15 downto 0)) = signed(temp_prog_cmd_data)))
else (others => '0') when (S_AXI_MEM_BREADY = '1' and S_AXI_MEM_BVALID1 = '1')
else ADDR_PROGRAM_D;
-------------------------------
BURST_RD_ADDR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_SYNCH_BURST_RD_D <= (others => '0');
elsif(S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1') then
ADDR_SYNCH_BURST_RD_D <= ADDR_SYNCH_BURST_RD;
end if;
--if (s_axi_aresetn = '0') then
-- ADDR_SYNCH_BURST_RD <= (others => '0');
--elsif(S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1') then
-- ADDR_SYNCH_BURST_RD <= S_AXI_MEM_ARADDR;
--end if;
end if;
end process BURST_RD_ADDR_PROCESS;
ADDR_SYNCH_BURST_RD <= (others => '0') when (s_axi_aresetn = '0')
else S_AXI_MEM_ARADDR when (S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1')
else ADDR_SYNCH_BURST_RD_D;
--CTRL_REG_ADDR(16 downto 1) <= CTRL_REG_DATA;
-- Linear_flash_rd_data_ack <= sync_data_select;
--Linear_flash_brst_rd_flag <= sync_mode and (not Cre_reg_en);
FLASH_SYNCH_CRE_WR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
Cre_reg_en <= (others => '0');
sync_mode <= (others => '0');
else
Cre_reg_en <= (others => '0');
sync_mode <= (others => '0');
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if(bus2ip_ce_lite_cmb(4+i) = '1' ) then
sync_mode(i) <= ( PCR_REG(i)(30));
Cre_reg_en(i) <= PCR_REG(i)(31);
end if;
end loop;
end if;
end if;
end process FLASH_SYNCH_CRE_WR_PROCESS;
end generate LINEAR_FLASH_CONFIG_REG_GEN;
--------------------------------------------------------------------------------
NO_LFLASH_PSRAM_CONFIG_REG_GEN: if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
--------------------
begin
-----
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= '0';
axi_lite_ip2bus_wrack2 <= '0'; -- 6/6/2013
psram_page_mode <= '1';-- DONT change this value
CRE_WR_PROCESS_G : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
Mem_CRE_int <= '0';
end if;
end process CRE_WR_PROCESS_G;
end generate NO_LFLASH_PSRAM_CONFIG_REG_GEN;
-------------------------------------
-- NO_PSRAM_CONFIG_REG_GEN : If any of the memories are defined with PSRAM, then there will
-- local register in the core.
----------------
PSRAM_CONFIG_REG_GEN: if (GLOBAL_PSRAM_MEM = 1) generate
--------------------
begin
-----
--SRAM_CONFIG_REG_RD_PROCESS : process (bus2ip_rdce_lite_cmb,
-- PCR_REG) is
--egin
--- defaults
--xi_lite_ip2bus_data2 <= (others => '0');
--xi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb); -- 9/14/2013 -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0));
--or i in C_NUM_BANKS_MEM-1 downto 0 loop
-- if( (bus2ip_rdce_lite_cmb(4+i)='1') and
-- (MEM_TYPE_ARRAY(i)=4 )
-- )then
-- axi_lite_ip2bus_data2 <= PCR_REG(i);
-- else -- 9/14/2013
-- axi_lite_ip2bus_data2 <= (others => '0');
-- end if;
--nd loop;
--nd process PSRAM_CONFIG_REG_RD_PROCESS;
PSRAM_ONE_GEN: if C_NUM_BANKS_MEM = 1 generate
PSRAM_CONFIG_REG_RD_PROCESS_1 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_1;
end generate PSRAM_ONE_GEN;
PSRAM_TWO_GEN: if C_NUM_BANKS_MEM = 2 generate
PSRAM_CONFIG_REG_RD_PROCESS_2 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_2;
end generate PSRAM_TWO_GEN;
PSRAM_THREE_GEN: if C_NUM_BANKS_MEM = 3 generate
PSRAM_CONFIG_REG_RD_PROCESS_3 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_3;
end generate PSRAM_THREE_GEN;
PSRAM_FOUR_GEN: if C_NUM_BANKS_MEM = 4 generate
PSRAM_CONFIG_REG_RD_PROCESS_4 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= PCR_REG(3);
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_4;
end generate PSRAM_FOUR_GEN;
axi_lite_ip2bus_wrack2 <= or_reduce(bus2ip_wrce_lite_cmb); -- 9/14/2013 -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0));
PSRAM_CONFIG_REG_WR_PROCESS : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PCR_REG (i) <= X"0000_0024";
end loop;
else
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if((bus2ip_wrce_lite_cmb(4+i)='1') and
(MEM_TYPE_ARRAY(i) = 4 )
)then
--PCR_REG(i) <= s_axi_reg_wdata;
PCR_REG(i)(31 downto 30) <= s_axi_reg_wdata(31 downto 30);
PCR_REG(i)(6 downto 0) <= s_axi_reg_wdata(6 downto 0);
else
PCR_REG(i) <= PCR_REG(i);
end if;
end loop;
end if;
end if;
end process PSRAM_CONFIG_REG_WR_PROCESS;
----------------------------------------
CRE_WR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
Mem_CRE_int <= '0';
psram_page_mode <= '1';
else
-- defaults
Mem_CRE_int <= '0';
psram_page_mode <= '0';
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if (temp_bus2ip_cs(i) = '1' ) then
Mem_CRE_int <= PCR_REG(i)(6);-- (25);
psram_page_mode <= PCR_REG(i)(0); -- (31);
end if;
end loop;
end if;
end if;
end process CRE_WR_PROCESS;
---------------------------
end generate PSRAM_CONFIG_REG_GEN;
-------------------------
end generate REG_EN_GEN;
-------------------------------------------------------------------------------
AXI_EMC_NATIVE_INTERFACE_I: entity axi_emc_v3_0.axi_emc_native_interface
-- Generics to be set by user
generic map(
C_FAMILY => C_FAMILY ,
C_S_AXI_MEM_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH ,
C_S_AXI_MEM_DATA_WIDTH => C_S_AXI_MEM_DATA_WIDTH ,
C_S_AXI_MEM_ID_WIDTH => C_S_AXI_MEM_ID_WIDTH ,
C_S_AXI_MEM0_BASEADDR => C_S_AXI_MEM0_BASEADDR ,
C_S_AXI_MEM0_HIGHADDR => C_S_AXI_MEM0_HIGHADDR ,
C_S_AXI_MEM1_BASEADDR => C_S_AXI_MEM1_BASEADDR ,
C_S_AXI_MEM1_HIGHADDR => C_S_AXI_MEM1_HIGHADDR ,
C_S_AXI_MEM2_BASEADDR => C_S_AXI_MEM2_BASEADDR ,
C_S_AXI_MEM2_HIGHADDR => C_S_AXI_MEM2_HIGHADDR ,
C_S_AXI_MEM3_BASEADDR => C_S_AXI_MEM3_BASEADDR ,
C_S_AXI_MEM3_HIGHADDR => C_S_AXI_MEM3_HIGHADDR ,
AXI_ARD_ADDR_RANGE_ARRAY => AXI_ARD_ADDR_RANGE_ARRAY,
AXI_ARD_NUM_CE_ARRAY => AXI_ARD_NUM_CE_ARRAY ,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM
)
port map(
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
-- -- AXI Write Address Channel Signals
S_AXI_MEM_AWID => s_axi_mem_awid ,
S_AXI_MEM_AWADDR => s_axi_mem_awaddr ,
S_AXI_MEM_AWLEN => s_axi_mem_awlen ,
S_AXI_MEM_AWSIZE => s_axi_mem_awsize ,
S_AXI_MEM_AWBURST => s_axi_mem_awburst ,
S_AXI_MEM_AWLOCK => s_axi_mem_awlock ,
S_AXI_MEM_AWCACHE => s_axi_mem_awcache ,
S_AXI_MEM_AWPROT => s_axi_mem_awprot ,
S_AXI_MEM_AWVALID => s_axi_mem_awvalid ,
S_AXI_MEM_AWREADY => s_axi_mem_awready ,
-- -- AXI Write Channel Signals
S_AXI_MEM_WDATA => s_axi_mem_wdata ,
S_AXI_MEM_WSTRB => s_axi_mem_wstrb ,
S_AXI_MEM_WLAST => s_axi_mem_wlast ,
S_AXI_MEM_WVALID => s_axi_mem_wvalid ,
S_AXI_MEM_WREADY => s_axi_mem_wready1 ,
-- -- AXI Write Response Channel Signals
S_AXI_MEM_BID => s_axi_mem_bid ,
S_AXI_MEM_BRESP => s_axi_mem_bresp ,
S_AXI_MEM_BVALID => s_axi_mem_bvalid1 ,
S_AXI_MEM_BREADY => s_axi_mem_bready ,
-- -- AXI Read Address Channel Signals
S_AXI_MEM_ARID => s_axi_mem_arid ,
S_AXI_MEM_ARADDR => s_axi_mem_araddr ,
S_AXI_MEM_ARLEN => s_axi_mem_arlen ,
S_AXI_MEM_ARSIZE => s_axi_mem_arsize ,
S_AXI_MEM_ARBURST => s_axi_mem_arburst ,
S_AXI_MEM_ARLOCK => s_axi_mem_arlock ,
S_AXI_MEM_ARCACHE => s_axi_mem_arcache ,
S_AXI_MEM_ARPROT => s_axi_mem_arprot ,
S_AXI_MEM_ARVALID => s_axi_mem_arvalid ,
S_AXI_MEM_ARREADY => s_axi_mem_arready1 ,
-- -- AXI Read Data Channel Signals
S_AXI_MEM_RID => s_axi_mem_rid ,
S_AXI_MEM_RDATA => s_axi_mem_rdata ,
S_AXI_MEM_RRESP => s_axi_mem_rresp ,
S_AXI_MEM_RLAST => s_axi_mem_rlast ,
S_AXI_MEM_RVALID => s_axi_mem_rvalid ,
S_AXI_MEM_RREADY => s_axi_mem_rready ,
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data => temp_ip2bus_data ,
IP2Bus_WrAck => IP2Bus_WrAck ,
IP2Bus_RdAck => IP2Bus_RdAck ,
IP2Bus_AddrAck => IP2Bus_AddrAck ,
IP2Bus_Error => ip2bus_errack ,
Bus2IP_Addr => bus2ip_addr_temp ,
Bus2IP_Data => temp_bus2ip_data ,
Bus2IP_RNW => Bus2IP_RNW ,
Bus2IP_BE => temp_bus2ip_be ,
Bus2IP_Burst => Bus2IP_Burst ,
Bus2IP_BurstLength => bus2ip_burstlength ,
Bus2IP_RdReq => Bus2IP_RdReq_emc ,
Bus2IP_WrReq => Bus2IP_WrReq_emc ,
Bus2IP_CS => temp_bus2ip_cs ,
Bus2IP_RdCE => bus2ip_rdce ,
Bus2IP_WrCE => bus2ip_wrce ,
Type_of_xfer => Type_of_xfer ,
Cre_reg_en => Cre_reg_en_reduced , -- newly added
synch_mem => synch_mem ,
last_addr1 => last_addr1 ,
pr_idle => pr_idle ,
axi_trans_size_reg => axi_trans_size_reg_int
);
---------------------------------------------------------------------------
-- Miscellaneous assignments to match EMC controller to IPIC
---------------------------------------------------------------------------
or_reduced_wrce <= or_reduce(bus2ip_wrce);
------------------------------------------
RD_CE_PIPE_PROCESS : process(s_axi_aclk)is
begin
if(s_axi_aclk'EVENT and s_axi_aclk = '1') then
or_reduced_rdce_d1 <= or_reduce(bus2ip_rdce);
bus2ip_wrreq_reg <= or_reduced_wrce;
end if;
end process RD_CE_PIPE_PROCESS;
------------------------------------------
original_wrce <= or_reduced_wrce;
bus2ip_wrreq_i <= Bus2IP_WrReq_emc;--or_reduce(bus2ip_wrce);
--bus2ip_rdreq_i <= or_reduce(bus2ip_rdce); -- Bus2IP_RdReq_emc;--or_reduce(bus2ip_rdce);
bus2ip_rdreq_i <= Bus2IP_RdReq_emc when synch_mem = '1' else or_reduce(bus2ip_rdce);--or_reduce(bus2ip_rdce);
bus2ip_cs_i <= or_reduce(temp_bus2ip_cs);
---------------------------------------------------------------------------
-- AXI EMC is little endian and EMC COMMON is still big endian, to make
-- this interface work normally, we need to swap the Write and read data
-- comming from and going to slave burst interface
---------------------------------------------------------------------------
ENDIAN_BANKS_0 : if (C_NUM_BANKS_MEM = 1) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
end generate ENDIAN_BANKS_0;
ENDIAN_BANKS_1 : if (C_NUM_BANKS_MEM = 2) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
end generate ENDIAN_BANKS_1;
ENDIAN_BANKS_2 : if (C_NUM_BANKS_MEM = 3) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
bus2ip_cs(2)<= temp_bus2ip_cs(2);
end generate ENDIAN_BANKS_2;
ENDIAN_BANKS_3 : if (C_NUM_BANKS_MEM = 4) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
bus2ip_cs(2)<= temp_bus2ip_cs(2);
bus2ip_cs(3)<= temp_bus2ip_cs(3);
end generate ENDIAN_BANKS_3;
ENDIAN_CONVERSION_32 : if (C_S_AXI_MEM_DATA_WIDTH = 32) generate
bus2ip_data(0 to 7) <= temp_bus2ip_data(7 downto 0);
bus2ip_data(8 to 15) <= temp_bus2ip_data(15 downto 8);
bus2ip_data(16 to 23) <= temp_bus2ip_data(23 downto 16);
bus2ip_data(24 to 31) <= temp_bus2ip_data(31 downto 24);
temp_ip2bus_data(7 downto 0) <= ip2bus_data(0 to 7) ;
temp_ip2bus_data(15 downto 8) <= ip2bus_data(8 to 15) ;
temp_ip2bus_data(23 downto 16) <= ip2bus_data(16 to 23);
temp_ip2bus_data(31 downto 24) <= ip2bus_data(24 to 31);
bus2ip_be(0) <= temp_bus2ip_be(0);
bus2ip_be(1) <= temp_bus2ip_be(1);
bus2ip_be(2) <= temp_bus2ip_be(2);
bus2ip_be(3) <= temp_bus2ip_be(3);
-- the below logic is to generate the lower 2 bits of address for 32
-- bit data width
temp_single_0 <= or_reduce(temp_bus2ip_be(1 downto 0));
temp_single_1 <= or_reduce(temp_bus2ip_be(3 downto 0));
bus2ip_addr_reg(2) <= ((not temp_bus2ip_be(0)) and
(temp_bus2ip_be(1)
OR
((NOT temp_bus2ip_be(2)) and
temp_bus2ip_be(3) and
(NOT temp_single_0)
)
)
) and Type_of_xfer;
bus2ip_addr_reg(1) <= (((not temp_bus2ip_be(0)) and (not
temp_bus2ip_be(1))) and (temp_bus2ip_be(2) OR
temp_bus2ip_be(3)))and Type_of_xfer;
bus2ip_addr <= (bus2ip_addr_temp (0 to 29) & bus2ip_addr_reg (1 to 2))
when (Cre_reg_en_reduced = '0')
else
bus2ip_addr_temp ;
bus2ip_addr_reg(0) <= '0';
end generate ENDIAN_CONVERSION_32;
ENDIAN_CONVERSION_64 : if (C_S_AXI_MEM_DATA_WIDTH = 64) generate
bus2ip_data(0 to 7) <= temp_bus2ip_data(7 downto 0);
bus2ip_data(8 to 15) <= temp_bus2ip_data(15 downto 8);
bus2ip_data(16 to 23) <= temp_bus2ip_data(23 downto 16);
bus2ip_data(24 to 31) <= temp_bus2ip_data(31 downto 24);
bus2ip_data(32 to 39) <= temp_bus2ip_data(39 downto 32);
bus2ip_data(40 to 47) <= temp_bus2ip_data(47 downto 40);
bus2ip_data(48 to 55) <= temp_bus2ip_data(55 downto 48);
bus2ip_data(56 to 63) <= temp_bus2ip_data(63 downto 56);
temp_ip2bus_data(7 downto 0) <= ip2bus_data(0 to 7) ;
temp_ip2bus_data(15 downto 8) <= ip2bus_data(8 to 15) ;
temp_ip2bus_data(23 downto 16) <= ip2bus_data(16 to 23);
temp_ip2bus_data(31 downto 24) <= ip2bus_data(24 to 31);
temp_ip2bus_data(39 downto 32) <= ip2bus_data(32 to 39);
temp_ip2bus_data(47 downto 40) <= ip2bus_data(40 to 47);
temp_ip2bus_data(55 downto 48) <= ip2bus_data(48 to 55);
temp_ip2bus_data(63 downto 56) <= ip2bus_data(56 to 63);
bus2ip_be(0) <= temp_bus2ip_be(0);
bus2ip_be(1) <= temp_bus2ip_be(1);
bus2ip_be(2) <= temp_bus2ip_be(2);
bus2ip_be(3) <= temp_bus2ip_be(3);
bus2ip_be(4) <= temp_bus2ip_be(4);
bus2ip_be(5) <= temp_bus2ip_be(5);
bus2ip_be(6) <= temp_bus2ip_be(6);
bus2ip_be(7) <= temp_bus2ip_be(7);
-- the below logic is to generate the lower 3 bits of address for 64 bit
-- data width
temp_single_0 <= or_reduce(temp_bus2ip_be(1 downto 0));
temp_single_1 <= or_reduce(temp_bus2ip_be(3 downto 0));
temp_single_2 <= or_reduce(temp_bus2ip_be(5 downto 0));
bus2ip_addr_reg(2) <=((not temp_bus2ip_be(0)) and (temp_bus2ip_be(1)
OR ((NOT temp_bus2ip_be(2)) and
temp_bus2ip_be(3) and
(NOT temp_single_0))
OR ((NOT temp_bus2ip_be(4)) and
temp_bus2ip_be(5) and
(NOT temp_single_1))
OR ((NOT temp_bus2ip_be(6)) and
temp_bus2ip_be(7) and
(NOT temp_single_2)))) and Type_of_xfer;
bus2ip_addr_reg(1) <=((((not temp_bus2ip_be(0)) and
(not temp_bus2ip_be(1))) and (temp_bus2ip_be(2)
OR temp_bus2ip_be(3))) OR
(((not temp_bus2ip_be(4)) and
(not temp_bus2ip_be(5))) and (temp_bus2ip_be(6)
OR temp_bus2ip_be(7)) and (NOT temp_single_0)))
and Type_of_xfer;
bus2ip_addr_reg(0) <= (not (temp_bus2ip_be(0) or temp_bus2ip_be(1) or
temp_bus2ip_be(2) or temp_bus2ip_be(3)))
and Type_of_xfer;
bus2ip_addr <= bus2ip_addr_temp (0 to 28) &
bus2ip_addr_reg (0 to 2)
when bus2ip_cs_i = '1' else
(others => '0');
end generate ENDIAN_CONVERSION_64;
-----------------------------------------------------------------------------
--RESET_TOGGLE: convert active low to active hig reset to rest of the core.
-----------------------------------------------------------------------------
RESET_TOGGLE: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(s_axi_aresetn);
end if;
end process RESET_TOGGLE;
EMC_CTRL_I: entity emc_common_v3_0.emc
generic map(
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_IPIF_DWIDTH => C_S_AXI_MEM_DATA_WIDTH,
C_IPIF_AWIDTH => C_S_AXI_MEM_ADDR_WIDTH,
C_MEM0_BASEADDR => C_S_AXI_MEM0_BASEADDR,
C_MEM0_HIGHADDR => C_S_AXI_MEM0_HIGHADDR,
C_MEM1_BASEADDR => C_S_AXI_MEM1_BASEADDR,
C_MEM1_HIGHADDR => C_S_AXI_MEM1_HIGHADDR,
C_MEM2_BASEADDR => C_S_AXI_MEM2_BASEADDR,
C_MEM2_HIGHADDR => C_S_AXI_MEM2_HIGHADDR,
C_MEM3_BASEADDR => C_S_AXI_MEM3_BASEADDR,
C_MEM3_HIGHADDR => C_S_AXI_MEM3_HIGHADDR,
C_PAGEMODE_FLASH_0 => C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1 => C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2 => C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3 => C_PAGEMODE_FLASH_3,
C_INCLUDE_NEGEDGE_IOREGS => C_INCLUDE_NEGEDGE_IOREGS,
C_MEM0_WIDTH => C_MEM0_WIDTH,
C_MEM1_WIDTH => C_MEM1_WIDTH,
C_MEM2_WIDTH => C_MEM2_WIDTH,
C_MEM3_WIDTH => C_MEM3_WIDTH,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_MEM0_TYPE => C_MEM0_TYPE,
C_MEM1_TYPE => C_MEM1_TYPE,
C_MEM2_TYPE => C_MEM2_TYPE,
C_MEM3_TYPE => C_MEM3_TYPE,
C_PARITY_TYPE_0 => C_PARITY_TYPE_MEM_0,
C_PARITY_TYPE_1 => C_PARITY_TYPE_MEM_1,
C_PARITY_TYPE_2 => C_PARITY_TYPE_MEM_2,
C_PARITY_TYPE_3 => C_PARITY_TYPE_MEM_3,
C_INCLUDE_DATAWIDTH_MATCHING_0 => C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3 => C_INCLUDE_DATAWIDTH_MATCHING_3,
-- Memory read and write access times for all memory banks
C_BUS_CLOCK_PERIOD_PS => C_AXI_CLK_PERIOD_PS,
C_SYNCH_MEM_0 => C_SYNCH_MEM_0,
C_SYNCH_PIPEDELAY_0 => C_SYNCH_PIPEDELAY_0,
C_TCEDV_PS_MEM_0 => C_TCEDV_PS_MEM_0,
C_TAVDV_PS_MEM_0 => C_TAVDV_PS_MEM_0,
C_TPACC_PS_FLASH_0 => C_TPACC_PS_FLASH_0,
C_THZCE_PS_MEM_0 => C_THZCE_PS_MEM_0,
C_THZOE_PS_MEM_0 => C_THZOE_PS_MEM_0,
C_TWC_PS_MEM_0 => C_TWC_PS_MEM_0,
C_TWP_PS_MEM_0 => C_TWP_PS_MEM_0,
C_TWPH_PS_MEM_0 => C_TWPH_PS_MEM_0,
C_TLZWE_PS_MEM_0 => C_TLZWE_PS_MEM_0,
C_WR_REC_TIME_MEM_0 => C_WR_REC_TIME_MEM_0,
C_SYNCH_MEM_1 => C_SYNCH_MEM_1,
C_SYNCH_PIPEDELAY_1 => C_SYNCH_PIPEDELAY_1,
C_TCEDV_PS_MEM_1 => C_TCEDV_PS_MEM_1,
C_TAVDV_PS_MEM_1 => C_TAVDV_PS_MEM_1,
C_TPACC_PS_FLASH_1 => C_TPACC_PS_FLASH_1,
C_THZCE_PS_MEM_1 => C_THZCE_PS_MEM_1,
C_THZOE_PS_MEM_1 => C_THZOE_PS_MEM_1,
C_TWC_PS_MEM_1 => C_TWC_PS_MEM_1,
C_TWP_PS_MEM_1 => C_TWP_PS_MEM_1,
C_TWPH_PS_MEM_1 => C_TWPH_PS_MEM_1,
C_TLZWE_PS_MEM_1 => C_TLZWE_PS_MEM_1,
C_WR_REC_TIME_MEM_1 => C_WR_REC_TIME_MEM_1,
C_SYNCH_MEM_2 => C_SYNCH_MEM_2,
C_SYNCH_PIPEDELAY_2 => C_SYNCH_PIPEDELAY_2,
C_TCEDV_PS_MEM_2 => C_TCEDV_PS_MEM_2,
C_TAVDV_PS_MEM_2 => C_TAVDV_PS_MEM_2,
C_TPACC_PS_FLASH_2 => C_TPACC_PS_FLASH_2,
C_THZCE_PS_MEM_2 => C_THZCE_PS_MEM_2,
C_THZOE_PS_MEM_2 => C_THZOE_PS_MEM_2,
C_TWC_PS_MEM_2 => C_TWC_PS_MEM_2,
C_TWP_PS_MEM_2 => C_TWP_PS_MEM_2,
C_TWPH_PS_MEM_2 => C_TWPH_PS_MEM_2,
C_TLZWE_PS_MEM_2 => C_TLZWE_PS_MEM_2,
C_WR_REC_TIME_MEM_2 => C_WR_REC_TIME_MEM_2,
C_SYNCH_MEM_3 => C_SYNCH_MEM_3,
C_SYNCH_PIPEDELAY_3 => C_SYNCH_PIPEDELAY_3,
C_TCEDV_PS_MEM_3 => C_TCEDV_PS_MEM_3,
C_TAVDV_PS_MEM_3 => C_TAVDV_PS_MEM_3,
C_TPACC_PS_FLASH_3 => C_TPACC_PS_FLASH_3,
C_THZCE_PS_MEM_3 => C_THZCE_PS_MEM_3,
C_THZOE_PS_MEM_3 => C_THZOE_PS_MEM_3,
C_TWC_PS_MEM_3 => C_TWC_PS_MEM_3,
C_TWP_PS_MEM_3 => C_TWP_PS_MEM_3,
C_TWPH_PS_MEM_3 => C_TWPH_PS_MEM_3,
C_TLZWE_PS_MEM_3 => C_TLZWE_PS_MEM_3,
C_WR_REC_TIME_MEM_3 => C_WR_REC_TIME_MEM_3
)
port map (
Bus2IP_Clk => s_axi_aclk ,
RdClk => RdClk ,
Bus2IP_Reset => Bus2IP_Reset ,
-- Bus and IPIC Interface signals
Bus2IP_Addr => bus2ip_addr ,
Bus2IP_BE => bus2ip_be ,
Bus2IP_Data => bus2ip_data ,
Bus2IP_RNW => bus2ip_rnw ,
Bus2IP_Burst => bus2ip_burst ,
Bus2IP_WrReq => bus2ip_wrreq_i ,
Bus2IP_RdReq => bus2ip_rdreq_i ,
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag ,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack ,
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc ,
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc ,
Bus2IP_Mem_CS => bus2ip_cs ,
Bus2IP_BurstLength => bus2ip_burstlength ,
IP2Bus_Data => ip2bus_data ,
IP2Bus_errAck => ip2bus_errack ,
IP2Bus_retry => open ,
IP2Bus_toutSup => open ,
IP2Bus_RdAck => ip2bus_rdack ,
IP2Bus_WrAck => ip2bus_wrack ,
IP2Bus_AddrAck => ip2bus_addrack ,
parity_error_adrss => parity_error_adrss , -- 32 bit
parity_error_mem => parity_error_MEM , -- 2 bit
Type_of_xfer => Type_of_xfer ,
psram_page_mode => psram_page_mode ,
original_wrce => original_wrce ,
-- Memory signals
Mem_A => mem_a_i ,
Mem_DQ_I => mem_dq_i_i ,
Mem_DQ_O => mem_dq_o_i ,
Mem_DQ_T => mem_dq_t_i ,
Mem_DQ_PRTY_I => mem_dq_parity_i_i ,
Mem_DQ_PRTY_O => mem_dq_parity_o_i ,
Mem_DQ_PRTY_T => mem_dq_parity_t_i ,
Mem_CEN => mem_cen_i ,
Mem_OEN => mem_oen_i ,
Mem_WEN => mem_wen_i ,
Mem_QWEN => mem_qwen_i ,
Mem_BEN => mem_ben_i ,
Mem_RPN => Mem_RPN ,
Mem_CE => mem_ce_i ,
Mem_ADV_LDN => mem_adv_ldn_i ,
Mem_LBON => Mem_LBON ,
Mem_CKEN => mem_cken_i ,
Mem_RNW => Mem_RNW ,
Cre_reg_en => Cre_reg_en_reduced ,
MEM_WAIT => Mem_WAIT_reg ,
synch_mem12 => synch_mem ,
last_addr1 => last_addr1 ,
pr_idle => pr_idle ,
axi_trans_size_reg => axi_trans_size_reg_int,
axi_arsize => axi_arsize,
axi_wvalid => S_AXI_MEM_WVALID,
axi_wlast => S_AXI_MEM_WLAST,
Parity_err => Parity_err_i
);
end imp;
| gpl-3.0 | ddc5b3f7e4a627074e471c7f5e89faa4 | 0.458722 | 3.629262 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/emac_dpram.vhd | 4 | 18,812 | -------------------------------------------------------------------------------
-- emac_dpram.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac_dpram.vhd
-- Version : v2.0
-- Description : Realization of dprams
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
library lib_bmg_v1_0;
use lib_bmg_v1_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Ce_a -- Port A enable
-- Wr_rd_n_a -- Port A write/read enable
-- Adr_a -- Port A address
-- Data_in_a -- Port A data in
-- Data_out_a -- Port A data out
-- Ce_b -- Port B enable
-- Wr_rd_n_b -- Port B write/read enable
-- Adr_b -- Port B address
-- Data_in_b -- Port B data in
-- Data_out_b -- Port B data out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac_dpram is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
-- a Port signals
Ce_a : in std_logic;
Wr_rd_n_a : in std_logic;
Adr_a : in std_logic_vector(11 downto 0);
Data_in_a : in std_logic_vector(3 downto 0);
Data_out_a : out std_logic_vector(3 downto 0);
-- b Port Signals
Ce_b : in std_logic;
Wr_rd_n_b : in std_logic;
Adr_b : in std_logic_vector(8 downto 0);
Data_in_b : in std_logic_vector(31 downto 0);
Data_out_b : out std_logic_vector(31 downto 0)
);
end entity emac_dpram;
architecture imp of emac_dpram is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- component RAMB16_S4_S36
---- pragma translate_off
-- generic
-- (
-- WRITE_MODE_A : string := "READ_FIRST";
-- --WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE
-- WRITE_MODE_B : string := "READ_FIRST"
-- --WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE
-- );
---- pragma translate_on
-- port (
-- DOA : out std_logic_vector (3 downto 0);
-- DOB : out std_logic_vector (31 downto 0);
-- DOPB : out std_logic_vector (3 downto 0);
-- ADDRA : in std_logic_vector (11 downto 0);
-- CLKA : in std_logic;
-- DIA : in std_logic_vector (3 downto 0);
-- ENA : in std_logic;
-- SSRA : in std_logic;
-- WEA : in std_logic;
-- ADDRB : in std_logic_vector (8 downto 0);
-- CLKB : in std_logic;
-- DIB : in std_logic_vector (31 downto 0);
-- DIPB : in std_logic_vector (3 downto 0);
-- ENB : in std_logic;
-- SSRB : in std_logic;
-- WEB : in std_logic
-- );
-- end component;
--constant create_v2_mem : boolean := supported(C_FAMILY, u_RAMB16_S4_S36);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ce_a_i : std_logic;
signal ce_b_i : std_logic;
--signal wr_rd_n_a_i : std_logic;
signal wr_rd_n_a_i : std_logic_vector(0 downto 0);
--signal wr_rd_n_b_i : std_logic;
signal wr_rd_n_b_i : std_logic_vector(0 downto 0);
signal port_b_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal port_b_data_out : STD_LOGIC_VECTOR (31 downto 0);
--attribute WRITE_MODE_A : string;
--attribute WRITE_MODE_A of I_DPB16_4_9: label is "READ_FIRST";
--attribute WRITE_MODE_B : string;
--attribute WRITE_MODE_B of I_DPB16_4_9: label is "READ_FIRST";
begin -- architecture
ce_a_i <= Ce_a or Rst;
ce_b_i <= Ce_b or Rst;
wr_rd_n_a_i(0) <= Wr_rd_n_a and not(Rst);
wr_rd_n_b_i(0) <= Wr_rd_n_b and not(Rst);
-------------------------------------------------------------------------------
-- Using VII 4096 x 4 : 2048 x 8 Dual Port Primitive
-------------------------------------------------------------------------------
-- port_b_data_in(31) <= Data_in_b(0);
-- port_b_data_in(30) <= Data_in_b(1);
-- port_b_data_in(29) <= Data_in_b(2);
-- port_b_data_in(28) <= Data_in_b(3);
-- port_b_data_in(27) <= Data_in_b(4);
-- port_b_data_in(26) <= Data_in_b(5);
-- port_b_data_in(25) <= Data_in_b(6);
-- port_b_data_in(24) <= Data_in_b(7);
-- port_b_data_in(23) <= Data_in_b(8);
-- port_b_data_in(22) <= Data_in_b(9);
-- port_b_data_in(21) <= Data_in_b(10);
-- port_b_data_in(20) <= Data_in_b(11);
-- port_b_data_in(19) <= Data_in_b(12);
-- port_b_data_in(18) <= Data_in_b(13);
-- port_b_data_in(17) <= Data_in_b(14);
-- port_b_data_in(16) <= Data_in_b(15);
-- port_b_data_in(15) <= Data_in_b(16);
-- port_b_data_in(14) <= Data_in_b(17);
-- port_b_data_in(13) <= Data_in_b(18);
-- port_b_data_in(12) <= Data_in_b(19);
-- port_b_data_in(11) <= Data_in_b(20);
-- port_b_data_in(10) <= Data_in_b(21);
-- port_b_data_in(9) <= Data_in_b(22);
-- port_b_data_in(8) <= Data_in_b(23);
-- port_b_data_in(7) <= Data_in_b(24);
-- port_b_data_in(6) <= Data_in_b(25);
-- port_b_data_in(5) <= Data_in_b(26);
-- port_b_data_in(4) <= Data_in_b(27);
-- port_b_data_in(3) <= Data_in_b(28);
-- port_b_data_in(2) <= Data_in_b(29);
-- port_b_data_in(1) <= Data_in_b(30);
-- port_b_data_in(0) <= Data_in_b(31);
--
-- Data_out_b(31) <= port_b_data_out(0);
-- Data_out_b(30) <= port_b_data_out(1);
-- Data_out_b(29) <= port_b_data_out(2);
-- Data_out_b(28) <= port_b_data_out(3);
-- Data_out_b(27) <= port_b_data_out(4);
-- Data_out_b(26) <= port_b_data_out(5);
-- Data_out_b(25) <= port_b_data_out(6);
-- Data_out_b(24) <= port_b_data_out(7);
-- Data_out_b(23) <= port_b_data_out(8);
-- Data_out_b(22) <= port_b_data_out(9);
-- Data_out_b(21) <= port_b_data_out(10);
-- Data_out_b(20) <= port_b_data_out(11);
-- Data_out_b(19) <= port_b_data_out(12);
-- Data_out_b(18) <= port_b_data_out(13);
-- Data_out_b(17) <= port_b_data_out(14);
-- Data_out_b(16) <= port_b_data_out(15);
-- Data_out_b(15) <= port_b_data_out(16);
-- Data_out_b(14) <= port_b_data_out(17);
-- Data_out_b(13) <= port_b_data_out(18);
-- Data_out_b(12) <= port_b_data_out(19);
-- Data_out_b(11) <= port_b_data_out(20);
-- Data_out_b(10) <= port_b_data_out(21);
-- Data_out_b(9) <= port_b_data_out(22);
-- Data_out_b(8) <= port_b_data_out(23);
-- Data_out_b(7) <= port_b_data_out(24);
-- Data_out_b(6) <= port_b_data_out(25);
-- Data_out_b(5) <= port_b_data_out(26);
-- Data_out_b(4) <= port_b_data_out(27);
-- Data_out_b(3) <= port_b_data_out(28);
-- Data_out_b(2) <= port_b_data_out(29);
-- Data_out_b(1) <= port_b_data_out(30);
-- Data_out_b(0) <= port_b_data_out(31);
--
--
-- I_DPB16_4_9: RAMB16_S4_S36
-- port map (
-- DOA => Data_out_a, --[out]
-- DOB => port_b_data_out, --[out]
-- DOPB => open, --[out]
-- ADDRA => Adr_a, --[in]
-- CLKA => Clk, --[in]
-- DIA => Data_in_a, --[in]
-- ENA => ce_a_i, --[in]
-- SSRA => Rst, --[in]
-- WEA => wr_rd_n_a_i, --[in]
-- ADDRB => Adr_b, --[in]
-- CLKB => Clk, --[in]
-- DIB => port_b_data_in, --[in]
-- DIPB => (others => '0'), --[in]
-- ENB => ce_b_i, --[in]
-- SSRB => Rst, --[in]
-- WEB => wr_rd_n_b_i --[in]
-- );
--
-- I_DPB16_4_9: RAMB16_S4_S36
-- port map (
-- DOA => Data_out_a, --[out]
-- DOB => Data_out_b, --[out]
-- DOPB => open, --[out]
-- ADDRA => Adr_a, --[in]
-- CLKA => Clk, --[in]
-- DIA => Data_in_a, --[in]
-- ENA => ce_a_i, --[in]
-- SSRA => Rst, --[in]
-- WEA => wr_rd_n_a_i, --[in]
-- ADDRB => Adr_b, --[in]
-- CLKB => Clk, --[in]
-- DIB => Data_in_b, --[in]
-- DIPB => (others => '0'), --[in]
-- ENB => ce_b_i, --[in]
-- SSRB => Rst, --[in]
-- WEB => wr_rd_n_b_i --[in]
-- );
dpram_blkmem: entity lib_bmg_v1_0.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => 2,
c_algorithm => 1,
c_prim_type => 1,
c_byte_size => 8, -- 8 or 9
c_sim_collision_check => "NONE",
c_common_clk => 1, -- 0, 1
c_disable_warn_bhv_coll => 1, -- 0, 1
c_disable_warn_bhv_range => 1, -- 0, 1
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0, -- 0, 1
c_default_data => "0", -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a => 0, -- 0, 1
c_has_mux_output_regs_a => 0, -- 0, 1
c_write_width_a => 4, -- 1 to 1152
c_read_width_a => 4, -- 1 to 1152
c_write_depth_a => 4096, -- 2 to 9011200
c_read_depth_a => 4096, -- 2 to 9011200
c_addra_width => 12, -- 1 to 24
c_write_mode_a => "READ_FIRST",
c_has_ena => 1, -- 0, 1
c_has_regcea => 1, -- 0, 1
c_has_ssra => 0, -- 0, 1
c_sinita_val => "0", --"..."
c_use_byte_wea => 0, -- 0, 1
c_wea_width => 1, -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b => 0, -- 0, 1
c_has_mux_output_regs_b => 0, -- 0, 1
c_write_width_b => 32, -- 1 to 1152
c_read_width_b => 32, -- 1 to 1152
c_write_depth_b => 512, -- 2 to 9011200
c_read_depth_b => 512, -- 2 to 9011200
c_addrb_width => 9, -- 1 to 24
c_write_mode_b => "READ_FIRST",
c_has_enb => 1, -- 0, 1
c_has_regceb => 1, -- 0, 1
c_has_ssrb => 0, -- 0, 1
c_sinitb_val => "0", -- "..."
c_use_byte_web => 0, -- 0, 1
c_web_width => 1, -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages => 0, -- 0, 1, 2, 3
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0--, --0, 1
)
port map (
clka => Clk,
ssra => '0',
dina => Data_in_a,
addra => Adr_a,
ena => ce_a_i,
regcea => '1',
wea => wr_rd_n_a_i,
douta => Data_out_a,
clkb => Clk,
ssrb => '0',
dinb => Data_in_b,
addrb => Adr_b,
enb => ce_b_i,
regceb => '1',
web => wr_rd_n_b_i,
doutb => Data_out_b,
dbiterr => open,
sbiterr => open );
--assert (create_v2_mem)
--report "The primitive RAMB16_S4_S36 is not Supported by the Target device"
--severity FAILURE;
end architecture imp;
| gpl-3.0 | 5f82e1a27c238dd32bd542b6262f8efb | 0.401552 | 3.48564 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/CipherCore.vhd | 1 | 26,280 | -------------------------------------------------------------------------------
--! @file CipherCore.vhd
--! @author Hannes Gross
--! @brief Generic Ascon-128(a) implementation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity CipherCore is
generic (
-- Ascon related generics
RATE : integer := 64; -- Selects:
-- (64) -> Ascon128
-- (128)-> Acon128a
UNROLED_ROUNDS : integer := 1; -- Ascon128: 1, 2, 3, or 6 rounds
-- Ascon128a: 1, 2, or 4 rounds
ROUNDS_A : integer := 12; -- Number of rounds for initialization
-- and finalization
ROUNDS_B : integer := 6; -- Num permutation rounds for data for
-- (6) -> Ascon128
-- (8) -> Ascon128a
--- Interface generics:
-- Reset behavior
G_ASYNC_RSTN : boolean := false; --! Async active low reset
-- Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 32; --! Key
G_TAG_SIZE : integer := 128; --! Tag
-- The number of bits required to hold block size expressed in
-- bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
G_MAX_LEN : integer := SINGLE_PASS_MAX
);
port (
--! Global
clk : in std_logic;
rst : in std_logic;
--! PreProcessor (data)
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! PreProcessor (controls)
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_partial : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! PostProcessor
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : out std_logic;
bdo_ready : in std_logic;
bdo_size : out std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Constants
constant CONST_UNROLED_R : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(UNROLED_ROUNDS, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
constant CONST_ROUNDS_AmR: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A-UNROLED_ROUNDS, 4));
constant CONST_ROUNDS_BmR: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B-UNROLED_ROUNDS, 4));
constant CONST_RATE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(RATE, 8));
constant STATE_WORD_SIZE : integer := 64;
constant KEY_SIZE : integer := 128;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
-- Segment Type Encoding
constant TYPE_AD : std_logic_vector(2 downto 0) := "000";
constant TYPE_PTCT : std_logic_vector(2 downto 0) := "010";
constant TYPE_TAG : std_logic_vector(2 downto 0) := "100";
constant TYPE_LEN : std_logic_vector(2 downto 0) := "101";
constant TYPE_NONCE : std_logic_vector(2 downto 0) := "110";
-- FSM state definition
type state_t is (STATE_IDLE,
STATE_UPDATE_KEY,
STATE_WRITE_NONCE_0,
STATE_WRITE_NONCE_1,
STATE_INITIALIZATION,
STATE_PERMUTATION,
STATE_FINALIZATION,
STATE_WAIT_FOR_INPUT,
STATE_PROCESS_TAG_0,
STATE_PROCESS_TAG_1);
-- FSM next and present state signals
signal State_DN,State_DP : state_t;
-- Ascon's state registers
signal X0_DN, X0_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X1_DN, X1_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X2_DN, X2_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X3_DN, X3_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X4_DN, X4_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
-- Key register
signal Keyreg_DN : std_logic_vector(KEY_SIZE-1 downto 0);
signal Keyreg_DP : std_logic_vector(KEY_SIZE-1 downto 0);
-- Round counter
signal RoundCounter_DN : std_logic_vector(3 downto 0);
signal RoundCounter_DP : std_logic_vector(3 downto 0);
signal DisableRoundCounter_S : std_logic;
-- Additional control logic registers
signal IsFirstPTCT_DN, IsFirstPTCT_DP : std_logic;
signal IsDecryption_DN, IsDecryption_DP : std_logic;
-- Helper function, rotates a state word
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
begin -- ROTATE_STATE_WORD
return word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
end ROTATE_STATE_WORD;
begin
-----------------------------------------------------------------------------
-- State operations (permutation, data loading, et cetera)
state_opeartions_p : process (IsDecryption_DP, IsFirstPTCT_DP,
Keyreg_DP, RoundCounter_DP,
RoundCounter_DP, State_DN,
State_DP, X0_DP,
X1_DP, X2_DP, X3_DP,
X4_DP, bdi,
bdi, bdi_eot, bdi_type,
bdi_valid, bdi_valid_bytes, decrypt) is
-- Roudn permutation input, intermediates, and output
variable P0_DV, P1_DV, P2_DV, P3_DV, P4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable R0_DV, R1_DV, R2_DV, R3_DV, R4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable S0_DV, S1_DV, S2_DV, S3_DV, S4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable T0_DV, T1_DV, T2_DV, T3_DV, T4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable U0_DV, U1_DV, U2_DV, U3_DV, U4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
-- Round constant
variable RoundConst_DV : std_logic_vector(63 downto 0);
-- Second part of tag comparison
variable TagCompResult_DV : std_logic_vector(RATE-1 downto 0);
begin -- process state_opeartions_p
--- Default values:
-- State variable X0-X4 --> keep current value
X0_DN <= X0_DP; X1_DN <= X1_DP; X2_DN <= X2_DP; X3_DN <= X3_DP; X4_DN <= X4_DP;
-- Permutation input --> use current state as default input
P0_DV := X0_DP; P1_DV := X1_DP; P2_DV := X2_DP; P3_DV := X3_DP; P4_DV := X4_DP;
-- Reset informational signals, when perfoming initialization
if State_DP = STATE_INITIALIZATION then
IsFirstPTCT_DN <= '1';
IsDecryption_DN <= decrypt;
else -- otherwise just keep value
IsFirstPTCT_DN <= IsFirstPTCT_DP;
IsDecryption_DN <= IsDecryption_DP;
end if;
--- P0,[P1] MUX: When data input is ready --> select P0,[P1] accordingly
if State_DP = STATE_WAIT_FOR_INPUT and (bdi_valid = '1') then
-- Encryption
if (IsDecryption_DP = '0') or (bdi_type = TYPE_AD) then
if RATE = 128 then -- Ascon128a variant
P0_DV := X0_DP xor bdi(RATE-1 downto RATE-64);
P1_DV := X1_DP xor bdi(63 downto 0);
else
P0_DV := X0_DP xor bdi;
end if;
-- Decryption
else
-- We need to take care of the number of valid bytes!
for i in 7 downto 0 loop
if RATE = 128 then -- Ascon128a variant
-- P1 xor input data ...
P0_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 + 64 downto i*8 + 64);
P1_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 downto i*8);
-- if invalid byte then use additionally xor X1
if bdi_valid_bytes(i) = '0' then
P1_DV(i*8 + 7 downto i*8) := P1_DV(i*8 + 7 downto i*8) xor X1_DP(i*8 + 7 downto i*8);
end if;
-- if invalid byte then use additionally xor X0
if bdi_valid_bytes(i+8) = '0' then
P0_DV(i*8 + 7 downto i*8) := P0_DV(i*8 + 7 downto i*8) xor X0_DP(i*8 + 7 downto i*8);
end if;
else -- Ascon128 variant
-- P0 xor input data ...
P0_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 downto i*8);
-- if invalid byte then use additionally xor X0
if bdi_valid_bytes(i) = '0' then
P0_DV(i*8 + 7 downto i*8) := P0_DV(i*8 + 7 downto i*8) xor X0_DP(i*8 + 7 downto i*8);
end if;
end if;
end loop; -- i
end if;
--- P1[2]-4 MUX:
-- if performing FINALIZATION next
if State_DN = STATE_FINALIZATION then
-- TODO: when 128a variant write P2
-- Add key before permutation
if RATE = 64 then -- Ascon128 variant
P1_DV := P1_DV xor Keyreg_DP(127 downto 64);
P2_DV := P2_DV xor Keyreg_DP(63 downto 0);
else -- Ascon128a variant
P2_DV := P2_DV xor Keyreg_DP(127 downto 64);
P3_DV := P3_DV xor Keyreg_DP(63 downto 0);
end if;
-- If first PT/CT never processed (empty AD + PT/CT case)
if (IsFirstPTCT_DP = '1') then
P4_DV(0) := not P4_DV(0); -- Add 0*||1
end if;
-- if performing PERMUTATION next
elsif ((bdi_valid = '1') and not ((bdi_type = TYPE_TAG) or
(bdi_type = TYPE_PTCT and bdi_eot = '1'))) then
-- ... and first round of PT/CT calculation
if (bdi_type = TYPE_PTCT) and (IsFirstPTCT_DP = '1') then
IsFirstPTCT_DN <= '0'; -- SET first PT/CT performed
P4_DV(0) := not P4_DV(0); -- Add 0*||1
end if;
end if;
end if;
-- Unroled round permutation
for r in 0 to UNROLED_ROUNDS-1 loop
-- Calculate round constant
RoundConst_DV := (others => '0'); -- set to zero
RoundConst_DV(7 downto 0) := not std_logic_vector(unsigned(RoundCounter_DP(3 downto 0)) + r) &
std_logic_vector(unsigned(RoundCounter_DP(3 downto 0)) + r);
R0_DV := P0_DV xor P4_DV;
R1_DV := P1_DV;
R2_DV := P2_DV xor P1_DV xor RoundConst_DV;
R3_DV := P3_DV;
R4_DV := P4_DV xor P3_DV;
S0_DV := R0_DV xor (not R1_DV and R2_DV);
S1_DV := R1_DV xor (not R2_DV and R3_DV);
S2_DV := R2_DV xor (not R3_DV and R4_DV);
S3_DV := R3_DV xor (not R4_DV and R0_DV);
S4_DV := R4_DV xor (not R0_DV and R1_DV);
T0_DV := S0_DV xor S4_DV;
T1_DV := S1_DV xor S0_DV;
T2_DV := not S2_DV;
T3_DV := S3_DV xor S2_DV;
T4_DV := S4_DV;
U0_DV := T0_DV xor ROTATE_STATE_WORD(T0_DV, 19) xor ROTATE_STATE_WORD(T0_DV, 28);
U1_DV := T1_DV xor ROTATE_STATE_WORD(T1_DV, 61) xor ROTATE_STATE_WORD(T1_DV, 39);
U2_DV := T2_DV xor ROTATE_STATE_WORD(T2_DV, 1) xor ROTATE_STATE_WORD(T2_DV, 6);
U3_DV := T3_DV xor ROTATE_STATE_WORD(T3_DV, 10) xor ROTATE_STATE_WORD(T3_DV, 17);
U4_DV := T4_DV xor ROTATE_STATE_WORD(T4_DV, 7) xor ROTATE_STATE_WORD(T4_DV, 41);
P0_DV := U0_DV;
P1_DV := U1_DV;
P2_DV := U2_DV;
P3_DV := U3_DV;
P4_DV := U4_DV;
end loop;
-- Do tag comparison when doing decryption in PROCESS TAG states
msg_auth_done <= '0'; --default
msg_auth_valid <= '0';
if IsDecryption_DP = '1' then
if (State_DP = STATE_PROCESS_TAG_0) then
-- valid data for comparison ready?
if bdi_valid = '1' then
if RATE = 128 then -- Ascon128a variant
-- signal we are done with comparison
msg_auth_done <= '1';
-- tags equal?
TagCompResult_DV := (X3_DP & X4_DP) xor Keyreg_DP;
if (TagCompResult_DV = bdi) then
msg_auth_valid <= '1';
end if;
else -- Ascon128 variant
X3_DN <= X3_DP xor Keyreg_DP(127 downto 64) xor bdi;
end if;
end if;
elsif (State_DP = STATE_PROCESS_TAG_1) then
-- debug
if RATE = 64 then -- Ascon128 variant
-- valid data for comparison ready?
if bdi_valid = '1' then
-- signal we are done with comparison
msg_auth_done <= '1';
-- Check if tags are equal
TagCompResult_DV := (X4_DP xor Keyreg_DP(63 downto 0) xor bdi);
if (X3_DP & TagCompResult_DV) = x"00000000000000000000000000000000" then
msg_auth_valid <= '1';
end if;
end if;
end if;
end if;
end if;
--- State X0...4 MUX: select input of state registers
case State_DP is
-- WRITE_NONCE_0 --> and init state
when STATE_WRITE_NONCE_0 =>
-- ready to receive
if (bdi_valid = '1') then
-- fill X0 with IV
X0_DN <= CONST_KEY_SIZE & CONST_RATE & CONST_ROUNDS_A & CONST_ROUNDS_B & x"00000000";
X1_DN <= Keyreg_DP(127 downto 64);
X2_DN <= Keyreg_DP(63 downto 0);
if RATE = 128 then -- Ascon128a variant
X3_DN <= bdi(RATE-1 downto RATE-64);
X4_DN <= bdi( 63 downto 0);
else -- Ascon128 variant
X3_DN <= bdi(63 downto 0);
end if;
end if;
-- WRITE_NONCE_1 --> second part of nonce
when STATE_WRITE_NONCE_1 =>
-- ready to receive
if (bdi_valid = '1') then
X4_DN <= bdi;
end if;
-- INITIALIZATION, PERMUTATION, FINALIZATION --> apply round transformation
when STATE_PERMUTATION | STATE_INITIALIZATION | STATE_FINALIZATION =>
X0_DN <= P0_DV; X1_DN <= P1_DV; X2_DN <= P2_DV;
-- Add key after initialization
if (State_DP = STATE_INITIALIZATION and RoundCounter_DP = CONST_ROUNDS_AmR) then
X3_DN <= P3_DV xor Keyreg_DP(127 downto 64);
X4_DN <= P4_DV xor Keyreg_DP(63 downto 0);
else
X3_DN <= P3_DV;
X4_DN <= P4_DV;
end if;
-- WAIT FOR INPUT --> apply round transformation when input is ready
when STATE_WAIT_FOR_INPUT =>
if bdi_valid = '1' then
-- State <= permutation output
X0_DN <= P0_DV; X1_DN <= P1_DV; X2_DN <= P2_DV; X3_DN <= P3_DV; X4_DN <= P4_DV;
end if;
when others => null;
end case;
end process state_opeartions_p;
-----------------------------------------------------------------------------
-- Update key register --> simple shift register
key_update_p: process (Keyreg_DP, State_DP, key, key_valid) is
begin -- process key_update_p
Keyreg_DN <= Keyreg_DP; -- default
key_ready <= '0';
-- only update key while in the update state
if State_DP = STATE_UPDATE_KEY then
key_ready <= '1'; -- always ready
-- shift register and insert new key data
if key_valid = '1' then
Keyreg_DN <= Keyreg_DP (KEY_SIZE-G_KEY_SIZE-1 downto 0) & key;
end if;
end if;
end process key_update_p;
-----------------------------------------------------------------------------
-- Input logic --> controlling input interface signals
input_logic_p: process (State_DP, bdi_type, bdi_valid) is
begin -- process input_logic_p
bdi_ready <= '1'; -- default, ready
-- We are busy when...
if State_DP = STATE_IDLE or
State_DP = STATE_UPDATE_KEY or
State_DP = STATE_INITIALIZATION or
State_DP = STATE_PERMUTATION or
(State_DP = STATE_PROCESS_TAG_0 and IsDecryption_DP = '0') or
(State_DP = STATE_PROCESS_TAG_1 and IsDecryption_DP = '0') or
State_DP = STATE_FINALIZATION then
-- signal busyness
bdi_ready <= '0';
end if;
end process input_logic_p;
-----------------------------------------------------------------------------
-- Output logic --> controlling output interface signals
output_logic_p: process (Keyreg_DP,
State_DP, X0_DP, X1_DP, X3_DP, X4_DP, bdi,
bdi, bdi_size,
bdi_type, bdi_valid, bdo_ready) is
begin -- process output_logic_p
bdo_valid <= '0'; -- default, nothing to output
if RATE = 128 then -- Ascon128a variant
bdo(RATE-1 downto RATE-64) <= X0_DP xor bdi(RATE-1 downto RATE-64);
bdo(63 downto 0) <= X1_DP xor bdi(63 downto 0);
else -- Ascon128 variant
bdo <= X0_DP xor bdi;
end if;
-- Wait for output to be ready
if bdo_ready = '1' then
-- waiting for output of PT/CT and there is something to output (size > 0)?
if (State_DP = STATE_WAIT_FOR_INPUT) then
if (bdi_valid = '1') and (bdi_type = TYPE_PTCT) and (bdi_size /= (bdi_size'range => '0')) then
bdo_valid <= '1';
end if;
-- output Tag part 1
elsif State_DP = STATE_PROCESS_TAG_0 then
bdo_valid <= '1';
if RATE = 128 then -- Ascon128a variant
bdo(RATE-1 downto RATE-64) <= X3_DP xor Keyreg_DP(127 downto 64);
bdo(63 downto 0) <= X4_DP xor Keyreg_DP(63 downto 0);
else -- Ascon128 variant
bdo <= X3_DP xor Keyreg_DP(127 downto 64);
end if;
-- output Tag part 2
elsif State_DP = STATE_PROCESS_TAG_1 then
bdo_valid <= '1';
bdo <= X4_DP xor Keyreg_DP(63 downto 0);
end if;
end if;
end process output_logic_p;
-----------------------------------------------------------------------------
-- Next state logic
fsm_comb_p: process (IsDecryption_DP, RoundCounter_DP, State_DP, bdi_eot,
bdi_type, bdi_valid, bdo_ready, key_update, key_valid) is
begin -- process fsm_comb_p
State_DN <= State_DP; -- default
-- FSM state transfers
case State_DP is
-- IDLE
when STATE_IDLE =>
-- preprocessor forces key update
if (key_update = '1') then
State_DN <= STATE_UPDATE_KEY;
-- skip key update and start writing the nonce
elsif (bdi_valid = '1') and (bdi_type = TYPE_NONCE) then
State_DN <= STATE_WRITE_NONCE_0;
end if;
-- UPDATE_KEY
when STATE_UPDATE_KEY =>
-- when key is invalid we assume the key update is finished
if (key_valid = '0' and key_update = '0') then
-- go back to IDLE
State_DN <= STATE_IDLE;
end if;
-- WRITE_NONCE_0 (Part 1)
when STATE_WRITE_NONCE_0 =>
-- write first part of nonce
if (bdi_valid = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_INITIALIZATION;
else
State_DN <= STATE_WRITE_NONCE_1;
end if;
end if;
-- WRITE_NONCE_1 (Part 2)
when STATE_WRITE_NONCE_1 =>
-- write second part of nonce
if (bdi_valid = '1') then
State_DN <= STATE_INITIALIZATION;
end if;
-- INITIALIZATION
when STATE_INITIALIZATION =>
if RoundCounter_DP = CONST_ROUNDS_AmR then
State_DN <= STATE_WAIT_FOR_INPUT;
end if;
-- PERMUTATION
when STATE_PERMUTATION =>
if RoundCounter_DP = CONST_ROUNDS_BmR then
State_DN <= STATE_WAIT_FOR_INPUT;
end if;
-- FINALIZATION
when STATE_FINALIZATION =>
if RoundCounter_DP = CONST_ROUNDS_AmR then
State_DN <= STATE_PROCESS_TAG_0;
end if;
-- PROCESS TAG PART 1
when STATE_PROCESS_TAG_0 =>
-- encryption -> wait for output stream to be ready
if (IsDecryption_DP = '0') then
if (bdo_ready = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_IDLE;
else -- Ascon128 variant
State_DN <= STATE_PROCESS_TAG_1;
end if;
end if;
else
-- decryption -> wait for tag for comparison
if (bdi_valid = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_IDLE;
else -- Ascon128 variant
State_DN <= STATE_PROCESS_TAG_1;
end if;
end if;
end if;
-- PROCESS TAG PART 2
when STATE_PROCESS_TAG_1 =>
-- encryption -> wait for output stream to be ready
if (IsDecryption_DP = '0') then
if (bdo_ready = '1') then
State_DN <= STATE_IDLE;
end if;
else
-- decryption -> wait for tag for comparison
if (bdi_valid = '1') then
State_DN <= STATE_IDLE;
end if;
end if;
-- WAIT_FOR_INPUT
when STATE_WAIT_FOR_INPUT =>
-- input is ready so process
if (bdi_valid = '1') then
-- if its a tag or last PT/CT then...
if (bdi_type = TYPE_TAG) or
(bdi_type = TYPE_PTCT and bdi_eot = '1')then
State_DN <= STATE_FINALIZATION;
else -- process AD or PT/CT
-- PERMUTATION state is unnecessary if we fully unroll
if (UNROLED_ROUNDS /= ROUNDS_B) then
State_DN <= STATE_PERMUTATION;
end if;
end if;
end if;
when others => null;
end case;
end process fsm_comb_p;
-----------------------------------------------------------------------------
-- Round counter realization
round_counter_p: process (DisableRoundCounter_S, RoundCounter_DP, State_DP,
bdi_valid) is
variable CounterVal_DV : integer;
begin -- process round_counter_p
RoundCounter_DN <= RoundCounter_DP; -- default
-- Enable counter during ...
if (State_DP = STATE_PERMUTATION) or
(State_DP = STATE_INITIALIZATION) or
(State_DP = STATE_FINALIZATION) or
(State_DP = STATE_WAIT_FOR_INPUT and bdi_valid = '1') then
-- Counter += #unroled rounds
CounterVal_DV := to_integer(unsigned(RoundCounter_DP)) + UNROLED_ROUNDS; -- increment
-- Overrun detection --> set back to 0
if (CounterVal_DV >= ROUNDS_A) or (State_DP = STATE_PERMUTATION and CounterVal_DV >= ROUNDS_B) then
CounterVal_DV := 0;
end if;
-- set next counter register value
RoundCounter_DN <= std_logic_vector(to_unsigned(CounterVal_DV, RoundCounter_DN'length));
else -- Disable round counter and set it to zero
RoundCounter_DN <= (others => '0');
end if;
end process round_counter_p;
-----------------------------------------------------------------------------
-- Process for all registers in design
gen_register_with_asynchronous_reset : if G_ASYNC_RSTN = false generate
register_process_p : process (clk, rst) is
begin -- process register_process_p
if rst = '1' then -- asynchronous reset (active high)
State_DP <= STATE_IDLE;
X0_DP <= (others => '0');
X1_DP <= (others => '0');
X2_DP <= (others => '0');
X3_DP <= (others => '0');
X4_DP <= (others => '0');
Keyreg_DP <= (others => '0');
RoundCounter_DP <= (others => '0');
IsFirstPTCT_DP <= '1';
IsDecryption_DP <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
State_DP <= State_DN;
X0_DP <= X0_DN;
X1_DP <= X1_DN;
X2_DP <= X2_DN;
X3_DP <= X3_DN;
X4_DP <= X4_DN;
Keyreg_DP <= Keyreg_DN;
RoundCounter_DP <= RoundCounter_DN;
IsFirstPTCT_DP <= IsFirstPTCT_DN;
IsDecryption_DP <= IsDecryption_DN;
end if;
end process register_process_p;
end generate gen_register_with_asynchronous_reset;
-- else generate with synchronous reset
gen_register_with_synchronous_reset : if G_ASYNC_RSTN = true generate
register_process_p : process (clk, rst) is
begin -- process register_process_p
if clk'event and clk = '1' then -- rising clock edge
if rst = '1' then -- synchronous reset (active high)
State_DP <= STATE_IDLE;
X0_DP <= (others => '0');
X1_DP <= (others => '0');
X2_DP <= (others => '0');
X3_DP <= (others => '0');
X4_DP <= (others => '0');
Keyreg_DP <= (others => '0');
RoundCounter_DP <= (others => '0');
IsFirstPTCT_DP <= '1';
IsDecryption_DP <= '0';
else
State_DP <= State_DN;
X0_DP <= X0_DN;
X1_DP <= X1_DN;
X2_DP <= X2_DN;
X3_DP <= X3_DN;
X4_DP <= X4_DN;
Keyreg_DP <= Keyreg_DN;
RoundCounter_DP <= RoundCounter_DN;
IsFirstPTCT_DP <= IsFirstPTCT_DN;
IsDecryption_DP <= IsDecryption_DN;
end if;
end if;
end process register_process_p;
end generate gen_register_with_synchronous_reset;
end structure;
| apache-2.0 | 5e97556912220569957646e5b7abe1b9 | 0.521537 | 3.638377 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/synth/design_1_axi_uartlite_0_0.vhd | 2 | 8,973 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_uartlite_0_0_arch : ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
| gpl-3.0 | 644f7d43973023a0a789a3f25805568e | 0.697091 | 3.291636 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/tx_statemachine.vhd | 4 | 61,222 | -------------------------------------------------------------------------------
-- tx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : tx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the transmit control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxClkEn -- Transmit clocl enable
-- Jam_rst -- Jam reset
-- TxRst -- Transmit reset
-- Deferring -- Deffering
-- ColRetryCnt -- Collision retry coun
-- ColWindowNibCnt -- Collision window nibble count
-- JamTxNibCnt -- TX Jam nibble count
-- TxNibbleCnt -- TX Nibble count
-- BusFifoWrNibbleCnt -- Bus FIFO write nibble count
-- CrcCnt -- CRC count
-- BusFifoFull -- Bus FIFO full
-- BusFifoEmpty -- Bus FIFO empty
-- PhyCollision -- Phy collision
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- InitBackoff -- Initialize back off
-- TxRetryRst -- TX retry reset
-- TxExcessDefrlRst -- TX excess defer reset
-- TxLateColnRst -- TX late collision reset
-- TxColRetryCntRst_n -- TX collision retry counter reset
-- TxColRetryCntEnbl -- TX collision retry counter enable
-- TxNibbleCntRst -- TX nibble counter reset
-- TxEnNibbleCnt -- TX nibble count
-- TxNibbleCntLd -- TX nibble counter load
-- BusFifoWrCntRst -- Bus FIFO write counter reset
-- BusFifoWrCntEn -- Bus FIFO write counter enable
-- EnblPre -- Enable Preamble
-- EnblSFD -- Enable SFD
-- EnblData -- Enable Data
-- EnblJam -- Enable Jam
-- EnblCRC -- Enable CRC
-- BusFifoWr -- Bus FIFO write enable
-- Phytx_en -- PHY transmit enable
-- TxCrcEn -- TX CRC enable
-- TxCrcShftOutEn -- TX CRC shift out enable
-- Tx_addr_en -- TX buffer address enable
-- Tx_start -- Trasnmit start
-- Tx_done -- Transmit done
-- Tx_idle -- Transmit idle
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Enblclear -- Enable clear
-- Transmit_start -- Transmit start
-- Mac_program_start -- MAC Program start
-- Mac_addr_ram_we -- MAC Address RAM write enable
-- Mac_addr_ram_addr_wr -- MAC Address RAM write address
-- Pre_sfd_done -- Pre SFD done
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity tx_statemachine is
generic
(
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port
(
Clk : in std_logic;
Rst : in std_logic;
TxClkEn : in std_logic;
Jam_rst : out std_logic;
TxRst : in std_logic;
Deferring : in std_logic;
ColRetryCnt : in std_logic_vector (0 to 4);
ColWindowNibCnt : in std_logic_vector (0 to 7);
JamTxNibCnt : in std_logic_vector (0 to 3);
TxNibbleCnt : in std_logic_vector (0 to 11);
BusFifoWrNibbleCnt : in std_logic_vector (0 to 11);
CrcCnt : in std_logic_vector (0 to 3);
BusFifoFull : in std_logic;
BusFifoEmpty : in std_logic;
PhyCollision : in std_logic;
Tx_pong_ping_l : in std_logic;
InitBackoff : out std_logic;
TxRetryRst : out std_logic;
TxExcessDefrlRst : out std_logic;
TxLateColnRst : out std_logic;
TxColRetryCntRst_n : out std_logic;
TxColRetryCntEnbl : out std_logic;
TxNibbleCntRst : out std_logic;
TxEnNibbleCnt : out std_logic;
TxNibbleCntLd : out std_logic;
BusFifoWrCntRst : out std_logic;
BusFifoWrCntEn : out std_logic;
EnblPre : out std_logic;
EnblSFD : out std_logic;
EnblData : out std_logic;
EnblJam : out std_logic;
EnblCRC : out std_logic;
BusFifoWr : out std_logic;
Phytx_en : out std_logic;
TxCrcEn : out std_logic;
TxCrcShftOutEn : out std_logic;
Tx_addr_en : out std_logic;
Tx_start : out std_logic;
Tx_done : out std_logic;
Tx_idle : out std_logic;
Tx_DPM_ce : out std_logic;
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Enblclear : out std_logic;
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Mac_addr_ram_we : out std_logic;
Mac_addr_ram_addr_wr : out std_logic_vector(0 to 3);
Pre_sfd_done : out std_logic
);
end tx_statemachine;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of tx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal idle : std_logic; -- state 0
signal lngthDelay1 : std_logic; -- state 5
signal lngthDelay2 : std_logic; -- state 6
signal ldLngthCntr : std_logic; -- state 7
signal preamble : std_logic; -- state 8
signal checkBusFifoFullSFD : std_logic; -- state 9
signal SFD : std_logic; -- state 10
signal checkBusFifoFull : std_logic; -- state 11
signal loadBusFifo : std_logic; -- state 12
signal checkCrc : std_logic; -- state 13
signal checkBusFifoFullCrc : std_logic; -- state 14
signal loadBusFifoCrc : std_logic; -- state 15
signal waitFifoEmpty : std_logic; -- state 16
signal txDone : std_logic; -- state 17
signal checkBusFifoFullJam : std_logic; -- state 18
signal loadBusFifoJam : std_logic; -- state 19
signal half_dup_error : std_logic; -- state 20
signal collisionRetry : std_logic; -- state 21
signal retryWaitFifoEmpty : std_logic; -- state 22
signal retryReset : std_logic; -- state 23
signal txDone2 : std_logic; -- state 24
signal txDonePause : std_logic; -- state 25
signal chgMacAdr1 : std_logic; -- state 26
signal chgMacAdr2 : std_logic; -- state 27
signal chgMacAdr3 : std_logic; -- state 28
signal chgMacAdr4 : std_logic; -- state 29
signal chgMacAdr5 : std_logic; -- state 30
signal chgMacAdr6 : std_logic; -- state 31
signal chgMacAdr7 : std_logic; -- state 32
signal chgMacAdr8 : std_logic; -- state 33
signal chgMacAdr9 : std_logic; -- state 34
signal chgMacAdr10 : std_logic; -- state 35
signal chgMacAdr11 : std_logic; -- state 36
signal chgMacAdr12 : std_logic; -- state 37
signal chgMacAdr13 : std_logic; -- state 38
signal chgMacAdr14 : std_logic; -- state 39
signal idle_D : std_logic; -- state 0
signal txLngthRdNib1_D : std_logic; -- state 1
signal lngthDelay1_D : std_logic; -- state 5
signal lngthDelay2_D : std_logic; -- state 6
signal ldLngthCntr_D : std_logic; -- state 7
signal preamble_D : std_logic; -- state 8
signal checkBusFifoFullSFD_D : std_logic; -- state 9
signal SFD_D : std_logic; -- state 10
signal checkBusFifoFull_D : std_logic; -- state 11
signal loadBusFifo_D : std_logic; -- state 12
signal checkCrc_D : std_logic; -- state 13
signal checkBusFifoFullCrc_D : std_logic; -- state 14
signal loadBusFifoCrc_D : std_logic; -- state 15
signal waitFifoEmpty_D : std_logic; -- state 16
signal txDone_D : std_logic; -- state 17
signal checkBusFifoFullJam_D : std_logic; -- state 18
signal loadBusFifoJam_D : std_logic; -- state 19
signal half_dup_error_D : std_logic; -- state 20
signal collisionRetry_D : std_logic; -- state 21
signal retryWaitFifoEmpty_D : std_logic; -- state 22
signal retryReset_D : std_logic; -- state 23
signal txDone2_D : std_logic; -- state 24
signal txDonePause_D : std_logic; -- state 25
signal chgMacAdr1_D : std_logic; -- state 26
signal chgMacAdr2_D : std_logic; -- state 27
signal chgMacAdr3_D : std_logic; -- state 28
signal chgMacAdr4_D : std_logic; -- state 29
signal chgMacAdr5_D : std_logic; -- state 30
signal chgMacAdr6_D : std_logic; -- state 31
signal chgMacAdr7_D : std_logic; -- state 32
signal chgMacAdr8_D : std_logic; -- state 33
signal chgMacAdr9_D : std_logic; -- state 34
signal chgMacAdr10_D : std_logic; -- state 35
signal chgMacAdr11_D : std_logic; -- state 36
signal chgMacAdr12_D : std_logic; -- state 37
signal chgMacAdr13_D : std_logic; -- state 38
signal chgMacAdr14_D : std_logic; -- state 39
signal txNibbleCntRst_i : std_logic;
signal txEnNibbleCnt_i : std_logic;
signal txNibbleCntLd_i : std_logic;
signal busFifoWr_i : std_logic;
signal phytx_en_i : std_logic;
signal phytx_en_i_n : std_logic;
signal txCrcEn_i : std_logic;
signal retrying_i : std_logic;
signal phytx_en_reg : std_logic;
signal busFifoWrCntRst_reg : std_logic;
signal retrying_reg : std_logic;
signal txCrcEn_reg : std_logic;
signal busFifoWrCntRst_i : std_logic;
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal goto_idle : std_logic; -- state 0
signal stay_idle : std_logic; -- state 0
signal goto_txLngthRdNib1_1 : std_logic; -- state 1
signal goto_txLngthRdNib1_2 : std_logic; -- state 1
signal goto_lngthDelay1 : std_logic; -- state 5
signal goto_lngthDelay2 : std_logic; -- state 6
signal goto_ldLngthCntr : std_logic; -- state 7
signal stay_ldLngthCntr : std_logic; -- state 7
signal goto_preamble : std_logic; -- state 8
signal stay_preamble : std_logic; -- state 8
signal goto_checkBusFifoFullSFD : std_logic; -- state 9
signal stay_checkBusFifoFullSFD : std_logic; -- state 9
signal goto_SFD : std_logic; -- state 10
signal stay_SFD : std_logic; -- state 10
signal goto_checkBusFifoFull_1 : std_logic; -- state 11
signal goto_checkBusFifoFull_2 : std_logic; -- state 11
signal stay_checkBusFifoFull : std_logic; -- state 11
signal goto_loadBusFifo : std_logic; -- state 12
signal goto_checkCrc : std_logic; -- state 13
signal goto_checkBusFifoFullCrc_1 : std_logic; -- state 14
signal goto_checkBusFifoFullCrc_2 : std_logic; -- state 14
signal stay_checkBusFifoFullCrc : std_logic; -- state 14
signal goto_loadBusFifoCrc_1 : std_logic; -- state 15
signal goto_waitFifoEmpty_2 : std_logic; -- state 16
signal stay_waitFifoEmpty : std_logic; -- state 16
signal goto_txDone_1 : std_logic; -- state 17
signal goto_txDone_2 : std_logic; -- state 17
signal goto_checkBusFifoFullJam_1 : std_logic; -- state 18
signal goto_checkBusFifoFullJam_2 : std_logic; -- state 18
signal stay_checkBusFifoFullJam : std_logic; -- state 18
signal goto_loadBusFifoJam : std_logic; -- state 19
signal goto_half_dup_error_1 : std_logic; -- state 20
signal goto_half_dup_error_2 : std_logic; -- state 20
signal goto_collisionRetry : std_logic; -- state 21
signal goto_retryWaitFifoEmpty : std_logic; -- state 22
signal stay_retryWaitFifoEmpty : std_logic; -- state 22
signal goto_retryReset : std_logic; -- state 23
signal goto_txDone2 : std_logic; -- state 24
signal goto_txDonePause : std_logic; -- state 25
signal goto_chgMacAdr1 : std_logic; -- state 26
signal goto_chgMacAdr2 : std_logic; -- state 27
signal goto_chgMacAdr3 : std_logic; -- state 28
signal goto_chgMacAdr4 : std_logic; -- state 29
signal goto_chgMacAdr5 : std_logic; -- state 30
signal goto_chgMacAdr6 : std_logic; -- state 31
signal goto_chgMacAdr7 : std_logic; -- state 32
signal goto_chgMacAdr8 : std_logic; -- state 33
signal goto_chgMacAdr9 : std_logic; -- state 34
signal goto_chgMacAdr10 : std_logic; -- state 35
signal goto_chgMacAdr11 : std_logic; -- state 36
signal goto_chgMacAdr12 : std_logic; -- state 37
signal goto_chgMacAdr13 : std_logic; -- state 38
signal goto_chgMacAdr14 : std_logic; -- state 39
signal txNibbleCnt_is_1 : std_logic;
signal busFifoWrNibbleCnt_is_14 : std_logic;
signal busFifoWrNibbleCnt_not_14 : std_logic;
signal busFifoWrNibbleCnt_is_15 : std_logic;
signal busFifoWrNibbleCnt_not_15 : std_logic;
signal crcCnt_not_0 : std_logic;
signal crcCnt_is_0 : std_logic;
signal jamTxNibCnt_not_0 : std_logic;
signal jamTxNibCnt_is_0 : std_logic;
signal colWindowNibCnt_not_0 : std_logic;
signal colWindowNibCnt_is_0 : std_logic;
signal colRetryCnt_is_15 : std_logic;
signal pre_SFD_zero : std_logic;
signal waitdone_pre_sfd : std_logic;
signal transmit_start_reg : std_logic;
signal mac_program_start_reg : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the tx state machine
component FDR
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
Tx_DPM_wr_data <= (others => '0');
-- Trnasmit Done indicator
-- added txDone for ping pong control
Tx_done <= txDone and not retrying_reg;
-- Full/Half duplex indicator
full_half_n <= '1'when C_DUPLEX = 1 else '0';
-- Wait for Pre SFD
--waitdone_pre_sfd <= PhyCollision and not(full_half_n) and not(pre_sfd_zero);
Pre_sfd_done <= pre_SFD_zero;
-- PHY tx enable
phytx_en_i_n <= not(phytx_en_i);
----------------------------------------------------------------------------
-- Signal Assignment
----------------------------------------------------------------------------
TxNibbleCntRst <= txNibbleCntRst_i;
TxEnNibbleCnt <= txEnNibbleCnt_i;
TxNibbleCntLd <= txNibbleCntLd_i;
BusFifoWr <= busFifoWr_i;
Phytx_en <= phytx_en_i;
TxCrcEn <= txCrcEn_i;
BusFifoWrCntRst <= busFifoWrCntRst_i;
----------------------------------------------------------------------------
-- Pre SFD Counter
----------------------------------------------------------------------------
PRE_SFD_count: entity axi_ethernetlite_v3_0.cntr5bit
port map
(
cntout => open,
Clk => Clk,
Rst => Rst,
en => TxClkEn,
ld => phytx_en_i_n,
load_in => "10011",
zero => pre_SFD_zero
);
-- State machine reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- Counter enable generation
----------------------------------------------------------------------------
-- Transmit Nibble Counte=1
txNibbleCnt_is_1 <= not(TxNibbleCnt(0)) and not(TxNibbleCnt(1)) and
not(TxNibbleCnt(2)) and not(TxNibbleCnt(3)) and
not(TxNibbleCnt(4)) and not(TxNibbleCnt(5)) and
not(TxNibbleCnt(6)) and not(TxNibbleCnt(7)) and
not(TxNibbleCnt(8)) and not(TxNibbleCnt(9)) and
not(TxNibbleCnt(10))and TxNibbleCnt(11);
-- Bus FIFO write Nibble Counte=14
busFifoWrNibbleCnt_is_14 <= BusFifoWrNibbleCnt(8) and
BusFifoWrNibbleCnt(9) and
BusFifoWrNibbleCnt(10) and
not(BusFifoWrNibbleCnt(11));
-- Bus FIFO write Nibble Counte/=14
busFifoWrNibbleCnt_not_14 <= not(busFifoWrNibbleCnt_is_14);
-- Bus FIFO write Nibble Counte=15
busFifoWrNibbleCnt_is_15 <= (BusFifoWrNibbleCnt(8) and
BusFifoWrNibbleCnt(9) and
BusFifoWrNibbleCnt(10) and
BusFifoWrNibbleCnt(11));
-- Bus FIFO write Nibble Counte/=15
busFifoWrNibbleCnt_not_15 <= not(busFifoWrNibbleCnt_is_15);
-- CRC Count/=0
crcCnt_not_0 <= CrcCnt(0) or CrcCnt(1) or CrcCnt(2) or CrcCnt(3);
-- CRC Count=0
crcCnt_is_0 <= not crcCnt_not_0;
-- Jam Transmit Nibble count/=0
jamTxNibCnt_not_0 <= JamTxNibCnt(0) or JamTxNibCnt(1) or JamTxNibCnt(2) or
JamTxNibCnt(3);
-- Jam Transmit Nibble count=0
jamTxNibCnt_is_0 <= not(jamTxNibCnt_not_0);
-- Collision windo Nibble count/=0
colWindowNibCnt_not_0 <= ColWindowNibCnt(0) or ColWindowNibCnt(1) or
ColWindowNibCnt(2) or ColWindowNibCnt(3) or
ColWindowNibCnt(4) or ColWindowNibCnt(5) or
ColWindowNibCnt(6) or ColWindowNibCnt(7);
-- Collision windo Nibble count=0
colWindowNibCnt_is_0 <= not(colWindowNibCnt_not_0);
-- Collision retry count=15
colRetryCnt_is_15 <= not(ColRetryCnt(0)) and ColRetryCnt(1) and
ColRetryCnt(2) and ColRetryCnt(3) and
ColRetryCnt(4);
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle <= txDonePause;
stay_idle <= idle and not(Transmit_start) and not Mac_program_start;
idle_D <= goto_idle or stay_idle;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
STATE0A: FDS
port map
(
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
Tx_idle <= idle;
----------------------------------------------------------------------------
-- txLngthRdNib1 state
----------------------------------------------------------------------------
--goto_txLngthRdNib1_1 <= idle and Transmit_start and not transmit_start_reg;
goto_txLngthRdNib1_1 <= idle and
((transmit_start and not transmit_start_reg)
or
(transmit_start and retrying_reg));
goto_txLngthRdNib1_2 <= retryReset;
txLngthRdNib1_D <= goto_txLngthRdNib1_1 or goto_txLngthRdNib1_2;
goto_lngthDelay1 <= txLngthRdNib1_D;
----------------------------------------------------------------------------
-- lngthDelay1 state
----------------------------------------------------------------------------
lngthDelay1_D <= goto_lngthDelay1;
STATE5A: FDR
port map
(
Q => lngthDelay1, --[out]
C => Clk, --[in]
D => lngthDelay1_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- lngthDelay2 state
----------------------------------------------------------------------------
goto_lngthDelay2 <= lngthDelay1;
lngthDelay2_D <= goto_lngthDelay2;
STATE6A: FDR
port map
(
Q => lngthDelay2, --[out]
C => Clk, --[in]
D => lngthDelay2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- ldLngthCntr state
----------------------------------------------------------------------------
goto_ldLngthCntr <= lngthDelay1;
stay_ldLngthCntr <= ldLngthCntr and Deferring;
ldLngthCntr_D <= goto_ldLngthCntr or stay_ldLngthCntr;
STATE7A: FDR
port map
(
Q => ldLngthCntr, --[out]
C => Clk, --[in]
D => ldLngthCntr_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- preamble state
----------------------------------------------------------------------------
goto_preamble <= (ldLngthCntr and (not(Deferring)));
stay_preamble <= preamble and busFifoWrNibbleCnt_not_14;
preamble_D <= goto_preamble or stay_preamble;
STATE8A: FDR
port map
(
Q => preamble, --[out]
C => Clk, --[in]
D => preamble_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullSFD state
----------------------------------------------------------------------------
goto_checkBusFifoFullSFD <= preamble and busFifoWrNibbleCnt_is_14;
stay_checkBusFifoFullSFD <= checkBusFifoFullSFD and BusFifoFull;
checkBusFifoFullSFD_D <= goto_checkBusFifoFullSFD or
stay_checkBusFifoFullSFD;
STATE9A: FDR
port map
(
Q => checkBusFifoFullSFD, --[out]
C => Clk, --[in]
D => checkBusFifoFullSFD_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- SFD state
----------------------------------------------------------------------------
goto_SFD <= checkBusFifoFullSFD and not (BusFifoFull);
stay_SFD <= SFD and busFifoWrNibbleCnt_not_15;
SFD_D <= goto_SFD or stay_SFD;
STATE10A: FDR
port map
(
Q => SFD, --[out]
C => Clk, --[in]
D => SFD_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFull state
----------------------------------------------------------------------------
goto_checkBusFifoFull_1 <= loadBusFifo and not(goto_checkCrc) and
not(goto_checkBusFifoFullJam_1);
goto_checkBusFifoFull_2 <= SFD and busFifoWrNibbleCnt_is_15;
stay_checkBusFifoFull <= checkBusFifoFull and BusFifoFull and
not (goto_checkBusFifoFullJam_1);
checkBusFifoFull_D <= goto_checkBusFifoFull_1 or
goto_checkBusFifoFull_2 or
stay_checkBusFifoFull;
STATE11A: FDR
port map
(
Q => checkBusFifoFull, --[out]
C => Clk, --[in]
D => checkBusFifoFull_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifo state
----------------------------------------------------------------------------
goto_loadBusFifo <= checkBusFifoFull and not(BusFifoFull) and
not(goto_checkCrc) and not(goto_checkBusFifoFullJam_1);
loadBusFifo_D <= goto_loadBusFifo;
STATE12A: FDR
port map
(
Q => loadBusFifo, --[out]
C => Clk, --[in]
D => loadBusFifo_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkCrc state
----------------------------------------------------------------------------
goto_checkCrc <= loadBusFifo and txNibbleCnt_is_1 and
not(goto_checkBusFifoFullJam_1);
checkCrc_D <= goto_checkCrc;
STATE13A: FDR
port map
(
Q => checkCrc, --[out]
C => Clk, --[in]
D => checkCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullCrc state
----------------------------------------------------------------------------
goto_checkBusFifoFullCrc_1 <= checkCrc and not(goto_checkBusFifoFullJam_1);
goto_checkBusFifoFullCrc_2 <= loadBusFifoCrc and
not(goto_checkBusFifoFullJam_1);
stay_checkBusFifoFullCrc <= checkBusFifoFullCrc and BusFifoFull and
not(goto_checkBusFifoFullJam_1);
checkBusFifoFullCrc_D <= goto_checkBusFifoFullCrc_1 or
goto_checkBusFifoFullCrc_2 or
stay_checkBusFifoFullCrc;
STATE14A: FDR
port map
(
Q => checkBusFifoFullCrc, --[out]
C => Clk, --[in]
D => checkBusFifoFullCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifoCrc state
----------------------------------------------------------------------------
goto_loadBusFifoCrc_1 <= checkBusFifoFullCrc and not(BusFifoFull) and
crcCnt_not_0 and not(goto_checkBusFifoFullJam_1);
loadBusFifoCrc_D <= goto_loadBusFifoCrc_1;
STATE15A: FDR
port map
(
Q => loadBusFifoCrc, --[out]
C => Clk, --[in]
D => loadBusFifoCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitFifoEmpty state
----------------------------------------------------------------------------
goto_waitFifoEmpty_2 <= checkBusFifoFullCrc and crcCnt_is_0 and
not(BusFifoFull) and not(goto_checkBusFifoFullJam_1);
stay_waitFifoEmpty <= waitFifoEmpty and not(BusFifoEmpty) and
not(goto_checkBusFifoFullJam_1);
waitFifoEmpty_D <= goto_waitFifoEmpty_2 or stay_waitFifoEmpty;
STATE16A: FDR
port map
(
Q => waitFifoEmpty, --[out]
C => Clk, --[in]
D => waitFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDone state
----------------------------------------------------------------------------
goto_txDone_1 <= waitFifoEmpty and BusFifoEmpty and
not(goto_checkBusFifoFullJam_1);
goto_txDone_2 <= half_dup_error or chgMacAdr14;
txDone_D <= goto_txDone_1 or goto_txDone_2;
STATE17A: FDR
port map
(
Q => txDone, --[out]
C => Clk, --[in]
D => txDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullJam state
----------------------------------------------------------------------------
goto_checkBusFifoFullJam_1 <= (checkBusFifoFull or loadBusFifo or checkCrc
or checkBusFifoFullCrc or waitFifoEmpty) and
PhyCollision and not(full_half_n);
goto_checkBusFifoFullJam_2 <= loadBusFifoJam;
stay_checkBusFifoFullJam <= checkBusFifoFullJam and (BusFifoFull or
not(pre_SFD_zero));
checkBusFifoFullJam_D <= goto_checkBusFifoFullJam_1 or
goto_checkBusFifoFullJam_2 or
stay_checkBusFifoFullJam;
STATE18A: FDR
port map
(
Q => checkBusFifoFullJam, --[out]
C => Clk, --[in]
D => checkBusFifoFullJam_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifoJam state
----------------------------------------------------------------------------
goto_loadBusFifoJam <= checkBusFifoFullJam and
not(stay_checkBusFifoFullJam) and
jamTxNibCnt_not_0;
loadBusFifoJam_D <= goto_loadBusFifoJam;
STATE19A: FDR
port map
(
Q => loadBusFifoJam, --[out]
C => Clk, --[in]
D => loadBusFifoJam_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- half_dup_error state
----------------------------------------------------------------------------
goto_half_dup_error_1 <= checkBusFifoFullJam and not(BusFifoFull or
not(pre_SFD_zero)) and jamTxNibCnt_is_0 and
colWindowNibCnt_not_0 and colRetryCnt_is_15;
goto_half_dup_error_2 <= checkBusFifoFullJam and not(BusFifoFull or
not(pre_SFD_zero)) and jamTxNibCnt_is_0 and
colWindowNibCnt_is_0;
half_dup_error_D <= goto_half_dup_error_1 or goto_half_dup_error_2;
STATE20A: FDR
port map
(
Q => half_dup_error, --[out]
C => Clk, --[in]
D => half_dup_error_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- collisionRetry state
----------------------------------------------------------------------------
goto_collisionRetry <= checkBusFifoFullJam and not(stay_checkBusFifoFullJam)
and not(goto_half_dup_error_1) and
not(goto_half_dup_error_2) and
not(goto_loadBusFifoJam);
collisionRetry_D <= goto_collisionRetry;
STATE21A: FDR
port map
(
Q => collisionRetry, --[out]
C => Clk, --[in]
D => collisionRetry_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- retryWaitFifoEmpty state
----------------------------------------------------------------------------
goto_retryWaitFifoEmpty <= collisionRetry;
stay_retryWaitFifoEmpty <= retryWaitFifoEmpty and not(BusFifoEmpty);
retryWaitFifoEmpty_D <= goto_retryWaitFifoEmpty or stay_retryWaitFifoEmpty;
STATE22A: FDR
port map
(
Q => retryWaitFifoEmpty, --[out]
C => Clk, --[in]
D => retryWaitFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- retryReset state
----------------------------------------------------------------------------
goto_retryReset <= retryWaitFifoEmpty and BusFifoEmpty;
retryReset_D <= goto_retryReset;
STATE23A: FDR
port map
(
Q => retryReset, --[out]
C => Clk, --[in]
D => retryReset_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDone2 state
----------------------------------------------------------------------------
goto_txDone2 <= txDone;
txDone2_D <= goto_txDone2;
STATE24A: FDR
port map
(
Q => txDone2, --[out]
C => Clk, --[in]
D => txDone2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDonePause state
----------------------------------------------------------------------------
goto_txDonePause <= txDone2;
txDonePause_D <= goto_txDonePause;
STATE25A: FDR
port map
(
Q => txDonePause, --[out]
C => Clk, --[in]
D => txDonePause_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr1 state
----------------------------------------------------------------------------
goto_chgMacAdr1 <= idle and Mac_program_start and not mac_program_start_reg;
chgMacAdr1_D <= goto_chgMacAdr1 ;
STATE26A: FDR
port map
(
Q => chgMacAdr1, --[out]
C => Clk, --[in]
D => chgMacAdr1_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr2 state
----------------------------------------------------------------------------
goto_chgMacAdr2 <= chgMacAdr1;
chgMacAdr2_D <= goto_chgMacAdr2 ;
STATE27A: FDR
port map
(
Q => chgMacAdr2, --[out]
C => Clk, --[in]
D => chgMacAdr2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr3 state
----------------------------------------------------------------------------
goto_chgMacAdr3 <= chgMacAdr2;
chgMacAdr3_D <= goto_chgMacAdr3 ;
STATE28A: FDR
port map
(
Q => chgMacAdr3, --[out]
C => Clk, --[in]
D => chgMacAdr3_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr4 state
----------------------------------------------------------------------------
goto_chgMacAdr4 <= chgMacAdr3;
chgMacAdr4_D <= goto_chgMacAdr4 ;
STATE29A: FDR
port map
(
Q => chgMacAdr4, --[out]
C => Clk, --[in]
D => chgMacAdr4_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr5 state
----------------------------------------------------------------------------
goto_chgMacAdr5 <= chgMacAdr4;
chgMacAdr5_D <= goto_chgMacAdr5 ;
STATE30A: FDR
port map
(
Q => chgMacAdr5, --[out]
C => Clk, --[in]
D => chgMacAdr5_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr6 state
----------------------------------------------------------------------------
goto_chgMacAdr6 <= chgMacAdr5;
chgMacAdr6_D <= goto_chgMacAdr6 ;
STATE31A: FDR
port map
(
Q => chgMacAdr6, --[out]
C => Clk, --[in]
D => chgMacAdr6_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr7 state
----------------------------------------------------------------------------
goto_chgMacAdr7 <= chgMacAdr6;
chgMacAdr7_D <= goto_chgMacAdr7 ;
STATE32A: FDR
port map
(
Q => chgMacAdr7, --[out]
C => Clk, --[in]
D => chgMacAdr7_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr8 state
----------------------------------------------------------------------------
goto_chgMacAdr8 <= chgMacAdr7;
chgMacAdr8_D <= goto_chgMacAdr8 ;
STATE33A: FDR
port map
(
Q => chgMacAdr8, --[out]
C => Clk, --[in]
D => chgMacAdr8_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr9 state
----------------------------------------------------------------------------
goto_chgMacAdr9 <= chgMacAdr8;
chgMacAdr9_D <= goto_chgMacAdr9 ;
STATE34A: FDR
port map
(
Q => chgMacAdr9, --[out]
C => Clk, --[in]
D => chgMacAdr9_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr10 state
----------------------------------------------------------------------------
goto_chgMacAdr10 <= chgMacAdr9;
chgMacAdr10_D <= goto_chgMacAdr10 ;
STATE35A: FDR
port map
(
Q => chgMacAdr10, --[out]
C => Clk, --[in]
D => chgMacAdr10_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr11 state
----------------------------------------------------------------------------
goto_chgMacAdr11 <= chgMacAdr10;
chgMacAdr11_D <= goto_chgMacAdr11 ;
STATE36A: FDR
port map
(
Q => chgMacAdr11, --[out]
C => Clk, --[in]
D => chgMacAdr11_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr12 state
----------------------------------------------------------------------------
goto_chgMacAdr12 <= chgMacAdr11;
chgMacAdr12_D <= goto_chgMacAdr12 ;
STATE37A: FDR
port map
(
Q => chgMacAdr12, --[out]
C => Clk, --[in]
D => chgMacAdr12_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr13 state
----------------------------------------------------------------------------
goto_chgMacAdr13 <= chgMacAdr12;
chgMacAdr13_D <= goto_chgMacAdr13 ;
STATE38A: FDR
port map
(
Q => chgMacAdr13, --[out]
C => Clk, --[in]
D => chgMacAdr13_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr14 state
----------------------------------------------------------------------------
goto_chgMacAdr14 <= chgMacAdr13;
chgMacAdr14_D <= goto_chgMacAdr14 ;
STATE39A: FDR
port map
(
Q => chgMacAdr14, --[out]
C => Clk, --[in]
D => chgMacAdr14_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers all the signals on the bus clock.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
phytx_en_reg <= '0';
busFifoWrCntRst_reg <= '0';
retrying_reg <= '0';
txCrcEn_reg <= '0';
transmit_start_reg <= '0';
mac_program_start_reg <= '0';
else
phytx_en_reg <= phytx_en_i;
busFifoWrCntRst_reg <= busFifoWrCntRst_i;
retrying_reg <= retrying_i;
txCrcEn_reg <= txCrcEn_i;
transmit_start_reg <= Transmit_start;
mac_program_start_reg <= Mac_program_start;
end if;
end if;
end process REG_PROCESS;
----------------------------------------------------------------------------
-- COMB_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
COMB_PROCESS : process (phytx_en_reg, busFifoWrCntRst_reg,
txCrcEn_reg, txDone, idle, preamble,
half_dup_error, checkBusFifoFull,
collisionRetry, retrying_reg,
checkBusFifoFullCrc, SFD, loadBusFifoCrc,
checkBusFifoFullSFD)
begin
-- Generate PHY Tx Enable
if (txDone='1' or idle='1') then
phytx_en_i <= '0';
elsif (preamble = '1') then
phytx_en_i <= '1';
else
phytx_en_i <= phytx_en_reg;
end if;
-- Generate BusFifo Write Counter reset
if (half_dup_error='1' or txDone='1' or idle='1') then
busFifoWrCntRst_i <= '1';
elsif (preamble = '1') then
busFifoWrCntRst_i <= '0';
else
busFifoWrCntRst_i <= busFifoWrCntRst_reg;
end if;
-- Generate retry signal in case of collision
if (collisionRetry='1') then
retrying_i <= '1';
elsif (idle = '1') then
retrying_i <= '0';
else
retrying_i <= retrying_reg;
end if;
-- Generate transmit CRC enable
if (checkBusFifoFull='1') then
txCrcEn_i <= '1';
elsif (checkBusFifoFullSFD='1' or checkBusFifoFullCRC='1' or SFD='1' or
idle='1' or loadBusFifoCrc='1' or preamble='1') then
txCrcEn_i <= '0';
else
txCrcEn_i <= txCrcEn_reg;
end if;
end process COMB_PROCESS;
----------------------------------------------------------------------------
-- FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine for
-- transmit operation
----------------------------------------------------------------------------
FSMD_PROCESS : process(crcCnt_is_0, JamTxNibCnt, goto_checkBusFifoFullCrc_1,
pre_SFD_zero, checkBusFifoFullJam, full_half_n,
retryReset, txDonePause, loadBusFifo, loadBusFifoJam,
checkCrc, txDone2, chgMacAdr2, chgMacAdr3,
chgMacAdr4, chgMacAdr5, chgMacAdr6, chgMacAdr7,
chgMacAdr8, chgMacAdr9, chgMacAdr10, chgMacAdr11,
chgMacAdr12, chgMacAdr13, chgMacAdr14, chgMacAdr1,
lngthDelay1, lngthDelay2, idle, checkBusFifoFull,
txDone, ldLngthCntr,half_dup_error, collisionRetry,
checkBusFifoFullCrc, loadBusFifoCrc, retrying_reg,
preamble, SFD)
begin
-- Enable JAM reset
if (checkBusFifoFullJam = '1' and pre_SFD_zero = '1' and
full_half_n = '0' and (JamTxNibCnt = "0111")) then
Jam_rst <= '1';
else
Jam_rst <= '0';
end if;
-- Bus FIFO write counte enable
BusFifoWrCntEn <= '1'; -- temp
-- Enable TX late collision reset
TxLateColnRst <= '0';
-- Enable TX deffer reset
TxExcessDefrlRst <= '0';
-- Enable back off and TX collision retry counter
if (collisionRetry = '1') then
InitBackoff <= '1';
TxColRetryCntEnbl <= '1';
else
InitBackoff <= '0';
TxColRetryCntEnbl <= '0';
end if;
-- Enable TX retry reset
if (retryReset = '1') or
(txDonePause = '1') then -- clear up any built up garbage in async
-- FIFOs at the end of a packet
TxRetryRst <= '1';
else
TxRetryRst <= '0';
end if;
-- Enable TX nibble counter reset
if (idle = '1') then
txNibbleCntRst_i <= '1';
else
txNibbleCntRst_i <= '0';
end if;
-- Enable TX collision retry reset
if (idle = '1' and retrying_reg = '0') then
TxColRetryCntRst_n <= '0';
else
TxColRetryCntRst_n <= '1';
end if;
-- Enable TX CRC counter shift
if ((checkBusFifoFullCrc = '1') or (loadBusFifoCrc = '1')) then
TxCrcShftOutEn <= '1';
else
TxCrcShftOutEn <= '0';
end if;
-- Enable Preamble in the frame
if (preamble = '1') then
EnblPre <= '1';
else
EnblPre <= '0';
end if;
-- Enable SFD in the frame
if (SFD = '1') then
EnblSFD <= '1';
else
EnblSFD <= '0';
end if;
-- Enable Data in the frame
if (loadBusFifo = '1') then
EnblData <= '1';
else
EnblData <= '0';
end if;
-- Enable CRC
if (loadBusFifoCrc = '1') then
EnblCRC <= '1';
else
EnblCRC <= '0';
end if;
-- Enable TX nibble counter load
if (SFD = '1') then
txNibbleCntLd_i <= '1';
else
txNibbleCntLd_i <= '0';
end if;
-- Enable clear for TX interface FIFO
if (checkBusFifoFullCrc = '1' and crcCnt_is_0 = '1') or
((checkBusFifoFullJam='1' or loadBusFifoJam='1')
and pre_SFD_zero = '1' and full_half_n = '0') or
(collisionRetry = '1' ) or (half_dup_error = '1') or
(checkCrc = '1' and goto_checkBusFifoFullCrc_1 = '0') then
Enblclear <= '1';
else
Enblclear <= '0';
end if;
-- Enable Bus FIFO write
if ((loadBusFifo = '1') or
(preamble = '1') or
(SFD = '1') or
(loadBusFifoCrc = '1')
) then
busFifoWr_i <= '1';
else
busFifoWr_i <= '0';
end if;
-- Enable JAM TX nibble
if (loadBusFifo = '1') then
txEnNibbleCnt_i <= '1';
else
txEnNibbleCnt_i <= '0';
end if;
-- Enable TX buffer address increment
if (loadBusFifo = '1') or (chgMacAdr2 = '1') or (chgMacAdr3 = '1') or
(chgMacAdr4 = '1') or (chgMacAdr5 = '1') or (chgMacAdr6 = '1') or
(chgMacAdr7 = '1') or (chgMacAdr8 = '1') or (chgMacAdr9 = '1') or
(chgMacAdr10 = '1') or (chgMacAdr11 = '1') or (chgMacAdr12 = '1') or
(chgMacAdr13 = '1') or (chgMacAdr14 = '1') then
Tx_addr_en <= '1';
else
Tx_addr_en <= '0';
end if;
-- Generate TX start after preamble
if (preamble = '1') or
(chgMacAdr1 = '1') then
Tx_start <= '1'; -- reset address to 0 for start of transmit
else
Tx_start <= '0';
end if;
-- TX DPM buffer CE
if (idle = '1') or
(lngthDelay1 = '1') or (lngthDelay2 = '1') or
(checkBusFifoFull = '1') or (ldLngthCntr = '1') or
(txDone = '1') or (txDone2 = '1') or (txDonePause = '1') or
(chgMacAdr1 = '1') or (chgMacAdr2 = '1') or (chgMacAdr3 = '1') or
(chgMacAdr4 = '1') or (chgMacAdr5 = '1') or (chgMacAdr6 = '1') or
(chgMacAdr7 = '1') or (chgMacAdr8 = '1') or (chgMacAdr9 = '1') or
(chgMacAdr10 = '1') or (chgMacAdr11 = '1') or (chgMacAdr12 = '1') or
(chgMacAdr13 = '1') or (chgMacAdr14 = '1') then
Tx_DPM_ce <= '1';
else
Tx_DPM_ce <= '0';
end if;
-- Enable JAM
if (loadBusFifoJam = '1') then
EnblJam <= '1';
else
EnblJam <= '0';
end if;
-- TX DPM write enable
Tx_DPM_wr_rd_n <= '0';
end process FSMD_PROCESS;
----------------------------------------------------------------------------
-- OUTPUT_REG1
----------------------------------------------------------------------------
-- This process generate mack address RAM write enable
----------------------------------------------------------------------------
OUTPUT_REG1:process (Clk)
begin
if (Clk'event and Clk='1') then
if (Rst = '1') then
Mac_addr_ram_we <= '0';
elsif (idle_D = '1') then
Mac_addr_ram_we <= '0';
elsif (chgMacAdr3_D = '1') or
(chgMacAdr4_D = '1') or
(chgMacAdr5_D = '1') or
(chgMacAdr6_D = '1') or
(chgMacAdr7_D = '1') or
(chgMacAdr8_D = '1') or
(chgMacAdr9_D = '1') or
(chgMacAdr10_D = '1') or
(chgMacAdr11_D = '1') or
(chgMacAdr12_D = '1') or
(chgMacAdr13_D = '1') or
(chgMacAdr14_D = '1') then
Mac_addr_ram_we <= '1';
else
Mac_addr_ram_we <= '0';
end if;
end if;
end process OUTPUT_REG1;
----------------------------------------------------------------------------
-- OUTPUT_REG2
----------------------------------------------------------------------------
-- This process MAC Addr RAM write Adrress to update the MAC address of
-- EMACLite Core.
----------------------------------------------------------------------------
OUTPUT_REG2:process (Clk)
begin
if (Clk'event and Clk='1') then
if (Rst = '1') then
Mac_addr_ram_addr_wr <= x"0";
else
if idle_D = '1' then
Mac_addr_ram_addr_wr <= x"0";
elsif chgMacAdr3_D = '1' then
Mac_addr_ram_addr_wr <= x"0";
elsif chgMacAdr4_D = '1' then
Mac_addr_ram_addr_wr <= x"1";
elsif chgMacAdr5_D = '1' then
Mac_addr_ram_addr_wr <= x"2";
elsif chgMacAdr6_D = '1' then
Mac_addr_ram_addr_wr <= x"3";
elsif chgMacAdr7_D = '1' then
Mac_addr_ram_addr_wr <= x"4";
elsif chgMacAdr8_D = '1' then
Mac_addr_ram_addr_wr <= x"5";
elsif chgMacAdr9_D = '1' then
Mac_addr_ram_addr_wr <= x"6";
elsif chgMacAdr10_D = '1' then
Mac_addr_ram_addr_wr <= x"7";
elsif chgMacAdr11_D = '1' then
Mac_addr_ram_addr_wr <= x"8";
elsif chgMacAdr12_D = '1' then
Mac_addr_ram_addr_wr <= x"9";
elsif chgMacAdr13_D = '1' then
Mac_addr_ram_addr_wr <= x"a";
elsif chgMacAdr14_D = '1' then
Mac_addr_ram_addr_wr <= x"b";
else
Mac_addr_ram_addr_wr <= x"0";
end if;
end if;
end if;
end process OUTPUT_REG2;
end implementation;
| gpl-3.0 | 41f770a216a4ea971482f542dfcfbbc8 | 0.417726 | 5.02355 | false | false | false | false |
h397wang/Lab2 | Fanzhe/lab3.vhd | 1 | 1,037 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Lab3 is port (
ledr: out std_logic_vector(1 downto 0); -- displays the operator and result on the other end
ledg: out std_logic_vector(0 downto 0);
sw : in std_logic_vector(3 downto 0); -- 4 dip switches
);
end Lab3;
architecture SimpleCircuit of Lab3 is
-- signal declaration
signal Current, NextF: std_logic_vector(1 downto 0);
signal Enable, Down, Up: std_logic_vector(0 downto 0);
begin
CurrentFloor <= sw(1 downto 0);
NextFloor <= sw(3 downto 2);
-- w is current[1]
-- x is current[0]
-- y is next[1]
-- z is next[0]
Down <= (Current(1) and not NextF and NextF(0)) or
(Current(1) and Current(0)and NextF(1) and not NextF(0));
Up <= (not Current(1) and Current(0) and NextF(1)) or
(current(1) and not Current(0) and NextF(1) and NextF(0));
-- motor = (w'x' + y'z')' is this correct? consider when Current == NextF
-- down = w y' z + w x y z'
-- up = w'xy + wx'yz
end SimpleCircuit
| apache-2.0 | 7bf9bf4c7be9386f948e35f5eb1a6133 | 0.634523 | 2.912921 | false | false | false | false |
hoangt/PoC | src/common/utils.vhdl | 1 | 29,273 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
package utils is
-- PoC settings
-- ==========================================================================
constant POC_VERBOSE : BOOLEAN := MY_VERBOSE;
-- Environment
-- ==========================================================================
-- Distinguishes simulation from synthesis
constant SIMULATION : BOOLEAN; -- deferred constant declaration
-- Type declarations
-- ==========================================================================
--+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++
type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN;
type T_INTVEC is array(NATURAL range <>) of INTEGER;
type T_NATVEC is array(NATURAL range <>) of NATURAL;
type T_POSVEC is array(NATURAL range <>) of POSITIVE;
type T_REALVEC is array(NATURAL range <>) of REAL;
--+ Integer subranges sometimes useful for speeding up simulation ++++++++++
subtype T_INT_8 is INTEGER range -128 to 127;
subtype T_INT_16 is INTEGER range -32768 to 32767;
subtype T_UINT_8 is INTEGER range 0 to 255;
subtype T_UINT_16 is INTEGER range 0 to 65535;
--+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Intellectual Property (IP) type
type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT);
-- Bit Order
type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST);
-- Byte Order (Endian)
type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN);
-- rounding style
type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
type T_BCD is array(3 downto 0) of std_logic;
type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD;
constant C_BCD_MINUS : T_BCD := "1010";
constant C_BCD_OFF : T_BCD := "1011";
-- Function declarations
-- ==========================================================================
--+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(a / b)
function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL;
--+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- is input a power of 2?
function is_pow2(int : NATURAL) return BOOLEAN;
-- round to next power of 2
function ceil_pow2(int : NATURAL) return POSITIVE;
-- round to previous power of 2
function floor_pow2(int : NATURAL) return NATURAL;
--+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(ld(arg))
function log2ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(ld(arg)))
function log2ceilnz(arg : positive) return positive;
-- Calculates: ceil(lg(arg))
function log10ceil(arg : POSITIVE) return NATURAL;
-- Calculates: max(1, ceil(lg(arg)))
function log10ceilnz(arg : POSITIVE) return POSITIVE;
--+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++
function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN;
function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER;
function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL;
function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC;
function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR;
function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER;
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING;
--+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers
function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals
function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector
function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector
function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector
function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector
function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers
function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals
function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector
function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector
function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector
function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector
function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector
function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector
function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector
function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector
--+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- to integer: to_int
function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
-- to std_logic: to_sl
function to_sl(Value : BOOLEAN) return STD_LOGIC;
function to_sl(Value : CHARACTER) return STD_LOGIC;
-- to std_logic_vector: to_slv
function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size))
-- TODO: comment
function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER;
function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER;
-- is_*
function is_sl(c : CHARACTER) return BOOLEAN;
--+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++
-- Aggregate functions
function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_xor (vec : std_logic_vector) return std_logic;
-- NO slv_xnor! This operation would not be well-defined as
-- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd.
-- Reverses the elements of the passed Vector.
--
-- @synthesis supported
--
function reverse(vec : std_logic_vector) return std_logic_vector;
function reverse(vec : bit_vector) return bit_vector;
function reverse(vec : unsigned) return unsigned;
-- Resizes the vector to the specified length. The adjustment is make on
-- on the 'high end of the vector. The 'low index remains as in the argument.
-- If the result vector is larger, the extension uses the provided fill value
-- (default: '0').
-- Use the resize functions of the numeric_std package for value-preserving
-- resizes of the signed and unsigned data types.
--
-- @synthesis supported
--
function resize(vec : bit_vector; length : natural; fill : bit := '0')
return bit_vector;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0')
return std_logic_vector;
-- Shift the index range of a vector by the specified offset.
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector;
-- Shift the index range of a vector making vec'low = 0.
function movez(vec : std_logic_vector) return std_logic_vector;
function ascend(vec : std_logic_vector) return std_logic_vector;
function descend(vec : std_logic_vector) return std_logic_vector;
-- Least-Significant Set Bit (lssb):
-- Computes a vector of the same length as the argument with
-- at most one bit set at the rightmost '1' found in arg.
--
-- @synthesis supported
--
function lssb(arg : std_logic_vector) return std_logic_vector;
function lssb(arg : bit_vector) return bit_vector;
-- Returns the index of the least-significant set bit.
--
-- @synthesis supported
--
function lssb_idx(arg : std_logic_vector) return integer;
function lssb_idx(arg : bit_vector) return integer;
-- Most-Significant Set Bit (mssb): computes a vector of the same length
-- with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector;
function mssb(arg : bit_vector) return bit_vector;
function mssb_idx(arg : std_logic_vector) return integer;
function mssb_idx(arg : bit_vector) return integer;
-- Swap sub vectors in vector (endian reversal)
function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR;
-- generate bit masks
function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
--+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- One-Hot-Code to Binary-Code.
function onehot2bin(onehot : std_logic_vector) return unsigned;
-- Converts Gray-Code into Binary-Code.
--
-- @synthesis supported
--
function gray2bin (gray_val : std_logic_vector) return std_logic_vector;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector;
end package;
package body utils is
-- Environment
-- ==========================================================================
function is_simulation return boolean is
variable ret : boolean;
begin
ret := false;
--synthesis translate_off
if Is_X('X') then ret := true; end if;
--synthesis translate_on
return ret;
end function;
-- deferred constant assignment
constant SIMULATION : BOOLEAN := is_simulation;
-- Divisions: div_*
function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b)
begin
return (a + (b - 1)) / b;
end function;
-- Power functions: *_pow2
-- ==========================================================================
-- is input a power of 2?
function is_pow2(int : NATURAL) return BOOLEAN is
begin
return ceil_pow2(int) = int;
end function;
-- round to next power of 2
function ceil_pow2(int : NATURAL) return POSITIVE is
begin
return 2 ** log2ceil(int);
end function;
-- round to previous power of 2
function floor_pow2(int : NATURAL) return NATURAL is
variable temp : UNSIGNED(30 downto 0);
begin
temp := to_unsigned(int, 31);
for i in temp'range loop
if (temp(i) = '1') then
return 2 ** i;
end if;
end loop;
return 0;
end function;
-- Logarithms: log*ceil*
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
function log2ceilnz(arg : positive) return positive is
begin
return imax(1, log2ceil(arg));
end function;
function log10ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 10;
log := log + 1;
end loop;
return log;
end function;
function log10ceilnz(arg : positive) return positive is
begin
return imax(1, log10ceil(arg));
end function;
-- if-then-else (ite)
-- ==========================================================================
function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- *min / *max / *sum
-- ==========================================================================
function imin(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
function rmin(arg1 : real; arg2 : real) return real is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
function imin(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := INTEGER'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imin(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := NATURAL'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imin(vec : T_POSVEC) return POSITIVE is
variable Result : POSITIVE;
begin
Result := POSITIVE'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function rmin(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
function rmax(arg1 : real; arg2 : real) return real is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
function imax(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := INTEGER'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imax(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := NATURAL'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imax(vec : T_POSVEC) return POSITIVE is
variable Result : POSITIVE;
begin
Result := POSITIVE'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function rmax(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function isum(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(I);
end loop;
return Result;
end function;
function isum(vec : T_POSVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(I);
end loop;
return Result;
end function;
function rsum(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := 0.0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
-- Vector aggregate functions: slv_*
-- ==========================================================================
function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
variable Result : STD_LOGIC;
begin
Result := '0';
for i in vec'range loop
Result := Result or vec(i);
end loop;
return Result;
end function;
function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return not slv_or(vec);
end function;
function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
variable Result : STD_LOGIC;
begin
Result := '1';
for i in vec'range loop
Result := Result and vec(i);
end loop;
return Result;
end function;
function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return not slv_and(vec);
end function;
function slv_xor(vec : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in vec'range loop
res := res xor vec(i);
end loop;
return res;
end slv_xor;
-- Convert to integer: to_int
function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
begin
return ite(bool, one, zero);
end function;
function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
begin
if (sl = '1') then
return one;
end if;
return zero;
end function;
-- Convert to bit: to_sl
-- ==========================================================================
function to_sl(Value : BOOLEAN) return STD_LOGIC is
begin
return ite(Value, '1', '0');
end function;
function to_sl(Value : CHARACTER) return STD_LOGIC is
begin
case Value is
when 'U' => return 'U';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when OTHERS => return 'X';
end case;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- short for std_logic_vector(to_unsigned(Value, Size))
-- the return value is guaranteed to have the range (Size-1 downto 0)
function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is
constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size));
begin
return res;
end function;
function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is
variable res : integer;
begin
if (slv'length = 0) then return 0; end if;
res := to_integer(slv);
if SIMULATION and max > 0 then
res := imin(res, max);
end if;
return res;
end function;
function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is
begin
return to_index(unsigned(slv), max);
end function;
-- is_*
-- ==========================================================================
function is_sl(c : CHARACTER) return BOOLEAN is
begin
case c is
when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true;
when OTHERS => return false;
end case;
end function;
-- Reverse vector elements
function reverse(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high-i)) := vec(i);
end loop;
return res;
end function;
function reverse(vec : bit_vector) return bit_vector is
variable res : bit_vector(vec'range);
begin
res := to_bitvector(reverse(to_stdlogicvector(vec)));
return res;
end reverse;
function reverse(vec : unsigned) return unsigned is
begin
return unsigned(reverse(std_logic_vector(vec)));
end function;
-- Swap sub vectors in vector
-- ==========================================================================
function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS
CONSTANT SegmentCount : NATURAL := slv'length / Size;
variable FromH : NATURAL;
variable FromL : NATURAL;
variable ToH : NATURAL;
variable ToL : NATURAL;
variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0);
begin
for i in 0 TO SegmentCount - 1 loop
FromH := ((I + 1) * Size) - 1;
FromL := I * Size;
ToH := ((SegmentCount - I) * Size) - 1;
ToL := (SegmentCount - I - 1) * Size;
Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL);
end loop;
return Result;
end function;
-- generate bit masks
-- ==========================================================================
function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS
begin
if (Bits = 0) then
return (MaskLength - 1 DOWNTO 0 => '0');
else
return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0');
end if;
end function;
function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is
begin
if (Bits = 0) then
return (MaskLength - 1 DOWNTO 0 => '0');
else
return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1');
end if;
end function;
-- binary encoding conversion functions
-- ==========================================================================
-- One-Hot-Code to Binary-Code
function onehot2bin(onehot : std_logic_vector) return unsigned is
variable res : unsigned(log2ceilnz(onehot'high+1)-1 downto 0);
variable chk : natural;
begin
res := (others => '0');
chk := 0;
for i in onehot'range loop
if onehot(i) = '1' then
res := res or to_unsigned(i, res'length);
chk := chk + 1;
end if;
end loop;
if SIMULATION and chk /= 1 then
report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set."
severity error;
end if;
return res;
end onehot2bin;
-- Gray-Code to Binary-Code
function gray2bin(gray_val : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(gray_val'range);
begin -- gray2bin
res(res'left) := gray_val(gray_val'left);
for i in res'left-1 downto res'right loop
res(i) := res(i+1) xor gray_val(i);
end loop;
return res;
end gray2bin;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(2**value'length - 1 downto 0);
begin
result := (others => '0');
result(to_index(value, 0)) := '1';
return result;
end function;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(value'range);
begin
result(result'left) := value(value'left);
for i in (result'left - 1) downto result'right loop
result(i) := value(i) xor value(i + 1);
end loop;
return result;
end function;
-- bit searching / bit indices
-- ==========================================================================
-- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg.
function lssb(arg : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(arg'range);
begin
res := arg and std_logic_vector(unsigned(not arg)+1);
return res;
end function;
function lssb(arg : bit_vector) return bit_vector is
variable res : bit_vector(arg'range);
begin
res := to_bitvector(lssb(to_stdlogicvector(arg)));
return res;
end lssb;
-- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
function mssb(arg : bit_vector) return bit_vector is
begin
return reverse(lssb(reverse(arg)));
end mssb;
-- Index of lssb
function lssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(lssb(arg)));
end function;
function lssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return lssb_idx(slv);
end lssb_idx;
-- Index of mssb
function mssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(mssb(arg)));
end function;
function mssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return mssb_idx(slv);
end mssb_idx;
function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : bit_vector(vec'low to high2b);
variable res_dn : bit_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end resize;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : std_logic_vector(vec'low to high2b);
variable res_dn : std_logic_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end resize;
-- Move vector boundaries
-- ==========================================================================
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is
variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs);
variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs);
begin
if vec'ascending then
res_up := vec;
return res_up;
else
res_dn := vec;
return res_dn;
end if;
end move;
function movez(vec : std_logic_vector) return std_logic_vector is
begin
return move(vec, -vec'low);
end movez;
function ascend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'low to vec'high);
begin
res := vec;
return res;
end ascend;
function descend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'high downto vec'low);
begin
res := vec;
return res;
end descend;
end package body;
| apache-2.0 | f50fd57a99b8e96224bffbf47ca1519b | 0.621426 | 3.431368 | false | false | false | false |
hoangt/PoC | src/arith/arith_prefix_and.vhdl | 2 | 2,810 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- =============================================================================
-- Copyright 2007-2015 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
library poc;
use poc.config.all;
entity arith_prefix_and is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_and;
architecture rtl of arith_prefix_and is
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) and x(1);
gen2: if N > 2 generate
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
s <= std_logic_vector(('0' & p) + 1);
y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
component MUXCY
port (
S : in std_logic;
DI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
signal c : std_logic_vector(N-1 downto 0);
begin
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : MUXCY
port map (
S => p(i),
DI => '0',
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
| apache-2.0 | 9653d97f5a3bf747abad0945212f86ca | 0.582414 | 3.340071 | false | false | false | false |
hoangt/PoC | src/mem/ocrom/ocrom_sp.vhdl | 2 | 4,542 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Single-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating single-port read-only memory
--
-- - single clock, clock enable
-- - 1 read port
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocrom_sp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocrom_sp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates single-port memory as expected.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type rom_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return rom_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : rom_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
constant rom : rom_t := ocram_ReadMemFile(FILENAME);
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
a_reg <= a;
end if;
end if;
end process;
q <= rom(to_integer(a_reg)); -- gets new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
assert FALSE report "Do you really want to generate a block of zeros?" severity FAILURE;
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_sp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_sp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk => clk,
ce => ce,
we => '0',
a => a,
d => (others => '0'),
q => q
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
| apache-2.0 | fdff32aa419e1fe0da0c5c2b2f8536a2 | 0.612726 | 3.325037 | false | false | false | false |
BogdanArdelean/FPWAM | hardware/src/hdl/DataFlowControl.vhd | 1 | 51,467 | -------------------------------------------------------------------------------
-- FILE NAME : DataFlowControl.vhd
-- MODULE NAME : DataFlowControl
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-03 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Module used for decoding WAM instructions and setting
-- appropriate signals on dataflow path
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity DataFlowControl is
port
(
-- Common
clk : in std_logic;
rst : in std_logic;
-- interface
instruction : in std_logic_vector(kWamInstructionWidth -1 downto 0);
instruction_valid : in std_logic;
mem_obj : in std_logic_vector(kWamWordWidth -1 downto 0);
deref_done : in std_logic;
mode_reg : in wam_mode_t;
unify_done : in std_logic;
bind_done : in std_logic;
nr_args : in std_logic_vector(kGPRAddressWidth -1 downto 0);
unwind_done : in std_logic;
local_fail : in std_logic;
global_fail : in std_logic;
b_reg : in std_logic_vector(kWamAddressWidth -1 downto 0);
new_b_reg : in std_logic_vector(kWamAddressWidth -1 downto 0);
deref_addr : in std_logic_vector(kWamAddressWidth -1 downto 0);
deref_word : in std_logic_vector(kWamWordWidth -1 downto 0);
H_reg : in std_logic_vector(kWamAddressWidth -1 downto 0);
E_reg : in std_logic_vector(kWamAddressWidth -1 downto 0);
bsearch_done : in std_logic;
bsearch_found : in std_logic;
local_fail_rst : out std_logic;
global_fail_out : out std_logic;
global_fail_rst : out std_logic;
get_instruction : out std_logic;
start_deref : out std_logic;
deref_input : out deref_input_t;
wr_s_reg : out std_logic;
s_reg_input : out s_input_t;
wr_mode_reg : out std_logic;
mode_value : out wam_mode_t; -- 1 = READ, 0 = WRITE; should define type
rd_mem_port1 : out std_logic;
wr_mem_port1 : out std_logic;
mem_input1 : out mem_port_input_t;
mem_addr_input1 : out mem_addr_input_t;
rd_mem_port2 : out std_logic;
wr_mem_port2 : out std_logic;
mem_input2 : out mem_port_input_t;
mem_addr_input2 : out mem_addr_input_t;
bind : out std_logic;
bind_port1 : out bind_input_t;
bind_port2 : out bind_input_t;
trail_input : out trail_input_t;
wr_h_reg : out std_logic;
h_input : out h_input_t;
wr_gpr1 : out std_logic;
gpr_addr1 : out GPR_addr_input_t;
gpr_input1 : out gpr_input_t;
wr_gpr2 : out std_logic;
gpr_addr2 : out GPR_addr_input_t;
gpr_input2 : out gpr_input_t;
start_unify : out std_logic;
unify_input_a : out unify_input_t;
unify_input_b : out unify_input_t;
p_input : out p_input_t;
p_wr : out std_logic;
cp_wr : out std_logic;
cp_input : out cp_input_t;
nrargs_wr : out std_logic;
nrargs_input : out nrargs_input_t;
newE_wr : out std_logic;
E_wr : out std_logic;
e_input : out e_input_t;
b_input : out b_input_t;
b_wr : out std_logic;
newB_wr : out std_logic;
tr_wr : out std_logic;
tr_input : out tr_input_t;
hb_wr : out std_logic;
hb_input : out hb_input_t;
i : out unsigned(kWamAddressWidth -1 downto 0);
start_unwind : out std_logic;
mem_addr1 : out std_logic_vector(kWamAddressWidth -1 downto 0);
mem_addr2 : out std_logic_vector(kWamAddressWidth -1 downto 0);
mem_out1 : out std_logic_vector(kWamWordWidth -1 downto 0);
mem_out2 : out std_logic_vector(kWamWordWidth -1 downto 0);
trail_do : out std_logic;
bladdr_wr : out std_logic;
bhaddr_wr : out std_logic;
bsearch_start : out std_logic
);
end DataFlowControl;
architecture Behavioral of DataFlowControl is
signal counter : unsigned(kWamAddressWidth -1 downto 0);
signal count : std_logic;
signal rst_cnt : std_logic;
-- FSM
type state_t is (idle_t, next_instr_t
,put_structure_t
,get_structure_t, get_structure_t2, get_structure_t3, get_structure_t4
,unify_variable_t, unify_variable_t2
,unify_value_t, unify_value_t2
,unify_local_value_t, unify_local_value_t2, unify_local_value_t3, unify_local_value_t4, unify_local_value_t5
,unify_constant_t, unify_constant_t2, unify_constant_t3
,unify_void_t, unify_void_t2
,put_variable_X_t
,put_variable_Y_t
,put_value_t, put_value_t2
,put_unsafe_value_t, put_unsafe_value_t2, put_unsafe_value_t3, put_unsafe_value_t4
,put_list_t
,put_constant_t
,get_variable_t
,get_value_t, get_value_t2
,get_list_t, get_list_t2, get_list_t3, get_list_t4
,get_constant_t, get_constant_t2
,call_t
,proceed_t
,allocate_t, allocate_t2, allocate_t3, allocate_t4
,deallocate_t, deallocate_t2
,try_me_else_t, try_me_else_t2, try_me_else_t3, try_me_else_t4, try_me_else_t5, try_me_else_t6, try_me_else_t7
,retry_me_else_t, retry_me_else_t2
,trust_me_t, trust_me_t2, trust_me_t3
,update_delete_start_t, update_delete_start_t2, update_delete_start_t3, update_delete_common_t, update_delete_common_t2, update_delete_common_t3, update_delete_common_t4, update_delete_common_t5, update_delete_common_t6
,backtrack_t, backtrack_t2, backtrack_t3, backtrack_t4, backtrack_t5
,execute_t
,unify_structure_t, unify_structure_t2
,switch_on_term_t
,switch_on_int_str_t, switch_on_int_str_t2, switch_on_int_str_t3, switch_on_int_str_t4
,unify_list_t, unify_list_t2
);
signal cr_state, nx_state, decoded_state : state_t;
signal mem_obj_reg : std_logic_vector(kWamWordWidth -1 downto 0);
signal wr_mem_reg : std_logic;
signal mem_addr1_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_addr2_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_addr1_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_addr2_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_addr_reg_wr : std_logic;
signal mem_out1_reg : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_out2_reg : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_out1_comb : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_out2_comb : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_out_reg_wr : std_logic;
begin
mem_addr1 <= mem_addr1_reg;
mem_addr2 <= mem_addr2_reg;
mem_out1 <= mem_out1_reg;
mem_out2 <= mem_out2_reg;
MEMOUTREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mem_out1_reg <= (others => '0');
mem_out2_reg <= (others => '0');
elsif mem_out_reg_wr = '1' then
mem_out1_reg <= mem_out1_comb;
mem_out2_reg <= mem_out2_comb;
end if;
end if;
end process;
MEMOBJREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mem_obj_reg <= (others => '0');
elsif wr_mem_reg = '1' then
mem_obj_reg <= mem_obj;
end if;
end if;
end process;
MEMADDRREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mem_addr1_reg <= (others => '0');
mem_addr2_reg <= (others => '0');
elsif mem_addr_reg_wr = '1' then
mem_addr1_reg <= mem_addr1_comb;
mem_addr2_reg <= mem_addr2_comb;
end if;
end if;
end process;
-- Decode the first state based on current instruction
-- TO DO: maybe put in function?
DECODE_STATE_FIRST: process(instruction, instruction_valid, global_fail)
begin
decoded_state <= idle_t;
if instruction_valid = '1' and global_fail /= '1' then
case fpwam_instr(instruction) is
when i_put_structure_t =>
decoded_state <= put_structure_t;
when i_get_structure_t =>
decoded_state <= get_structure_t;
when i_unify_variable_t =>
decoded_state <= unify_variable_t;
when i_unify_value_t =>
decoded_state <= unify_value_t;
when i_unify_local_value_t =>
decoded_state <= unify_local_value_t;
when i_unify_constant_t =>
decoded_state <= unify_constant_t;
when i_unify_void =>
decoded_state <= unify_void_t;
when i_put_variable_X_t =>
decoded_state <= put_variable_X_t;
when i_put_variable_Y_t =>
decoded_state <= put_variable_Y_t;
when i_put_value_t =>
decoded_state <= put_value_t;
when i_put_unsafe_value_t =>
decoded_state <= put_unsafe_value_t;
when i_put_list_t =>
decoded_state <= put_list_t;
when i_put_constant_t =>
decoded_state <= put_constant_t;
when i_get_variable_t =>
decoded_state <= get_variable_t;
when i_get_value_t =>
decoded_state <= get_value_t;
when i_get_list_t =>
decoded_state <= get_list_t;
when i_get_constant_t =>
decoded_state <= get_constant_t;
when i_call_t =>
decoded_state <= call_t;
when i_proceed_t =>
decoded_state <= proceed_t;
when i_allocate_t =>
decoded_state <= allocate_t;
when i_deallocate_t =>
decoded_state <= deallocate_t;
when i_try_me_else_t =>
decoded_state <= try_me_else_t;
when i_retry_me_else_t =>
decoded_state <= update_delete_start_t;
when i_trust_me_t =>
decoded_state <= update_delete_start_t;
when i_try_t =>
decoded_state <= try_me_else_t;
when i_retry_t =>
decoded_state <= update_delete_start_t;
when i_trust_t =>
decoded_state <= update_delete_start_t;
when i_execute_t =>
decoded_state <= execute_t;
when i_unify_structure_t =>
decoded_state <= unify_structure_t;
when i_switch_on_term_t =>
decoded_state <= switch_on_term_t;
when i_fail_t =>
decoded_state <= backtrack_t;
when i_switch_on_int_str_t =>
decoded_state <= switch_on_int_str_t;
when i_unify_list_t =>
decoded_state <= unify_list_t;
when others =>
decoded_state <= idle_t;
end case;
end if;
end process DECODE_STATE_FIRST;
-- FSM
FSM: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cr_state <= next_instr_t;
else
cr_state <= nx_state;
end if;
end if;
end process FSM;
NEXT_STATE_DECODE: process(decoded_state, cr_state, deref_done, mem_obj, instruction, instruction_valid, bind_done, mode_reg, unify_done, unwind_done, counter, local_fail, b_reg, mem_obj_reg, deref_addr, H_reg, deref_word, E_reg, nr_args, bsearch_done, bsearch_found)
begin
nx_state <= cr_state;
case cr_state is
when next_instr_t =>
if local_fail /= '1' then
nx_state <= idle_t;
else
nx_state <= backtrack_t;
end if;
when backtrack_t =>
if b_reg = kWamStackStart then
nx_state <= idle_t;
else
nx_state <= backtrack_t2;
end if;
when backtrack_t2 =>
nx_state <= backtrack_t3;
when backtrack_t3 =>
nx_state <= backtrack_t4;
when backtrack_t4 =>
nx_state <= backtrack_t5;
when backtrack_t5 =>
nx_state <= next_instr_t;
when idle_t =>
nx_state <= decoded_state;
when put_structure_t =>
nx_state <= next_instr_t;
----- BEGIN get_structure f, a(i) -----
when get_structure_t =>
if deref_done = '1' then
nx_state <= get_structure_t2;
end if;
when get_structure_t2 =>
nx_state <= get_structure_t3;
when get_structure_t3 =>
if fpwam_tag(mem_obj_reg) = tag_str_t and mem_obj_reg = instruction(17 downto 0) then
nx_state <= next_instr_t;
elsif fpwam_tag(mem_obj_reg) = tag_ref_t then
nx_state <= get_structure_t4;
else
nx_state <= backtrack_t;
end if;
when get_structure_t4 => -- maybe should wait for trail and bind to finish?
if bind_done = '1' then
nx_state <= next_instr_t;
end if;
----- END get_structure f, a(i) -----
when unify_variable_t =>
if mode_reg = mode_read_t then
nx_state <= unify_variable_t2;
else
nx_state <= next_instr_t;
end if;
when unify_variable_t2 =>
nx_state <= next_instr_t;
when unify_value_t =>
if mode_reg = mode_read_t then
nx_state <= unify_value_t2;
else
if fpwam_var_on_stack(instruction) then -- on stack need 2 cycles
nx_state <= unify_value_t2;
else
nx_state <= next_instr_t;
end if;
end if;
when unify_value_t2 =>
if mode_reg = mode_read_t then
if unify_done = '1' then
nx_state <= next_instr_t;
end if;
else
nx_state <= next_instr_t;
end if;
when unify_local_value_t =>
nx_state <= unify_local_value_t2;
when unify_local_value_t2 =>
case mode_reg is
when mode_read_t =>
if unify_done = '1' then
nx_state <= next_instr_t;
end if;
when mode_write_t =>
if deref_done = '1' then
if deref_addr < H_reg then
nx_state <= unify_local_value_t3;
else
nx_state <= unify_local_value_t4;
end if;
end if;
end case;
when unify_local_value_t3 =>
nx_state <= next_instr_t;
when unify_local_value_t4 =>
nx_state <= unify_local_value_t5;
when unify_local_value_t5 =>
if bind_done = '1' then
nx_state <= next_instr_t;
end if;
when unify_constant_t =>
case mode_reg is
when mode_read_t =>
nx_state <= unify_constant_t2;
when mode_write_t =>
nx_state <= next_instr_t;
end case;
when unify_constant_t2 =>
if deref_done = '1' then
case fpwam_tag(deref_word) is
when tag_ref_t =>
nx_state <= unify_constant_t3;
when tag_int_t =>
if deref_word = instruction(kWamWordWidth -1 downto 0) then
nx_state <= next_instr_t;
else
nx_state <= backtrack_t;
end if;
when others =>
nx_state <= backtrack_t;
end case;
end if;
when unify_constant_t3 =>
nx_state <= next_instr_t;
when put_variable_X_t =>
nx_state <= next_instr_t;
when put_variable_Y_t =>
nx_state <= next_instr_t;
when put_value_t =>
if fpwam_var_on_stack(instruction) then -- value on stack
nx_state <= put_value_t2;
else
nx_state <= next_instr_t;
end if;
when put_value_t2 =>
nx_state <= next_instr_t;
when put_unsafe_value_t =>
if deref_done = '1' then
if deref_addr < E_reg then
nx_state <= put_unsafe_value_t2;
else
nx_state <= put_unsafe_value_t3;
end if;
end if;
when put_unsafe_value_t2 =>
nx_state <= next_instr_t;
when put_unsafe_value_t3 =>
nx_state <= put_unsafe_value_t4;
when put_unsafe_value_t4 =>
if bind_done = '1' then
nx_state <= next_instr_t;
end if;
when put_list_t =>
nx_state <= next_instr_t;
when put_constant_t =>
nx_state <= next_instr_t;
when get_variable_t =>
nx_state <= next_instr_t;
when get_value_t =>
nx_state <= get_value_t2;
when get_value_t2 =>
if unify_done = '1' then
nx_state <= next_instr_t;
end if;
when get_list_t =>
if deref_done = '1' then
case fpwam_tag(deref_word) is
when tag_ref_t =>
nx_state <= get_list_t3;
when tag_lis_t =>
nx_state <= get_list_t2;
when others =>
nx_state <= backtrack_t;
end case;
end if;
when get_list_t2 =>
nx_state <= next_instr_t;
when get_list_t3 =>
nx_state <= get_list_t4;
when get_list_t4 =>
if bind_done = '1' then
nx_state <= next_instr_t;
end if;
when get_constant_t =>
if deref_done = '1' then
case fpwam_tag(deref_word) is
when tag_ref_t =>
nx_state <= get_constant_t2;
when tag_int_t =>
if deref_word = instruction(kWamWordWidth -1 downto 0) then
nx_state <= next_instr_t;
else
nx_state <= backtrack_t;
end if;
when others =>
nx_state <= backtrack_t;
end case;
end if;
when call_t =>
nx_state <= next_instr_t;
when proceed_t =>
nx_state <= next_instr_t;
when allocate_t =>
nx_state <= allocate_t2;
when allocate_t2 =>
nx_state <= allocate_t3;
when allocate_t3 =>
nx_state <= allocate_t4;
when allocate_t4 =>
nx_state <= next_instr_t;
when deallocate_t =>
nx_state <= deallocate_t2;
when deallocate_t2 =>
nx_state <= next_instr_t;
when try_me_else_t =>
nx_state <= try_me_else_t2;
when try_me_else_t2 =>
nx_state <= try_me_else_t3;
when try_me_else_t3 =>
nx_state <= try_me_else_t4;
when try_me_else_t4 =>
nx_state <= try_me_else_t5;
when try_me_else_t5 =>
nx_state <= try_me_else_t6;
when try_me_else_t6 =>
nx_state <= try_me_else_t7;
when try_me_else_t7 =>
if counter+2 > unsigned(nr_args) then
nx_state <= next_instr_t;
end if;
when update_delete_start_t =>
nx_state <= update_delete_start_t2;
when update_delete_start_t2 =>
nx_state <= update_delete_start_t3;
when update_delete_start_t3=>
nx_state <= update_delete_common_t;
when update_delete_common_t =>
nx_state <= update_delete_common_t2;
when update_delete_common_t2 =>
nx_state <= update_delete_common_t3;
when update_delete_common_t3 =>
nx_state <= update_delete_common_t4;
when update_delete_common_t4 =>
if unwind_done = '1' then
nx_state <= update_delete_common_t5;
end if;
when update_delete_common_t5 =>
nx_state <= update_delete_common_t6;
when update_delete_common_t6 =>
if counter+2 > unsigned(nr_args) then
case fpwam_instr(instruction) is
when i_retry_me_else_t =>
nx_state <= retry_me_else_t;
when i_retry_t =>
nx_state <= retry_me_else_t;
when i_trust_me_t =>
nx_state <= trust_me_t;
when i_trust_t =>
nx_state <= trust_me_t;
when others =>
null;
end case;
end if;
when retry_me_else_t =>
nx_state <= retry_me_else_t2;
when retry_me_else_t2 =>
nx_state <= next_instr_t;
when trust_me_t =>
nx_state <= trust_me_t2;
when trust_me_t2 =>
nx_state <= trust_me_t3;
when trust_me_t3 =>
nx_state <= next_instr_t;
when unify_void_t =>
case mode_reg is
when mode_read_t =>
nx_state <= next_instr_t;
when mode_write_t =>
nx_state <= unify_void_t2;
end case;
when unify_void_t2 =>
if counter+2 > unsigned(instruction(kGPRAddressWidth -1 downto 0)) then
nx_state <= next_instr_t;
end if;
when execute_t =>
nx_state <= next_instr_t;
when unify_structure_t =>
case mode_reg is
when mode_read_t =>
nx_state <= unify_structure_t2;
when mode_write_t =>
nx_state <= next_instr_t;
end case;
when unify_structure_t2 =>
if deref_done = '1' then
nx_state <= get_structure_t2;
end if;
when switch_on_term_t =>
if deref_done = '1' then
nx_state <= next_instr_t;
end if;
when switch_on_int_str_t =>
nx_state <= switch_on_int_str_t2;
when switch_on_int_str_t2 =>
nx_state <= switch_on_int_str_t3;
when switch_on_int_str_t3 =>
if deref_done = '1' then
nx_state <= switch_on_int_str_t4;
end if;
when switch_on_int_str_t4 =>
if bsearch_done = '1' then
if bsearch_found = '1' then
nx_state <= next_instr_t;
else
nx_state <= backtrack_t;
end if;
end if;
when unify_list_t =>
case mode_reg is
when mode_read_t =>
nx_state <= unify_list_t2;
when mode_write_t =>
nx_state <= next_instr_t;
end case;
when unify_list_t2 =>
if deref_done = '1' then
case fpwam_tag(deref_word) is
when tag_ref_t =>
nx_state <= get_list_t3;
when tag_lis_t =>
nx_state <= get_list_t2;
when others =>
nx_state <= backtrack_t;
end case;
end if;
when others => null;
end case;
end process NEXT_STATE_DECODE;
OUTPUT_DECODE: process(cr_state, deref_done, mem_obj, instruction, bind_done, mode_reg, counter, nr_args, new_b_reg, b_reg, mem_addr1_reg, mem_addr2_reg, local_fail, mem_obj_reg, H_reg, mem_addr1_comb, mem_addr2_comb, deref_word, bsearch_done, bsearch_found)
begin
--DEFAULT VALUES
local_fail_rst <= '0';
global_fail_out <= '0';
global_fail_rst <= '0';
get_instruction <= '0';
start_deref <= '0';
deref_input <= DI_GPR_t;
wr_s_reg <= '0';
s_reg_input <= SI_untag_deref_p1_t;
wr_mode_reg <= '0';
mode_value <= mode_write_t;
rd_mem_port1 <= '0';
rd_mem_port2 <= '0';
wr_mem_port1 <= '0';
wr_mem_port2 <= '0';
mem_input1 <= MI_str_Hplus1_t;
mem_input2 <= MI_str_Hplus1_t;
mem_addr_input1 <= MA_H_t;
mem_addr_input2 <= MA_H_t;
bind <= '0';
bind_port1 <= BI_deref_unit_t;
bind_port2 <= BI_deref_unit_t;
trail_input <= TI_bind_output_t;
wr_h_reg <= '0';
h_input <= HI_p1_t;
wr_gpr1 <= '0';
gpr_addr1 <= GPRA_instr_t;
gpr_input1 <= GPRI_ref_H_t;
wr_gpr2 <= '0';
gpr_addr2 <= GPRA_instr_t;
gpr_input2 <= GPRI_ref_H_t;
start_unify <= '0';
unify_input_a <= UI_GPR_t;
unify_input_b <= UI_GPR_t;
p_input <= PI_p1_t;
p_wr <= '0';
cp_wr <= '0';
cp_input <= CPI_P_t;
nrargs_wr <= '0';
nrargs_input <= NRARGSI_instr_t;
newE_wr <= '0';
E_wr <= '0';
e_input <= EI_newE_t;
b_input <= BRI_newB_t;
b_wr <= '0';
newB_wr <= '0';
tr_wr <= '0';
tr_input <= TRI_Trp1_t;
hb_wr <= '0';
hb_input <= HBI_H_t;
i <= to_unsigned(0, i'length);
start_unwind <= '0';
rst_cnt <= '0';
count <= '0';
wr_mem_reg <= '0';
mem_out_reg_wr <= '0';
mem_addr_reg_wr <= '0';
mem_addr1_comb <= (others => '0');
mem_addr2_comb <= (others => '0');
trail_do <= '0';
bladdr_wr <= '0';
bhaddr_wr <= '0';
bladdr_wr <= '0';
bhaddr_wr <= '0';
bsearch_start <= '0';
mem_out1_comb <= (others => '0');
mem_out2_comb <= (others => '0');
case cr_state is
when next_instr_t =>
if local_fail /= '1' then
get_instruction <= '1';
p_wr <= '1';
p_input <= PI_p1_t;
end if;
when backtrack_t =>
if b_reg = kWamStackStart then
global_fail_out <= '1';
else
local_fail_rst <= '1';
rd_mem_port2 <= '1';
mem_addr_input2 <= MA_B_t;
end if;
when backtrack_t2 =>
nrargs_wr <= '1';
nrargs_input <= NRARGSI_mem_port2_t;
wr_mem_reg <= '1';
when backtrack_t3 =>
mem_addr1_comb <= std_logic_vector((unsigned(b_reg(kWamAddressWidth -1 downto 0))+unsigned(mem_obj_reg(kWamAddressWidth -1 downto 0)))+to_unsigned(4, i'length));
mem_addr_reg_wr <= '1';
when backtrack_t4 =>
rd_mem_port1 <= '1';
mem_addr_input1 <= MA_DFC_t;
when backtrack_t5 =>
p_wr <= '1';
p_input <= PI_mem_port1_t;
when idle_t =>
null;
when get_structure_t => -- deref(Ai)
start_deref <= '1';
deref_input <= DI_GPR_t; -- mux => input for deref = A(i)
mem_addr_input1 <= MA_deref_unit_t; -- mux => mem input from deref module
if deref_done = '1' then
mem_addr_input2 <= MA_untag_deref_t;
rd_mem_port2 <= '1';
end if;
when get_structure_t2 =>
wr_mem_reg <= '1';
when get_structure_t3 =>
if fpwam_tag(mem_obj_reg) = tag_str_t and mem_obj_reg = instruction(17 downto 0) then
-- S = a + 1
wr_s_reg <= '1';
s_reg_input <= SI_untag_deref_p1_t;
wr_mode_reg <= '1';
mode_value <= mode_read_t;
elsif fpwam_tag(mem_obj_reg) = tag_ref_t then -- need to refactor
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_str_Hplus1_t;
mem_addr_input2 <= MA_Hplus1_t;
mem_input2 <= MI_constant_t;
rd_mem_port1 <= '1';
rd_mem_port2 <= '1';
wr_mem_port1 <= '1';
wr_mem_port2 <= '1';
wr_mode_reg <= '1';
mode_value <= mode_write_t;
end if;
when get_structure_t4 => -- refactor at bind input!!!
bind <= '1'; -- bind(
bind_port1 <= BI_deref_unit_t; -- tag(STORE[addr])
bind_port2 <= BI_mem_port1_t; -- tag(STORE[H]))
mem_addr_input1 <= MA_bind_unit_1_t;
mem_input1 <= MI_bind_unit_1_t;
mem_addr_input2 <= MA_bind_unit_2_t;
mem_input2 <= MI_bind_unit_2_t;
trail_input <= TI_bind_output_t;
if bind_done = '1' then
wr_h_reg <= '1'; -- H =
h_input <= HI_p2_t; -- H+2
end if;
when put_structure_t =>
wr_mem_port1 <= '1';
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_constant_t;
wr_h_reg <= '1';
h_input <= HI_p1_t;
wr_gpr1 <= '1';
gpr_input1 <= GPRI_str_H_t;
wr_mode_reg <= '1';
mode_value <= mode_write_t;
when unify_value_t =>
case mode_reg is
when mode_read_t =>
mem_addr_input2 <= MA_S_t;
rd_mem_port2 <= '1';
wr_s_reg <= '1';
s_reg_input <= SI_p1_t;
if fpwam_var_on_stack(instruction) then -- if value is on stack. Issue read.
mem_addr_input1 <= MA_stack_addr_t;
rd_mem_port1 <= '1';
end if;
when mode_write_t =>
if fpwam_var_on_stack(instruction) then -- value on stack. Issue read.
mem_addr_input1 <= MA_stack_addr_t;
rd_mem_port1 <= '1';
else
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_GPR_t;
wr_mem_port1 <= '1';
wr_h_reg <= '1';
h_input <= HI_p1_t;
end if;
end case;
when unify_value_t2 =>
if mode_reg = mode_read_t then
start_unify <= '1';
unify_input_b <= UI_mem_port2_t;
mem_addr_input1 <= MA_unify_unit_t;
mem_addr_input2 <= MA_unify_unit_t;
mem_input1 <= MI_unify_unit_t;
mem_input2 <= MI_unify_unit_t;
bind_port1 <= BI_unify_unit_t;
bind_port2 <= BI_unify_unit_t;
deref_input <= DI_unify_unit_t;
if fpwam_var_on_stack(instruction) then -- value on stack
unify_input_a <= UI_mem_port1_t;
else
unify_input_a <= UI_GPR_t;
end if;
else
mem_addr_input2 <= MA_H_t;
mem_input2 <= MI_mem_port1_t;
wr_mem_port2 <= '1';
wr_h_reg <= '1';
h_input <= HI_p1_t;
end if;
when unify_local_value_t =>
mem_addr_input2 <= MA_S_t;
s_reg_input <= SI_p1_t;
case mode_reg is
when mode_read_t =>
mem_addr_input1 <= MA_stack_addr_t;
rd_mem_port2 <= '1';
wr_s_reg <= '1';
if fpwam_var_on_stack(instruction) then -- if value is on stack. Issue read.
rd_mem_port1 <= '1';
end if;
when mode_write_t =>
mem_addr_input1 <= MA_stack_addr_t;
if fpwam_var_on_stack(instruction) then -- value on stack. Issue read.
rd_mem_port1 <= '1';
end if;
end case;
when unify_local_value_t2 =>
case mode_reg is
when mode_read_t =>
start_unify <= '1';
unify_input_b <= UI_mem_port2_t;
mem_addr_input1 <= MA_unify_unit_t;
mem_addr_input2 <= MA_unify_unit_t;
mem_input1 <= MI_unify_unit_t;
mem_input2 <= MI_unify_unit_t;
bind_port1 <= BI_unify_unit_t;
bind_port2 <= BI_unify_unit_t;
deref_input <= DI_unify_unit_t;
if fpwam_var_on_stack(instruction) then -- value on stack
unify_input_a <= UI_mem_port1_t;
else
unify_input_a <= UI_GPR_t;
end if;
when mode_write_t =>
start_deref <= '1';
mem_addr_input1 <= MA_deref_unit_t;
if fpwam_var_on_stack(instruction) then
deref_input <= DI_mem_port1_t;
else
deref_input <= DI_GPR_t;
end if;
end case;
when unify_local_value_t3 =>
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_deref_t;
wr_mem_port1 <= '1';
wr_h_reg <= '1';
when unify_local_value_t4 =>
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_ref_H_t;
wr_mem_port1 <= '1';
rd_mem_port1 <= '1';
wr_h_reg <= '1';
h_input <= HI_p1_t;
when unify_local_value_t5 =>
bind <= '1'; -- bind(
bind_port1 <= BI_deref_unit_t; -- tag(STORE[addr])
bind_port2 <= BI_mem_port1_t; -- tag(STORE[H]))
mem_addr_input1 <= MA_bind_unit_1_t;
mem_input1 <= MI_bind_unit_1_t;
mem_addr_input2 <= MA_bind_unit_2_t;
mem_input2 <= MI_bind_unit_2_t;
trail_input <= TI_bind_output_t;
when unify_variable_t =>
if mode_reg = mode_read_t then
mem_addr_input1 <= MA_S_t;
rd_mem_port1 <= '1';
wr_s_reg <= '1';
s_reg_input <= SI_p1_t;
else
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_ref_H_t;
wr_mem_port1 <= '1';
wr_h_reg <= '1';
h_input <= HI_p1_t;
mem_addr_input2 <= MA_stack_addr_t;
mem_input2 <= MI_ref_H_t;
gpr_input1 <= GPRI_ref_H_t;
if fpwam_var_on_stack(instruction) then --value on stack
wr_mem_port2 <= '1';
else
wr_gpr1 <= '1';
end if;
end if;
when unify_variable_t2 =>
mem_addr_input2 <= MA_stack_addr_t;
mem_input2 <= MI_mem_port1_t;
gpr_input1 <= GPRI_mem_port1_t;
if mode_reg = mode_read_t then
if fpwam_var_on_stack(instruction) then
wr_mem_port2 <= '1';
else
wr_gpr1 <= '1';
end if;
end if;
when unify_constant_t =>
mem_input1 <= MI_constant_t;
case mode_reg is
when mode_read_t =>
mem_addr_input1 <= MA_S_t;
rd_mem_port1 <= '1';
when mode_write_t =>
mem_addr_input1 <= MA_H_t;
wr_mem_port1 <= '1';
wr_h_reg <= '1';
end case;
when unify_constant_t2 =>
start_deref <= '1';
deref_input <= DI_mem_port1_t;
mem_addr_input1 <= MA_deref_unit_t;
if deref_done = '1' then
wr_s_reg <= '1';
s_reg_input <= SI_p1_t;
end if;
when unify_constant_t3 =>
mem_addr_input1 <= MA_deref_unit_t;
mem_input1 <= MI_constant_t;
wr_mem_port1 <= '1';
trail_input <= TI_deref_t;
trail_do <= '1';
when put_variable_X_t =>
wr_gpr1 <= '1';
wr_gpr2 <= '1';
gpr_input1 <= GPRI_ref_H_t;
gpr_input2 <= GPRI_ref_H_t;
wr_mem_port1 <= '1';
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_ref_H_t;
wr_h_reg <= '1';
h_input <= HI_p1_t;
when put_variable_Y_t =>
wr_gpr2 <= '1';
gpr_input2 <= GPRI_ref_addr_t;
wr_mem_port1 <= '1';
mem_input1 <= MI_ref_addr_t;
mem_addr_input1 <= MA_stack_addr_t;
when put_value_t =>
mem_addr_input1 <= MA_stack_addr_t;
gpr_input2 <= GPRI_gpr1_t;
if fpwam_var_on_stack(instruction) then -- value on stack
rd_mem_port1 <= '1';
else
wr_gpr2 <= '1';
end if;
when put_value_t2 =>
wr_gpr2 <= '1';
gpr_input2 <= GPRI_mem_port1_t;
when put_unsafe_value_t =>
start_deref <= '1';
deref_input <= DI_EYnp2_t;
mem_addr_input1 <= MA_deref_unit_t;
when put_unsafe_value_t2 =>
wr_gpr2 <= '1';
gpr_input2 <= GPRI_deref_t;
gpr_addr2 <= GPRA_instr_t;
when put_unsafe_value_t3 =>
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_ref_H_t;
rd_mem_port1 <= '1';
wr_mem_port1 <= '1';
gpr_input2 <= GPRI_ref_H_t;
gpr_addr2 <= GPRA_instr_t;
wr_gpr2 <= '1';
wr_h_reg <= '1';
when put_unsafe_value_t4 =>
bind <= '1';
bind_port1 <= BI_deref_unit_t;
bind_port2 <= BI_mem_port1_t;
mem_addr_input1 <= MA_bind_unit_1_t;
mem_input1 <= MI_bind_unit_1_t;
mem_addr_input2 <= MA_bind_unit_2_t;
mem_input2 <= MI_bind_unit_2_t;
trail_input <= TI_bind_output_t;
when put_list_t =>
gpr_input1 <= GPRI_lis_H_t;
wr_gpr1 <= '1';
wr_mode_reg <= '1';
mode_value <= mode_write_t;
when put_constant_t =>
gpr_input1 <= GPRI_constant_t;
wr_gpr1 <= '1';
when get_variable_t =>
mem_input1 <= MI_GPR2_t;
mem_addr_input1 <= MA_stack_addr_t;
gpr_input1 <= GPRI_gpr2_t;
if fpwam_var_on_stack(instruction) then
wr_mem_port1 <= '1';
else
wr_gpr1 <= '1';
end if;
when get_value_t =>
mem_addr_input1 <= MA_stack_addr_t;
rd_mem_port1 <= to_std_logic(fpwam_var_on_stack(instruction));
when get_value_t2 =>
start_unify <= '1';
unify_input_b <= UI_GPR_t;
mem_addr_input1 <= MA_unify_unit_t;
mem_addr_input2 <= MA_unify_unit_t;
mem_input1 <= MI_unify_unit_t;
mem_input2 <= MI_unify_unit_t;
bind_port1 <= BI_unify_unit_t;
bind_port2 <= BI_unify_unit_t;
deref_input <= DI_unify_unit_t;
if fpwam_var_on_stack(instruction) then
unify_input_a <= UI_mem_port1_t;
else
unify_input_a <= UI_GPR_t;
end if;
when get_list_t =>
start_deref <= '1';
deref_input <= DI_GPR_t;
mem_addr_input1 <= MA_deref_unit_t;
when get_list_t2 =>
wr_s_reg <= '1';
s_reg_input <= SI_untag_deref_t;
wr_mode_reg <= '1';
mode_value <= mode_read_t;
when get_list_t3 =>
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_lis_Hplus1_t;
rd_mem_port1 <= '1';
wr_mem_port1 <= '1';
wr_mode_reg <= '1';
mode_value <= mode_write_t;
wr_h_reg <= '1';
when get_list_t4 =>
bind <= '1';
bind_port1 <= BI_deref_unit_t;
bind_port2 <= BI_mem_port1_t;
mem_addr_input1 <= MA_bind_unit_1_t;
mem_input1 <= MI_bind_unit_1_t;
mem_addr_input2 <= MA_bind_unit_2_t;
mem_input2 <= MI_bind_unit_2_t;
trail_input <= TI_bind_output_t;
when get_constant_t =>
start_deref <= '1';
deref_input <= DI_GPR_t;
mem_addr_input1 <= MA_deref_unit_t;
when get_constant_t2 =>
mem_addr_input1 <= MA_deref_unit_t;
mem_input1 <= MI_constant_t;
wr_mem_port1 <= '1';
trail_input <= TI_deref_t;
trail_do <= '1';
when call_t =>
p_input <= PI_instr_t;
p_wr <= '1';
cp_wr <= '1';
nrargs_wr <= '1';
when execute_t =>
p_input <= PI_instr_t;
p_wr <= '1';
nrargs_wr <= '1';
when proceed_t =>
p_input <= PI_CP_t;
p_wr <= '1';
when allocate_t =>
rd_mem_port2 <= '1';
mem_addr_input2 <= MA_Ep2orB_t;
when allocate_t2 =>
newE_wr <= '1';
when allocate_t3 =>
mem_addr_input1 <= MA_newE_t;
mem_input1 <= MI_E_t;
wr_mem_port1 <= '1';
mem_addr_input2 <= MA_newEp1_t;
mem_input2 <= MI_CP_t;
wr_mem_port2 <= '1';
when allocate_t4 =>
mem_addr_input1 <= MA_newEp2_t;
mem_input1 <= MI_constant_t;
wr_mem_port1 <= '1';
E_wr <= '1';
when deallocate_t =>
rd_mem_port1 <= '1';
mem_addr_input1 <= MA_E_t;
rd_mem_port2 <= '1';
mem_addr_input2 <= MA_Ep1_t;
when deallocate_t2 =>
E_wr <= '1';
e_input <= EI_mem_port1_t;
cp_wr <= '1';
cp_input <= CPI_mem_port2_t;
when try_me_else_t =>
rd_mem_port2 <= '1';
mem_addr_input2 <= MA_Ep2orB_t;
when try_me_else_t2 =>
newB_wr <= '1';
when try_me_else_t3 =>
mem_addr_input1 <= MA_newB_t;
mem_input1 <= MI_NRAGRGS_t;
wr_mem_port1 <= '1';
mem_addr1_comb <= std_logic_vector(unsigned(new_b_reg)+unsigned(nr_args)+to_unsigned(2, i'length));
mem_addr2_comb <= std_logic_vector(unsigned(new_b_reg)+unsigned(nr_args)+to_unsigned(3, i'length));
mem_addr_reg_wr <= '1';
when try_me_else_t4 =>
mem_addr_input1 <= MA_DFC_t;
mem_input1 <= MI_CP_t;
wr_mem_port1 <= '1';
mem_addr_input2 <= MA_DFC_t;
mem_input2 <= MI_B_t;
wr_mem_port2 <= '1';
mem_addr1_comb <= std_logic_vector(unsigned(new_b_reg)+unsigned(nr_args)+to_unsigned(4, i'length));
mem_addr2_comb <= std_logic_vector(unsigned(new_b_reg)+unsigned(nr_args)+to_unsigned(5, i'length));
mem_addr_reg_wr <= '1';
when try_me_else_t5 =>
mem_addr_input1 <= MA_DFC_t;
p_input <= PI_constant_t;
if fpwam_instr(instruction) = i_try_t then
mem_input1 <= MI_P_t;
p_wr <= '1';
else
mem_input1 <= MI_constant_t;
end if;
wr_mem_port1 <= '1';
mem_addr_input2 <= MA_DFC_t;
mem_input2 <= MI_TR_t;
wr_mem_port2 <= '1';
mem_addr1_comb <= std_logic_vector(unsigned(new_b_reg)+unsigned(nr_args)+to_unsigned(6, i'length));
mem_addr2_comb <= std_logic_vector(unsigned(new_b_reg)+unsigned(nr_args)+to_unsigned(1, i'length));
mem_addr_reg_wr <= '1';
when try_me_else_t6 =>
mem_addr_input1 <= MA_DFC_t;
mem_input1 <= MI_H_t;
wr_mem_port1 <= '1';
mem_addr_input2 <= MA_DFC_t;
mem_input2 <= MI_E_t;
wr_mem_port2 <= '1';
b_input <= BRI_newB_t;
b_wr <= '1';
hb_wr <= '1';
hb_input <= HBI_H_t;
rst_cnt <= '1';
mem_addr1_comb <= std_logic_vector(unsigned(new_b_reg) + to_unsigned(1, b_reg'length));
mem_addr2_comb <= std_logic_vector(unsigned(new_b_reg) + to_unsigned(2, b_reg'length));
mem_addr_reg_wr <= '1';
when try_me_else_t7 =>
i <= counter;
count <= '1';
mem_addr_input1 <= MA_DFC_t;
mem_input1 <= MI_GPR_t;
wr_mem_port1 <= to_std_logic(counter <= unsigned(nr_args));
mem_addr_input2 <= MA_DFC_t;
mem_input2 <= MI_GPR2_t;
wr_mem_port2 <= to_std_logic(counter+1 <= unsigned(nr_args));
gpr_addr1 <= GPRA_I_t;
gpr_addr2 <= GPRA_Ip1_t;
mem_addr1_comb <= std_logic_vector(unsigned(mem_addr1_reg) + 2);
mem_addr2_comb <= std_logic_vector(unsigned(mem_addr2_reg) + 2);
mem_addr_reg_wr <= '1';
count <= '1';
when retry_me_else_t =>
mem_addr1_comb <= std_logic_vector(unsigned(b_reg)+unsigned(nr_args)+to_unsigned(4, i'length));
mem_addr_reg_wr <= '1';
when retry_me_else_t2 =>
wr_mem_port1 <= '1';
mem_addr_input1 <= MA_DFC_t;
p_input <= PI_constant_t;
if fpwam_instr(instruction) = i_retry_t then
mem_input1 <= MI_P_t;
p_wr <= '1';
else
mem_input1 <= MI_constant_t;
end if;
hb_input <= HBI_H_t;
hb_wr <= '1';
when trust_me_t =>
mem_addr1_comb <= std_logic_vector(unsigned(b_reg)+unsigned(nr_args)+to_unsigned(3, i'length));
mem_addr_reg_wr <= '1';
when trust_me_t2 =>
rd_mem_port1 <= '1';
mem_addr_input1 <= MA_DFC_t;
when trust_me_t3 =>
B_wr <= '1';
b_input <= BRI_mem_port1_t;
hb_wr <= '1';
hb_input <= HBI_H_t;
p_input <= PI_constant_t;
p_wr <= to_std_logic(fpwam_instr(instruction) = i_trust_t);
when update_delete_start_t =>
mem_addr_input2 <= MA_B_t;
rd_mem_port2 <= '1';
when update_delete_start_t2 =>
wr_mem_reg <= '1';
when update_delete_start_t3 =>
nrargs_wr <= '1';
nrargs_input <= NRARGSI_mem_port2_t;
mem_addr1_comb <= std_logic_vector(unsigned(b_reg)+unsigned(mem_obj_reg(kWamAddressWidth -1 downto 0))+to_unsigned(1, i'length));
mem_addr2_comb <= std_logic_vector(unsigned(b_reg)+unsigned(mem_obj_reg(kWamAddressWidth -1 downto 0))+to_unsigned(2, i'length));
mem_addr_reg_wr <= '1';
when update_delete_common_t =>
mem_addr_input1 <= MA_DFC_t;
rd_mem_port1 <= '1';
mem_addr_input2 <= MA_DFC_t;
rd_mem_port2 <= '1';
rst_cnt <= '1';
mem_addr1_comb <= std_logic_vector(unsigned(b_reg)+unsigned(nr_args)+to_unsigned(5, i'length));
mem_addr2_comb <= std_logic_vector(unsigned(b_reg)+unsigned(nr_args)+to_unsigned(6, i'length));
mem_addr_reg_wr <= '1';
when update_delete_common_t2 =>
mem_addr_input1 <= MA_DFC_t;
rd_mem_port1 <= '1';
mem_addr_input2 <= MA_DFC_t;
rd_mem_port2 <= '1';
E_wr <= '1';
e_input <= EI_mem_port1_t;
cp_wr <= '1';
cp_input <= CPI_mem_port2_t;
when update_delete_common_t3 =>
tr_wr <= '1';
tr_input <= TRI_mem_port1_t;
wr_h_reg <= '1';
h_input <= HI_mem_port2_t;
start_unwind <= '1';
when update_delete_common_t4 =>
trail_input <= TI_unwind_trail_t;
mem_addr_input1 <= MA_unwind_trail_t;
mem_addr_input2 <= MA_unwind_trail_t;
mem_input1 <= MI_unwind_trail_t;
mem_input2 <= MI_unwind_trail_t;
mem_addr1_comb <= std_logic_vector(unsigned(b_reg) + to_unsigned(1, b_reg'length));
mem_addr2_comb <= std_logic_vector(unsigned(b_reg) + to_unsigned(2, b_reg'length));
mem_addr_reg_wr <= '1';
rst_cnt <= '1';
when update_delete_common_t5 =>
i <= counter;
mem_addr_input1 <= MA_DFC_t;
rd_mem_port1 <= to_std_logic(counter <= unsigned(nr_args));
mem_addr_input2 <= MA_DFC_t;
rd_mem_port2 <= to_std_logic(counter+1 <= unsigned(nr_args));
mem_addr1_comb <= std_logic_vector(unsigned(mem_addr1_reg) + 2);
mem_addr2_comb <= std_logic_vector(unsigned(mem_addr2_reg) + 2);
mem_addr_reg_wr <= '1';
when update_delete_common_t6 =>
i <= counter;
mem_addr_input1 <= MA_DFC_t;
rd_mem_port1 <= to_std_logic(counter+2 <= unsigned(nr_args));
mem_addr_input2 <= MA_DFC_t;
rd_mem_port2 <= to_std_logic(counter+3 <= unsigned(nr_args));
gpr_addr1 <= GPRA_I_t;
gpr_addr2 <= GPRA_Ip1_t;
wr_gpr1 <= to_std_logic(counter <= unsigned(nr_args));
wr_gpr2 <= to_std_logic(counter+1 <= unsigned(nr_args));
gpr_input1 <= GPRI_mem_port1_t;
gpr_input2 <= GPRI_mem_port2_t;
mem_addr1_comb <= std_logic_vector(unsigned(mem_addr1_reg) + 2);
mem_addr2_comb <= std_logic_vector(unsigned(mem_addr2_reg) + 2);
mem_addr_reg_wr <= '1';
count <= '1';
when unify_void_t =>
case mode_reg is
when mode_read_t =>
wr_s_reg <= '1';
s_reg_input <= SI_pconstant_t;
when mode_write_t =>
rst_cnt <= '1';
mem_addr1_comb <= H_reg;
mem_addr2_comb <= std_logic_vector(unsigned(H_reg)+1);
mem_addr_reg_wr <= '1';
mem_out1_comb <= fpwam_word(H_reg, tag_ref_t);
mem_out2_comb <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_ref_t);
mem_out_reg_wr <= '1';
end case;
when unify_void_t2 =>
mem_addr_input1 <= MA_DFC_t;
mem_input1 <= MI_DFC_t;
wr_mem_port1 <= to_std_logic(counter <= unsigned(instruction(kGPRAddressWidth -1 downto 0)));
mem_addr_input2 <= MA_DFC_t;
mem_input2 <= MI_DFC_t;
wr_mem_port2 <= to_std_logic(counter+1 <= unsigned(instruction(kGPRAddressWidth -1 downto 0)));
mem_addr1_comb <= std_logic_vector(unsigned(mem_addr1_reg)+2);
mem_addr2_comb <= std_logic_vector(unsigned(mem_addr2_reg)+2);
mem_addr_reg_wr <= '1';
mem_out1_comb <= fpwam_word(mem_addr1_comb, tag_ref_t);
mem_out2_comb <= fpwam_word(mem_addr2_comb, tag_ref_t);
mem_out_reg_wr <= '1';
count <= '1';
h_input <= HI_Hpconstant_t;
wr_h_reg <= to_std_logic(counter+2 > unsigned(instruction(kGPRAddressWidth -1 downto 0)));
when unify_structure_t =>
case mode_reg is
when mode_read_t =>
mem_addr_input1 <= MA_S_t;
rd_mem_port1 <= '1';
when mode_write_t =>
mem_addr_input1 <= MA_Hplus1_t;
mem_input1 <= MI_constant_t;
mem_addr_input2 <= MA_H_t;
mem_input2 <= MI_str_Hplus1_t;
wr_mem_port1 <= '1';
wr_mem_port2 <= '1';
wr_h_reg <= '1';
h_input <= HI_p2_t;
end case;
when unify_structure_t2 =>
start_deref <= '1';
deref_input <= DI_mem_port1_t;
mem_addr_input1 <= MA_deref_unit_t;
mem_addr_input2 <= MA_untag_deref_t;
rd_mem_port2 <= deref_done;
when unify_list_t =>
case mode_reg is
when mode_read_t =>
mem_addr_input1 <= MA_S_t;
rd_mem_port1 <= '1';
when mode_write_t =>
mem_addr_input1 <= MA_H_t;
mem_input1 <= MI_lis_Hplus1_t;
wr_mem_port1 <= '1';
wr_h_reg <= '1';
end case;
when unify_list_t2 =>
start_deref <= '1';
deref_input <= DI_mem_port1_t;
mem_addr_input1 <= MA_deref_unit_t;
mem_addr_input2 <= MA_untag_deref_t;
rd_mem_port2 <= deref_done and to_std_logic(fpwam_tag(deref_word)=tag_lis_t);
when switch_on_term_t =>
start_deref <= '1';
deref_input <= DI_GPR_t;
mem_addr_input1 <= MA_deref_unit_t;
gpr_addr1 <= GPRA_1_t;
p_input <= PI_PpI_t;
p_wr <= deref_done;
case fpwam_tag(deref_word) is
when tag_ref_t =>
i <= to_unsigned(0, i'length);
when tag_int_t =>
i <= to_unsigned(1, i'length);
when tag_lis_t =>
i <= to_unsigned(2, i'length);
when tag_str_t =>
i <= to_unsigned(3, i'length);
end case;
when switch_on_int_str_t =>
get_instruction <= '1';
p_wr <= '1';
bladdr_wr <= '1';
when switch_on_int_str_t2 =>
bhaddr_wr <= '1';
start_deref <= '1';
deref_input <= DI_GPR_t;
mem_addr_input1 <= MA_deref_unit_t;
when switch_on_int_str_t3 =>
deref_input <= DI_GPR_t;
mem_addr_input1 <= MA_deref_unit_t;
when switch_on_int_str_t4 =>
bsearch_start <= '1';
p_wr <= bsearch_done and bsearch_found;
p_input <= PI_bmem_port1_t;
when others => null;
end case;
end process OUTPUT_DECODE;
CNTR: process(clk)
begin
if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= to_unsigned(1, counter'length);
elsif count = '1' then
counter <= counter + 2;
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | 442b4c8f0f514003ab400e0407db9096 | 0.497406 | 3.161364 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_tb/AEAD_TB.vhd | 1 | 22,957 | -------------------------------------------------------------------------------
--! @file AEAD_TB.vhd
--! @brief Testbench for GMU CAESAR project.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @version 1.0b1
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity AEAD_TB IS
generic (
G_ASYNC_RSTN : boolean := False;
--! Test parameters
G_STOP_AT_FAULT : boolean := False;
G_TEST_MODE : integer := 0;
G_TEST_ISTALL : integer := 10;
G_TEST_OSTALL : integer := 10;
G_LOG2_FIFODEPTH : integer := 8;
G_PWIDTH : integer := 32;
G_SWIDTH : integer := 32;
G_PERIOD : time := 10 ns;
G_FNAME_PDI : string := "pdi.txt";
G_FNAME_SDI : string := "sdi.txt";
G_FNAME_DO : string := "do.txt";
G_FNAME_LOG : string := "log.txt";
G_FNAME_RESULT : string := "result.txt"
);
end AEAD_TB;
architecture behavior of AEAD_TB is
--! =================== --
--! SIGNALS DECLARATION --
--! =================== --
--! simulation signals (used by ATHENa script, ignore if not used)
signal simulation_fails : std_logic := '0';
signal stop_clock : boolean := False;
--! error check signal
signal global_stop : std_logic := '1';
--! globals
signal clk : std_logic := '0';
signal io_clk : std_logic := '0';
signal rst : std_logic := '0';
--! pdi
signal fpdi_din : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
signal fpdi_din_valid : std_logic := '0';
signal fpdi_din_ready : std_logic;
signal fpdi_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal fpdi_dout_valid : std_logic;
signal fpdi_dout_ready : std_logic;
signal pdi_delayed : std_logic_vector(G_PWIDTH-1 downto 0);
signal pdi_valid : std_logic;
signal pdi_valid_selected : std_logic;
signal pdi_ready : std_logic;
--! sdi
signal fsdi_din : std_logic_vector(G_SWIDTH-1 downto 0)
:= (others=>'0');
signal fsdi_din_valid : std_logic := '0';
signal fsdi_din_ready : std_logic;
signal fsdi_dout : std_logic_vector(G_SWIDTH-1 downto 0);
signal fsdi_dout_valid : std_logic;
signal fsdi_dout_ready : std_logic;
signal sdi_delayed : std_logic_vector(G_SWIDTH-1 downto 0);
signal sdi_valid : std_logic;
signal sdi_valid_selected : std_logic;
signal sdi_ready : std_logic;
--! do
signal do : std_logic_vector(G_PWIDTH-1 downto 0);
signal do_valid : std_logic;
signal do_ready : std_logic;
signal do_ready_selected : std_logic;
signal fdo_din_ready : std_logic;
signal fdo_din_valid : std_logic;
signal fdo_dout : std_logic_vector(G_PWIDTH-1 downto 0);
signal fdo_dout_valid : std_logic;
signal fdo_dout_ready : std_logic := '0';
--! Verification signals
signal stall_pdi_valid : std_logic := '0';
signal stall_sdi_valid : std_logic := '0';
signal stall_do_full : std_logic := '0';
------------- clock constant ------------------
constant clk_period : time := G_PERIOD;
constant io_clk_period : time := clk_period;
----------- end of clock constant -------------
------------- string constant ------------------
--! constant
constant cons_tb : string(1 to 6) := "# TB :";
constant cons_ins : string(1 to 6) := "INS = ";
constant cons_hdr : string(1 to 6) := "HDR = ";
constant cons_dat : string(1 to 6) := "DAT = ";
constant cons_stt : string(1 to 6) := "STT = ";
--! Shared constant
constant cons_eof : string(1 to 6) := "###EOF";
----------- end of string constant -------------
------------- debug constant ------------------
constant debug_input : boolean := False;
constant debug_output : boolean := False;
----------- end of clock constant -------------
-- ================= --
-- FILES DECLARATION --
-- ================= --
--------------- input / output files -------------------
file pdi_file : text open read_mode is G_FNAME_PDI;
file sdi_file : text open read_mode is G_FNAME_SDI;
file do_file : text open read_mode is G_FNAME_DO;
file log_file : text open write_mode is G_FNAME_LOG;
file result_file : text open write_mode is G_FNAME_RESULT;
------------- end of input files --------------------
begin
genClk: process
begin
if (not stop_clock and global_stop = '1') then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process genClk;
genIOclk: process
begin
if ((not stop_clock) and (global_stop = '1')) then
io_clk <= '1';
wait for io_clk_period/2;
io_clk <= '0';
wait for io_clk_period/2;
else
wait;
end if;
end process genIOclk;
--! ============ --
--! PORT MAPPING --
--! ============ --
genPDIfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => fpdi_din,
din_valid => fpdi_din_valid,
din_ready => fpdi_din_ready,
dout => fpdi_dout,
dout_valid => fpdi_dout_valid,
dout_ready => fpdi_dout_ready
);
fpdi_dout_ready <= '0' when stall_pdi_valid = '1' else pdi_ready;
pdi_valid_selected <= '1' when stall_pdi_valid = '1' else fpdi_dout_valid;
pdi_valid <= pdi_valid_selected after 1/4*clk_period;
pdi_delayed <= fpdi_dout after 1/4*clk_period;
genSDIfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_SWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => fsdi_din,
din_valid => fsdi_din_valid,
din_ready => fsdi_din_ready,
dout => fsdi_dout,
dout_valid => fsdi_dout_valid,
dout_ready => fsdi_dout_ready
);
fsdi_dout_ready <= '0' when stall_sdi_valid = '1' else sdi_ready;
sdi_valid_selected <= '1' when stall_sdi_valid = '1' else fsdi_dout_valid;
sdi_valid <= sdi_valid_selected after 1/4*clk_period;
sdi_delayed <= fsdi_dout after 1/4*clk_period;
genDOfifo: entity work.fwft_fifo(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_LOG2DEPTH => G_LOG2_FIFODEPTH)
port map (
clk => io_clk,
rst => rst,
din => do,
din_valid => fdo_din_valid,
din_ready => fdo_din_ready,
dout => fdo_dout,
dout_valid => fdo_dout_valid,
dout_ready => fdo_dout_ready
);
fdo_din_valid <= '0' when stall_do_full = '1' else do_valid;
do_ready_selected <= '1' when stall_do_full = '1' else fdo_din_ready;
do_ready <= do_ready_selected after 1/4*clk_period;
uut: entity work.AEAD(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_W => G_PWIDTH,
G_SW => G_SWIDTH
)
port map (
rst => rst,
clk => clk,
pdi_data => pdi_delayed,
pdi_ready => pdi_ready,
pdi_valid => pdi_valid,
sdi_data => sdi_delayed,
sdi_ready => sdi_ready,
sdi_valid => sdi_valid,
do_data => do,
do_valid => do_valid,
do_ready => do_ready
);
--! =================== --
--! END OF PORT MAPPING --
--! =================== --
--! =======================================================================
--! ==================== DATA POPULATION FOR PUBLIC DATA ==================
tb_read_pdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
if (not G_ASYNC_RSTN) then
rst <= '1'; wait for 5*clk_period;
rst <= '0'; wait for clk_period;
else
rst <= '0'; wait for 5*clk_period;
rst <= '1'; wait for clk_period;
end if;
--! read header
while ( not endfile (pdi_file)) and ( loop_enable = '1' ) loop
if endfile (pdi_file) then
loop_enable := '0';
end if;
readline(pdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( pdi_file ) loop
--! if the fifo is full, wait ...
fpdi_din_valid <= '1';
if ( fpdi_din_ready = '0' ) then
fpdi_din_valid <= '0';
wait until fpdi_din_ready <= '1';
wait for io_clk_period/2; --! write in the rising edge
fpdi_din_valid <= '1';
end if;
hreadnew( line_data, word_block, read_result );
while (((read_result = False) or (valid_line = False))
and (not endfile( pdi_file )))
loop
readline(pdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if ( temp_read = cons_ins or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
fpdi_din_valid <= '1';
else
valid_line := False;
fpdi_din_valid <= '0';
end if;
hreadnew( line_data, word_block, read_result ); --! read data
end loop;
fpdi_din <= word_block;
wait for io_clk_period;
end loop;
fpdi_din_valid <= '0';
wait;
end process;
--! =======================================================================
--! ==================== DATA POPULATION FOR SECRET DATA ==================
tb_read_sdi : process
variable line_data : line;
variable word_block : std_logic_vector(G_SWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable loop_enable : std_logic := '1';
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
begin
--! Wait until reset is done
wait for 7*clk_period;
--! read header
while (not endfile (sdi_file)) and (loop_enable = '1') loop
if endfile (sdi_file) then
loop_enable := '0';
end if;
readline(sdi_file, line_data);
read(line_data, temp_read, read_result);
if (temp_read = cons_ins) then
loop_enable := '0';
end if;
end loop;
--! do operations in the falling edge of the io_clk
wait for io_clk_period/2;
while not endfile ( sdi_file ) loop
--! if the fifo is full, wait ...
fsdi_din_valid <= '1';
if ( fsdi_din_ready = '0' ) then
fsdi_din_valid <= '0';
wait until fsdi_din_ready <= '1';
wait for io_clk_period/2; --! write in the rising edge
fsdi_din_valid <= '1';
end if;
hreadnew(line_data, word_block, read_result);
while (((read_result = False) or (valid_line = False))
and (not endfile(sdi_file)))
loop
readline(sdi_file, line_data);
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_ins or temp_read = cons_hdr
or temp_read = cons_dat)
then
valid_line := True;
fsdi_din_valid <= '1';
else
valid_line := False;
fsdi_din_valid <= '0';
end if;
hreadnew( line_data, word_block, read_result ); --! read data
end loop;
fsdi_din <= word_block;
wait for io_clk_period;
end loop;
fsdi_din_valid <= '0';
wait;
end process;
--! =======================================================================
--! =======================================================================
--! =================== DATA VERIFICATION =================================
tb_verifydata : process
variable line_no : integer := 0;
variable line_data : line;
variable logMsg : line;
variable tb_block : std_logic_vector(20 -1 downto 0);
variable word_block : std_logic_vector(G_PWIDTH-1 downto 0)
:= (others=>'0');
variable read_result : boolean;
variable temp_read : string(1 to 6);
variable valid_line : boolean := True;
variable word_count : integer := 1;
variable word_pass : integer := 1;
variable instr_encoding : boolean := False;
variable force_exit : boolean := False;
variable msgid : integer;
variable keyid : integer;
variable isEncrypt : boolean := False;
variable opcode : std_logic_vector(3 downto 0);
begin
wait for 6*clk_period;
while (not endfile (do_file) and valid_line and (not force_exit)) loop
--! Keep reading new line until a valid line is found
hreadnew( line_data, word_block, read_result );
while ((read_result = False or valid_line = False)
and (not endfile(do_file)))
loop
readline(do_file, line_data);
line_no := line_no + 1;
read(line_data, temp_read, read_result); --! read line header
if (temp_read = cons_hdr
or temp_read = cons_dat
or temp_read = cons_stt)
then
valid_line := True;
word_count := 1;
else
valid_line := False;
if (temp_read = cons_tb) then
instr_encoding := True;
end if;
end if;
if (temp_read = cons_eof) then
force_exit := True;
end if;
if (instr_encoding = True) then
hreadnew(line_data, tb_block, read_result); --! read data
instr_encoding := False;
read_result := False;
opcode := tb_block(19 downto 16);
keyid := to_integer(unsigned(tb_block(15 downto 8)));
msgid := to_integer(unsigned(tb_block(7 downto 0)));
isEncrypt := False;
if ((opcode = OP_DEC or opcode = OP_ENC)
or (opcode = STAT_SUCCESS or opcode = STAT_FAILURE))
then
write(logMsg, string'("[Log] == Verifying msg ID #")
& integer'image(msgid)
& string'(" with key ID #") & integer'image(keyid));
if (opcode = OP_ENC) then
isEncrypt := True;
write(logMsg, string'(" for ENC"));
else
write(logMsg, string'(" for DEC"));
end if;
writeline(log_file,logMsg);
end if;
report "---------Started verifying message number "
& integer'image(msgid) & " at "
& time'image(now) severity note;
else
hreadnew(line_data, word_block, read_result); --! read data
end if;
end loop;
--! if the core is slow in outputting the digested message, wait ...
if ( valid_line ) then
fdo_dout_ready <= '1';
if ( fdo_dout_valid = '0') then
fdo_dout_ready <= '0';
wait until fdo_dout_valid = '1';
wait for io_clk_period/2;
fdo_dout_ready <= '1';
end if;
word_pass := 1;
for i in G_PWIDTH-1 downto 0 loop
if fdo_dout(i) /= word_block(i)
and word_block(i) /= 'X'
then
word_pass := 0;
end if;
end loop;
if word_pass = 0 then
simulation_fails <= '1';
write(logMsg, string'("[Log] Msg ID #")
& integer'image(msgid)
& string'(" fails at line #") & integer'image(line_no)
& string'(" word #") & integer'image(word_count));
writeline(log_file,logMsg);
write(logMsg, string'("[Log] Expected: ")
& to_hstring(word_block)
& string'(" Received: ") & to_hstring(fdo_dout));
writeline(log_file,logMsg);
--! Stop the simulation right away when an error is detected
report "---------Data line #" & integer'image(line_no)
& " Msg ID #" & integer'image(msgid)
& " Key ID #" & integer'image(keyid)
& " Word #" & integer'image(word_count)
& " at " & time'image(now) & " FAILS T_T --------"
severity note;
report "Expected: " & to_hstring(word_block)
& " Actual: " & to_hstring(fdo_dout) severity note;
write(result_file, "fail");
if (G_STOP_AT_FAULT = True) then
force_exit := True;
else
if isEncrypt = False then
report "---------Skip to the next instruction"
& " at " & time'image(now) severity note;
write(logMsg,
string'("[Log] ...skips to next message ID"));
writeline(log_file, logMsg);
end if;
end if;
else
write(logMsg, string'("[Log] Expected: ")
& to_hstring(word_block)
& string'(" Received: ") & to_hstring(fdo_dout)
& string'(" Matched!"));
writeline(log_file,logMsg);
end if;
wait for io_clk_period;
word_count := word_count + 1;
end if;
end loop;
fdo_dout_ready <= '0';
wait for io_clk_period;
if (simulation_fails = '1') then
report "FAIL (1): SIMULATION FINISHED || Input/Output files :: T_T"
& G_FNAME_PDI & "/" & G_FNAME_SDI
& "/" & G_FNAME_DO severity error;
write(result_file, "1");
else
report "PASS (0): SIMULATION FINISHED || Input/Output files :: ^0^"
& G_FNAME_PDI & "/" & G_FNAME_SDI
& "/" & G_FNAME_DO severity note;
write(result_file, "0");
end if;
write(logMsg, string'("[Log] Done"));
writeline(log_file,logMsg);
stop_clock <= True;
wait;
end process;
--! =======================================================================
--! =======================================================================
--! =================== Test MODE =========================================
genInputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 2 then
wait until rising_edge( pdi_ready );
wait for io_clk_period;
stall_pdi_valid <= '1';
stall_sdi_valid <= '1';
wait for io_clk_period*G_TEST_ISTALL;
stall_pdi_valid <= '0';
stall_sdi_valid <= '0';
else
wait;
end if;
end process;
genOutputStall : process
begin
if G_TEST_MODE = 1 or G_TEST_MODE = 3 then
wait until rising_edge( do_valid );
wait for io_clk_period;
stall_do_full <= '1';
wait for io_clk_period*G_TEST_OSTALL;
stall_do_full <= '0';
else
wait;
end if;
end process;
end;
| apache-2.0 | 8522489caec551ea20749b298192ad1e | 0.44413 | 4.274674 | false | false | false | false |
hoangt/PoC | tb/arith/arith_addw_tb.vhdl | 2 | 3,914 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Entity: arith_addw_tb
--
-- Authors: Thomas B. Preusser <[email protected]>
--
-- Description:
-- ------------
-- Testbench for arith_addw.
--
-- License:
-- ============================================================================
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
entity arith_addw_tb is
end entity arith_addw_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.arith.all;
use PoC.simulation.all;
architecture tb of arith_addw_tb is
-- component generics
constant N : positive := 9;
constant K : positive := 2;
subtype tArch_test is tArch;
subtype tSkip_test is tSkipping;
-- component ports
subtype word is std_logic_vector(N-1 downto 0);
type word_vector is array(tArch_test, tSkip_test, boolean) of word;
type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic;
signal a, b : word;
signal cin : std_logic;
signal s : word_vector;
signal cout : carry_vector;
begin
-- DUTs
genArchs: for i in tArch_test generate
genSkips: for j in tSkip_test generate
genIncl: for p in false to true generate
DUT : arith_addw
generic map (
N => N,
K => K,
ARCH => i,
SKIPPING => j,
P_INCLUSIVE => p
)
port map (
a => a,
b => b,
cin => cin,
s => s(i, j, p),
cout => cout(i, j, p)
);
end generate genIncl;
end generate;
end generate;
-- Stimuli
process
begin
for i in natural range 0 to 2**N-1 loop
a <= std_logic_vector(to_unsigned(i, N));
for j in natural range 0 to 2**N-1 loop
b <= std_logic_vector(to_unsigned(j, N));
cin <= '0';
wait for 5 ns;
for arch in tArch_test loop
for skip in tSkip_test loop
for incl in boolean loop
tbAssert((i+j) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
"Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
integer'image(i)&'+'&integer'image(j)&" != "&
integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
end loop;
end loop;
end loop;
cin <= '1';
wait for 5 ns;
for arch in tArch_test loop
for skip in tSkip_test loop
for incl in boolean loop
tbAssert((i+j+1) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
"Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
integer'image(i)&'+'&integer'image(j)&"+1 != "&
integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
end loop;
end loop;
end loop;
end loop; -- j
end loop; -- i
tbPrintResult;
wait; -- forever
end process;
end architecture tb;
| apache-2.0 | bd6ae882a74ab434896e3e843adcf3b3 | 0.549821 | 3.781643 | false | true | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sources_1/new/serialLoader.vhd | 1 | 3,004 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 17:22:42
-- Design Name:
-- Module Name: serialLoader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity serialLoader is
Port (
--serial control data
S_Send : out STD_LOGIC:='0';
S_DataOut : out std_logic_vector (7 downto 0);
S_Ready : in STD_LOGIC;
--FIFO DATA
FIFO_Empty : in STD_LOGIC; -- flag if no data is left
FIFO_Data : in STD_LOGIC_VECTOR (7 downto 0); -- actual data
FIFO_ReadEn : out STD_LOGIC := '0'; -- enable read
-- global clock
clk : in STD_LOGIC;
reset: in STD_LOGIC
);
end serialLoader;
architecture Behavioral of serialLoader is
type state_type is ( STATE_WAIT, STATE_STARTREAD, STATE_ENDREAD, STATE_STARTWRITE, STATE_ENDWRITE);
signal state_reg: state_type := STATE_WAIT;
begin
process (clk, FIFO_Empty, S_Ready, reset) -- process to handle the next state
begin
if (reset = '1') then
--reset state:
FIFO_ReadEn <= '0';
S_Send <= '0';
state_reg <= STATE_WAIT;
else
if rising_edge (clk) then
case state_reg is
when STATE_WAIT =>
if (FIFO_Empty = '1' or S_Ready = '0') then
state_reg <= STATE_WAIT;
else
state_reg <= STATE_STARTREAD;
end if;
when STATE_STARTREAD =>
-- request the data
FIFO_ReadEn <= '1';
state_reg <= STATE_ENDREAD;
when STATE_ENDREAD =>
--clock the data out
S_DataOut <= FIFO_Data;
FIFO_ReadEn <= '0';
state_reg <= STATE_STARTWRITE;
when STATE_STARTWRITE =>
-- tell the serial module to pickup the data
S_Send <= '1';
state_reg <= STATE_ENDWRITE;
when STATE_ENDWRITE =>
-- close all the modules down
S_Send <= '0';
if (FIFO_Empty = '0' and S_Ready = '1') then
state_reg <= STATE_STARTREAD;
else
state_reg <= STATE_WAIT;
end if;
when others =>
state_reg <= STATE_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 8ba1dc027ada54a48bbadd2dcae132e0 | 0.510652 | 4.267045 | false | false | false | false |
hoangt/PoC | src/bus/stream/stream_Buffer.vhdl | 2 | 10,977 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_Buffer is
generic (
FRAMES : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
DATA_FifO_DEPTH : POSITIVE := 8;
META_BITS : T_POSVEC := (0 => 8);
META_FifO_DEPTH : T_POSVEC := (0 => 16)
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- IN Port
In_Valid : in STD_LOGIC;
In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
In_SOF : in STD_LOGIC;
In_EOF : in STD_LOGIC;
In_Ack : out STD_LOGIC;
In_Meta_rst : out STD_LOGIC;
In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0);
In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0);
-- OUT Port
Out_Valid : out STD_LOGIC;
Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC;
Out_EOF : out STD_LOGIC;
Out_Ack : in STD_LOGIC;
Out_Meta_rst : in STD_LOGIC;
Out_Meta_nxt : in STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0);
Out_Meta_Data : out STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0)
);
end;
architecture rtl of Stream_Buffer is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
constant META_STREAMS : POSITIVE := META_BITS'length;
type T_WRITER_STATE is (ST_IDLE, ST_FRAME);
type T_READER_STATE is (ST_IDLE, ST_FRAME);
signal Writer_State : T_WRITER_STATE := ST_IDLE;
signal Writer_NextState : T_WRITER_STATE;
signal Reader_State : T_READER_STATE := ST_IDLE;
signal Reader_NextState : T_READER_STATE;
constant EOF_BIT : NATURAL := DATA_BITS;
signal DataFifO_put : STD_LOGIC;
signal DataFifO_DataIn : STD_LOGIC_VECTOR(DATA_BITS downto 0);
signal DataFifO_Full : STD_LOGIC;
signal DataFifO_got : STD_LOGIC;
signal DataFifO_DataOut : STD_LOGIC_VECTOR(DataFifO_DataIn'range);
signal DataFifO_Valid : STD_LOGIC;
signal FrameCommit : STD_LOGIC;
signal Meta_rst : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0);
begin
assert (META_BITS'length = META_FifO_DEPTH'length) report "META_BITS'length /= META_FifO_DEPTH'length" severity FAILURE;
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Writer_State <= ST_IDLE;
Reader_State <= ST_IDLE;
else
Writer_State <= Writer_NextState;
Reader_State <= Reader_NextState;
end if;
end if;
end process;
process(Writer_State,
In_Valid, In_Data, In_SOF, In_EOF,
DataFifO_Full)
begin
Writer_NextState <= Writer_State;
In_Ack <= '0';
DataFifO_put <= '0';
DataFifO_DataIn(In_Data'range) <= In_Data;
DataFifO_DataIn(EOF_BIT) <= In_EOF;
case Writer_State is
when ST_IDLE =>
In_Ack <= NOT DataFifO_Full;
DataFifO_put <= In_Valid;
if ((In_Valid AND In_SOF AND NOT In_EOF) = '1') then
Writer_NextState <= ST_FRAME;
end if;
when ST_FRAME =>
In_Ack <= NOT DataFifO_Full;
DataFifO_put <= In_Valid;
if ((In_Valid AND In_EOF AND NOT DataFifO_Full) = '1') then
Writer_NextState <= ST_IDLE;
end if;
end case;
end process;
process(Reader_State,
Out_Ack,
DataFifO_Valid, DataFifO_DataOut)
begin
Reader_NextState <= Reader_State;
Out_Valid <= '0';
Out_Data <= DataFifO_DataOut(Out_Data'range);
Out_SOF <= '0';
Out_EOF <= DataFifO_DataOut(EOF_BIT);
DataFifO_got <= '0';
case Reader_State is
when ST_IDLE =>
Out_Valid <= DataFifO_Valid;
Out_SOF <= '1';
DataFifO_got <= Out_Ack;
if ((DataFifO_Valid AND NOT DataFifO_DataOut(EOF_BIT) AND Out_Ack) = '1') then
Reader_NextState <= ST_FRAME;
end if;
when ST_FRAME =>
Out_Valid <= DataFifO_Valid;
DataFifO_got <= Out_Ack;
if ((DataFifO_Valid AND DataFifO_DataOut(EOF_BIT) AND Out_Ack) = '1') then
Reader_NextState <= ST_IDLE;
end if;
end case;
end process;
DataFifO : entity PoC.fifo_cc_got
generic map (
D_BITS => DATA_BITS + 1, -- Data Width
MIN_DEPTH => (DATA_FifO_DEPTH * FRAMES), -- Minimum FifO Depth
DATA_REG => ((DATA_FifO_DEPTH * FRAMES) <= 128), -- Store Data Content in Registers
STATE_REG => TRUE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FifO Output
ESTATE_WR_BITS => 0, -- Empty State Bits
FSTATE_RD_BITS => 0 -- Full State Bits
)
port map (
-- Global Reset and Clock
clk => Clock,
rst => Reset,
-- Writing Interface
put => DataFifO_put,
din => DataFifO_DataIn,
full => DataFifO_Full,
estate_wr => OPEN,
-- Reading Interface
got => DataFifO_got,
dout => DataFifO_DataOut,
valid => DataFifO_Valid,
fstate_rd => OPEN
);
FrameCommit <= DataFifO_Valid AND DataFifO_DataOut(EOF_BIT) AND Out_Ack;
In_Meta_rst <= slv_and(Meta_rst);
genMeta : for i in 0 to META_BITS'length - 1 generate
begin
genReg : if (META_FifO_DEPTH(i) = 1) generate
signal MetaReg_DataIn : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0);
signal MetaReg_d : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0) := (others => '0');
signal MetaReg_DataOut : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0);
begin
MetaReg_DataIn <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I));
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
MetaReg_d <= (others => '0');
else
if ((In_Valid AND In_SOF) = '1') then
MetaReg_d <= MetaReg_DataIn;
end if;
end if;
end if;
end process;
MetaReg_DataOut <= MetaReg_d;
Out_Meta_Data(high(META_BITS, I) downto low(META_BITS, I)) <= MetaReg_DataOut;
end generate; -- META_FifO_DEPTH(i) = 1
genFifO : if (META_FifO_DEPTH(i) > 1) generate
signal MetaFifO_put : STD_LOGIC;
signal MetaFifO_DataIn : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0);
signal MetaFifO_Full : STD_LOGIC;
signal MetaFifO_Commit : STD_LOGIC;
signal MetaFifO_Rollback : STD_LOGIC;
signal MetaFifO_got : STD_LOGIC;
signal MetaFifO_DataOut : STD_LOGIC_VECTOR(MetaFifO_DataIn'range);
signal MetaFifO_Valid : STD_LOGIC;
signal Writer_CounterControl : STD_LOGIC := '0';
signal Writer_Counter_en : STD_LOGIC;
signal Writer_Counter_us : UNSIGNED(log2ceilnz(META_FifO_DEPTH(i)) - 1 downto 0) := (others => '0');
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Writer_CounterControl <= '0';
else
if ((In_Valid AND In_SOF) = '1') then
Writer_CounterControl <= '1';
ELSif (Writer_Counter_us = (META_FifO_DEPTH(i) - 1)) then
Writer_CounterControl <= '0';
end if;
end if;
end if;
end process;
Writer_Counter_en <= (In_Valid AND In_SOF) OR Writer_CounterControl;
process(Clock)
begin
if rising_edge(Clock) then
if (Writer_Counter_en = '0') then
Writer_Counter_us <= (others => '0');
else
Writer_Counter_us <= Writer_Counter_us + 1;
end if;
end if;
end process;
Meta_rst(i) <= NOT Writer_Counter_en;
In_Meta_nxt(i) <= Writer_Counter_en;
MetaFifO_put <= Writer_Counter_en;
MetaFifO_DataIn <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I));
MetaFifO : entity PoC.fifo_cc_got_tempgot
generic map (
D_BITS => META_BITS(i), -- Data Width
MIN_DEPTH => (META_FifO_DEPTH(i) * FRAMES), -- Minimum FifO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FifO Output
ESTATE_WR_BITS => 0, -- Empty State Bits
FSTATE_RD_BITS => 0 -- Full State Bits
)
port map (
-- Global Reset and Clock
clk => Clock,
rst => Reset,
-- Writing Interface
put => MetaFifO_put,
din => MetaFifO_DataIn,
full => MetaFifO_Full,
estate_wr => OPEN,
-- Reading Interface
got => MetaFifO_got,
dout => MetaFifO_DataOut,
valid => MetaFifO_Valid,
fstate_rd => OPEN,
commit => MetaFifO_Commit,
rollback => MetaFifO_Rollback
);
MetaFifO_got <= Out_Meta_nxt(i);
MetaFifO_Commit <= FrameCommit;
MetaFifO_Rollback <= Out_Meta_rst;
Out_Meta_Data(high(META_BITS, I) downto low(META_BITS, I)) <= MetaFifO_DataOut;
end generate; -- (META_FifO_DEPTH(i) > 1)
end generate;
end;
| apache-2.0 | 24b5c08ca5b951e50532616e23f8f5f6 | 0.553339 | 3.220006 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_rtl/old/CipherCore.vhd | 1 | 13,769 | -------------------------------------------------------------------------------
--! @file CipherCore.vhd
--! @brief Cipher core for dummy1
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.AEAD_pkg.ALL;
entity CipherCore is
generic (
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
--! Algorithm parameter to simulate run-time behavior
--! Warning: Do not set any number higher than 32
G_LAT_KEYINIT : integer := 4; --! Key inialization latency
G_LAT_PREP : integer := 12; --! Pre-processing latency (init)
G_LAT_PROC_AD : integer := 10; --! Processing latency (per block)
G_LAT_PROC_DATA : integer := 16; --! Processing latency (per block)
G_LAT_POST : integer := 20 --! Post-processing latency (tag)
);
port (
--! Global
clk : in std_logic;
rst : in std_logic;
--! PreProcessor (data)
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! PreProcessor (controls)
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_partial : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! PostProcessor
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : out std_logic;
bdo_ready : in std_logic;
bdo_size : out std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
--! Registers
signal bdi_r : std_logic_vector(128 -1 downto 0);
signal vbytes_r : std_logic_vector(128/8 -1 downto 0);
signal padloc_r : std_logic_vector(128/8 -1 downto 0);
signal key_block : std_logic_vector(128 -1 downto 0);
signal init_block : std_logic_vector(128 -1 downto 0);
signal ctr_block : std_logic_vector(32 -1 downto 0);
signal accum : std_logic_vector(128 -1 downto 0);
signal tag : std_logic_vector(128 -1 downto 0);
--! Signals
signal ctr_block128 : std_logic_vector(128 -1 downto 0);
signal accum_or_ctr : std_logic_vector(128 -1 downto 0);
signal to_output : std_logic_vector(128 -1 downto 0);
signal ad_or_msg : std_logic_vector(128 -1 downto 0);
--! Controls
--! Register
signal is_decrypt : std_logic;
--! Combinatorial
signal ctr : std_logic_vector(5 -1 downto 0);
signal clr_accum : std_logic;
signal ld_accum : std_logic;
signal ld_key : std_logic;
signal ld_npub : std_logic;
signal en_block : std_logic;
signal ld_ctr : std_logic;
signal ld_input : std_logic;
signal en_ctr : std_logic;
signal en_tag : std_logic;
signal sel_decrypt : std_logic;
signal sel_final : std_logic;
type t_state is (S_INIT, S_WAIT_START, S_WAIT_KEY, S_INIT_KEY,
S_WAIT_NPUB, S_INIT_MSG, S_WAIT_MSG,
S_PROC_AD, S_PROC_DATA, S_PROC_LENGTH,
S_WAIT_TAG_AUTH);
signal state : t_state;
signal nstate : t_state;
begin
--! =======================================================================
--! Datapath
--! =======================================================================
process(clk)
begin
if rising_edge(clk) then
if (ld_input = '1') then
bdi_r <= bdi;
vbytes_r <= bdi_valid_bytes;
padloc_r <= bdi_pad_loc;
end if;
if (ld_key = '1') then
key_block <= key;
end if;
if (ld_npub = '1') then
init_block <= bdi xor key_block;
end if;
if (clr_accum = '1') then
accum <= (others => '0');
elsif (ld_accum = '1') then
accum <= ad_or_msg xor accum;
end if;
if (clr_accum = '1') then
ctr_block <= (0 => '1', others => '0');
elsif (en_block = '1') then
ctr_block <= std_logic_vector(unsigned(ctr_block) + 1);
end if;
if (en_tag = '1') then
tag <= to_output;
end if;
end if;
end process;
ctr_block128(127 downto 32) <= (others => '0');
ctr_block128(31 downto 0 ) <= ctr_block;
accum_or_ctr <= accum when sel_final = '1' else ctr_block128;
to_output <= bdi_r xor accum_or_ctr xor init_block;
aBlock: block
signal vbits : std_logic_vector(G_DBLK_SIZE-1 downto 0);
signal data : std_logic_vector(G_DBLK_SIZE-1 downto 0);
signal pad : std_logic_vector(G_DBLK_SIZE-1 downto 0);
signal ext : std_logic_vector(G_DBLK_SIZE-1 downto 0);
begin
gVbits:
for i in 0 to G_DBLK_SIZE/8-1 generate
--! Get valid bits from valid bytes
vbits(8*i+7 downto 8*i) <= (others => vbytes_r(i));
--! Get padding bit
pad (8*i+7 ) <= padloc_r(i);
pad (8*i+6 downto 8*i) <= (others => '0');
end generate;
--! Use sel_final signal as a flag to determine whether
--! vbits should be used or not.
--! Note: sel_final is tag
ext(127 downto 0) <= (others => sel_final);
data <= bdi_r when sel_decrypt = '0' else to_output;
ad_or_msg <= (data and vbits) xor pad;
bdo <= to_output and (vbits or ext);
end block;
msg_auth_valid <= '1' when tag = bdi else '0';
--! =======================================================================
--! Control
--! =======================================================================
gSyncRst:
if (not G_ASYNC_RSTN) generate
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
state <= S_INIT;
else
state <= nstate;
end if;
end if;
end process;
end generate;
gAsyncRstn:
if (G_ASYNC_RSTN) generate
process(clk, rst)
begin
if (rst = '0') then
state <= S_INIT;
elsif rising_edge(clk) then
state <= nstate;
end if;
end process;
end generate;
process(clk)
begin
if rising_edge(clk) then
if (ld_ctr = '1') then
ctr <= (others => '0');
elsif (en_ctr = '1') then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
--! Store Decrypt signal internally for use during the tag
--! authentication state.
if (state = S_WAIT_START) then
is_decrypt <= decrypt;
end if;
end if;
end process;
process(
state, key_valid, key_update, is_decrypt, ctr,
bdi_valid, bdi_type, bdi_eot, bdi_eoi, bdi_size,
bdo_ready)
begin
--! Internal
nstate <= state;
clr_accum <= '0';
ld_accum <= '0';
ld_key <= '0';
ld_npub <= '0';
en_block <= '0';
ld_ctr <= '0';
ld_input <= '0';
en_tag <= '0';
en_ctr <= '0';
sel_decrypt <= '0';
sel_final <= '0';
--! External
key_ready <= '0';
bdi_ready <= '0';
bdo_valid <= '0';
msg_auth_done <= '0';
case state is
when S_INIT =>
--! After reset
clr_accum <= '1';
ld_ctr <= '1';
nstate <= S_WAIT_START;
when S_WAIT_START =>
--! Needs to check whether a new input is available first
--! prior to checking key to ensure the correct operational
--! step.
if (bdi_valid = '1') then
if (key_update = '1') then
nstate <= S_WAIT_KEY;
else
nstate <= S_WAIT_NPUB;
end if;
end if;
when S_WAIT_KEY =>
--! Wait for key
if (key_valid = '1') then
key_ready <= '1';
ld_key <= '1';
nstate <= S_INIT_KEY;
end if;
when S_INIT_KEY =>
--! Simulate key initialization delay
en_ctr <= '1';
if (unsigned(ctr) = G_LAT_KEYINIT-1) then
ld_ctr <= '1';
nstate <= S_WAIT_NPUB;
end if;
when S_WAIT_NPUB =>
bdi_ready <= '1';
if (bdi_valid = '1') then
ld_npub <= '1';
nstate <= S_INIT_MSG;
end if;
when S_INIT_MSG =>
--! Simulate msg initialization delay
en_ctr <= '1';
if (unsigned(ctr) = G_LAT_PREP-1) then
ld_ctr <= '1';
nstate <= S_WAIT_MSG;
end if;
when S_WAIT_MSG =>
--! Accumulate AD onto accum register
bdi_ready <= '1';
if (bdi_valid = '1') then
ld_input <= '1';
if (bdi_type = BDI_TYPE_ASS0) then
--! Note: Assume ST_AD is used (see: AEAD_pkg.vhd)
nstate <= S_PROC_AD;
elsif (bdi_type = BDI_TYPE_DAT0) then
nstate <= S_PROC_DATA;
else
--! Length type
nstate <= S_PROC_LENGTH;
end if;
end if;
when S_PROC_AD =>
--! Process AD
en_ctr <= '1';
if (unsigned(ctr) = G_LAT_PROC_AD-1) then
ld_accum <= '1';
ld_ctr <= '1';
nstate <= S_WAIT_MSG;
end if;
when S_PROC_DATA =>
--! Process Data
if (unsigned(ctr) = G_LAT_PROC_DATA-1) then
if (bdo_ready = '1') then
sel_decrypt <= is_decrypt;
ld_accum <= '1';
bdo_valid <= '1';
ld_ctr <= '1';
en_block <= '1';
nstate <= S_WAIT_MSG;
end if;
else
en_ctr <= '1';
end if;
when S_PROC_LENGTH =>
--! Process Length (generate tag)
if (unsigned(ctr) = G_LAT_POST-1) then
if (bdo_ready = '1' or is_decrypt = '1') then
sel_final <= '1';
ld_ctr <= '1';
if (is_decrypt = '1') then
en_tag <= '1';
nstate <= S_WAIT_TAG_AUTH;
else
bdo_valid <= '1';
nstate <= S_INIT;
end if;
end if;
else
en_ctr <= '1';
end if;
when S_WAIT_TAG_AUTH =>
--! Wait to compare tag
bdi_ready <= '1';
if (bdi_valid = '1') then
msg_auth_done <= '1';
nstate <= S_INIT;
end if;
end case;
end process;
end structure; | apache-2.0 | 6a9632c103ed5b004adc0b45a350d31b | 0.428779 | 4.099762 | false | false | false | false |
RussGlover/381-module-1 | project/hardware/vhdl/euclidean.vhd | 1 | 2,197 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library work;
use work.sqrt_package.all;
entity euclidean is
port(
input1values, input2values : in std_logic_vector(127 downto 0);
distance : out std_logic_vector(31 downto 0)
);
end euclidean;
architecture behavioural of euclidean is
signal operand : unsigned(31 downto 0);
signal input0bin0, input0bin1, input0bin2, input0bin3, input0bin4, input0bin5, input0bin6, input0bin7 : signed(15 downto 0);
signal input1bin0, input1bin1, input1bin2, input1bin3, input1bin4, input1bin5, input1bin6, input1bin7 : signed(15 downto 0);
begin
process(input1values, input2values)
begin
input0bin0 <= signed(input1values(15 downto 0));
input0bin1 <= signed(input1values(31 downto 16));
input0bin2 <= signed(input1values(47 downto 32));
input0bin3 <= signed(input1values(63 downto 48));
input0bin4 <= signed(input1values(78 downto 64));
input0bin5 <= signed(input1values(95 downto 79));
input0bin6 <= signed(input1values(111 downto 96));
input0bin7 <= signed(input1values(127 downto 112));
input1bin0 <= signed(input1values(15 downto 0));
input1bin1 <= signed(input1values(31 downto 16));
input1bin2 <= signed(input1values(47 downto 32));
input1bin3 <= signed(input1values(63 downto 48));
input1bin4 <= signed(input1values(78 downto 64));
input1bin5 <= signed(input1values(95 downto 79));
input1bin6 <= signed(input1values(111 downto 96));
input1bin7 <= signed(input1values(127 downto 112));
end process;
process(input0bin0, input0bin1, input0bin2, input0bin3, input0bin4, input0bin5, input0bin6, input0bin7, input1bin0, input1bin1, input1bin2, input1bin3, input1bin4, input1bin5, input1bin6, input1bin7)
begin
distance <= std_logic_vector(sqrt(to_unsigned((to_integer(input0bin0 - input1bin0)**2)
+ (to_integer(input0bin1 - input1bin1)**2)
+ (to_integer(input0bin2 - input1bin2)**2)
+ (to_integer(input0bin3 - input1bin3)**2)
+ (to_integer(input0bin4 - input1bin4)**2)
+ (to_integer(input0bin5 - input1bin5)**2)
+ (to_integer(input0bin6 - input1bin6)**2)
+ (to_integer(input0bin7 - input1bin7)**2), 32)));
end process;
end behavioural; | mit | ed8c6db4ed7204a61d88dbdbadfa21dc | 0.731452 | 2.845855 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_v10_v3_0/d6c0f905/hdl/vhdl/lmb_v10.vhd | 4 | 9,111 | -------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
| gpl-3.0 | d5af9eaa3e9ca76af847c4af4191dbc0 | 0.530128 | 3.911979 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sim_1/new/topmodule_tb.vhd | 1 | 1,974 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.01.2016 13:50:06
-- Design Name:
-- Module Name: topmodule_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity topmodule_tb is
-- Port ( );
end topmodule_tb;
architecture Behavioral of topmodule_tb is
constant Clk_period : time := 10ns;
signal clk : STD_LOGIC;
signal JA0 : STD_LOGIC;
signal JA1 : STD_LOGIC;
signal JA2 : STD_LOGIC;
signal JA3 : STD_LOGIC;
signal RsTx : STD_LOGIC;
signal btnCpuReset : STD_LOGIC := '1';
begin
UUT: entity work.topmodule(Behavioral)
port map (
clk => clk,
btnCpuReset => btnCpuReset,
JA0 => JA0,
JA1 => JA1,
JA2 => JA2,
JA3 => JA3,
RsTx => RsTx
);
-- Clock process definitions
Clk_process :process
begin
clk <= '0';
wait for Clk_period/2;
clk <= '1';
wait for Clk_period/2;
end process;
-- random reset program
reset_process : process
begin
btnCpuReset <= '0';
wait for Clk_period * 200;
btnCpuReset <= '1';
-- JA1 <= 'H';
wait for Clk_period * 2555;
-- JA1 <= '0';
wait for Clk_period * 249;
-- JA1 <= 'H';
wait for Clk_period * 999;
wait for Clk_period * 999;
wait;
end process;
JA0 <= 'H';
JA1 <= 'H';
end Behavioral;
| gpl-3.0 | 5ce2595c026bd9d70e715e489ae9b9b6 | 0.550659 | 3.738636 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_rtl/CipherCore.vhd | 1 | 26,165 | -------------------------------------------------------------------------------
--! @file CipherCore.vhd
--! @author Hannes Gross
--! @brief Generic Ascon-128(a) implementation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity CipherCore is
generic (
-- Ascon related generics
RATE : integer := 64; -- Selects:
-- (64) -> Ascon128
-- (128)-> Acon128a
UNROLED_ROUNDS : integer := 6; -- Ascon128: 1, 2, 3, or 6 rounds
-- Ascon128a: 1, 2, or 4 rounds
ROUNDS_A : integer := 12; -- Number of rounds for initialization
-- and finalization
ROUNDS_B : integer := 6; -- Num permutation rounds for data for
-- (6) -> Ascon128
-- (8) -> Ascon128a
--- Interface generics:
-- Reset behavior
G_ASYNC_RSTN : boolean := false; --! Async active low reset
-- Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 32; --! Key
G_TAG_SIZE : integer := 128; --! Tag
-- The number of bits required to hold block size expressed in
-- bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4
);
port (
--! Global
clk : in std_logic;
rst : in std_logic;
--! PreProcessor (data)
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! PreProcessor (controls)
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_partial : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! PostProcessor
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : out std_logic;
bdo_ready : in std_logic;
bdo_size : out std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Constants
constant CONST_UNROLED_R : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(UNROLED_ROUNDS, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
constant CONST_ROUNDS_AmR: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A-UNROLED_ROUNDS, 4));
constant CONST_ROUNDS_BmR: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B-UNROLED_ROUNDS, 4));
constant CONST_RATE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(RATE, 8));
constant STATE_WORD_SIZE : integer := 64;
constant KEY_SIZE : integer := 128;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
-- Segment Type Encoding
constant TYPE_AD : std_logic_vector(2 downto 0) := "000";
constant TYPE_PTCT : std_logic_vector(2 downto 0) := "010";
constant TYPE_TAG : std_logic_vector(2 downto 0) := "100";
constant TYPE_LEN : std_logic_vector(2 downto 0) := "101";
constant TYPE_NONCE : std_logic_vector(2 downto 0) := "110";
-- FSM state definition
type state_t is (STATE_IDLE,
STATE_UPDATE_KEY,
STATE_WRITE_NONCE_0,
STATE_WRITE_NONCE_1,
STATE_INITIALIZATION,
STATE_PERMUTATION,
STATE_FINALIZATION,
STATE_WAIT_FOR_INPUT,
STATE_PROCESS_TAG_0,
STATE_PROCESS_TAG_1);
-- FSM next and present state signals
signal State_DN,State_DP : state_t;
-- Ascon's state registers
signal X0_DN, X0_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X1_DN, X1_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X2_DN, X2_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X3_DN, X3_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X4_DN, X4_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
-- Key register
signal Keyreg_DN : std_logic_vector(KEY_SIZE-1 downto 0);
signal Keyreg_DP : std_logic_vector(KEY_SIZE-1 downto 0);
-- Round counter
signal RoundCounter_DN : std_logic_vector(3 downto 0);
signal RoundCounter_DP : std_logic_vector(3 downto 0);
signal DisableRoundCounter_S : std_logic;
-- Additional control logic registers
signal IsFirstPTCT_DN, IsFirstPTCT_DP : std_logic;
signal IsDecryption_DN, IsDecryption_DP : std_logic;
-- Helper function, rotates a state word
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
begin -- ROTATE_STATE_WORD
return word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
end ROTATE_STATE_WORD;
begin
-----------------------------------------------------------------------------
-- State operations (permutation, data loading, et cetera)
state_opeartions_p : process (IsDecryption_DP, IsFirstPTCT_DP,
Keyreg_DP, RoundCounter_DP,
RoundCounter_DP, State_DN,
State_DP, X0_DP,
X1_DP, X2_DP, X3_DP,
X4_DP, bdi,
bdi, bdi_eot, bdi_type,
bdi_valid, bdi_valid_bytes, decrypt) is
-- Roudn permutation input, intermediates, and output
variable P0_DV, P1_DV, P2_DV, P3_DV, P4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable R0_DV, R1_DV, R2_DV, R3_DV, R4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable S0_DV, S1_DV, S2_DV, S3_DV, S4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable T0_DV, T1_DV, T2_DV, T3_DV, T4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable U0_DV, U1_DV, U2_DV, U3_DV, U4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
-- Round constant
variable RoundConst_DV : std_logic_vector(63 downto 0);
-- Second part of tag comparison
variable TagCompResult_DV : std_logic_vector(RATE-1 downto 0);
begin -- process state_opeartions_p
--- Default values:
-- State variable X0-X4 --> keep current value
X0_DN <= X0_DP; X1_DN <= X1_DP; X2_DN <= X2_DP; X3_DN <= X3_DP; X4_DN <= X4_DP;
-- Permutation input --> use current state as default input
P0_DV := X0_DP; P1_DV := X1_DP; P2_DV := X2_DP; P3_DV := X3_DP; P4_DV := X4_DP;
-- Reset informational signals, when perfoming initialization
if State_DP = STATE_INITIALIZATION then
IsFirstPTCT_DN <= '1';
IsDecryption_DN <= decrypt;
else -- otherwise just keep value
IsFirstPTCT_DN <= IsFirstPTCT_DP;
IsDecryption_DN <= IsDecryption_DP;
end if;
--- P0,[P1] MUX: When data input is ready --> select P0,[P1] accordingly
if State_DP = STATE_WAIT_FOR_INPUT and (bdi_valid = '1') then
-- Encryption
if (IsDecryption_DP = '0') or (bdi_type = TYPE_AD) then
if RATE = 128 then -- Ascon128a variant
P0_DV := X0_DP xor bdi(RATE-1 downto RATE-64);
P1_DV := X1_DP xor bdi(63 downto 0);
else
P0_DV := X0_DP xor bdi;
end if;
-- Decryption
else
-- We need to take care of the number of valid bytes!
for i in 7 downto 0 loop
if RATE = 128 then -- Ascon128a variant
-- P1 xor input data ...
P0_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 + 64 downto i*8 + 64);
P1_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 downto i*8);
-- if invalid byte then use additionally xor X1
if bdi_valid_bytes(i) = '0' then
P1_DV(i*8 + 7 downto i*8) := P1_DV(i*8 + 7 downto i*8) xor X1_DP(i*8 + 7 downto i*8);
end if;
-- if invalid byte then use additionally xor X0
if bdi_valid_bytes(i+8) = '0' then
P0_DV(i*8 + 7 downto i*8) := P0_DV(i*8 + 7 downto i*8) xor X0_DP(i*8 + 7 downto i*8);
end if;
else -- Ascon128 variant
-- P0 xor input data ...
P0_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 downto i*8);
-- if invalid byte then use additionally xor X0
if bdi_valid_bytes(i) = '0' then
P0_DV(i*8 + 7 downto i*8) := P0_DV(i*8 + 7 downto i*8) xor X0_DP(i*8 + 7 downto i*8);
end if;
end if;
end loop; -- i
end if;
--- P1[2]-4 MUX:
-- if performing FINALIZATION next
if State_DN = STATE_FINALIZATION then
-- TODO: when 128a variant write P2
-- Add key before permutation
if RATE = 64 then -- Ascon128 variant
P1_DV := P1_DV xor Keyreg_DP(127 downto 64);
P2_DV := P2_DV xor Keyreg_DP(63 downto 0);
else -- Ascon128a variant
P2_DV := P2_DV xor Keyreg_DP(127 downto 64);
P3_DV := P3_DV xor Keyreg_DP(63 downto 0);
end if;
-- If first PT/CT never processed (empty AD + PT/CT case)
if (IsFirstPTCT_DP = '1') then
P4_DV(0) := not P4_DV(0); -- Add 0*||1
end if;
-- if performing PERMUTATION next
elsif ((bdi_valid = '1') and not ((bdi_type = TYPE_TAG) or
(bdi_type = TYPE_PTCT and bdi_eot = '1'))) then
-- ... and first round of PT/CT calculation
if (bdi_type = TYPE_PTCT) and (IsFirstPTCT_DP = '1') then
IsFirstPTCT_DN <= '0'; -- SET first PT/CT performed
P4_DV(0) := not P4_DV(0); -- Add 0*||1
end if;
end if;
end if;
-- Unroled round permutation
for r in 0 to UNROLED_ROUNDS-1 loop
-- Calculate round constant
RoundConst_DV := (others => '0'); -- set to zero
RoundConst_DV(7 downto 0) := not std_logic_vector(unsigned(RoundCounter_DP(3 downto 0)) + r) &
std_logic_vector(unsigned(RoundCounter_DP(3 downto 0)) + r);
R0_DV := P0_DV xor P4_DV;
R1_DV := P1_DV;
R2_DV := P2_DV xor P1_DV xor RoundConst_DV;
R3_DV := P3_DV;
R4_DV := P4_DV xor P3_DV;
S0_DV := R0_DV xor (not R1_DV and R2_DV);
S1_DV := R1_DV xor (not R2_DV and R3_DV);
S2_DV := R2_DV xor (not R3_DV and R4_DV);
S3_DV := R3_DV xor (not R4_DV and R0_DV);
S4_DV := R4_DV xor (not R0_DV and R1_DV);
T0_DV := S0_DV xor S4_DV;
T1_DV := S1_DV xor S0_DV;
T2_DV := not S2_DV;
T3_DV := S3_DV xor S2_DV;
T4_DV := S4_DV;
U0_DV := T0_DV xor ROTATE_STATE_WORD(T0_DV, 19) xor ROTATE_STATE_WORD(T0_DV, 28);
U1_DV := T1_DV xor ROTATE_STATE_WORD(T1_DV, 61) xor ROTATE_STATE_WORD(T1_DV, 39);
U2_DV := T2_DV xor ROTATE_STATE_WORD(T2_DV, 1) xor ROTATE_STATE_WORD(T2_DV, 6);
U3_DV := T3_DV xor ROTATE_STATE_WORD(T3_DV, 10) xor ROTATE_STATE_WORD(T3_DV, 17);
U4_DV := T4_DV xor ROTATE_STATE_WORD(T4_DV, 7) xor ROTATE_STATE_WORD(T4_DV, 41);
P0_DV := U0_DV;
P1_DV := U1_DV;
P2_DV := U2_DV;
P3_DV := U3_DV;
P4_DV := U4_DV;
end loop;
-- Do tag comparison when doing decryption in PROCESS TAG states
msg_auth_done <= '0'; --default
msg_auth_valid <= '0';
if IsDecryption_DP = '1' then
if (State_DP = STATE_PROCESS_TAG_0) then
-- valid data for comparison ready?
if bdi_valid = '1' then
if RATE = 128 then -- Ascon128a variant
-- signal we are done with comparison
msg_auth_done <= '1';
-- tags equal?
TagCompResult_DV := (X3_DP & X4_DP) xor Keyreg_DP;
if (TagCompResult_DV = bdi) then
msg_auth_valid <= '1';
end if;
else -- Ascon128 variant
X3_DN <= X3_DP xor Keyreg_DP(127 downto 64) xor bdi;
end if;
end if;
elsif (State_DP = STATE_PROCESS_TAG_1) then
-- debug
if RATE = 64 then -- Ascon128 variant
-- valid data for comparison ready?
if bdi_valid = '1' then
-- signal we are done with comparison
msg_auth_done <= '1';
-- Check if tags are equal
TagCompResult_DV := (X4_DP xor Keyreg_DP(63 downto 0) xor bdi);
if (X3_DP & TagCompResult_DV) = x"00000000000000000000000000000000" then
msg_auth_valid <= '1';
end if;
end if;
end if;
end if;
end if;
--- State X0...4 MUX: select input of state registers
case State_DP is
-- WRITE_NONCE_0 --> and init state
when STATE_WRITE_NONCE_0 =>
-- ready to receive
if (bdi_valid = '1') then
-- fill X0 with IV
X0_DN <= CONST_KEY_SIZE & CONST_RATE & CONST_ROUNDS_A & CONST_ROUNDS_B & x"00000000";
X1_DN <= Keyreg_DP(127 downto 64);
X2_DN <= Keyreg_DP(63 downto 0);
if RATE = 128 then -- Ascon128a variant
X3_DN <= bdi(RATE-1 downto RATE-64);
X4_DN <= bdi( 63 downto 0);
else -- Ascon128 variant
X3_DN <= bdi(63 downto 0);
end if;
end if;
-- WRITE_NONCE_1 --> second part of nonce
when STATE_WRITE_NONCE_1 =>
-- ready to receive
if (bdi_valid = '1') then
X4_DN <= bdi;
end if;
-- INITIALIZATION, PERMUTATION, FINALIZATION --> apply round transformation
when STATE_PERMUTATION | STATE_INITIALIZATION | STATE_FINALIZATION =>
X0_DN <= P0_DV; X1_DN <= P1_DV; X2_DN <= P2_DV;
-- Add key after initialization
if (State_DP = STATE_INITIALIZATION and RoundCounter_DP = CONST_ROUNDS_AmR) then
X3_DN <= P3_DV xor Keyreg_DP(127 downto 64);
X4_DN <= P4_DV xor Keyreg_DP(63 downto 0);
else
X3_DN <= P3_DV;
X4_DN <= P4_DV;
end if;
-- WAIT FOR INPUT --> apply round transformation when input is ready
when STATE_WAIT_FOR_INPUT =>
if bdi_valid = '1' then
-- State <= permutation output
X0_DN <= P0_DV; X1_DN <= P1_DV; X2_DN <= P2_DV; X3_DN <= P3_DV; X4_DN <= P4_DV;
end if;
when others => null;
end case;
end process state_opeartions_p;
-----------------------------------------------------------------------------
-- Update key register --> simple shift register
key_update_p: process (Keyreg_DP, State_DP, key, key_valid) is
begin -- process key_update_p
Keyreg_DN <= Keyreg_DP; -- default
key_ready <= '0';
-- only update key while in the update state
if State_DP = STATE_UPDATE_KEY then
key_ready <= '1'; -- always ready
-- shift register and insert new key data
if key_valid = '1' then
Keyreg_DN <= Keyreg_DP (KEY_SIZE-G_KEY_SIZE-1 downto 0) & key;
end if;
end if;
end process key_update_p;
-----------------------------------------------------------------------------
-- Input logic --> controlling input interface signals
input_logic_p: process (State_DP, bdi_type, bdi_valid) is
begin -- process input_logic_p
bdi_ready <= '1'; -- default, ready
-- We dont require LENGTH segment, but we acknowlede it command is received
if (State_DP = STATE_IDLE and not((bdi_type = TYPE_LEN) and (bdi_valid = '1'))) or
State_DP = STATE_INITIALIZATION or
State_DP = STATE_PERMUTATION or
State_DP = STATE_FINALIZATION then
-- signal busyness
bdi_ready <= '0';
end if;
end process input_logic_p;
-----------------------------------------------------------------------------
-- Output logic --> controlling output interface signals
output_logic_p: process (Keyreg_DP,
State_DP, X0_DP, X1_DP, X3_DP, X4_DP, bdi,
bdi, bdi_size,
bdi_type, bdi_valid, bdo_ready) is
begin -- process output_logic_p
bdo_valid <= '0'; -- default, nothing to output
if RATE = 128 then -- Ascon128a variant
bdo(RATE-1 downto RATE-64) <= X0_DP xor bdi(RATE-1 downto RATE-64);
bdo(63 downto 0) <= X1_DP xor bdi(63 downto 0);
else -- Ascon128 variant
bdo <= X0_DP xor bdi;
end if;
-- Wait for output to be ready
if bdo_ready = '1' then
-- waiting for output of PT/CT and there is something to output (size > 0)?
if (State_DP = STATE_WAIT_FOR_INPUT) then
if (bdi_valid = '1') and (bdi_type = TYPE_PTCT) and (bdi_size /= (bdi_size'range => '0')) then
bdo_valid <= '1';
end if;
-- output Tag part 1
elsif State_DP = STATE_PROCESS_TAG_0 then
bdo_valid <= '1';
if RATE = 128 then -- Ascon128a variant
bdo(RATE-1 downto RATE-64) <= X3_DP xor Keyreg_DP(127 downto 64);
bdo(63 downto 0) <= X4_DP xor Keyreg_DP(63 downto 0);
else -- Ascon128 variant
bdo <= X3_DP xor Keyreg_DP(127 downto 64);
end if;
-- output Tag part 2
elsif State_DP = STATE_PROCESS_TAG_1 then
bdo_valid <= '1';
bdo <= X4_DP xor Keyreg_DP(63 downto 0);
end if;
end if;
end process output_logic_p;
-----------------------------------------------------------------------------
-- Next state logic
fsm_comb_p: process (IsDecryption_DP, RoundCounter_DP, State_DP, bdi_eot,
bdi_type, bdi_valid, bdo_ready, key_update, key_valid) is
begin -- process fsm_comb_p
State_DN <= State_DP; -- default
-- FSM state transfers
case State_DP is
-- IDLE
when STATE_IDLE =>
-- preprocessor forces key update
if (key_update = '1') then
State_DN <= STATE_UPDATE_KEY;
-- skip key update and start writing the nonce
elsif (bdi_valid = '1') and (bdi_type = TYPE_NONCE) then
State_DN <= STATE_WRITE_NONCE_0;
end if;
-- UPDATE_KEY
when STATE_UPDATE_KEY =>
-- when key is invalid we assume the key update is finished
if (key_valid = '0' and key_update = '0') then
-- go back to IDLE
State_DN <= STATE_IDLE;
end if;
-- WRITE_NONCE_0 (Part 1)
when STATE_WRITE_NONCE_0 =>
-- write first part of nonce
if (bdi_valid = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_INITIALIZATION;
else
State_DN <= STATE_WRITE_NONCE_1;
end if;
end if;
-- WRITE_NONCE_1 (Part 2)
when STATE_WRITE_NONCE_1 =>
-- write second part of nonce
if (bdi_valid = '1') then
State_DN <= STATE_INITIALIZATION;
end if;
-- INITIALIZATION
when STATE_INITIALIZATION =>
if RoundCounter_DP = CONST_ROUNDS_AmR then
State_DN <= STATE_WAIT_FOR_INPUT;
end if;
-- PERMUTATION
when STATE_PERMUTATION =>
if RoundCounter_DP = CONST_ROUNDS_BmR then
State_DN <= STATE_WAIT_FOR_INPUT;
end if;
-- FINALIZATION
when STATE_FINALIZATION =>
if RoundCounter_DP = CONST_ROUNDS_AmR then
State_DN <= STATE_PROCESS_TAG_0;
end if;
-- PROCESS TAG PART 1
when STATE_PROCESS_TAG_0 =>
-- encryption -> wait for output stream to be ready
if (IsDecryption_DP = '0') then
if (bdo_ready = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_IDLE;
else -- Ascon128 variant
State_DN <= STATE_PROCESS_TAG_1;
end if;
end if;
else
-- decryption -> wait for tag for comparison
if (bdi_valid = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_IDLE;
else -- Ascon128 variant
State_DN <= STATE_PROCESS_TAG_1;
end if;
end if;
end if;
-- PROCESS TAG PART 2
when STATE_PROCESS_TAG_1 =>
-- encryption -> wait for output stream to be ready
if (IsDecryption_DP = '0') then
if (bdo_ready = '1') then
State_DN <= STATE_IDLE;
end if;
else
-- decryption -> wait for tag for comparison
if (bdi_valid = '1') then
State_DN <= STATE_IDLE;
end if;
end if;
-- WAIT_FOR_INPUT
when STATE_WAIT_FOR_INPUT =>
-- input is ready so process
if (bdi_valid = '1') then
-- if its a tag or last PT/CT then...
if (bdi_type = TYPE_TAG) or
(bdi_type = TYPE_PTCT and bdi_eot = '1')then
State_DN <= STATE_FINALIZATION;
else -- process AD or PT/CT
-- PERMUTATION state is unnecessary if we fully unroll
if (UNROLED_ROUNDS /= ROUNDS_B) then
State_DN <= STATE_PERMUTATION;
end if;
end if;
end if;
when others => null;
end case;
end process fsm_comb_p;
-----------------------------------------------------------------------------
-- Round counter realization
round_counter_p: process (DisableRoundCounter_S, RoundCounter_DP, State_DP,
bdi_valid) is
variable CounterVal_DV : integer;
begin -- process round_counter_p
RoundCounter_DN <= RoundCounter_DP; -- default
-- Enable counter during ...
if (State_DP = STATE_PERMUTATION) or
(State_DP = STATE_INITIALIZATION) or
(State_DP = STATE_FINALIZATION) or
(State_DP = STATE_WAIT_FOR_INPUT and bdi_valid = '1') then
-- Counter += #unroled rounds
CounterVal_DV := to_integer(unsigned(RoundCounter_DP)) + UNROLED_ROUNDS; -- increment
-- Overrun detection --> set back to 0
if (CounterVal_DV >= ROUNDS_A) or (State_DP = STATE_PERMUTATION and CounterVal_DV >= ROUNDS_B) then
CounterVal_DV := 0;
end if;
-- set next counter register value
RoundCounter_DN <= std_logic_vector(to_unsigned(CounterVal_DV, RoundCounter_DN'length));
else -- Disable round counter and set it to zero
RoundCounter_DN <= (others => '0');
end if;
end process round_counter_p;
-----------------------------------------------------------------------------
-- Process for all registers in design
gen_register_with_asynchronous_reset : if G_ASYNC_RSTN = false generate
register_process_p : process (clk, rst) is
begin -- process register_process_p
if rst = '1' then -- asynchronous reset (active high)
State_DP <= STATE_IDLE;
X0_DP <= (others => '0');
X1_DP <= (others => '0');
X2_DP <= (others => '0');
X3_DP <= (others => '0');
X4_DP <= (others => '0');
Keyreg_DP <= (others => '0');
RoundCounter_DP <= (others => '0');
IsFirstPTCT_DP <= '1';
IsDecryption_DP <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
State_DP <= State_DN;
X0_DP <= X0_DN;
X1_DP <= X1_DN;
X2_DP <= X2_DN;
X3_DP <= X3_DN;
X4_DP <= X4_DN;
Keyreg_DP <= Keyreg_DN;
RoundCounter_DP <= RoundCounter_DN;
IsFirstPTCT_DP <= IsFirstPTCT_DN;
IsDecryption_DP <= IsDecryption_DN;
end if;
end process register_process_p;
end generate gen_register_with_asynchronous_reset;
-- else generate with synchronous reset
gen_register_with_synchronous_reset : if G_ASYNC_RSTN = true generate
register_process_p : process (clk, rst) is
begin -- process register_process_p
if clk'event and clk = '1' then -- rising clock edge
if rst = '1' then -- synchronous reset (active high)
State_DP <= STATE_IDLE;
X0_DP <= (others => '0');
X1_DP <= (others => '0');
X2_DP <= (others => '0');
X3_DP <= (others => '0');
X4_DP <= (others => '0');
Keyreg_DP <= (others => '0');
RoundCounter_DP <= (others => '0');
IsFirstPTCT_DP <= '1';
IsDecryption_DP <= '0';
else
State_DP <= State_DN;
X0_DP <= X0_DN;
X1_DP <= X1_DN;
X2_DP <= X2_DN;
X3_DP <= X3_DN;
X4_DP <= X4_DN;
Keyreg_DP <= Keyreg_DN;
RoundCounter_DP <= RoundCounter_DN;
IsFirstPTCT_DP <= IsFirstPTCT_DN;
IsDecryption_DP <= IsDecryption_DN;
end if;
end if;
end process register_process_p;
end generate gen_register_with_synchronous_reset;
end structure;
| apache-2.0 | 58755a85cf1c69d55bc1b1d4ea807d15 | 0.521651 | 3.642628 | false | false | false | false |
bpervan/uart | BaudRateGenerator.vhd | 1 | 1,377 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:25 03/11/2014
-- Design Name:
-- Module Name: BaudRateGenerator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BaudRateGenerator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC);
end BaudRateGenerator;
architecture Behavioral of BaudRateGenerator is
signal brojac, brojacNext : unsigned (7 downto 0);
begin
process (clk, rst)
begin
if(rst = '1') then
brojac <= "00000000";
else
if (clk'event and clk = '1') then
brojac <= brojacNext;
end if;
end if;
end process;
brojacNext <= "00000000" when brojac = 176 else
brojac + 1;
tick <= '1' when brojac = 176 else '0';
end Behavioral;
| mit | 559e9d5c8b2e7bbdf8a2487b93551453 | 0.590414 | 3.752044 | false | false | false | false |
hoangt/PoC | tb/misc/sync/sync_Strobe_tb.vhdl | 2 | 3,288 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a strobe signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Strobe_tb is
end;
architecture test of sync_Strobe_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal Sync_out : STD_LOGIC_VECTOR(0 downto 0);
signal Sync_Busy : STD_LOGIC_VECTOR(0 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "X";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "1";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "0";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncStrobe : entity PoC.sync_Strobe
generic map (
BITS => 1, -- number of bit to be synchronized
GATED_INPUT_BY_BUSY => TRUE -- use gated input (by busy signal)
)
port map (
Clock1 => Clock1, -- input clock domain
Clock2 => Clock2, -- output clock domain
Input => Sync_in, -- input bits
Output => Sync_out, -- output bits
Busy => Sync_Busy -- busy bits
);
end;
| apache-2.0 | 82ead556f41c991bad4a1304eec0410b | 0.561436 | 3.265144 | false | false | false | false |
lowRISC/greth-library | greth_library/commonlib/types_common.vhd | 2 | 6,651 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Declaration and implementation of the types_common package.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--! @brief Definition of the generic VHDL methods and constants.
--! @details This package defines common mathematical methods and
--! utility methods for the VHDL types conversions.
package types_common is
--! @brief Array declaration of the pre-computed log2 values.
type log2arr is array(0 to 512) of integer;
--! @brief Array definition of the pre-computed log2 values.
--! @details These values are used as an argument in bus width
--! declaration.
--!
--! Example usage:
--! @code
--! component foo_component is
--! generic (
--! max_clients : integer := 8
--! );
--! port (
--! foo : inout std_logic_vector(log2(max_clients)-1 downto 0)
--! );
--! end component;
--! @endcode
constant log2 : log2arr := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant log2x : log2arr := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant zero32 : std_logic_vector(31 downto 0) := X"00000000";
constant zero64 : std_logic_vector(63 downto 0) := zero32 & zero32;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
function "-" (a, b : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
function "+" (a, b : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function conv_integer(v : std_logic_vector) return integer;
function conv_integer(v : std_logic) return integer;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
function conv_std_logic(b : boolean) return std_ulogic;
end;
package body types_common is
function conv_integer(v : std_logic_vector) return integer is
begin
if not is_x(v) then return(to_integer(unsigned(v)));
else return(0); end if;
end;
function conv_integer(v : std_logic) return integer is
begin
if not is_x(v) then
if v = '1' then return(1);
else return(0); end if;
else return(0); end if;
end;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_unsigned(i, w));
return(tmp);
end;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_signed(i, w));
return(tmp);
end;
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) + unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(i - unsigned(d)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if not is_x(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) - unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
end;
| bsd-2-clause | bb0f786109689f948259831f57888835 | 0.628627 | 2.410656 | false | false | false | false |
hoangt/PoC | src/comm/comm.pkg.vhdl | 2 | 2,766 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: VHDL package for component declarations, types and
-- functions associated to the PoC.comm namespace
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
package comm is
-- Calculates the Remainder of the Division by the Generator Polynomial GEN.
component comm_crc is
generic (
GEN : bit_vector; -- Generator Polynom
BITS : positive -- Number of Bits to be processed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Parallel Preload of Remainder
init : in std_logic_vector(GEN'length-2 downto 0); --
step : in std_logic; -- Process Input Data (MSB first)
din : in std_logic_vector(BITS-1 downto 0); --
rmd : out std_logic_vector(GEN'length-2 downto 0); -- Remainder
zero : out std_logic -- Remainder is Zero
);
end component;
-- Computes XOR masks for stream scrambling from an LFSR generator.
component comm_scramble is
generic (
GEN : bit_vector; -- Generator Polynomial (little endian)
BITS : positive -- Width of Mask Bits to be computed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Set LFSR to provided Value
din : in std_logic_vector(GEN'length-2 downto 0); --
step : in std_logic; -- Compute a Mask Output
mask : out std_logic_vector(BITS-1 downto 0) --
);
end component;
end package;
| apache-2.0 | 599f2a8e49b9f46b9b5bb12a126de4aa | 0.569053 | 4.020349 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_rx_agile.vhd | 4 | 15,461 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_rx_agile.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_rx_agile is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Rx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Rmii2Mac_rx_clk : out std_logic;
Rmii2Mac_crs : out std_logic;
Rmii2Mac_rx_dv : out std_logic;
Rmii2Mac_rx_er : out std_logic;
Rmii2Mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY --------------------------------
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0)
);
end rmii_rx_agile;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_rx_agile is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component rx_fifo_loader
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end component;
component rx_fifo
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_fifo_wr_en : in std_logic;
Rx_fifo_rd_en : in std_logic;
Rx_fifo_input : in std_logic_vector(15 downto 0);
Rx_fifo_mt_n : out std_logic;
Rx_fifo_full : out std_logic;
Rx_fifo_output : out std_logic_vector(15 downto 0)
);
end component;
component rx_fifo_disposer
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constant Declarations
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
signal rx_fifo_wr_en : std_logic;
signal rx_fifo_rd_en : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_mt_n : std_logic;
signal rx_10 : std_logic;
signal rx_100 : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_valid : std_logic;
signal rx_cary_sense : std_logic;
signal rx_error : std_logic;
signal rx_end_of_packet : std_logic;
signal rx_mii_eop : std_logic_vector(1 downto 0);
signal rx_mii_crs : std_logic_vector(1 downto 0);
signal rx_mii_er : std_logic_vector(1 downto 0);
signal rx_mii_dv : std_logic_vector(1 downto 0);
signal rx_mii_data : std_logic_vector(7 downto 0);
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
Rmii2Mac_crs <= rx_cary_sense;
------------------------------------------------------------------------------
-- Component Instantiations
------------------------------------------------------------------------------
I_RX_FIFO_LOADER : rx_fifo_loader
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Phy2Rmii_crs_dv => Phy2Rmii_crs_dv,
Phy2Rmii_rx_er => Phy2Rmii_rx_er,
Phy2Rmii_rxd => Phy2Rmii_rxd,
Rx_fifo_wr_en => rx_fifo_wr_en,
Rx_10 => rx_10,
Rx_100 => rx_100,
Rx_data => rx_data,
Rx_error => rx_error,
Rx_data_valid => rx_data_valid,
Rx_cary_sense => rx_cary_sense,
Rx_end_of_packet => rx_end_of_packet
);
I_RX_FIFO : rx_fifo
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Rx_fifo_wr_en => rx_fifo_wr_en,
Rx_fifo_rd_en => rx_fifo_rd_en,
Rx_fifo_input(15) => rx_end_of_packet,
Rx_fifo_input(14) => rx_cary_sense,
Rx_fifo_input(13) => rx_error,
Rx_fifo_input(12) => rx_data_valid,
Rx_fifo_input(11) => rx_data(7),
Rx_fifo_input(10) => rx_data(6),
Rx_fifo_input(9) => rx_data(5),
Rx_fifo_input(8) => rx_data(4),
Rx_fifo_input(7) => rx_end_of_packet,
Rx_fifo_input(6) => rx_cary_sense,
Rx_fifo_input(5) => rx_error,
Rx_fifo_input(4) => rx_data_valid,
Rx_fifo_input(3) => rx_data(3),
Rx_fifo_input(2) => rx_data(2),
Rx_fifo_input(1) => rx_data(1),
Rx_fifo_input(0) => rx_data(0),
Rx_fifo_mt_n => rx_fifo_mt_n,
Rx_fifo_full => rx_fifo_full,
Rx_fifo_output(15) => rx_mii_eop(1),
Rx_fifo_output(14) => rx_mii_crs(1),
Rx_fifo_output(13) => rx_mii_er(1),
Rx_fifo_output(12) => rx_mii_dv(1),
Rx_fifo_output(11) => rx_mii_data(7),
Rx_fifo_output(10) => rx_mii_data(6),
Rx_fifo_output(9) => rx_mii_data(5),
Rx_fifo_output(8) => rx_mii_data(4),
Rx_fifo_output(7) => rx_mii_eop(0),
Rx_fifo_output(6) => rx_mii_crs(0),
Rx_fifo_output(5) => rx_mii_er(0),
Rx_fifo_output(4) => rx_mii_dv(0),
Rx_fifo_output(3) => rx_mii_data(3),
Rx_fifo_output(2) => rx_mii_data(2),
Rx_fifo_output(1) => rx_mii_data(1),
Rx_fifo_output(0) => rx_mii_data(0)
);
I_RX_FIFO_DISPOSER : rx_fifo_disposer
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Rx_10 => rx_10,
Rx_100 => rx_100,
Rmii_rx_eop => rx_mii_eop,
Rmii_rx_crs => rx_mii_crs,
Rmii_rx_er => rx_mii_er,
Rmii_rx_dv => rx_mii_dv,
Rmii_rx_data => rx_mii_data,
Rx_fifo_mt_n => rx_fifo_mt_n,
Rx_fifo_rd_en => rx_fifo_rd_en,
-- Rmii2mac_crs => Rmii2mac_crs,
Rmii2mac_crs => open,
Rmii2mac_rx_clk => Rmii2mac_rx_clk,
Rmii2mac_rx_er => Rmii2mac_rx_er,
Rmii2mac_rx_dv => Rmii2mac_rx_dv,
Rmii2mac_rxd => Rmii2mac_rxd
);
end simulation;
| gpl-3.0 | d9ca5b8a80d03809950f6bf8509a3a3f | 0.43697 | 4.17752 | false | false | false | false |
hoangt/PoC | src/io/io_PulseWidthModulation.vhdl | 2 | 3,482 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Pulse Width Modulated (PWM) signal generator
--
-- Description:
-- ------------------------------------
-- This module generates a pulse width modulated signal, that can be configured
-- in frequency (PWM_FREQ) and modulation granularity (PWM_RESOLUTION).
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_PulseWidthModulation is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
PWM_FREQ : FREQ := 1 kHz;
PWM_RESOLUTION : POSITIVE := 8
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
PWMIn : in STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0);
PWMOut : out STD_LOGIC
);
end;
architecture rtl of io_PulseWidthModulation is
constant PWM_STEPS : POSITIVE := 2**PWM_RESOLUTION;
constant PWM_STEP_FREQ : FREQ := PWM_FREQ * real(PWM_STEPS - 1);
constant PWM_FREQUENCYCOUNTER_MAX : POSITIVE := TimingToCycles(to_time(PWM_STEP_FREQ), CLOCK_FREQ);
constant PWM_FREQUENCYCOUNTER_BITS : POSITIVE := log2ceilnz(PWM_FREQUENCYCOUNTER_MAX);
signal PWM_FrequencyCounter_us : UNSIGNED(PWM_FREQUENCYCOUNTER_BITS downto 0) := (others => '0');
signal PWM_FrequencyCounter_ov : STD_LOGIC;
signal PWM_PulseCounter_us : UNSIGNED(PWM_RESOLUTION - 1 downto 0) := (others => '0');
signal PWM_PulseCounter_ov : STD_LOGIC;
begin
-- PWM frequency counter
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or PWM_FrequencyCounter_ov) = '1') then
PWM_FrequencyCounter_us <= (others => '0');
else
PWM_FrequencyCounter_us <= PWM_FrequencyCounter_us + 1;
end if;
end if;
end process;
PWM_FrequencyCounter_ov <= to_sl(PWM_FrequencyCounter_us = PWM_FREQUENCYCOUNTER_MAX);
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or PWM_PulseCounter_ov) = '1') then
PWM_PulseCounter_us <= (others => '0');
elsif (PWM_FrequencyCounter_ov = '1') then
PWM_PulseCounter_us <= PWM_PulseCounter_us + 1;
end if;
end if;
end process;
PWM_PulseCounter_ov <= to_sl(PWM_PulseCounter_us = ((2**PWM_RESOLUTION) - 2)) and PWM_FrequencyCounter_ov;
PWMOut <= to_sl(PWM_PulseCounter_us < unsigned(PWMIn));
end;
| apache-2.0 | 69408269245fb590630deb020d52d8a2 | 0.612579 | 3.619543 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_native_interface.vhd | 4 | 62,797 | -------------------------------------------------------------------------------
-- axi_emc_native_interface - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_native_interface.vhd
-- Version: v2.0
-- Description: Native AXI interface to the EMC core.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- ~~~~~~
-- SK 09/20/10
-- ^^^^^^
-- -- Designed the native interface for AXI to reduce the utilization of core.
-- -- Added "enable_rdce_cmb <= '0'; in the default signal lists in state machine.
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.all;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
----------------------------------------------------------------------------
entity axi_emc_native_interface is
-- Generics to be set by user
generic (
C_FAMILY : string := "virtex6";
---- AXI MEM Parameters
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer := 32;--8,16,32,64
C_S_AXI_MEM_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_MEM0_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM0_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM1_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM1_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM2_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM2_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM3_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM3_HIGHADDR : std_logic_vector := x"00000000";
AXI_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
AXI_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number -- only 1 is supported per addr range
1 -- User1 CE Number -- only 1 is supported per addr range
);
C_NUM_BANKS_MEM : integer
);
port(
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- -- AXI Write Address Channel Signals
S_AXI_MEM_AWID : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
S_AXI_MEM_AWADDR : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)
downto 0);
S_AXI_MEM_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_MEM_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_MEM_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_MEM_AWLOCK : in std_logic;
S_AXI_MEM_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_MEM_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_MEM_AWVALID : in std_logic;
S_AXI_MEM_AWREADY : out std_logic;
-- -- AXI Write Channel Signals
S_AXI_MEM_WDATA : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
S_AXI_MEM_WSTRB : in std_logic_vector
(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
S_AXI_MEM_WLAST : in std_logic;
S_AXI_MEM_WVALID : in std_logic;
S_AXI_MEM_WREADY : out std_logic;
-- -- AXI Write Response Channel Signals
S_AXI_MEM_BID : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
S_AXI_MEM_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MEM_BVALID : out std_logic;
S_AXI_MEM_BREADY : in std_logic;
-- -- AXI Read Address Channel Signals
S_AXI_MEM_ARID : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1) downto 0);
S_AXI_MEM_ARADDR : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
S_AXI_MEM_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_MEM_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_MEM_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_MEM_ARLOCK : in std_logic;
S_AXI_MEM_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_MEM_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_MEM_ARVALID : in std_logic;
S_AXI_MEM_ARREADY : out std_logic;
-- -- AXI Read Data Channel Signals
S_AXI_MEM_RID : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
S_AXI_MEM_RDATA : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
S_AXI_MEM_RRESP : out std_logic_vector(1 downto 0);
S_AXI_MEM_RLAST : out std_logic;
S_AXI_MEM_RVALID : out std_logic;
S_AXI_MEM_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Error : in std_logic;
-- these signals are generate little endian but reveresed in the top level file
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
Bus2IP_Data : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1)downto 0);
Bus2IP_Burst : out std_logic;
Bus2IP_BurstLength : out std_logic_vector(7 downto 0);
Bus2IP_RdReq : out std_logic;
Bus2IP_WrReq : out std_logic;
Bus2IP_CS : out std_logic_vector
(((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
Bus2IP_RdCE : out std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
Type_of_xfer : out std_logic;
Cre_reg_en : in std_logic;
synch_mem : in std_logic ;
last_addr1 : out std_logic; -- 11-12-2012
pr_idle : in std_logic;
axi_sm_ns_IDLE : out std_logic; -- 17-12-2012
axi_trans_size_reg : out std_logic_vector(1 downto 0)--1/3/2013
);
end axi_emc_native_interface;
-----------------------------------------------------------------------------
architecture imp of axi_emc_native_interface is
----------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
function get_fifo_width(NEW_LOGIC : integer;
C_S_AXI_MEM_DATA_WIDTH : integer)
return integer is
begin
if(NEW_LOGIC = 1)then
return C_S_AXI_MEM_DATA_WIDTH + 2;
else
return C_S_AXI_MEM_DATA_WIDTH + 1;
end if;
end function get_fifo_width;
constant ACTIVE_LOW_RESET : integer := 0;
constant C_RDATA_FIFO_DEPTH : integer := 256;
constant COUNTER_WIDTH : integer := clog2(C_RDATA_FIFO_DEPTH);
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_MEM_ADDR_WIDTH-1)
:= (others => '0');
constant RD_DATA_FIFO_DWIDTH : integer := get_fifo_width(NEW_LOGIC,C_S_AXI_MEM_DATA_WIDTH) ; -- (C_S_AXI_MEM_DATA_WIDTH+2);
constant ALL_1 : std_logic_vector(0 to COUNTER_WIDTH-1)
:= (others => '1');
constant ZEROES : std_logic_vector(0 to clog2(C_RDATA_FIFO_DEPTH)-1)
:= (others => '0');
-- local type declarations
type decode_bit_array_type is Array(natural range 0 to (
(AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
AXI_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to(C_S_AXI_MEM_ADDR_WIDTH-1));
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
----------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
--coverage off
return(slv_array);
--coverage on
end function slv64_2_slv_awidth;
----------------------------------------------------------------------------
-------------------------------------------------------------------------------
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(AXI_ARD_NUM_CE_ARRAY);
signal pselect_hit_i : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal cs_reg : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)
:=(others => '0');
signal rd_data_fifo_error : std_logic;
signal last_rd_data_cmb : std_logic;
signal rd_fifo_full : std_logic;
signal fifo_empty : std_logic;
signal last_fifo_data : std_logic;
signal rd_fifo_out : std_logic_vector(RD_DATA_FIFO_DWIDTH-1 downto 0);
signal rd_data_count : std_logic_vector(7 downto 0);
signal ORed_cs : std_logic;
---------------------------------------
type STATE_TYPE is
(IDLE,
RD,
RD_LAST,
WR,
WR_WAIT,
WR_RESP,
WR_LAST,
RESP);
signal emc_addr_ps: STATE_TYPE;
signal emc_addr_ns: STATE_TYPE;
-----------------------------------------
signal single_transfer_cmb : std_logic;
signal addr_sm_ps_IDLE_reg : std_logic;
signal addr_sm_ns_IDLE_cmb : std_logic;
signal wr_transaction : std_logic;
signal wr_addr_transaction : std_logic;
signal fifo_full : std_logic;
signal bvalid_cmb : std_logic;
signal enable_cs_cmb : std_logic;
signal rst_wrce_cmb : std_logic;
signal rst_rdce_cmb : std_logic;
signal rd_fifo_wr_en : std_logic;
signal rd_fifo_rd_en : std_logic;
signal type_of_xfer_reg : std_logic;
signal Type_of_xfer_cmb : std_logic;
signal addr_sm_ps_idle_cmb : std_logic;
signal last_burst_cnt : std_logic;
--IPIC request qualifier signals
signal ip2bus_errack : std_logic;
signal rd_fifo_data_in : std_logic_vector(RD_DATA_FIFO_DWIDTH-1 downto 0);-- (C_S_AXI_MEM_DATA_WIDTH downto 0);
signal rd_fifo_data_out : std_logic_vector(RD_DATA_FIFO_DWIDTH-1 downto 0);-- (C_S_AXI_MEM_DATA_WIDTH downto 0);
signal burst_length_cmb : std_logic_vector(7 downto 0);
signal addr_int_cmb : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal bus2ip_addr_i : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal derived_len_reg : std_logic_vector (3 downto 0);
signal size_cmb : std_logic_vector (1 downto 0);
signal bus2ip_data_reg : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal bus2ip_BE_reg : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1)downto 0);
signal Bus2ip_BE_cmb : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1)downto 0);
signal s_axi_mem_awready_reg : std_logic;
signal s_axi_mem_wready_reg : std_logic;
signal s_axi_mem_bid_reg : std_logic_vector (C_S_AXI_MEM_ID_WIDTH-1 downto 0);
signal s_axi_mem_bresp_reg : std_logic_vector (1 downto 0);
signal s_axi_mem_bvalid_reg : std_logic;
signal s_axi_mem_arready_reg : std_logic;
signal s_axi_mem_rid_reg : std_logic_vector (C_S_AXI_MEM_ID_WIDTH-1 downto 0);
signal s_axi_mem_rresp_reg : std_logic_vector (1 downto 0);
signal s_axi_mem_rlast_reg : std_logic;
signal s_axi_mem_rvalid_reg : std_logic;
signal s_axi_mem_rdata_i : std_logic_vector(C_S_AXI_MEM_DATA_WIDTH-1 downto 0);
signal s_axi_mem_rdata_reg : std_logic_vector(C_S_AXI_MEM_DATA_WIDTH-1 downto 0);
signal arready_cmb : std_logic;
signal awready_cmb : std_logic;
signal rw_flag_reg : std_logic;
signal wready_cmb : std_logic;
signal bus2ip_burst_reg : std_logic ;
signal rnw_reg : std_logic ;
signal rnw_cmb : std_logic ;
signal store_addr_info_cmb : std_logic ;
signal last_len_cmb : std_logic ;
signal second_last_cnt : std_logic;
signal bus2ip_wr_req_reg : std_logic;
signal bus2ip_rd_req_reg : std_logic;
signal burstlength_reg : std_logic_vector(7 downto 0);
signal bus2ip_wrreq_reg : std_logic;
signal burst_data_cnt : std_logic_vector(7 downto 0); -- is not declared.
signal derived_size_reg : std_logic_vector(1 downto 0); -- is not declared.
signal temp_single_0 : std_logic;
signal temp_single_1 : std_logic;
signal bus2ip_addr_cmb : std_logic_vector(1 to 2);
signal bus2ip_addr_int : std_logic_vector(0 to 31);
signal bus2ip_resetn : std_logic;
signal last_data_cmb : std_logic;
signal combine_ack : std_logic;
signal wready_reg : std_logic;
signal bus2ip_wr_req_cmb : std_logic;
signal bus2ip_rd_req_cmb : std_logic;
signal derived_burst_reg : std_logic_vector(1 downto 0);
signal bus2ip_rnw_i : std_logic;
signal temp_ip2bus_data: std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal updn_cnt_en : std_logic;
signal rd_fifo_empty : std_logic;
signal active_high_rst : std_logic;
signal burst_addr_cnt : std_logic_vector(7 downto 0);
signal second_last_addr : std_logic;
signal last_addr : std_logic;
signal stop_addr_incr : std_logic;
signal last_rd_reg : std_logic;
signal last_rd_data_reg : std_logic;
signal enable_rdce_cmb : std_logic;
signal enable_wrce_combo: std_logic;
signal enable_wrce_cmb : std_logic;
signal enable_rdce_combo: std_logic;
signal addr_sm_ps_WR_cmb: std_logic;
signal addr_sm_ps_WR_WAIT_cmb: std_logic;
signal rst_cs_cmb : std_logic;
signal single_transfer_reg : std_logic;
signal last_data_acked : std_logic;
signal cnt : std_logic_vector((COUNTER_WIDTH-1) downto 0);
signal RdFIFO_Space_two_int : std_logic;
signal no_space_in_fifo : std_logic;
signal last_write : std_logic;
-----------------------------------
begin
------
--OLD_LOGIC_GEN: if NEW_LOGIC = 0 generate
-----
--begin
-----
ACTIVE_HIGH_RST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
active_high_rst <= not(S_AXI_ARESETN);
end if;
end process ACTIVE_HIGH_RST_P;
-----------------------------------
-- AXI Side interface
---------------------
S_AXI_MEM_AWREADY <= awready_cmb;
S_AXI_MEM_WREADY <= wready_cmb;
S_AXI_MEM_BID <= s_axi_mem_bid_reg;
S_AXI_MEM_BRESP <= s_axi_mem_bresp_reg;
S_AXI_MEM_BVALID <= s_axi_mem_bvalid_reg;
S_AXI_MEM_ARREADY <= arready_cmb;
S_AXI_MEM_RID <= s_axi_mem_rid_reg;
S_AXI_MEM_RRESP <= s_axi_mem_rresp_reg;
S_AXI_MEM_RLAST <= s_axi_mem_rlast_reg;
S_AXI_MEM_RVALID <= s_axi_mem_rvalid_reg;
S_AXI_MEM_RDATA <= s_axi_mem_rdata_reg;
last_write <= (S_AXI_MEM_WLAST and S_AXI_MEM_WVALID and wready_cmb);
-----------------------
-- REG_BID_P,REG_RID_P: Below process makes the RID and BID '0' at POR and
-- : generate proper values based upon read/write
-- transaction
-----------------------
S_AXI_MEM_RID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
s_axi_mem_rid_reg <= (others=> '0');
elsif(arready_cmb='1')then
s_axi_mem_rid_reg <= S_AXI_MEM_ARID;
end if;
end if;
end process S_AXI_MEM_RID_P;
----------------------
S_AXI_MEM_BID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
s_axi_mem_bid_reg <= (others=> '0');
elsif(awready_cmb='1')then
s_axi_mem_bid_reg <= S_AXI_MEM_AWID;
end if;
end if;
end process S_AXI_MEM_BID_P;
-----------------------
AXI_MEM_BRESP_P: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK='1')then
if (addr_sm_ps_IDLE_cmb='1')then
s_axi_mem_bresp_reg <= (others => '0');
elsif(ip2bus_wrack = '1') and (IP2Bus_Error='1') then
s_axi_mem_bresp_reg <= "10";
end if;
end if;
end process AXI_MEM_BRESP_P;
-----------------------
AXI_MEM_BVALID_P: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK='1')then
if (addr_sm_ps_IDLE_cmb='1')then
s_axi_mem_bvalid_reg <= '0';
--elsif(last_write_reg = '1') and (last_addr = '1') then
elsif(last_addr = '1') and (IP2Bus_WrAck='1') then
s_axi_mem_bvalid_reg <= '1';
elsif(S_AXI_MEM_BREADY='1') then
s_axi_mem_bvalid_reg <= '0';
end if;
end if;
end process AXI_MEM_BVALID_P;
-----------------------
s_axi_mem_rresp_reg <= (rd_data_fifo_error & '0')
when (rnw_reg='1')
else
(others => '0');
-----------------------
s_axi_mem_rlast_reg <= last_rd_data_cmb and
last_data_acked;
-----------------------
s_axi_mem_rvalid_reg <= not fifo_empty;
-----------------------
s_axi_mem_rdata_reg <= s_axi_mem_rdata_i;
-----------------------
arready_cmb <= -- below logic is useful in idle state only
S_AXI_MEM_ARVALID and
addr_sm_ps_IDLE_cmb and
(not(rw_flag_reg) or
not(S_AXI_MEM_AWVALID)
) and S_AXI_ARESETN
and pr_idle;
awready_cmb <= -- below logic is useful in idle state only
(wr_transaction) and
addr_sm_ps_IDLE_cmb and
(rw_flag_reg or
(not S_AXI_MEM_ARVALID)
) and
S_AXI_ARESETN
and pr_idle;
-----------------------------------------------------------------------------
----------------------
-- IPIC Side interface
----------------------
Type_of_xfer <= type_of_xfer_reg;
bus2ip_Addr <= bus2ip_addr_int;
Bus2ip_BE <= bus2ip_BE_reg;
Bus2IP_Data <= bus2ip_data_reg;
Bus2IP_Burst <= bus2ip_burst_reg;
Bus2ip_RNW <= rnw_reg;
Bus2IP_RdReq <= bus2ip_rd_req_reg;
Bus2IP_WrReq <= bus2ip_wr_req_reg;
Bus2IP_BurstLength <= burstlength_reg;
--------------
BUS2IP_DATA_P: process (S_AXI_ACLK) is
--------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if ((S_AXI_ARESETN='0')) then
bus2ip_data_reg <= (others => '0');
elsif (((S_AXI_MEM_WVALID='1') and (wready_cmb='1'))
) then
bus2ip_data_reg <= S_AXI_MEM_WDATA;
end if;
end if;
end process BUS2IP_DATA_P;
-------------------------
------------------------
-- BUS2IP_BE_P:Register Bus2IP_BE for write strobe during write mode else '1'.
------------------------
BUS2IP_BE_P: process (S_AXI_ACLK) is
------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if ((S_AXI_ARESETN='0')) then
bus2ip_BE_reg <= (others => '0');
elsif ((rnw_cmb='0') and (wready_cmb='1') and (S_AXI_MEM_WVALID ='1')) then
bus2ip_BE_reg <= S_AXI_MEM_WSTRB;
elsif(store_addr_info_cmb = '1')or (rnw_cmb='1') then
bus2ip_BE_reg <= Bus2ip_BE_cmb;
end if;
end if;
end process BUS2IP_BE_P;
------------------------
-------------- bus2ip_burst should be active till last but one transaction data ack
BUS2IP_BURST_P: process (S_AXI_ACLK) is
--------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0')then
bus2ip_burst_reg <= '0';
elsif(store_addr_info_cmb='1') then
bus2ip_burst_reg <= last_len_cmb;
elsif(last_data_cmb='1') then
bus2ip_burst_reg <= '0';
end if;
end if;
end process BUS2IP_BURST_P;
---------------------------
------------------
BUS2IP_BURST_REG_P1: process (S_AXI_ACLK) is
------------------
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
burstlength_reg <= (others => '0');
elsif(store_addr_info_cmb='1')then
burstlength_reg <= burst_length_cmb;
end if;
end if;
end process BUS2IP_BURST_REG_P1;
--------------------------------------
------------------
AXI_TRANS_SIZE_REG_P1: process (S_AXI_ACLK) is
------------------
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
axi_trans_size_reg <= (others => '0');
elsif(store_addr_info_cmb='1' and rnw_cmb = '1')then
axi_trans_size_reg <= S_AXI_MEM_ARSIZE(1 downto 0);
end if;
end if;
end process AXI_TRANS_SIZE_REG_P1;
--------------------------------------
----------------------
-- internal signals
----------------------
second_last_cnt <= not(or_reduce(burst_data_cnt(7 downto 1)))
and burst_data_cnt(0);
addr_sm_ns_IDLE_cmb <= '1' when (emc_addr_ns=IDLE) else '0';
addr_sm_ps_IDLE_cmb <= '1' when (emc_addr_ps=IDLE) else '0';
axi_sm_ns_IDLE <= '1' when (emc_addr_ns=IDLE) else '0';-- 17-dec-2012
addr_sm_ps_WR_cmb <= '1' when (emc_addr_ps=WR) else '0';
addr_sm_ps_WR_WAIT_cmb <= '1' when (emc_addr_ps=WR_WAIT) else '0';
wr_transaction <= S_AXI_MEM_AWVALID and (S_AXI_MEM_WVALID);
wr_addr_transaction <= S_AXI_MEM_AWVALID and (not S_AXI_MEM_WVALID);
---------------------------
addr_int_cmb <= S_AXI_MEM_ARADDR when(rnw_cmb = '1')
else
S_AXI_MEM_AWADDR;
-------------------
size_cmb <= S_AXI_MEM_ARSIZE(1 downto 0) when (rnw_cmb = '1') else
S_AXI_MEM_AWSIZE(1 downto 0);
-------------------
burst_length_cmb <= S_AXI_MEM_ARLEN when (rnw_cmb = '1')
else
S_AXI_MEM_AWLEN;
-------------------
single_transfer_cmb <= not(or_reduce(burst_length_cmb));
-------------------
last_len_cmb <= or_reduce(burst_length_cmb);
-------------------
Type_of_xfer_cmb <= or_reduce(S_AXI_MEM_ARBURST) when (rnw_cmb = '1')
else
or_reduce(S_AXI_MEM_AWBURST);
-------------------
Bus2IP_Resetn <= S_AXI_ARESETN;
-------------------
combine_ack <= --IP2Bus_WrAck or IP2Bus_RdAck;
IP2Bus_RdAck;
-----------------
BURST_DATA_CNT_P: process (S_AXI_ACLK) is
-----------------
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
burst_data_cnt <= (others => '0');
elsif(store_addr_info_cmb='1') then
burst_data_cnt <= burst_length_cmb;
elsif((combine_ack='1') and (last_data_cmb='0')
)then
burst_data_cnt <= burst_data_cnt - '1';
end if;
end if;
end process BURST_DATA_CNT_P;
-----------------------------
last_data_cmb <= not(or_reduce(burst_data_cnt));
LAST_DATA_ACKED_P: process (S_AXI_ACLK) is
-----------------
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if(addr_sm_ps_IDLE_cmb='1') then
last_data_acked <= '0';
elsif(synch_mem = '0' and last_rd_data_cmb= '1' and IP2Bus_RdAck = '1') then
last_data_acked <= '1';
elsif (last_data_cmb= '1' and IP2Bus_RdAck = '1') then
last_data_acked <= '1';
end if;
end if;
end process LAST_DATA_ACKED_P;
-----------------
BURST_ADDR_CNT_P: process(S_AXI_ACLK) is
-----------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (store_addr_info_cmb='1') then
burst_addr_cnt <= burst_length_cmb;
elsif ((IP2Bus_AddrAck='1')and
((last_addr='0'))
) then
burst_addr_cnt <= burst_addr_cnt - '1';
end if;
end if;
end process BURST_ADDR_CNT_P;
-----------------------------
second_last_addr <= not(or_reduce(burst_addr_cnt(7 downto 1))) and
burst_addr_cnt(0);
last_addr <= not(or_reduce(burst_addr_cnt));
last_addr1 <= last_addr;
stop_addr_incr <= last_addr;
--------------------------------------------------------------------------
--Generate burst length for WRAP xfer when C_S_AXI_MEM_DATA_WIDTH = 32.
--------------------------------------------------------------------------
LEN_GEN_32 : if ( C_S_AXI_MEM_DATA_WIDTH = 32 ) generate
------------
begin
-----
-- ----------------------------------------------------------------------
-- Process DERIVED_LEN_P to find the burst length translate from byte,
-- Half word and word transfer types.
-- Logic - convert the number of data beat transfers in the equivalent words
-- ex - Wrap transfer, byte size of length = Words
-- AXI Data 10 00 2 0001 = 0000
-- AXI Data 10 00 4 0011 = 0001
-- AXI Data 10 00 8 0111 = 0010
-- AXI Data 10 00 16 1111 = 0100
-- So pick the 3:2 bits from AXI Size
-- ----------------------------------------------------------------------
DERIVED_LEN_P: process (S_AXI_ACLK) is
--------------
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (store_addr_info_cmb='1') then
case size_cmb is
when "00" => derived_len_reg <= ("00" & burst_length_cmb(3 downto 2));
when "01" => derived_len_reg <= ('0' & burst_length_cmb(3 downto 1));
-- coverage off
when others => derived_len_reg <= burst_length_cmb(3 downto 0);
-- coverage on
end case;
end if;
end if;
end process DERIVED_LEN_P;
--------------------------
end generate LEN_GEN_32;
-- --------------------------------------------------------------------------
-- Generate burst length for WRAP xfer when C_S_AXI_DATA_WIDTH = 64.
-- --------------------------------------------------------------------------
LEN_GEN_64 : if ( C_S_AXI_MEM_DATA_WIDTH = 64 ) generate
------------
begin
-- ----------------------------------------------------------------------
-- Process DERIVED_LEN_P to find the burst length translate from byte,
-- Half word and word transfer types.
-- ----------------------------------------------------------------------
DERIVED_LEN_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (store_addr_info_cmb='1') then
case size_cmb is
when "00" =>derived_len_reg <=("000" & burst_length_cmb(3));
when "01" =>derived_len_reg <=("00" & burst_length_cmb(3 downto 2));
when "10" =>derived_len_reg <=('0' & burst_length_cmb(3 downto 1));
-- coverage off
when others => derived_len_reg <= burst_length_cmb(3 downto 0);
-- coverage on
end case;
end if;
end if;
end process DERIVED_LEN_P;
--------------------------
end generate LEN_GEN_64;
------------------------
---------------------------
REG_P: process (S_AXI_ACLK) is
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
emc_addr_ps <= IDLE;
addr_sm_ps_IDLE_reg <= '1';
rnw_reg <= '0';
bus2ip_wr_req_reg <= '0';
bus2ip_rd_req_reg <= '0';
last_rd_data_reg <= '0';
else
emc_addr_ps <= emc_addr_ns;
addr_sm_ps_IDLE_reg <= addr_sm_ns_IDLE_cmb;
rnw_reg <= rnw_cmb;
bus2ip_wr_req_reg <= bus2ip_wr_req_cmb;
bus2ip_rd_req_reg <= bus2ip_rd_req_cmb;
last_rd_data_reg <= last_rd_data_cmb;
end if;
end if;
end process REG_P;
-------------------------------------------------------
REG_CONDITION_P: process (S_AXI_ACLK) is
----------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
type_of_xfer_reg <= '0'; -- default
single_transfer_reg <= '0';
elsif(store_addr_info_cmb='1') then
single_transfer_reg <= single_transfer_cmb;
type_of_xfer_reg <= Type_of_xfer_cmb;
derived_size_reg <= size_cmb;
if(rnw_cmb = '1') then
derived_burst_reg <= S_AXI_MEM_ARBURST;
else
derived_burst_reg <= S_AXI_MEM_AWBURST;
end if;
end if;
end if;
end process REG_CONDITION_P;
-------------------------------------------------------
--------------------------------------------------
-- RW_FLAG_P: Round robin logic for read and write
--------------------------------------------------
RW_FLAG_P: process(S_AXI_ACLK)is
----------
begin
if(S_AXI_ACLK'event and S_AXI_ACLK='1')then
if (S_AXI_ARESETN='0')then
rw_flag_reg <= '0';
elsif((addr_sm_ps_IDLE_reg='1' and pr_idle = '1'))then
rw_flag_reg <= (rw_flag_reg and not(S_AXI_MEM_AWVALID))
or
((not rw_flag_reg)and S_AXI_MEM_ARVALID);
end if;
end if;
end process RW_FLAG_P;
--------------------------------------------------
process (
-- axi signals
S_AXI_MEM_ARVALID,
S_AXI_MEM_AWVALID,
S_AXI_MEM_WVALID,
S_AXI_MEM_WLAST,
S_AXI_MEM_RREADY,
S_AXI_MEM_BREADY,
-- internal signals
emc_addr_ps,
single_transfer_cmb,
wr_transaction,
last_addr,
last_rd_data_cmb,
second_last_addr,
last_data_cmb,
IP2Bus_AddrAck,
IP2Bus_RdAck,
IP2Bus_WrAck,
rd_fifo_full,
fifo_empty,
single_transfer_cmb,
-- registered signals
single_transfer_reg,
rw_flag_reg,
rnw_reg,
bus2ip_wr_req_reg,
bus2ip_rd_req_reg,
last_data_acked,
s_axi_mem_rlast_reg,
addr_sm_ps_IDLE_cmb,
s_axi_mem_bvalid_reg,
pr_idle, -- 11-12-2012
S_AXI_MEM_AWBURST,
S_AXI_MEM_ARBURST
)is
begin -- default states
rnw_cmb <= rnw_reg;
bus2ip_wr_req_cmb <= bus2ip_wr_req_reg;
bus2ip_rd_req_cmb <= bus2ip_rd_req_reg;
enable_cs_cmb <= '0';
rst_rdce_cmb <= '0';
rst_wrce_cmb <= '0';
rst_cs_cmb <= '0';
enable_wrce_cmb <= '0';
enable_rdce_cmb <= '0';
store_addr_info_cmb <= '0';
wready_cmb <= '0';
case emc_addr_ps is
-------------------------------
when IDLE => if ( (S_AXI_MEM_ARVALID='1') and
((rw_flag_reg='0' ) or
(S_AXI_MEM_AWVALID='0')
)
) and (pr_idle = '1') and (or_reduce(S_AXI_MEM_ARBURST) = '1')then
enable_cs_cmb <= '1';
store_addr_info_cmb <= '1';
if(single_transfer_cmb='1')then
enable_rdce_cmb <= '1';
emc_addr_ns <= RD_LAST;
else
emc_addr_ns <= RD;
end if;
elsif( (wr_transaction = '1') and
((rw_flag_reg='1' ) or
(S_AXI_MEM_ARVALID='0')
)
) and (pr_idle = '1') and (or_reduce(S_AXI_MEM_AWBURST) = '1') then
enable_cs_cmb <= '1';
store_addr_info_cmb <= '1';
if(single_transfer_cmb='1')then
emc_addr_ns <= WR_LAST;
else
emc_addr_ns <= WR;
end if;
else
emc_addr_ns <= IDLE;
end if;
wready_cmb <= pr_idle and -- 11-12-2012
(wr_transaction) and
addr_sm_ps_IDLE_cmb and
(rw_flag_reg or
(not S_AXI_MEM_ARVALID)
);
-- priority is given for read over write
rnw_cmb <= S_AXI_MEM_ARVALID and
( not(rw_flag_reg) or
not(S_AXI_MEM_AWVALID)
);
bus2ip_rd_req_cmb <= S_AXI_MEM_ARVALID and
(not(rw_flag_reg)
or
not(S_AXI_MEM_AWVALID)
);
bus2ip_wr_req_cmb <= wr_transaction and
(rw_flag_reg or (not S_AXI_MEM_ARVALID) );
-------------------------------
when RD => if(s_axi_mem_rlast_reg='1' and S_AXI_MEM_RREADY='1')then
rst_cs_cmb <= '1';
rst_rdce_cmb <= '1';
rnw_cmb <= '0';
emc_addr_ns <= IDLE;
else
emc_addr_ns <= RD;
end if;
rst_cs_cmb <= (last_data_cmb and IP2Bus_RdAck);
rst_rdce_cmb <= rd_fifo_full or
(last_data_cmb and IP2Bus_RdAck);--1/17/2013
--(last_rd_data_cmb and IP2Bus_RdAck);
enable_rdce_cmb <= fifo_empty and (not last_data_cmb);
bus2ip_rd_req_cmb <= not(last_addr and IP2Bus_AddrAck)
and
bus2ip_rd_req_reg;
-------------------------------
when RD_LAST => --if(IP2Bus_RdAck='1')then
if(s_axi_mem_rlast_reg='1' and S_AXI_MEM_RREADY='1')then
rnw_cmb <= '0';
rst_cs_cmb <= '1';
emc_addr_ns <= IDLE;
else
emc_addr_ns <= RD_LAST;
end if;
--bus2ip_rd_req_cmb <= not IP2Bus_RdAck;
rst_cs_cmb <= IP2Bus_RdAck;
rst_rdce_cmb <= IP2Bus_RdAck;--rd_fifo_full
--or
--((last_data_cmb or
-- single_transfer_reg)
-- and
-- IP2Bus_RdAck
-- );
--enable_rdce_cmb <= not (fifo_empty or
-- (last_data_cmb and
-- IP2Bus_RdAck
-- )
-- );
-------------------------------
when WR => if ((IP2Bus_WrAck='1')) then
if (S_AXI_MEM_WVALID='0') then
emc_addr_ns <= WR_WAIT;
elsif (second_last_addr='1') then
emc_addr_ns <= WR_LAST;
else
emc_addr_ns <= WR;
end if;
else
emc_addr_ns <= WR;
end if;
bus2ip_wr_req_cmb <= '1';
wready_cmb <= IP2Bus_WrAck;
rst_wrce_cmb <= IP2Bus_WrAck and
(not S_AXI_MEM_WVALID);
-------------------------------
when WR_WAIT => if (S_AXI_MEM_WVALID='0') then
rst_wrce_cmb <= '1';
emc_addr_ns <= WR_WAIT;
elsif(last_addr='1') then
emc_addr_ns <= WR_LAST;
else
emc_addr_ns <= WR;
end if;
bus2ip_wr_req_cmb <= '1';
wready_cmb <= '1';
enable_wrce_cmb <= S_AXI_MEM_WVALID;
-------------------------------
when WR_LAST => if (last_addr='1') then
if ((IP2Bus_AddrAck='1'))then
wready_cmb <= '0';
emc_addr_ns <= RESP;
else
emc_addr_ns <= WR_LAST;
end if;
else
emc_addr_ns <= WR_LAST;
end if;
bus2ip_wr_req_cmb <= not(IP2Bus_WrAck);
rst_cs_cmb <= IP2Bus_WrAck;
rst_wrce_cmb <= IP2Bus_WrAck;
enable_wrce_cmb <= S_AXI_MEM_WVALID;
-------------------------------
when RESP => rst_cs_cmb <= '1';
rst_wrce_cmb <= '1';
if((S_AXI_MEM_BREADY='1') and (s_axi_mem_bvalid_reg='1')) then
emc_addr_ns <= IDLE;
--rst_wrce_cmb <= '1';
--rst_cs_cmb <= '1';
else
emc_addr_ns <= RESP;
end if;
-------------------------------
-- coverage off
when others => emc_addr_ns <= IDLE;
-- coverage on
-------------------------------
end case;
end process;
-----------------------
------------------------------------------------------------------------------
AXI_EMC_ADDR_GEN_INSTANCE_I:entity axi_emc_v3_0.axi_emc_addr_gen
generic map
(
C_S_AXI_MEM_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH,
C_S_AXI_MEM_DATA_WIDTH => C_S_AXI_MEM_DATA_WIDTH
)
port map
(
Bus2IP_Clk => S_AXI_ACLK , -- in std_logic
Bus2IP_Resetn => Bus2IP_Resetn , -- in std_logic
-- combo I/P signals
stop_addr_incr => stop_addr_incr,
Store_addr_info_cmb => Store_addr_info_cmb, -- in std_logic;
Addr_int_cmb => Addr_int_cmb , -- in std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack => IP2Bus_AddrAck , -- in std_logic;
Fifo_full_1 => rst_rdce_cmb, --Fifo_full , -- in std_logic;
Rst_Rd_CE => rst_rdce_cmb , -- : in std_logic;
-- registered signals
derived_len_reg => derived_len_reg , -- in std_logic_vector(3 downto 0);
Derived_burst_reg => Derived_burst_reg , -- in std_logic_vector(1 downto 0);
Derived_size_reg => Derived_size_reg , -- in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr => bus2ip_addr_int , -- out std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0)
Cre_reg_en => Cre_reg_en -- enable the lower address bits to pass - support un-aligned address
);
------------------------------------------------------------------------------
enable_rdce_combo <= enable_rdce_cmb;
enable_wrce_combo <= enable_wrce_cmb;
AXI_EMC_ADDRESS_DECODE_INSTANCE_I:entity axi_emc_v3_0.axi_emc_address_decode
generic map(
C_S_AXI_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH ,
C_ARD_ADDR_RANGE_ARRAY => AXI_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => AXI_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY ,
C_ADDR_DECODE_BITS => C_S_AXI_MEM_ADDR_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK , -- : in std_logic;
Bus2IP_Resetn => Bus2IP_Resetn , -- : in std_logic;
Enable_CS => enable_cs_cmb , -- : in std_logic;
Enable_RdCE => enable_rdce_combo , --Store_addr_info_cmb , -- : in std_logic;
Enable_WrCE => enable_wrce_combo , --Store_addr_info_cmb , -- : in std_logic;
Rst_CS => rst_cs_cmb , -- : in std_logic;
Rst_Wr_CE => rst_wrce_cmb , -- : in std_logic;
Rst_Rd_CE => rst_rdce_cmb , -- : in std_logic;
Addr_SM_PS_IDLE => addr_sm_ps_IDLE_cmb , -- : in std_logic;
Addr_int => Addr_int_cmb , -- : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
RNW => rnw_cmb , -- : in std_logic;
RdFIFO_Space_two_int => RdFIFO_Space_two_int,
Bus2IP_CS => bus2ip_cs , -- out std_logic_vector((((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)downto 0);
Bus2IP_RdCE => bus2ip_rdce , -- out std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
Bus2IP_WrCE => bus2ip_wrce , -- out std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
ORed_cs => ORed_cs
);
-----------------------------------------------------------------------------
rd_fifo_data_in <= (IP2Bus_Data & (IP2Bus_Error and IP2Bus_RdAck)); -- & (last_data_cmb and IP2Bus_RdAck);
rd_fifo_wr_en <= (IP2Bus_RdAck and ORed_cs);
rd_fifo_rd_en <= (not fifo_empty) and S_AXI_MEM_RREADY;
rd_fifo_empty <= fifo_empty or (s_axi_mem_rvalid_reg and
S_AXI_MEM_RREADY and
last_fifo_data);
------------------------
-- RDATA_FIFO_I : read buffer
-----------------
RDATA_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_rbu_f
generic map (
C_DWIDTH => RD_DATA_FIFO_DWIDTH,
C_DEPTH => C_RDATA_FIFO_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => S_AXI_ACLK, -- in
--------------
Reset => active_high_rst, -- in
--------------
FIFO_Write => rd_fifo_wr_en, --IP2Bus_RdAck, -- rd_fifo_wr_en, -- in
Data_In => rd_fifo_data_in, -- in std_logic_vector
FIFO_Read => rd_fifo_rd_en, -- in
Data_Out => rd_fifo_out, -- out std_logic_vector
FIFO_Full => rd_fifo_full, -- out
FIFO_Empty => fifo_empty, -- out
Addr => open, -- out std_logic_vector
Num_To_Reread => ZEROES, -- in std_logic_vector
Underflow => open, -- out
Overflow => open -- out
);
rd_data_fifo_error <= rd_fifo_out(0);
s_axi_mem_rdata_i <= rd_fifo_out(RD_DATA_FIFO_DWIDTH-1 downto 1);
---------------
updn_cnt_en <= rd_fifo_rd_en xor rd_fifo_wr_en;
------------------------
-- UPDN_COUNTER_I : The below counter used to keep track of FIFO rd/wr
-- The counter is loaded with the max. value at reset
-------------------
UPDN_COUNTER_I : entity axi_emc_v3_0.counter_f
generic map(
C_NUM_BITS => COUNTER_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI_ACLK, -- in
Rst => '0', -- in
Load_In => ALL_1, -- in
Count_Enable => updn_cnt_en, -- in
----------------
Count_Load => active_high_rst, -- in
----------------
Count_Down => rd_fifo_wr_en, -- in
Count_Out => cnt, -- out std_logic_vector
Carry_Out => open -- out
);
------------------------
no_space_in_fifo <= (or_reduce(cnt(COUNTER_WIDTH-1 downto 3)));
RDDATA_CNT_P1: process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
RdFIFO_Space_two_int <= '1';
elsif (cnt(COUNTER_WIDTH-1)='0' and
cnt(COUNTER_WIDTH-2)='1' and
cnt(COUNTER_WIDTH-3)='0' and
cnt(COUNTER_WIDTH-4)='0' and
cnt(COUNTER_WIDTH-5)='0'
)then
RdFIFO_Space_two_int <= '0';
elsif(cnt(COUNTER_WIDTH-1)='1' and
cnt(COUNTER_WIDTH-2)='0' and
cnt(COUNTER_WIDTH-3)='0' and
cnt(COUNTER_WIDTH-4)='0' and
cnt(COUNTER_WIDTH-5)='0'
)then
RdFIFO_Space_two_int <= '1';
end if;
end if;
end process RDDATA_CNT_P1;
---------------
------------------------
-- RDDATA_CNT_P : read data counter from AXI side
------------------------
RDDATA_CNT_P: process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
rd_data_count <= (others => '0');
elsif (store_addr_info_cmb='1') then
rd_data_count <= S_AXI_MEM_ARLEN;
elsif ((s_axi_mem_rvalid_reg='1') and (S_AXI_MEM_RREADY='1')) then
rd_data_count <= (rd_data_count - '1');
end if;
end if;
end process RDDATA_CNT_P;
last_rd_data_cmb <= not(or_reduce(rd_data_count));
-----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ALIGN_BYTE_ENABLE_DWTH_32_GEN: Generate the below logic for 32 bit dwidth
----------------------------------
ALIGN_BYTE_ENABLE_DWTH_32_GEN: if (C_S_AXI_MEM_DATA_WIDTH = 32) generate
------------------------------
----------------------------------------------------------------------------
-- be_generate_32 : This function returns byte_enables for the 32 bit dwidth
----------------------------------------------------------------------------
function be_generate_32 (addr_bits : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0))
return std_logic_vector is
variable int_bus2ip_be : std_logic_vector(3 downto 0):= (others => '0');
-----
begin
-----
int_bus2ip_be(0) := size(1) or
(
((not addr_bits(1)) and (not size(1)))
and
(not addr_bits(0) or size(0))
);
int_bus2ip_be(1) := size(1) or
(
((not addr_bits(1)) and (not size(1)))
and
(addr_bits(0) or size(0))
);
int_bus2ip_be(2) := size(1) or
(
(addr_bits(1) and (not size(1)))
and
((not addr_bits(0)) or size(0))
);
int_bus2ip_be(3) := size(1) or
(
(addr_bits(1) and (not size(1)))
and
(addr_bits(0) or size(0))
);
-- coverage off
return int_bus2ip_be;
-- coverage on
end function be_generate_32;
-----------------------------------------------------------------------------
------------------------------
begin
-------------------------
-- RD_ADDR_ALIGN_BE_32_P: the below logic generates the byte enables for
-- 32 bit data width
-------------------------
RD_ADDR_ALIGN_BE_32_P: process(store_addr_info_cmb,
size_cmb,
S_AXI_MEM_ARADDR(1 downto 0),
IP2Bus_AddrAck,
derived_size_reg,
bus2ip_BE_reg
)is
begin
if(store_addr_info_cmb = '1')then
Bus2ip_BE_cmb <= be_generate_32(S_AXI_MEM_ARADDR(1 downto 0),size_cmb);
elsif (IP2Bus_AddrAck = '1')then
case derived_size_reg is
when "00" => -- byte
Bus2ip_BE_cmb <= bus2ip_BE_reg(2 downto 0) & bus2ip_BE_reg(3);
when "01" => -- half word
Bus2ip_BE_cmb <= bus2ip_BE_reg(1 downto 0) &
bus2ip_BE_reg(3 downto 2);
-- coverage off
when others => Bus2ip_BE_cmb <= "1111";
-- coverage on
end case;
else
Bus2ip_BE_cmb <= bus2ip_BE_reg;
end if;
end process RD_ADDR_ALIGN_BE_32_P;
----------------------------------
end generate ALIGN_BYTE_ENABLE_DWTH_32_GEN;
------------------------------- ------------
------------------------------------------------------------------------------
-- ALIGN_BYTE_ENABLE_DWTH_64_GEN: Generate the below logic for 32 bit dwidth
----------------------------------
ALIGN_BYTE_ENABLE_DWTH_64_GEN: if (C_S_AXI_MEM_DATA_WIDTH = 64) generate
-------------------------
-- function declaration
---------------------------------------------------------------------------
-- be_generate_64 : To generate the Byte Enable w.r.t size and address
---------------------------------------------------------------------------
function be_generate_64 (addr_bits : std_logic_vector(2 downto 0);
size : std_logic_vector(1 downto 0))
return std_logic_vector is
variable int_bus2ip_be : std_logic_vector(7 downto 0):= (others => '0');
-----
begin
-----
int_bus2ip_be(0) :=(size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
(not addr_bits(1)) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(1) :=(size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
(not addr_bits(1)) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
int_bus2ip_be(2) := (size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
addr_bits(1) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(3) := (size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
addr_bits(1) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
int_bus2ip_be(4) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
(not addr_bits(1)) and
addr_bits(2) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(5) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
(not addr_bits(1)) and
addr_bits(2) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
int_bus2ip_be(6) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
addr_bits(1) and
addr_bits(2) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(7) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
addr_bits(1) and
addr_bits(2) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
-- coverage off
return int_bus2ip_be;
-- coverage on
end function be_generate_64;
-----------------------------------------------------------------------------
-----
begin
-----
-- RD_ADDR_ALIGN_BE_64_P: The below logic generates the byte enables for
-- 64 bit data width
-------------------------
RD_ADDR_ALIGN_BE_64_P: process(store_addr_info_cmb,
size_cmb,
S_AXI_MEM_ARADDR(2 downto 0),
IP2Bus_AddrAck,
derived_size_reg,
Bus2ip_BE_reg
)is
begin
if(store_addr_info_cmb = '1')then
Bus2ip_BE_cmb <= be_generate_64(S_AXI_MEM_ARADDR(2 downto 0),size_cmb);
elsif (IP2Bus_AddrAck = '1')then
case derived_size_reg is
when "00" => -- byte
Bus2ip_BE_cmb <= bus2ip_BE_reg(6 downto 0) & bus2ip_BE_reg(7);
when "01" => -- half word
Bus2ip_BE_cmb <= bus2ip_BE_reg(5 downto 0) &
bus2ip_BE_reg(7 downto 6);
when "10" => -- half word
Bus2ip_BE_cmb <= bus2ip_BE_reg(3 downto 0) &
bus2ip_BE_reg(7 downto 4);
-- coverage off
when others => Bus2ip_BE_cmb <= (others => '1');
-- coverage on
end case;
else
Bus2ip_BE_cmb <= bus2ip_BE_reg;
end if;
end process RD_ADDR_ALIGN_BE_64_P;
-------------------------------
end generate ALIGN_BYTE_ENABLE_DWTH_64_GEN;
------------------------
--end generate OLD_LOGIC_GEN;
end architecture imp;
| gpl-3.0 | 062463e9aeae03d8832ea9e169a25b89 | 0.447171 | 3.796445 | false | false | false | false |
hoangt/PoC | src/io/ddrio/ddrio_inout_altera.vhdl | 2 | 2,484 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Input/Output Registers for Xilinx FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.inout for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library Altera_mf;
use Altera_mf.Altera_MF_Components.all;
entity ddrio_inout_altera is
generic (
BITS : POSITIVE
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_inout_altera is
begin
ioff : altddio_in
generic map (
WIDTH => BITS,
INTENDED_DEVICE_FAMILY => "STRATIXII" -- TODO: built device string from PoC.config information
)
port map (
outclock => Clock,
outclocken => ClockEnable,
oe => OutputEnable,
datain_h => DataOut_high,
datain_l => DataOut_low,
inclock => Clock,
inclocken => ClockEnable,
dataout_h => DataIn_high,
dataout_l => DataIn_low,
padio => Pad
);
end architecture;
| apache-2.0 | 727ee4328ad71158d05f9288ce00f495 | 0.599034 | 3.615721 | false | false | false | false |
hoangt/PoC | src/io/ddrio/ddrio_out_xilinx.vhdl | 2 | 2,866 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Output Registers for Xilinx FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.out for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library UniSim;
use UniSim.vComponents.all;
entity ddrio_out_xilinx is
generic (
NO_OUTPUT_ENABLE : BOOLEAN := false;
BITS : POSITIVE;
INIT_VALUE : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_out_xilinx is
begin
gen : for i in 0 to WIDTH - 1 generate
signal o : std_logic;
begin
off : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => INIT_VALUE(i),
SRTYPE => "SYNC"
)
port map (
Q => o,
C => Clock,
CE => ClockEnable,
D1 => DataOut_high(i),
D2 => DataOut_low(i),
R => '0',
S => '0'
);
genOE : if not NO_OE generate
signal oe_n : std_logic;
signal t : std_logic;
begin
oe_n <= not OutputEnable;
tff : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '1',
SRTYPE => "SYNC"
)
port map (
Q => t,
C => Clock,
CE => ClockEnable,
D1 => oe_n,
D2 => oe_n,
R => '0',
S => '0'
);
Pad(i) <= o when t = '0' else 'Z'; -- 't' is low-active!
end generate genOE;
genNoOE : if NO_OE generate
Pad(i) <= o;
end generate genNoOE;
end generate;
end architecture;
| apache-2.0 | bb5fb9e859f763f94346e93ad739f2dc | 0.555827 | 3.267959 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | d80d66ef34d1b8ae1110a8f5437f46aa | 0.942365 | 1.869991 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/bufg/bufgmux_tech.vhd | 2 | 1,700 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual clock multiplexer with buffered output.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bufgmux_tech is
generic
(
tech : integer := 0;
tmode_always_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of bufgmux_tech is
component bufgmux_fpga is
generic (
tmode_always_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end component;
component bufgmux_micron180 is
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
inf : if tech = inferred generate
O <= I1 when S = '0' else I2;
end generate;
xlnx : if tech = virtex6 or tech = kintex7 or tech = artix7 generate
mux_buf : bufgmux_fpga generic map (
tmode_always_ena => tmode_always_ena
) port map (
O => O,
I1 => I1,
I2 => I2,
S => S
);
end generate;
mic0 : if tech = micron180 generate
mux_buf : bufgmux_micron180
port map (
O => O,
I1 => I1,
I2 => I2,
S => S
);
end generate;
end;
| bsd-2-clause | 97d36123491851d461d2ba5afe0f7412 | 0.487647 | 3.803132 | false | false | false | false |
hoangt/PoC | src/arith/xilinx/arith_addw_xilinx.vhdl | 2 | 13,961 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw_xilinx
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- Xilinx-specific optimizations.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.arith.all;
entity arith_addw_xilinx is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := CAI; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC -- Carry Skip Scheme
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
use PoC.utils.all;
architecture rtl of arith_addw_xilinx is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => ASC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block and Core Carry Chain
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
signal cc : std_logic_vector(K+M-1 downto 0);
begin
cc(0) <= cin;
-- Rightmost Block
genChain: for i in 0 to M-1 generate
signal pp : std_logic;
begin
pp <= a(i) xor b(i);
cc_mux: MUXCY
port map (
O => cc(i+1),
CI => cc(i),
DI => a(i),
S => pp
);
cc_xor: XORCY
port map (
O => s(i),
CI => cc(i),
LI => pp
);
end generate genChain;
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
genChain: for i in 1 to K-1 generate
cc_mux: MUXCY
port map (
O => cc(M+i),
CI => cc(M+i-1),
DI => g(i),
S => p(i)
);
end generate genChain;
end generate genCCC;
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
cc(cc'left downto M+1) <= g or (p and cc(K+M-2 downto M));
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & cc(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
cc(cc'left downto M+1) <= gg(gg'high)(K-1 downto 1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & cc(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
cc(cc'left downto M+1) <= gg(gg'high)(K-1 downto 1);
end generate genPPN_BK;
c <= cc(K+M-2 downto M);
cout <= cc(cc'left);
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
begin
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal c0 : std_logic_vector(HI+1 downto LO);
signal c1 : std_logic_vector(HI+1 downto LO);
begin
c0(LO) <= '0';
c1(LO) <= '1';
genChain: for j in LO to HI generate
signal p0, s0 : std_logic;
signal p1, s1 : std_logic;
begin
p0 <= a(j) xor b(j);
-- Computation of (c0, s0)
c0_mux: MUXCY
port map (
O => c0(j+1),
CI => c0(j),
DI => a(j),
S => p0
);
c0_xor: XORCY
port map (
O => s0,
CI => c0(j),
LI => p0
);
-- Computation of (c1, s1) and Block Sum
c1_lut: LUT6_2
generic map (
INIT => x"66666666_FF00F0F0"
)
port map (
O6 => p1,
O5 => s(j),
I5 => '1',
I4 => c(i),
I3 => s1,
I2 => s0,
I1 => b(j),
I0 => a(j)
);
c1_mux: MUXCY
port map (
O => c1(j+1),
CI => c1(j),
DI => a(j),
S => p1
);
c1_xor: XORCY
port map (
O => s1,
CI => c1(j),
LI => p1
);
end generate genChain;
g(i) <= c0(HI+1);
p(i) <= c1(HI+1) xor c0(HI+1);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
constant MD : natural := (HI-LO+1)/2; -- Full double blocks
constant MR : natural := HI-LO+1 - 2*MD; -- Single closing block
signal c0 : std_logic_vector(HI+1 downto LO);
signal pp : std_logic_vector(MR+MD downto 0); -- Cumulative Propagates
begin
-- Computation of P and s
c0(LO) <= '0';
pp(0) <= '1';
genDoubles: for j in 0 to MD-1 generate
constant BASE : natural := LO + 2*j;
signal pl, pr : std_logic; -- Left / right propagates
signal sl, sr : std_logic; -- Left / right sum bits
signal pd : std_logic; -- Joint propagate
begin
-- Sum Bit Computations
ps_lut_r: LUT6_2
generic map (
INIT => x"66666666_9F60FF00"
)
port map (
O6 => pr,
O5 => s(BASE+1),
I5 => '1',
I4 => c(i),
I3 => sl,
I2 => pp(j),
I1 => b(BASE),
I0 => a(BASE)
);
ps_lut_l: LUT6_2
generic map (
INIT => x"66666666_0FF0FF00"
)
port map (
O6 => pl,
O5 => s(BASE),
I5 => '1',
I4 => c(i),
I3 => sr,
I2 => pp(j),
I1 => b(BASE+1),
I0 => a(BASE+1)
);
c0_mux_r: MUXCY
port map (
O => c0(BASE+1),
CI => c0(BASE),
DI => a(BASE),
S => pr
);
c0_mux_l: MUXCY
port map (
O => c0(BASE+2),
CI => c0(BASE+1),
DI => a(BASE+1),
S => pl
);
genLSB: if j = 0 generate
sr <= pr;
end generate;
genHSB: if j > 0 generate
s0_xor_r: XORCY
port map (
O => sr,
CI => c0(BASE),
LI => pr
);
end generate;
s0_xor_l: XORCY
port map (
O => sl,
CI => c0(BASE+1),
LI => pl
);
-- Propagate Chain
pd <= (a(BASE+1) xor b(BASE+1)) and (a(BASE) xor b(BASE));
pp_mux: MUXCY
port map (
O => pp(j+1),
CI => pp(j),
DI => '0',
S => pd
);
end generate genDoubles;
genLast: if MR > 0 generate
constant BASE : natural := LO+2*MD;
signal p, s0 : std_logic;
begin
ps_lut_l: LUT6_2
generic map (
INIT => x"66666666_0FF0FF00"
)
port map (
O6 => p,
O5 => s(BASE),
I5 => '1',
I4 => c(i),
I3 => s0,
I2 => pp(MD),
I1 => b(BASE),
I0 => a(BASE)
);
c0_mux: MUXCY
port map (
O => c0(BASE+1),
CI => c0(BASE),
DI => a(BASE),
S => p
);
s0_xor: XORCY
port map (
O => s0,
CI => c0(BASE),
LI => p
);
-- Let synthesis merge it into carry computation
pp(pp'left) <= (a(BASE) xor b(BASE)) and pp(MD);
end generate genLast;
g(i) <= c0(c0'left);
p(i) <= pp(pp'left);
end generate genCAI;
genCCA: if ARCH = CCA generate
constant M : positive := HI-LO+1;
constant D : positive := M/2;
constant H : positive := (D+5)/6;
signal pl : std_logic_vector(M-D-1 downto 0);
signal pc : std_logic_vector(M-D downto 0);
begin
pc(0) <= '0';
genDoubles: for j in 0 to D-1 generate
signal gl : std_logic;
begin
gp_lut: LUT6_2
generic map (
INIT => x"12480000_EE880000"
)
port map (
O6 => pl(j),
O5 => gl,
I5 => '1',
I4 => '1',
I3 => a(LO+2*j+1),
I2 => a(LO+2*j),
I1 => b(LO+2*j+1),
I0 => b(LO+2*j)
);
c0_mux: MUXCY
port map (
O => pc(j+1),
CI => pc(j),
DI => gl,
S => pl(j)
);
end generate genDoubles;
genOdd: if M-D > D generate
pl(D) <= a(HI) xnor b(HI);
pc(D+1) <= pl(D) and pc(D);
end generate genOdd;
g(i) <= pc(pc'left);
p(i) <= 'X' when Is_X(pl) else
'1' when pl = (pl'range => '1') else
'0';
s(HI downto LO) <= std_logic_vector(unsigned(a(HI downto LO)) + unsigned(b(HI downto LO)) +
(0 to 0 => c(i)));
end generate genCCA;
end generate genBlocks;
end architecture;
| apache-2.0 | 49a7fd3fb8036511181827175a885976 | 0.516725 | 3.0199 | false | false | false | false |
hoangt/PoC | src/misc/misc_bit_lz.vhdl | 2 | 8,857 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Description:
--
-- An LZ77-based bit stream compressor.
--
-- Output Format
--
-- 1 | Literal
-- A literal bit string of length COUNT_BITS+OFFSET_BITS.
--
-- 0 | <Count:COUNT_BITS> | <Offset:OFFSET_BITS>
-- Repetition starting at <Offset> in history buffer of length
-- <Count>+COUNT_BITS+OFFSET_BITS where <Count> < 2^COUNT_BITS-1.
-- Unless <Count> = 2^COUNT_BITS-2, this repetition is
-- followed by a trailing non-matching, i.e. inverted, bit.
-- The most recent bit just preceding the repetition is considered to be at
-- offset zero(0). Older bits are at higher offsets accordingly. The
-- reported length of the repetition may actually be greater than the
-- offset. In this case, the repetition is reoccuring in itself. The
-- reconstruction must then be performed in several steps.
--
-- 0 | <1:COUNT_BITS> | <Offset:OFFSET_BITS>
-- This marks the end of the message. The <Offset> field alters the
-- semantics of the immediately preceding message:
--
-- a)If the preceding message was a repetition, <Offset> specifies the value
-- of the trailing bit explicitly in its rightmost bit. The implicit
-- trailing non-matching bit is overridden.
-- b)If the preceding message was a literal, <Offset> is a non-positive
-- number d given in its one's complement representation. The value
-- ~d specifies the number of bits, which this literal repeated of the
-- preceding output. These bits must be deleted from the reconstructed
-- stream.
--
--
-- Parameter Constraints
--
-- COUNT_BITS <= OFFSET_BITS < 2**COUNT_BITS - COUNT_BITS
--
-- ===========================================================================
-- Authors: Thomas B. Preusser <[email protected]>
--
-- ===========================================================================
-- References:
--
-- Original Study
-- Kai-Uwe Irrgang <[email protected]>
-- PhD Thesis: "Modellierung von On-Chip-Trace-Architekturen
-- fuer eingebettete Systeme"
--
-- Papers
-- Kai-Uwe Irrgang and Thomas B. Preusser and Rainer G. Spallek:
-- "An LZ77-Style Bit-Level Compression for Trace Data Compaction",
-- International Conference on Field Programmable Logic and
-- Applications (FPL 2015), Sep, 2015.
--
-- Kai-Uwe Irrgang and Thomas B. Preusser and Rainer G. Spallek:
-- "Kompression von Tracedaten auf der Basis eines auf Bitebene
-- arbeitenden LZ77-Woerterbuchansatzes",
-- Fehlertolerante und energieeffiziente eingebettete Systeme:
-- Methoden und Anwendungen (FEES 2015), Oct, 2015.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity misc_bit_lz is
generic(
COUNT_BITS : positive;
OFFSET_BITS : positive;
OUTPUT_REGS : boolean := true; -- Register all outputs
OPTIMIZE_SPEED : boolean := true -- Favor achievable clock over size
);
port(
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Data Input
din : in std_logic;
put : in std_logic;
flush : in std_logic; -- end of message,
-- to be asserted after last associated put
-- Data Output
odat : out std_logic_vector(COUNT_BITS+OFFSET_BITS downto 0);
ostb : out std_logic
);
end misc_bit_lz;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of misc_bit_lz is
constant HISTORY_SIZE : positive := 2**OFFSET_BITS;
constant LITERAL_LEN : positive := COUNT_BITS + OFFSET_BITS;
-- History and Match Buffers
signal History : std_logic_vector(HISTORY_SIZE downto 0) := (others => '0');
signal Match : std_logic_vector(HISTORY_SIZE-1 downto 0) := (others => '1');
signal Count : signed(COUNT_BITS downto 0) := to_signed(-LITERAL_LEN-1, 1+COUNT_BITS);
signal Offset : unsigned(OFFSET_BITS-1 downto 0) := (others => '-');
signal Term : std_logic := '0';
signal Offset_nxt : unsigned(Offset'range);
signal ov : X01; -- Counter Overflow
signal valid : X01; -- Still some Match available
-- Outputs
signal data : std_logic_vector(odat'range);
signal push : std_logic;
begin
assert COUNT_BITS <= OFFSET_BITS
report "Requiring: COUNT_BITS <= OFFSET_BITS"
severity failure;
assert LITERAL_LEN < 2**COUNT_BITS
report "Requiring: COUNT_BITS + OFFSET_BITS < 2**COUNT_BITS"
severity failure;
-- Registers
process(clk)
variable Count_nxt : signed(Count'range);
variable Match_nxt : std_logic_vector(Match'range);
begin
if rising_edge(clk) then
if rst = '1' or Term = '1' then
History <= (others => '0');
Match <= (others => '1');
Count <= to_signed(-LITERAL_LEN-1, Count'length);
Offset <= (others => '-');
Term <= '0';
elsif flush = '1' then
History <= (others => '-');
Match <= (others => '-');
Count <= (others => '1'); -- End Marker
Count(Count'left) <= '0'; -- Output Format Selector
if Count(Count'left) = '0' then
Offset <= (others => '0');
Offset(0) <= History(0);
else
Offset <= (others => '1'); -- Sign Extension
Offset(Count'left-1 downto 0) <= unsigned(Count(Count'left-1 downto 0));
end if;
Term <= '1';
else
-- Check for an output condition
if push = '0' then
Match_nxt := Match;
Count_nxt := Count;
Offset <= Offset_nxt;
else
case ov is
when '0' =>
Count_nxt := to_signed(-LITERAL_LEN-1, Count'length);
Match_nxt := (others => '1');
when '1' =>
Count_nxt := to_signed(-LITERAL_LEN, Count'length);
Match_nxt := History(History'left downto 1) xnor (Match'range => History(0));
when 'X' =>
Count_nxt := (others => 'X');
Match_nxt := (others => 'X');
end case;
Offset <= (others => '-');
end if;
-- Check for an input condition
if put = '1' then
-- Shift input into History Buffer
History <= History(History'left-1 downto 0) & din;
-- Update Match vector and Count
Match_nxt := Match_nxt and (History(Match'range) xnor (Match'range => din));
Count_nxt := Count_nxt + 1;
end if;
Match <= Match_nxt;
Count <= Count_nxt;
end if; -- rst /= '1'
end if; -- rising_edge(clk)
end process;
genPlain: if OPTIMIZE_SPEED generate
process(Match)
begin
Offset_nxt <= (others => '-');
for i in Match'range loop
if Match(i) = '1' then
Offset_nxt <= to_unsigned(i, Offset'length);
end if;
end loop;
end process;
end generate genPlain;
genArith: if not OPTIMIZE_SPEED generate
process(Match)
variable onehot : std_logic_vector(Match'range);
variable binary : unsigned(Offset'range);
begin
onehot := std_logic_vector(unsigned(not Match) + 1) and Match;
binary := (others => '0');
for i in onehot'range loop
if onehot(i) = '1' then
binary := binary or to_unsigned(i, binary'length);
end if;
end loop;
Offset_nxt <= binary;
end process;
end generate genArith;
-- Check for Counter Overflow
ov <= 'X' when Is_X(std_logic_vector(Count)) else
'1' when Count = 2**COUNT_BITS-2 else
'0';
-- Check if there is still some valid Match
valid <= '0' when Match = (Match'range => '0') else -- all '0'
'X' when to_bitvector(std_ulogic_vector(Match)) = (Match'range => '0') else -- no '1'
'1'; -- some '1'
-- Compute Outputs
data <= '1' & History(LITERAL_LEN-1 downto 0) when Count(Count'left) = '1' else -- literal
std_logic_vector(Count) & std_logic_vector(Offset); -- repetition
push <= '1' when flush = '1' or Term = '1' else
'X' when Is_X(std_logic_vector(Count)) else
ov when ov /= '0' else
not valid when Count >= -1 else
'0';
genOutputComb: if not OUTPUT_REGS generate
odat <= data;
ostb <= push;
end generate;
genOutputRegs: if OUTPUT_REGS generate
process(clk)
begin
if rising_edge(clk) then
odat <= data;
ostb <= push;
end if;
end process;
end generate;
end rtl;
| apache-2.0 | 337bc387ef43a0e207c915e17047c013 | 0.566783 | 3.754557 | false | false | false | false |
hoangt/PoC | src/io/io_GlitchFilter.vhdl | 2 | 3,752 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Glitch Filter
--
-- Description:
-- ------------------------------------
-- This module filters glitches on a wire. The high and low spike suppression
-- cycle counts can be configured.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.io.all;
entity io_GlitchFilter is
generic (
HIGH_SPIKE_SUPPRESSION_CYCLES : NATURAL := 5;
LOW_SPIKE_SUPPRESSION_CYCLES : NATURAL := 5
);
port (
Clock : in STD_LOGIC;
Input : in STD_LOGIC;
Output : out STD_LOGIC
);
end;
architecture rtl of io_GlitchFilter is
-- Timing table ID
constant TTID_HIGH_SPIKE : NATURAL := 0;
constant TTID_LOW_SPIKE : NATURAL := 1;
-- Timing table
constant TIMING_TABLE : T_NATVEC := (
TTID_HIGH_SPIKE => HIGH_SPIKE_SUPPRESSION_CYCLES,
TTID_LOW_SPIKE => LOW_SPIKE_SUPPRESSION_CYCLES
);
signal State : STD_LOGIC := '0';
signal NextState : STD_LOGIC;
signal TC_en : STD_LOGIC;
signal TC_Load : STD_LOGIC;
signal TC_Slot : NATURAL;
signal TC_Timeout : STD_LOGIC;
begin
assert FALSE
report "GlitchFilter: " &
"HighSpikeSuppressionCycles=" & INTEGER'image(TIMING_TABLE(TTID_HIGH_SPIKE)) & " " &
"LowSpikeSuppressionCycles=" & INTEGER'image(TIMING_TABLE(TTID_LOW_SPIKE)) & " "
severity NOTE;
process(Clock)
begin
if rising_edge(Clock) then
State <= NextState;
end if;
end process;
process(State, Input, TC_Timeout)
begin
NextState <= State;
TC_en <= '0';
TC_Load <= '0';
TC_Slot <= 0;
case State is
when '0' =>
TC_Slot <= TTID_HIGH_SPIKE;
if (Input = '1') then
TC_en <= '1';
else
TC_Load <= '1';
end if;
if ((Input and TC_Timeout) = '1') then
NextState <= '1';
end if;
when '1' =>
TC_Slot <= TTID_LOW_SPIKE;
if (Input = '0') then
TC_en <= '1';
else
TC_Load <= '1';
end if;
if ((not Input and TC_Timeout) = '1') then
NextState <= '0';
end if;
when others =>
null;
end case;
end process;
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => TIMING_TABLE -- timing table
)
port map (
Clock => Clock, -- clock
Enable => TC_en, -- enable counter
Load => TC_Load, -- load Timing Value from TIMING_TABLE selected by slot
Slot => TC_Slot, --
Timeout => TC_Timeout -- timing reached
);
Output <= State;
end;
| apache-2.0 | f72a834e6562722e410f393530ba3b1a | 0.559435 | 3.317418 | false | false | false | false |
hoangt/PoC | src/bus/stream/stream_Mux.vhdl | 2 | 6,727 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_Mux is
generic (
portS : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
META_BITS : NATURAL := 8;
META_REV_BITS : NATURAL := 2--;
-- WEIGHTS : T_INTVEC := (1, 1)
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- IN Ports
In_Valid : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_Data : in T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0);
In_Meta : in T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0);
In_Meta_rev : out T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0);
In_SOF : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_EOF : in STD_LOGIC_VECTOR(portS - 1 downto 0);
In_Ack : out STD_LOGIC_VECTOR(portS - 1 downto 0);
-- OUT Port
Out_Valid : out STD_LOGIC;
Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0);
Out_Meta_rev : in STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC;
Out_EOF : out STD_LOGIC;
Out_Ack : in STD_LOGIC
);
end;
architecture rtl of Stream_Mux is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1;
type T_STATE is (ST_IDLE, ST_DATAFLOW);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal FSM_Dataflow_en : STD_LOGIC;
signal RequestVector : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal RequestWithSelf : STD_LOGIC;
signal RequestWithoutSelf : STD_LOGIC;
signal RequestLeft : UNSIGNED(portS - 1 downto 0);
signal SelectLeft : UNSIGNED(portS - 1 downto 0);
signal SelectRight : UNSIGNED(portS - 1 downto 0);
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := to_slv(2 ** (portS - 1), portS);
signal ChannelPointer_nxt : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0);
signal idx : T_CHANNEL_INDEX;
signal Out_EOF_i : STD_LOGIC;
begin
RequestVector <= In_Valid and In_SOF;
RequestWithSelf <= slv_or(RequestVector);
RequestWithoutSelf <= slv_or(RequestVector and not ChannelPointer_d);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, RequestWithSelf, RequestWithoutSelf, Out_Ack, Out_EOF_i, ChannelPointer_d, ChannelPointer_nxt)
begin
NextState <= State;
FSM_Dataflow_en <= '0';
ChannelPointer_en <= '0';
ChannelPointer <= ChannelPointer_d;
case State is
when ST_IDLE =>
if (RequestWithSelf = '1') then
ChannelPointer_en <= '1';
NextState <= ST_DATAFLOW;
end if;
when ST_DATAFLOW =>
FSM_Dataflow_en <= '1';
if ((Out_Ack and Out_EOF_i) = '1') then
if (RequestWithoutSelf = '0') then
NextState <= ST_IDLE;
else
ChannelPointer_en <= '1';
end if;
end if;
end case;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(2 ** (portS - 1), portS);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
end if;
end if;
end process;
RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(RequestVector);
SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft;
SelectRight <= (unsigned(not RequestVector) + 1) and unsigned(RequestVector);
ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft));
ChannelPointer_bin <= onehot2bin(ChannelPointer);
idx <= to_integer(ChannelPointer_bin);
Out_Data <= get_row(In_Data, idx);
Out_Meta <= get_row(In_Meta, idx);
Out_SOF <= In_SOF(to_integer(ChannelPointer_bin));
Out_EOF_i <= In_EOF(to_integer(ChannelPointer_bin));
Out_Valid <= In_Valid(to_integer(ChannelPointer_bin)) and FSM_Dataflow_en;
Out_EOF <= Out_EOF_i;
In_Ack <= (In_Ack 'range => (Out_Ack and FSM_Dataflow_en)) and ChannelPointer;
genMetaReverse_0 : if (META_REV_BITS = 0) generate
In_Meta_rev <= (others => (others => '0'));
end generate;
genMetaReverse_1 : if (META_REV_BITS > 0) generate
signal Temp_Meta_rev : T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z'));
begin
genAssign : for i in 0 to portS - 1 generate
signal row : STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
begin
row <= Out_Meta_rev and (row'range => ChannelPointer(i));
assign_row(Temp_Meta_rev, row, i);
end generate;
In_Meta_rev <= Temp_Meta_rev;
end generate;
end architecture;
| apache-2.0 | 61b28f9bf05768e8d2b5ce2ebb5b1ed4 | 0.60116 | 3.201809 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/synth/design_1_lmb_bram_0.vhd | 2 | 15,379 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_lmb_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_lmb_bram_0;
ARCHITECTURE design_1_lmb_bram_0_arch OF design_1_lmb_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_lmb_bram_0_arch : ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=design_1_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "design_1_lmb_bram_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 8192,
C_READ_DEPTH_A => 8192,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 8192,
C_READ_DEPTH_B => 8192,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_lmb_bram_0_arch;
| gpl-3.0 | 43f025a5bd1f51550717b7d9418a8fc0 | 0.634372 | 3.03453 | false | false | false | false |
bpervan/uart | UARTController.vhd | 1 | 2,400 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:39:42 03/11/2014
-- Design Name:
-- Module Name: UARTController - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTController is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
w_data : in STD_LOGIC_VECTOR (7 downto 0);
w_start : in STD_LOGIC;
tx : out STD_LOGIC;
w_done : out STD_LOGIC;
r_data : out STD_LOGIC_VECTOR (7 downto 0);
r_done : out STD_LOGIC;
led_out : out std_logic_vector (6 downto 0));
end UARTController;
architecture Behavioral of UARTController is
component BaudRateGenerator port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC
);
end component;
component UARTReciever port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
rx : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0);
rx_done : out STD_LOGIC;
led : out std_logic_vector (6 downto 0));
end component;
component UARTTransmitter port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
d_in : in STD_LOGIC_VECTOR (7 downto 0);
tx_start : in STD_LOGIC;
tx_done : out STD_LOGIC;
tx : out STD_LOGIC);
end component;
signal tick : std_logic;
begin
BRG: entity work.BaudRateGenerator port map (clk => clk,rst => rst,tick => tick);
URx: entity work.UARTReciever port map (clk => clk, rst => rst, tick => tick, rx => rx, d_out => r_data, rx_done => r_done, led => led_out);
UTx: entity work.UARTTransmitter port map (clk => clk, rst => rst, tick => tick, d_in => w_data, tx_start => w_start, tx_done => w_done, tx => tx);
end Behavioral;
| mit | ba4fefc35f6dcde32a924537a57afa69 | 0.580833 | 3.478261 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm_primitives.vhd | 4 | 7,680 | -------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
| gpl-3.0 | 59ca527f8609824421dcacbf9c9f37b7 | 0.56888 | 3.902439 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sources_1/new/i2c_controller.vhd | 1 | 4,554 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.01.2016 19:23:03
-- Design Name:
-- Module Name: i2c_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_controller is
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
--fifo pins
FIFO_WriteEn : out STD_LOGIC;
FIFO_DataIn: out std_logic_vector ( 7 downto 0);
FIFO_Full : in STD_LOGIC;
ena : out STD_LOGIC := '0'; --latch in command
busy : in STD_LOGIC; --indicates transaction in progress
data_rd : in STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : in STD_LOGIC; --flag if improper acknowledge from slave
sensorId : in STD_LOGIC_VECTOR(7 downto 0);
delimeter : in STD_LOGIC_VECTOR(7 downto 0) -- delimeter character
);
end i2c_controller;
architecture Behavioral of i2c_controller is
-- state control signals
type state_type is (STATE_WAITREADY, STATE_STARTREAD, STATE_WAIT_RX, STATE_GETBYTE, STATE_WRITEBYTE, STATE_FINISHWRITE, STATE_FINISHREAD, STATE_SLEEPCHK, STATE_SLEEPINC, STATE_HEADERWRITE, STATE_HEADERIDWRITE);
signal state_reg: state_type := STATE_WAITREADY;
-- recd. byte counter
signal ByteCount :INTEGER RANGE 0 to 7 := 0;
signal delay : INTEGER RANGE 0 to 100000 := 0;
begin
-- state control
process (clk, FIFO_Full, busy, ack_error) -- process to handle the next state
begin
if rising_edge (clk) then
case state_reg is
when STATE_WAITREADY =>
--reset the timers & counters
delay <= 0;
ByteCount<= 0;
-- make sure not enabled
ena <= '0';
if (busy = '0') then
state_reg <= STATE_STARTREAD;
end if;
when STATE_STARTREAD =>
-- load the address and start a read
ena <= '1';
if (busy = '1') then
state_reg <= STATE_WAIT_RX;
end if;
when STATE_WAIT_RX =>
if (busy = '0' and ack_error = '0') then
state_reg <= STATE_GETBYTE;
else
if (ack_error = '1') then
state_reg <= STATE_WAITREADY;
end if;
end if;
when STATE_GETBYTE =>
FIFO_DataIn <= data_rd;
state_reg <= STATE_WRITEBYTE;
when STATE_WRITEBYTE =>
FIFO_WriteEn <= '1';
ByteCount <= ByteCount + 1;
state_reg <= STATE_FINISHWRITE;
when STATE_FINISHWRITE =>
FIFO_WriteEn <= '0';
if (ByteCount = 4) then
state_reg <=STATE_HEADERIDWRITE ;
elsif (ByteCount = 5) then
state_reg <= STATE_HEADERWRITE;
elsif (ByteCount = 6) then
state_reg <= STATE_SLEEPCHK;
else
state_reg <= STATE_FINISHREAD;
end if;
when STATE_FINISHREAD =>
if (ByteCount = 3) then
ena<='0';
end if;
if (busy ='1') then
state_reg <= STATE_WAIT_RX;
end if;
when STATE_HEADERWRITE =>
FIFO_DataIn <= delimeter;
state_reg <= STATE_WRITEBYTE;
when STATE_HEADERIDWRITE =>
FIFO_DataIn <= sensorId;
state_reg <= STATE_WRITEBYTE;
when STATE_SLEEPCHK =>
ena <= '0'; -- this might not be needed anymore.
if (delay = 100000) then
state_reg <= STATE_WAITREADY;
else
state_reg <= STATE_SLEEPINC;
end if;
when STATE_SLEEPINC =>
delay <= delay + 1;
state_reg <= STATE_SLEEPCHK;
when others =>
state_reg <= STATE_WAITREADY;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 8b3bd32e83f218fea6d54bb49a3ea670 | 0.527448 | 4.3125 | false | false | false | false |
olofk/oh | xilibs/ip/fifo_async_104x32/synth/fifo_async_104x32.vhd | 1 | 39,071 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_async_104x32 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(103 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(103 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END fifo_async_104x32;
ARCHITECTURE fifo_async_104x32_arch OF fifo_async_104x32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_async_104x32_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(103 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(103 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_async_104x32_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_async_104x32_arch : ARCHITECTURE IS "fifo_async_104x32,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_async_104x32_arch: ARCHITECTURE IS "fifo_async_104x32,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=104,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=104,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=1,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=16,C_PROG_FULL_THRESH_NEGATE_VAL=15,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF almost_full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE ALMOST_FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 5,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 104,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 104,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 1,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 16,
C_PROG_FULL_THRESH_NEGATE_VAL => 15,
C_PROG_FULL_TYPE => 1,
C_RD_DATA_COUNT_WIDTH => 5,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 5,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
valid => valid,
prog_full => prog_full,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_async_104x32_arch;
| gpl-3.0 | 7b4cd317425ace324d9cb55d7d4a14c1 | 0.629086 | 2.917488 | false | false | false | false |
hoangt/PoC | src/io/io_FanControl.vhdl | 1 | 10,219 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic Fan Controller
--
-- Description:
-- ------------------------------------
-- This module generates a PWM signal for a 3-pin (transistor controlled) or
-- 4-pin fan header. The FPGAs temperature is read from device specific system
-- monitors (normal, user temperature, over temperature).
--
-- For example the Xilinx System Monitors are configured as follows:
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.xil.all;
entity io_FanControl is
generic (
CLOCK_FREQ : FREQ;
ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE;
ENABLE_TACHO : BOOLEAN := FALSE
);
port (
-- Global Control
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Fan Control derived from internal System Health Monitor
Fan_PWM : out STD_LOGIC;
-- Decoding of Speed Sensor (Requires ENABLE_TACHO)
Fan_Tacho : in std_logic := 'X';
TachoFrequency : out std_logic_vector(15 downto 0)
);
end;
architecture rtl of io_FanControl is
constant TIME_STARTUP : TIME := 500 ms; -- StartUp time
constant PWM_RESOLUTION : POSITIVE := 4; -- 4 Bit resolution => 0 to 15 steps
constant PWM_FREQ : FREQ := 10 Hz; --
constant TACHO_RESOLUTION : POSITIVE := 8;
signal PWM_PWMIn : STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0);
signal PWM_PWMOut : STD_LOGIC := '0';
begin
-- System Monitor and temperature to PWM ratio calculation for Virtex6
-- ==========================================================================================================================================================
genXilinx : if (VENDOR = VENDOR_XILINX) generate
signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genML605 : if (BOARD = BOARD_ML605) generate
SystemMonitor : xil_SystemMonitor_Virtex6
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
genSeries7Board : if ((BOARD = BOARD_KC705) or (BOARD = BOARD_VC707)) generate
SystemMonitor : xil_SystemMonitor_Series7
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
sync : entity PoC.sync_Bits
generic map (
BITS => 2
)
port map (
Clock => Clock,
Input(0) => OverTemperature_async,
Input(1) => UserTemperature_async,
Output(0) => OverTemperature_sync,
Output(1) => UserTemperature_sync
);
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
-- signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
-- signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genDE4 : if (BOARD = BOARD_DE4) generate
OverTemperature_sync <= '0';
UserTemperature_sync <= '1';
end generate;
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
-- PWM signal modulator
-- ==========================================================================================================================================================
PWM : entity PoC.io_PulseWidthModulation
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
PWM_FREQ => PWM_FREQ, --
PWM_RESOLUTION => PWM_RESOLUTION --
)
port map (
Clock => Clock,
Reset => Reset,
PWMIn => PWM_PWMIn,
PWMOut => PWM_PWMOut
);
-- registered output
Fan_PWM <= PWM_PWMOut when rising_edge(Clock);
-- tacho signal interpretation -> convert to RPM
-- ==========================================================================================================================================================
genNoTacho : if (ENABLE_TACHO = FALSE) generate
TachoFrequency <= (TachoFrequency'range => 'X');
end generate;
genTacho : if (ENABLE_TACHO = TRUE) generate
signal Tacho_sync : STD_LOGIC;
signal Tacho_Freq : STD_LOGIC_VECTOR(TACHO_RESOLUTION - 1 downto 0);
begin
-- Input Synchronization
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
Tacho_sync <= Fan_Tacho;
end generate;
genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => Fan_Tacho, -- Data to be synchronized
Output(0) => Tacho_sync -- synchronised data
);
end generate;
Tacho : entity PoC.io_FrequencyCounter
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
TIMEBASE => (60 sec / 64), -- ca. 1 second
RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM
)
port map (
Clock => Clock,
Reset => Reset,
FreqIn => Tacho_sync,
FreqOut => Tacho_Freq
);
-- multiply by 64; divide by 2 for RPMs (2 impulses per revolution) => append 5x '0'
TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit
end generate;
end;
| apache-2.0 | 909edd298aadc9bc076bed45b5c38553 | 0.519131 | 3.64834 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/synth/design_1_rst_clk_wiz_1_100M_0.vhd | 2 | 6,711 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_clk_wiz_1_100M_0;
ARCHITECTURE design_1_rst_clk_wiz_1_100M_0_arch OF design_1_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_clk_wiz_1_100M_0_arch : ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_clk_wiz_1_100M_0_arch;
| gpl-3.0 | 1322cf155b8423f776c3167fb4144016 | 0.712412 | 3.392821 | false | false | false | false |
s-kostyuk/vhdl_samples | substractor/substractor.vhd | 1 | 845 | library ieee;
use ieee.std_logic_1164.all;
entity substractor is
port(
X, Y: in std_logic_vector(3 downto 0);
Bin: in std_logic;
D: out std_logic_vector(3 downto 0);
Bout: out std_logic
);
end entity;
architecture substractor of substractor is
component full_sub is
port(
X, Y: in std_logic;
Bin: in std_logic;
Bout: out std_logic;
D: out std_logic
);
end component;
signal B_1_2, B_2_3, B_3_4: std_logic;
begin
SUB1: full_sub port map(X => X(3), Y => Y(3), Bin => Bin, D => D(3), Bout => B_1_2);
SUB2: full_sub port map(X => X(2), Y => Y(2), Bin => B_1_2, D => D(2), Bout => B_2_3);
SUB3: full_sub port map(X => X(1), Y => Y(1), Bin => B_2_3, D => D(1), Bout => B_3_4);
SUB4: full_sub port map(X => X(0), Y => Y(0), Bin => B_3_4, D => D(0), Bout => Bout );
end architecture;
| mit | 0069e92cf20bb8ec36804547d0386a3e | 0.559763 | 2.360335 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernetlite_0_0/synth/design_1_axi_ethernetlite_0_0.vhd | 2 | 13,334 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0;
USE axi_ethernetlite_v3_0.axi_ethernetlite;
ENTITY design_1_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END design_1_axi_ethernetlite_0_0;
ARCHITECTURE design_1_axi_ethernetlite_0_0_arch OF design_1_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_PING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END design_1_axi_ethernetlite_0_0_arch;
| gpl-3.0 | 2450e8f83233bc36e13ee6de10d46a92 | 0.679841 | 3.135936 | false | false | false | false |
lowRISC/greth-library | greth_library/ambalib/types_amba4.vhd | 2 | 36,762 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Declaration and common methods implementation of the types_nasti
--! package.
--! @details This file defines bus interface constants that have to be
--! used by any periphery device implementation in order
--! to provide compatibility in a wide range of possible settings.
--! For better implementation use the AXI4 register bank and
--! implemented tasks from this file.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common constants and data conversion functions library
library commonlib;
use commonlib.types_common.all;
--! @brief System bus AMBA AXI(NASTI) types definition.
--! @details This package provides general constants, data structures and
--! and functions description that define behaviour of all
--! peripheries devices implementing AXI4 interface.
package types_amba4 is
--! @name AMBA AXI slaves generic IDs.
--! @details Each module in a SoC has to be indexed by unique identificator.
--! In current implementation it is used sequential indexing for it.
--! Indexes are used to specify a device bus item in a vectors.
--! @{
--! Configuration index of the GPIO (General Purpose In/Out) module.
constant CFG_NASTI_SLAVE_GPIO : integer := 0;
--! Configuration index of the Ethernet MAC module.
constant CFG_NASTI_SLAVE_ETHMAC : integer := 1;
--! Total number of the slaves devices.
constant CFG_NASTI_SLAVES_TOTAL : integer := 2;
--! @}
--! @name AXI4 masters generic IDs.
--! @details Each master must be assigned to a specific ID that used
--! as an index in the vector array of AXI master bus.
--! @{
--! Ethernet MAC master interface generic index.
constant CFG_NASTI_MASTER_ETHMAC : integer := 0;
--! Total Number of master devices on system bus.
constant CFG_NASTI_MASTER_TOTAL : integer := 1;
--! @}
--! @name AXI4 interrupt generic IDs.
--! @details Unique indentificator of the interrupt pin also used
--! as an index in the interrupts bus.
--! @{
--! Ethernet MAC interrupt pin.
constant CFG_IRQ_ETHMAC : integer := 0;
--! Total number of used interrupts in a system
constant CFG_IRQ_TOTAL : integer := 1;
--! @}
--! @name SCALA generated parameters
--! @brief This constant must correspond to Scala defined ones.
--! @{
--! User defined address ID bitwidth (aw_id / ar_id fields).
constant CFG_ROCKET_ID_BITS : integer := 5;
--! Data bus bits width.
constant CFG_NASTI_DATA_BITS : integer := 128;
--! Data bus bytes width
constant CFG_NASTI_DATA_BYTES : integer := CFG_NASTI_DATA_BITS / 8;
--! Address bus bits width.
constant CFG_NASTI_ADDR_BITS : integer := 32;
--! Definition of number of bits in address bus per one data transaction.
constant CFG_NASTI_ADDR_OFFSET : integer := log2(CFG_NASTI_DATA_BYTES);
--! @brief Number of address bits used for device addressing.
--! @details Default is 12 bits = 4 KB of address space minimum per each
--! mapped device.
constant CFG_NASTI_CFG_ADDR_BITS : integer := CFG_NASTI_ADDR_BITS-12;
--! @brief Global alignment is set 32 bits.
constant CFG_ALIGN_BYTES : integer := 4;
--! @brief Number of parallel access to the atomic data.
constant CFG_WORDS_ON_BUS : integer := CFG_NASTI_DATA_BYTES/CFG_ALIGN_BYTES;
--! @}
--! @name AXI Response values
--! @brief AMBA 4.0 specified response types from a slave device.
--! @{
--! @brief Normal access success.
--! @details Indicates that a normal access has been
--! successful. Can also indicate an exclusive access has failed.
constant NASTI_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
--! @brief Exclusive access okay.
--! @details Indicates that either the read or write
--! portion of an exclusive access has been successful.
constant NASTI_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
--! @brief Slave error.
--! @details Used when the access has reached the slave successfully,
--! but the slave wishes to return an error condition to the originating
--! master.
constant NASTI_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
--! @brief Decode error.
--! @details Generated, typically by an interconnect component,
--! to indicate that there is no slave at the transaction address.
constant NASTI_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
--! @}
--! @name AXI burst request type.
--! @brief AMBA 4.0 specified burst operation request types.
--! @{
--! @brief Fixed address burst operation.
--! @details The address is the same for every transfer in the burst
--! (FIFO type)
constant NASTI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
--! @brief Burst operation with address increment.
--! @details The address for each transfer in the burst is an increment of
--! the address for the previous transfer. The increment value depends
--! on the size of the transfer.
constant NASTI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
--! @brief Burst operation with address increment and wrapping.
--! @details A wrapping burst is similar to an incrementing burst, except that
--! the address wraps around to a lower address if an upper address
--! limit is reached
constant NASTI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
--! @}
--! @name Vendor IDs defintion.
--! @{
--! GNSS Sensor Ltd. vendor identificator.
constant VENDOR_GNSSSENSOR : std_logic_vector(15 downto 0) := X"00F1";
--! @}
--! @name Master Device IDs definition:
--! @{
--! RISC-V "Rocket-chip" core Cached TileLink master device.
constant RISCV_CACHED_TILELINK : std_logic_vector(15 downto 0) := X"0500";
--! RISC-V "Rocket-chip" core Uncached TileLink master device.
constant RISCV_UNCACHED_TILELINK : std_logic_vector(15 downto 0) := X"0501";
--! Ethernet MAC master device.
constant GAISLER_ETH_MAC_MASTER : std_logic_vector(15 downto 0) := X"0502";
--! Ethernet MAC master debug interface (EDCL).
constant GAISLER_ETH_EDCL_MASTER : std_logic_vector(15 downto 0) := X"0503";
--! @}
--! @name Slave Device IDs definition:
--! @{
--! Empty slot device
constant GNSSSENSOR_EMPTY : std_logic_vector(15 downto 0) := X"5577";
--! Boot ROM Device ID
constant GNSSSENSOR_BOOTROM : std_logic_vector(15 downto 0) := X"0071";
--! FW ROM image Device ID
constant GNSSSENSOR_FWIMAGE : std_logic_vector(15 downto 0) := X"0072";
--! Internal SRAM block Device ID
constant GNSSSENSOR_SRAM : std_logic_vector(15 downto 0) := X"0073";
--! Configuration Registers Module Device ID provided by gnsslib
constant GNSSSENSOR_PNP : std_logic_vector(15 downto 0) := X"0074";
--! SD-card controller Device ID provided by gnsslib
constant GNSSSENSOR_SPI_FLASH : std_logic_vector(15 downto 0) := X"0075";
--! General purpose IOs Device ID provided by gnsslib
constant GNSSSENSOR_GPIO : std_logic_vector(15 downto 0) := X"0076";
--! RF front-end controller Device ID provided by gnsslib
constant GNSSSENSOR_RF_CONTROL : std_logic_vector(15 downto 0) := X"0077";
--! GNSS Engine Device ID provided by gnsslib
constant GNSSSENSOR_ENGINE : std_logic_vector(15 downto 0) := X"0078";
--! GNSS Engine Stub device
constant GNSSSENSOR_ENGINE_STUB : std_logic_vector(15 downto 0) := X"0068";
--! Fast Search Engines Device ID provided by gnsslib
constant GNSSSENSOR_FSE_V2 : std_logic_vector(15 downto 0) := X"0079";
--! rs-232 UART Device ID
constant GNSSSENSOR_UART : std_logic_vector(15 downto 0) := X"007a";
--! Accelerometer Device ID provided by gnsslib
constant GNSSSENSOR_ACCELEROMETER : std_logic_vector(15 downto 0) := X"007b";
--! Gyroscope Device ID provided by gnsslib
constant GNSSSENSOR_GYROSCOPE : std_logic_vector(15 downto 0) := X"007c";
--! Interrupt controller
constant GNSSSENSOR_IRQCTRL : std_logic_vector(15 downto 0) := X"007d";
--! Ethernet MAC inherited from Gaisler greth module.
constant GNSSSENSOR_ETHMAC : std_logic_vector(15 downto 0) := X"007f";
--! Debug Support Unit device id.
constant GNSSSENSOR_DSU : std_logic_vector(15 downto 0) := X"0080";
--! GP Timers device id.
constant GNSSSENSOR_GPTIMERS : std_logic_vector(15 downto 0) := X"0081";
--! @}
--! @name Decoder of the transaction size.
--! @{
--! Burst length size decoder
constant XSIZE_TOTAL : integer := 8;
--! Definition of the AXI bytes converter.
type xsize_type is array (0 to XSIZE_TOTAL-1) of integer;
--! Decoder of the transaction bytes from AXI format to Bytes.
constant XSizeToBytes : xsize_type := (
0 => 1,
1 => 2,
2 => 4,
3 => 8,
4 => 16,
5 => 32,
6 => 64,
7 => 128
);
--! @}
--! @name Plug'n'Play descriptor constants.
--! @{
--! Undefined type of the descriptor (empty device).
constant PNP_CFG_TYPE_NONE : std_logic_vector := "11";
--! AXI slave device standard descriptor.
constant PNP_CFG_TYPE_SLAVE : std_logic_vector := "00";
--! AXI master device standard descriptor.
constant PNP_CFG_TYPE_MASTER : std_logic_vector := "01";
--! @brief Size in bytes of the standard slave descriptor..
--! @details Firmware uses this value instead of sizeof(nasti_slave_config_type).
constant PNP_CFG_SLAVE_DESCR_BYTES : std_logic_vector(7 downto 0) := X"10";
--! @brief Size in bytes of the standard master descriptor.
--! @details Firmware uses this value instead of sizeof(nasti_master_config_type).
constant PNP_CFG_MASTER_DESCR_BYTES : std_logic_vector(7 downto 0) := X"01";
--! @}
--! @brief Plug-n-play descriptor structure for slave device.
--! @details Each slave device must generates this datatype output that
--! is connected directly to the 'pnp' slave module on system bus.
type nasti_slave_config_type is record
--! Index in the array of slaves devices.
xindex : integer;
--! Base address value.
xaddr : std_logic_vector(CFG_NASTI_CFG_ADDR_BITS-1 downto 0);
--! Maskable bits of the base address.
xmask : std_logic_vector(CFG_NASTI_CFG_ADDR_BITS-1 downto 0);
--! Vendor ID.
vid : std_logic_vector(15 downto 0);
--! Device ID.
did : std_logic_vector(15 downto 0);
--! Descriptor type.
descrtype : std_logic_vector(1 downto 0);
--! Descriptor size in bytes.
descrsize : std_logic_vector(7 downto 0);
end record;
--! @brief Arrays of the plug-n-play descriptors.
--! @details Configuration bus vector from all slaves to plug'n'play
--! NASTI device (pnp).
type nasti_slave_cfg_vector is array (0 to CFG_NASTI_SLAVES_TOTAL-1)
of nasti_slave_config_type;
--! @brief Default slave config value.
--! @default This value corresponds to an empty device and often used
--! as assignment of outputs for the disabled device.
constant nasti_slave_config_none : nasti_slave_config_type := (
0, (others => '0'), (others => '1'), VENDOR_GNSSSENSOR, GNSSSENSOR_EMPTY,
PNP_CFG_TYPE_NONE, PNP_CFG_SLAVE_DESCR_BYTES);
--! @brief Plug-n-play descriptor structure for master device.
--! @details Each master device must generates this datatype output that
--! is connected directly to the 'pnp' slave module on system bus.
type nasti_master_config_type is record
--! Index in the array of masters devices.
xindex : integer;
--! Vendor ID.
vid : std_logic_vector(15 downto 0);
--! Device ID.
did : std_logic_vector(15 downto 0);
--! Descriptor type.
descrtype : std_logic_vector(1 downto 0);
--! Descriptor size in bytes.
descrsize : std_logic_vector(7 downto 0);
end record;
--! @brief Arrays of the plug-n-play descriptors.
--! @details Configuration bus vector from all slaves to plug'n'play
--! NASTI device (pnp).
type nasti_master_cfg_vector is array (0 to CFG_NASTI_MASTER_TOTAL-1)
of nasti_master_config_type;
--! @brief Default master config value.
constant nasti_master_config_none : nasti_master_config_type := (
0, VENDOR_GNSSSENSOR, GNSSSENSOR_EMPTY, PNP_CFG_TYPE_NONE,
PNP_CFG_MASTER_DESCR_BYTES);
--! @brief AMBA AXI4 compliant data structure.
type nasti_metadata_type is record
--! @brief Read address.
--! @details The read address gives the address of the first transfer
--! in a read burst transaction.
addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
--! @brief Burst length.
--! @details This signal indicates the exact number of transfers in
--! a burst. This changes between AXI3 and AXI4. nastiXLenBits=8 so
--! this is an AXI4 implementation.
--! Burst_Length = len[7:0] + 1
len : std_logic_vector(7 downto 0);
--! @brief Burst size.
--! @details This signal indicates the size of each transfer
--! in the burst: 0=1 byte; ..., 6=64 bytes; 7=128 bytes;
size : std_logic_vector(2 downto 0);
--! @brief Read response.
--! @details This signal indicates the status of the read transfer.
--! The responses are:
--! 0b00 FIXED - In a fixed burst, the address is the same for every transfer
--! in the burst. Typically is used for FIFO.
--! 0b01 INCR - Incrementing. In an incrementing burst, the address for each
--! transfer in the burst is an increment of the address for the
--! previous transfer. The increment value depends on the size of
--! the transfer.
--! 0b10 WRAP - A wrapping burst is similar to an incrementing burst, except
--! that the address wraps around to a lower address if an upper address
--! limit is reached.
--! 0b11 resrved.
burst : std_logic_vector(1 downto 0);
--! @brief Lock type.
--! @details Not supported in AXI4.
lock : std_logic;
--! @brief Memory type.
--! @details See table for write and read transactions.
cache : std_logic_vector(3 downto 0);
--! @brief Protection type.
--! @details This signal indicates the privilege and security level
--! of the transaction, and whether the transaction is a data access
--! or an instruction access:
--! [0] : 0 = Unpriviledge access
--! 1 = Priviledge access
--! [1] : 0 = Secure access
--! 1 = Non-secure access
--! [2] : 0 = Data access
--! 1 = Instruction access
prot : std_logic_vector(2 downto 0);
--! @brief Quality of Service, QoS.
--! @details QoS identifier sent for each read transaction.
--! Implemented only in AXI4:
--! 0b0000 - default value. Indicates that the interface is
--! not participating in any QoS scheme.
qos : std_logic_vector(3 downto 0);
--! @brief Region identifier.
--! @details Permits a single physical interface on a slave to be used for
--! multiple logical interfaces. Implemented only in AXI4. This is
--! similar to the banks implementation in Leon3 without address
--! decoding.
region : std_logic_vector(3 downto 0);
end record;
--! @brief Empty metadata value.
constant META_NONE : nasti_metadata_type := (
(others =>'0'), X"00", "000", NASTI_BURST_INCR, '0', X"0", "000", "0000", "0000"
);
--! @brief Master device output signals
type nasti_master_out_type is record
--! Write Address channel:
aw_valid : std_logic;
--! metadata of the read channel.
aw_bits : nasti_metadata_type;
--! Write address ID. Identification tag used for a trasaction ordering.
aw_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
--! Optional user defined signal in a write address channel.
aw_user : std_logic;
--! Write Data channel valid flag
w_valid : std_logic;
--! Write channel data value
w_data : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
--! Write Data channel last address in a burst marker.
w_last : std_logic;
--! Write Data channel strob signals selecting certain bytes.
w_strb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
--! Optional user defined signal in write channel.
w_user : std_logic;
--! Write Response channel accepted by master.
b_ready : std_logic;
--! Read Address Channel data valid.
ar_valid : std_logic;
--! Read Address channel metadata.
ar_bits : nasti_metadata_type;
--! Read address ID. Identification tag used for a trasaction ordering.
ar_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
--! Optional user defined signal in read address channel.
ar_user : std_logic;
--! Read Data channel:
r_ready : std_logic;
end record;
--! @brief Master device empty value.
--! @warning If the master is not connected to the vector then vector value
--! MUST BE initialized by this value.
constant nasti_master_out_none : nasti_master_out_type := (
'0', META_NONE, (others=>'0'), '0',
'0', (others=>'0'), '0', (others=>'0'), '0',
'0', '0', META_NONE, (others=>'0'), '0', '0');
--! @brief Array of all masters outputs.
type nasti_master_out_vector is array (0 to CFG_NASTI_MASTER_TOTAL-1)
of nasti_master_out_type;
--! @brief Master device input signals.
type nasti_master_in_type is record
--! How is owner of the AXI bus. It's controlled by 'axictrl' module.
grant : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
--! Write Address channel.
aw_ready : std_logic;
--! Write Data channel.
w_ready : std_logic;
--! Write Response channel:
b_valid : std_logic;
b_resp : std_logic_vector(1 downto 0);
b_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
b_user : std_logic;
--! Read Address Channel
ar_ready : std_logic;
--! Read valid.
r_valid : std_logic;
--! @brief Read response.
--! @details This signal indicates the status of the read transfer.
--! The responses are:
--! 0b00 OKAY - Normal access success. Indicates that a normal access has
--! been successful. Can also indicate an exclusive access
--! has failed.
--! 0b01 EXOKAY - Exclusive access okay. Indicates that either the read or
--! write portion of an exclusive access has been successful.
--! 0b10 SLVERR - Slave error. Used when the access has reached the slave
--! successfully, but the slave wishes to return an error
--! condition to the originating master.
--! 0b11 DECERR - Decode error. Generated, typically by an interconnect
--! component, to indicate that there is no slave at the
--! transaction address.
r_resp : std_logic_vector(1 downto 0);
--! Read data
r_data : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
--! @brief Read last.
--! @details This signal indicates the last transfer in a read burst.
r_last : std_logic;
--! @brief Read ID tag.
--! @details This signal is the identification tag for the read data
--! group of signals generated by the slave.
r_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
--! @brief User signal.
--! @details Optional User-defined signal in the read channel. Supported
--! only in AXI4.
r_user : std_logic;
end record;
--! @brief Slave device AMBA AXI input signals.
type nasti_slave_in_type is record
--! Write Address channel:
aw_valid : std_logic;
aw_bits : nasti_metadata_type;
aw_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
aw_user : std_logic;
--! Write Data channel:
w_valid : std_logic;
w_data : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
w_last : std_logic;
w_strb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
w_user : std_logic;
--! Write Response channel:
b_ready : std_logic;
--! Read Address Channel:
ar_valid : std_logic;
ar_bits : nasti_metadata_type;
ar_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
ar_user : std_logic;
--! Read Data channel:
r_ready : std_logic;
end record;
--! @brief Slave device AMBA AXI output signals.
type nasti_slave_out_type is record
--! Write Address channel:
aw_ready : std_logic;
--! Write Data channel:
w_ready : std_logic;
--! Write Response channel:
b_valid : std_logic;
b_resp : std_logic_vector(1 downto 0);
b_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
b_user : std_logic;
--! Read Address Channel
ar_ready : std_logic;
--! Read Data channel:
r_valid : std_logic;
--! @brief Read response.
--! @details This signal indicates the status of the read transfer.
--! The responses are:
--! 0b00 OKAY - Normal access success. Indicates that a normal access has
--! been successful. Can also indicate an exclusive access
--! has failed.
--! 0b01 EXOKAY - Exclusive access okay. Indicates that either the read or
--! write portion of an exclusive access has been successful.
--! 0b10 SLVERR - Slave error. Used when the access has reached the slave
--! successfully, but the slave wishes to return an error
--! condition to the originating master.
--! 0b11 DECERR - Decode error. Generated, typically by an interconnect
--! component, to indicate that there is no slave at the
--! transaction address.
r_resp : std_logic_vector(1 downto 0);
--! Read data
r_data : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
--! Read last. This signal indicates the last transfer in a read burst.
r_last : std_logic;
--! @brief Read ID tag.
--! @details This signal is the identification tag for the read data
--! group of signals generated by the slave.
r_id : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
--! @brief User signal.
--! @details Optinal User-defined signal in the read channel. Supported
--! only in AXI4.
r_user : std_logic;--_vector(0 downto 0);
end record;
--! @brief Slave output signals connected to system bus.
--! @details If the slave is not connected to the vector then vector value
--! MUST BE initialized by this value.
constant nasti_slave_out_none : nasti_slave_out_type := (
'0', '0', '0', NASTI_RESP_EXOKAY,
(others=>'0'), '0', '0', '0', NASTI_RESP_EXOKAY, (others=>'1'),
'0', (others=>'0'), '0');
--! Array of all slaves outputs.
type nasti_slaves_out_vector is array (0 to CFG_NASTI_SLAVES_TOTAL-1)
of nasti_slave_out_type;
--! Array of addresses providing word aligned access.
type global_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
--! Slave device states during reading value operation.
type nasti_slave_rstatetype is (rwait, rtrans);
--! Slave device states during writting data operation.
type nasti_slave_wstatetype is (wwait, wtrans);
--! @brief Template bank of registers for any slave device.
type nasti_slave_bank_type is record
rstate : nasti_slave_rstatetype;
wstate : nasti_slave_wstatetype;
rburst : std_logic_vector(1 downto 0);
rsize : integer;
raddr : global_addr_array_type;
rlen : integer; --! AXI4 supports 256 burst operation
rid : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
rresp : std_logic_vector(1 downto 0); --! OK=0
ruser : std_logic;
rwaitready : std_logic; --! Reading wait state flag: 0=waiting
wburst : std_logic_vector(1 downto 0); -- 0=INCREMENT
wsize : integer; -- code in range 0=1 Bytes upto 7=128 Bytes.
waddr : global_addr_array_type; --! 4 KB bank
wlen : integer; --! AXI4 supports 256 burst operation
wid : std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
wresp : std_logic_vector(1 downto 0); --! OK=0
wuser : std_logic;
b_valid : std_logic;
end record;
--! Reset value of the template bank of registers of a slave device.
constant NASTI_SLAVE_BANK_RESET : nasti_slave_bank_type := (
rwait, wwait,
NASTI_BURST_FIXED, 0, (others=>(others=>'0')), 0, (others=>'0'), NASTI_RESP_OKAY, '0', '1',
NASTI_BURST_FIXED, 0, (others=>(others=>'0')), 0, (others=>'0'), NASTI_RESP_OKAY, '0', '0'
);
--! Read/write access state machines implementation for the slave device.
--! @param [in] i Slave input signal passed from system bus.
--! @param [in] cfg Slave confguration descriptor defining memory base address.
--! @param [in] i_bank Bank of registers implemented by each slave device.
--! @param [out] o_bank Updated value for the slave bank of registers.
procedure procedureAxi4(
i : in nasti_slave_in_type;
cfg : in nasti_slave_config_type;
i_bank : in nasti_slave_bank_type;
o_bank : out nasti_slave_bank_type
);
--! @brief Reordering elements of the address to provide 4-bytes memory access.
--! @param[in] mux Reordering control bits.
--! @param[in] iaddr Input addresses array.
--! @return Reordered addresses array.
function functionAddressReorder(
mux : std_logic_vector;
iaddr : global_addr_array_type)
return global_addr_array_type;
procedure procedureWriteReorder(
ena : in std_logic;
mux : in std_logic_vector(1 downto 0);
iwaddr : in global_addr_array_type;
iwstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
iwdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
owaddr : out global_addr_array_type;
owstrb : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
owdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
--! @brief Complementary to address data reordring.
--! @details This function restore data bus as there wasn't address reordering.
--! @param[in] mux Reordering control bits.
--! @param[in] idata Input data array.
--! @return Restored data array.
function functionDataRestoreOrder(
mux : std_logic_vector;
idata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0))
return std_logic_vector;
--! Convert slave bank registers into bus output signals.
--! @param[in] r Bank of registers of the slave device.
--! @param[in] rd_val Formed by slave device read data value.
--! @return Slave device output signals connected to system bus.
function functionAxi4Output(
r : nasti_slave_bank_type;
rd_val : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0))
return nasti_slave_out_type;
--! @brief AXI bus controller.
--! @details Simplified version with the hardcoded priorities to bus access.
--! Lower master index has a higher priority.
--! @param [in] rdslave_with_waitstate
--! @param [in] clk System bus clock.
--! @param [in] nrst Reset with active LOW level.
--! @param [in] slvoi Vector of slaves output signals.
--! @param [in] mstoi Vector of masters output signals.
--! @param [out] slvio Signals of the selected slave accordingly with
--! the specified priority.
--! @param [out] mstio Signals of the selected master accordingly with
--! the specified priority.
--! @todo Round-robin priority algorithm.
component axictrl is
generic (
rdslave_with_waitstate : boolean := false
);
port (
clk : in std_logic;
nrst : in std_logic;
slvoi : in nasti_slaves_out_vector;
mstoi : in nasti_master_out_vector;
slvio : out nasti_slave_in_type;
mstio : out nasti_master_in_type
);
end component;
end; -- package declaration
--! Implementation of the declared sub-programs (functions and
--! procedures).
package body types_amba4 is
--! Read/write access state machines implementation.
--! @param [in] i Slave input signal passed from system bus.
--! @param [in] cfg Slave confguration descriptor defining memory base address.
--! @param [in] i_bank Bank of registers implemented by each slave device.
--! @param [out] o_bank Updated value for the slave bank of registers.
procedure procedureAxi4(
i : in nasti_slave_in_type;
cfg : in nasti_slave_config_type;
i_bank : in nasti_slave_bank_type;
o_bank : out nasti_slave_bank_type
) is
variable traddr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable twaddr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
begin
o_bank := i_bank;
-- Reading state machine:
case i_bank.rstate is
when rwait =>
if i.ar_valid = '1'
and ((i.ar_bits.addr(CFG_NASTI_ADDR_BITS-1 downto 12) and cfg.xmask) = cfg.xaddr) then
o_bank.rstate := rtrans;
traddr := (i.ar_bits.addr(CFG_NASTI_ADDR_BITS-1 downto 12) and (not cfg.xmask))
& i.ar_bits.addr(11 downto 0);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
o_bank.raddr(n) := traddr + n*CFG_ALIGN_BYTES;
end loop;
o_bank.rsize := XSizeToBytes(conv_integer(i.ar_bits.size));
o_bank.rburst := i.ar_bits.burst;
o_bank.rlen := conv_integer(i.ar_bits.len);
o_bank.rid := i.ar_id;
o_bank.rresp := NASTI_RESP_OKAY;
o_bank.ruser := i.ar_user;
--! No Wait States by default for reading operation.
--!
--! User can re-assign this value directly in module to implement
--! reading wait states.
--! Example: see axi2fse.vhd bridge implementation
o_bank.rwaitready := '1';
end if;
when rtrans =>
if i.r_ready = '1' and i_bank.rwaitready = '1' then
o_bank.rlen := i_bank.rlen - 1;
if i_bank.rburst = NASTI_BURST_INCR then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
o_bank.raddr(n) := i_bank.raddr(n) + i_bank.rsize;
end loop;
end if;
-- End of transaction:
if i_bank.rlen = 0 then
o_bank.rstate := rwait;
end if;
end if;
end case;
-- Writting state machine:
case i_bank.wstate is
when wwait =>
if i.aw_valid = '1'
and ((i.aw_bits.addr(CFG_NASTI_ADDR_BITS-1 downto 12) and cfg.xmask) = cfg.xaddr) then
o_bank.wstate := wtrans;
twaddr := (i.aw_bits.addr(CFG_NASTI_ADDR_BITS-1 downto 12) and (not cfg.xmask))
& i.aw_bits.addr(11 downto 0);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
o_bank.waddr(n) := twaddr + n*CFG_ALIGN_BYTES;
end loop;
o_bank.wsize := XSizeToBytes(conv_integer(i.aw_bits.size));
o_bank.wburst := i.aw_bits.burst;
o_bank.wlen := conv_integer(i.aw_bits.len);
o_bank.wid := i.aw_id;
o_bank.wresp := NASTI_RESP_OKAY;
o_bank.wuser := i.aw_user;
end if;
when wtrans =>
if i.w_valid = '1' then
o_bank.wlen := i_bank.wlen - 1;
if i_bank.wburst = NASTI_BURST_INCR then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
o_bank.waddr(n) := i_bank.waddr(n) + i_bank.wsize;
end loop;
end if;
-- End of transaction:
if i_bank.wlen = 0 then
o_bank.wstate := wwait;
o_bank.b_valid := '1';
end if;
end if;
end case;
if i.b_ready = '1' and i_bank.b_valid = '1' then
o_bank.b_valid := '0';
end if;
end; -- procedure
--! @brief Reordering elements of the address to provide 4-bytes memory access.
--! @param[in] mux Reordering control bits.
--! @param[in] iaddr Input addresses array.
--! @return Reordered addresses array.
function functionAddressReorder(
mux : std_logic_vector;
iaddr : global_addr_array_type)
return global_addr_array_type is
variable oaddr : global_addr_array_type;
begin
if CFG_NASTI_DATA_BITS = 128 then
if mux = "00" then
oaddr := iaddr;
elsif mux = "01" then
oaddr(0) := iaddr(3);
oaddr(1) := iaddr(0);
oaddr(2) := iaddr(1);
oaddr(3) := iaddr(2);
elsif mux = "10" then
oaddr(0) := iaddr(2);
oaddr(1) := iaddr(3);
oaddr(2) := iaddr(0);
oaddr(3) := iaddr(1);
else
oaddr(0) := iaddr(1);
oaddr(1) := iaddr(2);
oaddr(2) := iaddr(3);
oaddr(3) := iaddr(0);
end if;
end if;
return oaddr;
end;
--! @brief Reordering elements of the write transaction to provide 4-bytes memory access.
procedure procedureWriteReorder(
ena : in std_logic;
mux : in std_logic_vector(1 downto 0);
iwaddr : in global_addr_array_type;
iwstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
iwdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
owaddr : out global_addr_array_type;
owstrb : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
owdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)) is
begin
if CFG_NASTI_DATA_BITS = 128 and ena = '1' then
if mux = "00" then
owaddr := iwaddr;
owdata := iwdata;
owstrb := iwstrb;
elsif mux = "01" then
owaddr(0) := iwaddr(3);
owaddr(1) := iwaddr(0);
owaddr(2) := iwaddr(1);
owaddr(3) := iwaddr(2);
owdata(31 downto 0) := iwdata(127 downto 96);
owdata(127 downto 32) := iwdata(95 downto 0);
owstrb := iwstrb(11 downto 0) & iwstrb(15 downto 12);
elsif mux = "10" then
owaddr(0) := iwaddr(2);
owaddr(1) := iwaddr(3);
owaddr(2) := iwaddr(0);
owaddr(3) := iwaddr(1);
owdata(63 downto 0) := iwdata(127 downto 64);
owdata(127 downto 64) := iwdata(63 downto 0);
owstrb := iwstrb(7 downto 0) & iwstrb(15 downto 8);
else
owaddr(0) := iwaddr(1);
owaddr(1) := iwaddr(2);
owaddr(2) := iwaddr(3);
owaddr(3) := iwaddr(0);
owdata(95 downto 0) := iwdata(127 downto 32);
owdata(127 downto 96) := iwdata(31 downto 0);
owstrb := iwstrb(3 downto 0) & iwstrb(15 downto 4);
end if;
else
owaddr := (others => (others => '0'));
owdata := (others => '0');
owstrb := (others => '0');
end if;
end;
--! @brief Complementary to address data reordring.
--! @details This function restore data bus as there wasn't address reordering.
--! @param[in] mux Reordering control bits.
--! @param[in] idata Input data array.
--! @return Restored data array.
function functionDataRestoreOrder(
mux : std_logic_vector;
idata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0))
return std_logic_vector is
variable odata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
begin
if CFG_NASTI_DATA_BITS = 128 then
if mux = "00" then
odata := idata;
elsif mux = "01" then
odata(95 downto 0) := idata(127 downto 32);
odata(127 downto 96) := idata(31 downto 0);
elsif mux = "10" then
odata(63 downto 0) := idata(127 downto 64);
odata(127 downto 64) := idata(63 downto 0);
else
odata(31 downto 0) := idata(127 downto 96);
odata(127 downto 32) := idata(95 downto 0);
end if;
end if;
return odata;
end;
--! @brief Convert bank registers into output signals
--! @param[in] r Registers bank with the AXI4 state machines
--! implementaitons.
--! @param[in] rd_val Read value from the device's registers bank.
--! This value fully depends of device implementation.
--! @return NASTI output signals of the implemented slave device.
function functionAxi4Output(
r : nasti_slave_bank_type;
rd_val : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0))
return nasti_slave_out_type is
variable ret : nasti_slave_out_type;
begin
-- Read transfer:
if r.rstate = rwait then
ret.ar_ready := '1';
else
ret.ar_ready := '0';
end if;
ret.r_id := r.rid;
if r.rstate = rtrans and r.rlen = 0 then
ret.r_last := '1';
else
ret.r_last := '0';
end if;
ret.r_resp := r.rresp;
ret.r_user := r.ruser;
if r.rwaitready = '1' and r.rstate = rtrans then
ret.r_valid := '1';
else
ret.r_valid := '0';
end if;
ret.r_data := rd_val;
-- Write transfer:
if r.wstate = wwait then
ret.aw_ready := '1';
else
ret.aw_ready := '0';
end if;
if r.wstate = wtrans then
ret.w_ready := '1';
else
ret.w_ready := '0';
end if;
-- Write Handshaking:
ret.b_id := r.wid;
ret.b_resp := r.wresp;
ret.b_user := r.wuser;
ret.b_valid := r.b_valid;
return (ret);
end;
end; -- package body
| bsd-2-clause | 2456f8f0938f0f020a14dd6e30b0f81d | 0.636418 | 3.675097 | false | false | false | false |
BogdanArdelean/FPWAM | hardware/src/hdl/Memory.vhd | 1 | 3,406 | -------------------------------------------------------------------------------
-- FILE NAME : Memory.vhd
-- MODULE NAME : Memory
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : BRAM implementation of a memory unit with two ports.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Memory is
generic
(
kMemAddressWidth : natural := 16;
kWordWidth : natural := 18
);
port
(
clk : in std_logic;
addr_port_1 : in std_logic_vector(kMemAddressWidth -1 downto 0);
word_port_1_o : out std_logic_vector(kWordWidth -1 downto 0);
word_port_1_i : in std_logic_vector(kWordWidth -1 downto 0);
wr_port_1 : in std_logic;
rd_port_1 : in std_logic;
addr_port_2 : in std_logic_vector(kMemAddressWidth -1 downto 0);
word_port_2_o : out std_logic_vector(kWordWidth -1 downto 0);
word_port_2_i : in std_logic_vector(kWordWidth -1 downto 0);
wr_port_2 : in std_logic;
rd_port_2 : in std_logic
);
end Memory;
architecture Behavioral of Memory is
type mem is array (0 to 2**kMemAddressWidth) of std_logic_vector(kWordWidth - 1 downto 0);
signal BRAM : mem := (others => (others => '0'));
begin
PORT_1: process(clk)
begin
if rising_edge(clk) then
if rd_port_1 = '1' then
if wr_port_1 = '1' then
BRAM(to_integer(unsigned(addr_port_1))) <= word_port_1_i;
word_port_1_o <= word_port_1_i;
else
word_port_1_o <= BRAM(to_integer(unsigned(addr_port_1)));
end if;
end if;
end if;
end process;
PORT_2: process(clk)
begin
if rising_edge(clk) then
if rd_port_2 = '1' then
if wr_port_2 = '1' then
BRAM(to_integer(unsigned(addr_port_2))) <= word_port_2_i;
word_port_2_o <= word_port_2_i;
else
word_port_2_o <= BRAM(to_integer(unsigned(addr_port_2)));
end if;
end if;
end if;
end process;
end Behavioral;
architecture Simulation of Memory is
type mem is array (0 to 2**kMemAddressWidth) of std_logic_vector(kWordWidth - 1 downto 0);
signal BRAM : mem := (others => (others => '0'));
signal reg_addr1 : std_logic_vector(kMemAddressWidth -1 downto 0) := (others =>'0');
signal reg_addr2 : std_logic_vector(kMemAddressWidth -1 downto 0) := (others =>'0');
begin
word_port_1_o <= BRAM(to_integer(unsigned(reg_addr1)));
word_port_2_o <= BRAM(to_integer(unsigned(reg_addr2)));
WRITE: process(clk)
begin
if rising_edge(clk) then
if wr_port_1 = '1' then
BRAM(to_integer(unsigned(addr_port_1))) <= word_port_1_i;
end if;
if wr_port_2 = '1' then
BRAM(to_integer(unsigned(addr_port_2))) <= word_port_2_i;
end if;
end if;
end process;
READ: process(clk)
begin
if rising_edge(clk) then
if rd_port_1 = '1' then
reg_addr1 <= addr_port_1;
end if;
if rd_port_2 = '1' then
reg_addr2<= addr_port_2;
end if;
end if;
end process;
end Simulation;
| apache-2.0 | a22d3a476bbaa2e5e0a785b9e314fb86 | 0.550499 | 3.406 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/select_param.vhd | 4 | 37,910 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
------------------------------------------------------------------------------
-- Filename: select_param.vhd
-- Description: Selects correct parameter for addressed memory bank
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- KSB 07/14/08 version v4_00_a
-- ^^^^^^^^
-- 1. Added TPACC_* and timing parameter and new page access for reading page
-- mode flash
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
--use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_GLOBAL_SYNC_MEM -- At least one memory bank is synchronous
-- C_SYNCH_MEM_(0:3) -- Memory bank (0:3) type
-- C_MEM(0:3)_WIDTH -- Data width of memory banks (0:3)
-- C_SYNCH_PIPEDELAY_(0:3) -- Synchronous pipe delay of memory
-- -- banks (0:3)
-- C_GLOBAL_DATAWIDTH_MATCH -- Datawidth matching is supported for
-- at least one memory bank
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3)
-- -- Include datawidth matching for memory
-- C_PAGEMODE_FLASH -- Page Mode Flash is supported for
-- at least one memory bank
-- -- banks (0:3)
-- PARITY_TYPE_MEMORY -- Partity Type support any memory bank
-- C_PARITY_TYPE_(0:3) -- Parity type for each bank
--
-- TRDCNT_0 -- Read Cycle Count for Memory 0
-- TRDCNT_1 -- Read Cycle Count for Memory 1
-- TRDCNT_2 -- Read Cycle Count for Memory 2
-- TRDCNT_3 -- Read Cycle Count for Memory 3
--
-- THZCNT_0 -- Read End to Data High Impedance, Memory 0
-- THZCNT_1 -- Read End to Data High Impedance, Memory 1
-- THZCNT_2 -- Read End to Data High Impedance, Memory 2
-- THZCNT_3 -- Read End to Data High Impedance, Memory 3
--
-- TWRCNT_0 -- Write Cycle Count for Memory 0
-- TWRCNT_1 -- Write Cycle Count for Memory 1
-- TWRCNT_2 -- Write Cycle Count for Memory 2
-- TWRCNT_3 -- Write Cycle Count for Memory 3
--
-- TWPHCNT_0 -- Write Cycle High Count for Memory 0
-- TWPHCNT_1 -- Write Cycle High Count for Memory 1
-- TWPHCNT_2 -- Write Cycle High Count for Memory 2
-- TWPHCNT_3 -- Write Cycle High Count for Memory 3
--
--
-- TLZCNT_0 -- Write End to Data Low Impedance, Memory 0
-- TLZCNT_1 -- Write End to Data Low Impedance, Memory 1
-- TLZCNT_2 -- Write End to Data Low Impedance, Memory 2
-- TLZCNT_3 -- Write End to Data Low Impedance, Memory 3
--
-- TPACC_0 -- Page Access time , Memory 0
-- TPACC_1 -- Page Access time , Memory 1
-- TPACC_2 -- Page Access time , Memory 2
-- TPACC_3 -- Page Access time , Memory 3
--
-- TP_WR_REC_CNT_x -- Write recovery time for memory x, when Flash
-- memory is selected
-- Definition of Ports:
-- Bus2IP_Mem_CS -- Memory Channel Chip Select
-- Twr_data -- Write Cycle Time
-- Tlz_data -- Write Cycle Recovery Time
-- Trd_data -- Read Cycle Start Time
-- Thz_data -- Read Recovery Time
-- Parity_enable -- Parity is enabled or not
-- Parity_type -- Parity is either odd/Even
-- Synch_mem -- Synchronous Memory Control
-- Mem_width_bytes -- Memory Width in Bytes
-- Two_pipe_delay -- Synchronous Memory Pipeline Control
-- Datawidth_match -- Datawidth Matching Control
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity select_param is
generic (
C_NUM_BANKS_MEM : integer range 1 to 4 := 4;
C_GLOBAL_SYNC_MEM : integer range 0 to 1 := 0;
C_SYNCH_MEM_0 : integer range 0 to 1 := 0;
C_SYNCH_MEM_1 : integer range 0 to 1 := 0;
C_SYNCH_MEM_2 : integer range 0 to 1 := 0;
C_SYNCH_MEM_3 : integer range 0 to 1 := 0;
C_MEM0_WIDTH : integer := 64;
C_MEM1_WIDTH : integer := 64;
C_MEM2_WIDTH : integer := 64;
C_MEM3_WIDTH : integer := 64;
C_PAGEMODE_FLASH : integer range 0 to 1 := 1;
C_PAGEMODE_FLASH_0 : integer := 0;
C_PAGEMODE_FLASH_1 : integer := 0;
C_PAGEMODE_FLASH_2 : integer := 0;
C_PAGEMODE_FLASH_3 : integer := 0;
PARITY_TYPE_MEMORY : integer range 0 to 1 := 1;
C_PARITY_TYPE_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_3 : integer range 0 to 2 := 0;
C_IPIF_AWIDTH : integer := 32;
C_IPIF_DWIDTH : integer := 32;
C_SYNCH_PIPEDELAY_0 : integer range 1 to 2 := 2;
C_SYNCH_PIPEDELAY_1 : integer range 1 to 2 := 2;
C_SYNCH_PIPEDELAY_2 : integer range 1 to 2 := 2;
C_SYNCH_PIPEDELAY_3 : integer range 1 to 2 := 2;
C_GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1 := 1;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer := 1;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer := 1;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer := 1;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer := 1;
TRDCNT_0 : std_logic_vector(0 to 4);
TRDCNT_1 : std_logic_vector(0 to 4);
TRDCNT_2 : std_logic_vector(0 to 4);
TRDCNT_3 : std_logic_vector(0 to 4);
THZCNT_0 : std_logic_vector(0 to 4);
THZCNT_1 : std_logic_vector(0 to 4);
THZCNT_2 : std_logic_vector(0 to 4);
THZCNT_3 : std_logic_vector(0 to 4);
TWRCNT_0 : std_logic_vector(0 to 4);
TWRCNT_1 : std_logic_vector(0 to 4);
TWRCNT_2 : std_logic_vector(0 to 4);
TWRCNT_3 : std_logic_vector(0 to 4);
TWPHCNT_0 : std_logic_vector(0 to 4);
TWPHCNT_1 : std_logic_vector(0 to 4);
TWPHCNT_2 : std_logic_vector(0 to 4);
TWPHCNT_3 : std_logic_vector(0 to 4);
TPACC_0 : std_logic_vector(0 to 4);
TPACC_1 : std_logic_vector(0 to 4);
TPACC_2 : std_logic_vector(0 to 4);
TPACC_3 : std_logic_vector(0 to 4);
TLZCNT_0 : std_logic_vector(0 to 4);
TLZCNT_1 : std_logic_vector(0 to 4);
TLZCNT_2 : std_logic_vector(0 to 4);
TLZCNT_3 : std_logic_vector(0 to 4);
-- --
TP_WR_REC_CNT_0 : std_logic_vector(0 to 15);
TP_WR_REC_CNT_1 : std_logic_vector(0 to 15);
TP_WR_REC_CNT_2 : std_logic_vector(0 to 15);
TP_WR_REC_CNT_3 : std_logic_vector(0 to 15)
-- --
);
port (
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_RNW : in std_logic;
New_page_access : out std_logic;
Parity_enable : out std_logic;
Parity_type : out std_logic;
psram_page_mode : in std_logic;
Twr_data : out std_logic_vector(0 to 4);
Twph_data : out std_logic_vector(0 to 4);
Tlz_data : out std_logic_vector(0 to 4);
Trd_data : out std_logic_vector(0 to 4);
Thz_data : out std_logic_vector(0 to 4);
Tpacc_data : out std_logic_vector(0 to 4);
Twr_rec_data : out std_logic_vector(0 to 15);--9/6/2011
Synch_mem : out std_logic;
Mem_width_bytes : out std_logic_vector(0 to 3);
Two_pipe_delay : out std_logic;
Datawidth_match : out std_logic
);
end entity select_param;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of select_param is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declaration
-------------------------------------------------------------------------------
type SYNCH_ARRAY_TYPE is array (0 to 3) of integer;
constant SYNCH_MEM_ARRAY : SYNCH_ARRAY_TYPE :=
(
C_SYNCH_MEM_0,
C_SYNCH_MEM_1,
C_SYNCH_MEM_2,
C_SYNCH_MEM_3
);
type MEM_WIDTH_ARRAY_TYPE is array (0 to 3) of integer range 0 to 64;
constant MEM_WIDTH_ARRAY : MEM_WIDTH_ARRAY_TYPE :=
(
C_MEM0_WIDTH,
C_MEM1_WIDTH,
C_MEM2_WIDTH,
C_MEM3_WIDTH
);
type PIPE_DELAY_ARRAY_TYPE is array (0 to 3) of integer range 1 to 2;
constant PIPE_DELAY_ARRAY : PIPE_DELAY_ARRAY_TYPE :=
(
C_SYNCH_PIPEDELAY_0,
C_SYNCH_PIPEDELAY_1,
C_SYNCH_PIPEDELAY_2,
C_SYNCH_PIPEDELAY_3
);
type DATAWIDTH_MATCH_ARRAY_TYPE is array (0 to 3) of integer range 0 to 1;
constant DATAWIDTH_MATCH_ARRAY : DATAWIDTH_MATCH_ARRAY_TYPE :=
(
C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3
);
type TIME_ARRAY_TYPE is array (0 to 3) of std_logic_vector(0 to 4);
constant TWR_CNTR_ARRAY : TIME_ARRAY_TYPE :=
(
TWRCNT_0,
TWRCNT_1,
TWRCNT_2,
TWRCNT_3
);
constant TWPH_CNTR_ARRAY : TIME_ARRAY_TYPE :=
(
TWPHCNT_0,
TWPHCNT_1,
TWPHCNT_2,
TWPHCNT_3
);
constant TRD_CNTR_ARRAY : TIME_ARRAY_TYPE :=
(
TRDCNT_0,
TRDCNT_1,
TRDCNT_2,
TRDCNT_3
);
constant THZ_CNTR_ARRAY : TIME_ARRAY_TYPE :=
(
THZCNT_0,
THZCNT_1,
THZCNT_2,
THZCNT_3
);
constant TLZ_CNTR_ARRAY : TIME_ARRAY_TYPE :=
(
TLZCNT_0,
TLZCNT_1,
TLZCNT_2,
TLZCNT_3
);
constant TPACC_CNTR_ARRAY : TIME_ARRAY_TYPE :=
(
TPACC_0,
TPACC_1,
TPACC_2,
TPACC_3
);
type TIME_ARRAY_TYPE_1 is array (0 to 3) of std_logic_vector(0 to 15);
constant TWR_REC_ARRAY : TIME_ARRAY_TYPE_1 :=
(
TP_WR_REC_CNT_0,
TP_WR_REC_CNT_1,
TP_WR_REC_CNT_2,
TP_WR_REC_CNT_3
);
type TYPE_PAGE_MODE_TYPE is array (0 to 3) of integer range 0 to 1;
constant PAGE_MODE_ARRAY : TYPE_PAGE_MODE_TYPE :=
(
C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3
);
type MEMORY_PARITY_TYPE_ARRAY is array (0 to 3) of integer range 0 to 2;
constant MEM_PARITY_TYPE_ARRAY : MEMORY_PARITY_TYPE_ARRAY :=
(
C_PARITY_TYPE_0,
C_PARITY_TYPE_1,
C_PARITY_TYPE_2,
C_PARITY_TYPE_3
);
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
function calc_page_boundary (C_IPIF_DWIDTH : integer) return integer is
begin
if(C_IPIF_DWIDTH = 32)then
return log2(C_IPIF_DWIDTH/2);
else
return log2(C_IPIF_DWIDTH/4);
end if;
end function calc_page_boundary;
signal mem_width : integer range 0 to 64;
signal ADDR_REG_0 : std_logic_vector(0 to 31);
signal page_mode_enable : std_logic;
-- address offset
constant ADDR_PAGE_OFFSET : integer range 0 to 5
:=calc_page_boundary(C_IPIF_DWIDTH); -- log2(C_IPIF_DWIDTH/2);
type ADDR_TYPE is array (0 to 3) of std_logic_vector(0 to C_IPIF_AWIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- SINGLE_BANK_GEN is used when the number of banks is 1
---------------------------------------------------------------------------
SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
-----------------------------------------------------------------------
-- Synch_mem indicates that current memory bank is synchronous
-----------------------------------------------------------------------
SYNC_MEM_GEN_SING: if SYNCH_MEM_ARRAY(0) = 1 generate
begin
Synch_mem <= '1';
end generate SYNC_MEM_GEN_SING;
-----------------------------------------------------------------------
-- Register the address coming from IPIF in case C_NUM_BANKS_MEM = 1
-----------------------------------------------------------------------
NEW_BANK_GEN_SING: if (PAGE_MODE_ARRAY(0) = 1) generate
begin
ADR_STORE_PROCESS_SING:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if Bus2IP_Reset = '1' then
ADDR_REG_0 <= (others=>'0');
elsif (Bus2IP_RNW = '1' and Bus2IP_Mem_CS(0)='1' and
psram_page_mode = '1') then
ADDR_REG_0 <= Bus2IP_Addr;
elsif Bus2IP_Mem_CS(0)='0'then
ADDR_REG_0 <= (others=>'0');
end if;
end if;
end process ADR_STORE_PROCESS_SING;
-----------------------------------------------------------------------
-- NEW BANK Access Detector generation in case C_PAGEMODE_FLASH = 1
-----------------------------------------------------------------------
new_page_access <= '1'when ((ADDR_REG_0(0 to
C_IPIF_AWIDTH-ADDR_PAGE_OFFSET-1))
/= (Bus2IP_Addr(0 to C_IPIF_AWIDTH-ADDR_PAGE_OFFSET-1))
and (Bus2IP_RNW = '1' and Bus2IP_Mem_CS(0)='1')) else
'0';
end generate NEW_BANK_GEN_SING;
-----------------------------------------------------------------------
-- Check The parity logic for C_NUM_BANKS_MEM = 1
-----------------------------------------------------------------------
BANK0_NO_PARITY_GEN: if (MEM_PARITY_TYPE_ARRAY(0) = 0) generate
begin
Parity_enable <= '0';
Parity_type <= '0';
end generate BANK0_NO_PARITY_GEN;
BANK0_PARITY_GEN: if (MEM_PARITY_TYPE_ARRAY(0) /= 0) generate
begin
Parity_enable <= '1';
Parity_type <= '1' when MEM_PARITY_TYPE_ARRAY(0) = 1 else '0';
end generate BANK0_PARITY_GEN;
-----------------------------------------------------------------------
-- new_page_access is always zero in case C_NUM_BANKS_MEM = 1
-----------------------------------------------------------------------
NO_NEW_BANK_GEN_SING: if (PAGE_MODE_ARRAY(0) = 0) generate
begin
ADDR_REG_0 <= (others=>'0');
new_page_access <= '1';
end generate NO_NEW_BANK_GEN_SING;
-----------------------------------------------------------------------
-- If current memory bank is asynchronous, Synch_mem is 0
-----------------------------------------------------------------------
ASYNC_MEM_GEN: if SYNCH_MEM_ARRAY(0) = 0 generate
begin
Synch_mem <= '0';
end generate ASYNC_MEM_GEN;
-----------------------------------------------------------------------
-- The pipe delay for the synchronous memory used is 1
-----------------------------------------------------------------------
ONE_PIPEDELAY_GEN: if PIPE_DELAY_ARRAY(0) = 1 generate
begin
Two_pipe_delay <= '0';
end generate ONE_PIPEDELAY_GEN;
-----------------------------------------------------------------------
-- The pipe delay for the synchronous memory used is 2
-----------------------------------------------------------------------
TWO_PIPEDELAY_GEN: if PIPE_DELAY_ARRAY(0) = 2 generate
begin
Two_pipe_delay <= '1';
end generate TWO_PIPEDELAY_GEN;
-----------------------------------------------------------------------
-- The datawidth_match signal=1 indicates that the memory width is not
-- equal to the opb/mch data width
-----------------------------------------------------------------------
DWIDTH_MATCH_GEN: if DATAWIDTH_MATCH_ARRAY(0) = 1 generate
begin
Datawidth_match <= '1';
end generate DWIDTH_MATCH_GEN;
-----------------------------------------------------------------------
-- The datawidth_match signal=0 indicates that the memory width is
-- equal to the opb/mch data width
-----------------------------------------------------------------------
DWIDTH_NOMATCH_GEN: if DATAWIDTH_MATCH_ARRAY(0) = 0 generate
begin
Datawidth_match <= '0';
end generate DWIDTH_NOMATCH_GEN;
Mem_width_bytes <= std_logic_vector
(conv_unsigned(MEM_WIDTH_ARRAY(0)/8,4));
-----------------------------------------------------------------------
-- Timing signals generation
-----------------------------------------------------------------------
Twr_data <= TWR_CNTR_ARRAY(0);
Twph_data <= TWPH_CNTR_ARRAY(0);
Tlz_data <= TLZ_CNTR_ARRAY(0);
Trd_data <= TRD_CNTR_ARRAY(0);
Thz_data <= THZ_CNTR_ARRAY(0);
Tpacc_data <= TPACC_CNTR_ARRAY(0);
Twr_rec_data <= TWR_REC_ARRAY(0);--9/6/2011
end generate SINGLE_BANK_GEN;
---------------------------------------------------------------------------
-- end of generate SINGLE_BANK_GEN
---------------------------------------------------------------------------
MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
---------------------------------------------------------------------------
-- MULTI_BANK_GEN is used when the number of banks is greater than 1
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- C_GLOBAL_SYNC_MEM = 1
---------------------------------------------------------------------------
SYNC_MEM_GEN_MULTI: if C_GLOBAL_SYNC_MEM = 1 generate
begin
-----------------------------------------------------------------------
-- This process is used to generate Synch_mem signal.
-----------------------------------------------------------------------
SYNCH_PROCESS: process (Bus2IP_Mem_CS) is
begin
Synch_mem <= '0';-- '0'; -- 1/3/2013
for i in 0 to C_NUM_BANKS_MEM-1 loop
if Bus2IP_Mem_CS(i) = '1' then
-- if (or_reduce(Bus2IP_Mem_CS) = '1') then
if SYNCH_MEM_ARRAY(i) = 1 then
Synch_mem <= '1';
elsif SYNCH_MEM_ARRAY(i) = 0 then
Synch_mem <= '0';
end if;
end if;
end loop;
end process SYNCH_PROCESS;
-----------------------------------------------------------------------
-- This process is used to generate Two_pipe_dalay signal.
-----------------------------------------------------------------------
SELECT_PIPEDELAY_PROCESS: process(Bus2IP_Mem_CS) is
begin
Two_pipe_delay <= '1';
for i in 0 to C_NUM_BANKS_MEM-1 loop
if Bus2IP_Mem_CS(i) = '1' then
-- if (or_reduce(Bus2IP_Mem_CS) = '1') then
if PIPE_DELAY_ARRAY(i) = 1 then
Two_pipe_delay <= '0';
else
Two_pipe_delay <= '1';
end if;
end if;
end loop;
end process SELECT_PIPEDELAY_PROCESS;
end generate SYNC_MEM_GEN_MULTI;
-----------------------------------------------------------------------
-- Register the address coming from IPIF in case C_NUM_BANKS_MEM > 1
-----------------------------------------------------------------------
NEW_BANK_GEN_MULI: if (C_PAGEMODE_FLASH = 1) generate
begin
PAGE_MODE: process (Bus2IP_Mem_CS,Bus2IP_RNW,psram_page_mode) is
begin
page_mode_enable <= '0';
for i in 0 to C_NUM_BANKS_MEM-1 loop
if (Bus2IP_RNW = '1' and or_reduce(Bus2IP_Mem_CS) = '1' and
psram_page_mode = '1') then
if PAGE_MODE_ARRAY(i) = 1 then
page_mode_enable <= '1';
end if;
else
page_mode_enable <= '0';
end if;
end loop;
end process PAGE_MODE;
ADR_STORE_PROCESS_MULT:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if Bus2IP_Reset = '1' then
ADDR_REG_0 <= (others=>'0');
elsif (page_mode_enable = '1') then
ADDR_REG_0 <= Bus2IP_Addr;
else
ADDR_REG_0 <= (others=>'0');
end if;
end if;
end process ADR_STORE_PROCESS_MULT;
new_page_access <= '1'when ((ADDR_REG_0(0 to
C_IPIF_AWIDTH-ADDR_PAGE_OFFSET-1))
/= (Bus2IP_Addr(0 to C_IPIF_AWIDTH-ADDR_PAGE_OFFSET-1))
and (page_mode_enable='1' or psram_page_mode = '0'))
else '0';
end generate NEW_BANK_GEN_MULI;
-----------------------------------------------------------------------
-- new_page_access is always zero in case C_NUM_BANKS_MEM = 1
-----------------------------------------------------------------------
NO_NEW_BANK_GEN_MULT: if (C_PAGEMODE_FLASH = 0) generate
begin
new_page_access <= '1';
end generate NO_NEW_BANK_GEN_MULT;
-----------------------------------------------------------------------
-- Check The parity logic for C_NUM_BANKS_MEM > 1
-----------------------------------------------------------------------
MEM_NO_PARITY_GEN: if (PARITY_TYPE_MEMORY = 0) generate
begin
Parity_enable <= '0';
Parity_type <= '0';
end generate MEM_NO_PARITY_GEN;
MEM_PARITY_GEN: if (PARITY_TYPE_MEMORY /= 0) generate
begin
PARITY_GEN_PROCESS: process(Bus2IP_Mem_CS) is
begin
Parity_type <= '0';
Parity_enable <= '0';
for i in 0 to C_NUM_BANKS_MEM-1 loop
if Bus2IP_Mem_CS(i) = '1' then
if MEM_PARITY_TYPE_ARRAY(i)/=0 then
Parity_enable <= '1';
end if;
if MEM_PARITY_TYPE_ARRAY(i)=1 then
Parity_type <= '1';
end if;
end if;
end loop;
end process PARITY_GEN_PROCESS;
end generate MEM_PARITY_GEN;
---------------------------------------------------------------------------
---------------------------- Asynchronous memories ------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
---------------------------------------------------------------------------
NO_SYNC_MEM_GEN: if C_GLOBAL_SYNC_MEM=0 generate
begin
Synch_mem <= '0';
Two_pipe_delay <= '0';
end generate NO_SYNC_MEM_GEN;
---------------------------------------------------------------------------
------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 --------------------------
---------------------------------------------------------------------------
DATAWIDTH_MATCH_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
---------------------------------------------------------------------------
-- This process is used to generate mem_width signal.
---------------------------------------------------------------------------
SELECT_MEM_WIDTH_PROCESS: process(Bus2IP_Mem_CS) is
begin
mem_width <= 0;
for i in 0 to C_NUM_BANKS_MEM-1 loop
if Bus2IP_Mem_CS(i) = '1' then
mem_width <= MEM_WIDTH_ARRAY(i);
end if;
end loop;
end process SELECT_MEM_WIDTH_PROCESS;
---------------------------------------------------------------------------
-- This process is used to generate mem_width signal.
-- This process is done in real time and is included to prevent
-- implementation of the /8 function
---------------------------------------------------------------------------
SELECT_MEM_WIDTH_BYTES_PROCESS: process(mem_width) is
begin
Mem_width_bytes <= (others => '0');
case mem_width is
when 8 =>
Mem_width_bytes <= "0001"; -- 1 Byte data width
when 16 =>
Mem_width_bytes <= "0010"; -- 2 Byte data width
when 32 =>
Mem_width_bytes <= "0100"; -- 4 Byte data width
when 64 =>
Mem_width_bytes <= "1000"; -- 8 Byte data width
when others =>
Mem_width_bytes <= (others => '0');
end case;
end process SELECT_MEM_WIDTH_BYTES_PROCESS;
---------------------------------------------------------------------------
-- This process is used to generate Datawidth_match signal.
---------------------------------------------------------------------------
SELECT_DATAWIDTH_MATCH_PROCESS: process(Bus2IP_Mem_CS) is
begin
Datawidth_match <= '0';
for i in 0 to C_NUM_BANKS_MEM-1 loop
if Bus2IP_Mem_CS(i) = '1' then
if DATAWIDTH_MATCH_ARRAY(i) = 1 then
Datawidth_match <= '1';
end if;
end if;
end loop;
end process SELECT_DATAWIDTH_MATCH_PROCESS;
end generate DATAWIDTH_MATCH_GEN;
---------------------------------------------------------------------------
---------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 -----------------------
---------------------------------------------------------------------------
NO_DATAWIDTH_MATCH_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
Mem_width_bytes <= std_logic_vector
(conv_unsigned(MEM_WIDTH_ARRAY(0)/8,4));
Datawidth_match <= '0';
end generate NO_DATAWIDTH_MATCH_GEN;
---------------------------------------------------------------------------
-- This process is used to generate timing signals.
---------------------------------------------------------------------------
SELECT_CNTR_PROCESS: process(Bus2IP_Mem_CS) is
begin
Twr_data <= (others => '0');
Twph_data <= (others => '0');
Tlz_data <= (others => '0');
Trd_data <= (others => '0');
Thz_data <= (others => '0');
Tpacc_data <= (others => '0');
Twr_rec_data <= (others => '0');--
for i in 0 to C_NUM_BANKS_MEM-1 loop
if Bus2IP_Mem_CS(i) = '1' then
Twr_data <= TWR_CNTR_ARRAY(i);
Twph_data <= TWPH_CNTR_ARRAY(i);
Tlz_data <= TLZ_CNTR_ARRAY(i);
Trd_data <= TRD_CNTR_ARRAY(i);
Thz_data <= THZ_CNTR_ARRAY(i);
Tpacc_data <= TPACC_CNTR_ARRAY(i);
Twr_rec_data <= TWR_REC_ARRAY(i);-- 9/6/2011
end if;
end loop;
end process SELECT_CNTR_PROCESS;
end generate MULTI_BANK_GEN;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File select_param.vhd
-------------------------------------------------------------------------------
| gpl-3.0 | fdaa0bbc89a1ea14aa441bb58047a2b0 | 0.413427 | 4.751817 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_tx_fixed.vhd | 4 | 17,460 | -----------------------------------------------------------------------
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-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
| gpl-3.0 | 8e67cf9d646c563b263c16f3b5631273 | 0.413116 | 3.938642 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/parityenable.vhd | 4 | 6,289 | -------------------------------------------------------------------------------
-- parityenable.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity ParityEnable is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 4
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic
);
end entity ParityEnable;
architecture IMP of ParityEnable is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
signal inA5 : std_logic_vector(0 to 4);
begin
Assign_InA : process (InA) is
begin
inA5 <= (others => '0');
inA5(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699600000000")
port map(
O => Res,
I0 => InA5(4),
I1 => inA5(3),
I2 => inA5(2),
I3 => inA5(1),
I4 => inA5(0),
I5 => Enable);
end generate Single_LUT6;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= Enable and ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
| gpl-3.0 | b7f8134db2b269a6bea3fa5a50475af7 | 0.535379 | 4.547361 | false | false | false | false |
hoangt/PoC | tb/arith/arith_counter_bcd_tb.vhdl | 2 | 3,800 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: arith_counter_bcd_tb
--
-- Authors: Martin Zabel
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.utils.all;
use poc.simulation.all;
entity arith_counter_bcd_tb is
end arith_counter_bcd_tb;
architecture rtl of arith_counter_bcd_tb is
constant DIGITS : positive := 4;
signal clk : std_logic;
signal rst : std_logic;
signal inc : std_logic;
signal val : T_BCD_VECTOR(DIGITS-1 downto 0);
constant clk_period : time := 10 ns;
begin
DUT: entity poc.arith_counter_bcd
generic map (
DIGITS => DIGITS)
port map (
clk => clk,
rst => rst,
inc => inc,
val => val);
process
procedure cycle is -- inspired by Thomas B. Preusser
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end cycle;
begin
-- initial half cycle so that rising edges are at multiples of clk_period
clk <= '1'; wait for clk_period/2;
rst <= '1';
inc <= '0';
cycle;
tbAssert(val = (x"0", x"0", x"0", x"0"), "Wrong initial state.");
rst <= '1';
inc <= '1';
cycle;
tbAssert(val = (x"0", x"0", x"0", x"0"), "Wrong initial state.");
-- d3..d0 denote the new counter state after increment
rst <= '0';
for d3 in 0 to 9 loop
for d2 in 0 to 9 loop
for d1 in 0 to 9 loop
for d0 in 0 to 9 loop
if d3 /= 0 or d2 /= 0 or d1 /= 0 or d0 /= 0 then
--increment
inc <= '1';
cycle;
tbAssert(val = (t_BCD(to_unsigned(d3,4)),
t_BCD(to_unsigned(d2,4)),
t_BCD(to_unsigned(d1,4)),
t_BCD(to_unsigned(d0,4))),
"Must be incremented to state "&
integer'image(d3)&
integer'image(d2)&
integer'image(d1)&
integer'image(d0)&".");
end if;
-- keep state
inc <= '0';
cycle;
tbAssert(val = (t_BCD(to_unsigned(d3,4)),
t_BCD(to_unsigned(d2,4)),
t_BCD(to_unsigned(d1,4)),
t_BCD(to_unsigned(d0,4))),
"Must keep in state "&
integer'image(d3)&
integer'image(d2)&
integer'image(d1)&
integer'image(d0)&".");
end loop;
end loop;
end loop;
end loop;
inc <= '1';
cycle;
tbAssert(val = (x"0", x"0", x"0", x"0"), "Should be wrapped to 0000.");
inc <= '1';
cycle;
inc <= '1';
cycle;
inc <= '1';
cycle;
inc <= '1';
rst <= '1';
cycle;
tbAssert(val = (x"0", x"0", x"0", x"0"), "Should be resetted again.");
tbPrintResult;
wait;
end process;
end rtl;
| apache-2.0 | c4111792f99b0ffb002256ed09ca7af8 | 0.545263 | 3.267412 | false | false | false | false |
hoangt/PoC | src/mem/ocram/ocram_tdp.vhdl | 2 | 7,873 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: True dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating true dual-port memory, with:
--
-- * dual clock, clock enable,
-- * 2 read/write ports.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- * Same-Port Read-During Write:
-- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1')
-- is directly passed to the output "q1". This is also known as write-first
-- mode or read-through write behavior. Same applies for port 2 (d2 -> q2).
--
-- * Mixed-Port Read-During Write:
-- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix
-- and Stratix II FPGAs) defines the minimum time after which the written data
-- at one port can be read-out at the other again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d1" written at the rising-edge of "clk1" at address
-- "a1" can be read-out at the 2nd port from the same address with the
-- 2nd rising-edge of "clk2" following the falling-edge of "clk1".
-- If the rising-edge of "clk2" coincides with the falling-edge of "clk1"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "clk2" in this timing. Same applies analogous to data written at port 2
-- and read-out at port 1.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_tdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
we2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
d2 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_tdp;
architecture rtl of ocram_tdp is
constant DEPTH : positive := 2**A_BITS;
begin
gXilinx: if DEVICE = DEVICE_SPARTAN6 or DEVICE = DEVICE_VIRTEX6 or
DEVICE=DEVICE_ARTIX7 or DEVICE=DEVICE_KINTEX7 or DEVICE=DEVICE_VIRTEX7
generate
-- RAM can be inferred correctly only for newer FPGAs!
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1, clk2)
begin -- process
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
if rising_edge(clk2) then
if ce2 = '1' then
if we2 = '1' then
ram(to_integer(a2)) <= d2;
end if;
a2_reg <= a2;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- returns new data
q2 <= ram(to_integer(a2_reg)); -- returns new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1, clk2)
begin -- process
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
if rising_edge(clk2) then
if ce2 = '1' then
if we2 = '1' then
ram(to_integer(a2)) <= d2;
end if;
a2_reg <= a2;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- returns new data
q2 <= ram(to_integer(a2_reg)); -- returns new data
end generate;
end generate gXilinx;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_tdp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
we2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
d2 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_tdp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk1 => clk1,
clk2 => clk2,
ce1 => ce1,
ce2 => ce2,
we1 => we1,
we2 => we2,
a1 => a1,
a2 => a2,
d1 => d1,
d2 => d2,
q1 => q1,
q2 => q2
);
end generate gAltera;
assert VENDOR = VENDOR_ALTERA or
DEVICE = DEVICE_SPARTAN6 or DEVICE = DEVICE_VIRTEX6 or
DEVICE = DEVICE_ARTIX7 or DEVICE = DEVICE_KINTEX7 or DEVICE = DEVICE_VIRTEX7
report "Device not yet supported."
severity failure;
end rtl;
| apache-2.0 | c2d433a5413151345b7410079079b188 | 0.62238 | 3.046827 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/tx_intrfce.vhd | 4 | 13,100 | -------------------------------------------------------------------------------
-- tx_intrfce - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : tx_intrfce.vhd
-- Version : v2.0
-- Description : This is the ethernet transmit interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
library lib_fifo_v1_0;
--library fifo_generator_v11_0; --FIFO Hier
--use fifo_generator_v11_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_tx_clk -- PHY TX Clock
-- Emac_tx_wr_data -- Ethernet transmit data
-- Tx_er -- Transmit error
-- Phy_tx_en -- Ethernet transmit enable
-- Tx_en -- Transmit enable
-- Emac_tx_wr -- TX FIFO write enable
-- Fifo_empty -- TX FIFO empty
-- Fifo_almost_emp -- TX FIFP almost empty
-- Fifo_full -- TX FIFO full
-- Phy_tx_data -- Ethernet transmit data
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity tx_intrfce is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Emac_tx_wr_data : in std_logic_vector (0 to 3);
Tx_er : in std_logic;
PhyTxEn : in std_logic;
Tx_en : in std_logic;
Emac_tx_wr : in std_logic;
Fifo_empty : out std_logic;
Fifo_full : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 5)
);
end tx_intrfce;
architecture implementation of tx_intrfce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal bus_combo : std_logic_vector (0 to 5);
signal fifo_empty_i : std_logic;
signal fifo_empty_c : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
-------------------------------------------------------------------------------
component FDR
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
--FIFO HIER
--component async_fifo_eth
-- port (
-- rst : in std_logic;
-- wr_clk : in std_logic;
-- rd_clk : in std_logic;
-- din : in std_logic_vector(5 downto 0);
-- wr_en : in std_logic;
-- rd_en : in std_logic;
-- dout : out std_logic_vector(5 downto 0);
-- full : out std_logic;
-- empty : out std_logic;
-- valid : out std_logic
-- );
--end component;
begin
I_TX_FIFO: entity lib_fifo_v1_0.async_fifo_fg
generic map(
C_ALLOW_2N_DEPTH => 0, -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY, -- new for FIFO Gen
C_DATA_WIDTH => 6,
C_ENABLE_RLOCS => 0, -- not supported in FG
C_FIFO_DEPTH => 15,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 2,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0, -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 2,
C_WR_ERR_LOW => 0
)
port map(
Din => bus_combo,
Wr_en => Emac_tx_wr,
Wr_clk => Clk,
Rd_en => Tx_en,
Rd_clk => Phy_tx_clk,
Ainit => Rst,
Dout => Phy_tx_data,
Full => Fifo_full,
Empty => fifo_empty_i,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => open,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
-- I_TX_FIFO : async_fifo_eth
-- port map(
-- din => bus_combo,
-- wr_en => Emac_tx_wr,
-- wr_clk => Clk,
-- rd_en => Tx_en,
-- rd_clk => Phy_tx_clk,
-- rst => Rst,
-- dout => Phy_tx_data,
-- full => Fifo_full,
-- empty => fifo_empty_i,
-- valid => open
-- );
pipeIt: FDR
port map
(
Q => Fifo_empty, --[out]
C => Clk, --[in]
D => fifo_empty_c, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
CDC_FIFO_EMPTY: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 3
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => fifo_empty_i,
prmry_ack => open,
scndry_out => fifo_empty_c,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
bus_combo <= (Emac_tx_wr_data & Tx_er & PhyTxEn);
end implementation;
| gpl-3.0 | 1a2dd066b3374dc72c91d50176b18a69 | 0.381832 | 4.60943 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/hdl/design_1.vhd | 1 | 275,844 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Thu Nov 19 17:38:29 2015
--Host : ALI-WORKSTATION running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1R706YB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1R706YB;
architecture STRUCTURE of m00_couplers_imp_1R706YB is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= m00_couplers_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= m00_couplers_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= m00_couplers_to_m00_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= m00_couplers_to_m00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= m00_couplers_to_m00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= m00_couplers_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= m00_couplers_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= m00_couplers_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= m00_couplers_to_m00_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= m00_couplers_to_m00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= m00_couplers_to_m00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= m00_couplers_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= m00_couplers_to_m00_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bid(0) <= m00_couplers_to_m00_couplers_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rid(0) <= m00_couplers_to_m00_couplers_RID(0);
S_AXI_rlast(0) <= m00_couplers_to_m00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_m00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_m00_couplers_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_m00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_m00_couplers_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_m00_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_m00_couplers_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_m00_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_m00_couplers_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BID(0) <= M_AXI_bid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RID(0) <= M_AXI_rid(0);
m00_couplers_to_m00_couplers_RLAST(0) <= M_AXI_rlast(0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WLAST(0) <= S_AXI_wlast(0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_8RVYHO is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_8RVYHO;
architecture STRUCTURE of m00_couplers_imp_8RVYHO is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(8 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1UTB3Y5 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1UTB3Y5;
architecture STRUCTURE of m01_couplers_imp_1UTB3Y5 is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(3 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(3 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_7ANRHB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_7ANRHB;
architecture STRUCTURE of m02_couplers_imp_7ANRHB is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(12 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(12 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(12 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(12 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(12 downto 0) <= S_AXI_araddr(12 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(12 downto 0) <= S_AXI_awaddr(12 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1W07O72 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1W07O72;
architecture STRUCTURE of m03_couplers_imp_1W07O72 is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(4 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(4 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(4 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(4 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(4 downto 0) <= S_AXI_araddr(4 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(4 downto 0) <= S_AXI_awaddr(4 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_local_memory_imp_1K0VQXK is
port (
DLMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_addrstrobe : in STD_LOGIC;
DLMB_be : in STD_LOGIC_VECTOR ( 0 to 3 );
DLMB_ce : out STD_LOGIC;
DLMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_readstrobe : in STD_LOGIC;
DLMB_ready : out STD_LOGIC;
DLMB_ue : out STD_LOGIC;
DLMB_wait : out STD_LOGIC;
DLMB_writedbus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_writestrobe : in STD_LOGIC;
ILMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_addrstrobe : in STD_LOGIC;
ILMB_ce : out STD_LOGIC;
ILMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_readstrobe : in STD_LOGIC;
ILMB_ready : out STD_LOGIC;
ILMB_ue : out STD_LOGIC;
ILMB_wait : out STD_LOGIC;
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end microblaze_0_local_memory_imp_1K0VQXK;
architecture STRUCTURE of microblaze_0_local_memory_imp_1K0VQXK is
component design_1_dlmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component design_1_dlmb_v10_0;
component design_1_ilmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component design_1_ilmb_v10_0;
component design_1_dlmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component design_1_dlmb_bram_if_cntlr_0;
component design_1_ilmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component design_1_ilmb_bram_if_cntlr_0;
component design_1_lmb_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_lmb_bram_0;
signal GND_1 : STD_LOGIC;
signal SYS_Rst_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_dlmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_CE : STD_LOGIC;
signal microblaze_0_dlmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_READY : STD_LOGIC;
signal microblaze_0_dlmb_UE : STD_LOGIC;
signal microblaze_0_dlmb_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_bus_CE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READY : STD_LOGIC;
signal microblaze_0_dlmb_bus_UE : STD_LOGIC;
signal microblaze_0_dlmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_dlmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_CE : STD_LOGIC;
signal microblaze_0_ilmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_READY : STD_LOGIC;
signal microblaze_0_ilmb_UE : STD_LOGIC;
signal microblaze_0_ilmb_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_bus_CE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READY : STD_LOGIC;
signal microblaze_0_ilmb_bus_UE : STD_LOGIC;
signal microblaze_0_ilmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_ilmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_dlmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x0 32 > design_1 microblaze_0_local_memory/lmb_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr : label is "yes";
begin
DLMB_ce <= microblaze_0_dlmb_CE;
DLMB_readdbus(0 to 31) <= microblaze_0_dlmb_READDBUS(0 to 31);
DLMB_ready <= microblaze_0_dlmb_READY;
DLMB_ue <= microblaze_0_dlmb_UE;
DLMB_wait <= microblaze_0_dlmb_WAIT;
ILMB_ce <= microblaze_0_ilmb_CE;
ILMB_readdbus(0 to 31) <= microblaze_0_ilmb_READDBUS(0 to 31);
ILMB_ready <= microblaze_0_ilmb_READY;
ILMB_ue <= microblaze_0_ilmb_UE;
ILMB_wait <= microblaze_0_ilmb_WAIT;
SYS_Rst_1(0) <= SYS_Rst(0);
microblaze_0_Clk <= LMB_Clk;
microblaze_0_dlmb_ABUS(0 to 31) <= DLMB_abus(0 to 31);
microblaze_0_dlmb_ADDRSTROBE <= DLMB_addrstrobe;
microblaze_0_dlmb_BE(0 to 3) <= DLMB_be(0 to 3);
microblaze_0_dlmb_READSTROBE <= DLMB_readstrobe;
microblaze_0_dlmb_WRITEDBUS(0 to 31) <= DLMB_writedbus(0 to 31);
microblaze_0_dlmb_WRITESTROBE <= DLMB_writestrobe;
microblaze_0_ilmb_ABUS(0 to 31) <= ILMB_abus(0 to 31);
microblaze_0_ilmb_ADDRSTROBE <= ILMB_addrstrobe;
microblaze_0_ilmb_READSTROBE <= ILMB_readstrobe;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
dlmb_bram_if_cntlr: component design_1_dlmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_dlmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_dlmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_dlmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_dlmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_dlmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_dlmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_dlmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_dlmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_dlmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_dlmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_dlmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_dlmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_dlmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_dlmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_dlmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_dlmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_dlmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_dlmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_dlmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_dlmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_dlmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_dlmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_dlmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_dlmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_dlmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_dlmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_dlmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_dlmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_dlmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_dlmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_dlmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_dlmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_dlmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_dlmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_dlmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_dlmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_dlmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_dlmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_dlmb_bus_READY,
Sl_UE => microblaze_0_dlmb_bus_UE,
Sl_Wait => microblaze_0_dlmb_bus_WAIT
);
dlmb_v10: component design_1_dlmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_dlmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_dlmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Ready => microblaze_0_dlmb_READY,
LMB_Rst => NLW_dlmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_dlmb_UE,
LMB_Wait => microblaze_0_dlmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_dlmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_dlmb_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_dlmb_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_dlmb_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_dlmb_READSTROBE,
M_WriteStrobe => microblaze_0_dlmb_WRITESTROBE,
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_dlmb_bus_READY,
Sl_UE(0) => microblaze_0_dlmb_bus_UE,
Sl_Wait(0) => microblaze_0_dlmb_bus_WAIT
);
ilmb_bram_if_cntlr: component design_1_ilmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_ilmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_ilmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_ilmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_ilmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_ilmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_ilmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_ilmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_ilmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_ilmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_ilmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_ilmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_ilmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_ilmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_ilmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_ilmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_ilmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_ilmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_ilmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_ilmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_ilmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_ilmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_ilmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_ilmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_ilmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_ilmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_ilmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_ilmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_ilmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_ilmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_ilmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_ilmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_ilmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_ilmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_ilmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_ilmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_ilmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_ilmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_ilmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_ilmb_bus_READY,
Sl_UE => microblaze_0_ilmb_bus_UE,
Sl_Wait => microblaze_0_ilmb_bus_WAIT
);
ilmb_v10: component design_1_ilmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_ilmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_ilmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Ready => microblaze_0_ilmb_READY,
LMB_Rst => NLW_ilmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ilmb_UE,
LMB_Wait => microblaze_0_ilmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ilmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ilmb_ADDRSTROBE,
M_BE(0) => GND_1,
M_BE(1) => GND_1,
M_BE(2) => GND_1,
M_BE(3) => GND_1,
M_DBus(0) => GND_1,
M_DBus(1) => GND_1,
M_DBus(2) => GND_1,
M_DBus(3) => GND_1,
M_DBus(4) => GND_1,
M_DBus(5) => GND_1,
M_DBus(6) => GND_1,
M_DBus(7) => GND_1,
M_DBus(8) => GND_1,
M_DBus(9) => GND_1,
M_DBus(10) => GND_1,
M_DBus(11) => GND_1,
M_DBus(12) => GND_1,
M_DBus(13) => GND_1,
M_DBus(14) => GND_1,
M_DBus(15) => GND_1,
M_DBus(16) => GND_1,
M_DBus(17) => GND_1,
M_DBus(18) => GND_1,
M_DBus(19) => GND_1,
M_DBus(20) => GND_1,
M_DBus(21) => GND_1,
M_DBus(22) => GND_1,
M_DBus(23) => GND_1,
M_DBus(24) => GND_1,
M_DBus(25) => GND_1,
M_DBus(26) => GND_1,
M_DBus(27) => GND_1,
M_DBus(28) => GND_1,
M_DBus(29) => GND_1,
M_DBus(30) => GND_1,
M_DBus(31) => GND_1,
M_ReadStrobe => microblaze_0_ilmb_READSTROBE,
M_WriteStrobe => GND_1,
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_ilmb_bus_READY,
Sl_UE(0) => microblaze_0_ilmb_bus_UE,
Sl_Wait(0) => microblaze_0_ilmb_bus_WAIT
);
lmb_bram: component design_1_lmb_bram_0
port map (
addra(31) => microblaze_0_dlmb_cntlr_ADDR(0),
addra(30) => microblaze_0_dlmb_cntlr_ADDR(1),
addra(29) => microblaze_0_dlmb_cntlr_ADDR(2),
addra(28) => microblaze_0_dlmb_cntlr_ADDR(3),
addra(27) => microblaze_0_dlmb_cntlr_ADDR(4),
addra(26) => microblaze_0_dlmb_cntlr_ADDR(5),
addra(25) => microblaze_0_dlmb_cntlr_ADDR(6),
addra(24) => microblaze_0_dlmb_cntlr_ADDR(7),
addra(23) => microblaze_0_dlmb_cntlr_ADDR(8),
addra(22) => microblaze_0_dlmb_cntlr_ADDR(9),
addra(21) => microblaze_0_dlmb_cntlr_ADDR(10),
addra(20) => microblaze_0_dlmb_cntlr_ADDR(11),
addra(19) => microblaze_0_dlmb_cntlr_ADDR(12),
addra(18) => microblaze_0_dlmb_cntlr_ADDR(13),
addra(17) => microblaze_0_dlmb_cntlr_ADDR(14),
addra(16) => microblaze_0_dlmb_cntlr_ADDR(15),
addra(15) => microblaze_0_dlmb_cntlr_ADDR(16),
addra(14) => microblaze_0_dlmb_cntlr_ADDR(17),
addra(13) => microblaze_0_dlmb_cntlr_ADDR(18),
addra(12) => microblaze_0_dlmb_cntlr_ADDR(19),
addra(11) => microblaze_0_dlmb_cntlr_ADDR(20),
addra(10) => microblaze_0_dlmb_cntlr_ADDR(21),
addra(9) => microblaze_0_dlmb_cntlr_ADDR(22),
addra(8) => microblaze_0_dlmb_cntlr_ADDR(23),
addra(7) => microblaze_0_dlmb_cntlr_ADDR(24),
addra(6) => microblaze_0_dlmb_cntlr_ADDR(25),
addra(5) => microblaze_0_dlmb_cntlr_ADDR(26),
addra(4) => microblaze_0_dlmb_cntlr_ADDR(27),
addra(3) => microblaze_0_dlmb_cntlr_ADDR(28),
addra(2) => microblaze_0_dlmb_cntlr_ADDR(29),
addra(1) => microblaze_0_dlmb_cntlr_ADDR(30),
addra(0) => microblaze_0_dlmb_cntlr_ADDR(31),
addrb(31) => microblaze_0_ilmb_cntlr_ADDR(0),
addrb(30) => microblaze_0_ilmb_cntlr_ADDR(1),
addrb(29) => microblaze_0_ilmb_cntlr_ADDR(2),
addrb(28) => microblaze_0_ilmb_cntlr_ADDR(3),
addrb(27) => microblaze_0_ilmb_cntlr_ADDR(4),
addrb(26) => microblaze_0_ilmb_cntlr_ADDR(5),
addrb(25) => microblaze_0_ilmb_cntlr_ADDR(6),
addrb(24) => microblaze_0_ilmb_cntlr_ADDR(7),
addrb(23) => microblaze_0_ilmb_cntlr_ADDR(8),
addrb(22) => microblaze_0_ilmb_cntlr_ADDR(9),
addrb(21) => microblaze_0_ilmb_cntlr_ADDR(10),
addrb(20) => microblaze_0_ilmb_cntlr_ADDR(11),
addrb(19) => microblaze_0_ilmb_cntlr_ADDR(12),
addrb(18) => microblaze_0_ilmb_cntlr_ADDR(13),
addrb(17) => microblaze_0_ilmb_cntlr_ADDR(14),
addrb(16) => microblaze_0_ilmb_cntlr_ADDR(15),
addrb(15) => microblaze_0_ilmb_cntlr_ADDR(16),
addrb(14) => microblaze_0_ilmb_cntlr_ADDR(17),
addrb(13) => microblaze_0_ilmb_cntlr_ADDR(18),
addrb(12) => microblaze_0_ilmb_cntlr_ADDR(19),
addrb(11) => microblaze_0_ilmb_cntlr_ADDR(20),
addrb(10) => microblaze_0_ilmb_cntlr_ADDR(21),
addrb(9) => microblaze_0_ilmb_cntlr_ADDR(22),
addrb(8) => microblaze_0_ilmb_cntlr_ADDR(23),
addrb(7) => microblaze_0_ilmb_cntlr_ADDR(24),
addrb(6) => microblaze_0_ilmb_cntlr_ADDR(25),
addrb(5) => microblaze_0_ilmb_cntlr_ADDR(26),
addrb(4) => microblaze_0_ilmb_cntlr_ADDR(27),
addrb(3) => microblaze_0_ilmb_cntlr_ADDR(28),
addrb(2) => microblaze_0_ilmb_cntlr_ADDR(29),
addrb(1) => microblaze_0_ilmb_cntlr_ADDR(30),
addrb(0) => microblaze_0_ilmb_cntlr_ADDR(31),
clka => microblaze_0_dlmb_cntlr_CLK,
clkb => microblaze_0_ilmb_cntlr_CLK,
dina(31) => microblaze_0_dlmb_cntlr_DIN(0),
dina(30) => microblaze_0_dlmb_cntlr_DIN(1),
dina(29) => microblaze_0_dlmb_cntlr_DIN(2),
dina(28) => microblaze_0_dlmb_cntlr_DIN(3),
dina(27) => microblaze_0_dlmb_cntlr_DIN(4),
dina(26) => microblaze_0_dlmb_cntlr_DIN(5),
dina(25) => microblaze_0_dlmb_cntlr_DIN(6),
dina(24) => microblaze_0_dlmb_cntlr_DIN(7),
dina(23) => microblaze_0_dlmb_cntlr_DIN(8),
dina(22) => microblaze_0_dlmb_cntlr_DIN(9),
dina(21) => microblaze_0_dlmb_cntlr_DIN(10),
dina(20) => microblaze_0_dlmb_cntlr_DIN(11),
dina(19) => microblaze_0_dlmb_cntlr_DIN(12),
dina(18) => microblaze_0_dlmb_cntlr_DIN(13),
dina(17) => microblaze_0_dlmb_cntlr_DIN(14),
dina(16) => microblaze_0_dlmb_cntlr_DIN(15),
dina(15) => microblaze_0_dlmb_cntlr_DIN(16),
dina(14) => microblaze_0_dlmb_cntlr_DIN(17),
dina(13) => microblaze_0_dlmb_cntlr_DIN(18),
dina(12) => microblaze_0_dlmb_cntlr_DIN(19),
dina(11) => microblaze_0_dlmb_cntlr_DIN(20),
dina(10) => microblaze_0_dlmb_cntlr_DIN(21),
dina(9) => microblaze_0_dlmb_cntlr_DIN(22),
dina(8) => microblaze_0_dlmb_cntlr_DIN(23),
dina(7) => microblaze_0_dlmb_cntlr_DIN(24),
dina(6) => microblaze_0_dlmb_cntlr_DIN(25),
dina(5) => microblaze_0_dlmb_cntlr_DIN(26),
dina(4) => microblaze_0_dlmb_cntlr_DIN(27),
dina(3) => microblaze_0_dlmb_cntlr_DIN(28),
dina(2) => microblaze_0_dlmb_cntlr_DIN(29),
dina(1) => microblaze_0_dlmb_cntlr_DIN(30),
dina(0) => microblaze_0_dlmb_cntlr_DIN(31),
dinb(31) => microblaze_0_ilmb_cntlr_DIN(0),
dinb(30) => microblaze_0_ilmb_cntlr_DIN(1),
dinb(29) => microblaze_0_ilmb_cntlr_DIN(2),
dinb(28) => microblaze_0_ilmb_cntlr_DIN(3),
dinb(27) => microblaze_0_ilmb_cntlr_DIN(4),
dinb(26) => microblaze_0_ilmb_cntlr_DIN(5),
dinb(25) => microblaze_0_ilmb_cntlr_DIN(6),
dinb(24) => microblaze_0_ilmb_cntlr_DIN(7),
dinb(23) => microblaze_0_ilmb_cntlr_DIN(8),
dinb(22) => microblaze_0_ilmb_cntlr_DIN(9),
dinb(21) => microblaze_0_ilmb_cntlr_DIN(10),
dinb(20) => microblaze_0_ilmb_cntlr_DIN(11),
dinb(19) => microblaze_0_ilmb_cntlr_DIN(12),
dinb(18) => microblaze_0_ilmb_cntlr_DIN(13),
dinb(17) => microblaze_0_ilmb_cntlr_DIN(14),
dinb(16) => microblaze_0_ilmb_cntlr_DIN(15),
dinb(15) => microblaze_0_ilmb_cntlr_DIN(16),
dinb(14) => microblaze_0_ilmb_cntlr_DIN(17),
dinb(13) => microblaze_0_ilmb_cntlr_DIN(18),
dinb(12) => microblaze_0_ilmb_cntlr_DIN(19),
dinb(11) => microblaze_0_ilmb_cntlr_DIN(20),
dinb(10) => microblaze_0_ilmb_cntlr_DIN(21),
dinb(9) => microblaze_0_ilmb_cntlr_DIN(22),
dinb(8) => microblaze_0_ilmb_cntlr_DIN(23),
dinb(7) => microblaze_0_ilmb_cntlr_DIN(24),
dinb(6) => microblaze_0_ilmb_cntlr_DIN(25),
dinb(5) => microblaze_0_ilmb_cntlr_DIN(26),
dinb(4) => microblaze_0_ilmb_cntlr_DIN(27),
dinb(3) => microblaze_0_ilmb_cntlr_DIN(28),
dinb(2) => microblaze_0_ilmb_cntlr_DIN(29),
dinb(1) => microblaze_0_ilmb_cntlr_DIN(30),
dinb(0) => microblaze_0_ilmb_cntlr_DIN(31),
douta(31 downto 0) => microblaze_0_dlmb_cntlr_DOUT(31 downto 0),
doutb(31 downto 0) => microblaze_0_ilmb_cntlr_DOUT(31 downto 0),
ena => microblaze_0_dlmb_cntlr_EN,
enb => microblaze_0_ilmb_cntlr_EN,
rsta => microblaze_0_dlmb_cntlr_RST,
rstb => microblaze_0_ilmb_cntlr_RST,
wea(3) => microblaze_0_dlmb_cntlr_WE(0),
wea(2) => microblaze_0_dlmb_cntlr_WE(1),
wea(1) => microblaze_0_dlmb_cntlr_WE(2),
wea(0) => microblaze_0_dlmb_cntlr_WE(3),
web(3) => microblaze_0_ilmb_cntlr_WE(0),
web(2) => microblaze_0_ilmb_cntlr_WE(1),
web(1) => microblaze_0_ilmb_cntlr_WE(2),
web(0) => microblaze_0_ilmb_cntlr_WE(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RZP34U is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_1RZP34U;
architecture STRUCTURE of s00_couplers_imp_1RZP34U is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7HNO1D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_7HNO1D;
architecture STRUCTURE of s00_couplers_imp_7HNO1D is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= s00_couplers_to_s00_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= s00_couplers_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= s00_couplers_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s00_couplers_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s00_couplers_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= s00_couplers_to_s00_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= s00_couplers_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= s00_couplers_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= s00_couplers_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= s00_couplers_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s00_couplers_to_s00_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bid(0) <= s00_couplers_to_s00_couplers_BID(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rid(0) <= s00_couplers_to_s00_couplers_RID(0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARID(0) <= S_AXI_arid(0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARLOCK(0) <= S_AXI_arlock(0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_s00_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_s00_couplers_AWID(0) <= S_AXI_awid(0);
s00_couplers_to_s00_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_s00_couplers_AWLOCK(0) <= S_AXI_awlock(0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BID(0) <= M_AXI_bid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RID(0) <= M_AXI_rid(0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WLAST(0) <= S_AXI_wlast(0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1W60HW0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s01_couplers_imp_1W60HW0;
architecture STRUCTURE of s01_couplers_imp_1W60HW0 is
signal s01_couplers_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s01_couplers_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s01_couplers_to_s01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s01_couplers_to_s01_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= s01_couplers_to_s01_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= s01_couplers_to_s01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= s01_couplers_to_s01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= s01_couplers_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= s01_couplers_to_s01_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= s01_couplers_to_s01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s01_couplers_to_s01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= s01_couplers_to_s01_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= s01_couplers_to_s01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= s01_couplers_to_s01_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s01_couplers_to_s01_couplers_AWVALID(0);
M_AXI_bready(0) <= s01_couplers_to_s01_couplers_BREADY(0);
M_AXI_rready(0) <= s01_couplers_to_s01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s01_couplers_to_s01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s01_couplers_to_s01_couplers_WVALID(0);
S_AXI_arready(0) <= s01_couplers_to_s01_couplers_ARREADY(0);
S_AXI_awready(0) <= s01_couplers_to_s01_couplers_AWREADY(0);
S_AXI_bid(0) <= s01_couplers_to_s01_couplers_BID(0);
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s01_couplers_to_s01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s01_couplers_to_s01_couplers_RDATA(31 downto 0);
S_AXI_rid(0) <= s01_couplers_to_s01_couplers_RID(0);
S_AXI_rlast(0) <= s01_couplers_to_s01_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s01_couplers_to_s01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s01_couplers_to_s01_couplers_RVALID(0);
S_AXI_wready(0) <= s01_couplers_to_s01_couplers_WREADY(0);
s01_couplers_to_s01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_s01_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s01_couplers_to_s01_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s01_couplers_to_s01_couplers_ARID(0) <= S_AXI_arid(0);
s01_couplers_to_s01_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s01_couplers_to_s01_couplers_ARLOCK(0) <= S_AXI_arlock(0);
s01_couplers_to_s01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_s01_couplers_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s01_couplers_to_s01_couplers_ARREADY(0) <= M_AXI_arready(0);
s01_couplers_to_s01_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s01_couplers_to_s01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWID(0) <= S_AXI_awid(0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWLOCK(0) <= S_AXI_awlock(0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s01_couplers_to_s01_couplers_AWREADY(0) <= M_AXI_awready(0);
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s01_couplers_to_s01_couplers_BID(0) <= M_AXI_bid(0);
s01_couplers_to_s01_couplers_BREADY(0) <= S_AXI_bready(0);
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID(0) <= M_AXI_bvalid(0);
s01_couplers_to_s01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s01_couplers_to_s01_couplers_RID(0) <= M_AXI_rid(0);
s01_couplers_to_s01_couplers_RLAST(0) <= M_AXI_rlast(0);
s01_couplers_to_s01_couplers_RREADY(0) <= S_AXI_rready(0);
s01_couplers_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s01_couplers_to_s01_couplers_RVALID(0) <= M_AXI_rvalid(0);
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST(0) <= S_AXI_wlast(0);
s01_couplers_to_s01_couplers_WREADY(0) <= M_AXI_wready(0);
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_1_axi_mem_intercon_0;
architecture STRUCTURE of design_1_axi_mem_intercon_0 is
component design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal s01_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_xbar_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_xbar_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_xbar_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0);
M00_AXI_arlock(0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_axi_mem_intercon_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0);
M00_AXI_awlock(0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_axi_mem_intercon_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_axi_mem_intercon_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_axi_mem_intercon_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wlast(0) <= m00_couplers_to_axi_mem_intercon_WLAST(0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_axi_mem_intercon_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= axi_mem_intercon_to_s00_couplers_AWREADY(0);
S00_AXI_bid(0) <= axi_mem_intercon_to_s00_couplers_BID(0);
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= axi_mem_intercon_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(0) <= axi_mem_intercon_to_s00_couplers_RID(0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= axi_mem_intercon_to_s00_couplers_WREADY(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_arready(0) <= axi_mem_intercon_to_s01_couplers_ARREADY(0);
S01_AXI_awready(0) <= axi_mem_intercon_to_s01_couplers_AWREADY(0);
S01_AXI_bid(0) <= axi_mem_intercon_to_s01_couplers_BID(0);
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid(0) <= axi_mem_intercon_to_s01_couplers_BVALID(0);
S01_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rid(0) <= axi_mem_intercon_to_s01_couplers_RID(0);
S01_AXI_rlast(0) <= axi_mem_intercon_to_s01_couplers_RLAST(0);
S01_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid(0) <= axi_mem_intercon_to_s01_couplers_RVALID(0);
S01_AXI_wready(0) <= axi_mem_intercon_to_s01_couplers_WREADY(0);
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARID(0) <= S00_AXI_arid(0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARLOCK(0) <= S00_AXI_arlock(0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWID(0) <= S00_AXI_awid(0);
axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_AWLOCK(0) <= S00_AXI_awlock(0);
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
axi_mem_intercon_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST(0) <= S00_AXI_wlast(0);
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0) <= S01_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0) <= S01_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARID(0) <= S01_AXI_arid(0);
axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0) <= S01_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_ARLOCK(0) <= S01_AXI_arlock(0);
axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0) <= S01_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0) <= S01_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARVALID(0) <= S01_AXI_arvalid(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWID(0) <= S01_AXI_awid(0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWLOCK(0) <= S01_AXI_awlock(0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWQOS(3 downto 0) <= S01_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID(0) <= S01_AXI_awvalid(0);
axi_mem_intercon_to_s01_couplers_BREADY(0) <= S01_AXI_bready(0);
axi_mem_intercon_to_s01_couplers_RREADY(0) <= S01_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST(0) <= S01_AXI_wlast(0);
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID(0) <= S01_AXI_wvalid(0);
m00_couplers_to_axi_mem_intercon_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_axi_mem_intercon_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_axi_mem_intercon_BID(0) <= M00_AXI_bid(0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(0) <= M00_AXI_rid(0);
m00_couplers_to_axi_mem_intercon_RLAST(0) <= M00_AXI_rlast(0);
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_axi_mem_intercon_WREADY(0) <= M00_AXI_wready(0);
m00_couplers: entity work.m00_couplers_imp_1R706YB
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0),
M_AXI_arlock(0) => m00_couplers_to_axi_mem_intercon_ARLOCK(0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_axi_mem_intercon_ARREADY(0),
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => m00_couplers_to_axi_mem_intercon_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0),
M_AXI_awlock(0) => m00_couplers_to_axi_mem_intercon_AWLOCK(0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_axi_mem_intercon_AWREADY(0),
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => m00_couplers_to_axi_mem_intercon_AWVALID(0),
M_AXI_bid(0) => m00_couplers_to_axi_mem_intercon_BID(0),
M_AXI_bready(0) => m00_couplers_to_axi_mem_intercon_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_axi_mem_intercon_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(0) => m00_couplers_to_axi_mem_intercon_RID(0),
M_AXI_rlast(0) => m00_couplers_to_axi_mem_intercon_RLAST(0),
M_AXI_rready(0) => m00_couplers_to_axi_mem_intercon_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_axi_mem_intercon_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wlast(0) => m00_couplers_to_axi_mem_intercon_WLAST(0),
M_AXI_wready(0) => m00_couplers_to_axi_mem_intercon_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_axi_mem_intercon_WVALID(0),
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast(0) => xbar_to_m00_couplers_RLAST(0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_7HNO1D
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(0) => s00_couplers_to_xbar_ARID(0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(0) => s00_couplers_to_xbar_AWID(0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bid(0) => s00_couplers_to_xbar_BID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rid(0) => s00_couplers_to_xbar_RID(0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s00_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => axi_mem_intercon_to_s00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_mem_intercon_to_s00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => axi_mem_intercon_to_s00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_mem_intercon_to_s00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s00_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s00_couplers_AWVALID(0),
S_AXI_bid(0) => axi_mem_intercon_to_s00_couplers_BID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => axi_mem_intercon_to_s00_couplers_RID(0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s00_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s00_couplers_WVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1W60HW0
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s01_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(0) => s01_couplers_to_xbar_ARID(0),
M_AXI_arlen(7 downto 0) => s01_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s01_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s01_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready(0) => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arsize(2 downto 0) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s01_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(0) => s01_couplers_to_xbar_AWID(0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready(0) => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s01_couplers_to_xbar_AWVALID(0),
M_AXI_bid(0) => s01_couplers_to_xbar_BID(1),
M_AXI_bready(0) => s01_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid(0) => s01_couplers_to_xbar_BVALID(1),
M_AXI_rdata(31 downto 0) => s01_couplers_to_xbar_RDATA(63 downto 32),
M_AXI_rid(0) => s01_couplers_to_xbar_RID(1),
M_AXI_rlast(0) => s01_couplers_to_xbar_RLAST(1),
M_AXI_rready(0) => s01_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid(0) => s01_couplers_to_xbar_RVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s01_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s01_couplers_to_xbar_WVALID(0),
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => axi_mem_intercon_to_s01_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_mem_intercon_to_s01_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s01_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s01_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => axi_mem_intercon_to_s01_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_mem_intercon_to_s01_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWQOS(3 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s01_couplers_AWVALID(0),
S_AXI_bid(0) => axi_mem_intercon_to_s01_couplers_BID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s01_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => axi_mem_intercon_to_s01_couplers_RID(0),
S_AXI_rlast(0) => axi_mem_intercon_to_s01_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s01_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s01_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s01_couplers_WVALID(0)
);
xbar: component design_1_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_xbar_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arregion(3 downto 0) => NLW_xbar_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_xbar_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awregion(3 downto 0) => NLW_xbar_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST(0),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => s01_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1) => s01_couplers_to_xbar_ARID(0),
s_axi_arid(0) => s00_couplers_to_xbar_ARID(0),
s_axi_arlen(15 downto 8) => s01_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1) => s01_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 4) => s01_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(1) => s01_couplers_to_xbar_AWID(0),
s_axi_awid(0) => s00_couplers_to_xbar_AWID(0),
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bid(1) => s01_couplers_to_xbar_BID(1),
s_axi_bid(0) => s00_couplers_to_xbar_BID(0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(63 downto 32) => s01_couplers_to_xbar_RDATA(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(1) => s01_couplers_to_xbar_RID(1),
s_axi_rid(0) => s00_couplers_to_xbar_RID(0),
s_axi_rlast(1) => s01_couplers_to_xbar_RLAST(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => s01_couplers_to_xbar_RREADY(0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST(0),
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST(0),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID(0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_1_microblaze_0_axi_periph_0;
architecture STRUCTURE of design_1_microblaze_0_axi_periph_0 is
component design_1_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_1_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_ACLK_net : STD_LOGIC;
signal microblaze_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid <= m00_couplers_to_microblaze_0_axi_periph_ARVALID;
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid <= m00_couplers_to_microblaze_0_axi_periph_AWVALID;
M00_AXI_bready <= m00_couplers_to_microblaze_0_axi_periph_BREADY;
M00_AXI_rready <= m00_couplers_to_microblaze_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_microblaze_0_axi_periph_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_ARADDR(3 downto 0);
M01_AXI_arvalid <= m01_couplers_to_microblaze_0_axi_periph_ARVALID;
M01_AXI_awaddr(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_AWADDR(3 downto 0);
M01_AXI_awvalid <= m01_couplers_to_microblaze_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_microblaze_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_microblaze_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_microblaze_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(12 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_ARADDR(12 downto 0);
M02_AXI_arvalid <= m02_couplers_to_microblaze_0_axi_periph_ARVALID;
M02_AXI_awaddr(12 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_AWADDR(12 downto 0);
M02_AXI_awvalid <= m02_couplers_to_microblaze_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_microblaze_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_microblaze_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_microblaze_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(4 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_ARADDR(4 downto 0);
M03_AXI_arvalid <= m03_couplers_to_microblaze_0_axi_periph_ARVALID;
M03_AXI_awaddr(4 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_AWADDR(4 downto 0);
M03_AXI_awvalid <= m03_couplers_to_microblaze_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_microblaze_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_microblaze_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_microblaze_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= microblaze_0_axi_periph_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= microblaze_0_axi_periph_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= microblaze_0_axi_periph_to_s00_couplers_WREADY(0);
m00_couplers_to_microblaze_0_axi_periph_ARREADY <= M00_AXI_arready;
m00_couplers_to_microblaze_0_axi_periph_AWREADY <= M00_AXI_awready;
m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_BVALID <= M00_AXI_bvalid;
m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RVALID <= M00_AXI_rvalid;
m00_couplers_to_microblaze_0_axi_periph_WREADY <= M00_AXI_wready;
m01_couplers_to_microblaze_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_microblaze_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_microblaze_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_microblaze_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_microblaze_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_microblaze_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_microblaze_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_microblaze_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_microblaze_0_axi_periph_WREADY <= M03_AXI_wready;
microblaze_0_axi_periph_ACLK_net <= ACLK;
microblaze_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
microblaze_0_axi_periph_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
microblaze_0_axi_periph_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers: entity work.m00_couplers_imp_8RVYHO
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_microblaze_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m00_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m00_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m00_couplers_to_microblaze_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m00_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m00_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m00_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m00_couplers_ARADDR(8 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(8 downto 0) => xbar_to_m00_couplers_AWADDR(8 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1UTB3Y5
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arready => m01_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awready => m01_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m01_couplers_ARADDR(35 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(3 downto 0) => xbar_to_m01_couplers_AWADDR(35 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_7ANRHB
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(12 downto 0) => m02_couplers_to_microblaze_0_axi_periph_ARADDR(12 downto 0),
M_AXI_arready => m02_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(12 downto 0) => m02_couplers_to_microblaze_0_axi_periph_AWADDR(12 downto 0),
M_AXI_awready => m02_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(12 downto 0) => xbar_to_m02_couplers_ARADDR(76 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(12 downto 0) => xbar_to_m02_couplers_AWADDR(76 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1W07O72
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(4 downto 0) => m03_couplers_to_microblaze_0_axi_periph_ARADDR(4 downto 0),
M_AXI_arready => m03_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(4 downto 0) => m03_couplers_to_microblaze_0_axi_periph_AWADDR(4 downto 0),
M_AXI_awready => m03_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(4 downto 0) => xbar_to_m03_couplers_ARADDR(100 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(4 downto 0) => xbar_to_m03_couplers_AWADDR(100 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
s00_couplers: entity work.s00_couplers_imp_1RZP34U
port map (
M_ACLK => microblaze_0_axi_periph_ACLK_net,
M_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => microblaze_0_axi_periph_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => microblaze_0_axi_periph_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => microblaze_0_axi_periph_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => microblaze_0_axi_periph_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => microblaze_0_axi_periph_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => microblaze_0_axi_periph_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => microblaze_0_axi_periph_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => microblaze_0_axi_periph_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => microblaze_0_axi_periph_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => microblaze_0_axi_periph_to_s00_couplers_WVALID(0)
);
xbar: component design_1_xbar_1
port map (
aclk => microblaze_0_axi_periph_ACLK_net,
aresetn => microblaze_0_axi_periph_ARESETN_net(0),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(11 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(11 downto 0),
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(11 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(11 downto 0),
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=29,numReposBlks=18,numNonXlnxBlks=0,numHierBlks=11,maxHierDepth=1,da_axi4_cnt=4,da_board_cnt=8,da_mb_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;
architecture STRUCTURE of design_1 is
component design_1_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_AWLOCK : out STD_LOGIC;
M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWVALID : out STD_LOGIC;
M_AXI_IC_AWREADY : in STD_LOGIC;
M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_WLAST : out STD_LOGIC;
M_AXI_IC_WVALID : out STD_LOGIC;
M_AXI_IC_WREADY : in STD_LOGIC;
M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_BVALID : in STD_LOGIC;
M_AXI_IC_BREADY : out STD_LOGIC;
M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_ARLOCK : out STD_LOGIC;
M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARVALID : out STD_LOGIC;
M_AXI_IC_ARREADY : in STD_LOGIC;
M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_RLAST : in STD_LOGIC;
M_AXI_IC_RVALID : in STD_LOGIC;
M_AXI_IC_RREADY : out STD_LOGIC;
M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_AWLOCK : out STD_LOGIC;
M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWVALID : out STD_LOGIC;
M_AXI_DC_AWREADY : in STD_LOGIC;
M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_WLAST : out STD_LOGIC;
M_AXI_DC_WVALID : out STD_LOGIC;
M_AXI_DC_WREADY : in STD_LOGIC;
M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_BVALID : in STD_LOGIC;
M_AXI_DC_BREADY : out STD_LOGIC;
M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_ARLOCK : out STD_LOGIC;
M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARVALID : out STD_LOGIC;
M_AXI_DC_ARREADY : in STD_LOGIC;
M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_RLAST : in STD_LOGIC;
M_AXI_DC_RVALID : in STD_LOGIC;
M_AXI_DC_RREADY : out STD_LOGIC
);
end component design_1_microblaze_0_0;
component design_1_microblaze_0_axi_intc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 1 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_microblaze_0_axi_intc_0;
component design_1_microblaze_0_xlconcat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_1_microblaze_0_xlconcat_0;
component design_1_mdm_1_0 is
port (
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC
);
end component design_1_mdm_1_0;
component design_1_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
end component design_1_clk_wiz_1_0;
component design_1_rst_clk_wiz_1_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_rst_clk_wiz_1_100M_0;
component design_1_axi_emc_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rdclk : in STD_LOGIC;
s_axi_mem_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_mem_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_awlock : in STD_LOGIC;
s_axi_mem_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_mem_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_awvalid : in STD_LOGIC;
s_axi_mem_awready : out STD_LOGIC;
s_axi_mem_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_mem_wlast : in STD_LOGIC;
s_axi_mem_wvalid : in STD_LOGIC;
s_axi_mem_wready : out STD_LOGIC;
s_axi_mem_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_bvalid : out STD_LOGIC;
s_axi_mem_bready : in STD_LOGIC;
s_axi_mem_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_mem_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_arlock : in STD_LOGIC;
s_axi_mem_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_mem_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_arvalid : in STD_LOGIC;
s_axi_mem_arready : out STD_LOGIC;
s_axi_mem_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_rlast : out STD_LOGIC;
s_axi_mem_rvalid : out STD_LOGIC;
s_axi_mem_rready : in STD_LOGIC;
mem_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
mem_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
mem_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
mem_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
mem_ce : out STD_LOGIC_VECTOR ( 0 to 0 );
mem_cen : out STD_LOGIC_VECTOR ( 0 to 0 );
mem_oen : out STD_LOGIC_VECTOR ( 0 to 0 );
mem_wen : out STD_LOGIC;
mem_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
mem_qwen : out STD_LOGIC_VECTOR ( 1 downto 0 );
mem_rpn : out STD_LOGIC;
mem_adv_ldn : out STD_LOGIC;
mem_lbon : out STD_LOGIC;
mem_cken : out STD_LOGIC;
mem_rnw : out STD_LOGIC;
mem_cre : out STD_LOGIC;
mem_wait : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_axi_emc_0_0;
component design_1_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
end component design_1_axi_uartlite_0_0;
component design_1_mii_to_rmii_0_0 is
port (
rst_n : in STD_LOGIC;
ref_clk : in STD_LOGIC;
mac2rmii_tx_en : in STD_LOGIC;
mac2rmii_txd : in STD_LOGIC_VECTOR ( 3 downto 0 );
mac2rmii_tx_er : in STD_LOGIC;
rmii2mac_tx_clk : out STD_LOGIC;
rmii2mac_rx_clk : out STD_LOGIC;
rmii2mac_col : out STD_LOGIC;
rmii2mac_crs : out STD_LOGIC;
rmii2mac_rx_dv : out STD_LOGIC;
rmii2mac_rx_er : out STD_LOGIC;
rmii2mac_rxd : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy2rmii_crs_dv : in STD_LOGIC;
phy2rmii_rx_er : in STD_LOGIC;
phy2rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
rmii2phy_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
rmii2phy_tx_en : out STD_LOGIC
);
end component design_1_mii_to_rmii_0_0;
component design_1_axi_ethernetlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
end component design_1_axi_ethernetlite_0_0;
component design_1_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component design_1_axi_timer_0_0;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal axi_emc_0_EMC_INTF_ADDR : STD_LOGIC_VECTOR ( 22 downto 0 );
signal axi_emc_0_EMC_INTF_ADV_LDN : STD_LOGIC;
signal axi_emc_0_EMC_INTF_BEN : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_emc_0_EMC_INTF_CE_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_emc_0_EMC_INTF_CRE : STD_LOGIC;
signal axi_emc_0_EMC_INTF_DQ_I : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_emc_0_EMC_INTF_DQ_O : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_emc_0_EMC_INTF_DQ_T : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_emc_0_EMC_INTF_OEN : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_emc_0_EMC_INTF_WAIT : STD_LOGIC;
signal axi_emc_0_EMC_INTF_WEN : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDC : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_I : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_O : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_T : STD_LOGIC;
signal axi_ethernetlite_0_MII_COL : STD_LOGIC;
signal axi_ethernetlite_0_MII_CRS : STD_LOGIC;
signal axi_ethernetlite_0_MII_RXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_RX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_DV : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_ER : STD_LOGIC;
signal axi_ethernetlite_0_MII_TXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_TX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_TX_EN : STD_LOGIC;
signal axi_ethernetlite_0_ip2intc_irpt : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_timer_0_interrupt : STD_LOGIC;
signal axi_uartlite_0_UART_RxD : STD_LOGIC;
signal axi_uartlite_0_UART_TxD : STD_LOGIC;
signal clk_wiz_1_clk_out2 : STD_LOGIC;
signal clk_wiz_1_locked : STD_LOGIC;
signal mdm_1_debug_sys_rst : STD_LOGIC;
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_AWLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_BREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_WLAST : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_WVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_IC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_IC_AWLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_IC_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_AWVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_BREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_WLAST : STD_LOGIC;
signal microblaze_0_M_AXI_IC_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_WVALID : STD_LOGIC;
signal microblaze_0_axi_dp_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_ARVALID : STD_LOGIC;
signal microblaze_0_axi_dp_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_AWVALID : STD_LOGIC;
signal microblaze_0_axi_dp_BREADY : STD_LOGIC;
signal microblaze_0_axi_dp_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_RREADY : STD_LOGIC;
signal microblaze_0_axi_dp_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_dp_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal microblaze_0_debug_CAPTURE : STD_LOGIC;
signal microblaze_0_debug_CLK : STD_LOGIC;
signal microblaze_0_debug_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal microblaze_0_debug_RST : STD_LOGIC;
signal microblaze_0_debug_SHIFT : STD_LOGIC;
signal microblaze_0_debug_TDI : STD_LOGIC;
signal microblaze_0_debug_TDO : STD_LOGIC;
signal microblaze_0_debug_UPDATE : STD_LOGIC;
signal microblaze_0_dlmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_1_CE : STD_LOGIC;
signal microblaze_0_dlmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_READY : STD_LOGIC;
signal microblaze_0_dlmb_1_UE : STD_LOGIC;
signal microblaze_0_dlmb_1_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_CE : STD_LOGIC;
signal microblaze_0_ilmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_READY : STD_LOGIC;
signal microblaze_0_ilmb_1_UE : STD_LOGIC;
signal microblaze_0_ilmb_1_WAIT : STD_LOGIC;
signal microblaze_0_intc_axi_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal microblaze_0_intc_axi_ARREADY : STD_LOGIC;
signal microblaze_0_intc_axi_ARVALID : STD_LOGIC;
signal microblaze_0_intc_axi_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal microblaze_0_intc_axi_AWREADY : STD_LOGIC;
signal microblaze_0_intc_axi_AWVALID : STD_LOGIC;
signal microblaze_0_intc_axi_BREADY : STD_LOGIC;
signal microblaze_0_intc_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_BVALID : STD_LOGIC;
signal microblaze_0_intc_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_RREADY : STD_LOGIC;
signal microblaze_0_intc_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_RVALID : STD_LOGIC;
signal microblaze_0_intc_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_WREADY : STD_LOGIC;
signal microblaze_0_intc_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_intc_axi_WVALID : STD_LOGIC;
signal microblaze_0_interrupt_ACK : STD_LOGIC_VECTOR ( 0 to 1 );
signal microblaze_0_interrupt_ADDRESS : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_interrupt_INTERRUPT : STD_LOGIC;
signal microblaze_0_intr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mii_to_rmii_0_RMII_PHY_M_CRS_DV : STD_LOGIC;
signal mii_to_rmii_0_RMII_PHY_M_RXD : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mii_to_rmii_0_RMII_PHY_M_RX_ER : STD_LOGIC;
signal mii_to_rmii_0_RMII_PHY_M_TXD : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mii_to_rmii_0_RMII_PHY_M_TX_EN : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rst_clk_wiz_1_100M_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_mb_reset : STD_LOGIC;
signal rst_clk_wiz_1_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_clock_1 : STD_LOGIC;
signal NLW_axi_emc_0_mem_cken_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_lbon_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_rnw_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_rpn_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_a_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 23 );
signal NLW_axi_emc_0_mem_ce_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_emc_0_mem_qwen_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_axi_ethernetlite_0_phy_rst_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_uartlite_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > design_1 microblaze_0_local_memory/dlmb_bram_if_cntlr";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
begin
axi_emc_0_EMC_INTF_DQ_I(15 downto 0) <= cellular_ram_dq_i(15 downto 0);
axi_emc_0_EMC_INTF_WAIT <= cellular_ram_wait;
axi_ethernetlite_0_MDIO_MDIO_I <= eth_mdio_mdc_mdio_i;
axi_uartlite_0_UART_RxD <= usb_uart_rxd;
cellular_ram_addr(22 downto 0) <= axi_emc_0_EMC_INTF_ADDR(22 downto 0);
cellular_ram_adv_ldn <= axi_emc_0_EMC_INTF_ADV_LDN;
cellular_ram_ben(1 downto 0) <= axi_emc_0_EMC_INTF_BEN(1 downto 0);
cellular_ram_ce_n <= axi_emc_0_EMC_INTF_CE_N(0);
cellular_ram_cre <= axi_emc_0_EMC_INTF_CRE;
cellular_ram_dq_o(15 downto 0) <= axi_emc_0_EMC_INTF_DQ_O(15 downto 0);
cellular_ram_dq_t(15 downto 0) <= axi_emc_0_EMC_INTF_DQ_T(15 downto 0);
cellular_ram_oen <= axi_emc_0_EMC_INTF_OEN(0);
cellular_ram_wen <= axi_emc_0_EMC_INTF_WEN;
eth_mdio_mdc_mdc <= axi_ethernetlite_0_MDIO_MDC;
eth_mdio_mdc_mdio_o <= axi_ethernetlite_0_MDIO_MDIO_O;
eth_mdio_mdc_mdio_t <= axi_ethernetlite_0_MDIO_MDIO_T;
eth_ref_clk <= clk_wiz_1_clk_out2;
eth_rmii_tx_en <= mii_to_rmii_0_RMII_PHY_M_TX_EN;
eth_rmii_txd(1 downto 0) <= mii_to_rmii_0_RMII_PHY_M_TXD(1 downto 0);
mii_to_rmii_0_RMII_PHY_M_CRS_DV <= eth_rmii_crs_dv;
mii_to_rmii_0_RMII_PHY_M_RXD(1 downto 0) <= eth_rmii_rxd(1 downto 0);
mii_to_rmii_0_RMII_PHY_M_RX_ER <= eth_rmii_rx_er;
reset_1 <= reset;
sys_clock_1 <= sys_clock;
usb_uart_txd <= axi_uartlite_0_UART_TxD;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_emc_0: component design_1_axi_emc_0_0
port map (
mem_a(31 downto 23) => NLW_axi_emc_0_mem_a_UNCONNECTED(31 downto 23),
mem_a(22 downto 0) => axi_emc_0_EMC_INTF_ADDR(22 downto 0),
mem_adv_ldn => axi_emc_0_EMC_INTF_ADV_LDN,
mem_ben(1 downto 0) => axi_emc_0_EMC_INTF_BEN(1 downto 0),
mem_ce(0) => NLW_axi_emc_0_mem_ce_UNCONNECTED(0),
mem_cen(0) => axi_emc_0_EMC_INTF_CE_N(0),
mem_cken => NLW_axi_emc_0_mem_cken_UNCONNECTED,
mem_cre => axi_emc_0_EMC_INTF_CRE,
mem_dq_i(15 downto 0) => axi_emc_0_EMC_INTF_DQ_I(15 downto 0),
mem_dq_o(15 downto 0) => axi_emc_0_EMC_INTF_DQ_O(15 downto 0),
mem_dq_t(15 downto 0) => axi_emc_0_EMC_INTF_DQ_T(15 downto 0),
mem_lbon => NLW_axi_emc_0_mem_lbon_UNCONNECTED,
mem_oen(0) => axi_emc_0_EMC_INTF_OEN(0),
mem_qwen(1 downto 0) => NLW_axi_emc_0_mem_qwen_UNCONNECTED(1 downto 0),
mem_rnw => NLW_axi_emc_0_mem_rnw_UNCONNECTED,
mem_rpn => NLW_axi_emc_0_mem_rpn_UNCONNECTED,
mem_wait(0) => axi_emc_0_EMC_INTF_WAIT,
mem_wen => axi_emc_0_EMC_INTF_WEN,
rdclk => microblaze_0_Clk,
s_axi_aclk => microblaze_0_Clk,
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_mem_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
s_axi_mem_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
s_axi_mem_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
s_axi_mem_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
s_axi_mem_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
s_axi_mem_arlock => axi_mem_intercon_M00_AXI_ARLOCK(0),
s_axi_mem_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
s_axi_mem_arready => axi_mem_intercon_M00_AXI_ARREADY,
s_axi_mem_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
s_axi_mem_arvalid => axi_mem_intercon_M00_AXI_ARVALID(0),
s_axi_mem_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
s_axi_mem_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
s_axi_mem_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
s_axi_mem_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
s_axi_mem_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
s_axi_mem_awlock => axi_mem_intercon_M00_AXI_AWLOCK(0),
s_axi_mem_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
s_axi_mem_awready => axi_mem_intercon_M00_AXI_AWREADY,
s_axi_mem_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
s_axi_mem_awvalid => axi_mem_intercon_M00_AXI_AWVALID(0),
s_axi_mem_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
s_axi_mem_bready => axi_mem_intercon_M00_AXI_BREADY(0),
s_axi_mem_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
s_axi_mem_bvalid => axi_mem_intercon_M00_AXI_BVALID,
s_axi_mem_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
s_axi_mem_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
s_axi_mem_rlast => axi_mem_intercon_M00_AXI_RLAST,
s_axi_mem_rready => axi_mem_intercon_M00_AXI_RREADY(0),
s_axi_mem_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
s_axi_mem_rvalid => axi_mem_intercon_M00_AXI_RVALID,
s_axi_mem_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
s_axi_mem_wlast => axi_mem_intercon_M00_AXI_WLAST(0),
s_axi_mem_wready => axi_mem_intercon_M00_AXI_WREADY,
s_axi_mem_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
s_axi_mem_wvalid => axi_mem_intercon_M00_AXI_WVALID(0)
);
axi_ethernetlite_0: component design_1_axi_ethernetlite_0_0
port map (
ip2intc_irpt => axi_ethernetlite_0_ip2intc_irpt,
phy_col => axi_ethernetlite_0_MII_COL,
phy_crs => axi_ethernetlite_0_MII_CRS,
phy_dv => axi_ethernetlite_0_MII_RX_DV,
phy_mdc => axi_ethernetlite_0_MDIO_MDC,
phy_mdio_i => axi_ethernetlite_0_MDIO_MDIO_I,
phy_mdio_o => axi_ethernetlite_0_MDIO_MDIO_O,
phy_mdio_t => axi_ethernetlite_0_MDIO_MDIO_T,
phy_rst_n => NLW_axi_ethernetlite_0_phy_rst_n_UNCONNECTED,
phy_rx_clk => axi_ethernetlite_0_MII_RX_CLK,
phy_rx_data(3 downto 0) => axi_ethernetlite_0_MII_RXD(3 downto 0),
phy_rx_er => axi_ethernetlite_0_MII_RX_ER,
phy_tx_clk => axi_ethernetlite_0_MII_TX_CLK,
phy_tx_data(3 downto 0) => axi_ethernetlite_0_MII_TXD(3 downto 0),
phy_tx_en => axi_ethernetlite_0_MII_TX_EN,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(12 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID,
s_axi_awaddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(12 downto 0),
s_axi_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID
);
axi_mem_intercon: entity work.design_1_axi_mem_intercon_0
port map (
ACLK => microblaze_0_Clk,
ARESETN(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => axi_mem_intercon_M00_AXI_ARLOCK(0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid(0) => axi_mem_intercon_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => axi_mem_intercon_M00_AXI_AWLOCK(0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid(0) => axi_mem_intercon_M00_AXI_AWVALID(0),
M00_AXI_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
M00_AXI_bready(0) => axi_mem_intercon_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
M00_AXI_rlast(0) => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready(0) => axi_mem_intercon_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wlast(0) => axi_mem_intercon_M00_AXI_WLAST(0),
M00_AXI_wready(0) => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => axi_mem_intercon_M00_AXI_WVALID(0),
S00_ACLK => microblaze_0_Clk,
S00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
S00_AXI_arid(0) => microblaze_0_M_AXI_DC_ARID(0),
S00_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
S00_AXI_arlock(0) => microblaze_0_M_AXI_DC_ARLOCK,
S00_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
S00_AXI_arready(0) => microblaze_0_M_AXI_DC_ARREADY(0),
S00_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => microblaze_0_M_AXI_DC_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
S00_AXI_awid(0) => microblaze_0_M_AXI_DC_AWID(0),
S00_AXI_awlen(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
S00_AXI_awlock(0) => microblaze_0_M_AXI_DC_AWLOCK,
S00_AXI_awprot(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
S00_AXI_awready(0) => microblaze_0_M_AXI_DC_AWREADY(0),
S00_AXI_awsize(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
S00_AXI_awvalid(0) => microblaze_0_M_AXI_DC_AWVALID,
S00_AXI_bid(0) => microblaze_0_M_AXI_DC_BID(0),
S00_AXI_bready(0) => microblaze_0_M_AXI_DC_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_M_AXI_DC_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
S00_AXI_rid(0) => microblaze_0_M_AXI_DC_RID(0),
S00_AXI_rlast(0) => microblaze_0_M_AXI_DC_RLAST(0),
S00_AXI_rready(0) => microblaze_0_M_AXI_DC_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_M_AXI_DC_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
S00_AXI_wlast(0) => microblaze_0_M_AXI_DC_WLAST,
S00_AXI_wready(0) => microblaze_0_M_AXI_DC_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_M_AXI_DC_WVALID,
S01_ACLK => microblaze_0_Clk,
S01_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S01_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
S01_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
S01_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
S01_AXI_arid(0) => microblaze_0_M_AXI_IC_ARID(0),
S01_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
S01_AXI_arlock(0) => microblaze_0_M_AXI_IC_ARLOCK,
S01_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
S01_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
S01_AXI_arready(0) => microblaze_0_M_AXI_IC_ARREADY(0),
S01_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
S01_AXI_arvalid(0) => microblaze_0_M_AXI_IC_ARVALID,
S01_AXI_awaddr(31 downto 0) => microblaze_0_M_AXI_IC_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => microblaze_0_M_AXI_IC_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => microblaze_0_M_AXI_IC_AWCACHE(3 downto 0),
S01_AXI_awid(0) => microblaze_0_M_AXI_IC_AWID(0),
S01_AXI_awlen(7 downto 0) => microblaze_0_M_AXI_IC_AWLEN(7 downto 0),
S01_AXI_awlock(0) => microblaze_0_M_AXI_IC_AWLOCK,
S01_AXI_awprot(2 downto 0) => microblaze_0_M_AXI_IC_AWPROT(2 downto 0),
S01_AXI_awqos(3 downto 0) => microblaze_0_M_AXI_IC_AWQOS(3 downto 0),
S01_AXI_awready(0) => microblaze_0_M_AXI_IC_AWREADY(0),
S01_AXI_awsize(2 downto 0) => microblaze_0_M_AXI_IC_AWSIZE(2 downto 0),
S01_AXI_awvalid(0) => microblaze_0_M_AXI_IC_AWVALID,
S01_AXI_bid(0) => microblaze_0_M_AXI_IC_BID(0),
S01_AXI_bready(0) => microblaze_0_M_AXI_IC_BREADY,
S01_AXI_bresp(1 downto 0) => microblaze_0_M_AXI_IC_BRESP(1 downto 0),
S01_AXI_bvalid(0) => microblaze_0_M_AXI_IC_BVALID(0),
S01_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
S01_AXI_rid(0) => microblaze_0_M_AXI_IC_RID(0),
S01_AXI_rlast(0) => microblaze_0_M_AXI_IC_RLAST(0),
S01_AXI_rready(0) => microblaze_0_M_AXI_IC_RREADY,
S01_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
S01_AXI_rvalid(0) => microblaze_0_M_AXI_IC_RVALID(0),
S01_AXI_wdata(31 downto 0) => microblaze_0_M_AXI_IC_WDATA(31 downto 0),
S01_AXI_wlast(0) => microblaze_0_M_AXI_IC_WLAST,
S01_AXI_wready(0) => microblaze_0_M_AXI_IC_WREADY(0),
S01_AXI_wstrb(3 downto 0) => microblaze_0_M_AXI_IC_WSTRB(3 downto 0),
S01_AXI_wvalid(0) => microblaze_0_M_AXI_IC_WVALID
);
axi_timer_0: component design_1_axi_timer_0_0
port map (
capturetrig0 => GND_1,
capturetrig1 => GND_1,
freeze => GND_1,
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(4 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID,
s_axi_awaddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(4 downto 0),
s_axi_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M03_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M03_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID
);
axi_uartlite_0: component design_1_axi_uartlite_0_0
port map (
interrupt => NLW_axi_uartlite_0_interrupt_UNCONNECTED,
rx => axi_uartlite_0_UART_RxD,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M01_AXI_ARVALID,
s_axi_awaddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
s_axi_awready => microblaze_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M01_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M01_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M01_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M01_AXI_WVALID,
tx => axi_uartlite_0_UART_TxD
);
clk_wiz_1: component design_1_clk_wiz_1_0
port map (
clk_in1 => sys_clock_1,
clk_out1 => microblaze_0_Clk,
clk_out2 => clk_wiz_1_clk_out2,
locked => clk_wiz_1_locked,
resetn => reset_1
);
mdm_1: component design_1_mdm_1_0
port map (
Dbg_Capture_0 => microblaze_0_debug_CAPTURE,
Dbg_Clk_0 => microblaze_0_debug_CLK,
Dbg_Reg_En_0(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Rst_0 => microblaze_0_debug_RST,
Dbg_Shift_0 => microblaze_0_debug_SHIFT,
Dbg_TDI_0 => microblaze_0_debug_TDI,
Dbg_TDO_0 => microblaze_0_debug_TDO,
Dbg_Update_0 => microblaze_0_debug_UPDATE,
Debug_SYS_Rst => mdm_1_debug_sys_rst
);
microblaze_0: component design_1_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
Clk => microblaze_0_Clk,
DCE => microblaze_0_dlmb_1_CE,
DReady => microblaze_0_dlmb_1_READY,
DUE => microblaze_0_dlmb_1_UE,
DWait => microblaze_0_dlmb_1_WAIT,
D_AS => microblaze_0_dlmb_1_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
Dbg_Capture => microblaze_0_debug_CAPTURE,
Dbg_Clk => microblaze_0_debug_CLK,
Dbg_Reg_En(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Shift => microblaze_0_debug_SHIFT,
Dbg_TDI => microblaze_0_debug_TDI,
Dbg_TDO => microblaze_0_debug_TDO,
Dbg_Update => microblaze_0_debug_UPDATE,
Debug_Rst => microblaze_0_debug_RST,
ICE => microblaze_0_ilmb_1_CE,
IFetch => microblaze_0_ilmb_1_READSTROBE,
IReady => microblaze_0_ilmb_1_READY,
IUE => microblaze_0_ilmb_1_UE,
IWAIT => microblaze_0_ilmb_1_WAIT,
I_AS => microblaze_0_ilmb_1_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
Interrupt => microblaze_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => microblaze_0_interrupt_ACK(0 to 1),
Interrupt_Address(0) => microblaze_0_interrupt_ADDRESS(31),
Interrupt_Address(1) => microblaze_0_interrupt_ADDRESS(30),
Interrupt_Address(2) => microblaze_0_interrupt_ADDRESS(29),
Interrupt_Address(3) => microblaze_0_interrupt_ADDRESS(28),
Interrupt_Address(4) => microblaze_0_interrupt_ADDRESS(27),
Interrupt_Address(5) => microblaze_0_interrupt_ADDRESS(26),
Interrupt_Address(6) => microblaze_0_interrupt_ADDRESS(25),
Interrupt_Address(7) => microblaze_0_interrupt_ADDRESS(24),
Interrupt_Address(8) => microblaze_0_interrupt_ADDRESS(23),
Interrupt_Address(9) => microblaze_0_interrupt_ADDRESS(22),
Interrupt_Address(10) => microblaze_0_interrupt_ADDRESS(21),
Interrupt_Address(11) => microblaze_0_interrupt_ADDRESS(20),
Interrupt_Address(12) => microblaze_0_interrupt_ADDRESS(19),
Interrupt_Address(13) => microblaze_0_interrupt_ADDRESS(18),
Interrupt_Address(14) => microblaze_0_interrupt_ADDRESS(17),
Interrupt_Address(15) => microblaze_0_interrupt_ADDRESS(16),
Interrupt_Address(16) => microblaze_0_interrupt_ADDRESS(15),
Interrupt_Address(17) => microblaze_0_interrupt_ADDRESS(14),
Interrupt_Address(18) => microblaze_0_interrupt_ADDRESS(13),
Interrupt_Address(19) => microblaze_0_interrupt_ADDRESS(12),
Interrupt_Address(20) => microblaze_0_interrupt_ADDRESS(11),
Interrupt_Address(21) => microblaze_0_interrupt_ADDRESS(10),
Interrupt_Address(22) => microblaze_0_interrupt_ADDRESS(9),
Interrupt_Address(23) => microblaze_0_interrupt_ADDRESS(8),
Interrupt_Address(24) => microblaze_0_interrupt_ADDRESS(7),
Interrupt_Address(25) => microblaze_0_interrupt_ADDRESS(6),
Interrupt_Address(26) => microblaze_0_interrupt_ADDRESS(5),
Interrupt_Address(27) => microblaze_0_interrupt_ADDRESS(4),
Interrupt_Address(28) => microblaze_0_interrupt_ADDRESS(3),
Interrupt_Address(29) => microblaze_0_interrupt_ADDRESS(2),
Interrupt_Address(30) => microblaze_0_interrupt_ADDRESS(1),
Interrupt_Address(31) => microblaze_0_interrupt_ADDRESS(0),
M_AXI_DC_ARADDR(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
M_AXI_DC_ARBURST(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
M_AXI_DC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
M_AXI_DC_ARID(0) => microblaze_0_M_AXI_DC_ARID(0),
M_AXI_DC_ARLEN(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
M_AXI_DC_ARLOCK => microblaze_0_M_AXI_DC_ARLOCK,
M_AXI_DC_ARPROT(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
M_AXI_DC_ARQOS(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
M_AXI_DC_ARREADY => microblaze_0_M_AXI_DC_ARREADY(0),
M_AXI_DC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
M_AXI_DC_ARVALID => microblaze_0_M_AXI_DC_ARVALID,
M_AXI_DC_AWADDR(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
M_AXI_DC_AWBURST(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
M_AXI_DC_AWCACHE(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
M_AXI_DC_AWID(0) => microblaze_0_M_AXI_DC_AWID(0),
M_AXI_DC_AWLEN(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
M_AXI_DC_AWLOCK => microblaze_0_M_AXI_DC_AWLOCK,
M_AXI_DC_AWPROT(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
M_AXI_DC_AWQOS(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
M_AXI_DC_AWREADY => microblaze_0_M_AXI_DC_AWREADY(0),
M_AXI_DC_AWSIZE(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
M_AXI_DC_AWVALID => microblaze_0_M_AXI_DC_AWVALID,
M_AXI_DC_BID(0) => microblaze_0_M_AXI_DC_BID(0),
M_AXI_DC_BREADY => microblaze_0_M_AXI_DC_BREADY,
M_AXI_DC_BRESP(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
M_AXI_DC_BVALID => microblaze_0_M_AXI_DC_BVALID(0),
M_AXI_DC_RDATA(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
M_AXI_DC_RID(0) => microblaze_0_M_AXI_DC_RID(0),
M_AXI_DC_RLAST => microblaze_0_M_AXI_DC_RLAST(0),
M_AXI_DC_RREADY => microblaze_0_M_AXI_DC_RREADY,
M_AXI_DC_RRESP(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
M_AXI_DC_RVALID => microblaze_0_M_AXI_DC_RVALID(0),
M_AXI_DC_WDATA(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
M_AXI_DC_WLAST => microblaze_0_M_AXI_DC_WLAST,
M_AXI_DC_WREADY => microblaze_0_M_AXI_DC_WREADY(0),
M_AXI_DC_WSTRB(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
M_AXI_DC_WVALID => microblaze_0_M_AXI_DC_WVALID,
M_AXI_DP_ARADDR(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => microblaze_0_axi_dp_ARREADY(0),
M_AXI_DP_ARVALID => microblaze_0_axi_dp_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => microblaze_0_axi_dp_AWREADY(0),
M_AXI_DP_AWVALID => microblaze_0_axi_dp_AWVALID,
M_AXI_DP_BREADY => microblaze_0_axi_dp_BREADY,
M_AXI_DP_BRESP(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
M_AXI_DP_BVALID => microblaze_0_axi_dp_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
M_AXI_DP_RREADY => microblaze_0_axi_dp_RREADY,
M_AXI_DP_RRESP(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
M_AXI_DP_RVALID => microblaze_0_axi_dp_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
M_AXI_DP_WREADY => microblaze_0_axi_dp_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
M_AXI_DP_WVALID => microblaze_0_axi_dp_WVALID,
M_AXI_IC_ARADDR(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
M_AXI_IC_ARBURST(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
M_AXI_IC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
M_AXI_IC_ARID(0) => microblaze_0_M_AXI_IC_ARID(0),
M_AXI_IC_ARLEN(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
M_AXI_IC_ARLOCK => microblaze_0_M_AXI_IC_ARLOCK,
M_AXI_IC_ARPROT(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
M_AXI_IC_ARQOS(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
M_AXI_IC_ARREADY => microblaze_0_M_AXI_IC_ARREADY(0),
M_AXI_IC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
M_AXI_IC_ARVALID => microblaze_0_M_AXI_IC_ARVALID,
M_AXI_IC_AWADDR(31 downto 0) => microblaze_0_M_AXI_IC_AWADDR(31 downto 0),
M_AXI_IC_AWBURST(1 downto 0) => microblaze_0_M_AXI_IC_AWBURST(1 downto 0),
M_AXI_IC_AWCACHE(3 downto 0) => microblaze_0_M_AXI_IC_AWCACHE(3 downto 0),
M_AXI_IC_AWID(0) => microblaze_0_M_AXI_IC_AWID(0),
M_AXI_IC_AWLEN(7 downto 0) => microblaze_0_M_AXI_IC_AWLEN(7 downto 0),
M_AXI_IC_AWLOCK => microblaze_0_M_AXI_IC_AWLOCK,
M_AXI_IC_AWPROT(2 downto 0) => microblaze_0_M_AXI_IC_AWPROT(2 downto 0),
M_AXI_IC_AWQOS(3 downto 0) => microblaze_0_M_AXI_IC_AWQOS(3 downto 0),
M_AXI_IC_AWREADY => microblaze_0_M_AXI_IC_AWREADY(0),
M_AXI_IC_AWSIZE(2 downto 0) => microblaze_0_M_AXI_IC_AWSIZE(2 downto 0),
M_AXI_IC_AWVALID => microblaze_0_M_AXI_IC_AWVALID,
M_AXI_IC_BID(0) => microblaze_0_M_AXI_IC_BID(0),
M_AXI_IC_BREADY => microblaze_0_M_AXI_IC_BREADY,
M_AXI_IC_BRESP(1 downto 0) => microblaze_0_M_AXI_IC_BRESP(1 downto 0),
M_AXI_IC_BVALID => microblaze_0_M_AXI_IC_BVALID(0),
M_AXI_IC_RDATA(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
M_AXI_IC_RID(0) => microblaze_0_M_AXI_IC_RID(0),
M_AXI_IC_RLAST => microblaze_0_M_AXI_IC_RLAST(0),
M_AXI_IC_RREADY => microblaze_0_M_AXI_IC_RREADY,
M_AXI_IC_RRESP(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
M_AXI_IC_RVALID => microblaze_0_M_AXI_IC_RVALID(0),
M_AXI_IC_WDATA(31 downto 0) => microblaze_0_M_AXI_IC_WDATA(31 downto 0),
M_AXI_IC_WLAST => microblaze_0_M_AXI_IC_WLAST,
M_AXI_IC_WREADY => microblaze_0_M_AXI_IC_WREADY(0),
M_AXI_IC_WSTRB(3 downto 0) => microblaze_0_M_AXI_IC_WSTRB(3 downto 0),
M_AXI_IC_WVALID => microblaze_0_M_AXI_IC_WVALID,
Read_Strobe => microblaze_0_dlmb_1_READSTROBE,
Reset => rst_clk_wiz_1_100M_mb_reset,
Write_Strobe => microblaze_0_dlmb_1_WRITESTROBE
);
microblaze_0_axi_intc: component design_1_microblaze_0_axi_intc_0
port map (
interrupt_address(31 downto 0) => microblaze_0_interrupt_ADDRESS(31 downto 0),
intr(1 downto 0) => microblaze_0_intr(1 downto 0),
irq => microblaze_0_interrupt_INTERRUPT,
processor_ack(1) => microblaze_0_interrupt_ACK(0),
processor_ack(0) => microblaze_0_interrupt_ACK(1),
processor_clk => microblaze_0_Clk,
processor_rst => rst_clk_wiz_1_100M_mb_reset,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_intc_axi_ARREADY,
s_axi_arvalid => microblaze_0_intc_axi_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_intc_axi_AWREADY,
s_axi_awvalid => microblaze_0_intc_axi_AWVALID,
s_axi_bready => microblaze_0_intc_axi_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_intc_axi_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
s_axi_rready => microblaze_0_intc_axi_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_intc_axi_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
s_axi_wready => microblaze_0_intc_axi_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_intc_axi_WVALID
);
microblaze_0_axi_periph: entity work.design_1_microblaze_0_axi_periph_0
port map (
ACLK => microblaze_0_Clk,
ARESETN(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
M00_AXI_arready => microblaze_0_intc_axi_ARREADY,
M00_AXI_arvalid => microblaze_0_intc_axi_ARVALID,
M00_AXI_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
M00_AXI_awready => microblaze_0_intc_axi_AWREADY,
M00_AXI_awvalid => microblaze_0_intc_axi_AWVALID,
M00_AXI_bready => microblaze_0_intc_axi_BREADY,
M00_AXI_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
M00_AXI_bvalid => microblaze_0_intc_axi_BVALID,
M00_AXI_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
M00_AXI_rready => microblaze_0_intc_axi_RREADY,
M00_AXI_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
M00_AXI_rvalid => microblaze_0_intc_axi_RVALID,
M00_AXI_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
M00_AXI_wready => microblaze_0_intc_axi_WREADY,
M00_AXI_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
M00_AXI_wvalid => microblaze_0_intc_axi_WVALID,
M01_ACLK => microblaze_0_Clk,
M01_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M01_AXI_araddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
M01_AXI_arready => microblaze_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => microblaze_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
M01_AXI_awready => microblaze_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => microblaze_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => microblaze_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => microblaze_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => microblaze_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => microblaze_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => microblaze_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => microblaze_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => microblaze_0_Clk,
M02_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M02_AXI_araddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(12 downto 0),
M02_AXI_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(12 downto 0),
M02_AXI_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => microblaze_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => microblaze_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => microblaze_0_Clk,
M03_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M03_AXI_araddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(4 downto 0),
M03_AXI_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(4 downto 0),
M03_AXI_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => microblaze_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => microblaze_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
S00_AXI_arready(0) => microblaze_0_axi_dp_ARREADY(0),
S00_AXI_arvalid(0) => microblaze_0_axi_dp_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
S00_AXI_awready(0) => microblaze_0_axi_dp_AWREADY(0),
S00_AXI_awvalid(0) => microblaze_0_axi_dp_AWVALID,
S00_AXI_bready(0) => microblaze_0_axi_dp_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_axi_dp_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
S00_AXI_rready(0) => microblaze_0_axi_dp_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_axi_dp_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
S00_AXI_wready(0) => microblaze_0_axi_dp_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_axi_dp_WVALID
);
microblaze_0_local_memory: entity work.microblaze_0_local_memory_imp_1K0VQXK
port map (
DLMB_abus(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
DLMB_addrstrobe => microblaze_0_dlmb_1_ADDRSTROBE,
DLMB_be(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
DLMB_ce => microblaze_0_dlmb_1_CE,
DLMB_readdbus(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
DLMB_readstrobe => microblaze_0_dlmb_1_READSTROBE,
DLMB_ready => microblaze_0_dlmb_1_READY,
DLMB_ue => microblaze_0_dlmb_1_UE,
DLMB_wait => microblaze_0_dlmb_1_WAIT,
DLMB_writedbus(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
DLMB_writestrobe => microblaze_0_dlmb_1_WRITESTROBE,
ILMB_abus(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
ILMB_addrstrobe => microblaze_0_ilmb_1_ADDRSTROBE,
ILMB_ce => microblaze_0_ilmb_1_CE,
ILMB_readdbus(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
ILMB_readstrobe => microblaze_0_ilmb_1_READSTROBE,
ILMB_ready => microblaze_0_ilmb_1_READY,
ILMB_ue => microblaze_0_ilmb_1_UE,
ILMB_wait => microblaze_0_ilmb_1_WAIT,
LMB_Clk => microblaze_0_Clk,
SYS_Rst(0) => rst_clk_wiz_1_100M_bus_struct_reset(0)
);
microblaze_0_xlconcat: component design_1_microblaze_0_xlconcat_0
port map (
In0(0) => axi_timer_0_interrupt,
In1(0) => axi_ethernetlite_0_ip2intc_irpt,
dout(1 downto 0) => microblaze_0_intr(1 downto 0)
);
mii_to_rmii_0: component design_1_mii_to_rmii_0_0
port map (
mac2rmii_tx_en => axi_ethernetlite_0_MII_TX_EN,
mac2rmii_tx_er => GND_1,
mac2rmii_txd(3 downto 0) => axi_ethernetlite_0_MII_TXD(3 downto 0),
phy2rmii_crs_dv => mii_to_rmii_0_RMII_PHY_M_CRS_DV,
phy2rmii_rx_er => mii_to_rmii_0_RMII_PHY_M_RX_ER,
phy2rmii_rxd(1 downto 0) => mii_to_rmii_0_RMII_PHY_M_RXD(1 downto 0),
ref_clk => clk_wiz_1_clk_out2,
rmii2mac_col => axi_ethernetlite_0_MII_COL,
rmii2mac_crs => axi_ethernetlite_0_MII_CRS,
rmii2mac_rx_clk => axi_ethernetlite_0_MII_RX_CLK,
rmii2mac_rx_dv => axi_ethernetlite_0_MII_RX_DV,
rmii2mac_rx_er => axi_ethernetlite_0_MII_RX_ER,
rmii2mac_rxd(3 downto 0) => axi_ethernetlite_0_MII_RXD(3 downto 0),
rmii2mac_tx_clk => axi_ethernetlite_0_MII_TX_CLK,
rmii2phy_tx_en => mii_to_rmii_0_RMII_PHY_M_TX_EN,
rmii2phy_txd(1 downto 0) => mii_to_rmii_0_RMII_PHY_M_TXD(1 downto 0),
rst_n => reset_1
);
rst_clk_wiz_1_100M: component design_1_rst_clk_wiz_1_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => rst_clk_wiz_1_100M_bus_struct_reset(0),
dcm_locked => clk_wiz_1_locked,
ext_reset_in => reset_1,
interconnect_aresetn(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_1_debug_sys_rst,
mb_reset => rst_clk_wiz_1_100M_mb_reset,
peripheral_aresetn(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => microblaze_0_Clk
);
end STRUCTURE;
| gpl-3.0 | b48c857e6e3e0ce882f80a618e0a219a | 0.66704 | 2.814706 | false | false | false | false |
hoangt/PoC | src/bus/bus_Arbiter.vhdl | 2 | 5,257 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic arbiter
--
-- Description:
-- ------------------------------------
-- This module implements a generic arbiter. It currently support the
-- following arbitration strategies:
-- - Round Robin (RR)
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity bus_Arbiter is
generic (
STRATEGY : STRING := "RR"; -- RR, LOT
PORTS : POSITIVE := 1;
WEIGHTS : T_INTVEC := (0 => 1);
OUTPUT_REG : BOOLEAN := TRUE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Arbitrate : in STD_LOGIC;
Request_Vector : in STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Arbitrated : out STD_LOGIC;
Grant_Vector : out STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Grant_Index : out STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0)
);
end;
architecture rtl of bus_Arbiter is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
begin
-- Assert STRATEGY for known strings
-- ==========================================================================================================================================================
assert ((STRATEGY = "RR") OR (STRATEGY = "LOT"))
report "Unknown arbiter strategy." severity FAILURE;
-- Round Robin Arbiter
-- ==========================================================================================================================================================
genRR : if (STRATEGY = "RR") generate
signal RequestLeft : UNSIGNED(PORTS - 1 downto 0);
signal SelectLeft : UNSIGNED(PORTS - 1 downto 0);
signal SelectRight : UNSIGNED(PORTS - 1 downto 0);
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := to_slv(1, PORTS);
signal ChannelPointer_nxt : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
begin
ChannelPointer_en <= Arbitrate;
RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(Request_Vector);
SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft;
SelectRight <= (unsigned(not Request_Vector) + 1) and unsigned(Request_Vector);
ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft));
-- generate ChannelPointer register and unregistered outputs
genREG0 : if (OUTPUT_REG = FALSE) generate
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(1, PORTS);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
end if;
end if;
end process;
Arbitrated <= Arbitrate;
Grant_Vector <= ChannelPointer_nxt;
Grant_Index <= std_logic_vector(onehot2bin(ChannelPointer_nxt));
end generate;
-- generate ChannelPointer register and registered outputs
genREG1 : if (OUTPUT_REG = TRUE) generate
signal ChannelPointer_bin_d : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0) := to_slv(0, log2ceilnz(PORTS) - 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(1, PORTS);
ChannelPointer_bin_d <= to_slv(0, log2ceilnz(PORTS) - 1);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
ChannelPointer_bin_d <= std_logic_vector(onehot2bin(ChannelPointer_nxt));
end if;
end if;
end process;
Arbitrated <= Arbitrate when rising_edge(Clock);
Grant_Vector <= ChannelPointer_d;
Grant_Index <= ChannelPointer_bin_d;
end generate;
end generate;
-- Lottery Arbiter
-- ==========================================================================================================================================================
-- genLOT : if (STRATEGY = "RR") generate
-- begin
--
-- end generate;
end architecture;
| apache-2.0 | cd36765dac8d5c710071e045cb0915ff | 0.559825 | 3.854106 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_rx_fixed.vhd | 4 | 44,001 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_rx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
use mii_to_rmii_v2_0.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't
-- -- fit align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or
-- Port_name2 -- destination description of port
--
------------------------------------------------------------------------------
entity rmii_rx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0';
C_SPEED_100 : std_logic := '1'
);
port (
Rx_speed_100 : in std_logic;
------------------ System Signals ---------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII ----------------------
Rmii2Mac_rx_clk : out std_logic;
Rmii2Mac_crs : out std_logic;
Rmii2Mac_rx_dv : out std_logic;
Rmii2Mac_rx_er : out std_logic;
Rmii2Mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY ----------------------
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0)
);
end rmii_rx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_rx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should
-- be collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a
-- register. If no constants are required, simply state this in a comment
-- below the file section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- No Signal or Types
------------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------------
-- No Components
begin
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput of 10 Mb/s
--
------------------------------------------------------------------------------
RX_10_MBPS : if (C_SPEED_100 = '0') generate
--------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------
type F_LDR_TYPE is (
IDLE,
RXD_DIB0_0,
RXD_DIB0_1,
RXD_DIB0_2,
RXD_DIB0_3,
RXD_DIB0_4,
RXD_DIB0_5,
RXD_DIB0_6,
RXD_DIB0_7,
RXD_DIB0_8,
RXD_DIB0_9,
RXD_DIB1_0,
RXD_DIB1_1,
RXD_DIB1_2,
RXD_DIB1_3,
RXD_DIB1_4,
RXD_DIB1_5,
RXD_DIB1_6,
RXD_DIB1_7,
RXD_DIB1_8,
RXD_DIB1_9
);
type F_UNLDR_TYPE is (
RX_CLK_L0,
RX_CLK_L1,
RX_CLK_L2,
RX_CLK_L3,
RX_CLK_L4,
RX_CLK_L5,
RX_CLK_L6,
RX_CLK_L7,
RX_CLK_L8,
RX_CLK_L9,
RX_CLK_H0,
RX_CLK_H1,
RX_CLK_H2,
RX_CLK_H3,
RX_CLK_H4,
RX_CLK_H5,
RX_CLK_H6,
RX_CLK_H7,
RX_CLK_H8,
RX_CLK_H9
);
signal fifo_ldr_cs : F_LDR_TYPE;
signal fifo_ldr_ns : F_LDR_TYPE;
signal fifo_unldr_cs : F_UNLDR_TYPE;
signal fifo_unldr_ns : F_UNLDR_TYPE;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_er_i : std_logic;
signal rx_begin_packet : std_logic_vector(1 downto 0);
signal rx_beg_of_packet : std_logic;
signal rx_end_packet : std_logic_vector(1 downto 0);
signal rx_end_of_packet : std_logic;
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal rx_out_mux_sel : std_logic;
signal rx_out_reg_en : std_logic;
signal phy2Rmii_rxd_d1 : std_logic_vector(3 downto 0);
signal fIFO_Reset : std_logic;
signal fIFO_Write : std_logic;
signal fIFO_Data_In : std_logic_vector(4 downto 0);
signal fIFO_Read : std_logic;
signal fIFO_Data_Out : std_logic_vector(4 downto 0);
signal fIFO_Data_Exists : std_logic;
signal fifo_din_dv : std_logic;
signal rxd_smpl_dibit : std_logic;
begin
--------------------------------------------------------------------------
-- Component Instaniations
--------------------------------------------------------------------------
SRL_FIFO_I_1 : entity mii_to_rmii_v2_0.srl_fifo(IMP)
generic map (
C_DATA_BITS => 5,
C_DEPTH => 16
)
port map (
Clk => Ref_Clk, -- in
Reset => fIFO_Reset, -- in
FIFO_Write => fIFO_Write, -- in
Data_In => fIFO_Data_In, -- in
FIFO_Read => fIFO_Read, -- out
Data_Out => fIFO_Data_Out, -- out
FIFO_Full => open, -- out
Data_Exists => fIFO_Data_Exists, -- out
Addr => open
);
--------------------------------------------------------------------------
-- FIFO_RESET_PROCESS
--------------------------------------------------------------------------
FIFO_RESET_PROCESS : process ( sync_rst_n )
begin
if (sync_rst_n = C_RESET_ACTIVE) then
fIFO_Reset <= '1';
else
fIFO_Reset <= '0';
end if;
end process;
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
Rmii2Mac_crs <= rmii2Mac_crs_i;
rx_beg_of_packet <= rx_begin_packet(0) and not rx_begin_packet(1);
rx_end_of_packet <= rx_end_packet(0) and not rx_end_packet(1);
fIFO_Data_In <= fifo_din_dv & phy2Rmii_rxd_d1;
--------------------------------------------------------------------------
-- RX_CARRY_SENSE_PROCESS
--------------------------------------------------------------------------
RX_CARRY_SENSE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_crs_i <= '0';
else
rmii2Mac_crs_i <= ( phy2Rmii_crs_dv_sr(1) and rmii2Mac_crs_i ) or
(phy2Rmii_crs_dv_sr(1) and not
phy2Rmii_crs_dv_sr(21) );
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
--------------------------------------------------------------------------
RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
phy2Rmii_crs_dv_sr <= (others => '0');
else
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
Phy2Rmii_crs_dv;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_DIN_DV_PROCESS
--------------------------------------------------------------------------
FIFO_DIN_DV_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ( Sync_rst_n = '0' ) then
fifo_din_dv <= '0';
elsif ( rx_beg_of_packet = '1' ) then
fifo_din_dv <= '1';
elsif ( rx_end_of_packet = '1' ) then
fifo_din_dv <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_IN_REG_PROCESS
--------------------------------------------------------------------------
RX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
phy2Rmii_rxd_d1 <= (others => '0');
elsif (rxd_smpl_dibit = '1') then
phy2Rmii_rxd_d1(1 downto 0) <= phy2Rmii_rxd_d1(3 downto 2);
phy2Rmii_rxd_d1(3 downto 2) <= Phy2Rmii_rxd;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_BEGIN_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_BEGIN_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_end_of_packet = '1' )) then
rx_begin_packet <= "00";
else
rx_begin_packet(1) <= rx_begin_packet(0);
if ( ( Phy2Rmii_crs_dv = '1' ) and
( Phy2Rmii_rxd = "01" ) and
( rx_beg_of_packet = '0' ) ) then
rx_begin_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_END_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_beg_of_packet = '1' )) then
rx_end_packet <= "00";
else
rx_end_packet(1) <= rx_end_packet(0);
if ( ( phy2Rmii_crs_dv_sr(9) = '0' ) and
( phy2Rmii_crs_dv = '0' ) and
( rx_end_of_packet = '0' ) ) then
rx_end_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_ERROR_PROCESS
--------------------------------------------------------------------------
RX_ERROR_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_rx_er_i <= '0';
else
rmii2Mac_rx_er_i <= Phy2Rmii_rx_er;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_OUT_REG_PROCESS
--------------------------------------------------------------------------
RX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Mac_rx_er <= '0';
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
elsif (rx_out_reg_en = '1') then
if (rx_out_mux_sel = '1') then
Rmii2Mac_rx_er <= rmii2Mac_rx_er_i;
Rmii2Mac_rx_dv <= fIFO_Data_Out(4);
Rmii2Mac_rxd <= fIFO_Data_Out(3 downto 0);
else
Rmii2Mac_rx_er <= rmii2Mac_rx_er_i;
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- STATE_MACHS_SYNC_PROCESS
--------------------------------------------------------------------------
STATE_MACHS_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
fifo_ldr_cs <= IDLE;
fifo_unldr_cs <= RX_CLK_L0;
else
fifo_ldr_cs <= fifo_ldr_ns;
fifo_unldr_cs <= fifo_unldr_ns;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_LOADER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_LOADER_NEXT_STATE_PROCESS : process (
fifo_ldr_cs,
fifo_din_dv
)
begin
case fifo_ldr_cs is
when IDLE =>
if (fifo_din_dv = '1') then
fifo_ldr_ns <= RXD_DIB0_0;
else
fifo_ldr_ns <= IDLE;
end if;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_0 =>
fifo_ldr_ns <= RXD_DIB0_1;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_1 =>
fifo_ldr_ns <= RXD_DIB0_2;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_2 =>
fifo_ldr_ns <= RXD_DIB0_3;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_3 =>
fifo_ldr_ns <= RXD_DIB0_4;
rxd_smpl_dibit <= '1';
fIFO_Write <= '0';
when RXD_DIB0_4 =>
fifo_ldr_ns <= RXD_DIB0_5;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_5 =>
fifo_ldr_ns <= RXD_DIB0_6;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_6 =>
fifo_ldr_ns <= RXD_DIB0_7;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_7 =>
fifo_ldr_ns <= RXD_DIB0_8;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_8 =>
fifo_ldr_ns <= RXD_DIB0_9;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_9 =>
fifo_ldr_ns <= RXD_DIB1_0;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_0 =>
fifo_ldr_ns <= RXD_DIB1_1;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_1 =>
fifo_ldr_ns <= RXD_DIB1_2;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_2 =>
fifo_ldr_ns <= RXD_DIB1_3;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_3 =>
fifo_ldr_ns <= RXD_DIB1_4;
rxd_smpl_dibit <= '1';
fIFO_Write <= '0';
when RXD_DIB1_4 =>
fifo_ldr_ns <= RXD_DIB1_5;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_5 =>
fifo_ldr_ns <= RXD_DIB1_6;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_6 =>
fifo_ldr_ns <= RXD_DIB1_7;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_7 =>
fifo_ldr_ns <= RXD_DIB1_8;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_8 =>
fifo_ldr_ns <= RXD_DIB1_9;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_9 =>
if (fifo_din_dv = '1') then
fifo_ldr_ns <= RXD_DIB0_0;
else
fifo_ldr_ns <= IDLE;
end if;
rxd_smpl_dibit <= '0';
fIFO_Write <= '1';
end case;
end process;
--------------------------------------------------------------------------
-- FIFO_UNLOADER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_UNLOADER_NEXT_STATE_PROCESS : process (
fifo_unldr_cs,
fIFO_Data_Exists
)
begin
case fifo_unldr_cs is
when RX_CLK_L0 =>
fifo_unldr_ns <= RX_CLK_L1;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L1 =>
fifo_unldr_ns <= RX_CLK_L2;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L2 =>
fifo_unldr_ns <= RX_CLK_L3;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L3 =>
fifo_unldr_ns <= RX_CLK_L4;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L4 =>
fifo_unldr_ns <= RX_CLK_L5;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L5 =>
fifo_unldr_ns <= RX_CLK_L6;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L6 =>
fifo_unldr_ns <= RX_CLK_L7;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L7 =>
fifo_unldr_ns <= RX_CLK_L8;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L8 =>
fifo_unldr_ns <= RX_CLK_L9;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L9 =>
fifo_unldr_ns <= RX_CLK_H0;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H0 =>
fifo_unldr_ns <= RX_CLK_H1;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H1 =>
fifo_unldr_ns <= RX_CLK_H2;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H2 =>
fifo_unldr_ns <= RX_CLK_H3;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H3 =>
fifo_unldr_ns <= RX_CLK_H4;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H4 =>
fifo_unldr_ns <= RX_CLK_H5;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H5 =>
fifo_unldr_ns <= RX_CLK_H6;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H6 =>
fifo_unldr_ns <= RX_CLK_H7;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H7 =>
fifo_unldr_ns <= RX_CLK_H8;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= fIFO_Data_Exists;
rx_out_mux_sel <= '0';
when RX_CLK_H8 =>
fifo_unldr_ns <= RX_CLK_H9;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H9 =>
fifo_unldr_ns <= RX_CLK_L0;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '1';
fIFO_Read <= '0';
rx_out_mux_sel <= '1';
end case;
end process;
end generate;
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput of 100 Mb/s
--
------------------------------------------------------------------------------
RX_100_MBPS : if (C_SPEED_100 = '1') generate
--------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------
type F_LDR_TYPE is (
IDLE_NO_WR,
RX_NO_WR,
RX_WR
);
signal fifo_ldr_cs : F_LDR_TYPE;
signal fifo_ldr_ns : F_LDR_TYPE;
type FLSHR_TYPE is (
FLSHR_IDLE_L,
FLSHR_IDLE_H,
RX100_CLK_L,
RX100_CLK_H
);
signal fifo_flshr_cs : FLSHR_TYPE;
signal fifo_flshr_ns : FLSHR_TYPE;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_er_d3 : std_logic;
signal rmii2Mac_rx_er_d2 : std_logic;
signal rmii2Mac_rx_er_d1 : std_logic;
signal rx_begin_packet : std_logic_vector(1 downto 0);
signal rx_beg_of_packet : std_logic;
signal rx_end_packet : std_logic_vector(1 downto 0);
signal rx_end_of_packet : std_logic;
signal phy2Rmii_crs_dv_d4 : std_logic;
signal phy2Rmii_crs_dv_d3 : std_logic;
signal phy2Rmii_crs_dv_d2 : std_logic;
signal phy2Rmii_crs_dv_d1 : std_logic;
signal rx_out_mux_sel : std_logic;
signal rx_out_reg_en : std_logic;
signal phy2Rmii_rxd_d3 : std_logic_vector(3 downto 0);
signal phy2Rmii_rxd_d2 : std_logic_vector(3 downto 0);
signal phy2Rmii_rxd_d1 : std_logic_vector(3 downto 0);
signal fIFO_Reset : std_logic;
signal fIFO_Write : std_logic;
signal fIFO_Data_In : std_logic_vector(4 downto 0);
signal fIFO_Read : std_logic;
signal fIFO_Data_Out : std_logic_vector(4 downto 0);
signal fIFO_Full : std_logic;
signal fIFO_Data_Exists : std_logic;
signal fifo_din_dv : std_logic;
--CR#618005
attribute shreg_extract : string;
attribute shreg_extract of phy2Rmii_crs_dv_d1 : signal is "no";
attribute shreg_extract of phy2Rmii_rxd_d1 : signal is "no";
attribute shreg_extract of rmii2Mac_rx_er_d1 : signal is "no";
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component srl_fifo
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end component;
begin
--------------------------------------------------------------------------
-- Component Instaniations
--------------------------------------------------------------------------
I_SRL_FIFO : srl_fifo
generic map (
C_DATA_BITS => 5,
C_DEPTH => 16
)
port map (
Clk => Ref_Clk,
Reset => fIFO_Reset,
FIFO_Write => fIFO_Write,
Data_In => fIFO_Data_In,
FIFO_Read => fIFO_Read,
Data_Out => fIFO_Data_Out,
FIFO_Full => fIFO_Full,
Data_Exists => fIFO_Data_Exists,
Addr => open
);
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
Rmii2Mac_crs <= rmii2Mac_crs_i;
rx_beg_of_packet <= rx_begin_packet(0) and not rx_begin_packet(1);
rx_end_of_packet <= rx_end_packet(0) and not rx_end_packet(1);
fIFO_Reset <= not sync_rst_n;
fIFO_Data_In <= fifo_din_dv & phy2Rmii_rxd_d3;
--------------------------------------------------------------------------
-- RX_CARRY_SENSE_PROCESS
--------------------------------------------------------------------------
RX_CARRY_SENSE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_crs_i <= '0';
else
rmii2Mac_crs_i <= ( Phy2Rmii_crs_dv_d2 and rmii2Mac_crs_i ) or
( Phy2Rmii_crs_dv_d2 and not phy2Rmii_crs_dv_d4 );
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
--------------------------------------------------------------------------
RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
phy2Rmii_crs_dv_d4 <= '0';
phy2Rmii_crs_dv_d3 <= '0';
phy2Rmii_crs_dv_d2 <= '0';
phy2Rmii_crs_dv_d1 <= '0';
else
phy2Rmii_crs_dv_d4 <= phy2Rmii_crs_dv_d3;
phy2Rmii_crs_dv_d3 <= phy2Rmii_crs_dv_d2;
phy2Rmii_crs_dv_d2 <= phy2Rmii_crs_dv_d1;
phy2Rmii_crs_dv_d1 <= Phy2Rmii_crs_dv;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_DIN_DV_PROCESS
--------------------------------------------------------------------------
FIFO_DIN_DV_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ( Sync_rst_n = '0' ) then
fifo_din_dv <= '0';
elsif ( rx_beg_of_packet = '1') then
fifo_din_dv <= '1';
elsif ( ( Phy2Rmii_crs_dv_d2 = '0' ) and
( phy2Rmii_crs_dv_d3 = '0' ) ) then
fifo_din_dv <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_IN_REG_PROCESS
--------------------------------------------------------------------------
RX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
phy2Rmii_rxd_d3 <= (others => '0');
phy2Rmii_rxd_d2 <= (others => '0');
phy2Rmii_rxd_d1 <= (others => '0');
else
phy2Rmii_rxd_d3 <= phy2Rmii_rxd_d2;
phy2Rmii_rxd_d2 <= phy2Rmii_rxd_d1;
phy2Rmii_rxd_d1(1 downto 0) <= phy2Rmii_rxd_d1(3 downto 2);
phy2Rmii_rxd_d1(3 downto 2) <= Phy2Rmii_rxd;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_BEGIN_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_BEGIN_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_end_of_packet = '1' )) then
rx_begin_packet <= "00";
else
rx_begin_packet(1) <= rx_begin_packet(0);
if ( ( Phy2Rmii_crs_dv_d2 = '1' ) and
( Phy2Rmii_rxd_d2(3 downto 2) = "01" ) and
( rx_beg_of_packet = '0' ) ) then
rx_begin_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_END_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_beg_of_packet = '1' )) then
rx_end_packet <= "00";
else
rx_end_packet(1) <= rx_end_packet(0);
if ( ( Phy2Rmii_crs_dv_d2 = '0' ) and
( phy2Rmii_crs_dv_d3 = '0' ) and
( rx_end_of_packet = '0' ) ) then
rx_end_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_ERROR_PROCESS
--------------------------------------------------------------------------
RX_ERROR_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_rx_er_d3 <= '0';
rmii2Mac_rx_er_d2 <= '0';
rmii2Mac_rx_er_d1 <= '0';
else
rmii2Mac_rx_er_d3 <= rmii2Mac_rx_er_d2;
rmii2Mac_rx_er_d2 <= rmii2Mac_rx_er_d1;
rmii2Mac_rx_er_d1 <= Phy2Rmii_rx_er;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_OUT_REG_PROCESS
--------------------------------------------------------------------------
RX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Mac_rx_er <= '0';
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
elsif (rx_out_reg_en = '1') then
if ( rx_out_mux_sel = '1' ) then
Rmii2Mac_rx_er <= rmii2Mac_rx_er_d3;
Rmii2Mac_rx_dv <= '1';
Rmii2Mac_rxd <= fIFO_Data_Out(3 downto 0);
else
Rmii2Mac_rx_er <= '0';
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- STATE_MACHS_SYNC_PROCESS
--------------------------------------------------------------------------
STATE_MACHS_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
fifo_ldr_cs <= IDLE_NO_WR;
fifo_flshr_cs <= FLSHR_IDLE_L;
else
fifo_ldr_cs <= fifo_ldr_ns;
fifo_flshr_cs <= fifo_flshr_ns;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_LOADER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_LOADER_NEXT_STATE_PROCESS : process (
fifo_ldr_cs,
rx_beg_of_packet,
rx_end_of_packet
)
begin
case fifo_ldr_cs is
when IDLE_NO_WR =>
if (rx_beg_of_packet = '1') then
fifo_ldr_ns <= RX_WR;
else
fifo_ldr_ns <= IDLE_NO_WR;
end if;
fIFO_Write <= '0';
when RX_NO_WR =>
if (rx_end_of_packet = '1') then
fifo_ldr_ns <= IDLE_NO_WR;
else
fifo_ldr_ns <= RX_WR;
end if;
fIFO_Write <= '0';
when RX_WR =>
if (rx_end_of_packet = '1') then
fifo_ldr_ns <= IDLE_NO_WR;
fIFO_Write <= '0';
else
fifo_ldr_ns <= RX_NO_WR;
fIFO_Write <= '1';
end if;
end case;
end process;
--------------------------------------------------------------------------
-- FIFO_FLUSHER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_FLUSHER_NEXT_STATE_PROCESS : process (
fifo_flshr_cs,
fIFO_Data_Exists
)
begin
case fifo_flshr_cs is
when FLSHR_IDLE_L =>
if (fIFO_Data_Exists = '1') then
fifo_flshr_ns <= RX100_CLK_H;
else
fifo_flshr_ns <= FLSHR_IDLE_H;
end if;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when FLSHR_IDLE_H =>
if (fIFO_Data_Exists = '1') then
fifo_flshr_ns <= RX100_CLK_L;
else
fifo_flshr_ns <= FLSHR_IDLE_L;
end if;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '1';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX100_CLK_L =>
if (fIFO_Data_Exists = '0') then
fifo_flshr_ns <= FLSHR_IDLE_H;
else
fifo_flshr_ns <= RX100_CLK_H;
end if;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '1';
when RX100_CLK_H =>
if (fIFO_Data_Exists = '0') then
fifo_flshr_ns <= FLSHR_IDLE_L;
else
fifo_flshr_ns <= RX100_CLK_L;
end if;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '1';
fIFO_Read <= '1';
rx_out_mux_sel <= '1';
end case;
end process;
end generate;
end simulation;
| gpl-3.0 | 854e8aedc10194732e87158c3a7a2caf | 0.35606 | 4.279004 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/intc_core.vhd | 4 | 135,641 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v3.1
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- ~~~~~~
-- - Initial release of v2.00.a
-- - Updated by pkaruna
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support in v3.1 version of the core
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_misc.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Bus2ip_rdce -- Read
-- Bus2ip_wrce -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-- Processor_clk -- input same as processor clock
-- Processor_rst -- input same as processor reset
-- Processor_ack -- input Connected to processor ACK
-- Interrupt_address -- output Connected to processor interrupt address pins
-- Interrupt_address_in -- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- Processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_FAMILY : string := "virtex6";
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 0;
C_HAS_FAST : integer range 0 to 1 := 0;
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
);
port
(
-- Inputs
Clk : in std_logic; --- AXI Clock
Rst_n : in std_logic; --- active low AXI Reset
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(6 downto 0);
Bus2ip_rdce : in std_logic_vector(0 to 16);
Bus2ip_wrce : in std_logic_vector(0 to 16);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- active high MB rst, reset from MicroBlaze
Irq : out std_logic;
Processor_ack : in std_logic_vector(1 downto 0); --- added for fast interrupt mode
Interrupt_address : out std_logic_vector(31 downto 0); --- added for fast interrupt mode
--
Interrupt_address_in : in std_logic_vector(31 downto 0);
Processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Component Declarations
-- ======================
constant C_NUM_INTR : integer := C_NUM_INTR_INPUTS + C_NUM_SW_INTR;
constant RESET_ACTIVE : std_logic := '0';
CONSTANT INDEX_BIT : INTEGER := INTEGER(CEIL(LOG2(REAL(C_NUM_INTR+1))));
constant MICROBLAZE_FIXED_ADDRESS : std_logic_vector := X"00000010";
CONSTANT IVR_ALL_ONES : std_logic_vector(INDEX_BIT-1 downto 0) := (others => '1');
--- *** --- Decision is pending for logic used - mail sent to Bsb on 3rd Oct, 2012
CONSTANT C_USE_METHOD : integer := 1;
--- *** ---
-- Signal declaration
-- ==================
signal processor_rst_n : std_logic;
signal ack_b01 : std_logic;
signal first_ack : std_logic;
signal first_ack_active : std_logic;
signal second_ack : std_logic;
signal first_ack_sync : std_logic;
signal second_ack_sync : std_logic;
signal second_ack_sync_d1 : std_logic;
signal second_ack_sync_d2 : std_logic;
signal second_ack_sync_d3 : std_logic;
signal second_ack_sync_mb_clk : std_logic;
signal Irq_i : std_logic;
signal ivr_data_in : std_logic_vector(INDEX_BIT - 1 downto 0);
signal wr_data_int : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ivr : std_logic_vector(INDEX_BIT - 1 downto 0);
signal ivr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ilr : std_logic_vector(INDEX_BIT downto 0);
signal ilr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal imr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal imr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen_i : std_logic;
signal irq_gen : std_logic;
signal irq_gen_sync : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or_i : std_logic;
signal ack_or : std_logic;
signal ack_or_sync : std_logic;
signal read_ivar : std_logic;
signal write_ivar : std_logic;
signal isr_or : std_logic;
signal ivar_index_mb_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal ivar_index_axi_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal in_idle : std_logic;
signal in_idle_axi_clk : std_logic;
signal idle_and_irq : std_logic;
signal idle_and_irq_d1 : std_logic;
signal ivar_index_sample_en_i : std_logic;
signal ivar_index_sample_en : std_logic;
signal ivar_index_sample_en_mb_clk : std_logic;
signal irq_dis_sample_mb_clk : std_logic;
signal ivar_rd_addr_mb_clk : std_logic_vector(4 downto 0);
signal mer_0_sync : std_logic;
--signal bus2ip_rdce_fast : std_logic_vector(0 to 31);
--signal bus2ip_wrce_fast : std_logic_vector(0 to 31);
signal bus2ip_rdce_fast : std_logic;
signal bus2ip_wrce_fast : std_logic;
signal ivar_rd_data_axi_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivar_rd_data_mb_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_ored_30_0_bits : std_logic;
signal Interrupt_address_in_reg_int : std_logic_vector(31 downto 0);
signal intr_31_deassert_info : std_logic;
signal intr_31_deasserted_d1 : std_logic;
signal intr_31_deasserted : std_logic;
-- --------------------------------------------------------------------------------------
-- -- Function to find logic OR of 32 bit width vector
-- --------------------------------------------------------------------------------------
-- Function OR32_VEC2STDLOGIC (vec_in : std_logic_vector) return std_logic is
-- variable or_out : std_logic := '0';
-- begin
-- for i in 0 to 31 loop
-- or_out := vec_in(i) or or_out;
-- end loop;
-- return or_out;
-- end function Or32_vec2stdlogic;
-- --------------------------------------------------------------------------------------
FUNCTION calc_ivar_ram_addr_bits (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 5;
else
RETURN 4;
end if;
end FUNCTION calc_ivar_ram_addr_bits;
-------------------------------------
FUNCTION calc_ivar_ram_depth (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 32;
else
RETURN 16;
end if;
end FUNCTION calc_ivar_ram_depth;
---------------------------------
CONSTANT IVAR_MEM_ADDR_LINES : INTEGER := calc_ivar_ram_addr_bits (C_NUM_INTR);
CONSTANT IVAR_MEM_DEPTH : INTEGER := calc_ivar_ram_depth (C_NUM_INTR);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
-- Begin of architecture
begin
-----
-- active low reset
processor_rst_n <= not Processor_rst;
read <= bus2ip_rdce(0) or -- for ISR
bus2ip_rdce(1) or -- for IPR
bus2ip_rdce(2) or -- for IER
bus2ip_rdce(6) or -- for IVR
bus2ip_rdce(7) or -- for MER
bus2ip_rdce(8) or -- for IMR
bus2ip_rdce(9); -- for ILR
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR - 1 downto 0);
-------------------------------------------------------------------------
-- GENERATING IVAR READ ENABLES
-------------------------------------------------------------------------
bus2ip_rdce_fast <= bus2ip_rdce(16);
bus2ip_wrce_fast <= bus2ip_wrce(16);
write_ivar <= bus2ip_wrce_fast;
read_ivar <= bus2ip_rdce_fast;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------
NO_CASCADE_MASTER_MODE : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------------------------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
-----------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
-----------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
-----------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
-----------------------------------------
end generate NO_CASCADE_MASTER_MODE;
-----------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) & -- to avoide any delay the processor is
(Processor_ack(0) and (not isr_ored_30_0_bits)) ; -- simply passed to below modules
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
--------------------------------------------
end generate ACK_EN_SYNC_EN_GEN;
--------------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
--------------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
--------------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
--------------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
--------------------------------------------
end generate CASCADE_MASTER_MODE_10;
-----------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
------------------------------------
end generate CASCADE_MASTER_MODE_11;
-----------------------------
end generate ACK_EN_SYNC_ON_MB_CLK_GEN;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
NO_CASCADE_MASTER : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate NO_CASCADE_MASTER;
-------------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate CASCADE_MASTER_MODE_10;
-------------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')-- and
--(isr(31) = '0') and
--(ier(31) = '0') -- and
-- (isr_ored_30_0_bits = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
-----------------------------------
end generate CASCADE_MASTER_MODE_11;
-------------------------------
----------------------------------------
end generate ACK_EN_SYNC_ON_AXI_CLK_GEN;
SECOND_ACK_FAST_0_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
second_ack_sync_mb_clk <= ack_or_sync;
Processor_ack_out <= (others => '0');
end generate SECOND_ACK_FAST_0_GEN;
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (bus2ip_wrce(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((bus2ip_wrce(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
-----------------------------------
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
-----------------------------------
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
-----
begin
-----
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (bus2ip_wrce(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
-----
begin
-----
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
-----
begin
-----
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (bus2ip_wrce(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or bus2ip_wrce(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR - 1) generate
-----
begin
-----
--IAR_NORMAL_MODE_GEN: if ((C_HAS_FAST = 0) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
IAR_NORMAL_MODE_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_NORMAL_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1')) then
iar(i) <= wr_data_int(i);
else
iar(i) <= '0';
end if;
end if;
end process IAR_NORMAL_BIT_P;
-----------------------------------
end generate IAR_NORMAL_MODE_GEN;
---------------------------------
IAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_FAST_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1') and (imr(i) = '0')) then
iar(i) <= wr_data_int(i);
elsif (imr(i) = '1') then
if (((C_KIND_OF_INTR(i) = '1') and (first_ack_sync = '1')) or
((C_KIND_OF_INTR(i) = '0') and (second_ack_sync = '1'))) then
if (i = TO_INTEGER(unsigned(ivar_index_axi_clk))) then -- -- clearing IAR based on Processor_ack in FAST_INTERRUPT mode
iar(i) <= '1';
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
end if;
end process IAR_FAST_BIT_P;
-----------------------------------
end generate IAR_FAST_MODE_GEN;
-------------------------------
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (bus2ip_wrce(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (i < C_NUM_INTR_INPUTS) then
if (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
elsif (i >= C_NUM_INTR_INPUTS) then
if (bus2ip_wrce(0) = '1') then
isr(i) <= Wr_data(i);
end if;
end if;
end if;
end process ISR_P;
----------------------------------------------------------------------
-- Process IMR_P for generating IMR(Interrrupt Mode Register) Register
----------------------------------------------------------------------
IMR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IMR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
imr(i) <= '0';
elsif bus2ip_wrce(8) = '1' then
imr(i) <= wr_data_int(i);
end if;
end if;
end process IMR_P;
end generate IMR_FAST_MODE_GEN;
-----------------------------------
end generate REG_GEN;
---------------------
---------------------------------------------------------------------------
-- Proces IVAR_REG_P for generating IVAR Registers
---------------------------------------------------------------------------
IVAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IVAR_REG_MEM_MB_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 0) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Processor_clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_MB_CLK_GEN;
IVAR_REG_MEM_AXI_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 1) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_AXI_CLK_GEN;
end generate IVAR_FAST_MODE_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR /= C_DWIDTH) generate
-----
begin
-----
ier_out(C_NUM_INTR - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_out(C_NUM_INTR - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
imr_out(C_NUM_INTR - 1 downto 0) <= imr;
imr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-1 downto 0));
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR = C_DWIDTH) generate
-----
begin
-----
ier_out <= ier;
isr_out <= isr;
imr_out <= imr;
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-2 downto 0));
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
ilr_out (INDEX_BIT-1 downto 0) <= ilr(INDEX_BIT - 1 downto 0);
ilr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ilr(INDEX_BIT) = '1' else
(others => '0');
ivr_out (INDEX_BIT-1 downto 0) <= ivr;
ivr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ((ivr = IVR_ALL_ONES)) else
(others => '0');
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
------------------
end generate IPR_GEN;
---------------------
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1 or C_HAS_FAST = 1)
--------------------------------------------------------------------------
IVR_GEN: if ((C_HAS_IVR = 1) or (C_HAS_FAST = 1)) generate
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier) is
variable ivr_in : std_logic_vector(INDEX_BIT - 1 downto 0)
:= (others => '1');
-----
begin
-----
for i in 0 to (C_NUM_INTR - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
--ivr_in := CONV_STD_LOGIC_VECTOR(i, INDEX_BIT);
ivr_in := std_logic_vector(to_unsigned(i, INDEX_BIT));
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ONES if (C_HAS_IVR = 0) and (C_HAS_FAST = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if ((C_HAS_IVR = 0) and (C_HAS_FAST = 0)) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- Generate ILR if (C_HAS_ILR = 1)
--------------------------------------------------------------------------
ILR_GEN: if (C_HAS_ILR = 1) generate
begin
----------------------------------------------------------------------
-- Process ILR_P for generating ILR register
----------------------------------------------------------------------
ILR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ilr <= (others => '1');
elsif (bus2ip_wrce(9) = '1') then
ilr <= Wr_data(INDEX_BIT downto 0);
end if;
end if;
end process ILR_P;
end generate ILR_GEN;
--------------------------------------------------------------------------
-- Assign ILR ALL ONES if (C_HAS_ILR = 0)
--------------------------------------------------------------------------
ILR_NO_GEN: if (C_HAS_ILR = 0) generate
begin
ilr <= (others => '1');
end generate ILR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
signal synced_intr : std_logic := '0';
begin
-----------------------------------------------------------------------
-- Generating the synchronization flip-flops if C_ASYNC_INTR(i) = 1
-----------------------------------------------------------------------
ASYNC_GEN: if C_ASYNC_INTR(i) = '1' and C_NUM_SYNC_FF > 0 generate
signal intr_ff : std_logic_vector(0 to C_NUM_SYNC_FF - 1) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of intr_ff : signal is "TRUE";
begin
--------------------------------------------
-- Process SYNC_P to synchronize hw_intr
--------------------------------------------
SYNC_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
intr_ff(0) <= Intr(i);
for k in intr_ff'left to intr_ff'right - 1 loop
intr_ff(k + 1) <= intr_ff(k);
end loop;
end if;
end process SYNC_P;
synced_intr <= intr_ff(intr_ff'right);
------------------------------
end generate ASYNC_GEN;
-----------------------------------------------------------------------
-- No synchronization flip-flops if C_ASYNC_INTR(i) = 0
-----------------------------------------------------------------------
SYNC_GEN: if C_ASYNC_INTR(i) = '0' or C_NUM_SYNC_FF = 0 generate
begin
synced_intr <= Intr(i);
end generate SYNC_GEN;
-----------------------------------------------------------------------
-- Generating the edge triggered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if C_KIND_OF_INTR(i) = '1' generate
signal intr_d1 : std_logic;
signal intr_edge : std_logic;
begin
----------------------------------------------------------------
-- Process REG_INTR_EDGE_P to register the interrupt signal edge
----------------------------------------------------------------
REG_INTR_EDGE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if Rst_n = RESET_ACTIVE then
intr_d1 <= not C_KIND_OF_EDGE(i);
else
intr_d1 <= synced_intr;
end if;
end if;
end process REG_INTR_EDGE_P;
-- Creating one-shot edge triggered interrupt
intr_edge <= '1' when (synced_intr = C_KIND_OF_EDGE(i)) and
(intr_d1 = not C_KIND_OF_EDGE(i)) else
'0';
-----------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge triggered interrupt
-----------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if Clk'event and Clk='1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif (intr_edge = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
--------------------------
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if C_KIND_OF_INTR(i) = '0' generate
begin
------------------------------------------------------------------
-- Process LVL_P to generate hw_intr (active high or low)
------------------------------------------------------------------
LVL_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif synced_intr = C_KIND_OF_LVL(i) then
hw_intr(i) <= '1';
end if;
end if;
end process LVL_P;
------------------
end generate LVL_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
-----
begin
-----
irq_gen_i<= isr(0) and ier(0) and ilr(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier, ilr) is
variable ilr_value : integer;
variable irq_gen_int : std_logic;
-----
begin
-----
ilr_value := TO_INTEGER(unsigned( ilr(INDEX_BIT - 1 downto 0) ));
irq_gen_int := '0';
for i in 0 to (isr'length - 1) loop
if (C_HAS_ILR = 1) then
exit when (i = ilr_value) and (ilr(INDEX_BIT) = '0');
end if;
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen_i <= irq_gen_int;
end process IRQ_GEN_P;
----------------------
end generate IRQ_MULTI_INTR_GEN;
--------------------------------
-- Registering irq_gen_i as it will be going through double synchronizer
IRQ_GEN_REG_P : Process(Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_gen <= '0';
else
irq_gen <= irq_gen_i;
end if;
end if;
end process IRQ_GEN_REG_P;
--------------------------
--------------------------------------------------------------
-- Synchronizing irq_gen
--------------------------------------------------------------
IRQ_GEN_SYNC_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
signal irq_gen_sync_vec : std_logic_vector(0 downto 0);
-----
begin
-----
-- Synchronize irq_gen to Processor clock domain
IRQ_GEN_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(irq_gen),
SYNC_DATA_OUT => irq_gen_sync_vec
);
irq_gen_sync <= irq_gen_sync_vec(0);
end generate IRQ_GEN_SYNC_GEN;
IRQ_GEN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
irq_gen_sync <= irq_gen;
end generate IRQ_GEN_SYNC_DISABLE_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
IN_IDLE_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
signal in_idle_axi_clk_vec : std_logic_vector(0 downto 0);
begin
IN_IDLE_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Clk,
RESET_2_n => Rst_n,
DATA_IN => scalar_to_vector(in_idle),
SYNC_DATA_OUT => in_idle_axi_clk_vec
);
in_idle_axi_clk <= in_idle_axi_clk_vec(0);
end generate IN_IDLE_SYNC_EN_GEN;
---------------------------------
IN_IDLE_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
in_idle_axi_clk <= in_idle;
end generate IN_IDLE_SYNC_DISABLE_GEN;
--------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen_i and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
------------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
------------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
------------------------------------
IVAR_INDEX_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ivar_index_sample_en,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ivar_index_sample_en_mb_clk
);
end generate IVAR_INDEX_SYNC_EN_GEN;
------------------------------------
IVAR_INDEX_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
end generate IVAR_INDEX_SYNC_DISABLE_GEN;
------------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr_data_in;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
------------------------------------
IVAR_INDEX_MB_REG_P : Process(Processor_clk)
begin
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
ivar_index_mb_clk <= (others => '0');
else
if (ivar_index_sample_en_mb_clk = '1') then
ivar_index_mb_clk <= ivar_index_axi_clk;
else
ivar_index_mb_clk <= ivar_index_mb_clk;
end if;
end if;
end if;
end process IVAR_INDEX_MB_REG_P;
------------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
------------------------------------
end generate IVAR_INDEX_SYNC_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen_i;
IDLE_NOT_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_NOT_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
IRQ_DIS_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => irq_dis_sample,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => irq_dis_sample_mb_clk
);
end generate IRQ_DIS_SYNC_EN_GEN;
IRQ_DIS_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_DISABLE_GEN;
end generate IRQ_DIS_SYNC_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
in_idle_axi_clk <= in_idle;
------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
--------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
--------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
--------------------------------
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
--------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
--------------------------------
ivar_index_mb_clk <= ivar_index_axi_clk;
--------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
end generate IVAR_INDEX_SYNC_ON_AXI_CLK_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen;
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_ON_AXI_CLK_GEN;
NO_IRQ_DIS_SYNC: if (C_HAS_FAST = 0) or (C_HAS_ILR = 0) generate
begin
irq_dis_sample_mb_clk <= '0';
end generate NO_IRQ_DIS_SYNC;
----------------------------------------------------------------------
-- MER_0_DOUBLE_SYNC_I to synchronize MER(0) with Processor_clk
----------------------------------------------------------------------
MER_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
signal mer_0_sync_vec : std_logic_vector(0 downto 0);
begin
--Synchronize mer(0) to Processor clock domain
MER_0_DOUBLE_SYNC_I: entity axi_intc_v4_1.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(mer(0)),
SYNC_DATA_OUT => mer_0_sync_vec
);
mer_0_sync <= mer_0_sync_vec(0);
end generate MER_SYNC_EN_GEN;
------------------------------
MER_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
mer_0_sync <= mer(0);
end generate MER_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
-- Level IRQ generation if C_HAS_FAST is 1
IRQ_LEVEL_FAST_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((ivar_index_sample_en_mb_clk = '1')) then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-----------------------------
GEN_LEVEL_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
-----------------------------
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-- local signal declaration
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
end generate IRQ_LEVEL_FAST_ON_MB_CLK_GEN;
------------------------------------------------------------------
IRQ_LEVEL_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-------------------------------
GEN_LEVEL_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
----------------------------
-- Interrupt_address <= ivar_rd_data_mb_clk;
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
-------------------------------------------
end generate IRQ_LEVEL_FAST_ON_AXI_CLK_GEN;
-- Level IRQ generation if C_HAS_FAST is 0
IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Processor_clk) is
begin
if(Processor_clk'event and Processor_clk = '1') then
if ((processor_rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
-------------------------------------
Interrupt_address <= (others => '0');
-------------------------------------
end generate IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN;
IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_ON_AXI_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_ON_AXI_P;
Interrupt_address <= (others => '0');
end generate IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN;
end generate IRQ_LEVEL_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
ack_or_i <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or_i <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
----------------------------------
ACK_OR_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ack_or <= '0';
else
ack_or <= ack_or_i;
end if;
end if;
end process ACK_OR_REG_P;
-------------------------
ACK_OR_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
ACK_OR_PULSE_SYNC_I: entity axi_intc_v4_1.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ack_or,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ack_or_sync
);
end generate ACK_OR_SYNC_EN_GEN;
ACK_OR_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
ack_or_sync <= ack_or;
end generate ACK_OR_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
IRQ_EDGE_FAST_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
GEN_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------
end generate IRQ_EDGE_FAST_GEN;
IRQ_EDGE_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
---------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
---------------------------
GEN_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-----------------------
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------------------
end generate IRQ_EDGE_FAST_ON_AXI_CLK_GEN;
--IRQ_EDGE_NORMAL_GEN: if (C_HAS_FAST = 0) generate
IRQ_EDGE_NO_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_NO_MB_CLK_GEN;
IRQ_EDGE_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK, WAIT_SYNC);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
if (C_DISABLE_SYNCHRONIZERS = 1) then
current_state <= IDLE;
else
current_state <= WAIT_SYNC;
end if;
else
current_state <= WAIT_ACK;
end if;
when WAIT_SYNC => current_state <= IDLE;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_MB_CLK_GEN;
--end generate IRQ_EDGE_NORMAL_GEN;
end generate IRQ_EDGE_GEN;
--Read data in Normal mode (C_HAS_FAST = 0)
OUTPUT_DATA_NORMAL_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out,
ilr_out, ivr_out, mer) is
-----
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate OUTPUT_DATA_NORMAL_GEN;
--Read data in mixed mode (C_HAS_FAST = 1) and C_EN_CASCADE_MODE = 1 and C_CASCADE_MASTER = 1
CASCADE_OP_DATA_FAST_GEN: if ((C_HAS_FAST = 1) and
(C_EN_CASCADE_MODE = 1)
) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk,
Interrupt_address_in_reg_int,
ier ,
isr ,
isr_ored_30_0_bits) is
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then -- read IVAR of 31st bit in case the interrupt is present
if((isr(31) = '1') and -- else to read IVAR of lower modules the processor has to
(ier(31) = '1') and -- initiate the transaction for lower module separately
(isr_ored_30_0_bits = '0')
)then
Rd_data <= Interrupt_address_in_reg_int;
else
Rd_data <= ivar_rd_data_axi_clk;
end if;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
NO_CASCADE_OP_DATA_FAST_GEN: if (C_HAS_FAST = 1) and
(C_CASCADE_MASTER = 0) and
(C_EN_CASCADE_MODE = 0)
generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk) is
begin
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then
Rd_data <= ivar_rd_data_axi_clk;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate NO_CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
end imp;
| gpl-3.0 | c47b09c80c07cdf50a450f7ed977fd89 | 0.359176 | 4.992859 | false | false | false | false |
speters/mprfgen | test3.vhd | 1 | 2,984 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 1;
NRP : integer := 2;
AW : integer := 10;
DW : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
component regfile_core
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end component;
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(0),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0))
);
nwp_nrp_bram_instance_1 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(1),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+1)+1)-1 downto DW*(0*NRP+1))
);
ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1)-1 downto DW*0);
ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+1)-1 downto DW*1);
end rtl;
| gpl-3.0 | 808e57167560d473c047841a1e9552b8 | 0.506367 | 3.069959 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rx_fifo_loader.vhd | 4 | 16,298 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_loader.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_loader is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end rx_fifo_loader;
------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_loader is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
type STATES_TYPE is (
IPG,
PREAMBLE,
PREAMBLE_10,
RX100,
RX10
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal rx_cary_sense_i : std_logic;
signal rx_data_valid_i : std_logic;
signal rx_end_of_packet_i : std_logic;
signal repeated_data_cnt : integer range 0 to 63;
signal phy2rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal phy2rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal dibit_cnt : std_logic_vector(3 downto 0);
signal sample_rxd_cnt : std_logic_vector(4 downto 0);
signal sample_rxd : std_logic;
signal rxd_is_idle : std_logic;
signal rxd_is_preamble : std_logic;
signal rxd_is_preamble10 : std_logic;
signal rxd_10_i : std_logic;
signal rxd_100_i : std_logic;
begin
------------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
------------------------------------------------------------------------------
--RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
--begin
-- if (Ref_Clk'event and Ref_Clk = '1') then
-- if (Sync_rst_n = '0') then
-- phy2Rmii_crs_dv_sr <= (others => '0');
-- else
-- phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
-- Phy2Rmii_crs_dv;
-- end if;
-- end if;
--end process;
------------------------------------------------------------------------------
-- RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
RX_CARRY_SENSE_DATA_VALID_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_error <= '0';
Rx_cary_sense <= '0';
rx_cary_sense_i <= '0';
rx_end_of_packet_i <= '0';
Rx_data_valid <= '0';
phy2Rmii_crs_dv_sr <= (others => '0');
else
Rx_error <= Phy2Rmii_rx_er;
Rx_cary_sense <= rx_cary_sense_i;
Rx_data_valid <= rx_data_valid_i;
rx_end_of_packet_i <= (rxd_100_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(0)) or
(rxd_10_i and not Phy2Rmii_crs_dv and not phy2Rmii_crs_dv_sr(9));
rx_cary_sense_i <= (Phy2Rmii_crs_dv and rx_cary_sense_i) or
(Phy2Rmii_crs_dv and not rxd_10_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(1)) or
(Phy2Rmii_crs_dv and not rxd_100_i and not
phy2Rmii_crs_dv_sr(0) and not phy2Rmii_crs_dv_sr(11));
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) & Phy2Rmii_crs_dv;
end if;
if (Sync_rst_n = '0') then
rx_data_valid_i <= '0';
elsif (rx_data_valid_i = '0') then
rx_data_valid_i <= Phy2Rmii_crs_dv or phy2Rmii_crs_dv_sr(0);
elsif (rx_data_valid_i = '1') then
rx_data_valid_i <= not rx_end_of_packet_i;
end if;
end if;
end process;
Rx_end_of_packet <= rx_end_of_packet_i;
---------------------------------------------------------------------------
-- RXD_PIPELINE_DELAY_PROCESS
---------------------------------------------------------------------------
RXD_PIPELINE_DELAY_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
phy2rmii_rxd_d2 <= (others => '0');
phy2rmii_rxd_d1 <= (others => '0');
else
phy2rmii_rxd_d2 <= phy2rmii_rxd_d1;
phy2rmii_rxd_d1 <= Phy2Rmii_rxd;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- REPEATED_DATA_CNT_PROCESS
---------------------------------------------------------------------------
REPEATED_DATA_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
repeated_data_cnt <= 0;
elsif (phy2rmii_rxd_d1 = Phy2Rmii_rxd) then
if (repeated_data_cnt = 63) then
repeated_data_cnt <= 63;
else
repeated_data_cnt <= repeated_data_cnt + 1;
end if;
else
repeated_data_cnt <= 0;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- SAMPLE_RXD_CNT_PROCESS
---------------------------------------------------------------------------
SAMPLE_RXD_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
sample_rxd_cnt <= "00000";
sample_rxd <= '0';
elsif (rxd_10_i = '1') then
if (sample_rxd_cnt = "00000") then
sample_rxd <= '1';
else
sample_rxd <= '0';
end if;
sample_rxd_cnt <= sample_rxd_cnt(3 downto 0) & not sample_rxd_cnt(4);
elsif (rxd_is_preamble10 = '1') then
sample_rxd_cnt <= "10000";
else
sample_rxd_cnt <= "00001";
sample_rxd <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_CNT_PROCESS
---------------------------------------------------------------------------
DIBIT_CNT_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ((Sync_rst_n = '0') or (rxd_is_idle = '1')) then
dibit_cnt <= "0001";
elsif (rxd_is_preamble10 = '1') then
dibit_cnt <= "0100";
elsif ((sample_rxd = '1') and (rxd_is_idle = '0')) then
dibit_cnt <= dibit_cnt(2 downto 0) & (dibit_cnt(3));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DIBIT_TO_BYTE_MAPPING_PROCESS
---------------------------------------------------------------------------
DIBIT_TO_BYTE_MAPPING_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = C_RESET_ACTIVE) then
Rx_data <= (others => '0');
elsif (dibit_cnt(0) = '1') then
Rx_data(0) <= phy2rmii_rxd_d2(0);
Rx_data(1) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(1) = '1') then
Rx_data(2) <= phy2rmii_rxd_d2(0);
Rx_data(3) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(2) = '1') then
Rx_data(4) <= phy2rmii_rxd_d2(0);
Rx_data(5) <= phy2rmii_rxd_d2(1);
elsif (dibit_cnt(3) = '1') then
Rx_data(6) <= phy2rmii_rxd_d2(0);
Rx_data(7) <= phy2rmii_rxd_d2(1);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR_FIFO_EN_PROCESS
---------------------------------------------------------------------------
WR_FIFO_EN_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
Rx_fifo_wr_en <= '0';
elsif ((sample_rxd = '1') and (dibit_cnt(3) = '1') and (rxd_is_idle = '0') and
(rxd_is_preamble10 = '0')) then
Rx_fifo_wr_en <= '1';
else
Rx_fifo_wr_en <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IPG;
else
present_state <= next_state;
end if;
case next_state is
when IPG =>
rxd_is_idle <= '1';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE =>
rxd_is_idle <= '0';
rxd_is_preamble <= '1';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '0';
when PREAMBLE_10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '1';
rxd_100_i <= '0';
rxd_10_i <= '0';
when RX100 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '1';
rxd_10_i <= '0';
when RX10 =>
rxd_is_idle <= '0';
rxd_is_preamble <= '0';
rxd_is_preamble10 <= '0';
rxd_100_i <= '0';
rxd_10_i <= '1';
end case;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
repeated_data_cnt,
phy2rmii_rxd_d1,
Phy2Rmii_rxd,
Phy2Rmii_crs_dv,
rx_data_valid_i
)
begin
case present_state is
when IPG =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "01") and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE;
else
next_state <= IPG;
end if;
when PREAMBLE =>
if ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt < 31) and (Phy2Rmii_rxd = "11")) then
next_state <= RX100;
elsif ((Phy2Rmii_crs_dv = '1') and (repeated_data_cnt > 30) and (phy2rmii_rxd_d1 = "01")) then
next_state <= PREAMBLE_10;
else
next_state <= PREAMBLE;
end if;
when PREAMBLE_10 =>
if ((Phy2Rmii_crs_dv = '1') and (Phy2Rmii_rxd = "11")) then
next_state <= RX10;
else
next_state <= PREAMBLE_10;
end if;
when RX100 =>
if (rx_data_valid_i = '0')then
next_state <= IPG;
else
next_state <= RX100;
end if;
when RX10 =>
if (rx_data_valid_i = '0') then
next_state <= IPG;
else
next_state <= RX10;
end if;
end case;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
RX_10 <= rxd_10_i;
RX_100 <= rxd_100_i;
end simulation;
| gpl-3.0 | c37b7cbad9c0781529fe3a3a550ea9c7 | 0.428826 | 4.004423 | false | false | false | false |
BogdanArdelean/FPWAM | hardware/src/hdl/PsramCntrl.vhd | 1 | 14,776 | -----------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2013, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : psram_cntrl.vhd
-- MODULE NAME : PsramCntrl - Pseudo-Static Random Access Memory Controller
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2011-12-08 Mihaita Nagy Created
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements the state machine to control the
-- basic read and write of the memory. It is also capable of
-- doing 32-bit writes, using two consecutive 16-bit writes,
-- and 8-bit access as well, using the UB/LB pins.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PsramCntrl is
generic (
-- read/write cycle (ns)
C_RW_CYCLE_NS : integer := 100
);
port (
-- Control interface
clk_i : in std_logic; -- 100 MHz system clock
rst_i : in std_logic; -- active high system reset
rnw_i : in std_logic; -- read/write
be_i : in std_logic_vector(3 downto 0); -- byte enable
addr_i : in std_logic_vector(31 downto 0); -- address input
data_i : in std_logic_vector(31 downto 0); -- data input
cs_i : in std_logic; -- active high chip select
data_o : out std_logic_vector(31 downto 0); -- data output
rd_ack_o : out std_logic; -- read acknowledge flag
wr_ack_o : out std_logic; -- write acknowledge flag
-- PSRAM Memory signals
Mem_A : out std_logic_vector(22 downto 0);
Mem_DQ_O : out std_logic_vector(15 downto 0);
Mem_DQ_I : in std_logic_vector(15 downto 0);
Mem_DQ_T : out std_logic_vector(15 downto 0);
Mem_CEN : out std_logic;
Mem_OEN : out std_logic;
Mem_WEN : out std_logic;
Mem_UB : out std_logic;
Mem_LB : out std_logic;
Mem_ADV : out std_logic;
Mem_CLK : out std_logic;
Mem_CRE : out std_logic;
Mem_Wait : in std_logic
);
end PsramCntrl;
architecture Behavioral of PsramCntrl is
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- State machine state names
type States is(Idle, AssertCen, AssertOenWen, Waitt, Deassert, SendData,
Ack, Done);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- State machine signals
signal State, NState: States := Idle;
-- For a 32-bit access, two cycles are needed
signal TwoCycle: std_logic := '0';
-- Memory LSB
signal AddrLsb: std_logic;
-- RnW registered signal
signal RnwInt: std_logic;
-- Byte enable internal bus
signal BeInt: std_logic_vector(3 downto 0);
-- Internal registerred Bus2IP_Addr bus
signal AddrInt: std_logic_vector(31 downto 0);
-- Internal registerred Bus2IP_Data bus
signal Data2WrInt: std_logic_vector(31 downto 0);
-- Internal registerred IP2_Bus bus
signal DataRdInt: std_logic_vector(31 downto 0);
-- Integer for the counter of the rd/wr cycle time
signal CntCycleTime: integer range 0 to 32;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- Unused memory signals
Mem_ADV <= '0';
Mem_CLK <= '0';
Mem_CRE <= '0';
------------------------------------------------------------------------
-- Register internal signals
------------------------------------------------------------------------
REGISTER_INT: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Idle and cs_i = '1' then
RnwInt <= rnw_i;
BeInt <= be_i;
AddrInt <= addr_i;
Data2WrInt <= data_i;
end if;
end if;
end process REGISTER_INT;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Initialize the state machine
FSM_REGISTER_STATES: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
State <= Idle;
else
State <= NState;
end if;
end if;
end process FSM_REGISTER_STATES;
-- State machine transitions
FSM_TRANSITIONS: process(cs_i, TwoCycle, CntCycleTime, State)
begin
case State is
when Idle =>
if cs_i = '1' then
NState <= AssertCen;
else
NState <= Idle;
end if;
when AssertCen => NState <= AssertOenWen;
when AssertOenWen => NState <= Waitt;
when Waitt =>
if CntCycleTime = ((C_RW_CYCLE_NS/10) - 2) then
NState <= Deassert;
else
NState <= Waitt;
end if;
when Deassert => NState <= SendData;
when SendData =>
if TwoCycle = '1' then
NState <= AssertCen;
else
NState <= Ack;
end if;
when Ack => NState <= Done;
when Done => NState <= Idle;
when others => Nstate <= Idle;
end case;
end process FSM_TRANSITIONS;
------------------------------------------------------------------------
-- Counter for the write/read cycle time
------------------------------------------------------------------------
CYCLE_COUNTER: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Waitt then
CntCycleTime <= CntCycleTime + 1;
else
CntCycleTime <= 0;
end if;
end if;
end process CYCLE_COUNTER;
------------------------------------------------------------------------
-- Assert CEN
------------------------------------------------------------------------
ASSERT_CEN: process(clk_i)
begin
if rising_edge(clk_i) then
if State = AssertOenWen or
State = Waitt or
State = Deassert then
Mem_CEN <= '0';
else
Mem_CEN <= '1';
end if;
end if;
end process ASSERT_CEN;
------------------------------------------------------------------------
-- Assert WEN/OEN
------------------------------------------------------------------------
ASSERT_WENOEN: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Waitt or State = Deassert then
if RnwInt = '1' then
Mem_OEN <= '0';
Mem_WEN <= '1';
else
Mem_OEN <= '1';
Mem_WEN <= '0';
end if;
else
Mem_OEN <= '1';
Mem_WEN <= '1';
end if;
end if;
end process ASSERT_WENOEN;
------------------------------------------------------------------------
-- When a 32-bit access mode has to be performed, assert the TwoCycle
-- signal
------------------------------------------------------------------------
ASSIGN_TWOCYCLE: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
TwoCycle <= '0';
elsif State = AssertCen and be_i = "1111" then -- 32-bit access
TwoCycle <= not TwoCycle;
end if;
end if;
end process ASSIGN_TWOCYCLE;
------------------------------------------------------------------------
-- Assign AddrLsb signal
------------------------------------------------------------------------
ASSIGN_ADDR_LSB: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
AddrLsb <= '0';
elsif State = AssertCen then
case BeInt is
-- In 32-bit access: first the lowest address then the highest
-- address is written
when "1111" => AddrLsb <= not TwoCycle;
-- Higher address
when "1100"|"0100"|"1000" => AddrLsb <= '1';
-- Lower address
when "0011"|"0010"|"0001" => AddrLsb <= '0';
when others => null;
end case;
end if;
end if;
end process ASSIGN_ADDR_LSB;
------------------------------------------------------------------------
-- Assign Mem_A
------------------------------------------------------------------------
ASSIGN_ADDRESS: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
Mem_A <= (others => '0');
elsif State = AssertOenWen or
State = Waitt or
State = Deassert then
Mem_A <= AddrInt(22 downto 1) & AddrLsb;
end if;
end if;
end process ASSIGN_ADDRESS;
------------------------------------------------------------------------
-- Assign Mem_DQ_O and Mem_DQ_T
------------------------------------------------------------------------
ASSIGN_DATA: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
Mem_DQ_O <= (others => '0');
elsif ((State = AssertOenWen or State = Waitt or State = Deassert) and RnwInt = '0') then
case BeInt is
when "1111" =>
if TwoCycle = '1' then
-- Write lowest address with MSdata
Mem_DQ_O <= Data2WrInt(15 downto 0);
else
-- Write highest address with LSdata
Mem_DQ_O <= Data2WrInt(31 downto 16);
end if;
when "0011"|"0010"|"0001" => Mem_DQ_O <= Data2WrInt(15 downto 0);
when "1100"|"1000"|"0100" => Mem_DQ_O <= Data2WrInt(31 downto 16);
when others => null;
end case;
else
Mem_DQ_O <= (others => '0');
end if;
end if;
end process ASSIGN_DATA;
Mem_DQ_T <= (others => '1') when RnwInt = '1' else (others => '0');
------------------------------------------------------------------------
-- Read data from the memory
------------------------------------------------------------------------
READ_DATA: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
DataRdInt <= (others => '0');
elsif State = Deassert then
case BeInt is
when "1111" =>
if TwoCycle = '1' then
-- Read lowest address with MSdata
DataRdInt(15 downto 0) <= Mem_DQ_I;
else
-- Read highest address with LSdata
DataRdInt(31 downto 16) <= Mem_DQ_I;
end if;
-- Perform data mirroring
when "0011"|"1100" =>
DataRdInt(15 downto 0) <= Mem_DQ_I;
DataRdInt(31 downto 16) <= Mem_DQ_I;
when "0100"|"0001" =>
DataRdInt(7 downto 0) <= Mem_DQ_I(7 downto 0);
DataRdInt(15 downto 8) <= Mem_DQ_I(7 downto 0);
DataRdInt(23 downto 16) <= Mem_DQ_I(7 downto 0);
DataRdInt(31 downto 24) <= Mem_DQ_I(7 downto 0);
when "1000"|"0010" =>
DataRdInt(7 downto 0) <= Mem_DQ_I(15 downto 8);
DataRdInt(15 downto 8) <= Mem_DQ_I(15 downto 8);
DataRdInt(23 downto 16) <= Mem_DQ_I(15 downto 8);
DataRdInt(31 downto 24) <= Mem_DQ_I(15 downto 8);
when others => null;
end case;
end if;
end if;
end process READ_DATA;
------------------------------------------------------------------------
-- Send data to AXI bus
------------------------------------------------------------------------
REGISTER_DREAD: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_o <= (others => '0');
elsif ((State = SendData or State = Ack or State = Done) and RnwInt = '1') then
-- Set the output data on the bus only if a read cycle was performed
data_o <= DataRdInt;
else
data_o <= (others => '0');
end if;
end if;
end process REGISTER_DREAD;
------------------------------------------------------------------------
-- Assign acknowledge signals
------------------------------------------------------------------------
REGISTER_ACK: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
rd_ack_o <= '0';
wr_ack_o <= '0';
elsif State = Ack and TwoCycle = '0' then
if RnwInt = '1' then -- read
rd_ack_o <= '1';
wr_ack_o <= '0';
else -- write
rd_ack_o <= '0';
wr_ack_o <= '1';
end if;
else
rd_ack_o <= '0';
wr_ack_o <= '0';
end if;
end if;
end process REGISTER_ACK;
------------------------------------------------------------------------
-- Assign UB, LB (used in 8-bit write mode)
------------------------------------------------------------------------
ASSIGN_UB_LB: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
Mem_UB <= '0';
Mem_LB <= '0';
elsif RnwInt = '0' then
if State = AssertOenWen or
State = Waitt or
State = Deassert then
case BeInt is
-- Disable lower byte when MSByte is written
when "1000"|"0010" =>
Mem_UB <= '0';
Mem_LB <= '1';
-- Disable upper byte when LSByte is written
when "0100"|"0001" =>
Mem_UB <= '1';
Mem_LB <= '0';
-- Enable both bytes in other modes
when others =>
Mem_UB <= '0';
Mem_LB <= '0';
end case;
end if;
else -- Enable both when reading
Mem_UB <= '0';
Mem_LB <= '0';
end if;
end if;
end process ASSIGN_UB_LB;
end Behavioral;
| apache-2.0 | 708ad0b5a81e3b643a5e5272f10cf0c6 | 0.410531 | 4.795846 | false | false | false | false |
hoangt/PoC | src/io/ddrio/ddrio_inout.vhdl | 2 | 3,850 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Chip-Specific DDR Input and Output Registers
--
-- Description:
-- ------------------------------------
-- Instantiates chip-specific DDR input and output registers.
--
-- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if
-- necessary. If an output enable is not required, you may save some logic by
-- setting NO_OUTPUT_ENABLE = true. However, "OutputEnable" must be set to '1'.
--
-- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with
-- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought
-- out with this rising edge. "DataOut_low" is brought out with the falling
-- edge.
--
-- "Pad" must be connected to a PAD because FPGAs only have these registers in
-- IOBs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.config.all;
use PoC.ddrio.all;
entity ddrio_out is
generic (
NO_OUTPUT_ENABLE : BOOLEAN := false;
BITS : POSITIVE;
INIT_VALUE_OUT : BIT_VECTOR := "1";
INIT_VALUE_IN_HIGH : BIT_VECTOR := "1";
INIT_VALUE_IN_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_out is
begin
assert (VENDOR = VENDOR_XILINX) or (VENDOR = VENDOR_ALTERA)
report "PoC.io.ddrio.inout is not implemented for given DEVICE."
severity FAILURE;
genXilinx : if (VENDOR = VENDOR_XILINX) generate
inst : ddrio_inout_xilinx
generic map (
NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE,
BITS => BITS,
INIT_VALUE_OUT => INIT_VALUE_OUT,
INIT_VALUE_IN_HIGH => INIT_VALUE_IN_HIGH,
INIT_VALUE_IN_LOW => INIT_VALUE_IN_LOW
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
OutputEnable => OutputEnable,
DataOut_high => DataOut_high,
DataOut_low => DataOut_low,
DataIn_high => DataIn_high,
DataIn_low => DataIn_low,
Pad => Pad
);
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
inst : ddrio_inout_altera
generic map (
BITS => BITS
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
OutputEnable => OutputEnable,
DataOut_high => DataOut_high,
DataOut_low => DataOut_low,
DataIn_high => DataIn_high,
DataIn_low => DataIn_low,
Pad => Pad
);
end generate;
end architecture;
| apache-2.0 | 2d15c44adf7a4f8b9e7a3999c09bdff2 | 0.617403 | 3.395062 | false | false | false | false |
hoangt/PoC | tb/misc/stat/stat_Minimum_tb.vhdl | 2 | 6,179 | -- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Authors: Patrick Lehmann
--
-- Description: Testbench for stat_Minimum.
--
-------------------------------------------------------------------------------
-- Copyright 2007-2015 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use poC.utils.all;
use poC.vectors.all;
entity stat_Minimum_tb is
end entity;
architecture tb of stat_Minimum_tb is
-- component generics
constant VALUES : T_NATVEC := (
113, 106, 126, 239, 146, 72, 51, 210, 44, 56, 10, 126, 7, 7, 22, 18,
128, 217, 106, 210, 58, 71, 213, 206, 169, 213, 90, 27, 166, 159, 83, 116,
246, 208, 105, 64, 112, 12, 110, 10, 5, 100, 12, 231, 191, 235, 27, 143,
162, 178, 136, 149, 92, 221, 122, 44, 143, 169, 72, 182, 232, 26, 46, 135,
223, 144, 129, 48, 148, 208, 156, 119, 109, 98, 207, 208, 62, 232, 17, 183,
189, 197, 115, 237, 25, 183, 27, 27, 89, 64, 170, 192, 189, 177, 28, 228,
56, 127, 10, 49, 108, 229, 244, 204, 25, 20, 42, 243, 16, 163, 232, 161,
154, 139, 243, 38, 160, 59, 113, 42, 120, 104, 208, 87, 40, 213, 179, 181,
73, 228, 155, 184, 224, 218, 77, 210, 202, 161, 215, 7, 143, 34, 13, 175,
81, 12, 40, 53, 184, 240, 71, 247, 17, 218, 179, 7, 23, 159, 166, 61,
90, 111, 172, 37, 11, 50, 186, 186, 64, 36, 85, 249, 93, 108, 148, 89,
93, 35, 7, 30, 175, 129, 247, 83, 160, 157, 170, 9, 41, 73, 189, 45,
244, 157, 166, 35, 111, 226, 167, 34, 76, 104, 239, 151, 157, 71, 156, 159,
72, 93, 163, 237, 153, 139, 135, 211, 113, 92, 126, 103, 130, 180, 147, 240,
96, 42, 7, 185, 191, 115, 227, 117, 118, 224, 204, 74, 140, 98, 176, 92,
3, 13, 187, 198, 160, 201, 141, 108, 24, 205, 171, 22, 102, 66, 153, 146,
206, 248, 58, 117, 67, 220, 217, 206, 115, 48, 122, 179, 184, 63, 74, 18,
166, 37, 103, 119, 242, 198, 82, 144, 151, 149, 164, 235, 193, 207, 18, 55,
74, 61, 118, 141, 42, 61, 28, 32, 46, 230, 85, 114, 82, 212, 173, 210,
134, 156, 106, 67, 212, 36, 153, 10, 168, 164, 216, 168, 59, 231, 15, 157,
33, 69, 107, 126, 195, 182, 225, 107, 12, 73, 76, 15, 116, 218, 64, 188,
225, 203, 104, 40, 104, 200, 92, 40, 158, 110, 222, 128, 95, 110, 223, 64,
218, 178, 84, 16, 108, 50, 18, 202, 180, 249, 58, 142, 210, 141, 144, 200,
102, 30, 192, 106, 130, 224, 56, 82, 226, 69, 218, 88, 209, 100, 15, 152,
100, 14, 46, 188, 136, 51, 83, 178, 188, 152, 110, 105, 145, 199, 80, 19,
215, 25, 29, 67, 167, 119, 184, 243, 124, 5, 39, 41, 81, 179, 242, 83,
236, 155, 45, 198, 97, 206, 67, 54, 197, 17, 168, 227, 117, 200, 186, 29,
239, 201, 122, 187, 74, 197, 234, 230, 80, 53, 66, 133, 14, 44, 99, 11,
160, 29, 118, 239, 157, 131, 172, 12, 207, 224, 119, 153, 201, 206, 128, 173,
69, 12, 51, 129, 60, 57, 12, 42, 171, 64, 121, 46, 143, 184, 42, 156,
167, 160, 70, 91, 85, 196, 122, 110, 32, 113, 229, 99, 81, 84, 32, 123,
174, 142, 66, 5, 242, 220, 200, 105, 20, 79, 71, 95, 13, 128, 119, 26
);
type T_RESULT is record
Minimum : NATURAL;
Count : POSITIVE;
end record;
type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT;
constant RESULT : T_RESULT_VECTOR := (
(Minimum => 3, Count => 1),
(Minimum => 5, Count => 3),
(Minimum => 7, Count => 6),
(Minimum => 9, Count => 1),
(Minimum => 10, Count => 4),
(Minimum => 11, Count => 2),
(Minimum => 12, Count => 7),
(Minimum => 13, Count => 3)
);
constant DEPTH : POSITIVE := RESULT'length;
constant DATA_BITS : POSITIVE := 8;
constant COUNTER_BITS : POSITIVE := 16;
-- component ports
signal Clock : STD_LOGIC := '1';
signal Reset : STD_LOGIC := '0';
signal Enable : STD_LOGIC := '0';
signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal Minimums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0);
signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0);
signal Minimums_slvv : T_SLVV_8(DEPTH - 1 downto 0);
signal Counts_slvv : T_SLVV_4(DEPTH - 1 downto 0);
begin
-- component instantiation
DUT: entity PoC.stat_Minimum
generic map (
DEPTH => DEPTH,
DATA_BITS => DATA_BITS,
COUNTER_BITS => COUNTER_BITS
)
port map (
Clock => Clock,
Reset => Reset,
Enable => Enable,
DataIn => DataIn,
Valids => Valids,
Minimums => Minimums,
Counts => Counts
);
Minimums_slvv <= to_slvv_8(Minimums);
Counts_slvv <= to_slvv_4(Counts);
process
procedure cycle is
begin
Clock <= '1';
wait for 5 ns;
Clock <= '0';
wait for 5 ns;
end cycle;
variable good : BOOLEAN;
begin
cycle;
Reset <= '1';
cycle;
Reset <= '0';
cycle;
cycle;
Enable <= '1';
for i in VALUES'range loop
--Enable <= to_sl(VALUES(i) /= 35);
DataIn <= to_slv(VALUES(i), DataIn'length);
cycle;
end loop;
cycle;
-- test result after all cycles
good := (slv_and(Valids) = '1');
for i in RESULT'range loop
good := good and (RESULT(i).Minimum = unsigned(Minimums_slvv(i))) and (RESULT(i).Count = unsigned(Counts_slvv(i)));
end loop;
assert (good = TRUE)
report "Test failed."
severity note;
assert (good = FALSE)
report "Test passed."
severity note;
wait;
end process;
end;
| apache-2.0 | d396f1391bb47c7c751074362e511f49 | 0.574458 | 2.761734 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/mem/syncram_2p_tech.vhd | 2 | 2,051 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific dual-port RAM.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of syncram_2p_tech is
component syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
inf : if tech = inferred generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xilinx6 : if tech = virtex6 or tech = kintex7 or tech = artix7 generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
end;
| bsd-2-clause | 34cac2950e31af1a38a269af7e7b9084 | 0.593369 | 3.763303 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/synth/design_1_axi_timer_0_0.vhd | 2 | 9,270 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_timer_0_0_arch : ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "artix7",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
| gpl-3.0 | 409fc48024c8599cc771739c6666900d | 0.691262 | 3.277935 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/transmit.vhd | 4 | 36,318 | -------------------------------------------------------------------------------
-- transmit - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : transmit.vhd
-- Version : v2.0
-- Description : This is the transmit path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std."-";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- NibbleLength -- Transmit frame nibble length
-- NibbleLength_orig -- Transmit nibble length before pkt adjustment
-- En_pad -- Enable padding
-- TxClkEn -- Transmit clock enable
-- Phy_tx_clk -- PHY TX Clock
-- Phy_crs -- Ethernet carrier sense
-- Phy_col -- Ethernet collision indicator
-- Phy_tx_en -- Ethernet transmit enable
-- Phy_tx_data -- Ethernet transmit data
-- Tx_addr_en -- TX buffer address enable
-- Tx_start -- TX start
-- Tx_done -- TX complete
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- TX idle
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Transmit_start -- Transmit start
-- Mac_program_start -- MAC Program start
-- Mac_addr_ram_we -- MAC Address RAM write enable
-- Mac_addr_ram_addr_wr -- MAC Address RAM write address
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity transmit is
generic
(
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
NibbleLength : in std_logic_vector(0 to 11);
NibbleLength_orig : in std_logic_vector(0 to 11);
En_pad : in std_logic;
TxClkEn : in std_logic;
Phy_tx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_col : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_addr_en : out std_logic;
Tx_start : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Tx_DPM_ce : out std_logic;
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Mac_addr_ram_we : out std_logic;
Mac_addr_ram_addr_wr : out std_logic_vector(0 to 3)
);
end transmit;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture imp of transmit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant logic_one :std_logic := '1';
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal tx_d_rst : std_logic;
signal full_half_n : std_logic;
signal bus_combo : std_logic_vector (0 to 5);
signal txChannelReset : std_logic;
signal emac_tx_wr_i : std_logic;
signal txfifo_full : std_logic;
signal txfifo_empty : std_logic;
signal tx_en_i : std_logic;
signal tx_en_i_tx_clk : std_logic;
signal fifo_tx_en : std_logic;
signal axi_fifo_tx_en : std_logic;
signal txNibbleCntLd : std_logic;
signal txNibbleCntEn : std_logic;
signal txNibbleCntRst : std_logic;
signal txComboNibbleCntRst : std_logic;
--signal phy_tx_en_i : std_logic;
signal phy_tx_en_i_p : std_logic;
signal axi_phy_tx_en_i_p : std_logic;
signal deferring : std_logic;
signal txBusFifoWrCntRst : std_logic;
signal txBusFifoWrCntEn : std_logic;
signal txComboBusFifoWrCntRst : std_logic;
signal txComboBusFifoWrCntEn : std_logic;
signal txComboColRetryCntRst_n : std_logic;
signal txComboBusFifoRst : std_logic;
signal txColRetryCntRst_n : std_logic;
signal enblPreamble : std_logic;
signal enblSFD : std_logic;
signal enblData : std_logic;
signal enblJam : std_logic;
signal enblCRC : std_logic;
signal txCntEnbl : std_logic;
signal txColRetryCntEnbl : std_logic;
signal jamTxComboNibCntEnbl : std_logic;
signal txRetryRst : std_logic;
signal txLateColnRst : std_logic;
signal initBackoff : std_logic;
signal backingOff_i : std_logic;
signal txCrcShftOutEn : std_logic;
signal txCrcEn : std_logic;
signal crcComboRst : std_logic;
signal emac_tx_wr_data_i : std_logic_vector (0 to 3);
signal crcCnt : std_logic_vector(0 to 3);
signal collisionRetryCnt : std_logic_vector(0 to 4);
signal jamTxNibbleCnt : std_logic_vector(0 to 3);
signal colWindowNibbleCnt : std_logic_vector(0 to 7);
signal prb : std_logic_vector(0 to 3);
signal sfd : std_logic_vector(0 to 3);
signal jam : std_logic_vector(0 to 3);
signal crc : std_logic_vector(0 to 3);
signal currentTxBusFifoWrCnt : std_logic_vector(0 to 11);
signal currentTxNibbleCnt : std_logic_vector (0 to 11);
signal phy_tx_en_n : std_logic;
signal txComboColRetryCntRst : std_logic;
signal phy_tx_en_i_n : std_logic;
signal jam_rst : std_logic;
signal txExcessDefrlRst : std_logic;
signal enblclear : std_logic;
signal tx_en_mod : std_logic;
signal emac_tx_wr_mod : std_logic;
signal pre_sfd_done : std_logic;
signal mux_in_data : std_logic_vector (0 to 6*4-1);
signal mux_in_sel : std_logic_vector (0 to 5);
signal transmit_data : std_logic_vector (0 to 3);
signal txNibbleCnt_pad : unsigned (0 to 11);
signal tx_idle_i : std_logic;
signal emac_tx_wr_data_d1 : std_logic_vector (0 to 3);
signal emac_tx_wr_d1 : std_logic;
signal txcrcen_d1 : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDCE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- tx crc generator
----------------------------------------------------------------------------
INST_CRCGENTX: entity axi_ethernetlite_v3_0.crcgentx
port map
(
Clk => Clk,
Rst => crcComboRst,
Clken => emac_tx_wr_d1,
Data => emac_tx_wr_data_d1,
DataEn => txcrcen_d1,
OutEn => txCrcShftOutEn,
CrcNibs => crc
);
crcComboRst <= Rst or not (tx_en_i); -- having tx_en form same clock domain as Clk
-- crcComboRst <= Rst or not (fifo_tx_en);
----------------------------------------------------------------------------
-- tx interface contains the ethernet tx fifo
----------------------------------------------------------------------------
INST_TX_INTRFCE: entity axi_ethernetlite_v3_0.tx_intrfce
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => txComboBusFifoRst,
Phy_tx_clk => Phy_tx_clk,
Emac_tx_wr_data => emac_tx_wr_data_i,
Tx_er => '0',
PhyTxEn => tx_en_mod,
Tx_en => fifo_tx_en,
Fifo_empty => txfifo_empty,
Fifo_full => txfifo_full,
Emac_tx_wr => emac_tx_wr_mod,
Phy_tx_data => bus_combo
);
txComboBusFifoRst <= Rst or txRetryRst or
(jam_rst and not(full_half_n) and
Phy_col and pre_sfd_done);
jam <= "0110"; -- arbitrary
prb <= "0101"; -- transmitted as 1010
sfd <= "1101"; -- transmitted as 1011
----------------------------------------------------------------------------
-- PHY output selection
----------------------------------------------------------------------------
mux_in_sel <= enblPreamble & enblSFD & enblData & enblJam & enblCRC &
logic_one;
mux_in_data <= prb & sfd & transmit_data & jam & crc & "0000";
transmit_data <= "0000" when (txNibbleCnt_pad = 0) else
Tx_DPM_rd_data;
Tx_idle <= tx_idle_i;
----------------------------------------------------------------------------
-- Multiplexing PHY transmit data
----------------------------------------------------------------------------
ONR_HOT_MUX:entity axi_ethernetlite_v3_0.mux_onehot_f
generic map
(
C_DW => 4,
C_NB => 6,
C_FAMILY => C_FAMILY
)
port map
(
D => mux_in_data,
S => mux_in_sel,
Y => emac_tx_wr_data_i
);
----------------------------------------------------------------------------
-- PHY transmit data
----------------------------------------------------------------------------
Phy_tx_data <= "0110" when (Phy_col = '1' or
not(jamTxNibbleCnt(0) = '1' and
jamTxNibbleCnt(1) = '0' and
jamTxNibbleCnt(2) = '0' and
jamTxNibbleCnt(3) = '1')) and
full_half_n = '0' and
not (jamTxNibbleCnt = "0000") and
pre_sfd_done = '1' else
"0000" when jamTxNibbleCnt = "0000" and
full_half_n = '0' else
"0000" when axi_phy_tx_en_i_p = '0' else
bus_combo(0 to 3);
----------------------------------------------------------------------------
-- PHY transmit enable
----------------------------------------------------------------------------
Phy_tx_en <= '1' when (Phy_col = '1' or
not(jamTxNibbleCnt(0) = '1' and
jamTxNibbleCnt(1) = '0' and
jamTxNibbleCnt(2) = '0' and
jamTxNibbleCnt(3) = '1')) and
full_half_n = '0' and
not (jamTxNibbleCnt = "0000") and
pre_sfd_done = '1' else
'0' when jamTxNibbleCnt = "0000" and
full_half_n = '0' else
'0' when axi_phy_tx_en_i_p = '0' else
bus_combo(5);
----------------------------------------------------------------------------
-- transmit packet fifo read nibble counter
----------------------------------------------------------------------------
INST_TXNIBBLECOUNT: entity axi_ethernetlite_v3_0.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 12,
C_RESET_VALUE => "000000000000",
C_LD_WIDTH => 12,
C_LD_OFFSET => 0,
C_AD_WIDTH => 12,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => txComboNibbleCntRst,
Q => currentTxNibbleCnt,
LD => NibbleLength,
AD => "000000000001",
LOAD => txNibbleCntLd,
OP => txNibbleCntEn
);
txComboNibbleCntRst <= Rst or txNibbleCntRst or txRetryRst;
----------------------------------------------------------------------------
-- PROCESS : PKT_TX_PAD_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_TX_PAD_COUNTER : process(Clk)
begin
if (Clk'event and Clk='1') then
if (Rst=RESET_ACTIVE) then
txNibbleCnt_pad <= (others=>'0');
elsif (enblSFD='1') then -- load the counter for minimum
txNibbleCnt_pad <= unsigned(NibbleLength_orig); -- packet length
elsif (enblData='1' and En_pad='1') then -- Enable Down Counter
if (txNibbleCnt_pad=0 ) then
txNibbleCnt_pad <= (others=>'0');
else
txNibbleCnt_pad <= txNibbleCnt_pad-1;
end if;
end if;
end if;
end process PKT_TX_PAD_COUNTER;
----------------------------------------------------------------------------
-- transmit state machine
----------------------------------------------------------------------------
INST_TX_STATE_MACHINE: entity axi_ethernetlite_v3_0.tx_statemachine
generic map
(
C_DUPLEX => C_DUPLEX
)
port map
(
Clk => Clk,
Rst => txChannelReset,
TxClkEn => TxClkEn,
Jam_rst => jam_rst,
TxRst => txChannelReset,
Deferring => deferring,
ColRetryCnt => collisionRetryCnt,
ColWindowNibCnt => colWindowNibbleCnt,
JamTxNibCnt => jamTxNibbleCnt,
TxNibbleCnt => currentTxNibbleCnt,
BusFifoWrNibbleCnt => currentTxBusFifoWrCnt,
CrcCnt => crcCnt,
BusFifoFull => txfifo_full,
BusFifoEmpty => txfifo_empty,
PhyCollision => Phy_col,
InitBackoff => initBackoff,
TxRetryRst => txRetryRst,
TxExcessDefrlRst => txExcessDefrlRst,
TxLateColnRst => txLateColnRst,
TxColRetryCntRst_n => txColRetryCntRst_n,
TxColRetryCntEnbl => txColRetryCntEnbl,
TxNibbleCntRst => txNibbleCntRst,
TxEnNibbleCnt => txNibbleCntEn,
TxNibbleCntLd => txNibbleCntLd,
BusFifoWrCntRst => txBusFifoWrCntRst,
BusFifoWrCntEn => txBusFifoWrCntEn,
EnblPre => enblPreamble,
EnblSFD => enblSFD,
EnblData => enblData,
EnblJam => enblJam,
EnblCRC => enblCRC,
BusFifoWr => emac_tx_wr_i,
Phytx_en => tx_en_i,
TxCrcEn => txCrcEn,
TxCrcShftOutEn => txCrcShftOutEn,
Tx_addr_en => Tx_addr_en,
Tx_start => Tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => tx_idle_i,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Enblclear => enblclear,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => Mac_addr_ram_we,
Mac_addr_ram_addr_wr => Mac_addr_ram_addr_wr,
Pre_sfd_done => pre_sfd_done
);
----------------------------------------------------------------------------
-- deferral control
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
INST_DEFERRAL_CONTROL: entity axi_ethernetlite_v3_0.deferral
port map
(
Clk => Clk,
Rst => Rst,
TxEn => tx_en_i,
TxRst => txChannelReset,
Tx_clk_en => TxClkEn,
BackingOff => backingOff_i,
Crs => Phy_crs,
Full_half_n => full_half_n,
Ifgp1 => "10000",
Ifgp2 => "01000",
Deferring => deferring
);
----------------------------------------------------------------------------
-- transmit bus fifo write nibble counter
----------------------------------------------------------------------------
INST_TXBUSFIFOWRITENIBBLECOUNT: entity axi_ethernetlite_v3_0.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => true,
C_REG_WIDTH => 12,
C_RESET_VALUE => "000000000000",
C_LD_WIDTH => 12,
C_LD_OFFSET => 0,
C_AD_WIDTH => 12,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => txComboBusFifoWrCntRst,
Q => currentTxBusFifoWrCnt,
LD => "000000000000",
AD => "000000000001",
LOAD => '0',
OP => txComboBusFifoWrCntEn
);
txComboBusFifoWrCntRst <= Rst or txBusFifoWrCntRst
or txRetryRst;
txComboBusFifoWrCntEn <= txBusFifoWrCntEn and emac_tx_wr_i;
----------------------------------------------------------------------------
-- crc down counter
----------------------------------------------------------------------------
phy_tx_en_n <= not(tx_en_i); -- modified to have this in lite clock domain
INST_CRCCOUNTER: entity axi_ethernetlite_v3_0.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 4,
C_RESET_VALUE => "1000",
C_LD_WIDTH => 4,
C_LD_OFFSET => 0,
C_AD_WIDTH => 4,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => Rst,
Q => crcCnt,
LD => "1000",
AD => "0001",
LOAD => phy_tx_en_n,
OP => enblCRC
);
----------------------------------------------------------------------------
-- Full Duplex mode operation
----------------------------------------------------------------------------
TX3_NOT_GENERATE: if(C_DUPLEX = 1) generate --Set outputs to zero
begin
collisionRetryCnt <= (others=> '0');
colWindowNibbleCnt <= (others=> '0');
jamTxNibbleCnt <= (others=> '0');
backingOff_i <= '0';
end generate TX3_NOT_GENERATE;
----------------------------------------------------------------------------
-- Half Duplex mode operation
----------------------------------------------------------------------------
tx3_generate: if(C_DUPLEX = 0) generate --Include collision cnts when 1
----------------------------------------------------------------------------
-- transmit collision retry down counter
----------------------------------------------------------------------------
INST_COLRETRYCNT: entity axi_ethernetlite_v3_0.msh_cnt
generic map
(
C_ADD_SUB_NOT => true,
C_REG_WIDTH => 5,
C_RESET_VALUE => "00000"
)
port map
(
Clk => Clk,
Rst => txComboColRetryCntRst,
Q => collisionRetryCnt,
Z => open,
LD => "00000",
AD => "00001",
LOAD => '0',
OP => txColRetryCntEnbl
);
txComboColRetryCntRst_n <= not(Rst) and txColRetryCntRst_n;
txComboColRetryCntRst <= not txComboColRetryCntRst_n;
----------------------------------------------------------------------------
-- transmit collision window nibble down counter
----------------------------------------------------------------------------
INST_COLWINDOWNIBCNT: entity axi_ethernetlite_v3_0.msh_cnt
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 8,
C_RESET_VALUE => "10001111"
)
port map
(
Clk => Clk,
Rst => phy_tx_en_i_n,
Q => colWindowNibbleCnt,
Z => open,
LD => "10001111",
AD => "00000001",
LOAD => '0',
OP => txCntEnbl
);
phy_tx_en_i_n <= not(axi_phy_tx_en_i_p);
----------------------------------------------------------------------------
-- jam transmit nibble down counter
----------------------------------------------------------------------------
INST_JAMTXNIBCNT: entity axi_ethernetlite_v3_0.msh_cnt
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 4,
C_RESET_VALUE => "1001"
)
port map
(
Clk => Clk,
Rst => phy_tx_en_i_n,
Q => jamTxNibbleCnt,
Z => open,
LD => "1001",
AD => "0001",
LOAD => '0',
OP => jamTxComboNibCntEnbl
);
----------------------------------------------------------------------------
-- tx collision back off counter
----------------------------------------------------------------------------
INST_BOCNT: entity axi_ethernetlite_v3_0.bocntr
port map
(
Clk => Clk,
Clken => TxClkEn,
Rst => Rst,
InitBackoff => initBackoff,
RetryCnt => collisionRetryCnt,
BackingOff => backingOff_i
);
end generate tx3_generate;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_EN: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => tx_en_i,
prmry_ack => open,
scndry_out => tx_en_i_tx_clk,
scndry_aclk => Phy_tx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
--- ----------------------------------------------------------------------------
--- -- CDC module for syncing phy_tx_en_i in Clk domain
--- ----------------------------------------------------------------------------
--- CDC_PHY_TX_EN: entity lib_cdc_v1_0.cdc_sync
--- generic map (
--- C_CDC_TYPE => 1,
--- C_RESET_STATE => 0,
--- C_SINGLE_BIT => 1,
--- C_FLOP_INPUT => 0,
--- C_VECTOR_WIDTH => 1,
--- C_MTBF_STAGES => 4
--- )
--- port map(
--- prmry_aclk => '1',
--- prmry_resetn => '1',
--- prmry_in => phy_tx_en_i_p,
--- prmry_ack => open,
--- scndry_out => phy_tx_en_i,
--- scndry_aclk => Clk,
--- scndry_resetn => '1',
--- prmry_vect_in => (OTHERS => '0'),
--- scndry_vect_out => open
--- );
--- ----------------------------------------------------------------------------
-- CDC module for syncing rst in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_RST: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Rst,
prmry_ack => open,
scndry_out => tx_d_rst,
scndry_aclk => Phy_tx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_en_PROCESS
----------------------------------------------------------------------------
-- This process assigns the outputs the phy enable
----------------------------------------------------------------------------
INT_TX_EN_PROCESS: process (Phy_tx_clk)
begin --
if (Phy_tx_clk'event and Phy_tx_clk = '1') then
if (tx_d_rst = RESET_ACTIVE) then
phy_tx_en_i_p <= '0';
fifo_tx_en <= '0';
else
fifo_tx_en <= tx_en_i_tx_clk; -- having cdc sync for tx_en_i for MTBF
phy_tx_en_i_p <= fifo_tx_en and tx_en_i_tx_clk;
-- fifo_tx_en <= tx_en_i;
-- phy_tx_en_i <= fifo_tx_en and tx_en_i;
end if;
end if;
end process INT_TX_EN_PROCESS;
AXI_INT_TX_EN_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
axi_fifo_tx_en <= '0';
axi_phy_tx_en_i_p <= '0';
else
axi_fifo_tx_en <= tx_en_i;
axi_phy_tx_en_i_p <= axi_fifo_tx_en and tx_en_i;
end if;
end if;
end process AXI_INT_TX_EN_PROCESS;
emac_tx_wr_mod <= emac_tx_wr_i or enblclear;
tx_en_mod <= '0' when enblclear = '1' else
tx_en_i;
txChannelReset <= Rst;
txCntEnbl <= TxClkEn and axi_phy_tx_en_i_p and
not(not(full_half_n) and Phy_col);
----------------------------------------------------------------------------
-- jam transmit nibble down counter enable
----------------------------------------------------------------------------
jamTxComboNibCntEnbl <= (Phy_col or not(jamTxNibbleCnt(0) and
not(jamTxNibbleCnt(1)) and
not(jamTxNibbleCnt(2)) and
jamTxNibbleCnt(3))) and
pre_sfd_done and TxClkEn and not(full_half_n);
----------------------------------------------------------------------------
-- INT_CRC_DATA_REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the emac data going to CRCgen Module to break long
-- timing path.
----------------------------------------------------------------------------
INT_CRC_DATA_REG_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
emac_tx_wr_data_d1 <= (others=>'0');
emac_tx_wr_d1 <= '0';
txcrcen_d1 <= '0';
else
emac_tx_wr_data_d1 <= emac_tx_wr_data_i;
emac_tx_wr_d1 <= emac_tx_wr_i;
txcrcen_d1 <= txCrcEn;
end if;
end if;
end process INT_CRC_DATA_REG_PROCESS;
end imp;
| gpl-3.0 | 86c8ea21b8a5c31eeb350b56c2788cdc | 0.385704 | 4.788766 | false | false | false | false |
hoangt/PoC | src/io/io_7SegmentMux_BCD.vhdl | 2 | 3,399 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: time multiplexed 7 Segment Display Controller for BCD chars
--
-- Description:
-- ------------------------------------
-- This module is a 7 segment display controller that uses time multiplexing
-- to control a common anode for each digit in the display. The shown characters
-- are BCD encoded. A dot per digit is optional. A minus sign for negative
-- numbers is supported.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity io_7SegmentMux_BCD is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
REFRESH_RATE : FREQ := 1 kHz;
DIGITS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
BCDDigits : in T_BCD_VECTOR(DIGITS - 1 downto 0);
BCDDots : in STD_LOGIC_VECTOR(DIGITS - 1 downto 0);
SegmentControl : out STD_LOGIC_VECTOR(7 downto 0);
DigitControl : out STD_LOGIC_VECTOR(DIGITS - 1 downto 0)
);
end;
architecture rtl of io_7SegmentMux_BCD is
signal DigitCounter_rst : STD_LOGIC;
signal DigitCounter_en : STD_LOGIC;
signal DigitCounter_us : UNSIGNED(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0');
begin
Strobe : entity PoC.misc_StrobeGenerator
generic map (
STROBE_PERIOD_CYCLES => TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ),
INITIAL_STROBE => FALSE
)
port map (
Clock => Clock,
O => DigitCounter_en
);
--
DigitCounter_rst <= counter_eq(DigitCounter_us, DIGITS - 1) and DigitCounter_en;
DigitCounter_us <= counter_inc(DigitCounter_us, DigitCounter_rst, DigitCounter_en) when rising_edge(Clock);
DigitControl <= resize(bin2onehot(std_logic_vector(DigitCounter_us)), DigitControl'length);
process(BCDDigits, BCDDots, DigitCounter_us)
variable BCDDigit : T_BCD;
variable BCDDot : STD_LOGIC;
begin
BCDDigit := BCDDigits(to_index(DigitCounter_us, BCDDigits'length));
BCDDot := BCDDots(to_index(DigitCounter_us, BCDDigits'length));
if (BCDDigit < C_BCD_MINUS) then
SegmentControl <= io_7SegmentDisplayEncoding(BCDDigit, BCDDot);
elsif (BCDDigit = C_BCD_MINUS) then
SegmentControl <= BCDDot & "1000000";
else
SegmentControl <= "00000000";
end if;
end process;
end;
| apache-2.0 | e07cc594fa24cf811448333555ddfd71 | 0.644307 | 3.518634 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/pll/SysPLL_k7.vhd | 2 | 8,013 | -- file: SysPLL_k7.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____60.000
-- CLK_OUT1____15.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_k7 is
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_k7;
architecture xilinx of SysPLL_k7 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_k7,clk_wiz_v3_6,{component_name=SysPLL_k7,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN1_P,
IB => CLK_IN1_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 10,
CLKFBOUT_MULT_F => 51.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 17.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 68,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
CLK_OUT2 <= clkout1;
end xilinx;
| bsd-2-clause | 75621564cf58a32064b9922e9fccddf0 | 0.581555 | 4.115562 | false | false | false | false |
hoangt/PoC | src/mem/ocram/ocram_sdp.vhdl | 1 | 7,044 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating simple dual-port memory, with:
-- * dual clock, clock enable,
-- * 1 read port plus 1 write port.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- The Altera M512/M4K TriMatrix memory (as found e.g. in Stratix and
-- Stratix II FPGAs) defines the minimum time after which the written data at
-- the write port can be read-out at read port again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d" written at the rising-edge of "wclk" at address
-- "wa" can be read-out at the read port from the same address with the
-- 2nd rising-edge of "rclk" following the falling-edge of "wclk".
-- If the rising-edge of "rclk" coincides with the falling-edge of "wclk"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "rclk" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ocram_sdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
rclk : in std_logic; -- read clock
rce : in std_logic; -- read clock-enable
wclk : in std_logic; -- write clock
wce : in std_logic; -- write clock-enable
we : in std_logic; -- write enable
ra : in unsigned(A_BITS-1 downto 0); -- read address
wa : in unsigned(A_BITS-1 downto 0); -- write address
d : in std_logic_vector(D_BITS-1 downto 0); -- data in
q : out std_logic_vector(D_BITS-1 downto 0)); -- data out
end entity;
library std;
use std.TextIO.all;
library IEEE;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
architecture rtl of ocram_sdp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA generate
-- RAM can be inferred correctly
-- Xilinx notes:
-- WRITE_MODE is set to WRITE_FIRST, but this also means that read data
-- is unknown on the opposite port. (As expected.)
-- Altera notes:
-- Setting attribute "ramstyle" to "no_rw_check" suppresses generation of
-- bypass logic, when 'clk1'='clk2' and 'ra' is feed from a register.
-- This is the expected behaviour.
-- With two different clocks, synthesis complains about an undefined
-- read-write behaviour, that can be ignored.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
attribute ramstyle : string;
-- Compute the initialization of a RAM array, if specified, from the passed file.
impure function ocram_InitMemory(FileName : string) return ram_t is
-- Read the specified file name into the RAM array.
procedure ReadMemFile(FileName : in string; variable mem : inout ram_t) is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
mem(i) := TempWord(word_t'range);
end loop;
end;
variable res : ram_t := (others => (others => 'U'));
begin
if str_length(FileName) > 0 then
ReadMemFile(FileName, res);
end if;
return res;
end ocram_InitMemory;
signal ram : ram_t := ocram_InitMemory(FILENAME);
attribute ramstyle of ram : signal is "no_rw_check";
begin
process(wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
-- Note: Hide plausibility tests from synthesis to ensure
-- proper RAM inference.
--synthesis translate_off
if Is_X(std_logic_vector(wa)) then
report "ocram_sdp: Writing to ill-defined address."
severity error;
else
--synthesis translate_on
ram(to_integer(wa)) <= d;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
process(rclk)
begin
if rising_edge(rclk) then
if rce = '1' then
-- Note: Hide plausibility tests from synthesis to ensure
-- proper RAM inference.
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
elsif ra = wa then
-- read data unknown when reading at write address
q <= (others => 'X');
report "ocram_sdp: Reading from address just writing: Unknown result."
severity warning;
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate gInfer;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
| apache-2.0 | 61fdd403c0ca6b2819725935b7fcafc8 | 0.624361 | 3.776944 | false | false | false | false |
hoangt/PoC | src/xil/xil_SystemMonitor_Series7.vhdl | 2 | 5,321 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: XADC wrapper for temperature supervision applications
--
-- Description:
-- ------------------------------------
-- This module wraps a Series-7 XADC to report if preconfigured temperature values
-- are overrun. The XADC was formerly known as "System Monitor".
--
-- Temperature curve:
-- ------------------
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UniSim;
use UniSim.vComponents.all;
entity xil_SystemMonitor_Series7 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms
VP : in STD_LOGIC; -- Dedicated Analog Input Pair
VN : in STD_LOGIC
);
end;
architecture xilinx of xil_SystemMonitor_Series7 IS
SIGNAL FLOAT_VCCAUX_ALARM : STD_LOGIC;
SIGNAL FLOAT_VCCINT_ALARM : STD_LOGIC;
SIGNAL FLOAT_VBRAM_ALARM : STD_LOGIC;
SIGNAL FLOAT_MUXADDR : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL aux_channel_p : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL aux_channel_n : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL XADC_Alarm : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
genAUXChannel : for i in 0 to 15 generate
aux_channel_p(I) <= '0';
aux_channel_n(I) <= '0';
end generate;
SysMonitor : XADC
generic map (
INIT_40 => x"8000", -- config reg 0
INIT_41 => x"8f0c", -- config reg 1
INIT_42 => x"0400", -- config reg 2
INIT_48 => x"0000", -- Sequencer channel selection
INIT_49 => x"0000", -- Sequencer channel selection
INIT_4A => x"0000", -- Sequencer Average selection
INIT_4B => x"0000", -- Sequencer Average selection
INIT_4C => x"0000", -- Sequencer Bipolar selection
INIT_4D => x"0000", -- Sequencer Bipolar selection
INIT_4E => x"0000", -- Sequencer Acq time selection
INIT_4F => x"0000", -- Sequencer Acq time selection
INIT_50 => x"9c87", -- Temp alarm trigger
INIT_51 => x"57e4", -- Vccint upper alarm limit
INIT_52 => x"a147", -- Vccaux upper alarm limit
INIT_53 => x"b363", -- Temp alarm OT upper
INIT_54 => x"99fd", -- Temp alarm reset
INIT_55 => x"52c6", -- Vccint lower alarm limit
INIT_56 => x"9555", -- Vccaux lower alarm limit
INIT_57 => x"a93a", -- Temp alarm OT reset
INIT_58 => x"5999", -- Vbram upper alarm limit
INIT_5C => x"5111", -- Vbram lower alarm limit
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "design.txt"
)
port map (
-- Control and Clock
RESET => Reset,
CONVSTCLK => '0',
CONVST => '0',
-- DRP port
DCLK => '0',
DEN => '0',
DADDR => "0000000",
DWE => '0',
DI => x"0000",
DO => open,
DRDY => open,
-- External analog inputs
VAUXN => aux_channel_n(15 downto 0),
VAUXP => aux_channel_p(15 downto 0),
VN => VN,
VP => VP,
-- Alarms
OT => Alarm_OverTemp,
ALM => XADC_Alarm,
-- Status
MUXADDR => FLOAT_MUXADDR,
CHANNEL => open,
BUSY => open,
EOC => open,
EOS => open,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open
);
Alarm <= XADC_Alarm(7);
Alarm_UserTemp <= XADC_Alarm(0);
end;
| apache-2.0 | 1d278c4b239739f16ead649d8eb4ccc1 | 0.510242 | 3.163496 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/defer_state.vhd | 4 | 12,686 | -------------------------------------------------------------------------------
-- defer_state - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : defer_state.vhd
-- Version : v2.0
-- Description : This file contains the transmit deferral state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxEn -- Transmit enable
-- Txrst -- Transmit reset
-- Ifgp2Done -- Interframe gap2 done
-- Ifgp1Done -- Interframe gap1 done
-- BackingOff -- Backing off
-- Crs -- Carrier sense
-- Full_half_n -- Full/Half duplex indicator
-- Deferring -- Deffering for the tx data
-- CntrEnbl -- Counter enable
-- CntrLd -- Counter load
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity defer_state is
port (
Clk : in std_logic;
Rst : in std_logic;
TxEn : in std_logic;
Txrst : in std_logic;
Ifgp2Done : in std_logic;
Ifgp1Done : in std_logic;
BackingOff : in std_logic;
Crs : in std_logic;
Full_half_n : in std_logic;
Deferring : out std_logic;
CntrEnbl : out std_logic;
CntrLd : out std_logic
);
end defer_state;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of defer_state is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type StateName is (loadCntr,startIfgp1Cnt,startIfgp2Cnt,cntDone);
signal thisState : StateName;
signal nextState : StateName;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the tx state machine
begin
----------------------------------------------------------------------------
-- FSMR Process
----------------------------------------------------------------------------
-- An FSM that deals with transmitting data
----------------------------------------------------------------------------
FSMR : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1' or Txrst = '1') then
thisState <= loadCntr;
else
thisState <= nextState;
end if;
end if;
end process FSMR;
----------------------------------------------------------------------------
-- FSMC Process
----------------------------------------------------------------------------
FSMC : process (thisState,TxEn,Ifgp2Done,Ifgp1Done,BackingOff,Crs,
Full_half_n)
begin --
case thisState is
when loadCntr =>
if (((TxEn = '0') and (Full_half_n = '1')) or
((Crs = '0') and (Full_half_n = '0') and
(BackingOff = '0'))) and
Ifgp1Done = '0' and Ifgp2Done = '0' then
nextState <= startIfgp1Cnt;
else
nextState <= loadCntr; -- wait for end of transmission
end if;
when startIfgp1Cnt =>
if (((Crs = '1') and (Full_half_n = '0')) or
((BackingOff = '1') and (Full_half_n = '0'))) then
nextState <= loadCntr;
elsif (Ifgp1Done = '1') then -- gap done
nextState <= startIfgp2Cnt;
else
nextState <= startIfgp1Cnt; -- still counting
end if;
when startIfgp2Cnt =>
-- Added check for CRS to reset counter in when CRS goes low.
if (((Crs = '1') and (Full_half_n = '0')) or
((BackingOff = '1') and (Full_half_n = '0'))) then
nextState <= loadCntr;
elsif (Ifgp2Done = '1') then -- gap done
nextState <= cntDone;
else
nextState <= startIfgp2Cnt; -- still counting
end if;
when cntDone =>
if (TxEn = '1' or Crs = '1') then -- transmission started
nextState <= loadCntr;
else
nextState <= cntDone;
end if;
-- coverage off
when others => null;
nextState <= loadCntr;
-- coverage on
end case;
end process FSMC;
----------------------------------------------------------------------------
-- FSMD Process
----------------------------------------------------------------------------
FSMD : process(thisState)
begin --
if ((thisState = loadCntr) or (thisState = startIfgp1Cnt) or
(thisState = startIfgp2Cnt)) then
Deferring <= '1';
else
Deferring <= '0';
end if;
if ((thisState = startIfgp1Cnt) or (thisState = startIfgp2Cnt)) then
CntrEnbl <= '1';
else
CntrEnbl <= '0';
end if;
if (thisState = loadCntr) then
CntrLd <= '1';
else
CntrLd <= '0';
end if;
end process FSMD;
end implementation;
| gpl-3.0 | d5968242a271e2ed5b70254c9f61a9c2 | 0.381365 | 5.487024 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/synth/design_1_microblaze_0_0.vhd | 2 | 64,533 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:9.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v9_5;
USE microblaze_v9_5.MicroBlaze;
ENTITY design_1_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END design_1_microblaze_0_0;
ARCHITECTURE design_1_microblaze_0_0_arch OF design_1_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_0_arch : ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.5,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=design_1_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x60000000,C_ICACHE_HIGHADDR=0x60ffffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=10,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x60000000,C_DCACHE_HIGHADDR=0x60ffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=10,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTANCE => "design_1_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"00000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"60000000",
C_ICACHE_HIGHADDR => X"60ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 10,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"60000000",
C_DCACHE_HIGHADDR => X"60ffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 10,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
Dbg_Disable => '0',
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END design_1_microblaze_0_0_arch;
| gpl-3.0 | e3bf8a40ca4e9876a354e2998a4c6934 | 0.643578 | 2.848385 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/misc/nasti_sram.vhd | 2 | 3,629 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Internal SRAM module with the byte access
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_sram is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for inferred
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end;
architecture arch_nasti_sram of nasti_sram is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_SRAM,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type registers is record
bank_axi : nasti_slave_bank_type;
end record;
type ram_in_type is record
raddr : global_addr_array_type;
waddr : global_addr_array_type;
we : std_logic;
wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
end record;
signal r, rin : registers;
signal rdata_mux : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
signal rami : ram_in_type;
begin
comblogic : process(i, r, rdata_mux)
variable v : registers;
variable vrami : ram_in_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
begin
v := r;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
vrami.raddr := functionAddressReorder(v.bank_axi.raddr(0)(3 downto 2),
v.bank_axi.raddr);
vrami.we := '0';
if (i.w_valid = '1' and r.bank_axi.wstate = wtrans
and r.bank_axi.wresp = NASTI_RESP_OKAY) then
vrami.we := '1';
end if;
procedureWriteReorder(vrami.we,
r.bank_axi.waddr(0)(3 downto 2),
r.bank_axi.waddr,
i.w_strb,
i.w_data,
vrami.waddr,
vrami.wstrb,
vrami.wdata);
rdata := functionDataRestoreOrder(r.bank_axi.raddr(0)(3 downto 2),
rdata_mux);
o <= functionAxi4Output(r.bank_axi, rdata);
rami <= vrami;
rin <= v;
end process;
cfg <= xconfig;
tech0 : srambytes_tech generic map (
memtech => memtech,
abits => abits,
init_file => init_file -- only for 'inferred'
) port map (
clk => clk,
raddr => rami.raddr,
rdata => rdata_mux,
waddr => rami.waddr,
we => rami.we,
wstrb => rami.wstrb,
wdata => rami.wdata
);
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | f72d0183e8c4ce1b8187e1cb42f2df01 | 0.554974 | 3.618146 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/tilelink/htifctrl.vhd | 2 | 2,317 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details Implementation of the Host Controller device.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief HostIO (HTIF) bus controller.
entity htifctrl is
port (
clk : in std_logic;
nrst : in std_logic;
srcsi : in host_out_vector;
srcso : out host_out_type;
htifii : in host_in_type;
htifio : out host_in_type
);
end;
architecture arch_htifctrl of htifctrl is
constant HTIF_ZERO : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0) := (others => '0');
type reg_type is record
idx : integer range 0 to CFG_HTIF_SRC_TOTAL-1;
srcsel : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0);
end record;
signal rin, r : reg_type;
begin
comblogic : process(srcsi, htifii, r)
variable v : reg_type;
variable idx : integer range 0 to CFG_HTIF_SRC_TOTAL-1;
variable srcsel : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0);
variable req : std_logic;
begin
v := r;
req := '0';
idx := 0;
srcsel := r.srcsel;
for n in 0 to CFG_HTIF_SRC_TOTAL-1 loop
if req = '0' and srcsi(n).csr_req_valid = '1' then
idx := n;
req := '1';
end if;
end loop;
if (srcsel = HTIF_ZERO) or (htifii.csr_resp_valid and srcsi(r.idx).csr_resp_ready) = '1' then
srcsel(r.idx) := '0';
srcsel(idx) := req;
v.idx := idx;
else
idx := r.idx;
end if;
v.srcsel := srcsel;
rin <= v;
srcso <= srcsi(idx);
htifio.grant <= srcsel;
htifio.csr_req_ready <= htifii.csr_req_ready;
htifio.csr_resp_valid <= htifii.csr_resp_valid;
htifio.csr_resp_bits <= htifii.csr_resp_bits;
htifio.debug_stats_csr <= htifii.debug_stats_csr;
end process;
reg0 : process(clk, nrst) begin
if nrst = '0' then
r.idx <= 0;
r.srcsel <= (others =>'0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 1192ec45bbc21901287bd2a5d820a785 | 0.562797 | 3.422452 | false | false | false | false |
RussGlover/381-module-1 | project/hardware/vhdl/sqrt.vhd | 1 | 908 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; -- for UNSIGNED
package sqrt_package is
function sqrt ( d : UNSIGNED ) return UNSIGNED;
end sqrt_package;
package body sqrt_package is
function sqrt ( d : UNSIGNED ) return UNSIGNED is
variable a : unsigned(31 downto 0):=d; --original input.
variable q : unsigned(15 downto 0):=(others => '0'); --result.
variable left,right,r : unsigned(17 downto 0):=(others => '0'); --input to adder/sub.r-remainder.
variable i : integer:=0;
begin
for i in 0 to 15 loop
right(0):='1';
right(1):=r(17);
right(17 downto 2):=q;
left(1 downto 0):=a(31 downto 30);
left(17 downto 2):=r(15 downto 0);
a(31 downto 2):=a(29 downto 0); --shifting by 2 bit.
if ( r(17) = '1') then
r := left + right;
else
r := left - right;
end if;
q(15 downto 1) := q(14 downto 0);
q(0) := not r(17);
end loop;
return q;
end sqrt;
end sqrt_package; | mit | 7284e8d4dbaccb247e19d1ba44f786b8 | 0.64978 | 2.802469 | false | false | false | false |
hoangt/PoC | tb/arith/arith_prefix_and_tb.vhdl | 2 | 2,336 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Testbench: Testbench for arith_prefix_and.
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith.prefix_and
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity arith_prefix_and_tb is
end arith_prefix_and_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.simulation.ALL;
architecture tb of arith_prefix_and_tb is
-- component generics
constant N : positive := 8;
-- component ports
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic_vector(N-1 downto 0);
begin -- tb
-- component instantiation
DUT: entity PoC.arith_prefix_and
generic map (
N => N
)
port map (
x => x,
y => y
);
-- Stimuli
process
begin
-- Exhaustive Testing
for i in NATURAL range 0 to 2**N-1 loop
x <= std_logic_vector(to_unsigned(i, N));
wait for 10 ns;
for j in 0 to N-1 loop
tbAssert((y(j) = '1') = (x(j downto 0) = (j downto 0 => '1')),
"Wrong result for "&integer'image(i)&" / "&integer'image(j));
end loop;
end loop;
-- Report overall result
tbPrintResult;
wait; -- forever
end process;
end tb;
| apache-2.0 | 5b75d3f5ac2564030fd0fef37aa1b7c0 | 0.579195 | 3.854785 | false | false | false | false |
hoangt/PoC | src/misc/sync/sync_Bits.vhdl | 2 | 4,342 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Synchronizes a flag signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes multiple flag bits from clock-domain 'Clock1' to
-- clock-domain 'Clock'. The clock-domain boundary crossing is done by two
-- synchronizer D-FFs. All bits are independent from each other. If a known
-- vendor like Altera or Xilinx are recognized, a vendor specific
-- implementation is choosen.
--
-- ATTENTION:
-- Use this synchronizer only for long time stable signals (flags).
--
-- CONSTRAINTS:
-- General:
-- Please add constraints for meta stability to all '_meta' signals and
-- timing ignore constraints to all '_async' signals.
--
-- Xilinx:
-- In case of a Xilinx device, this module will instantiate the optimized
-- module PoC.xil.SyncBits. Please attend to the notes of xil_SyncBits.vhdl.
--
-- Altera sdc file:
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.sync.all;
entity sync_Bits is
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits
);
port (
Clock : in STD_LOGIC; -- <Clock> output clock domain
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits
);
end entity;
architecture rtl of sync_Bits is
constant INIT_I : STD_LOGIC_VECTOR := resize(descend(INIT), BITS);
begin
genGeneric : if ((VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX)) generate
attribute ASYNC_REG : STRING;
attribute SHREG_EXTRACT : STRING;
begin
gen : for i in 0 to BITS - 1 generate
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := INIT_I(i);
signal Data_sync : STD_LOGIC := INIT_I(i);
-- Mark register DataSync_async's input as asynchronous and ignore timings (TIG)
attribute ASYNC_REG of Data_meta : signal is "TRUE";
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of Data_meta : signal is "NO";
attribute SHREG_EXTRACT of Data_sync : signal is "NO";
begin
Data_async <= Input(i);
process(Clock)
begin
if rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output(i) <= Data_sync;
end generate;
end generate;
-- use dedicated and optimized 2 D-FF synchronizer for Altera FPGAs
genAltera : if (VENDOR = VENDOR_ALTERA) generate
sync : sync_Bits_Altera
generic map (
BITS => BITS,
INIT => INIT_I
)
port map (
Clock => Clock,
Input => Input,
Output => Output
);
end generate;
-- use dedicated and optimized 2 D-FF synchronizer for Xilinx FPGAs
genXilinx : if (VENDOR = VENDOR_XILINX) generate
sync : sync_Bits_Xilinx
generic map (
BITS => BITS,
INIT => INIT_I
)
port map (
Clock => Clock,
Input => Input,
Output => Output
);
end generate;
end architecture;
| apache-2.0 | db05b163cd548b874c54d72f1beafa7c | 0.616997 | 3.582508 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/axi_intc.vhd | 4 | 24,943 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1;
use axi_intc_v4_1.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc iInterface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0); --- newly added port
interrupt_address : out std_logic_vector(31 downto 0); --- newly added port
--
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Component Declarations
---------------------------------------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => C_NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
| gpl-3.0 | 70c9b51926be131e94a901cefc7d715e | 0.504711 | 4.051819 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/eth/grethaxi.vhd | 2 | 25,542 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the grethaxi device.
--! @details This is Ethernet MAC device with the AMBA AXI inteface
--! and EDCL debugging functionality.
------------------------------------------------------------------------------
--!
--! @page eth_link Ethernet
--!
--! @par Overview
--! The Ethernet Media Access Controller (GRETH) provides an interface between
--! an AMBA-AXI bus and Ethernet network. It supports 10/100 Mbit speed in both
--! full- and half-duplex modes. Integrated EDCL submodule implements hardware
--! decoding of UDP traffic and redirects EDCL request directly on AXI system
--! bus. The AMBA interface consists of an AXI slave
--! interface for configuration and control and an AXI master interface
--! for transmit and receive data. There is one DMA engine for the transmitter
--! and one for receiver. EDCL submodule and both DMA engines share the same
--! AXI master interface.
--!
--! @subsection eth_confgure Configure Host Computer
--! To make development board visible in your local network your should
--! properly specify connection properties. In this chapter I will show how to
--! configure the host computer (Windows 7 or Linux) to communicate with the
--! FPGA hardware over Ethernet.
--!
--! @note <em>If you also want simultaneous Internet access your host computer
--! requires a second Ethernet port. I couldn't find workable
--! configuration via router.</em>
--!
--! @warning I recommend you to make restore point before you start.
--!
--! @section eth_cfgwin Configure Windows Host
--!
--! Let's setup the following network configuration that allows to work with
--! FPGA board and to be connected to Internet. I use different Ethernet
--! ports and different subnets (192.168.0.x and 192.168.1.x accordingly).
--!
--! <img src="pics/eth_common.png" alt="Ethernet config">
--!
--! @par Host IP and subnet definition:
--! -# Open \c cmd console.
--! -# Use \c ipconfig command to determine network settings.</b>
--! @verbatim
--! ipconfig /all
--! @endverbatim
--! -# Find your IP address (in my case it's 192.168.1.4)
--! -# Check and change if needed default IP address of SOC as follow.
--!
--! @par Setup hard-reset FPGA IP address:
--! -# Open in editor <i>rocket_soc.vhd</i>.
--! -# Find place where <i>grethaxi</i> module is instantiated.
--! -# Change generic <b>ipaddrh</b> and <b>ipaddrl</b> parameters so that
--! they belonged another subnet (Default values: C0A8.0033 corresponding
--! to 192.168.0.51) than Internet connection.
--!
--! @par Configure the Ethernet card for your FPGA hardware
--! -# Load pre-built image file into FPGA board (located in
--! <i>./rocket_soc/bit_files/</i> folder) or use your own one.<br>
--! -# Open <b>Network and Sharing Center</b> via Control Panel
--! <img src="pics/eth_win1.png" alt="ControlPanel">
--! -# Click on <b>Local Area Connection 2</b> link
--! <img src="pics/eth_win2.png" alt="ControlPanel">
--! -# Click on <b>Properties</b> to open properties dialog.
--! <img src="pics/eth_win3.png" alt="ControlPanel">
--! -# Disable all network services except <b>Internet Protocol Version 4</b>
--! as shown on figure above.<br>
--! -# Select enabled service and click on <b>Properties</b> button.
--! <img src="pics/eth_win4.png" alt="ControlPanel">
--! -# Specify unique IP as shown above so that FPGA and your Local
--! Connection were placed <b>in the same subnet</b>.<br>
--! -# Leave the subnet mask set to the default value 255.255.255.0.<br>
--! -# Click OK.
--!
--! @par Check connection
--! -# Check presence of the Ethernet activity by blinking LEDs near the
--! Ethernet connector on FPGA board
--! -# Run \c arp command to see arp table entries.
--! @verbatim
--! arp -a -v
--! @endverbatim
--! <img src="pics/eth_check1.png" alt="Check arp">
--! -# MAC supports only ARP and EDCL requests on hardware level and it cannot
--! respond on others without properly installed software. By this reason ping
--! won't work without running OS on FPGA target but it maybe usefull to ping
--! FPGA target so that it can force updating of the ARP table.
--!
--! @section eth_cfglin Configure Linux Host
--!
--! Let's setup the similar network configuration on Linux host.
--! -# Check <b>ipaddrh</b> and <b>ipaddrl</b> values that are hardcoded
--! on top-level of SOC (default values: C0A8.0033 corresponding
--! to 192.168.0.51).
--! -# Set host IP value in the same subnet using the \c ifconfig command.
--! You might need to enter a password to use the \c sudo command.
--! @verbatim
--! % sudo ifconfig eth0 192.168.0.53 netmask 255.255.255.0
--! @endverbatim
--! -# Enter the following command in the shell to check that the changes
--! took effect:
--! @verbatim
--! % ifconfig eth0
--! @endverbatim
--!
--! @section eth_appl Run Application
--!
--! Now your FPGA board is ready to interact with the host computer via Ethernet.
--! You can find detailed information about MAC (GRETH)
--! in [GRLIB IP Core User's Manual](http://gaisler.com/products/grlib/grip.pdf).
--!
--! There you can find:
--! -# DMA Configuration registers description (Rx/Tx Descriptors tables and entries).
--! -# EDCL message format.
--! -# \c GRLIB itself includes C-example that configure MAC Rx/Tx queues
--! and start transmission of the 1500 Mbyte of data to define Bitrate in Mbps.
--!
--! We provide debugger functionality via Ethernet.
--! See @link dbg_link Debugger description @endlink page.
--!
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Ethernet specific declarations.
library rocketlib;
use rocketlib.grethpkg.all;
entity grethaxi is
generic(
xslvindex : integer := 0;
xmstindex : integer := 0;
xmstindex2 : integer := 1;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0135#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : in nasti_master_in_type;
msto : out nasti_master_out_type;
mstcfg : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
slvi : in nasti_slave_in_type;
slvo : out nasti_slave_out_type;
slvcfg : out nasti_slave_config_type;
ethi : in eth_in_type;
etho : out eth_out_type;
irq : out std_logic
);
end entity;
architecture arch_grethaxi of grethaxi is
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant xslvconfig : nasti_slave_config_type := (
xindex => xslvindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_ETHMAC,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
constant xmstconfig : nasti_master_config_type := (
xindex => xmstindex,
vid => VENDOR_GNSSSENSOR,
did => GAISLER_ETH_MAC_MASTER,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xmstindex2,
vid => VENDOR_GNSSSENSOR,
did => GAISLER_ETH_EDCL_MASTER,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of std_logic_vector(15 downto 0);
type registers is record
bank_slv : nasti_slave_bank_type;
ctrl : eth_control_type;
end record;
signal r, rin : registers;
signal imac_cmd : eth_command_type;
signal omac_status : eth_mac_status_type;
signal omac_rdbgdata : std_logic_vector(31 downto 0);
signal omac_tmsto : eth_tx_ahb_in_type;
signal imac_tmsti : eth_tx_ahb_out_type;
signal omac_tmsto2 : eth_tx_ahb_in_type;
signal imac_tmsti2 : eth_tx_ahb_out_type;
signal omac_rmsto : eth_rx_ahb_in_type;
signal imac_rmsti : eth_rx_ahb_out_type;
begin
comb : process(r, ethi, slvi, omac_rdbgdata, omac_status, rst) is
variable v : registers;
variable vcmd : eth_command_type;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wdata32 : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable val : std_logic_vector(8*CFG_ALIGN_BYTES-1 downto 0);
begin
v := r;
vcmd := eth_command_none;
procedureAxi4(slvi, xslvconfig, r.bank_slv, v.bank_slv);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := r.bank_slv.raddr(n)(17 downto log2(CFG_ALIGN_BYTES));
val := (others => '0');
if (ramdebug = 0) or (raddr_reg(n)(15 downto 14) = "00") then
case raddr_reg(n)(3 downto 0) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
val(13) := r.ctrl.ramdebugen;
end if;
if (edcl /= 0) then
val(31) := '1';
val(30 downto 28) := bufsize;
val(14) := r.ctrl.edcldis;
val(12) := r.ctrl.disableduplex;
end if;
if enable_mdint = 1 then
val(26) := '1';
val(10) := r.ctrl.pstatirqen;
end if;
if multicast = 1 then
val(25) := '1';
val(11) := r.ctrl.mcasten;
end if;
if rmii = 1 then
val(7) := omac_status.speed;
end if;
val(6) := omac_status.reset;
val(5) := r.ctrl.prom;
val(4) := omac_status.full_duplex;
val(3) := r.ctrl.rx_irqen;
val(2) := r.ctrl.tx_irqen;
val(1) := omac_status.rxen;
val(0) := omac_status.txen;
when "0001" => --status/int source reg
val(9) := not (omac_status.edcltx_idle or omac_status.edclrx_idle);
if enable_mdint = 1 then
val(8) := omac_status.phystat;
end if;
val(7) := omac_status.invaddr;
val(6) := omac_status.toosmall;
val(5) := omac_status.txahberr;
val(4) := omac_status.rxahberr;
val(3) := omac_status.tx_int;
val(2) := omac_status.rx_int;
val(1) := omac_status.tx_err;
val(0) := omac_status.rx_err;
when "0010" => --mac addr lsb
val := r.ctrl.mac_addr(31 downto 0);
when "0011" => --mac addr msb/mdio address
val(15 downto 0) := r.ctrl.mac_addr(47 downto 32);
when "0100" => --mdio ctrl/status
val(31 downto 16) := omac_status.mdio.cmd.data;
val(15 downto 11) := r.ctrl.mdio_phyadr;
val(10 downto 6) := omac_status.mdio.cmd.regadr;
val(3) := omac_status.mdio.busy;
val(2) := omac_status.mdio.linkfail;
val(1) := omac_status.mdio.cmd.read;
val(0) := omac_status.mdio.cmd.write;
when "0101" => --tx descriptor
val(31 downto 10) := r.ctrl.txdesc;
val(9 downto 3) := omac_status.txdsel;
when "0110" => --rx descriptor
val(31 downto 10) := r.ctrl.rxdesc;
val(9 downto 3) := omac_status.rxdsel;
when "0111" => --edcl ip
if (edcl /= 0) then
val := r.ctrl.edclip;
end if;
when "1000" =>
if multicast = 1 then
val := r.ctrl.hash(63 downto 32);
end if;
when "1001" =>
if multicast = 1 then
val := r.ctrl.hash(31 downto 0);
end if;
when "1010" =>
if edcl /= 0 then
val(15 downto 0) := r.ctrl.emacaddr(47 downto 32);
end if;
when "1011" =>
if edcl /= 0 then
val := r.ctrl.emacaddr(31 downto 0);
end if;
when others => null;
end case;
elsif raddr_reg(n)(15 downto 14) = "01" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
elsif raddr_reg(n)(15 downto 14) = "10" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
elsif raddr_reg(n)(15 downto 14) = "11" then
if (ramdebug = 2) and (edcl /= 0) then
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
val := omac_rdbgdata;
end if;
end if;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := val;
end loop;
if slvi.w_valid = '1' and
r.bank_slv.wstate = wtrans and
r.bank_slv.wresp = NASTI_RESP_OKAY then
wdata := slvi.w_data;
wstrb := slvi.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := r.bank_slv.waddr(n)(17 downto 2);
wdata32 := wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
if wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n) /= "0000" then
if (ramdebug = 0) or (waddr_reg(n)(15 downto 14) = "00") then
case waddr_reg(n)(3 downto 0) is
when "0000" => --ctrl reg
if ramdebug /= 0 then
v.ctrl.ramdebugen := wdata32(13);
end if;
if edcl /= 0 then
v.ctrl.edcldis := wdata32(14);
v.ctrl.disableduplex := wdata32(12);
end if;
if multicast = 1 then
v.ctrl.mcasten := wdata32(11);
end if;
if enable_mdint = 1 then
v.ctrl.pstatirqen := wdata32(10);
end if;
if rmii = 1 then
vcmd.set_speed := wdata32(7);
vcmd.clr_speed := not wdata32(7);
end if;
vcmd.set_reset := wdata32(6);
vcmd.clr_reset := not wdata32(6);
v.ctrl.prom := wdata32(5);
vcmd.set_full_duplex := wdata32(4);
vcmd.clr_full_duplex := not wdata32(4);
v.ctrl.rx_irqen := wdata32(3);
v.ctrl.tx_irqen := wdata32(2);
vcmd.set_rxena := wdata32(1);
vcmd.clr_rxena := not wdata32(1);
vcmd.set_txena := wdata32(0);
vcmd.clr_txena := not wdata32(0);
when "0001" => --status/int source reg
if enable_mdint = 1 then
vcmd.clr_status_phystat := wdata32(8);
end if;
vcmd.clr_status_invaddr := wdata32(7);
vcmd.clr_status_toosmall := wdata32(6);
vcmd.clr_status_txahberr := wdata32(5);
vcmd.clr_status_rxahberr := wdata32(4);
vcmd.clr_status_tx_int := wdata32(3);
vcmd.clr_status_rx_int := wdata32(2);
vcmd.clr_status_tx_err := wdata32(1);
vcmd.clr_status_rx_err := wdata32(0);
when "0010" => --mac addr lsb
v.ctrl.mac_addr(31 downto 0) := wdata32(31 downto 0);
when "0011" => --mac addr msb
v.ctrl.mac_addr(47 downto 32) := wdata32(15 downto 0);
when "0100" => --mdio ctrl/status
if enable_mdio = 1 then
vcmd.mdio_cmd.valid := not omac_status.mdio.busy;
if omac_status.mdio.busy = '0' then
v.ctrl.mdio_phyadr := wdata32(15 downto 11);
end if;
vcmd.mdio_cmd.data := wdata32(31 downto 16);
vcmd.mdio_cmd.regadr := wdata32(10 downto 6);
vcmd.mdio_cmd.read := wdata32(1);
vcmd.mdio_cmd.write := wdata32(0);
end if;
when "0101" => --tx descriptor
vcmd.set_txdsel := '1';
vcmd.txdsel := wdata32(9 downto 3);
v.ctrl.txdesc := wdata32(31 downto 10);
when "0110" => --rx descriptor
vcmd.set_rxdsel := '1';
vcmd.rxdsel := wdata32(9 downto 3);
v.ctrl.rxdesc := wdata32(31 downto 10);
when "0111" => --edcl ip
if (edcl /= 0) then
v.ctrl.edclip := wdata32;
end if;
when "1000" => --hash msb
if multicast = 1 then
v.ctrl.hash(63 downto 32) := wdata32;
end if;
when "1001" => --hash lsb
if multicast = 1 then
v.ctrl.hash(31 downto 0) := wdata32;
end if;
when "1010" =>
if edcl /= 0 then
v.ctrl.emacaddr(47 downto 32) := wdata32(15 downto 0);
end if;
when "1011" =>
if edcl /= 0 then
v.ctrl.emacaddr(31 downto 0) := wdata32;
end if;
when others => null;
end case;
elsif waddr_reg(n)(15 downto 14) = "01" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
elsif waddr_reg(n)(15 downto 14) = "10" then
if ramdebug /= 0 then
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
elsif waddr_reg(n)(15 downto 14) = "11" then
if (ramdebug = 2) and (edcl /= 0) then
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
vcmd.dbg_wdata := wdata32;
end if;
end if;
end if;
end loop;
end if;
slvo <= functionAxi4Output(r.bank_slv, rdata);
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if rst = '0' then
v.bank_slv := NASTI_SLAVE_BANK_RESET;
v.ctrl.tx_irqen := '0';
v.ctrl.rx_irqen := '0';
v.ctrl.prom := '0';
v.ctrl.pstatirqen := '0';
v.ctrl.mcasten := '0';
v.ctrl.ramdebugen := '0';
if edcl = 3 then
v.ctrl.edcldis := ethi.edcldisable;
elsif edcl /= 0 then
v.ctrl.edcldis := '0';
end if;
v.ctrl.disableduplex := '0';
if phyrstadr /= 32 then
v.ctrl.mdio_phyadr := conv_std_logic_vector(phyrstadr, 5);
else
v.ctrl.mdio_phyadr := ethi.phyrstaddr;
end if;
v.ctrl.mac_addr := (others => '0');
v.ctrl.txdesc := (others => '0');
v.ctrl.rxdesc := (others => '0');
v.ctrl.hash := (others => '0');
v.ctrl.edclip := conv_std_logic_vector(ipaddrh, 16) &
conv_std_logic_vector(ipaddrl, 16);
v.ctrl.emacaddr := conv_std_logic_vector(macaddrh, 24) &
conv_std_logic_vector(macaddrl, 24);
if edcl > 1 then
v.ctrl.edclip(3 downto 0) := ethi.edcladdr;
v.ctrl.emacaddr(3 downto 0) := ethi.edcladdr;
end if;
end if;
rin <= v;
imac_cmd <= vcmd;
end process;
slvcfg <= xslvconfig;
mstcfg <= xmstconfig;
mstcfg2 <= xmstconfig2;
eth64 : grethc64 generic map (
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
) port map (
rst => rst,
clk => clk,
ctrli => r.ctrl,
cmdi => imac_cmd,
statuso => omac_status,
rdbgdatao => omac_rdbgdata,
--irq
irq => irq,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
tx_dv => ethi.tx_dv,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_en => ethi.rx_en,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
testrst => '0',
testen => '0',
testoen => '0',
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed,
tmsto => omac_tmsto,
tmsti => imac_tmsti,
tmsto2 => omac_tmsto2,
tmsti2 => imac_tmsti2,
rmsto => omac_rmsto,
rmsti => imac_rmsti
);
etho.tx_clk <= '0';
etho.gbit <= '0';
--! AXI Master interface providing DMA access
axi0 : eth_axi_mst generic map (
xindex => xmstindex
) port map (
rst,
clk,
msti,
msto,
omac_tmsto,
imac_tmsti,
omac_rmsto,
imac_rmsti
);
edclmst_on : if edclsepahbg = 1 generate
axi1 : eth_axi_mst generic map (
xindex => xmstindex2
) port map (
rst,
clk,
msti,
msto2,
omac_tmsto2,
imac_tmsti2,
eth_rx_in_none,
open
);
end generate;
edclmst_off : if edclsepahbg = 0 generate
msto2 <= nasti_master_out_none;
imac_tmsti2.grant <= '0';
imac_tmsti2.data <= (others => '0');
imac_tmsti2.ready <= '0';
imac_tmsti2.error <= '0';
imac_tmsti2.retry <= '0';
end generate;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
| bsd-2-clause | a0281fc2c6d5c140288b2472cab1e89a | 0.531673 | 3.768368 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/synth/design_1_mdm_1_0.vhd | 2 | 62,904 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2;
USE mdm_v3_2.MDM;
ENTITY design_1_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC
);
END design_1_mdm_1_0;
ARCHITECTURE design_1_mdm_1_0_arch OF design_1_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "MDM,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mdm_1_0_arch : ARCHITECTURE IS "design_1_mdm_1_0,MDM,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "design_1_mdm_1_0,MDM,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mdm,x_ipVersion=3.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_JTAG_CHAIN=2,C_USE_BSCAN=0,C_USE_CONFIG_RESET=0,C_INTERCONNECT=2,C_MB_DBG_PORTS=1,C_USE_UART=0,C_DBG_REG_ACCESS=0,C_DBG_MEM_ACCESS=0,C_USE_CROSS_TRIGGER=0,C_TRACE_OUTPUT=0,C_TRACE_DATA_WIDTH=32,C_TRACE_CLK_FREQ_HZ=200000000,C_TRACE_CLK_OUT_PHASE=90,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_FREQ_HZ=100000000,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_THREAD_ID_WIDTH=1,C_DATA_SIZE=32,C_M_AXIS_DATA_WIDTH=32,C_M_AXIS_ID_WIDTH=7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END design_1_mdm_1_0_arch;
| gpl-3.0 | 7393621b4ddab0f43564162a7e6d4394 | 0.588405 | 2.823593 | false | false | false | false |
IAIK/ascon_hardware | asconv1/ascon_128_xlow_area/ascon_sbox5.vhdl | 1 | 2,864 | -------------------------------------------------------------------------------
-- Title : Ascon SBox
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_sbox5.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2014-05-20
-- Last update: 2014-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-20 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon_sbox5 is
port (
SboxINxDI : in std_logic_vector(4 downto 0);
SboxOUTxDO : out std_logic_vector(4 downto 0));
end entity ascon_sbox5;
architecture structural of ascon_sbox5 is
begin -- architecture structural
-- purpose: implementation of the Ascno sbox
-- type : combinational
sbox: process (SBoxINxDI) is
-- Temp variables;
variable SBoxT0xV, SBoxT1xV, SBoxT2xV : std_logic_vector(4 downto 0);
begin -- process sbox
SBoxT0xV(0) := SBoxINxDI(0) xor SBoxINxDI(4);
SBoxT0xV(1) := SBoxINxDI(1);
SBoxT0xV(2) := SBoxINxDI(2) xor SBoxINxDI(1);
SBoxT0xV(3) := SBoxINxDI(3);
SBoxT0xV(4) := SBoxINxDI(4) xor SBoxINxDI(3);
SBoxT1xV(0) := SBoxT0xV(0) xor (not SBoxT0xV(1) and SBoxT0xV(2));
SBoxT1xV(1) := SBoxT0xV(1) xor (not SBoxT0xV(2) and SBoxT0xV(3));
SBoxT1xV(2) := SBoxT0xV(2) xor (not SBoxT0xV(3) and SBoxT0xV(4));
SBoxT1xV(3) := SBoxT0xV(3) xor (not SBoxT0xV(4) and SBoxT0xV(0));
SBoxT1xV(4) := SBoxT0xV(4) xor (not SBoxT0xV(0) and SBoxT0xV(1));
SboxOUTxDO(0) <= SBoxT1xV(0) xor SBoxT1xV(4);
SboxOUTxDO(1) <= SBoxT1xV(1) xor SBoxT1xV(0);
SboxOUTxDO(2) <= not SBoxT1xV(2);
SboxOUTxDO(3) <= SBoxT1xV(3) xor SBoxT1xV(2);
SboxOUTxDO(4) <= SBoxT1xV(4);
end process sbox;
end architecture structural;
| apache-2.0 | 82197758995af17b169bd8ddb8f4a794 | 0.556215 | 3.778364 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/crcgenrx.vhd | 4 | 14,428 | -------------------------------------------------------------------------------
-- crcgenrx - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : crcgenrx.vhd
-- Version : v4.00.a
-- Description : This module does an 4-bit parallel CRC generation.
-- The polynomial is that specified for IEEE 802.3 (ethernet)
-- LANs and other standards.
--
-- I. Functionality:
-- 1. The module does an 4-bit parallel CRC generation.
-- 2. The module provides a synchronous 4-bit per clock load and
-- unload function.
-- 3. The polynomial is that specified for 802.3 LANs and other
-- standards.
-- The polynomial computed is:
-- G(x)=X**32+X**26+X**23+X**22+X**16+X**12+X**11+X**10+X**8
-- +X**7+X**5+X**4+X** >2+X+1
--
-- II. Module I/O
-- Inputs: Clk, CLKEN, Rst, LOAD, COMPUTE, DATA_IN[3:0]
-- outputs: CRC_OK, DATA_OUT[3:0], CRC[31:0]
--
-- III.Truth Table:
--
-- CLKEN Rst COMPUTE LOAD | DATA_OUT
-- ------------------------------------------
-- 0 X X X | No change
-- 1 0 0 0 | No change
-- 1 1 X X | 0xFFFF (all ones)
-- 1 0 X 1 | load and shift 1 nibble of crc
-- 1 0 1 0 | Compute CRC
--
-- 0 0 1 1 | unload 4 byte crc
-- NOT IMPLEMENTED)
--
-- Loading and unloading of the 32-bit CRC register is done one
-- nibble at a time by asserting LOAD and CLKEN. The Data on
-- data_in is shifted into the the LSB of the CRC register. The
-- MSB of the CRC register is available on data_out.
--
-- Signals ending in _n are active low.
--
-- Copyright 1997 VAutomation Inc. Nashua NH USA (603) 882-2282.
-- Modification for 4 Bit done by Ronald Hecht @ Xilinx Inc.
-- This software is provided AS-IS and free of charge with the restriction that
-- this copyright notice remain in all copies of the Source Code at all times.
-- Visit HTTP://www.vautomation.com for more information on our cores.
-------------------------------------------------------------------------------
-- We remove the 32 bits register which restore the crc value in the old code.
-- For receive part we only need to know the crc is ok or not, so remove the
-- register for restoring crc value will save some resources.
--
-- THE INTERFACE REQUIREMENTS OF THIS MODULE
--
-- Rst reset everything to initial value. We must give this reset
-- before we use crc module, otherwise the result will incorrect.
-- Clk For use with mactx module, it will be 2.5 MHZ.
-- Data Input Data from other module in nibbles.
-- DataEn Enable crcgenrx. Make sure your enable and first Data can be
-- captured at the beginning of Data stream.
-- CrcOk At the end of Data stream, this will go high if the crc is
-- correct.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- xemac.vhd
-- \
-- \-- axi_ipif_interface.vhd
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ ethernetlite_v3_0_dmem_v2.edn
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- ethernetlite_v3_0_dmem_v2.edn
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Data -- Data in
-- DataEn -- Data enable
-- CrcOk -- CRC valid
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcgenrx is
port
(
Clk : in std_logic;
Rst : in std_logic;
Data : in std_logic_vector(3 downto 0);
DataEn : in std_logic;
CrcOk : out std_logic
);
end crcgenrx;
architecture arch1 of crcgenrx is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of arch1 : architecture is "yes";
constant CRC_REMAINDER : std_logic_vector(31 downto 0) :=
"11000111000001001101110101111011";
-- 0xC704DD7B
signal crc_local : std_logic_vector(31 downto 0); -- local version
signal data_transpose : std_logic_vector(3 downto 0);
function parallel_crc (crc_in : std_logic_vector(31 downto 0);
data_in : std_logic_vector(3 downto 0)
) return std_logic_vector is
variable c, crc_out : std_logic_vector(31 downto 0);
variable x : std_logic_vector (31 downto 28);
variable d : std_logic_vector (3 downto 0);
begin
-- Because the equations are long I am keeping the name of the incoming
-- CRC and the XOR vector short.
c := crc_in;
d := data_in;
-- the first thing that a parallel CRC needs to do is to develop the
-- vector formed by XORing the input vector by the current CRC. This
-- vector is then used during the CRC calculation.
x := (c(31) xor d(3)) & (c(30) xor d(2)) &
(c(29) xor d(1)) & (c(28) xor d(0));
-- The parellel CRC is a function of the X vector and the current CRC.
crc_out :=
(c(27) ) &
(c(26) ) &
(c(25) xor x(31) ) &
(c(24) xor x(30) ) &
(c(23) xor x(29) ) &
(c(22) xor x(31) xor x(28) ) &
(c(21) xor x(31) xor x(30) ) &
(c(20) xor x(30) xor x(29) ) &
(c(19) xor x(29) xor x(28) ) &
(c(18) xor x(28) ) &
(c(17) ) &
(c(16) ) &
(c(15) xor x(31) ) &
(c(14) xor x(30) ) &
(c(13) xor x(29) ) &
(c(12) xor x(28) ) &
(c(11) xor x(31) ) &
(c(10) xor x(31) xor x(30) ) &
(c(9 ) xor x(31) xor x(30) xor x(29) ) &
(c(8 ) xor x(30) xor x(29) xor x(28) ) &
(c(7 ) xor x(31) xor x(29) xor x(28) ) &
(c(6 ) xor x(31) xor x(30) xor x(28) ) &
(c(5 ) xor x(30) xor x(29) ) &
(c(4 ) xor x(31) xor x(29) xor x(28) ) &
(c(3 ) xor x(31) xor x(30) xor x(28) ) &
(c(2 ) xor x(30) xor x(29) ) &
(c(1 ) xor x(31) xor x(29) xor x(28) ) &
(c(0 ) xor x(31) xor x(30) xor x(28) ) &
( x(31) xor x(30) xor x(29) ) &
( x(30) xor x(29) xor x(28) ) &
( x(29) xor x(28) ) &
( x(28) );
return(crc_out);
end parallel_crc;
begin ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Xilinx modification, use asynchronous clear
-------------------------------------------------------------------------------
data_transpose <= Data(0) & Data(1) & Data(2) & Data(3);
-- Reverse the bit order
-- Create the 32 Flip flops (with clock enable flops)
CRC_REG : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
crc_local <= (others=>'1');
elsif DataEn = '1' then
crc_local <= parallel_crc(crc_local, data_transpose);
end if;
end if;
end process CRC_REG;
-------------------------------------------------------------------------------
-- Xilinx modification, remove reset from mux
-------------------------------------------------------------------------------
CrcOk <= '1' when crc_local = CRC_REMAINDER else '0';
-- This is a 32-bit wide AND
-- function, so proper
-- attention should be paid
-- when synthesizing to
-- achieve good results. If
-- there are cycles available
-- pipeling this gate would be
-- appropriate.
end arch1;
| gpl-3.0 | 317abd4c2c5c8cb56dc0bd8b9aba8fd3 | 0.418076 | 4.471026 | false | false | false | false |
hoangt/PoC | src/arith/arith_addw.vhdl | 2 | 11,935 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
use PoC.arith.all;
entity arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of arith_addw is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => DESC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
impure function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block + Carry Computation Core
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
begin
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
signal x, y : unsigned(K+M-2 downto 0);
signal z : unsigned(K+M-1 downto 0);
begin
x <= unsigned(g & a(M-1 downto 0));
genExcl: if not P_INCLUSIVE generate
y <= unsigned((g or p) & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor p;
end generate genExcl;
genIncl: if P_INCLUSIVE generate
y <= unsigned(p & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor (p xor g);
end generate genIncl;
z <= ('0' & x) + y + (0 to 0 => cin);
-- output of rightmost block
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- carry output
cout <= z(z'left);
end generate genCCC;
-- LUT-based Carry Computations
genLUT: if SKIPPING /= CCC generate
signal z : unsigned(M downto 0);
begin
-- rightmost block
z <= unsigned('0' & a(M-1 downto 0)) + unsigned(b(M-1 downto 0)) + (0 to 0 => cin);
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
signal t : std_logic_vector(K downto 1);
begin
-- carry forwarding
t(1) <= z(M);
t(K downto 2) <= g or (p and c);
c <= t(K-1 downto 1);
cout <= t(K);
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
c <= gg(LEVELS)(K-2 downto 0);
cout <= gg(LEVELS)(K-1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
c <= gg(gg'high)(K-2 downto 0);
cout <= gg(gg'high)(K-1);
end generate genPPN_BK;
end generate genLUT;
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
-- Internal Block Interface
signal aa : unsigned(HI downto LO);
signal bb : unsigned(HI downto LO);
signal ss : unsigned(HI downto LO);
begin
-- Connect common block interface
aa <= unsigned(a(HI downto LO));
bb <= unsigned(b(HI downto LO));
s(HI downto LO) <= std_logic_vector(ss);
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
signal s1 : unsigned(HI+1 downto LO); -- Block Sum (cin=1)
begin
s0 <= ('0' & aa) + bb;
s1 <= ('0' & aa) + bb + 1;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= s1(HI+1) xor s0(HI+1);
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= s1(HI+1);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s1(HI downto LO);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genCAI;
-- Propagate-Add-Increment
genPAI: if ARCH = PAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else g(i);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genPAI;
-- Compare-Compare-Add
genCCA: if ARCH = CCA generate
g(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa > not bb else '0';
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= aa + bb + (0 to 0 => c(i));
end generate genCCA;
end generate genBlocks;
end architecture;
| apache-2.0 | 51af56f12504efe750240933136bec79 | 0.566988 | 3.253817 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sources_1/new/i2c_master.vhd | 2 | 14,305 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 Scott Larson
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : OUT STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
SIGNAL INTERNALERROR : STD_LOGIC;
BEGIN
ack_error <= INTERNALERROR;
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
INTERNALERROR <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
INTERNALERROR <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR INTERNALERROR = '1') THEN --no-acknowledge or previous no-acknowledge
INTERNALERROR <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR INTERNALERROR = '1') THEN --no-acknowledge or previous no-acknowledge
INTERNALERROR <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
| gpl-3.0 | cb6c4e3a73ee34c5015ba66e6be498c2 | 0.492066 | 4.68709 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/misc/reset_glb.vhd | 2 | 1,703 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief System reset former.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! @brief NoC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[in] inPllLock PLL status.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
entity reset_global is
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
inPllLock : in std_ulogic;
outReset : out std_ulogic
);
end;
architecture arch_reset_global of reset_global is
type reg_type is record
delay_cnt : std_logic_vector(7 downto 0);
end record;
signal r : reg_type;
begin
proc_rst : process (inSysClk, inSysReset, inPllLock, r)
variable wb_delay_cnt : std_logic_vector(7 downto 0);
variable sys_reset : std_logic;
begin
sys_reset := inSysReset or not inPllLock;
wb_delay_cnt := r.delay_cnt;
if r.delay_cnt(7) = '0' then
wb_delay_cnt := r.delay_cnt + 1;
end if;
if sys_reset = '1' then
r.delay_cnt <= (others => '0');
elsif rising_edge(inSysClk) then
r.delay_cnt <= wb_delay_cnt;
end if;
end process;
outReset <= not r.delay_cnt(7);
end;
| bsd-2-clause | 916a808ae56af6c1df05baa34bc0e2ef | 0.589548 | 3.792873 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/arbiter.vhd | 4 | 9,525 | -------------------------------------------------------------------------------
-- arbiter.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: arbiter.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- arbiter.vhd
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2014/05/08 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Arbiter is
generic (
Size : natural := 32;
Size_Log2 : natural := 5);
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Requests : in std_logic_vector(Size-1 downto 0);
Granted : out std_logic_vector(Size-1 downto 0);
Valid_Sel : out std_logic;
Selected : out std_logic_vector(Size_Log2-1 downto 0));
end entity Arbiter;
architecture IMP of Arbiter is
component select_bit
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end component select_bit;
component carry_or_vec
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end component carry_or_vec;
component carry_and
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end component carry_and;
component carry_or
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end component carry_or;
subtype index_type is std_logic_vector(Size_Log2-1 downto 0);
type int_array_type is array (natural range 2*Size-1 downto 0) of index_type;
function init_index_table return int_array_type is
variable tmp : int_array_type;
begin -- function init_index_table
for I in 0 to Size-1 loop
tmp(I) := std_logic_vector(to_unsigned(I, Size_Log2));
tmp(Size+I) := std_logic_vector(to_unsigned(I, Size_Log2));
end loop; -- I
return tmp;
end function init_index_table;
constant index_table : int_array_type := init_index_table;
signal long_req : std_logic_vector(2*Size-1 downto 0);
signal mask : std_logic_vector(2*Size-1 downto 0);
signal grant_sel : std_logic_vector(Size_Log2-1 downto 0);
signal new_granted : std_logic;
signal reset_loop : std_logic;
signal mask_reset : std_logic;
signal valid_grant : std_logic;
begin -- architecture IMP
long_req <= Requests & Requests;
Request_Or : carry_or_vec
generic map (
Size => Size)
port map (
Carry_In => Enable,
In_Vec => Requests, -- in
Carry_Out => new_granted); -- out
Valid_Sel <= new_granted;
-----------------------------------------------------------------------------
-- Generate Carry-Chain structure
-----------------------------------------------------------------------------
Chain: for I in Size_Log2-1 downto 0 generate
signal carry : std_logic_vector(Size downto 0); -- Assumes 2 bit/muxcy
begin -- generate Bits
carry(Size) <= '0';
Bits: for J in Size-1 downto 0 generate
constant sel1 : std_logic := index_table(2*J+1)(I);
constant sel0 : std_logic := index_table(2*J)(I);
attribute keep_hierarchy : string;
attribute keep_hierarchy of Select_bits : label is "yes";
begin -- generate Bits
Select_bits : select_bit
generic map (
sel_value => sel1 & sel0)
port map (
Mask => mask(2*J+1 downto 2*J), -- in
Request => long_req(2*J+1 downto 2*J), -- in
Carry_In => carry(J+1), -- in
Carry_Out => carry(J)); -- out
end generate Bits;
grant_sel(I) <= carry(0);
end generate Chain;
Selected <= grant_sel;
-----------------------------------------------------------------------------
-- Handling Mask value
-----------------------------------------------------------------------------
-- if (Reset = '1') or ((new_granted and mask(1)) = '1') then
Reset_loop_and : carry_and
port map (
Carry_IN => new_granted, -- in
A => mask(1), -- in
Carry_OUT => reset_loop); -- out
Mask_Reset_carry : carry_or
port map (
Carry_IN => reset_loop, -- in
A => Reset, -- in
Carry_OUT => mask_reset); -- out
Mask_Handler : process (Clk) is
begin -- process Mask_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (mask_reset = '1') then -- synchronous reset (active high)
mask(2*Size-1 downto Size) <= (others => '1');
mask(Size-1 downto 0) <= (others => '0');
else
if (new_granted = '1') then
mask(2*Size-1 downto 1) <= mask(1) & mask(2*Size-1 downto 2);
end if;
end if;
end if;
end process Mask_Handler;
-----------------------------------------------------------------------------
-- Generate grant signal
-----------------------------------------------------------------------------
Grant_Signals: for K in Size-1 downto 1 generate
signal tmp : std_logic;
attribute keep : string;
attribute keep of tmp : signal is "true";
begin -- generate Grant_Signals
tmp <= '1' when (K = to_integer(unsigned(grant_sel))) else '0';
granted(K) <= tmp;
end generate Grant_Signals;
Granted(0) <= Requests(0) when to_integer(unsigned(grant_sel)) = 0 else '0';
end architecture IMP;
| gpl-3.0 | 948474e936a6a98c02d1b0813cc724d3 | 0.529869 | 4.259839 | false | false | false | false |
lowRISC/greth-library | greth_library/rocketlib/misc/nasti_pnp.vhd | 2 | 6,844 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Entity nasti_pnp implementation for the plug'n'play support.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief Hardware Configuration storage with the AMBA AXI4 interface.
entity nasti_pnp is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in nasti_master_cfg_vector;
slvcfg : in nasti_slave_cfg_vector;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end;
architecture arch_nasti_pnp of nasti_pnp is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_PNP,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type slave_config_map is array (0 to 4*CFG_NASTI_SLAVES_TOTAL-1)
of std_logic_vector(31 downto 0);
type bank_type is record
fw_id : std_logic_vector(31 downto 0);
idt : std_logic_vector(63 downto 0); --! debug counter
malloc_addr : std_logic_vector(63 downto 0); --! dynamic allocation addr
malloc_size : std_logic_vector(63 downto 0); --! dynamic allocation size
fwdbg1 : std_logic_vector(63 downto 0); --! FW marker for the debug porposes
adc_detect : std_logic_vector(7 downto 0);
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
constant RESET_VALUE : registers := (
NASTI_SLAVE_BANK_RESET,
((others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'))
);
signal r, rin : registers;
--! @brief Detector of the ADC clock.
--! @details If this register won't equal to 0xFF, then we suppose RF front-end
--! not connected and FW should print message to enable 'i_int_clkrf'
--! jumper to make possible generation of the 1 msec interrupts.
signal r_adc_detect : std_logic_vector(7 downto 0);
begin
comblogic : process(i, slvcfg, r, r_adc_detect, nrst)
variable v : registers;
variable slvmap : slave_config_map;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable rtmp : std_logic_vector(31 downto 0);
variable wtmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
begin
v := r;
v.bank0.adc_detect := r_adc_detect;
for k in 0 to CFG_NASTI_SLAVES_TOTAL-1 loop
slvmap(4*k) := slvcfg(k).xmask & X"000";
slvmap(4*k+1) := slvcfg(k).xaddr & X"000";
slvmap(4*k+2) := slvcfg(k).vid & slvcfg(k).did;
slvmap(4*k+3) := X"000000" & PNP_CFG_SLAVE_DESCR_BYTES;
end loop;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
rtmp := (others => '0');
if raddr_reg(n) = 0 then
rtmp := X"20160328";
elsif raddr_reg(n) = 1 then
rtmp := r.bank0.fw_id;
elsif raddr_reg(n) = 2 then
rtmp := r.bank0.adc_detect
& conv_std_logic_vector(CFG_NASTI_MASTER_TOTAL,8)
& conv_std_logic_vector(CFG_NASTI_SLAVES_TOTAL,8)
& conv_std_logic_vector(tech,8);
elsif raddr_reg(n) = 3 then
-- reserved
elsif raddr_reg(n) = 4 then
rtmp := r.bank0.idt(31 downto 0);
elsif raddr_reg(n) = 5 then
rtmp := r.bank0.idt(63 downto 32);
elsif raddr_reg(n) = 6 then
rtmp := r.bank0.malloc_addr(31 downto 0);
elsif raddr_reg(n) = 7 then
rtmp := r.bank0.malloc_addr(63 downto 32);
elsif raddr_reg(n) = 8 then
rtmp := r.bank0.malloc_size(31 downto 0);
elsif raddr_reg(n) = 9 then
rtmp := r.bank0.malloc_size(63 downto 32);
elsif raddr_reg(n) = 10 then
rtmp := r.bank0.fwdbg1(31 downto 0);
elsif raddr_reg(n) = 11 then
rtmp := r.bank0.fwdbg1(63 downto 32);
elsif raddr_reg(n) >= 16 and raddr_reg(n) < 16+4*CFG_NASTI_SLAVES_TOTAL then
rtmp := slvmap(raddr_reg(n) - 16);
end if;
rdata(32*(n+1)-1 downto 32*n) := rtmp;
end loop;
if i.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
wtmp := i.w_data(32*(n+1)-1 downto 32*n);
wstrb := i.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 1 => v.bank0.fw_id := wtmp;
when 4 => v.bank0.idt(31 downto 0) := wtmp;
when 5 => v.bank0.idt(63 downto 32) := wtmp;
when 6 => v.bank0.malloc_addr(31 downto 0) := wtmp;
when 7 => v.bank0.malloc_addr(63 downto 32) := wtmp;
when 8 => v.bank0.malloc_size(31 downto 0) := wtmp;
when 9 => v.bank0.malloc_size(63 downto 32) := wtmp;
when 10 => v.bank0.fwdbg1(31 downto 0) := wtmp;
when 11 => v.bank0.fwdbg1(63 downto 32) := wtmp;
when others =>
end case;
end if;
end loop;
end if;
o <= functionAxi4Output(r.bank_axi, rdata);
if nrst = '0' then
v := RESET_VALUE;
end if;
rin <= v;
end process;
cfg <= xconfig;
-- registers:
regs : process(sys_clk)
begin
if rising_edge(sys_clk) then
r <= rin;
end if;
end process;
-- ADC clock detector:
regsadc : process(adc_clk, nrst)
begin
if nrst = '0' then
r_adc_detect <= (others => '0');
elsif rising_edge(adc_clk) then
r_adc_detect <= r_adc_detect(6 downto 0) & nrst;
end if;
end process;
end;
| bsd-2-clause | 58ff98d77327eb0ad287e9f24b81ccc3 | 0.575102 | 3.351616 | false | false | false | false |
lincanbin/VHDL-Frequency-Divider | FrequencyDivider.vhd | 1 | 919 | --ÀûÓÃbufferʵÏֵķÖƵÆ÷£¬´úÂëÁ¿ÉÙÓÚÓÃCNT10¸ÄÔì
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY FrequencyDivider is
PORT(
data: in std_logic_vector(15 downto 0);--16λԤÖÃÊý£¬load·Ç¸ßµçƽÖÃÊý
en,clk:in std_logic;--ʹÄÜ£¬Ê±ÖÓ
q: buffer std_logic_vector(15 downto 0);--16λ¼ÆÊý
cout:buffer std_logic--Òç³ö룬¸ßµçƽÒç³ö£¬ÓÃbuffer±£´æ״̬ȡ·´£¬ÇáÒ×ʵÏÖ·ÖƵ
);
END FrequencyDivider;
architecture behavior OF FrequencyDivider IS
BEGIN
process(clk,en,cout) begin
if(rising_edge(clk)) then --ʱÖÓÉÏÉýÑØʱ¿ªÊ¼¹¤×÷
if(en='1')then --Enable£¬¿ª¹Ø
if(q=data-1)then --qΪdata£¬Òç³öʵÏÖ·ÖƵ£¬ÒòΪ´Ó0¿ªÊ¼¼ÓËùÒÔÒª¼õ1
q<="0000000000000000";
if(cout='1') then
cout<='0';
else
cout<='1';
end if;
else
q<=q+1;
end if;
else
q<=q;
end if;
end if;
end process;
END behavior;
--ÁÖ²Ó±ó
--https://github.com/lincanbin
--20150504 | apache-2.0 | a30aba2fc1821d0e5ca77956073f47e5 | 0.659412 | 2.137209 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_tb/std_logic_1164_additions.vhd | 2 | 68,175 | ------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-05-31 14:53:37-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.10 2007-05-31 14:53:37-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREADnew [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREADnew [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREADnew [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREADnew [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREADnew;
procedure HREADnew (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREADnew;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREADnew (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREADnew;
procedure HREADnew (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREADnew (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREADnew;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
| apache-2.0 | 4558d5221c7bbe12b667fdf7de93950f | 0.510363 | 3.855616 | false | false | false | false |
hoangt/PoC | src/arith/arith_convert_bin2bcd.vhdl | 2 | 5,053 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: Converter binary numbers to BCD encoded numbers.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library PoC;
use PoC.utils.all;
use PoC.components.all;
entity arith_convert_bin2bcd is
generic (
BITS : POSITIVE := 8;
DIGITS : POSITIVE := 3;
RADIX : POSITIVE := 2
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Start : in STD_LOGIC;
Busy : out STD_LOGIC;
Binary : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
IsSigned : in STD_LOGIC := '0';
BCDDigits : out T_BCD_VECTOR(DIGITS - 1 downto 0);
Sign : out STD_LOGIC
);
end;
architecture rtl of arith_convert_bin2bcd is
constant RADIX_BITS : POSITIVE := log2ceil(RADIX);
constant BINARY_SHIFTS : POSITIVE := div_ceil(BITS, RADIX_BITS);
constant BINARY_BITS : POSITIVE := BINARY_SHIFTS * RADIX_BITS;
subtype T_CARRY is UNSIGNED(RADIX_BITS - 1 downto 0);
type T_CARRY_VECTOR is array(NATURAL range <>) of T_CARRY;
signal Digit_Shift_rst : STD_LOGIC;
signal Digit_Shift_en : STD_LOGIC;
signal Digit_Shift_in : T_CARRY_VECTOR(DIGITS downto 0);
signal Binary_en : STD_LOGIC;
signal Binary_rl : STD_LOGIC;
signal Binary_d : STD_LOGIC_VECTOR(BINARY_BITS - 1 downto 0) := (others => '0');
signal Sign_d : STD_LOGIC := '0';
signal DelayShifter : STD_LOGIC_VECTOR(BINARY_SHIFTS downto 0) := '1' & (BINARY_SHIFTS - 1 downto 0 => '0');
function nextBCD(Value : UNSIGNED(4 downto 0)) return UNSIGNED is
constant Temp : UNSIGNED(4 downto 0) := Value - 10;
begin
if (Value > 9) then
return '1' & Temp(3 downto 0);
else
return Value;
end if;
end function;
begin
Busy <= not DelayShifter(DelayShifter'high);
Binary_en <= Start;
Binary_rl <= Start nor DelayShifter(DelayShifter'high);
Digit_Shift_rst <= Start;
Digit_Shift_en <= Start nor DelayShifter(DelayShifter'high);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Binary_d <= (others => '0');
elsif (Binary_en = '1') then
Binary_d(Binary_d'high downto Binary'high) <= (others => '0');
if ((IsSigned and Binary(Binary'high)) = '1') then
Binary_d(Binary'high downto 0) <= inc(not(Binary));
Sign_d <= '1';
else
Binary_d(Binary'high downto 0) <= Binary;
Sign_d <= '0';
end if;
DelayShifter <= (BINARY_SHIFTS downto 1 => '0') & '1';
elsif (Binary_rl = '1') then
DelayShifter <= DelayShifter(DelayShifter'high - 1 downto 0) & DelayShifter(DelayShifter'high);
Binary_d <= Binary_d(Binary_d'high - RADIX_BITS downto 0) & Binary_d(Binary_d'high downto Binary_d'high - RADIX_BITS + 1);
end if;
end if;
end process;
Sign <= Sign_d;
Digit_Shift_in(0) <= unsigned(Binary_d(Binary_d'high downto Binary_d'high - RADIX_BITS + 1));
-- generate DIGITS many systolic elements
genDigits : for i in 0 to DIGITS - 1 generate
signal Digit_nxt : UNSIGNED(3 + RADIX_BITS downto 0);
signal Digit_d : UNSIGNED(3 downto 0) := (others => '0');
begin
process(Digit_d, Digit_Shift_in)
variable Temp : UNSIGNED(4 downto 0);
begin
Temp := '0' & Digit_d;
for j in RADIX_BITS - 1 downto 0 loop
Temp := nextBCD(Temp(3 downto 0) & Digit_Shift_in(i)(j));
Digit_nxt(j + 4 downto j) <= Temp;
end loop;
end process;
Digit_Shift_in(i + 1) <= Digit_nxt(Digit_nxt'high downto Digit_nxt'high - RADIX_BITS + 1);
process(Clock)
begin
if rising_edge(Clock) then
if (Digit_Shift_rst = '1') then
Digit_d <= "0000";
elsif (Digit_Shift_en = '1') then
Digit_d <= Digit_nxt(Digit_d'range);
end if;
end if;
end process;
BCDDigits(i) <= t_bcd(std_logic_vector(Digit_d));
end generate;
end;
| apache-2.0 | 148cf1bd9ad4cec59c79dc9dcd696f82 | 0.598654 | 3.16604 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd | 1 | 14,171 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Tue Nov 17 20:19:34 2015
--Host : ALI-WORKSTATION running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_io : inout STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
reset : in STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
sys_clock : in STD_LOGIC
);
end component design_1;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal cellular_ram_dq_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal eth_mdio_mdc_mdio_i : STD_LOGIC;
signal eth_mdio_mdc_mdio_o : STD_LOGIC;
signal eth_mdio_mdc_mdio_t : STD_LOGIC;
begin
cellular_ram_dq_iobuf_0: component IOBUF
port map (
I => cellular_ram_dq_o_0(0),
IO => cellular_ram_dq_io(0),
O => cellular_ram_dq_i_0(0),
T => cellular_ram_dq_t_0(0)
);
cellular_ram_dq_iobuf_1: component IOBUF
port map (
I => cellular_ram_dq_o_1(1),
IO => cellular_ram_dq_io(1),
O => cellular_ram_dq_i_1(1),
T => cellular_ram_dq_t_1(1)
);
cellular_ram_dq_iobuf_10: component IOBUF
port map (
I => cellular_ram_dq_o_10(10),
IO => cellular_ram_dq_io(10),
O => cellular_ram_dq_i_10(10),
T => cellular_ram_dq_t_10(10)
);
cellular_ram_dq_iobuf_11: component IOBUF
port map (
I => cellular_ram_dq_o_11(11),
IO => cellular_ram_dq_io(11),
O => cellular_ram_dq_i_11(11),
T => cellular_ram_dq_t_11(11)
);
cellular_ram_dq_iobuf_12: component IOBUF
port map (
I => cellular_ram_dq_o_12(12),
IO => cellular_ram_dq_io(12),
O => cellular_ram_dq_i_12(12),
T => cellular_ram_dq_t_12(12)
);
cellular_ram_dq_iobuf_13: component IOBUF
port map (
I => cellular_ram_dq_o_13(13),
IO => cellular_ram_dq_io(13),
O => cellular_ram_dq_i_13(13),
T => cellular_ram_dq_t_13(13)
);
cellular_ram_dq_iobuf_14: component IOBUF
port map (
I => cellular_ram_dq_o_14(14),
IO => cellular_ram_dq_io(14),
O => cellular_ram_dq_i_14(14),
T => cellular_ram_dq_t_14(14)
);
cellular_ram_dq_iobuf_15: component IOBUF
port map (
I => cellular_ram_dq_o_15(15),
IO => cellular_ram_dq_io(15),
O => cellular_ram_dq_i_15(15),
T => cellular_ram_dq_t_15(15)
);
cellular_ram_dq_iobuf_2: component IOBUF
port map (
I => cellular_ram_dq_o_2(2),
IO => cellular_ram_dq_io(2),
O => cellular_ram_dq_i_2(2),
T => cellular_ram_dq_t_2(2)
);
cellular_ram_dq_iobuf_3: component IOBUF
port map (
I => cellular_ram_dq_o_3(3),
IO => cellular_ram_dq_io(3),
O => cellular_ram_dq_i_3(3),
T => cellular_ram_dq_t_3(3)
);
cellular_ram_dq_iobuf_4: component IOBUF
port map (
I => cellular_ram_dq_o_4(4),
IO => cellular_ram_dq_io(4),
O => cellular_ram_dq_i_4(4),
T => cellular_ram_dq_t_4(4)
);
cellular_ram_dq_iobuf_5: component IOBUF
port map (
I => cellular_ram_dq_o_5(5),
IO => cellular_ram_dq_io(5),
O => cellular_ram_dq_i_5(5),
T => cellular_ram_dq_t_5(5)
);
cellular_ram_dq_iobuf_6: component IOBUF
port map (
I => cellular_ram_dq_o_6(6),
IO => cellular_ram_dq_io(6),
O => cellular_ram_dq_i_6(6),
T => cellular_ram_dq_t_6(6)
);
cellular_ram_dq_iobuf_7: component IOBUF
port map (
I => cellular_ram_dq_o_7(7),
IO => cellular_ram_dq_io(7),
O => cellular_ram_dq_i_7(7),
T => cellular_ram_dq_t_7(7)
);
cellular_ram_dq_iobuf_8: component IOBUF
port map (
I => cellular_ram_dq_o_8(8),
IO => cellular_ram_dq_io(8),
O => cellular_ram_dq_i_8(8),
T => cellular_ram_dq_t_8(8)
);
cellular_ram_dq_iobuf_9: component IOBUF
port map (
I => cellular_ram_dq_o_9(9),
IO => cellular_ram_dq_io(9),
O => cellular_ram_dq_i_9(9),
T => cellular_ram_dq_t_9(9)
);
design_1_i: component design_1
port map (
cellular_ram_addr(22 downto 0) => cellular_ram_addr(22 downto 0),
cellular_ram_adv_ldn => cellular_ram_adv_ldn,
cellular_ram_ben(1 downto 0) => cellular_ram_ben(1 downto 0),
cellular_ram_ce_n => cellular_ram_ce_n,
cellular_ram_cre => cellular_ram_cre,
cellular_ram_dq_i(15) => cellular_ram_dq_i_15(15),
cellular_ram_dq_i(14) => cellular_ram_dq_i_14(14),
cellular_ram_dq_i(13) => cellular_ram_dq_i_13(13),
cellular_ram_dq_i(12) => cellular_ram_dq_i_12(12),
cellular_ram_dq_i(11) => cellular_ram_dq_i_11(11),
cellular_ram_dq_i(10) => cellular_ram_dq_i_10(10),
cellular_ram_dq_i(9) => cellular_ram_dq_i_9(9),
cellular_ram_dq_i(8) => cellular_ram_dq_i_8(8),
cellular_ram_dq_i(7) => cellular_ram_dq_i_7(7),
cellular_ram_dq_i(6) => cellular_ram_dq_i_6(6),
cellular_ram_dq_i(5) => cellular_ram_dq_i_5(5),
cellular_ram_dq_i(4) => cellular_ram_dq_i_4(4),
cellular_ram_dq_i(3) => cellular_ram_dq_i_3(3),
cellular_ram_dq_i(2) => cellular_ram_dq_i_2(2),
cellular_ram_dq_i(1) => cellular_ram_dq_i_1(1),
cellular_ram_dq_i(0) => cellular_ram_dq_i_0(0),
cellular_ram_dq_o(15) => cellular_ram_dq_o_15(15),
cellular_ram_dq_o(14) => cellular_ram_dq_o_14(14),
cellular_ram_dq_o(13) => cellular_ram_dq_o_13(13),
cellular_ram_dq_o(12) => cellular_ram_dq_o_12(12),
cellular_ram_dq_o(11) => cellular_ram_dq_o_11(11),
cellular_ram_dq_o(10) => cellular_ram_dq_o_10(10),
cellular_ram_dq_o(9) => cellular_ram_dq_o_9(9),
cellular_ram_dq_o(8) => cellular_ram_dq_o_8(8),
cellular_ram_dq_o(7) => cellular_ram_dq_o_7(7),
cellular_ram_dq_o(6) => cellular_ram_dq_o_6(6),
cellular_ram_dq_o(5) => cellular_ram_dq_o_5(5),
cellular_ram_dq_o(4) => cellular_ram_dq_o_4(4),
cellular_ram_dq_o(3) => cellular_ram_dq_o_3(3),
cellular_ram_dq_o(2) => cellular_ram_dq_o_2(2),
cellular_ram_dq_o(1) => cellular_ram_dq_o_1(1),
cellular_ram_dq_o(0) => cellular_ram_dq_o_0(0),
cellular_ram_dq_t(15) => cellular_ram_dq_t_15(15),
cellular_ram_dq_t(14) => cellular_ram_dq_t_14(14),
cellular_ram_dq_t(13) => cellular_ram_dq_t_13(13),
cellular_ram_dq_t(12) => cellular_ram_dq_t_12(12),
cellular_ram_dq_t(11) => cellular_ram_dq_t_11(11),
cellular_ram_dq_t(10) => cellular_ram_dq_t_10(10),
cellular_ram_dq_t(9) => cellular_ram_dq_t_9(9),
cellular_ram_dq_t(8) => cellular_ram_dq_t_8(8),
cellular_ram_dq_t(7) => cellular_ram_dq_t_7(7),
cellular_ram_dq_t(6) => cellular_ram_dq_t_6(6),
cellular_ram_dq_t(5) => cellular_ram_dq_t_5(5),
cellular_ram_dq_t(4) => cellular_ram_dq_t_4(4),
cellular_ram_dq_t(3) => cellular_ram_dq_t_3(3),
cellular_ram_dq_t(2) => cellular_ram_dq_t_2(2),
cellular_ram_dq_t(1) => cellular_ram_dq_t_1(1),
cellular_ram_dq_t(0) => cellular_ram_dq_t_0(0),
cellular_ram_oen => cellular_ram_oen,
cellular_ram_wait => cellular_ram_wait,
cellular_ram_wen => cellular_ram_wen,
eth_mdio_mdc_mdc => eth_mdio_mdc_mdc,
eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i,
eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o,
eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t,
eth_ref_clk => eth_ref_clk,
eth_rmii_crs_dv => eth_rmii_crs_dv,
eth_rmii_rx_er => eth_rmii_rx_er,
eth_rmii_rxd(1 downto 0) => eth_rmii_rxd(1 downto 0),
eth_rmii_tx_en => eth_rmii_tx_en,
eth_rmii_txd(1 downto 0) => eth_rmii_txd(1 downto 0),
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
eth_mdio_mdc_mdio_iobuf: component IOBUF
port map (
I => eth_mdio_mdc_mdio_o,
IO => eth_mdio_mdc_mdio_io,
O => eth_mdio_mdc_mdio_i,
T => eth_mdio_mdc_mdio_t
);
end STRUCTURE;
| gpl-3.0 | b2a5501d722782ca2434a492d6abdae1 | 0.602498 | 2.733076 | false | false | false | false |
lowRISC/greth-library | greth_library/techmap/pll/SysPLL_v6.vhd | 2 | 8,133 | -- file: SysPLL_v6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____60.000______0.000______50.0______252.453____300.046
-- CLK_OUT2____15.000______0.000______50.0______315.611____300.046
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_v6 is
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_v6;
architecture xilinx of SysPLL_v6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_v6,clk_wiz_v3_6,{component_name=SysPLL_v6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN1_P,
IB => CLK_IN1_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 10,
CLKFBOUT_MULT_F => 51.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 17.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 68,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
CLK_OUT2 <= clkout1;
end xilinx;
| bsd-2-clause | 6c6b73a1e024dcb47ca00f9a1962021e | 0.579122 | 4.095166 | false | false | false | false |
MikhailKoslowski/Variax | Quartus/BaudGenerator.vhd | 1 | 1,265 | -----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY BaudGenerator IS
GENERIC ( baud : INTEGER := 9_600;
freq : INTEGER := 50_000_000);
PORT (clk: IN STD_LOGIC;
clk_out: OUT STD_LOGIC);
END ENTITY;
-----------------------------------------------------------
ARCHITECTURE structure OF BaudGenerator IS
SIGNAL x: STD_LOGIC :='0';
SIGNAL y: STD_LOGIC :='0';
CONSTANT M : INTEGER := freq/baud;
BEGIN
PROCESS (clk)
VARIABLE count1: INTEGER RANGE 0 TO M-1 := 0;
BEGIN
IF clk'EVENT AND clk='1' THEN
IF count1 < (M/2) THEN
x <= '1';
ELSE
x <= '0';
END IF;
count1 := count1 + 1;
IF count1 = M THEN
count1 := 0;
--x <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
VARIABLE count2: INTEGER RANGE 0 TO M-1 := 0;
BEGIN
IF clk'EVENT AND clk='0' AND M mod 2 = 1 THEN
IF count2 < (M/2) THEN
y <= '1';
ELSE
y <= '0';
END IF;
count2 := count2 + 1;
IF count2 = M THEN
count2 := 0;
--y <= '1';
END IF;
END IF;
END PROCESS;
clk_out <= x OR y;
END ARCHITECTURE structure; | mit | db1be06f593064a2a4827054c2fee391 | 0.504348 | 3.123457 | false | false | false | false |
IAIK/ascon_hardware | asconv1/ascon_super_fast.vhdl | 1 | 7,046 | -------------------------------------------------------------------------------
-- Title : A super fast implementation of Ascon
-- Project : Ascon
-------------------------------------------------------------------------------
-- File : ascon_fast.vhdl
-- Author : Erich Wenger <[email protected]>
-- Company : Graz University of Technology
-- Created : 2014-03-21
-- Last update: 2014-09-22
-- Platform : ASIC design
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-21 1.0 Erich Wenger Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon is
generic (
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
DataInxDI : in std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
DataOutxDO : out std_logic_vector(DATA_BLOCK_SIZE-1 downto 0));
end entity ascon;
architecture structural of ascon is
constant CONTROL_STATE_SIZE : integer := 4;
constant STATE_WORD_SIZE : integer := 64;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
type state_type is array (4 downto 0) of std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal StatexDP, StatexDN : state_type;
signal DataInxDP, DataInxDN : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
signal DataOutxDP, DataOutxDN : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
variable x : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- ROTATE_STATE_WORD
x := word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
return x;
end ROTATE_STATE_WORD;
function RoundFunction (
constant roundconst : std_logic_vector(3 downto 0);
StateInxD : state_type)
return state_type is
variable P0xDV, P1xDV, P2xDV, P3xDV, P4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable R0xDV, R1xDV, R2xDV, R3xDV, R4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable S0xDV, S1xDV, S2xDV, S3xDV, S4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable T0xDV, T1xDV, T2xDV, T3xDV, T4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable U0xDV, U1xDV, U2xDV, U3xDV, U4xDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable RoundConstxDV : std_logic_vector(63 downto 0);
variable StateOutxD : state_type;
begin -- function RoundFunction
RoundConstxDV := ZEROS(64-8) & not roundconst(3 downto 0) & roundconst(3 downto 0);
P0xDV := StateInxD(0);
P1xDV := StateInxD(1);
P2xDV := StateInxD(2);
P3xDV := StateInxD(3);
P4xDV := StateInxD(4);
R0xDV := P0xDV xor P4xDV;
R1xDV := P1xDV;
R2xDV := P2xDV xor P1xDV xor RoundConstxDV;
R3xDV := P3xDV;
R4xDV := P4xDV xor P3xDV;
S0xDV := R0xDV xor (not R1xDV and R2xDV);
S1xDV := R1xDV xor (not R2xDV and R3xDV);
S2xDV := R2xDV xor (not R3xDV and R4xDV);
S3xDV := R3xDV xor (not R4xDV and R0xDV);
S4xDV := R4xDV xor (not R0xDV and R1xDV);
T0xDV := S0xDV xor S4xDV;
T1xDV := S1xDV xor S0xDV;
T2xDV := not S2xDV;
T3xDV := S3xDV xor S2xDV;
T4xDV := S4xDV;
U0xDV := T0xDV xor ROTATE_STATE_WORD(T0xDV, 19) xor ROTATE_STATE_WORD(T0xDV, 28);
U1xDV := T1xDV xor ROTATE_STATE_WORD(T1xDV, 61) xor ROTATE_STATE_WORD(T1xDV, 39);
U2xDV := T2xDV xor ROTATE_STATE_WORD(T2xDV, 1) xor ROTATE_STATE_WORD(T2xDV, 6);
U3xDV := T3xDV xor ROTATE_STATE_WORD(T3xDV, 10) xor ROTATE_STATE_WORD(T3xDV, 17);
U4xDV := T4xDV xor ROTATE_STATE_WORD(T4xDV, 7) xor ROTATE_STATE_WORD(T4xDV, 41);
StateOutxD(0) := U0xDV;
StateOutxD(1) := U1xDV;
StateOutxD(2) := U2xDV;
StateOutxD(3) := U3xDV;
StateOutxD(4) := U4xDV;
return StateOutxD;
end function RoundFunction;
begin -- architecture structural
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
StatexDP <= (others => (others => '0'));
DataInxDP <= (others => '0');
DataOutxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
StatexDP <= StatexDN;
DataInxDP <= DataInxDN;
DataOutxDP <= DataOutxDN;
end if;
end process RegisterProc;
-- purpose: Datapath of Ascon
-- type : combinational
DatapathProc : process (DataInxDI, DataInxDP, DataOutxDP, StatexDP) is
variable State0xD, State1xD, State2xD, State3xD, State4xD, State5xD, State6xD : state_type;
variable P0xD : std_logic_vector(63 downto 0);
begin -- process DatapathProc
DataInxDN <= DataInxDI;
DataOutxDO <= DataOutxDP;
State0xD := StatexDP;
P0xD := StatexDP(0) xor DataInxDP;
DataOutxDN <= P0xD;
State0xD(0) := P0xD;
State1xD := RoundFunction("0000", State0xD);
State2xD := RoundFunction("0001", State1xD);
State3xD := RoundFunction("0010", State2xD);
State4xD := RoundFunction("0011", State3xD);
State5xD := RoundFunction("0100", State4xD);
State6xD := RoundFunction("0101", State5xD);
StatexDN <= State6xD;
end process DatapathProc;
end architecture structural;
| apache-2.0 | fa22ca0be9fdccef2b6def4dadf1ab3d | 0.615243 | 3.526527 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/io_registers.vhd | 4 | 22,661 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: io_registers.vhd
-- Description: This file contains the IO registers for the EMC
-- design.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is based on version v3_01_c updated to fixed CR #466745: -
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE. This is used to cpture the Mem_DQ_I
-- 1. If C_MEM_DQ_CAPTURE_NEGEDGE=0 Mem_DQ_I will be captured on +ve edge
-- (same as version v3_01_c)
-- 2. If C_MEM_DQ_CAPTURE_NEGEDGE=1 Mem_DQ_I will be captured on -ve edge (new)
-- ~~~~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE in comment "Definition of Generics"
-- section.
-- ~~~~~~~~
-- NSK 03/03/08 Updated
-- ^^^^^^^^
-- 1. Removed generic C_MEM_DQ_CAPTURE_NEGEDGE.
-- 2. Added the port RdClk used as clock to capture the data from memory.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. This file is same as in version v3_00_a.
-- 2. Upgraded to version v4.00.a
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INCLUDE_NEGEDGE_IOREGS -- include negative edge IO registers
-- C_IPIF_AWIDTH -- width of processor address bus
-- C_MAX_MEM_WIDTH -- maximum data width of memory banks
-- C_NUM_BANKS_MEM -- number of memory banks
--
-- Definition of Ports:
-- -- Internal memory signals
-- Mem_A_int -- Internal Memory address inputs
-- Mem_DQ_I_int -- Internal Memory input data bus
-- Mem_DQ_O_int -- Internal Memory output data bus
-- Mem_DQ_T_int -- Internal Memory data output enable
-- Mem_CEN_int -- Internal Memory chip select
-- Mem_OEN_int -- Internal Memory output enable
-- Mem_WEN_int -- Internal Memory write enable
-- Mem_QWEN_int -- Internal Memory qualified write enable
-- Mem_BEN_int -- Internal Memory byte enables
-- Mem_RPN_int -- Internal Memory reset/power down
-- Mem_CE_int -- Internal Memory chip enable
-- Mem_ADV_LDN_int -- Internal Memory counter
-- advance/load (=0)
-- Mem_LBON_int -- Internal Memory linear/interleaved
-- burst order (=0)
-- Mem_CKEN_int -- Internal Memory clock enable (=0)
-- Mem_RNW_int -- Internal Memory read not write
--
-- -- Memory signals
-- Mem_A -- Memory address inputs
-- Mem_DQ_I -- Memory input data bus
-- Mem_DQ_O -- Memory output data bus
-- Mem_DQ_T -- Memory data output enable
-- Mem_CEN -- Memory chip select
-- Mem_OEN -- Memory output enable
-- Mem_WEN -- Memory write enable
-- Mem_QWEN -- Memory qualified write enable
-- Mem_BEN -- Memory byte enables
-- Mem_RPN -- Memory reset/power down
-- Mem_CE -- Memory chip enable
-- Mem_ADV_LDN -- Memory counter advance/load (=0)
-- Mem_LBON -- Memory linear/interleaved burst
-- order (=0)
-- Mem_CKEN -- Memory clock enable (=0)
-- Mem_RNW -- Memory read not write
--
-- --- Clock & Reset
-- Clk -- System Clock
-- RdClk -- Read Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity io_registers is
generic (
C_INCLUDE_NEGEDGE_IOREGS : integer range 0 to 1;
C_IPIF_AWIDTH : integer;
C_MAX_MEM_WIDTH : integer;
C_NUM_BANKS_MEM : integer;
C_FAMILY : string := "virtex6"
);
port (
-- Internal memory signals
Mem_A_int : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_DQ_I_int : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PARITY_I_int : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PARITY_O_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PARITY_T_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CEN_int : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN_int : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN_int : in std_logic;
Mem_QWEN_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_RPN_int : in std_logic;
Mem_CE_int : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN_int : in std_logic;
Mem_LBON_int : in std_logic;
Mem_CKEN_int : in std_logic;
Mem_RNW_int : in std_logic;
Mem_Addr_rst : in std_logic;
-- Memory signals
Mem_A : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_DQ_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PRTY_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_RPN : out std_logic;
Mem_CE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic;
Linear_flash_brst_rd_flag : in std_logic;
-- Clock & Reset
Clk : in std_logic;
RdClk : in std_logic;
Rst : in std_logic
);
end entity io_registers;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of io_registers is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal mem_a_reg : std_logic_vector(0 to C_IPIF_AWIDTH-1);
--signal mem_a_reg1 : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal mem_dq_o_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_t_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_paity_o_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_paity_t_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_cen_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_oen_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_wen_reg : std_logic;
signal mem_qwen_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_ben_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_rpn_reg : std_logic;
signal mem_ce_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_adv_ldn_reg : std_logic;
signal mem_lbon_reg : std_logic;
signal mem_cken_reg : std_logic;
signal mem_rnw_reg : std_logic;
signal rd_data_ack : std_logic;
signal rd_data_ack_int : std_logic;
signal one_hot_rd_data_d1 : std_logic;
signal one_hot_rd_data_d2 : std_logic;
signal Mem_DQ_I_v : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal Mem_DQ_I_v1 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal Mem_DQ_PARITY_I_io : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
-------------------------------------------------------------------------------
-- Component declarations
-------------------------------------------------------------------------------
attribute KEEP : string;
attribute KEEP of mem_wen_reg : signal is "true";
attribute IOB : string;
attribute IOB of Mem_DQ_I_v : signal is "true";
attribute IOB of Mem_DQ_PARITY_I_io : signal is "true";
attribute IOB of mem_dq_o_reg : signal is "true";
attribute IOB of mem_dq_t_reg : signal is "true";
attribute IOB of mem_dq_paity_o_reg : signal is "true";
attribute IOB of mem_dq_paity_t_reg : signal is "true";
attribute IOB of mem_ce_reg : signal is "true";
attribute IOB of mem_cen_reg : signal is "true";
attribute IOB of mem_oen_reg : signal is "true";
attribute IOB of mem_ben_reg : signal is "true";
attribute IOB of mem_qwen_reg : signal is "true";
attribute IOB of mem_rpn_reg : signal is "true";
attribute IOB of mem_rnw_reg : signal is "true";
attribute IOB of mem_wen_reg : signal is "true";
--Ports tied to zero
attribute IOB of mem_adv_ldn_reg : signal is "true";
attribute IOB of mem_lbon_reg : signal is "true";
attribute IOB of mem_cken_reg : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- OUTPUTS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Instantiate the positive clock edge output register.
-- This is always present due to combinational logic on the memory control
-- signals.
-------------------------------------------------------------------------------
POSEDGE_OUTPUTREGS_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
mem_dq_o_reg <= (others => '0');
mem_dq_t_reg <= (others => '1');
mem_dq_paity_o_reg <= (others => '0');
mem_dq_paity_t_reg <= (others => '1');
mem_cen_reg <= (others => '1');
mem_oen_reg <= (others => '1');
mem_wen_reg <= '1';
mem_qwen_reg <= (others => '1');
mem_ben_reg <= (others => '1');
mem_rpn_reg <= '0';
mem_ce_reg <= (others => '0');
mem_adv_ldn_reg <= '0';
mem_lbon_reg <= '0';
mem_cken_reg <= '0';
mem_rnw_reg <= '0';
else
mem_dq_o_reg <= Mem_DQ_O_int;
mem_dq_t_reg <= Mem_DQ_T_int;
mem_dq_paity_o_reg <= Mem_DQ_PARITY_O_int;
mem_dq_paity_t_reg <= Mem_DQ_PARITY_T_int;
mem_cen_reg <= Mem_CEN_int;
mem_oen_reg <= Mem_OEN_int;
mem_wen_reg <= Mem_WEN_int;
mem_qwen_reg <= Mem_QWEN_int;
mem_ben_reg <= Mem_BEN_int;
mem_rpn_reg <= Mem_RPN_int;
mem_ce_reg <= Mem_CE_int;
mem_adv_ldn_reg <= Mem_ADV_LDN_int;
mem_lbon_reg <= Mem_LBON_int;
mem_cken_reg <= Mem_CKEN_int;
mem_rnw_reg <= Mem_RNW_int;
end if;
end if;
end process POSEDGE_OUTPUTREGS_PROCESS;
-------------------------------------------------------------------------------
-- MEM_ADDR_PROCESS: This process is added to fix CR: 214725
--
-------------------------------------------------------------------------------
--MEM_ADDR_PROCESS: process(clk)
--begin
-- if Clk'event and Clk = '1' then
-- if (Mem_Addr_rst = '1') then
-- mem_a_reg <= (others => '0');
-- --mem_a_reg1 <= (others => '0');
-- else
-- mem_a_reg <= Mem_A_int;
-- --mem_a_reg <= mem_a_reg1 ;
-- end if;
-- end if;
--end process MEM_ADDR_PROCESS;
mem_a_reg <= (others => '0') when (Mem_Addr_rst = '1') else Mem_A_int;
-------------------------------------------------------------------------------
-- Instantiate the negative clock edge output register if design has been
-- configured to do so.
-------------------------------------------------------------------------------
NEGEDGE_OUTPUT_REGS_GEN: if C_INCLUDE_NEGEDGE_IOREGS = 1 generate
begin
NEGEDGE_OUTPUTREGS_PROCESS: process(Clk)
begin
if Clk'event and Clk = '0' then
if Rst = '1' then
Mem_A <= (others => '0');
Mem_DQ_O <= (others => '0');
Mem_DQ_T <= (others => '1');
Mem_DQ_PRTY_O <= (others => '0');
Mem_DQ_PRTY_T <= (others => '1');
Mem_CEN <= (others => '1');
Mem_OEN <= (others => '1');
Mem_WEN <= '1';
Mem_QWEN <= (others => '1');
Mem_BEN <= (others => '1');
Mem_RPN <= '0';
Mem_CE <= (others => '0');
Mem_ADV_LDN <= '0';
Mem_LBON <= '0';
Mem_CKEN <= '0';
Mem_RNW <= '0';
else
Mem_A <= mem_a_reg;
Mem_DQ_O <= mem_dq_o_reg;
Mem_DQ_T <= mem_dq_t_reg;
Mem_DQ_PRTY_O <= mem_dq_paity_o_reg;
Mem_DQ_PRTY_T <= mem_dq_paity_t_reg;
Mem_CEN <= mem_cen_reg;
Mem_OEN <= mem_oen_reg;
Mem_WEN <= mem_wen_reg;
Mem_QWEN <= mem_qwen_reg;
Mem_BEN <= mem_ben_reg;
Mem_RPN <= mem_rpn_reg;
Mem_CE <= mem_ce_reg;
Mem_ADV_LDN <= mem_adv_ldn_reg;
Mem_LBON <= mem_lbon_reg;
Mem_CKEN <= mem_cken_reg;
Mem_RNW <= mem_rnw_reg;
end if;
end if;
end process NEGEDGE_OUTPUTREGS_PROCESS;
end generate NEGEDGE_OUTPUT_REGS_GEN;
-------------------------------------------------------------------------------
-- Pass the values through if there are no negative io registers
-------------------------------------------------------------------------------
NO_NEGEDGE_OUTPUT_REGS_GEN: if C_INCLUDE_NEGEDGE_IOREGS = 0 generate
begin
Mem_A <= mem_a_reg;
Mem_DQ_O <= mem_dq_o_reg;
Mem_DQ_T <= mem_dq_t_reg;
Mem_DQ_PRTY_O <= mem_dq_paity_o_reg;
Mem_DQ_PRTY_T <= mem_dq_paity_t_reg;
Mem_CEN <= mem_cen_reg;
Mem_OEN <= mem_oen_reg;
Mem_WEN <= mem_wen_reg;
Mem_QWEN <= mem_qwen_reg;
Mem_BEN <= mem_ben_reg;
Mem_RPN <= mem_rpn_reg;
Mem_CE <= mem_ce_reg;
Mem_ADV_LDN <= mem_adv_ldn_reg;
Mem_LBON <= mem_lbon_reg;
Mem_CKEN <= mem_cken_reg;
Mem_RNW <= mem_rnw_reg;
end generate NO_NEGEDGE_OUTPUT_REGS_GEN;
-------------------------------------------------------------------------------
-- Registers the input memory data port signals.
-------------------------------------------------------------------------------
INPUTREGS_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
if Rst = '1' then
Mem_DQ_I_v <= (others => '0');
Mem_DQ_I_v1 <= (others => '0');
Mem_DQ_PARITY_I_io <= (others => '0');
else
Mem_DQ_I_v <= Mem_DQ_I;
Mem_DQ_I_v1 <= Mem_DQ_I_v;
Mem_DQ_PARITY_I_io <= Mem_DQ_PRTY_I;
end if;
end if;
end process INPUTREGS_PROCESS;
Mem_DQ_I_int <= Mem_DQ_I_v1 when (Linear_flash_brst_rd_flag = '1') else Mem_DQ_I_v;
Mem_DQ_PARITY_I_int <= Mem_DQ_PARITY_I_io;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File io_registers.vhd.
-------------------------------------------------------------------------------
| gpl-3.0 | d29f03f7e8115b3aa5d97d89d56aa1cf | 0.459733 | 4.00725 | false | false | false | false |
RussGlover/381-module-1 | project/hardware/vhdl/euclidean_interface.vhd | 1 | 1,258 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity euclidean_interface is
port(
clock, reset : in std_logic;
writedata : in std_logic_vector(255 downto 0);
readdata : out std_logic_vector(255 downto 0);
write_n : in std_logic
);
end euclidean_interface;
architecture behavioural of euclidean_interface is
component euclidean
port (
input1values, input2values : in std_logic_vector(127 downto 0);
distance : out std_logic_vector(31 downto 0)
);
end component;
signal operand1, operand2 : std_logic_vector(127 downto 0) := (others => '0');
signal result : std_logic_vector(31 downto 0) := (others => '0');
signal zeroes : std_logic_vector(223 downto 0) := (others => '0');
begin
euclidean_distance : euclidean port map(
input1values => operand1,
input2values => operand2,
distance => result
);
process(clock, reset)
begin
if (reset = '1') then
operand1 <= (others => '0');
operand2 <= (others => '0');
elsif (rising_edge(clock)) then
if (write_n = '1') then
operand1 <= writedata(127 downto 0);
operand2 <= writedata(255 downto 128);
readdata <= zeroes & result;
else
null;
end if;
end if;
end process;
end behavioural;
| mit | 17dcad4167c409d09fea5ae77309c1a8 | 0.653418 | 3.217391 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/AEAD_Wrapper.vhd | 2 | 3,037 | -------------------------------------------------------------------------------
--! @file AEAD_Wrapper.vhd
--! @brief 5-bit wrapper for AEAD.vhd
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD_Wrapper is
generic (
G_W : integer := 32;
G_SW : integer := 32
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! SERDES signals
sin : in std_logic;
ssel : in std_logic;
sout : out std_logic
);
end entity AEAD_Wrapper;
architecture structure of AEAD_Wrapper is
signal sipo : std_logic_vector(G_W+G_SW+3 -1 downto 0);
signal piso : std_logic_vector(G_W+3 -1 downto 0);
signal piso_data : std_logic_vector(G_W+3 -1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
sipo <= sin & sipo(sipo'high downto 1);
if (ssel = '1') then
piso <= piso_data;
else
piso <= '0' & piso(piso'high downto 1);
end if;
end if;
end process;
sout <= piso(0);
u_aead:
entity work.AEAD(structure)
generic map (
G_W => G_W ,
G_SW => G_SW
)
port map (
clk => clk ,
rst => rst ,
--! Input signals
pdi_data => sipo( G_W-1 downto 0),
sdi_data => sipo( G_SW+G_W-1 downto G_W),
pdi_valid => sipo(1+G_SW+G_W-1) ,
sdi_valid => sipo(2+G_SW+G_W-1) ,
do_ready => sipo(3+G_SW+G_W-1) ,
--! Output signals
do_data => piso_data( G_W-1 downto 0),
pdi_ready => piso_data(1+G_W-1) ,
sdi_ready => piso_data(2+G_W-1) ,
do_valid => piso_data(3+G_W-1)
);
end structure; | apache-2.0 | 5ad8f97a2a80ee79e57cfa3758dc0649 | 0.426359 | 4.244755 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/emac.vhd | 4 | 21,370 | -------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
| gpl-3.0 | 58e59d00aaa4e11b71bf7194eeb2bfe9 | 0.387131 | 4.443751 | false | false | false | false |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_rtl/old/ASCON_Round.vhd | 1 | 2,854 | -------------------------------------------------------------------------------
--! @file ASCON_Round.vhd
--! @author Ekawat (ice) Homsirikamol
--! @brief Round unit for ASCON
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ASCON_Round is
port (
ii : in std_logic_vector(320 -1 downto 0);
rc : in std_logic_vector( 8 -1 downto 0);
oo : out std_logic_vector(320 -1 downto 0)
);
end entity ASCON_Round;
architecture structure of ASCON_Round is
type stype is array ( 0 to 4)
of std_logic_vector(64 -1 downto 0);
signal x : stype;
signal add : stype;
signal sub : stype;
signal ldiff : stype;
type sboxtype is array (63 downto 0)
of std_logic_vector(5 -1 downto 0);
signal subi : sboxtype;
signal subo : sboxtype;
type sbox_rom_type is array ( 0 to 31) of integer range 0 to 31;
constant sbox_rom : sbox_rom_type :=
(4, 11, 31, 20, 26, 21, 9, 2, 27, 5, 8, 18, 29, 3, 6, 28,
30, 19, 7, 14, 0, 13, 17, 24, 16, 12, 1, 25, 22, 10, 15, 23);
begin
gmap:
for i in 0 to 4 generate
x(i) <= ii(320-1-64*i downto 320-64-64*i);
oo(320-1-64*i downto 320-64-64*i) <= ldiff(i);
end generate;
--! Addition of RC
add(0) <= x(0);
add(1) <= x(1);
add(2) <= x(2)(63 downto 8) & (x(2)(7 downto 0) xor rc);
add(3) <= x(3);
add(4) <= x(4);
--! Substitution layer
gSub0:
for i in 63 downto 0 generate
subi(i) <= add(0)(i) & add(1)(i) & add(2)(i) & add(3)(i) & add(4)(i);
subo(i) <= std_logic_vector(to_unsigned(sbox_rom(to_integer(unsigned(subi(i)))), 5));
sub(0)(i) <= subo(i)(4);
sub(1)(i) <= subo(i)(3);
sub(2)(i) <= subo(i)(2);
sub(3)(i) <= subo(i)(1);
sub(4)(i) <= subo(i)(0);
end generate;
--! Linear diffusion
ldiff(0) <= sub(0) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(0)), 19)) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(0)), 28));
ldiff(1) <= sub(1) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(1)), 61)) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(1)), 39));
ldiff(2) <= sub(2) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(2)), 1)) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(2)), 6));
ldiff(3) <= sub(3) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(3)), 10)) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(3)), 17));
ldiff(4) <= sub(4) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(4)), 7)) xor std_logic_vector(ROTATE_RIGHT(unsigned(sub(4)), 41));
end architecture structure; | apache-2.0 | 633e9bb78970db8dda2e30a9c72407fd | 0.512263 | 3.082073 | false | false | false | false |
hoangt/PoC | tb/misc/sync/sync_Vector_tb.vhdl | 2 | 3,312 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a vector signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Vector_tb is
end;
architecture test of sync_Vector_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal Sync_out : STD_LOGIC_VECTOR(1 downto 0);
signal Sync_Busy : STD_LOGIC;
signal Sync_Changed : STD_LOGIC;
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "01";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "XX";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "XX";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "XX";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "XX";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "10";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "01";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncVec : entity PoC.sync_Vector
generic map (
BITS => 2, -- number of bit to be synchronized
INIT => "00" --
)
port map (
Clock1 => Clock1, -- input clock domain
Clock2 => Clock2, -- output clock domain
Input => Sync_in, -- input bits
Output => Sync_out, -- output bits
Busy => Sync_Busy, -- busy bits
Changed => Sync_Changed -- changed bits
);
end;
| apache-2.0 | 0c83f3553d742c286d480694c51ab689 | 0.560085 | 3.282458 | false | false | false | false |
hoangt/PoC | src/mem/ocram/altera/ocram_tdp_altera.vhdl | 2 | 5,318 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiate true dual-port memory on Altera FPGAs.
--
-- Description:
-- ------------------------------------
-- Quartus synthesis does not infer this RAM type correctly.
-- Instead, altsyncram is instantiated directly.
--
-- For further documentation see module "ocram_tdp"
-- (src/mem/ocram/ocram_tdp.vhdl).
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library altera_mf;
use altera_mf.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_tdp_altera is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
we2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
d2 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_tdp_altera;
architecture rtl of ocram_tdp_altera is
component altsyncram
generic (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING;
wrcontrol_wraddress_reg_b : STRING);
port (
clocken0 : IN STD_LOGIC;
clocken1 : IN STD_LOGIC;
wren_a : IN STD_LOGIC;
clock0 : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
clock1 : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
);
end component;
constant DEPTH : positive := 2**A_BITS;
constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME);
signal a1_sl : std_logic_vector(A_BITS-1 downto 0);
signal a2_sl : std_logic_vector(A_BITS-1 downto 0);
begin
a1_sl <= std_logic_vector(a1);
a2_sl <= std_logic_vector(a2);
mem : altsyncram
generic map (
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
indata_reg_b => "CLOCK1",
init_file => INIT_FILE,
intended_device_family => "Stratix",
lpm_type => "altsyncram",
numwords_a => DEPTH,
numwords_b => DEPTH,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
widthad_b => A_BITS,
width_a => D_BITS,
width_b => D_BITS,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE",
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
clock0 => clk1,
clock1 => clk2,
clocken0 => ce1,
clocken1 => ce2,
wren_a => we1,
wren_b => we2,
address_a => a1_sl,
address_b => a2_sl,
data_a => d1,
data_b => d2,
q_a => q1,
q_b => q2
);
end rtl;
| apache-2.0 | 341833f8c81d3ce275ec2209ddaa99a7 | 0.562053 | 2.979272 | false | false | false | false |
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