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skordal/potato | src/pp_alu.vhd | 1 | 1,952 | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
--! @brief
--! Arithmetic Logic Unit (ALU).
--!
--! @details
--! Performs logic and arithmetic calculations. The operation to perform
--! is specified by the user of the module.
entity pp_alu is
port(
x, y : in std_logic_vector(31 downto 0); --! Input operand.
result : out std_logic_vector(31 downto 0); --! Operation result.
operation : in alu_operation --! Operation type.
);
end entity pp_alu;
--! @brief Behavioural description of the ALU.
architecture behaviour of pp_alu is
begin
--! Performs the ALU calculation.
calculate: process(operation, x, y)
begin
case operation is
when ALU_AND =>
result <= x and y;
when ALU_OR =>
result <= x or y;
when ALU_XOR =>
result <= x xor y;
when ALU_SLT =>
if signed(x) < signed(y) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when ALU_SLTU =>
if unsigned(x) < unsigned(y) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when ALU_ADD =>
result <= std_logic_vector(unsigned(x) + unsigned(y));
when ALU_SUB =>
result <= std_logic_vector(unsigned(x) - unsigned(y));
when ALU_SRL =>
result <= std_logic_vector(shift_right(unsigned(x), to_integer(unsigned(y(4 downto 0)))));
when ALU_SLL =>
result <= std_logic_vector(shift_left(unsigned(x), to_integer(unsigned(y(4 downto 0)))));
when ALU_SRA =>
result <= std_logic_vector(shift_right(signed(x), to_integer(unsigned(y(4 downto 0)))));
when others =>
result <= (others => '0');
end case;
end process calculate;
end architecture behaviour;
| bsd-3-clause | 165b554b0ff697dbb32c39e499e4357f | 0.631148 | 3.194763 | false | false | false | false |
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| gpl-2.0 | 29d3adbaae5c8f4ddf8131768149d071 | 0.915576 | 1.943156 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_uart/tb/uvvm_demo_th.vhd | 1 | 11,085 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library uvvm_util;
context uvvm_util.uvvm_util_context; -- t_channel (RX/TX)
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;
library bitvis_vip_uart;
context bitvis_vip_uart.vvc_context;
use bitvis_vip_uart.monitor_cmd_pkg.all;
library bitvis_uart;
library bitvis_vip_clock_generator;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
-- Test harness entity
entity uvvm_demo_th is
generic (
-- Clock and bit period settings
GC_CLK_PERIOD : time := 10 ns;
GC_BIT_PERIOD : time := 16 * GC_CLK_PERIOD;
-- DUT addresses
GC_ADDR_RX_DATA : unsigned(2 downto 0) := "000";
GC_ADDR_RX_DATA_VALID : unsigned(2 downto 0) := "001";
GC_ADDR_TX_DATA : unsigned(2 downto 0) := "010";
GC_ADDR_TX_READY : unsigned(2 downto 0) := "011";
-- Activity watchdog setting
GC_ACTIVITY_WATCHDOG_TIMEOUT : time := 50 * GC_BIT_PERIOD
);
end entity uvvm_demo_th;
-- Test harness architecture
architecture struct of uvvm_demo_th is
-- VVC idx
constant C_SBI_VVC : natural := 1;
constant C_UART_TX_VVC : natural := 1;
constant C_UART_RX_VVC : natural := 1;
constant C_CLOCK_GEN_VVC : natural := 1;
-- UART if
constant C_DATA_WIDTH : natural := 8;
constant C_ADDR_WIDTH : natural := 3;
-- Clock and reset signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- SBI VVC signals
signal cs : std_logic;
signal addr : unsigned(2 downto 0);
signal wr : std_logic;
signal rd : std_logic;
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- UART VVC signals
signal uart_vvc_rx : std_logic := '1';
signal uart_vvc_tx : std_logic := '1';
-- UART Monitor
constant C_UART_MONITOR_INTERFACE_CONFIG : t_uart_interface_config := (
bit_time => GC_BIT_PERIOD,
num_data_bits => 8,
parity => PARITY_ODD,
num_stop_bits => STOP_BITS_ONE
);
constant C_UART_MONITOR_CONFIG : t_uart_monitor_config := (
scope_name => (1 to 12 => "UART Monitor", others => NUL),
msg_id_panel => C_UART_MONITOR_MSG_ID_PANEL_DEFAULT,
interface_config => C_UART_MONITOR_INTERFACE_CONFIG,
transaction_display_time => 0 ns
);
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => cs,
addr => addr,
wr => wr,
rd => rd,
wdata => wdata,
rdata => rdata,
-- UART signals
rx_a => uart_vvc_tx,
tx => uart_vvc_rx
);
-----------------------------------------------------------------------------
-- SBI VVC
-----------------------------------------------------------------------------
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => C_ADDR_WIDTH,
GC_DATA_WIDTH => C_DATA_WIDTH,
GC_INSTANCE_IDX => C_SBI_VVC
)
port map(
clk => clk,
sbi_vvc_master_if.cs => cs,
sbi_vvc_master_if.rena => rd,
sbi_vvc_master_if.wena => wr,
sbi_vvc_master_if.addr => addr,
sbi_vvc_master_if.wdata => wdata,
sbi_vvc_master_if.ready => ready,
sbi_vvc_master_if.rdata => rdata
);
-----------------------------------------------------------------------------
-- UART VVC
-----------------------------------------------------------------------------
i1_uart_vvc: entity bitvis_vip_uart.uart_vvc
generic map(
GC_INSTANCE_IDX => 1
)
port map(
uart_vvc_rx => uart_vvc_rx,
uart_vvc_tx => uart_vvc_tx
);
-- Static '1' ready signal for the SBI VVC
ready <= '1';
-----------------------------------------------------------------------------
-- Monitor - UART
--
-- Monitor and validate UART transactions.
--
-----------------------------------------------------------------------------
i1_uart_monitor : entity bitvis_vip_uart.uart_monitor
generic map(
GC_INSTANCE_IDX => 1,
GC_MONITOR_CONFIG => C_UART_MONITOR_CONFIG
)
port map(
uart_dut_tx => uart_vvc_rx,
uart_dut_rx => uart_vvc_tx
);
-----------------------------------------------------------------------------
-- Activity Watchdog
--
-- Monitor VVC activity and alert if no VVC activity is
-- detected before timeout.
--
-----------------------------------------------------------------------------
p_activity_watchdog:
activity_watchdog(timeout => GC_ACTIVITY_WATCHDOG_TIMEOUT,
num_exp_vvc => 4);
-----------------------------------------------------------------------------
-- Model
--
-- Subscribe to SBI and UART transaction infos, and send to Scoreboard or
-- send VVC commands based on transaction info content.
--
-----------------------------------------------------------------------------
p_model: process
-- SBI transaction info
alias sbi_vvc_transaction_info_trigger : std_logic is
global_sbi_vvc_transaction_trigger(C_SBI_VVC);
alias sbi_vvc_transaction_info : bitvis_vip_sbi.transaction_pkg.t_transaction_group is
shared_sbi_vvc_transaction_info(C_SBI_VVC);
-- UART transaction info
alias uart_rx_transaction_info_trigger : std_logic is
global_uart_vvc_transaction_trigger(RX, C_UART_RX_VVC);
alias uart_rx_transaction_info : bitvis_vip_uart.transaction_pkg.t_transaction_group is
shared_uart_vvc_transaction_info(RX, C_UART_RX_VVC);
alias uart_tx_transaction_info_trigger : std_logic is
global_uart_vvc_transaction_trigger(TX, C_UART_TX_VVC);
alias uart_tx_transaction_info : bitvis_vip_uart.transaction_pkg.t_transaction_group is
shared_uart_vvc_transaction_info(TX, C_UART_TX_VVC);
begin
while true loop
-- Wait for transaction info trigger
wait until (sbi_vvc_transaction_info_trigger = '1') or (uart_rx_transaction_info_trigger = '1') or (uart_tx_transaction_info_trigger = '1');
-------------------------------
-- SBI transaction info
-------------------------------
if sbi_vvc_transaction_info_trigger'event then
case sbi_vvc_transaction_info.bt.operation is
when WRITE =>
-- add to UART scoreboard
UART_VVC_SB.add_expected(sbi_vvc_transaction_info.bt.data(C_DATA_WIDTH-1 downto 0));
when READ =>
null;
when others =>
null;
end case;
end if;
-------------------------------
-- UART RX transaction info
-------------------------------
if uart_rx_transaction_info_trigger'event then
-- Send to SB is handled by RX VVC.
null;
end if;
-------------------------------
-- UART TX transaction
-------------------------------
if uart_tx_transaction_info_trigger'event then
case uart_tx_transaction_info.bt.operation is
when TRANSMIT =>
-- Check if transaction is intended valid / free of error
if (uart_tx_transaction_info.bt.error_info.parity_bit_error = false) and
(uart_tx_transaction_info.bt.error_info.stop_bit_error = false) then
-- Add to SBI scoreboard
SBI_VVC_SB.add_expected(pad_sbi_sb(uart_tx_transaction_info.bt.data(C_DATA_WIDTH-1 downto 0)));
-- Wait for UART Transmit to finish before SBI VVC start
insert_delay(SBI_VVCT, 1, 12*GC_BIT_PERIOD, "Wait for UART TX to finish");
-- Request SBI Read
sbi_read(SBI_VVCT, 1, GC_ADDR_RX_DATA, TO_SB, "SBI_READ");
end if;
when others =>
null;
end case;
end if;
end loop;
wait;
end process p_model;
-----------------------------------------------------------------------------
-- Clock Generator VVC
-----------------------------------------------------------------------------
i_clock_generator_vvc : entity bitvis_vip_clock_generator.clock_generator_vvc
generic map(
GC_INSTANCE_IDX => C_CLOCK_GEN_VVC,
GC_CLOCK_NAME => "Clock",
GC_CLOCK_PERIOD => GC_CLK_PERIOD,
GC_CLOCK_HIGH_TIME => GC_CLK_PERIOD / 2
)
port map(
clk => clk
);
-----------------------------------------------------------------------------
-- Reset
-----------------------------------------------------------------------------
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *GC_CLK_PERIOD;
end struct;
| mit | df6b1bf6f78974d770eeb9f496ea50ab | 0.476229 | 4.500609 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_spi/src/spi_vvc.vhd | 1 | 45,891 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.C_SB_CONFIG_DEFAULT;
use work.spi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
entity spi_vvc is
generic (
GC_DATA_WIDTH : natural := 8;
GC_DATA_ARRAY_WIDTH : natural := C_SPI_VVC_DATA_ARRAY_WIDTH;
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SPI_VVCT instance
GC_MASTER_MODE : boolean := true;
GC_SPI_CONFIG : t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
spi_vvc_if : inout t_spi_if := init_spi_if_signals(GC_SPI_CONFIG, GC_MASTER_MODE)
);
end entity spi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of spi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_spi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_spi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_spi_transaction_info(GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_spi_vvc_transaction_trigger(GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_spi_vvc_transaction_info(GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
--UVVM: temporary fix for HVVC, remove function below in v3.0
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
if command.msg(1 to 5) = "HVVC:" then
return vvc_config.parent_msg_id_panel;
else
return vvc_config.msg_id_panel;
end if;
end function;
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SPI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
variable v_temp_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc(name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
--UVVM: temporary fix for HVVC, remove two lines below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
v_temp_msg_id_panel := vvc_config.msg_id_panel;
vvc_config.msg_id_panel := v_msg_id_panel;
end if;
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack, v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
--UVVM: temporary fix for HVVC, remove line below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
vvc_config.msg_id_panel := v_temp_msg_id_panel;
end if;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
--uvvm_vvc_framework.ti_vvc_framework_support_pkg.acknowledge_cmd(global_vvc_ack);
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack, v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_msg_id_panel : t_msg_id_panel;
-- bus size
variable v_num_words : natural := 0;
-- normalized data to bus width
variable v_normalized_data : t_slv_array(GC_DATA_ARRAY_WIDTH-1 downto 0)(GC_DATA_WIDTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(GC_DATA_ARRAY_WIDTH-1 downto 0)(GC_DATA_WIDTH-1 downto 0) := (others => (others => '0'));
variable v_data_receive : t_slv_array(GC_DATA_ARRAY_WIDTH-1 downto 0)(GC_DATA_WIDTH-1 downto 0) := (others => (others => '0'));
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Setup SPI scoreboard
SPI_VVC_SB.set_scope("SPI_VVC_SB");
SPI_VVC_SB.enable(GC_INSTANCE_IDX, "SPI VVC SB Enabled");
SPI_VVC_SB.config(GC_INSTANCE_IDX, C_SB_CONFIG_DEFAULT);
SPI_VVC_SB.enable_log_msg(GC_INSTANCE_IDX, ID_DATA);
loop
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = MASTER_TRANSMIT_AND_RECEIVE or
v_cmd.operation = MASTER_TRANSMIT_AND_CHECK or
v_cmd.operation = MASTER_TRANSMIT_ONLY or
v_cmd.operation = MASTER_RECEIVE_ONLY or
v_cmd.operation = MASTER_CHECK_ONLY or
v_cmd.operation = SLAVE_TRANSMIT_AND_RECEIVE or
v_cmd.operation = SLAVE_TRANSMIT_AND_CHECK or
v_cmd.operation = SLAVE_TRANSMIT_ONLY or
v_cmd.operation = SLAVE_RECEIVE_ONLY or
v_cmd.operation = SLAVE_CHECK_ONLY
then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
msg_id_panel => v_msg_id_panel,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
v_num_words := v_cmd.num_words;
transaction_info.num_words := v_cmd.num_words;
transaction_info.word_length := GC_DATA_WIDTH;
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when MASTER_TRANSMIT_AND_RECEIVE =>
if GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
transaction_info.tx_data := v_cmd.data;
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_master_transmit_and_receive(tx_data => v_cmd.data(0)(GC_DATA_WIDTH-1 downto 0),
rx_data => v_result(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data := normalize_and_check(v_cmd.data, v_normalized_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalized_data", "normalizing data to BFM");
spi_master_transmit_and_receive(tx_data => v_normalized_data(v_num_words-1 downto 0),
rx_data => v_data_receive(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
action_between_words => v_cmd.action_between_words,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
v_result := normalize_and_check(v_data_receive, v_result, ALLOW_WIDER_NARROWER, "v_data_receive", "v_result", "normalizing data to result");
end if;
-- Store the result
for i in 0 to v_num_words-1 loop
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
SPI_VVC_SB.check_received(GC_INSTANCE_IDX, pad_spi_sb(v_result(i)(GC_DATA_WIDTH-1 downto 0)));
else
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result(i));
end if;
end loop;
else -- attempted master transmit and receive when in slave mode
alert(error, "Master transmit and receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_TRANSMIT_AND_CHECK =>
if GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
transaction_info.tx_data := v_cmd.data;
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_master_transmit_and_check(tx_data => v_cmd.data(0)(GC_DATA_WIDTH-1 downto 0),
data_exp => v_cmd.data_exp(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data := normalize_and_check(v_cmd.data, v_normalized_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalized_data", "normalizing data to BFM");
v_normalized_data_exp := normalize_and_check(v_cmd.data_exp, v_normalized_data_exp, ALLOW_WIDER_NARROWER, "v_cmd.data_exp", "v_normalized_data_exp", "normalizing data_exp to BFM");
spi_master_transmit_and_check(tx_data => v_normalized_data(v_num_words-1 downto 0),
data_exp => v_normalized_data_exp(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
action_between_words => v_cmd.action_between_words,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
else -- attempted master transmit and receive when in slave mode
alert(error, "Master transmit and check called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_TRANSMIT_ONLY =>
if GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
transaction_info.tx_data := v_cmd.data;
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_master_transmit(tx_data => v_cmd.data(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data := normalize_and_check(v_cmd.data, v_normalized_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalized_data", "normalizing data to BFM");
spi_master_transmit(tx_data => v_normalized_data(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
action_between_words => v_cmd.action_between_words,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
else -- attempted master transmit when in slave mode
alert(error, "Master transmit called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_RECEIVE_ONLY =>
if GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_master_receive(rx_data => v_result(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
spi_master_receive(rx_data => v_data_receive(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
action_between_words => v_cmd.action_between_words,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
v_result := normalize_and_check(v_data_receive, v_result, ALLOW_WIDER_NARROWER, "v_data_receive", "v_result", "normalizing data to result");
end if;
-- Store the result
for i in 0 to v_num_words-1 loop
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
SPI_VVC_SB.check_received(GC_INSTANCE_IDX, pad_spi_sb(v_result(i)(GC_DATA_WIDTH-1 downto 0)));
else
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result(i));
end if;
end loop;
else -- attempted master receive when in slave mode
alert(error, "Master receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_CHECK_ONLY =>
if GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_master_check(data_exp => v_cmd.data_exp(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data_exp := normalize_and_check(v_cmd.data_exp, v_normalized_data_exp, ALLOW_WIDER_NARROWER, "v_cmd.data_exp", "v_normalized_data_exp", "normalizing data_exp to BFM");
spi_master_check(data_exp => v_normalized_data_exp(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
action_when_transfer_is_done => v_cmd.action_when_transfer_is_done,
action_between_words => v_cmd.action_between_words,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
else -- attempted master check when in slave mode
alert(error, "Master check called when VVC is in slave mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_AND_RECEIVE =>
if not GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
transaction_info.tx_data := v_cmd.data;
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_slave_transmit_and_receive(tx_data => v_cmd.data(0)(GC_DATA_WIDTH-1 downto 0),
rx_data => v_result(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data := normalize_and_check(v_cmd.data, v_normalized_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalized_data", "normalizing data to BFM");
spi_slave_transmit_and_receive(tx_data => v_normalized_data(v_num_words-1 downto 0),
rx_data => v_data_receive(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
v_result := normalize_and_check(v_data_receive, v_result, ALLOW_WIDER_NARROWER, "v_data_receive", "v_result", "normalizing data to result");
end if;
-- Store the result
for i in 0 to v_num_words-1 loop
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
SPI_VVC_SB.check_received(GC_INSTANCE_IDX, pad_spi_sb(v_result(i)(GC_DATA_WIDTH-1 downto 0)));
else
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result(i));
end if;
end loop;
else -- attempted slave transmit when in master mode
alert(note, "Slave transmit and receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_AND_CHECK =>
if not GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_slave_transmit_and_check(tx_data => v_cmd.data(0)(GC_DATA_WIDTH-1 downto 0),
data_exp => v_cmd.data_exp(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data := normalize_and_check(v_cmd.data, v_normalized_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalized_data", "normalizing data to BFM");
v_normalized_data_exp := normalize_and_check(v_cmd.data_exp, v_normalized_data_exp, ALLOW_WIDER_NARROWER, "v_cmd.data_exp", "v_normalized_data_exp", "normalizing data_exp to BFM");
spi_slave_transmit_and_check(tx_data => v_normalized_data(v_num_words-1 downto 0),
data_exp => v_normalized_data_exp(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit and check called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_ONLY =>
if not GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_slave_transmit(tx_data => v_cmd.data(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data := normalize_and_check(v_cmd.data, v_normalized_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalized_data", "normalizing data to BFM");
spi_slave_transmit(tx_data => v_normalized_data(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_RECEIVE_ONLY =>
if not GC_MASTER_MODE then
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_slave_receive(rx_data => v_result(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
spi_slave_receive(rx_data => v_data_receive(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
v_result := normalize_and_check(v_data_receive, v_result, ALLOW_WIDER_NARROWER, "v_data_receive", "v_result", "normalizing data to result");
end if;
-- Store the result
for i in 0 to v_num_words-1 loop
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
SPI_VVC_SB.check_received(GC_INSTANCE_IDX, pad_spi_sb(v_result(i)(GC_DATA_WIDTH-1 downto 0)));
else
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result(i));
end if;
end loop;
else -- attempted slave receive when in master mode
alert(error, "Slave receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_CHECK_ONLY =>
if not GC_MASTER_MODE then -- slave check
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the BFM package.
if v_num_words = 1 then
spi_slave_check(data_exp => v_cmd.data_exp(0)(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
else
-- normalize
v_normalized_data_exp := normalize_and_check(v_cmd.data_exp, v_normalized_data_exp, ALLOW_WIDER_NARROWER, "v_cmd.data_exp", "v_normalized_data_exp", "normalizing data_exp to BFM");
spi_slave_check(data_exp => v_normalized_data_exp(v_num_words-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
when_to_start_transfer => v_cmd.when_to_start_transfer,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
end if;
else -- attempted slave check when in master mode
alert(error, "Slave check called when VVC is in master mode.", C_SCOPE);
end if;
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.spi_bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--========================================================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
| mit | 85d8ddf23b92dd36178bc4e9c5c78070 | 0.475017 | 4.517275 | false | true | false | false |
UVVM/uvvm_vvc_framework | xConstrRandFuncCov/src/NamePkg.vhd | 3 | 4,313 | --
-- File Name: NamePkg.vhd
-- Design Unit Name: NamePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for name.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- Separated name handling from message handling to simplify naming
-- 12/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 05/2015 2015.06 Added input to Get to return when not initialized
--
--
-- Copyright (c) 2010 - 2015 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use std.textio.all ;
package NamePkg is
type NamePType is protected
procedure Set (NameIn : String) ;
impure function Get (DefaultName : string := "") return string ;
impure function GetOpt return string ;
impure function IsSet return boolean ;
procedure Clear ; -- clear name
procedure Deallocate ; -- effectively alias to clear name
end protected NamePType ;
end package NamePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body NamePkg is
type NamePType is protected body
variable NamePtr : line ;
------------------------------------------------------------
procedure Set (NameIn : String) is
------------------------------------------------------------
begin
deallocate(NamePtr) ;
NamePtr := new string'(NameIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return DefaultName ;
else
return NamePtr.all ;
end if ;
end function Get ;
------------------------------------------------------------
impure function GetOpt return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return NUL & "" ;
else
return NamePtr.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return NamePtr /= NULL ;
end function IsSet ;
------------------------------------------------------------
procedure Clear is -- clear name
------------------------------------------------------------
begin
deallocate(NamePtr) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate is -- clear name
------------------------------------------------------------
begin
Clear ;
end procedure Deallocate ;
end protected body NamePType ;
end package body NamePkg ; | mit | 20a9755220823600046e69eac5e3acb1 | 0.497102 | 5.25335 | false | false | false | false |
keith-epidev/VHDL-lib | src/components/modn/modn.vhd | 1 | 577 | library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity modn is
generic(
size:integer := 4
);
port (
clk : in std_logic;
output : out std_logic_vector(log2(size)-1 downto 0)
);
end modn;
architecture arch of modn is
signal count: std_logic_vector(log2(size)-1 downto 0);
begin
counter:process(clk) begin
if(clk'event and clk = '1')then
output <= count;
if(count < size-1) then
count <= count + 1;
else
count <= (others=>'0');
end if;
end if;
end process;
end arch;
| gpl-2.0 | 208f0256f1592d36844acde99d6ccb53 | 0.665511 | 2.646789 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/VGA_BUFFER_RAM_tb.vhd | 8 | 4,695 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | f9a08f4383dc50e4d71f6435ac42c30e | 0.598296 | 4.379664 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_recip/flt_recip_eval.vhd | 3 | 41,947 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 29312)
`protect data_block
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`protect end_protected
| gpl-2.0 | 42e8233061035bfd418828da8cd8d1fc | 0.948292 | 1.822911 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/synth/bram.vhd | 3 | 13,781 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.11005 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.11005 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
| gpl-2.0 | adc74f441c5d6808305e37cc2a853080 | 0.629345 | 3.048894 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_spec_cov/demo/basic_usage/uart_vvc_tb.vhd | 1 | 7,368 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;
library bitvis_vip_uart;
context bitvis_vip_uart.vvc_context;
library bitvis_vip_spec_cov;
use bitvis_vip_spec_cov.spec_cov_pkg.all;
use bitvis_vip_spec_cov.local_adaptations_pkg.all;
--hdlunit:tb
-- Test bench entity
entity uart_vvc_tb is
end entity;
-- Test bench architecture
architecture func of uart_vvc_tb is
-- Assuming that the testbench is run from the sim folder
constant C_REQ_LIST_FILE : string := "../demo/basic_usage/req_list_basic_demo.csv";
constant C_PARTIAL_COV_FILE : string := "../sim/partial_cov_basic_demo.csv";
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
-- Clock and bit period settings
constant C_CLK_PERIOD : time := 10 ns;
constant C_BIT_PERIOD : time := 16 * C_CLK_PERIOD;
-- Time for one UART transmission to complete
constant C_TIME_OF_ONE_UART_TX : time := 11*C_BIT_PERIOD; -- =1760 ns;
-- Predefined SBI addresses
constant C_ADDR_RX_DATA : unsigned(2 downto 0) := "000";
constant C_ADDR_RX_DATA_VALID : unsigned(2 downto 0) := "001";
constant C_ADDR_TX_DATA : unsigned(2 downto 0) := "010";
constant C_ADDR_TX_READY : unsigned(2 downto 0) := "011";
begin
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and Executors
-----------------------------------------------------------------------------
i_test_harness : entity work.uart_vvc_th;
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_FILE_OPEN_CLOSE); -- Enable the Spec Cov IDs
enable_log_msg(ID_FILE_PARSER); -- Enable the Spec Cov IDs
enable_log_msg(ID_SPEC_COV); -- Enable the Spec Cov IDs
disable_log_msg(SBI_VVCT, 1, ALL_MESSAGES);
enable_log_msg(SBI_VVCT, 1, ID_BFM);
disable_log_msg(UART_VVCT, 1, RX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, RX, ID_BFM);
disable_log_msg(UART_VVCT, 1, TX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, TX, ID_BFM);
log("Starting the requirement coverage process");
initialize_req_cov("T_UART_1", C_REQ_LIST_FILE, C_PARTIAL_COV_FILE);
log(ID_LOG_HDR, "Starting simulation of TB for UART using VVCs", C_SCOPE);
------------------------------------------------------------
log("Wait 10 clock period for reset to be turned off");
wait for (10 * C_CLK_PERIOD); -- for reset to be turned off
log(ID_LOG_HDR, "Configure UART VVC 1", C_SCOPE);
------------------------------------------------------------
shared_uart_vvc_config(RX,1).bfm_config.bit_time := C_BIT_PERIOD;
shared_uart_vvc_config(TX,1).bfm_config.bit_time := C_BIT_PERIOD;
log(ID_LOG_HDR, "Check register defaults", C_SCOPE);
------------------------------------------------------------
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA, x"00", "RX_DATA default");
sbi_check(SBI_VVCT, 1, C_ADDR_TX_READY, x"01", "TX_READY default");
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA_VALID, x"00", "RX_DATA_VALID default");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
-- Log the requirement FPGA_SPEC_1 after test has completed
tick_off_req_cov("FPGA_SPEC_1");
log(ID_LOG_HDR, "Check simple transmit", C_SCOPE);
------------------------------------------------------------
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"55", "TX_DATA");
uart_expect(UART_VVCT,1,RX, x"55", "Expecting data on UART RX");
await_completion(UART_VVCT,1,RX, 13 * C_BIT_PERIOD);
-- Log the requirement FPGA_SPEC_2 after test has completed
tick_off_req_cov("FPGA_SPEC_2");
wait for 200 ns; -- margin
log(ID_LOG_HDR, "Check simple receive", C_SCOPE);
------------------------------------------------------------
uart_transmit(UART_VVCT,1,TX, x"AA", "UART TX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"AA", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
-- Log the requirement FPGA_SPEC_3 after test has completed
tick_off_req_cov("FPGA_SPEC_3");
log(ID_LOG_HDR, "Check single simultaneous transmit and receive", C_SCOPE);
------------------------------------------------------------
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"B4", "TX_DATA");
uart_transmit(UART_VVCT,1,TX, x"87", "UART TX");
uart_expect(UART_VVCT,1,RX, x"B4", "Expecting data on UART RX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"87", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
-- Log the requirement FPGA_SPEC_4 after test has completed
tick_off_req_cov("FPGA_SPEC_4");
-- End the requirement coverage process
finalize_req_cov(VOID);
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func; | mit | b8df82673b31ea5fd9fd5464739223fa | 0.54791 | 3.906681 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_shift_ram_v12_0/hdl/c_shift_ram_v12_0_comp.vhd | 3 | 8,941 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dUmudxQPJ5M2PUDUcYfgHnPRLwUwkC+XB5T9NZXSn1g1pZkQfv5gS7nPfe7ZEvjMS+o8Np/OANdA
qzGCJZt5cg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Q0E3aoAdb0B140iim4y1iiWNcdLjdZqMwLzOJF0nrmHO3yVpjEEgGf1jQH+Y/YzOfWa5Jl3SJkGc
ouotVfQ3L+XlWN5AjNfUWkJ53aP8Wv/WsOk/Y4PLvUEBmU0ktwMLMN8pnjpF12lPK1hINULYmL29
88CYRjB4uexXhBPiZAM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
guXO8dOVnzOMLvCDRhXwqvor/luFfcKIWSh2Utwe+ejYZeuA8SWjixYUeLxTvkIFHWNftaScbkxy
tWk+CPYQwpMDPVM+QFzH1mUehcqakbh/vF4Kz+xqLH+rgCCNRNdwsxiXIF6cJZ2H6gd5HBU69YmV
XsX9VER+56luo7nBZnq5y3LwvY/qJIwmAQU++TRuTRyGnV242iKGvtlv5YERkB4Y80eVXgNVMbDo
dW1x6Fb2wq7ynGdrgddF6A6+uBa4IVWQjQYB9HR5SOegmTsXziOgvSAYbY63zrgICebhgoYpSyIR
JKp82dZ6McEhEqWti+Z+z098lOqnguX6vcLwUA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect data_block
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`protect end_protected
| gpl-2.0 | 3397b1e5d3e71b9c0d232a0215253e60 | 0.920143 | 1.944118 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | Lab3/XTerm/XTerm/ipcore_dir/VGA_BUFFER_RAM.vhd | 1 | 5,842 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file VGA_BUFFER_RAM.vhd when simulating
-- the core, VGA_BUFFER_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY VGA_BUFFER_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END VGA_BUFFER_RAM;
ARCHITECTURE VGA_BUFFER_RAM_a OF VGA_BUFFER_RAM IS
-- synthesis translate_off
COMPONENT wrapped_VGA_BUFFER_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_VGA_BUFFER_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "VGA_BUFFER_RAM.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_VGA_BUFFER_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END VGA_BUFFER_RAM_a;
| gpl-3.0 | 9f23937b10afaec42f5d2a878716737c | 0.536118 | 3.902472 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/bram/synth/bram.vhd | 7 | 13,187 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- liability) for any loss or damage of any kind or nature
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
| gpl-2.0 | 29ad147bae964e0b6f44bc8083423abd | 0.631531 | 3.073893 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | bfa6774e09173323ba26d514035fd5df | 0.938862 | 1.860832 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_pkg.vhd | 8 | 27,921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18928)
`protect data_block
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`protect end_protected
| gpl-2.0 | bb1407014c2d389128e2bb183af1fef1 | 0.94531 | 1.841512 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_ethernet/src/transaction_pkg.vhd | 1 | 4,786 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.support_pkg.all;
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--==========================================================================================
-- t_operation
-- - VVC and BFM operations
--==========================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
TRANSMIT,
RECEIVE,
EXPECT
);
-- Constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
ethernet_frame : t_ethernet_frame;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
ethernet_frame => C_ETHERNET_FRAME_DEFAULT,
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT
);
subtype t_sub_channel is t_channel range RX to TX;
-- Global transaction info trigger signal
type t_ethernet_transaction_trigger_array is array (t_sub_channel range <>, natural range <>) of std_logic;
signal global_ethernet_vvc_transaction_trigger : t_ethernet_transaction_trigger_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => '0'));
-- Shared transaction info variable
type t_ethernet_transaction_group_array is array (t_sub_channel range <>, natural range <>) of t_transaction_group;
shared variable shared_ethernet_vvc_transaction_info : t_ethernet_transaction_group_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => C_TRANSACTION_GROUP_DEFAULT));
end package transaction_pkg;
| mit | f1c935a3212bb1b79858bc951921b720 | 0.515671 | 5.037895 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_fma/flt_fma_renorm_and_round_logic.vhd | 3 | 45,578 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 32000)
`protect data_block
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`protect end_protected
| gpl-2.0 | 0101f1b179131aebde750f714e72ff1a | 0.948594 | 1.822974 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/axi_wrapper_output_fifo.vhd | 3 | 14,518 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-2.0 | 4c738ca3195ac435415a07b2d66640f8 | 0.934771 | 1.876438 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | Lab2/Code/RPNCalc/netgen/par/RPN_toplevel_timesim.vhd | 1 | 446,888 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: RPN_toplevel_timesim.vhd
-- /___/ /\ Timestamp: Thu Feb 18 13:56:24 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -s 4 -pcf RPN_toplevel.pcf -rpw 100 -tpw 0 -ar Structure -tm RPN_toplevel -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim RPN_toplevel.ncd RPN_toplevel_timesim.vhd
-- Device : 3s500efg320-4 (PRODUCTION 1.27 2013-10-13)
-- Input file : RPN_toplevel.ncd
-- Output file : /home/robert/UMD_RISC-16G5/Lab2/Code/RPNCalc/netgen/par/RPN_toplevel_timesim.vhd
-- # of Entities : 1
-- Design Name : RPN_toplevel
-- Xilinx : /home/robert/XilinxISE/14.7/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity RPN_toplevel is
port (
CLK : in STD_LOGIC := 'X';
AN : out STD_LOGIC_VECTOR ( 3 downto 0 );
SEG : out STD_LOGIC_VECTOR ( 7 downto 0 );
BTN : in STD_LOGIC_VECTOR ( 3 downto 0 );
SW : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end RPN_toplevel;
architecture Structure of RPN_toplevel is
signal CLK_BUFGP : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000 : STD_LOGIC;
signal N27_0 : STD_LOGIC;
signal N94_0 : STD_LOGIC;
signal SW_1_IBUF_1740 : STD_LOGIC;
signal SW_0_IBUF_1741 : STD_LOGIC;
signal UXCntl_Unit_VALA_cmp_eq0000_0 : STD_LOGIC;
signal SW_3_IBUF_1743 : STD_LOGIC;
signal SW_2_IBUF_1744 : STD_LOGIC;
signal UXCntl_Unit_VALB_cmp_eq0000_0 : STD_LOGIC;
signal SW_5_IBUF_1748 : STD_LOGIC;
signal SW_4_IBUF_1749 : STD_LOGIC;
signal SW_7_IBUF_1753 : STD_LOGIC;
signal SW_6_IBUF_1754 : STD_LOGIC;
signal Load_Store_Unit_w_en_0 : STD_LOGIC;
signal Arith_Unit_arith_cmp_eq0000_0 : STD_LOGIC;
signal BTN_2_Count_and0000_0 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_cmp_eq0000_0 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal N28 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014201_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000126_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001422_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000146_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001476_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000166_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016157_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000186_0 : STD_LOGIC;
signal BTN_0_OUTPUT_1789 : STD_LOGIC;
signal BTN_3_OUTPUT_1790 : STD_LOGIC;
signal BTN_2_OUTPUT_1791 : STD_LOGIC;
signal BTN_1_OUTPUT_1792 : STD_LOGIC;
signal SSeg_clk240hz_1793 : STD_LOGIC;
signal N31 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001219_1796 : STD_LOGIC;
signal N26_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001222_0 : STD_LOGIC;
signal N25 : STD_LOGIC;
signal N82_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001417_0 : STD_LOGIC;
signal N30 : STD_LOGIC;
signal N23 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001285_1805 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001278_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001257 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012111_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001643_1810 : STD_LOGIC;
signal N88_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001655_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001834_1814 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001828 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001845_0 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal N24 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014256_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001860_0 : STD_LOGIC;
signal N78_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014272_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001866_1823 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001878_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018194 : STD_LOGIC;
signal N80_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012205_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012181_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012253_1829 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012229_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012263_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012196_1833 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012226_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018143_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014224_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016107_1838 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001669_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001686 : STD_LOGIC;
signal N62_0 : STD_LOGIC;
signal BTN_0_Count_and0000_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016175 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018120_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016180_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016263_1853 : STD_LOGIC;
signal N68 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016289_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018124_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018240_1857 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018252_0 : STD_LOGIC;
signal BTN_3_Count_and0000_0 : STD_LOGIC;
signal SSeg_DP_OUT_1865 : STD_LOGIC;
signal N92 : STD_LOGIC;
signal N74 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014135_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014147_0 : STD_LOGIC;
signal N76 : STD_LOGIC;
signal N90_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014346_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012151_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012171 : STD_LOGIC;
signal BTN_1_Count_and0000_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001825_0 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018187_0 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014107 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014312 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal Arith_Unit_Maddsub_arith_cy_1_Q : STD_LOGIC;
signal Arith_Unit_Maddsub_arith_cy_3_Q : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018290 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012292_O : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014384_SW0_O : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016330_O : STD_LOGIC;
signal SSeg_count240hz_15_DXMUX_2085 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_15 : STD_LOGIC;
signal SSeg_count240hz_15_DYMUX_2072 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_14 : STD_LOGIC;
signal SSeg_count240hz_15_CLKINV_2062 : STD_LOGIC;
signal SSeg_count240hz_16_DYMUX_2103 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_16 : STD_LOGIC;
signal SSeg_count240hz_16_CLKINV_2093 : STD_LOGIC;
signal SSeg_count240hz_1_DXMUX_2137 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_1 : STD_LOGIC;
signal SSeg_count240hz_1_DYMUX_2124 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_0 : STD_LOGIC;
signal SSeg_count240hz_1_CLKINV_2114 : STD_LOGIC;
signal SSeg_count240hz_3_DXMUX_2171 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_3 : STD_LOGIC;
signal SSeg_count240hz_3_DYMUX_2158 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_2 : STD_LOGIC;
signal SSeg_count240hz_3_CLKINV_2148 : STD_LOGIC;
signal SSeg_count240hz_5_DXMUX_2205 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_5 : STD_LOGIC;
signal SSeg_count240hz_5_DYMUX_2192 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_4 : STD_LOGIC;
signal SSeg_count240hz_5_CLKINV_2182 : STD_LOGIC;
signal SSeg_count240hz_7_DXMUX_2239 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_7 : STD_LOGIC;
signal SSeg_count240hz_7_DYMUX_2226 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_6 : STD_LOGIC;
signal SSeg_count240hz_7_CLKINV_2216 : STD_LOGIC;
signal SSeg_count240hz_9_DXMUX_2273 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_9 : STD_LOGIC;
signal SSeg_count240hz_9_DYMUX_2260 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_8 : STD_LOGIC;
signal SSeg_count240hz_9_CLKINV_2250 : STD_LOGIC;
signal N27 : STD_LOGIC;
signal N94 : STD_LOGIC;
signal UXCntl_Unit_VALA_1_DXMUX_2313 : STD_LOGIC;
signal UXCntl_Unit_VALA_1_DYMUX_2308 : STD_LOGIC;
signal UXCntl_Unit_VALA_1_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALA_3_DXMUX_2329 : STD_LOGIC;
signal UXCntl_Unit_VALA_3_DYMUX_2324 : STD_LOGIC;
signal UXCntl_Unit_VALA_3_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALB_1_DXMUX_2345 : STD_LOGIC;
signal UXCntl_Unit_VALB_1_DYMUX_2340 : STD_LOGIC;
signal UXCntl_Unit_VALB_1_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALA_5_DXMUX_2361 : STD_LOGIC;
signal UXCntl_Unit_VALA_5_DYMUX_2356 : STD_LOGIC;
signal UXCntl_Unit_VALA_5_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALB_3_DXMUX_2377 : STD_LOGIC;
signal UXCntl_Unit_VALB_3_DYMUX_2372 : STD_LOGIC;
signal UXCntl_Unit_VALB_3_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALA_7_DXMUX_2393 : STD_LOGIC;
signal UXCntl_Unit_VALA_7_DYMUX_2388 : STD_LOGIC;
signal UXCntl_Unit_VALA_7_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALB_5_DXMUX_2409 : STD_LOGIC;
signal UXCntl_Unit_VALB_5_DYMUX_2404 : STD_LOGIC;
signal UXCntl_Unit_VALB_5_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_VALB_7_DXMUX_2425 : STD_LOGIC;
signal UXCntl_Unit_VALB_7_DYMUX_2420 : STD_LOGIC;
signal UXCntl_Unit_VALB_7_CLKINVNOT : STD_LOGIC;
signal Load_Store_Unit_w_en : STD_LOGIC;
signal Arith_Unit_arith_cmp_eq0000 : STD_LOGIC;
signal SEG_0_OBUF_2474 : STD_LOGIC;
signal SEG_1_OBUF_2467 : STD_LOGIC;
signal BTN_2_OUTPUT_not0001 : STD_LOGIC;
signal BTN_2_Count_and0000 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_1_DXMUX_2513 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_1_DYMUX_2508 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_1_CLKINVNOT : STD_LOGIC;
signal UXCntl_Unit_OPCODE_3_DXMUX_2529 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_3_DYMUX_2524 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_3_CLKINVNOT : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014201_2554 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000126_2547 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001422_2578 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000146_2570 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001476_2602 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000166_2594 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016157_2626 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000186_2619 : STD_LOGIC;
signal UXCntl_Unit_OPCODE_cmp_eq0000 : STD_LOGIC;
signal UXCntl_Unit_VALA_cmp_eq0000 : STD_LOGIC;
signal SSeg_clk240hz_DYMUX_2660 : STD_LOGIC;
signal SSeg_clk240hz_CLKINV_2658 : STD_LOGIC;
signal SSeg_clk240hz_CEINV_2657 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001222_2686 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001219_pack_1 : STD_LOGIC;
signal N82 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001417_2702 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012111_2734 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001285_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001655_2758 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001643_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001845_2782 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001834_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014256_2806 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001860_2799 : STD_LOGIC;
signal N78 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014272 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001878_2854 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001866_pack_1 : STD_LOGIC;
signal N80 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012205_2871 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012263_2902 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012253_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012229_2926 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012196_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018143_2950 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014224_2943 : STD_LOGIC;
signal N62 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016107_pack_1 : STD_LOGIC;
signal BTN_0_Count_and0000 : STD_LOGIC;
signal BTN_0_OUTPUT_not0001 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018120_3022 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016180_3013 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016289_3046 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016263_pack_1 : STD_LOGIC;
signal N26 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018124_3062 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018252_3094 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018240_pack_1 : STD_LOGIC;
signal BTN_3_OUTPUT_not0001 : STD_LOGIC;
signal BTN_3_Count_and0000 : STD_LOGIC;
signal SSeg_DP_OUT_DYMUX_3126 : STD_LOGIC;
signal SSeg_DP_OUT_BYINV_3125 : STD_LOGIC;
signal SSeg_DP_OUT_CLKINV_3124 : STD_LOGIC;
signal N88 : STD_LOGIC;
signal N92_pack_1 : STD_LOGIC;
signal Load_Store_Unit_reg_1_DXMUX_3169 : STD_LOGIC;
signal Load_Store_Unit_reg_1_DYMUX_3163 : STD_LOGIC;
signal Load_Store_Unit_reg_1_CLKINV_3161 : STD_LOGIC;
signal Load_Store_Unit_reg_1_CEINV_3160 : STD_LOGIC;
signal Load_Store_Unit_reg_3_DXMUX_3189 : STD_LOGIC;
signal Load_Store_Unit_reg_3_DYMUX_3183 : STD_LOGIC;
signal Load_Store_Unit_reg_3_CLKINV_3181 : STD_LOGIC;
signal Load_Store_Unit_reg_3_CEINV_3180 : STD_LOGIC;
signal Load_Store_Unit_reg_5_DXMUX_3209 : STD_LOGIC;
signal Load_Store_Unit_reg_5_DYMUX_3203 : STD_LOGIC;
signal Load_Store_Unit_reg_5_CLKINV_3201 : STD_LOGIC;
signal Load_Store_Unit_reg_5_CEINV_3200 : STD_LOGIC;
signal Load_Store_Unit_reg_7_DXMUX_3229 : STD_LOGIC;
signal Load_Store_Unit_reg_7_DYMUX_3223 : STD_LOGIC;
signal Load_Store_Unit_reg_7_CLKINV_3221 : STD_LOGIC;
signal Load_Store_Unit_reg_7_CEINV_3220 : STD_LOGIC;
signal BTN_0_D_STATE_1_DXMUX_3246 : STD_LOGIC;
signal BTN_0_D_STATE_1_DYMUX_3241 : STD_LOGIC;
signal BTN_0_D_STATE_1_CLKINV_3239 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014147_3271 : STD_LOGIC;
signal N74_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014346_3295 : STD_LOGIC;
signal N76_pack_1 : STD_LOGIC;
signal SEG_3_OBUF_3319 : STD_LOGIC;
signal SEG_2_OBUF_3312 : STD_LOGIC;
signal SEG_5_OBUF_3343 : STD_LOGIC;
signal SEG_4_OBUF_3336 : STD_LOGIC;
signal SEG_6_OBUF_3355 : STD_LOGIC;
signal BTN_1_D_STATE_1_DXMUX_3370 : STD_LOGIC;
signal BTN_1_D_STATE_1_DYMUX_3365 : STD_LOGIC;
signal BTN_1_D_STATE_1_CLKINV_3363 : STD_LOGIC;
signal UXCntl_Unit_VALB_cmp_eq0000 : STD_LOGIC;
signal BTN_2_D_STATE_1_DXMUX_3398 : STD_LOGIC;
signal BTN_2_D_STATE_1_DYMUX_3393 : STD_LOGIC;
signal BTN_2_D_STATE_1_CLKINV_3391 : STD_LOGIC;
signal BTN_3_D_STATE_1_DXMUX_3414 : STD_LOGIC;
signal BTN_3_D_STATE_1_DYMUX_3409 : STD_LOGIC;
signal BTN_3_D_STATE_1_CLKINV_3407 : STD_LOGIC;
signal SSeg_pos_0_DXMUX_3439 : STD_LOGIC;
signal SSeg_pos_0_DYMUX_3434 : STD_LOGIC;
signal SSeg_Mcount_pos1 : STD_LOGIC;
signal SSeg_pos_0_CLKINV_3424 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012181_3464 : STD_LOGIC;
signal N31_pack_1 : STD_LOGIC;
signal BTN_1_OUTPUT_not0001 : STD_LOGIC;
signal BTN_1_Count_and0000 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012226_3512 : STD_LOGIC;
signal N25_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001825_3536 : STD_LOGIC;
signal N22_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001669_3560 : STD_LOGIC;
signal N24_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018187_3584 : STD_LOGIC;
signal N12_pack_2 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014135_3608 : STD_LOGIC;
signal N23_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012151_3632 : STD_LOGIC;
signal N28_pack_1 : STD_LOGIC;
signal N90 : STD_LOGIC;
signal N30_pack_1 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001278_3680 : STD_LOGIC;
signal N11_pack_2 : STD_LOGIC;
signal BTN_0_OUTPUT_DYMUX_3690 : STD_LOGIC;
signal BTN_0_OUTPUT_CLKINV_3688 : STD_LOGIC;
signal BTN_0_OUTPUT_CEINV_3687 : STD_LOGIC;
signal BTN_1_Count_0_DXMUX_3743 : STD_LOGIC;
signal BTN_1_Count_0_XORF_3741 : STD_LOGIC;
signal BTN_1_Count_0_LOGIC_ONE_3740 : STD_LOGIC;
signal BTN_1_Count_0_CYINIT_3739 : STD_LOGIC;
signal BTN_1_Count_0_CYSELF_3730 : STD_LOGIC;
signal BTN_1_Count_0_BXINV_3728 : STD_LOGIC;
signal BTN_1_Count_0_DYMUX_3722 : STD_LOGIC;
signal BTN_1_Count_0_XORG_3720 : STD_LOGIC;
signal BTN_1_Count_0_CYMUXG_3719 : STD_LOGIC;
signal BTN_1_Count_0_LOGIC_ZERO_3717 : STD_LOGIC;
signal BTN_1_Count_0_CYSELG_3708 : STD_LOGIC;
signal BTN_1_Count_0_G : STD_LOGIC;
signal BTN_1_Count_0_SRINV_3706 : STD_LOGIC;
signal BTN_1_Count_0_CLKINV_3705 : STD_LOGIC;
signal BTN_1_Count_0_CEINVNOT : STD_LOGIC;
signal BTN_1_OUTPUT_DYMUX_3756 : STD_LOGIC;
signal BTN_1_OUTPUT_CLKINV_3754 : STD_LOGIC;
signal BTN_1_OUTPUT_CEINV_3753 : STD_LOGIC;
signal BTN_1_Count_2_DXMUX_3811 : STD_LOGIC;
signal BTN_1_Count_2_XORF_3809 : STD_LOGIC;
signal BTN_1_Count_2_CYINIT_3808 : STD_LOGIC;
signal BTN_1_Count_2_F : STD_LOGIC;
signal BTN_1_Count_2_DYMUX_3793 : STD_LOGIC;
signal BTN_1_Count_2_XORG_3791 : STD_LOGIC;
signal BTN_1_Count_2_CYSELF_3789 : STD_LOGIC;
signal BTN_1_Count_2_CYMUXFAST_3788 : STD_LOGIC;
signal BTN_1_Count_2_CYAND_3787 : STD_LOGIC;
signal BTN_1_Count_2_FASTCARRY_3786 : STD_LOGIC;
signal BTN_1_Count_2_CYMUXG2_3785 : STD_LOGIC;
signal BTN_1_Count_2_CYMUXF2_3784 : STD_LOGIC;
signal BTN_1_Count_2_LOGIC_ZERO_3783 : STD_LOGIC;
signal BTN_1_Count_2_CYSELG_3774 : STD_LOGIC;
signal BTN_1_Count_2_G : STD_LOGIC;
signal BTN_1_Count_2_SRINV_3772 : STD_LOGIC;
signal BTN_1_Count_2_CLKINV_3771 : STD_LOGIC;
signal BTN_1_Count_2_CEINVNOT : STD_LOGIC;
signal BTN_2_OUTPUT_DYMUX_3824 : STD_LOGIC;
signal BTN_2_OUTPUT_CLKINV_3822 : STD_LOGIC;
signal BTN_2_OUTPUT_CEINV_3821 : STD_LOGIC;
signal BTN_1_Count_4_DXMUX_3879 : STD_LOGIC;
signal BTN_1_Count_4_XORF_3877 : STD_LOGIC;
signal BTN_1_Count_4_CYINIT_3876 : STD_LOGIC;
signal BTN_1_Count_4_F : STD_LOGIC;
signal BTN_1_Count_4_DYMUX_3861 : STD_LOGIC;
signal BTN_1_Count_4_XORG_3859 : STD_LOGIC;
signal BTN_1_Count_4_CYSELF_3857 : STD_LOGIC;
signal BTN_1_Count_4_CYMUXFAST_3856 : STD_LOGIC;
signal BTN_1_Count_4_CYAND_3855 : STD_LOGIC;
signal BTN_1_Count_4_FASTCARRY_3854 : STD_LOGIC;
signal BTN_1_Count_4_CYMUXG2_3853 : STD_LOGIC;
signal BTN_1_Count_4_CYMUXF2_3852 : STD_LOGIC;
signal BTN_1_Count_4_LOGIC_ZERO_3851 : STD_LOGIC;
signal BTN_1_Count_4_CYSELG_3842 : STD_LOGIC;
signal BTN_1_Count_4_G : STD_LOGIC;
signal BTN_1_Count_4_SRINV_3840 : STD_LOGIC;
signal BTN_1_Count_4_CLKINV_3839 : STD_LOGIC;
signal BTN_1_Count_4_CEINVNOT : STD_LOGIC;
signal BTN_3_OUTPUT_DYMUX_3892 : STD_LOGIC;
signal BTN_3_OUTPUT_CLKINV_3890 : STD_LOGIC;
signal BTN_3_OUTPUT_CEINV_3889 : STD_LOGIC;
signal BTN_1_Count_6_DXMUX_3947 : STD_LOGIC;
signal BTN_1_Count_6_XORF_3945 : STD_LOGIC;
signal BTN_1_Count_6_CYINIT_3944 : STD_LOGIC;
signal BTN_1_Count_6_F : STD_LOGIC;
signal BTN_1_Count_6_DYMUX_3929 : STD_LOGIC;
signal BTN_1_Count_6_XORG_3927 : STD_LOGIC;
signal BTN_1_Count_6_CYSELF_3925 : STD_LOGIC;
signal BTN_1_Count_6_CYMUXFAST_3924 : STD_LOGIC;
signal BTN_1_Count_6_CYAND_3923 : STD_LOGIC;
signal BTN_1_Count_6_FASTCARRY_3922 : STD_LOGIC;
signal BTN_1_Count_6_CYMUXG2_3921 : STD_LOGIC;
signal BTN_1_Count_6_CYMUXF2_3920 : STD_LOGIC;
signal BTN_1_Count_6_LOGIC_ZERO_3919 : STD_LOGIC;
signal BTN_1_Count_6_CYSELG_3910 : STD_LOGIC;
signal BTN_1_Count_6_G : STD_LOGIC;
signal BTN_1_Count_6_SRINV_3908 : STD_LOGIC;
signal BTN_1_Count_6_CLKINV_3907 : STD_LOGIC;
signal BTN_1_Count_6_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_8_DXMUX_4003 : STD_LOGIC;
signal BTN_1_Count_8_XORF_4001 : STD_LOGIC;
signal BTN_1_Count_8_CYINIT_4000 : STD_LOGIC;
signal BTN_1_Count_8_F : STD_LOGIC;
signal BTN_1_Count_8_DYMUX_3985 : STD_LOGIC;
signal BTN_1_Count_8_XORG_3983 : STD_LOGIC;
signal BTN_1_Count_8_CYSELF_3981 : STD_LOGIC;
signal BTN_1_Count_8_CYMUXFAST_3980 : STD_LOGIC;
signal BTN_1_Count_8_CYAND_3979 : STD_LOGIC;
signal BTN_1_Count_8_FASTCARRY_3978 : STD_LOGIC;
signal BTN_1_Count_8_CYMUXG2_3977 : STD_LOGIC;
signal BTN_1_Count_8_CYMUXF2_3976 : STD_LOGIC;
signal BTN_1_Count_8_LOGIC_ZERO_3975 : STD_LOGIC;
signal BTN_1_Count_8_CYSELG_3966 : STD_LOGIC;
signal BTN_1_Count_8_G : STD_LOGIC;
signal BTN_1_Count_8_SRINV_3964 : STD_LOGIC;
signal BTN_1_Count_8_CLKINV_3963 : STD_LOGIC;
signal BTN_1_Count_8_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_10_DXMUX_4059 : STD_LOGIC;
signal BTN_1_Count_10_XORF_4057 : STD_LOGIC;
signal BTN_1_Count_10_CYINIT_4056 : STD_LOGIC;
signal BTN_1_Count_10_F : STD_LOGIC;
signal BTN_1_Count_10_DYMUX_4041 : STD_LOGIC;
signal BTN_1_Count_10_XORG_4039 : STD_LOGIC;
signal BTN_1_Count_10_CYSELF_4037 : STD_LOGIC;
signal BTN_1_Count_10_CYMUXFAST_4036 : STD_LOGIC;
signal BTN_1_Count_10_CYAND_4035 : STD_LOGIC;
signal BTN_1_Count_10_FASTCARRY_4034 : STD_LOGIC;
signal BTN_1_Count_10_CYMUXG2_4033 : STD_LOGIC;
signal BTN_1_Count_10_CYMUXF2_4032 : STD_LOGIC;
signal BTN_1_Count_10_LOGIC_ZERO_4031 : STD_LOGIC;
signal BTN_1_Count_10_CYSELG_4022 : STD_LOGIC;
signal BTN_1_Count_10_G : STD_LOGIC;
signal BTN_1_Count_10_SRINV_4020 : STD_LOGIC;
signal BTN_1_Count_10_CLKINV_4019 : STD_LOGIC;
signal BTN_1_Count_10_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_12_DXMUX_4115 : STD_LOGIC;
signal BTN_1_Count_12_XORF_4113 : STD_LOGIC;
signal BTN_1_Count_12_CYINIT_4112 : STD_LOGIC;
signal BTN_1_Count_12_F : STD_LOGIC;
signal BTN_1_Count_12_DYMUX_4097 : STD_LOGIC;
signal BTN_1_Count_12_XORG_4095 : STD_LOGIC;
signal BTN_1_Count_12_CYSELF_4093 : STD_LOGIC;
signal BTN_1_Count_12_CYMUXFAST_4092 : STD_LOGIC;
signal BTN_1_Count_12_CYAND_4091 : STD_LOGIC;
signal BTN_1_Count_12_FASTCARRY_4090 : STD_LOGIC;
signal BTN_1_Count_12_CYMUXG2_4089 : STD_LOGIC;
signal BTN_1_Count_12_CYMUXF2_4088 : STD_LOGIC;
signal BTN_1_Count_12_LOGIC_ZERO_4087 : STD_LOGIC;
signal BTN_1_Count_12_CYSELG_4078 : STD_LOGIC;
signal BTN_1_Count_12_G : STD_LOGIC;
signal BTN_1_Count_12_SRINV_4076 : STD_LOGIC;
signal BTN_1_Count_12_CLKINV_4075 : STD_LOGIC;
signal BTN_1_Count_12_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_14_DXMUX_4171 : STD_LOGIC;
signal BTN_1_Count_14_XORF_4169 : STD_LOGIC;
signal BTN_1_Count_14_CYINIT_4168 : STD_LOGIC;
signal BTN_1_Count_14_F : STD_LOGIC;
signal BTN_1_Count_14_DYMUX_4153 : STD_LOGIC;
signal BTN_1_Count_14_XORG_4151 : STD_LOGIC;
signal BTN_1_Count_14_CYSELF_4149 : STD_LOGIC;
signal BTN_1_Count_14_CYMUXFAST_4148 : STD_LOGIC;
signal BTN_1_Count_14_CYAND_4147 : STD_LOGIC;
signal BTN_1_Count_14_FASTCARRY_4146 : STD_LOGIC;
signal BTN_1_Count_14_CYMUXG2_4145 : STD_LOGIC;
signal BTN_1_Count_14_CYMUXF2_4144 : STD_LOGIC;
signal BTN_1_Count_14_LOGIC_ZERO_4143 : STD_LOGIC;
signal BTN_1_Count_14_CYSELG_4134 : STD_LOGIC;
signal BTN_1_Count_14_G : STD_LOGIC;
signal BTN_1_Count_14_SRINV_4132 : STD_LOGIC;
signal BTN_1_Count_14_CLKINV_4131 : STD_LOGIC;
signal BTN_1_Count_14_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_16_DXMUX_4227 : STD_LOGIC;
signal BTN_1_Count_16_XORF_4225 : STD_LOGIC;
signal BTN_1_Count_16_CYINIT_4224 : STD_LOGIC;
signal BTN_1_Count_16_F : STD_LOGIC;
signal BTN_1_Count_16_DYMUX_4209 : STD_LOGIC;
signal BTN_1_Count_16_XORG_4207 : STD_LOGIC;
signal BTN_1_Count_16_CYSELF_4205 : STD_LOGIC;
signal BTN_1_Count_16_CYMUXFAST_4204 : STD_LOGIC;
signal BTN_1_Count_16_CYAND_4203 : STD_LOGIC;
signal BTN_1_Count_16_FASTCARRY_4202 : STD_LOGIC;
signal BTN_1_Count_16_CYMUXG2_4201 : STD_LOGIC;
signal BTN_1_Count_16_CYMUXF2_4200 : STD_LOGIC;
signal BTN_1_Count_16_LOGIC_ZERO_4199 : STD_LOGIC;
signal BTN_1_Count_16_CYSELG_4190 : STD_LOGIC;
signal BTN_1_Count_16_G : STD_LOGIC;
signal BTN_1_Count_16_SRINV_4188 : STD_LOGIC;
signal BTN_1_Count_16_CLKINV_4187 : STD_LOGIC;
signal BTN_1_Count_16_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_18_DXMUX_4283 : STD_LOGIC;
signal BTN_1_Count_18_XORF_4281 : STD_LOGIC;
signal BTN_1_Count_18_CYINIT_4280 : STD_LOGIC;
signal BTN_1_Count_18_F : STD_LOGIC;
signal BTN_1_Count_18_DYMUX_4265 : STD_LOGIC;
signal BTN_1_Count_18_XORG_4263 : STD_LOGIC;
signal BTN_1_Count_18_CYSELF_4261 : STD_LOGIC;
signal BTN_1_Count_18_CYMUXFAST_4260 : STD_LOGIC;
signal BTN_1_Count_18_CYAND_4259 : STD_LOGIC;
signal BTN_1_Count_18_FASTCARRY_4258 : STD_LOGIC;
signal BTN_1_Count_18_CYMUXG2_4257 : STD_LOGIC;
signal BTN_1_Count_18_CYMUXF2_4256 : STD_LOGIC;
signal BTN_1_Count_18_LOGIC_ZERO_4255 : STD_LOGIC;
signal BTN_1_Count_18_CYSELG_4246 : STD_LOGIC;
signal BTN_1_Count_18_G : STD_LOGIC;
signal BTN_1_Count_18_SRINV_4244 : STD_LOGIC;
signal BTN_1_Count_18_CLKINV_4243 : STD_LOGIC;
signal BTN_1_Count_18_CEINVNOT : STD_LOGIC;
signal BTN_1_Count_20_DXMUX_4310 : STD_LOGIC;
signal BTN_1_Count_20_XORF_4308 : STD_LOGIC;
signal BTN_1_Count_20_CYINIT_4307 : STD_LOGIC;
signal BTN_1_Count_20_rt_4305 : STD_LOGIC;
signal BTN_1_Count_20_SRINV_4297 : STD_LOGIC;
signal BTN_1_Count_20_CLKINV_4296 : STD_LOGIC;
signal BTN_1_Count_20_CEINVNOT : STD_LOGIC;
signal arith_0_XORF_4350 : STD_LOGIC;
signal arith_0_CYINIT_4349 : STD_LOGIC;
signal arith_0_CY0F_4348 : STD_LOGIC;
signal arith_0_CYSELF_4341 : STD_LOGIC;
signal arith_0_XORG_4337 : STD_LOGIC;
signal arith_0_CYMUXG_4336 : STD_LOGIC;
signal Arith_Unit_Maddsub_arith_cy_0_Q : STD_LOGIC;
signal arith_0_CY0G_4334 : STD_LOGIC;
signal arith_0_CYSELG_4327 : STD_LOGIC;
signal arith_2_XORF_4389 : STD_LOGIC;
signal arith_2_CYINIT_4388 : STD_LOGIC;
signal arith_2_CY0F_4387 : STD_LOGIC;
signal arith_2_XORG_4378 : STD_LOGIC;
signal Arith_Unit_Maddsub_arith_cy_2_Q : STD_LOGIC;
signal arith_2_CYSELF_4376 : STD_LOGIC;
signal arith_2_CYMUXFAST_4375 : STD_LOGIC;
signal arith_2_CYAND_4374 : STD_LOGIC;
signal arith_2_FASTCARRY_4373 : STD_LOGIC;
signal arith_2_CYMUXG2_4372 : STD_LOGIC;
signal arith_2_CYMUXF2_4371 : STD_LOGIC;
signal arith_2_CY0G_4370 : STD_LOGIC;
signal arith_2_CYSELG_4363 : STD_LOGIC;
signal arith_4_XORF_4428 : STD_LOGIC;
signal arith_4_CYINIT_4427 : STD_LOGIC;
signal arith_4_CY0F_4426 : STD_LOGIC;
signal arith_4_XORG_4417 : STD_LOGIC;
signal Arith_Unit_Maddsub_arith_cy_4_Q : STD_LOGIC;
signal arith_4_CYSELF_4415 : STD_LOGIC;
signal arith_4_CYMUXFAST_4414 : STD_LOGIC;
signal arith_4_CYAND_4413 : STD_LOGIC;
signal arith_4_FASTCARRY_4412 : STD_LOGIC;
signal arith_4_CYMUXG2_4411 : STD_LOGIC;
signal arith_4_CYMUXF2_4410 : STD_LOGIC;
signal arith_4_CY0G_4409 : STD_LOGIC;
signal arith_4_CYSELG_4402 : STD_LOGIC;
signal arith_6_XORF_4459 : STD_LOGIC;
signal arith_6_CYINIT_4458 : STD_LOGIC;
signal arith_6_CY0F_4457 : STD_LOGIC;
signal arith_6_CYSELF_4450 : STD_LOGIC;
signal arith_6_XORG_4447 : STD_LOGIC;
signal Arith_Unit_Maddsub_arith_cy_6_Q : STD_LOGIC;
signal BTN_0_Count_0_DXMUX_4509 : STD_LOGIC;
signal BTN_0_Count_0_XORF_4507 : STD_LOGIC;
signal BTN_0_Count_0_LOGIC_ONE_4506 : STD_LOGIC;
signal BTN_0_Count_0_CYINIT_4505 : STD_LOGIC;
signal BTN_0_Count_0_CYSELF_4496 : STD_LOGIC;
signal BTN_0_Count_0_BXINV_4494 : STD_LOGIC;
signal BTN_0_Count_0_DYMUX_4488 : STD_LOGIC;
signal BTN_0_Count_0_XORG_4486 : STD_LOGIC;
signal BTN_0_Count_0_CYMUXG_4485 : STD_LOGIC;
signal BTN_0_Count_0_LOGIC_ZERO_4483 : STD_LOGIC;
signal BTN_0_Count_0_CYSELG_4474 : STD_LOGIC;
signal BTN_0_Count_0_G : STD_LOGIC;
signal BTN_0_Count_0_SRINV_4472 : STD_LOGIC;
signal BTN_0_Count_0_CLKINV_4471 : STD_LOGIC;
signal BTN_0_Count_0_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_2_DXMUX_4565 : STD_LOGIC;
signal BTN_0_Count_2_XORF_4563 : STD_LOGIC;
signal BTN_0_Count_2_CYINIT_4562 : STD_LOGIC;
signal BTN_0_Count_2_F : STD_LOGIC;
signal BTN_0_Count_2_DYMUX_4547 : STD_LOGIC;
signal BTN_0_Count_2_XORG_4545 : STD_LOGIC;
signal BTN_0_Count_2_CYSELF_4543 : STD_LOGIC;
signal BTN_0_Count_2_CYMUXFAST_4542 : STD_LOGIC;
signal BTN_0_Count_2_CYAND_4541 : STD_LOGIC;
signal BTN_0_Count_2_FASTCARRY_4540 : STD_LOGIC;
signal BTN_0_Count_2_CYMUXG2_4539 : STD_LOGIC;
signal BTN_0_Count_2_CYMUXF2_4538 : STD_LOGIC;
signal BTN_0_Count_2_LOGIC_ZERO_4537 : STD_LOGIC;
signal BTN_0_Count_2_CYSELG_4528 : STD_LOGIC;
signal BTN_0_Count_2_G : STD_LOGIC;
signal BTN_0_Count_2_SRINV_4526 : STD_LOGIC;
signal BTN_0_Count_2_CLKINV_4525 : STD_LOGIC;
signal BTN_0_Count_2_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_4_DXMUX_4621 : STD_LOGIC;
signal BTN_0_Count_4_XORF_4619 : STD_LOGIC;
signal BTN_0_Count_4_CYINIT_4618 : STD_LOGIC;
signal BTN_0_Count_4_F : STD_LOGIC;
signal BTN_0_Count_4_DYMUX_4603 : STD_LOGIC;
signal BTN_0_Count_4_XORG_4601 : STD_LOGIC;
signal BTN_0_Count_4_CYSELF_4599 : STD_LOGIC;
signal BTN_0_Count_4_CYMUXFAST_4598 : STD_LOGIC;
signal BTN_0_Count_4_CYAND_4597 : STD_LOGIC;
signal BTN_0_Count_4_FASTCARRY_4596 : STD_LOGIC;
signal BTN_0_Count_4_CYMUXG2_4595 : STD_LOGIC;
signal BTN_0_Count_4_CYMUXF2_4594 : STD_LOGIC;
signal BTN_0_Count_4_LOGIC_ZERO_4593 : STD_LOGIC;
signal BTN_0_Count_4_CYSELG_4584 : STD_LOGIC;
signal BTN_0_Count_4_G : STD_LOGIC;
signal BTN_0_Count_4_SRINV_4582 : STD_LOGIC;
signal BTN_0_Count_4_CLKINV_4581 : STD_LOGIC;
signal BTN_0_Count_4_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_6_DXMUX_4677 : STD_LOGIC;
signal BTN_0_Count_6_XORF_4675 : STD_LOGIC;
signal BTN_0_Count_6_CYINIT_4674 : STD_LOGIC;
signal BTN_0_Count_6_F : STD_LOGIC;
signal BTN_0_Count_6_DYMUX_4659 : STD_LOGIC;
signal BTN_0_Count_6_XORG_4657 : STD_LOGIC;
signal BTN_0_Count_6_CYSELF_4655 : STD_LOGIC;
signal BTN_0_Count_6_CYMUXFAST_4654 : STD_LOGIC;
signal BTN_0_Count_6_CYAND_4653 : STD_LOGIC;
signal BTN_0_Count_6_FASTCARRY_4652 : STD_LOGIC;
signal BTN_0_Count_6_CYMUXG2_4651 : STD_LOGIC;
signal BTN_0_Count_6_CYMUXF2_4650 : STD_LOGIC;
signal BTN_0_Count_6_LOGIC_ZERO_4649 : STD_LOGIC;
signal BTN_0_Count_6_CYSELG_4640 : STD_LOGIC;
signal BTN_0_Count_6_G : STD_LOGIC;
signal BTN_0_Count_6_SRINV_4638 : STD_LOGIC;
signal BTN_0_Count_6_CLKINV_4637 : STD_LOGIC;
signal BTN_0_Count_6_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_8_DXMUX_4733 : STD_LOGIC;
signal BTN_0_Count_8_XORF_4731 : STD_LOGIC;
signal BTN_0_Count_8_CYINIT_4730 : STD_LOGIC;
signal BTN_0_Count_8_F : STD_LOGIC;
signal BTN_0_Count_8_DYMUX_4715 : STD_LOGIC;
signal BTN_0_Count_8_XORG_4713 : STD_LOGIC;
signal BTN_0_Count_8_CYSELF_4711 : STD_LOGIC;
signal BTN_0_Count_8_CYMUXFAST_4710 : STD_LOGIC;
signal BTN_0_Count_8_CYAND_4709 : STD_LOGIC;
signal BTN_0_Count_8_FASTCARRY_4708 : STD_LOGIC;
signal BTN_0_Count_8_CYMUXG2_4707 : STD_LOGIC;
signal BTN_0_Count_8_CYMUXF2_4706 : STD_LOGIC;
signal BTN_0_Count_8_LOGIC_ZERO_4705 : STD_LOGIC;
signal BTN_0_Count_8_CYSELG_4696 : STD_LOGIC;
signal BTN_0_Count_8_G : STD_LOGIC;
signal BTN_0_Count_8_SRINV_4694 : STD_LOGIC;
signal BTN_0_Count_8_CLKINV_4693 : STD_LOGIC;
signal BTN_0_Count_8_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_10_DXMUX_4789 : STD_LOGIC;
signal BTN_0_Count_10_XORF_4787 : STD_LOGIC;
signal BTN_0_Count_10_CYINIT_4786 : STD_LOGIC;
signal BTN_0_Count_10_F : STD_LOGIC;
signal BTN_0_Count_10_DYMUX_4771 : STD_LOGIC;
signal BTN_0_Count_10_XORG_4769 : STD_LOGIC;
signal BTN_0_Count_10_CYSELF_4767 : STD_LOGIC;
signal BTN_0_Count_10_CYMUXFAST_4766 : STD_LOGIC;
signal BTN_0_Count_10_CYAND_4765 : STD_LOGIC;
signal BTN_0_Count_10_FASTCARRY_4764 : STD_LOGIC;
signal BTN_0_Count_10_CYMUXG2_4763 : STD_LOGIC;
signal BTN_0_Count_10_CYMUXF2_4762 : STD_LOGIC;
signal BTN_0_Count_10_LOGIC_ZERO_4761 : STD_LOGIC;
signal BTN_0_Count_10_CYSELG_4752 : STD_LOGIC;
signal BTN_0_Count_10_G : STD_LOGIC;
signal BTN_0_Count_10_SRINV_4750 : STD_LOGIC;
signal BTN_0_Count_10_CLKINV_4749 : STD_LOGIC;
signal BTN_0_Count_10_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_12_DXMUX_4845 : STD_LOGIC;
signal BTN_0_Count_12_XORF_4843 : STD_LOGIC;
signal BTN_0_Count_12_CYINIT_4842 : STD_LOGIC;
signal BTN_0_Count_12_F : STD_LOGIC;
signal BTN_0_Count_12_DYMUX_4827 : STD_LOGIC;
signal BTN_0_Count_12_XORG_4825 : STD_LOGIC;
signal BTN_0_Count_12_CYSELF_4823 : STD_LOGIC;
signal BTN_0_Count_12_CYMUXFAST_4822 : STD_LOGIC;
signal BTN_0_Count_12_CYAND_4821 : STD_LOGIC;
signal BTN_0_Count_12_FASTCARRY_4820 : STD_LOGIC;
signal BTN_0_Count_12_CYMUXG2_4819 : STD_LOGIC;
signal BTN_0_Count_12_CYMUXF2_4818 : STD_LOGIC;
signal BTN_0_Count_12_LOGIC_ZERO_4817 : STD_LOGIC;
signal BTN_0_Count_12_CYSELG_4808 : STD_LOGIC;
signal BTN_0_Count_12_G : STD_LOGIC;
signal BTN_0_Count_12_SRINV_4806 : STD_LOGIC;
signal BTN_0_Count_12_CLKINV_4805 : STD_LOGIC;
signal BTN_0_Count_12_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_14_DXMUX_4901 : STD_LOGIC;
signal BTN_0_Count_14_XORF_4899 : STD_LOGIC;
signal BTN_0_Count_14_CYINIT_4898 : STD_LOGIC;
signal BTN_0_Count_14_F : STD_LOGIC;
signal BTN_0_Count_14_DYMUX_4883 : STD_LOGIC;
signal BTN_0_Count_14_XORG_4881 : STD_LOGIC;
signal BTN_0_Count_14_CYSELF_4879 : STD_LOGIC;
signal BTN_0_Count_14_CYMUXFAST_4878 : STD_LOGIC;
signal BTN_0_Count_14_CYAND_4877 : STD_LOGIC;
signal BTN_0_Count_14_FASTCARRY_4876 : STD_LOGIC;
signal BTN_0_Count_14_CYMUXG2_4875 : STD_LOGIC;
signal BTN_0_Count_14_CYMUXF2_4874 : STD_LOGIC;
signal BTN_0_Count_14_LOGIC_ZERO_4873 : STD_LOGIC;
signal BTN_0_Count_14_CYSELG_4864 : STD_LOGIC;
signal BTN_0_Count_14_G : STD_LOGIC;
signal BTN_0_Count_14_SRINV_4862 : STD_LOGIC;
signal BTN_0_Count_14_CLKINV_4861 : STD_LOGIC;
signal BTN_0_Count_14_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_16_DXMUX_4957 : STD_LOGIC;
signal BTN_0_Count_16_XORF_4955 : STD_LOGIC;
signal BTN_0_Count_16_CYINIT_4954 : STD_LOGIC;
signal BTN_0_Count_16_F : STD_LOGIC;
signal BTN_0_Count_16_DYMUX_4939 : STD_LOGIC;
signal BTN_0_Count_16_XORG_4937 : STD_LOGIC;
signal BTN_0_Count_16_CYSELF_4935 : STD_LOGIC;
signal BTN_0_Count_16_CYMUXFAST_4934 : STD_LOGIC;
signal BTN_0_Count_16_CYAND_4933 : STD_LOGIC;
signal BTN_0_Count_16_FASTCARRY_4932 : STD_LOGIC;
signal BTN_0_Count_16_CYMUXG2_4931 : STD_LOGIC;
signal BTN_0_Count_16_CYMUXF2_4930 : STD_LOGIC;
signal BTN_0_Count_16_LOGIC_ZERO_4929 : STD_LOGIC;
signal BTN_0_Count_16_CYSELG_4920 : STD_LOGIC;
signal BTN_0_Count_16_G : STD_LOGIC;
signal BTN_0_Count_16_SRINV_4918 : STD_LOGIC;
signal BTN_0_Count_16_CLKINV_4917 : STD_LOGIC;
signal BTN_0_Count_16_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_18_DXMUX_5013 : STD_LOGIC;
signal BTN_0_Count_18_XORF_5011 : STD_LOGIC;
signal BTN_0_Count_18_CYINIT_5010 : STD_LOGIC;
signal BTN_0_Count_18_F : STD_LOGIC;
signal BTN_0_Count_18_DYMUX_4995 : STD_LOGIC;
signal BTN_0_Count_18_XORG_4993 : STD_LOGIC;
signal BTN_0_Count_18_CYSELF_4991 : STD_LOGIC;
signal BTN_0_Count_18_CYMUXFAST_4990 : STD_LOGIC;
signal BTN_0_Count_18_CYAND_4989 : STD_LOGIC;
signal BTN_0_Count_18_FASTCARRY_4988 : STD_LOGIC;
signal BTN_0_Count_18_CYMUXG2_4987 : STD_LOGIC;
signal BTN_0_Count_18_CYMUXF2_4986 : STD_LOGIC;
signal BTN_0_Count_18_LOGIC_ZERO_4985 : STD_LOGIC;
signal BTN_0_Count_18_CYSELG_4976 : STD_LOGIC;
signal BTN_0_Count_18_G : STD_LOGIC;
signal BTN_0_Count_18_SRINV_4974 : STD_LOGIC;
signal BTN_0_Count_18_CLKINV_4973 : STD_LOGIC;
signal BTN_0_Count_18_CEINVNOT : STD_LOGIC;
signal BTN_0_Count_20_DXMUX_5040 : STD_LOGIC;
signal BTN_0_Count_20_XORF_5038 : STD_LOGIC;
signal BTN_0_Count_20_CYINIT_5037 : STD_LOGIC;
signal BTN_0_Count_20_rt_5035 : STD_LOGIC;
signal BTN_0_Count_20_SRINV_5027 : STD_LOGIC;
signal BTN_0_Count_20_CLKINV_5026 : STD_LOGIC;
signal BTN_0_Count_20_CEINVNOT : STD_LOGIC;
signal SSeg_Result_0_XORF_5080 : STD_LOGIC;
signal SSeg_Result_0_LOGIC_ONE_5079 : STD_LOGIC;
signal SSeg_Result_0_CYINIT_5078 : STD_LOGIC;
signal SSeg_Result_0_CYSELF_5069 : STD_LOGIC;
signal SSeg_Result_0_BXINV_5067 : STD_LOGIC;
signal SSeg_Result_0_XORG_5065 : STD_LOGIC;
signal SSeg_Result_0_CYMUXG_5064 : STD_LOGIC;
signal SSeg_Result_0_LOGIC_ZERO_5062 : STD_LOGIC;
signal SSeg_Result_0_CYSELG_5053 : STD_LOGIC;
signal SSeg_Result_0_G : STD_LOGIC;
signal SSeg_Result_2_XORF_5118 : STD_LOGIC;
signal SSeg_Result_2_CYINIT_5117 : STD_LOGIC;
signal SSeg_Result_2_F : STD_LOGIC;
signal SSeg_Result_2_XORG_5106 : STD_LOGIC;
signal SSeg_Result_2_CYSELF_5104 : STD_LOGIC;
signal SSeg_Result_2_CYMUXFAST_5103 : STD_LOGIC;
signal SSeg_Result_2_CYAND_5102 : STD_LOGIC;
signal SSeg_Result_2_FASTCARRY_5101 : STD_LOGIC;
signal SSeg_Result_2_CYMUXG2_5100 : STD_LOGIC;
signal SSeg_Result_2_CYMUXF2_5099 : STD_LOGIC;
signal SSeg_Result_2_LOGIC_ZERO_5098 : STD_LOGIC;
signal SSeg_Result_2_CYSELG_5089 : STD_LOGIC;
signal SSeg_Result_2_G : STD_LOGIC;
signal SSeg_Result_4_XORF_5156 : STD_LOGIC;
signal SSeg_Result_4_CYINIT_5155 : STD_LOGIC;
signal SSeg_Result_4_F : STD_LOGIC;
signal SSeg_Result_4_XORG_5144 : STD_LOGIC;
signal SSeg_Result_4_CYSELF_5142 : STD_LOGIC;
signal SSeg_Result_4_CYMUXFAST_5141 : STD_LOGIC;
signal SSeg_Result_4_CYAND_5140 : STD_LOGIC;
signal SSeg_Result_4_FASTCARRY_5139 : STD_LOGIC;
signal SSeg_Result_4_CYMUXG2_5138 : STD_LOGIC;
signal SSeg_Result_4_CYMUXF2_5137 : STD_LOGIC;
signal SSeg_Result_4_LOGIC_ZERO_5136 : STD_LOGIC;
signal SSeg_Result_4_CYSELG_5127 : STD_LOGIC;
signal SSeg_Result_4_G : STD_LOGIC;
signal SSeg_Result_6_XORF_5194 : STD_LOGIC;
signal SSeg_Result_6_CYINIT_5193 : STD_LOGIC;
signal SSeg_Result_6_F : STD_LOGIC;
signal SSeg_Result_6_XORG_5182 : STD_LOGIC;
signal SSeg_Result_6_CYSELF_5180 : STD_LOGIC;
signal SSeg_Result_6_CYMUXFAST_5179 : STD_LOGIC;
signal SSeg_Result_6_CYAND_5178 : STD_LOGIC;
signal SSeg_Result_6_FASTCARRY_5177 : STD_LOGIC;
signal SSeg_Result_6_CYMUXG2_5176 : STD_LOGIC;
signal SSeg_Result_6_CYMUXF2_5175 : STD_LOGIC;
signal SSeg_Result_6_LOGIC_ZERO_5174 : STD_LOGIC;
signal SSeg_Result_6_CYSELG_5165 : STD_LOGIC;
signal SSeg_Result_6_G : STD_LOGIC;
signal SSeg_Result_8_XORF_5232 : STD_LOGIC;
signal SSeg_Result_8_CYINIT_5231 : STD_LOGIC;
signal SSeg_Result_8_F : STD_LOGIC;
signal SSeg_Result_8_XORG_5220 : STD_LOGIC;
signal SSeg_Result_8_CYSELF_5218 : STD_LOGIC;
signal SSeg_Result_8_CYMUXFAST_5217 : STD_LOGIC;
signal SSeg_Result_8_CYAND_5216 : STD_LOGIC;
signal SSeg_Result_8_FASTCARRY_5215 : STD_LOGIC;
signal SSeg_Result_8_CYMUXG2_5214 : STD_LOGIC;
signal SSeg_Result_8_CYMUXF2_5213 : STD_LOGIC;
signal SSeg_Result_8_LOGIC_ZERO_5212 : STD_LOGIC;
signal SSeg_Result_8_CYSELG_5203 : STD_LOGIC;
signal SSeg_Result_8_G : STD_LOGIC;
signal SSeg_Result_10_XORF_5270 : STD_LOGIC;
signal SSeg_Result_10_CYINIT_5269 : STD_LOGIC;
signal SSeg_Result_10_F : STD_LOGIC;
signal SSeg_Result_10_XORG_5258 : STD_LOGIC;
signal SSeg_Result_10_CYSELF_5256 : STD_LOGIC;
signal SSeg_Result_10_CYMUXFAST_5255 : STD_LOGIC;
signal SSeg_Result_10_CYAND_5254 : STD_LOGIC;
signal SSeg_Result_10_FASTCARRY_5253 : STD_LOGIC;
signal SSeg_Result_10_CYMUXG2_5252 : STD_LOGIC;
signal SSeg_Result_10_CYMUXF2_5251 : STD_LOGIC;
signal SSeg_Result_10_LOGIC_ZERO_5250 : STD_LOGIC;
signal SSeg_Result_10_CYSELG_5241 : STD_LOGIC;
signal SSeg_Result_10_G : STD_LOGIC;
signal SSeg_Result_12_XORF_5308 : STD_LOGIC;
signal SSeg_Result_12_CYINIT_5307 : STD_LOGIC;
signal SSeg_Result_12_F : STD_LOGIC;
signal SSeg_Result_12_XORG_5296 : STD_LOGIC;
signal SSeg_Result_12_CYSELF_5294 : STD_LOGIC;
signal SSeg_Result_12_CYMUXFAST_5293 : STD_LOGIC;
signal SSeg_Result_12_CYAND_5292 : STD_LOGIC;
signal SSeg_Result_12_FASTCARRY_5291 : STD_LOGIC;
signal SSeg_Result_12_CYMUXG2_5290 : STD_LOGIC;
signal SSeg_Result_12_CYMUXF2_5289 : STD_LOGIC;
signal SSeg_Result_12_LOGIC_ZERO_5288 : STD_LOGIC;
signal SSeg_Result_12_CYSELG_5279 : STD_LOGIC;
signal SSeg_Result_12_G : STD_LOGIC;
signal SSeg_Result_14_XORF_5346 : STD_LOGIC;
signal SSeg_Result_14_CYINIT_5345 : STD_LOGIC;
signal SSeg_Result_14_F : STD_LOGIC;
signal SSeg_Result_14_XORG_5334 : STD_LOGIC;
signal SSeg_Result_14_CYSELF_5332 : STD_LOGIC;
signal SSeg_Result_14_CYMUXFAST_5331 : STD_LOGIC;
signal SSeg_Result_14_CYAND_5330 : STD_LOGIC;
signal SSeg_Result_14_FASTCARRY_5329 : STD_LOGIC;
signal SSeg_Result_14_CYMUXG2_5328 : STD_LOGIC;
signal SSeg_Result_14_CYMUXF2_5327 : STD_LOGIC;
signal SSeg_Result_14_LOGIC_ZERO_5326 : STD_LOGIC;
signal SSeg_Result_14_CYSELG_5317 : STD_LOGIC;
signal SSeg_Result_14_G : STD_LOGIC;
signal SSeg_Result_16_XORF_5361 : STD_LOGIC;
signal SSeg_Result_16_CYINIT_5360 : STD_LOGIC;
signal SSeg_count240hz_16_rt_5358 : STD_LOGIC;
signal BTN_2_Count_0_DXMUX_5411 : STD_LOGIC;
signal BTN_2_Count_0_XORF_5409 : STD_LOGIC;
signal BTN_2_Count_0_LOGIC_ONE_5408 : STD_LOGIC;
signal BTN_2_Count_0_CYINIT_5407 : STD_LOGIC;
signal BTN_2_Count_0_CYSELF_5398 : STD_LOGIC;
signal BTN_2_Count_0_BXINV_5396 : STD_LOGIC;
signal BTN_2_Count_0_DYMUX_5390 : STD_LOGIC;
signal BTN_2_Count_0_XORG_5388 : STD_LOGIC;
signal BTN_2_Count_0_CYMUXG_5387 : STD_LOGIC;
signal BTN_2_Count_0_LOGIC_ZERO_5385 : STD_LOGIC;
signal BTN_2_Count_0_CYSELG_5376 : STD_LOGIC;
signal BTN_2_Count_0_G : STD_LOGIC;
signal BTN_2_Count_0_SRINV_5374 : STD_LOGIC;
signal BTN_2_Count_0_CLKINV_5373 : STD_LOGIC;
signal BTN_2_Count_0_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_2_DXMUX_5467 : STD_LOGIC;
signal BTN_2_Count_2_XORF_5465 : STD_LOGIC;
signal BTN_2_Count_2_CYINIT_5464 : STD_LOGIC;
signal BTN_2_Count_2_F : STD_LOGIC;
signal BTN_2_Count_2_DYMUX_5449 : STD_LOGIC;
signal BTN_2_Count_2_XORG_5447 : STD_LOGIC;
signal BTN_2_Count_2_CYSELF_5445 : STD_LOGIC;
signal BTN_2_Count_2_CYMUXFAST_5444 : STD_LOGIC;
signal BTN_2_Count_2_CYAND_5443 : STD_LOGIC;
signal BTN_2_Count_2_FASTCARRY_5442 : STD_LOGIC;
signal BTN_2_Count_2_CYMUXG2_5441 : STD_LOGIC;
signal BTN_2_Count_2_CYMUXF2_5440 : STD_LOGIC;
signal BTN_2_Count_2_LOGIC_ZERO_5439 : STD_LOGIC;
signal BTN_2_Count_2_CYSELG_5430 : STD_LOGIC;
signal BTN_2_Count_2_G : STD_LOGIC;
signal BTN_2_Count_2_SRINV_5428 : STD_LOGIC;
signal BTN_2_Count_2_CLKINV_5427 : STD_LOGIC;
signal BTN_2_Count_2_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_4_DXMUX_5523 : STD_LOGIC;
signal BTN_2_Count_4_XORF_5521 : STD_LOGIC;
signal BTN_2_Count_4_CYINIT_5520 : STD_LOGIC;
signal BTN_2_Count_4_F : STD_LOGIC;
signal BTN_2_Count_4_DYMUX_5505 : STD_LOGIC;
signal BTN_2_Count_4_XORG_5503 : STD_LOGIC;
signal BTN_2_Count_4_CYSELF_5501 : STD_LOGIC;
signal BTN_2_Count_4_CYMUXFAST_5500 : STD_LOGIC;
signal BTN_2_Count_4_CYAND_5499 : STD_LOGIC;
signal BTN_2_Count_4_FASTCARRY_5498 : STD_LOGIC;
signal BTN_2_Count_4_CYMUXG2_5497 : STD_LOGIC;
signal BTN_2_Count_4_CYMUXF2_5496 : STD_LOGIC;
signal BTN_2_Count_4_LOGIC_ZERO_5495 : STD_LOGIC;
signal BTN_2_Count_4_CYSELG_5486 : STD_LOGIC;
signal BTN_2_Count_4_G : STD_LOGIC;
signal BTN_2_Count_4_SRINV_5484 : STD_LOGIC;
signal BTN_2_Count_4_CLKINV_5483 : STD_LOGIC;
signal BTN_2_Count_4_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_6_DXMUX_5579 : STD_LOGIC;
signal BTN_2_Count_6_XORF_5577 : STD_LOGIC;
signal BTN_2_Count_6_CYINIT_5576 : STD_LOGIC;
signal BTN_2_Count_6_F : STD_LOGIC;
signal BTN_2_Count_6_DYMUX_5561 : STD_LOGIC;
signal BTN_2_Count_6_XORG_5559 : STD_LOGIC;
signal BTN_2_Count_6_CYSELF_5557 : STD_LOGIC;
signal BTN_2_Count_6_CYMUXFAST_5556 : STD_LOGIC;
signal BTN_2_Count_6_CYAND_5555 : STD_LOGIC;
signal BTN_2_Count_6_FASTCARRY_5554 : STD_LOGIC;
signal BTN_2_Count_6_CYMUXG2_5553 : STD_LOGIC;
signal BTN_2_Count_6_CYMUXF2_5552 : STD_LOGIC;
signal BTN_2_Count_6_LOGIC_ZERO_5551 : STD_LOGIC;
signal BTN_2_Count_6_CYSELG_5542 : STD_LOGIC;
signal BTN_2_Count_6_G : STD_LOGIC;
signal BTN_2_Count_6_SRINV_5540 : STD_LOGIC;
signal BTN_2_Count_6_CLKINV_5539 : STD_LOGIC;
signal BTN_2_Count_6_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_8_DXMUX_5635 : STD_LOGIC;
signal BTN_2_Count_8_XORF_5633 : STD_LOGIC;
signal BTN_2_Count_8_CYINIT_5632 : STD_LOGIC;
signal BTN_2_Count_8_F : STD_LOGIC;
signal BTN_2_Count_8_DYMUX_5617 : STD_LOGIC;
signal BTN_2_Count_8_XORG_5615 : STD_LOGIC;
signal BTN_2_Count_8_CYSELF_5613 : STD_LOGIC;
signal BTN_2_Count_8_CYMUXFAST_5612 : STD_LOGIC;
signal BTN_2_Count_8_CYAND_5611 : STD_LOGIC;
signal BTN_2_Count_8_FASTCARRY_5610 : STD_LOGIC;
signal BTN_2_Count_8_CYMUXG2_5609 : STD_LOGIC;
signal BTN_2_Count_8_CYMUXF2_5608 : STD_LOGIC;
signal BTN_2_Count_8_LOGIC_ZERO_5607 : STD_LOGIC;
signal BTN_2_Count_8_CYSELG_5598 : STD_LOGIC;
signal BTN_2_Count_8_G : STD_LOGIC;
signal BTN_2_Count_8_SRINV_5596 : STD_LOGIC;
signal BTN_2_Count_8_CLKINV_5595 : STD_LOGIC;
signal BTN_2_Count_8_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_10_DXMUX_5691 : STD_LOGIC;
signal BTN_2_Count_10_XORF_5689 : STD_LOGIC;
signal BTN_2_Count_10_CYINIT_5688 : STD_LOGIC;
signal BTN_2_Count_10_F : STD_LOGIC;
signal BTN_2_Count_10_DYMUX_5673 : STD_LOGIC;
signal BTN_2_Count_10_XORG_5671 : STD_LOGIC;
signal BTN_2_Count_10_CYSELF_5669 : STD_LOGIC;
signal BTN_2_Count_10_CYMUXFAST_5668 : STD_LOGIC;
signal BTN_2_Count_10_CYAND_5667 : STD_LOGIC;
signal BTN_2_Count_10_FASTCARRY_5666 : STD_LOGIC;
signal BTN_2_Count_10_CYMUXG2_5665 : STD_LOGIC;
signal BTN_2_Count_10_CYMUXF2_5664 : STD_LOGIC;
signal BTN_2_Count_10_LOGIC_ZERO_5663 : STD_LOGIC;
signal BTN_2_Count_10_CYSELG_5654 : STD_LOGIC;
signal BTN_2_Count_10_G : STD_LOGIC;
signal BTN_2_Count_10_SRINV_5652 : STD_LOGIC;
signal BTN_2_Count_10_CLKINV_5651 : STD_LOGIC;
signal BTN_2_Count_10_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_12_DXMUX_5747 : STD_LOGIC;
signal BTN_2_Count_12_XORF_5745 : STD_LOGIC;
signal BTN_2_Count_12_CYINIT_5744 : STD_LOGIC;
signal BTN_2_Count_12_F : STD_LOGIC;
signal BTN_2_Count_12_DYMUX_5729 : STD_LOGIC;
signal BTN_2_Count_12_XORG_5727 : STD_LOGIC;
signal BTN_2_Count_12_CYSELF_5725 : STD_LOGIC;
signal BTN_2_Count_12_CYMUXFAST_5724 : STD_LOGIC;
signal BTN_2_Count_12_CYAND_5723 : STD_LOGIC;
signal BTN_2_Count_12_FASTCARRY_5722 : STD_LOGIC;
signal BTN_2_Count_12_CYMUXG2_5721 : STD_LOGIC;
signal BTN_2_Count_12_CYMUXF2_5720 : STD_LOGIC;
signal BTN_2_Count_12_LOGIC_ZERO_5719 : STD_LOGIC;
signal BTN_2_Count_12_CYSELG_5710 : STD_LOGIC;
signal BTN_2_Count_12_G : STD_LOGIC;
signal BTN_2_Count_12_SRINV_5708 : STD_LOGIC;
signal BTN_2_Count_12_CLKINV_5707 : STD_LOGIC;
signal BTN_2_Count_12_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_14_DXMUX_5803 : STD_LOGIC;
signal BTN_2_Count_14_XORF_5801 : STD_LOGIC;
signal BTN_2_Count_14_CYINIT_5800 : STD_LOGIC;
signal BTN_2_Count_14_F : STD_LOGIC;
signal BTN_2_Count_14_DYMUX_5785 : STD_LOGIC;
signal BTN_2_Count_14_XORG_5783 : STD_LOGIC;
signal BTN_2_Count_14_CYSELF_5781 : STD_LOGIC;
signal BTN_2_Count_14_CYMUXFAST_5780 : STD_LOGIC;
signal BTN_2_Count_14_CYAND_5779 : STD_LOGIC;
signal BTN_2_Count_14_FASTCARRY_5778 : STD_LOGIC;
signal BTN_2_Count_14_CYMUXG2_5777 : STD_LOGIC;
signal BTN_2_Count_14_CYMUXF2_5776 : STD_LOGIC;
signal BTN_2_Count_14_LOGIC_ZERO_5775 : STD_LOGIC;
signal BTN_2_Count_14_CYSELG_5766 : STD_LOGIC;
signal BTN_2_Count_14_G : STD_LOGIC;
signal BTN_2_Count_14_SRINV_5764 : STD_LOGIC;
signal BTN_2_Count_14_CLKINV_5763 : STD_LOGIC;
signal BTN_2_Count_14_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_16_DXMUX_5859 : STD_LOGIC;
signal BTN_2_Count_16_XORF_5857 : STD_LOGIC;
signal BTN_2_Count_16_CYINIT_5856 : STD_LOGIC;
signal BTN_2_Count_16_F : STD_LOGIC;
signal BTN_2_Count_16_DYMUX_5841 : STD_LOGIC;
signal BTN_2_Count_16_XORG_5839 : STD_LOGIC;
signal BTN_2_Count_16_CYSELF_5837 : STD_LOGIC;
signal BTN_2_Count_16_CYMUXFAST_5836 : STD_LOGIC;
signal BTN_2_Count_16_CYAND_5835 : STD_LOGIC;
signal BTN_2_Count_16_FASTCARRY_5834 : STD_LOGIC;
signal BTN_2_Count_16_CYMUXG2_5833 : STD_LOGIC;
signal BTN_2_Count_16_CYMUXF2_5832 : STD_LOGIC;
signal BTN_2_Count_16_LOGIC_ZERO_5831 : STD_LOGIC;
signal BTN_2_Count_16_CYSELG_5822 : STD_LOGIC;
signal BTN_2_Count_16_G : STD_LOGIC;
signal BTN_2_Count_16_SRINV_5820 : STD_LOGIC;
signal BTN_2_Count_16_CLKINV_5819 : STD_LOGIC;
signal BTN_2_Count_16_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_18_DXMUX_5915 : STD_LOGIC;
signal BTN_2_Count_18_XORF_5913 : STD_LOGIC;
signal BTN_2_Count_18_CYINIT_5912 : STD_LOGIC;
signal BTN_2_Count_18_F : STD_LOGIC;
signal BTN_2_Count_18_DYMUX_5897 : STD_LOGIC;
signal BTN_2_Count_18_XORG_5895 : STD_LOGIC;
signal BTN_2_Count_18_CYSELF_5893 : STD_LOGIC;
signal BTN_2_Count_18_CYMUXFAST_5892 : STD_LOGIC;
signal BTN_2_Count_18_CYAND_5891 : STD_LOGIC;
signal BTN_2_Count_18_FASTCARRY_5890 : STD_LOGIC;
signal BTN_2_Count_18_CYMUXG2_5889 : STD_LOGIC;
signal BTN_2_Count_18_CYMUXF2_5888 : STD_LOGIC;
signal BTN_2_Count_18_LOGIC_ZERO_5887 : STD_LOGIC;
signal BTN_2_Count_18_CYSELG_5878 : STD_LOGIC;
signal BTN_2_Count_18_G : STD_LOGIC;
signal BTN_2_Count_18_SRINV_5876 : STD_LOGIC;
signal BTN_2_Count_18_CLKINV_5875 : STD_LOGIC;
signal BTN_2_Count_18_CEINVNOT : STD_LOGIC;
signal BTN_2_Count_20_DXMUX_5942 : STD_LOGIC;
signal BTN_2_Count_20_XORF_5940 : STD_LOGIC;
signal BTN_2_Count_20_CYINIT_5939 : STD_LOGIC;
signal BTN_2_Count_20_rt_5937 : STD_LOGIC;
signal BTN_2_Count_20_SRINV_5929 : STD_LOGIC;
signal BTN_2_Count_20_CLKINV_5928 : STD_LOGIC;
signal BTN_2_Count_20_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_0_DXMUX_5996 : STD_LOGIC;
signal BTN_3_Count_0_XORF_5994 : STD_LOGIC;
signal BTN_3_Count_0_LOGIC_ONE_5993 : STD_LOGIC;
signal BTN_3_Count_0_CYINIT_5992 : STD_LOGIC;
signal BTN_3_Count_0_CYSELF_5983 : STD_LOGIC;
signal BTN_3_Count_0_BXINV_5981 : STD_LOGIC;
signal BTN_3_Count_0_DYMUX_5975 : STD_LOGIC;
signal BTN_3_Count_0_XORG_5973 : STD_LOGIC;
signal BTN_3_Count_0_CYMUXG_5972 : STD_LOGIC;
signal BTN_3_Count_0_LOGIC_ZERO_5970 : STD_LOGIC;
signal BTN_3_Count_0_CYSELG_5961 : STD_LOGIC;
signal BTN_3_Count_0_G : STD_LOGIC;
signal BTN_3_Count_0_SRINV_5959 : STD_LOGIC;
signal BTN_3_Count_0_CLKINV_5958 : STD_LOGIC;
signal BTN_3_Count_0_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_2_DXMUX_6052 : STD_LOGIC;
signal BTN_3_Count_2_XORF_6050 : STD_LOGIC;
signal BTN_3_Count_2_CYINIT_6049 : STD_LOGIC;
signal BTN_3_Count_2_F : STD_LOGIC;
signal BTN_3_Count_2_DYMUX_6034 : STD_LOGIC;
signal BTN_3_Count_2_XORG_6032 : STD_LOGIC;
signal BTN_3_Count_2_CYSELF_6030 : STD_LOGIC;
signal BTN_3_Count_2_CYMUXFAST_6029 : STD_LOGIC;
signal BTN_3_Count_2_CYAND_6028 : STD_LOGIC;
signal BTN_3_Count_2_FASTCARRY_6027 : STD_LOGIC;
signal BTN_3_Count_2_CYMUXG2_6026 : STD_LOGIC;
signal BTN_3_Count_2_CYMUXF2_6025 : STD_LOGIC;
signal BTN_3_Count_2_LOGIC_ZERO_6024 : STD_LOGIC;
signal BTN_3_Count_2_CYSELG_6015 : STD_LOGIC;
signal BTN_3_Count_2_G : STD_LOGIC;
signal BTN_3_Count_2_SRINV_6013 : STD_LOGIC;
signal BTN_3_Count_2_CLKINV_6012 : STD_LOGIC;
signal BTN_3_Count_2_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_4_DXMUX_6108 : STD_LOGIC;
signal BTN_3_Count_4_XORF_6106 : STD_LOGIC;
signal BTN_3_Count_4_CYINIT_6105 : STD_LOGIC;
signal BTN_3_Count_4_F : STD_LOGIC;
signal BTN_3_Count_4_DYMUX_6090 : STD_LOGIC;
signal BTN_3_Count_4_XORG_6088 : STD_LOGIC;
signal BTN_3_Count_4_CYSELF_6086 : STD_LOGIC;
signal BTN_3_Count_4_CYMUXFAST_6085 : STD_LOGIC;
signal BTN_3_Count_4_CYAND_6084 : STD_LOGIC;
signal BTN_3_Count_4_FASTCARRY_6083 : STD_LOGIC;
signal BTN_3_Count_4_CYMUXG2_6082 : STD_LOGIC;
signal BTN_3_Count_4_CYMUXF2_6081 : STD_LOGIC;
signal BTN_3_Count_4_LOGIC_ZERO_6080 : STD_LOGIC;
signal BTN_3_Count_4_CYSELG_6071 : STD_LOGIC;
signal BTN_3_Count_4_G : STD_LOGIC;
signal BTN_3_Count_4_SRINV_6069 : STD_LOGIC;
signal BTN_3_Count_4_CLKINV_6068 : STD_LOGIC;
signal BTN_3_Count_4_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_6_DXMUX_6164 : STD_LOGIC;
signal BTN_3_Count_6_XORF_6162 : STD_LOGIC;
signal BTN_3_Count_6_CYINIT_6161 : STD_LOGIC;
signal BTN_3_Count_6_F : STD_LOGIC;
signal BTN_3_Count_6_DYMUX_6146 : STD_LOGIC;
signal BTN_3_Count_6_XORG_6144 : STD_LOGIC;
signal BTN_3_Count_6_CYSELF_6142 : STD_LOGIC;
signal BTN_3_Count_6_CYMUXFAST_6141 : STD_LOGIC;
signal BTN_3_Count_6_CYAND_6140 : STD_LOGIC;
signal BTN_3_Count_6_FASTCARRY_6139 : STD_LOGIC;
signal BTN_3_Count_6_CYMUXG2_6138 : STD_LOGIC;
signal BTN_3_Count_6_CYMUXF2_6137 : STD_LOGIC;
signal BTN_3_Count_6_LOGIC_ZERO_6136 : STD_LOGIC;
signal BTN_3_Count_6_CYSELG_6127 : STD_LOGIC;
signal BTN_3_Count_6_G : STD_LOGIC;
signal BTN_3_Count_6_SRINV_6125 : STD_LOGIC;
signal BTN_3_Count_6_CLKINV_6124 : STD_LOGIC;
signal BTN_3_Count_6_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_8_DXMUX_6220 : STD_LOGIC;
signal BTN_3_Count_8_XORF_6218 : STD_LOGIC;
signal BTN_3_Count_8_CYINIT_6217 : STD_LOGIC;
signal BTN_3_Count_8_F : STD_LOGIC;
signal BTN_3_Count_8_DYMUX_6202 : STD_LOGIC;
signal BTN_3_Count_8_XORG_6200 : STD_LOGIC;
signal BTN_3_Count_8_CYSELF_6198 : STD_LOGIC;
signal BTN_3_Count_8_CYMUXFAST_6197 : STD_LOGIC;
signal BTN_3_Count_8_CYAND_6196 : STD_LOGIC;
signal BTN_3_Count_8_FASTCARRY_6195 : STD_LOGIC;
signal BTN_3_Count_8_CYMUXG2_6194 : STD_LOGIC;
signal BTN_3_Count_8_CYMUXF2_6193 : STD_LOGIC;
signal BTN_3_Count_8_LOGIC_ZERO_6192 : STD_LOGIC;
signal BTN_3_Count_8_CYSELG_6183 : STD_LOGIC;
signal BTN_3_Count_8_G : STD_LOGIC;
signal BTN_3_Count_8_SRINV_6181 : STD_LOGIC;
signal BTN_3_Count_8_CLKINV_6180 : STD_LOGIC;
signal BTN_3_Count_8_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_10_DXMUX_6276 : STD_LOGIC;
signal BTN_3_Count_10_XORF_6274 : STD_LOGIC;
signal BTN_3_Count_10_CYINIT_6273 : STD_LOGIC;
signal BTN_3_Count_10_F : STD_LOGIC;
signal BTN_3_Count_10_DYMUX_6258 : STD_LOGIC;
signal BTN_3_Count_10_XORG_6256 : STD_LOGIC;
signal BTN_3_Count_10_CYSELF_6254 : STD_LOGIC;
signal BTN_3_Count_10_CYMUXFAST_6253 : STD_LOGIC;
signal BTN_3_Count_10_CYAND_6252 : STD_LOGIC;
signal BTN_3_Count_10_FASTCARRY_6251 : STD_LOGIC;
signal BTN_3_Count_10_CYMUXG2_6250 : STD_LOGIC;
signal BTN_3_Count_10_CYMUXF2_6249 : STD_LOGIC;
signal BTN_3_Count_10_LOGIC_ZERO_6248 : STD_LOGIC;
signal BTN_3_Count_10_CYSELG_6239 : STD_LOGIC;
signal BTN_3_Count_10_G : STD_LOGIC;
signal BTN_3_Count_10_SRINV_6237 : STD_LOGIC;
signal BTN_3_Count_10_CLKINV_6236 : STD_LOGIC;
signal BTN_3_Count_10_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_12_DXMUX_6332 : STD_LOGIC;
signal BTN_3_Count_12_XORF_6330 : STD_LOGIC;
signal BTN_3_Count_12_CYINIT_6329 : STD_LOGIC;
signal BTN_3_Count_12_F : STD_LOGIC;
signal BTN_3_Count_12_DYMUX_6314 : STD_LOGIC;
signal BTN_3_Count_12_XORG_6312 : STD_LOGIC;
signal BTN_3_Count_12_CYSELF_6310 : STD_LOGIC;
signal BTN_3_Count_12_CYMUXFAST_6309 : STD_LOGIC;
signal BTN_3_Count_12_CYAND_6308 : STD_LOGIC;
signal BTN_3_Count_12_FASTCARRY_6307 : STD_LOGIC;
signal BTN_3_Count_12_CYMUXG2_6306 : STD_LOGIC;
signal BTN_3_Count_12_CYMUXF2_6305 : STD_LOGIC;
signal BTN_3_Count_12_LOGIC_ZERO_6304 : STD_LOGIC;
signal BTN_3_Count_12_CYSELG_6295 : STD_LOGIC;
signal BTN_3_Count_12_G : STD_LOGIC;
signal BTN_3_Count_12_SRINV_6293 : STD_LOGIC;
signal BTN_3_Count_12_CLKINV_6292 : STD_LOGIC;
signal BTN_3_Count_12_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_14_DXMUX_6388 : STD_LOGIC;
signal BTN_3_Count_14_XORF_6386 : STD_LOGIC;
signal BTN_3_Count_14_CYINIT_6385 : STD_LOGIC;
signal BTN_3_Count_14_F : STD_LOGIC;
signal BTN_3_Count_14_DYMUX_6370 : STD_LOGIC;
signal BTN_3_Count_14_XORG_6368 : STD_LOGIC;
signal BTN_3_Count_14_CYSELF_6366 : STD_LOGIC;
signal BTN_3_Count_14_CYMUXFAST_6365 : STD_LOGIC;
signal BTN_3_Count_14_CYAND_6364 : STD_LOGIC;
signal BTN_3_Count_14_FASTCARRY_6363 : STD_LOGIC;
signal BTN_3_Count_14_CYMUXG2_6362 : STD_LOGIC;
signal BTN_3_Count_14_CYMUXF2_6361 : STD_LOGIC;
signal BTN_3_Count_14_LOGIC_ZERO_6360 : STD_LOGIC;
signal BTN_3_Count_14_CYSELG_6351 : STD_LOGIC;
signal BTN_3_Count_14_G : STD_LOGIC;
signal BTN_3_Count_14_SRINV_6349 : STD_LOGIC;
signal BTN_3_Count_14_CLKINV_6348 : STD_LOGIC;
signal BTN_3_Count_14_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_16_DXMUX_6444 : STD_LOGIC;
signal BTN_3_Count_16_XORF_6442 : STD_LOGIC;
signal BTN_3_Count_16_CYINIT_6441 : STD_LOGIC;
signal BTN_3_Count_16_F : STD_LOGIC;
signal BTN_3_Count_16_DYMUX_6426 : STD_LOGIC;
signal BTN_3_Count_16_XORG_6424 : STD_LOGIC;
signal BTN_3_Count_16_CYSELF_6422 : STD_LOGIC;
signal BTN_3_Count_16_CYMUXFAST_6421 : STD_LOGIC;
signal BTN_3_Count_16_CYAND_6420 : STD_LOGIC;
signal BTN_3_Count_16_FASTCARRY_6419 : STD_LOGIC;
signal BTN_3_Count_16_CYMUXG2_6418 : STD_LOGIC;
signal BTN_3_Count_16_CYMUXF2_6417 : STD_LOGIC;
signal BTN_3_Count_16_LOGIC_ZERO_6416 : STD_LOGIC;
signal BTN_3_Count_16_CYSELG_6407 : STD_LOGIC;
signal BTN_3_Count_16_G : STD_LOGIC;
signal BTN_3_Count_16_SRINV_6405 : STD_LOGIC;
signal BTN_3_Count_16_CLKINV_6404 : STD_LOGIC;
signal BTN_3_Count_16_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_18_DXMUX_6500 : STD_LOGIC;
signal BTN_3_Count_18_XORF_6498 : STD_LOGIC;
signal BTN_3_Count_18_CYINIT_6497 : STD_LOGIC;
signal BTN_3_Count_18_F : STD_LOGIC;
signal BTN_3_Count_18_DYMUX_6482 : STD_LOGIC;
signal BTN_3_Count_18_XORG_6480 : STD_LOGIC;
signal BTN_3_Count_18_CYSELF_6478 : STD_LOGIC;
signal BTN_3_Count_18_CYMUXFAST_6477 : STD_LOGIC;
signal BTN_3_Count_18_CYAND_6476 : STD_LOGIC;
signal BTN_3_Count_18_FASTCARRY_6475 : STD_LOGIC;
signal BTN_3_Count_18_CYMUXG2_6474 : STD_LOGIC;
signal BTN_3_Count_18_CYMUXF2_6473 : STD_LOGIC;
signal BTN_3_Count_18_LOGIC_ZERO_6472 : STD_LOGIC;
signal BTN_3_Count_18_CYSELG_6463 : STD_LOGIC;
signal BTN_3_Count_18_G : STD_LOGIC;
signal BTN_3_Count_18_SRINV_6461 : STD_LOGIC;
signal BTN_3_Count_18_CLKINV_6460 : STD_LOGIC;
signal BTN_3_Count_18_CEINVNOT : STD_LOGIC;
signal BTN_3_Count_20_DXMUX_6527 : STD_LOGIC;
signal BTN_3_Count_20_XORF_6525 : STD_LOGIC;
signal BTN_3_Count_20_CYINIT_6524 : STD_LOGIC;
signal BTN_3_Count_20_rt_6522 : STD_LOGIC;
signal BTN_3_Count_20_SRINV_6514 : STD_LOGIC;
signal BTN_3_Count_20_CLKINV_6513 : STD_LOGIC;
signal BTN_3_Count_20_CEINVNOT : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_1_CYINIT_6561 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELF_6552 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_1_BXINV_6550 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_1_CYMUXG_6549 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_1_LOGIC_ZERO_6547 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELG_6541 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELF_6585 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXFAST_6584 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_CYAND_6583 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_FASTCARRY_6582 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXG2_6581 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXF2_6580 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_LOGIC_ZERO_6579 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELG_6573 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_LOGIC_ZERO_6606 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_CYINIT_6605 : STD_LOGIC;
signal SSeg_count240hz_cmp_eq0000_CYSELF_6599 : STD_LOGIC;
signal CLK_INBUF : STD_LOGIC;
signal AN_0_O : STD_LOGIC;
signal AN_1_O : STD_LOGIC;
signal AN_2_O : STD_LOGIC;
signal AN_3_O : STD_LOGIC;
signal SW_0_INBUF : STD_LOGIC;
signal SW_1_INBUF : STD_LOGIC;
signal SW_2_INBUF : STD_LOGIC;
signal SW_3_INBUF : STD_LOGIC;
signal SW_4_INBUF : STD_LOGIC;
signal SW_5_INBUF : STD_LOGIC;
signal SW_6_INBUF : STD_LOGIC;
signal SW_7_INBUF : STD_LOGIC;
signal BTN_0_INBUF : STD_LOGIC;
signal BTN_1_INBUF : STD_LOGIC;
signal BTN_2_INBUF : STD_LOGIC;
signal BTN_3_INBUF : STD_LOGIC;
signal SEG_0_O : STD_LOGIC;
signal SEG_1_O : STD_LOGIC;
signal SEG_2_O : STD_LOGIC;
signal SEG_3_O : STD_LOGIC;
signal SEG_4_O : STD_LOGIC;
signal SEG_5_O : STD_LOGIC;
signal SEG_6_O : STD_LOGIC;
signal CLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal CLK_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal N21_F5MUX_6801 : STD_LOGIC;
signal N21_F : STD_LOGIC;
signal N21_BXINV_6790 : STD_LOGIC;
signal ALU_Mux_ALU_OUT_0_51 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001257_F5MUX_6826 : STD_LOGIC;
signal N101 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001257_BXINV_6819 : STD_LOGIC;
signal N100 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001828_F5MUX_6851 : STD_LOGIC;
signal N99 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001828_BXINV_6844 : STD_LOGIC;
signal N98 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001686_F5MUX_6876 : STD_LOGIC;
signal N109 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux0001686_BXINV_6869 : STD_LOGIC;
signal N108 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014107_F5MUX_6901 : STD_LOGIC;
signal N103 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014107_BXINV_6894 : STD_LOGIC;
signal N102 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018194_F5MUX_6926 : STD_LOGIC;
signal N105 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018194_BXINV_6919 : STD_LOGIC;
signal N104 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018290_F5MUX_6951 : STD_LOGIC;
signal N97 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00018290_BXINV_6944 : STD_LOGIC;
signal N96 : STD_LOGIC;
signal N68_F5MUX_6976 : STD_LOGIC;
signal N107 : STD_LOGIC;
signal N68_BXINV_6969 : STD_LOGIC;
signal N106 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012171_F5MUX_7001 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000121711_6999 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012171_BXINV_6993 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000121712_6991 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014312_F5MUX_7026 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000143121_7024 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014312_BXINV_7019 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000143122_7017 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016175_F5MUX_7051 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016175_F : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016175_BXINV_7040 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux000161751_7038 : STD_LOGIC;
signal SSeg_hexnum_0_DXMUX_7079 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00012292_O_pack_1 : STD_LOGIC;
signal SSeg_hexnum_0_CLKINV_7062 : STD_LOGIC;
signal SSeg_hexnum_1_DXMUX_7109 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00014384_SW0_O_pack_2 : STD_LOGIC;
signal SSeg_hexnum_1_CLKINV_7093 : STD_LOGIC;
signal SSeg_hexnum_2_DXMUX_7139 : STD_LOGIC;
signal SSeg_Mmux_hexnum_mux00016330_O_pack_1 : STD_LOGIC;
signal SSeg_hexnum_2_CLKINV_7122 : STD_LOGIC;
signal SSeg_hexnum_3_DYMUX_7157 : STD_LOGIC;
signal SSeg_hexnum_3_CLKINV_7147 : STD_LOGIC;
signal SSeg_AN_OUT_1_DXMUX_7191 : STD_LOGIC;
signal SSeg_Mrom_AN_OUT_mux00011 : STD_LOGIC;
signal SSeg_AN_OUT_1_DYMUX_7178 : STD_LOGIC;
signal SSeg_Mrom_AN_OUT_mux0001 : STD_LOGIC;
signal SSeg_AN_OUT_1_CLKINV_7168 : STD_LOGIC;
signal SSeg_AN_OUT_3_DXMUX_7225 : STD_LOGIC;
signal SSeg_Mrom_AN_OUT_mux00013 : STD_LOGIC;
signal SSeg_AN_OUT_3_DYMUX_7212 : STD_LOGIC;
signal SSeg_Mrom_AN_OUT_mux00012 : STD_LOGIC;
signal SSeg_AN_OUT_3_CLKINV_7202 : STD_LOGIC;
signal SSeg_count240hz_11_DXMUX_7259 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_11 : STD_LOGIC;
signal SSeg_count240hz_11_DYMUX_7246 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_10 : STD_LOGIC;
signal SSeg_count240hz_11_CLKINV_7236 : STD_LOGIC;
signal SSeg_count240hz_13_DXMUX_7293 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_13 : STD_LOGIC;
signal SSeg_count240hz_13_DYMUX_7280 : STD_LOGIC;
signal SSeg_Mcount_count240hz_eqn_12 : STD_LOGIC;
signal SSeg_count240hz_13_CLKINV_7270 : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_2_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_3_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_6_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_7_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_4_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_5_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_6_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_7_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_OPCODE_0_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_OPCODE_1_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_OPCODE_2_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_OPCODE_3_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_0_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_1_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_2_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_3_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_0_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALB_1_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_4_CLK : STD_LOGIC;
signal NlwInverterSignal_UXCntl_Unit_VALA_5_CLK : STD_LOGIC;
signal SSeg_Result : STD_LOGIC_VECTOR ( 16 downto 0 );
signal SSeg_count240hz : STD_LOGIC_VECTOR ( 16 downto 0 );
signal UXCntl_Unit_VALB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal UXCntl_Unit_VALA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal UXCntl_Unit_OPCODE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SSeg_hexnum : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BTN_2_Count : STD_LOGIC_VECTOR ( 20 downto 0 );
signal BTN_2_D_STATE : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Load_Store_Unit_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal arith : STD_LOGIC_VECTOR ( 7 downto 0 );
signal BTN_0_D_STATE : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BTN_0_Count : STD_LOGIC_VECTOR ( 20 downto 0 );
signal BTN_3_Count : STD_LOGIC_VECTOR ( 20 downto 0 );
signal BTN_3_D_STATE : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BTN_1_D_STATE : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SSeg_pos : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BTN_1_Count : STD_LOGIC_VECTOR ( 20 downto 0 );
signal BTN_1_Mcount_Count_cy : STD_LOGIC_VECTOR ( 18 downto 0 );
signal BTN_0_Mcount_Count_cy : STD_LOGIC_VECTOR ( 18 downto 0 );
signal SSeg_Mcount_count240hz_cy : STD_LOGIC_VECTOR ( 14 downto 0 );
signal BTN_2_Mcount_Count_cy : STD_LOGIC_VECTOR ( 18 downto 0 );
signal BTN_3_Mcount_Count_cy : STD_LOGIC_VECTOR ( 18 downto 0 );
signal SSeg_AN_OUT : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BTN_1_Mcount_Count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Arith_Unit_Maddsub_arith_lut : STD_LOGIC_VECTOR ( 7 downto 0 );
signal BTN_0_Mcount_Count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal SSeg_Mcount_count240hz_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal BTN_2_Mcount_Count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal BTN_3_Mcount_Count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal SSeg_count240hz_cmp_eq0000_wg_lut : STD_LOGIC_VECTOR ( 4 downto 0 );
signal SSeg_count240hz_cmp_eq0000_wg_cy : STD_LOGIC_VECTOR ( 0 downto 0 );
signal SSeg_hexnum_mux0001 : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
SSeg_count240hz_15_DXMUX : X_BUF
generic map(
LOC => "SLICE_X32Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_15,
O => SSeg_count240hz_15_DXMUX_2085
);
SSeg_count240hz_15_DYMUX : X_BUF
generic map(
LOC => "SLICE_X32Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_14,
O => SSeg_count240hz_15_DYMUX_2072
);
SSeg_count240hz_15_CLKINV : X_BUF
generic map(
LOC => "SLICE_X32Y21",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_15_CLKINV_2062
);
SSeg_Mcount_count240hz_eqn_141 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X32Y21"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => SSeg_Result(14),
O => SSeg_Mcount_count240hz_eqn_14
);
SSeg_count240hz_16_DYMUX : X_BUF
generic map(
LOC => "SLICE_X35Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_16,
O => SSeg_count240hz_16_DYMUX_2103
);
SSeg_count240hz_16_CLKINV : X_BUF
generic map(
LOC => "SLICE_X35Y22",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_16_CLKINV_2093
);
SSeg_Mcount_count240hz_eqn_161 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X35Y22"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(16),
ADR2 => VCC,
ADR3 => SSeg_count240hz_cmp_eq0000,
O => SSeg_Mcount_count240hz_eqn_16
);
SSeg_count240hz_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X35Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_1,
O => SSeg_count240hz_1_DXMUX_2137
);
SSeg_count240hz_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X35Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_0,
O => SSeg_count240hz_1_DYMUX_2124
);
SSeg_count240hz_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X35Y15",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_1_CLKINV_2114
);
SSeg_Mcount_count240hz_eqn_01 : X_LUT4
generic map(
INIT => X"0C0C",
LOC => "SLICE_X35Y15"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(0),
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_0
);
SSeg_count240hz_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X35Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_3,
O => SSeg_count240hz_3_DXMUX_2171
);
SSeg_count240hz_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X35Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_2,
O => SSeg_count240hz_3_DYMUX_2158
);
SSeg_count240hz_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X35Y14",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_3_CLKINV_2148
);
SSeg_Mcount_count240hz_eqn_21 : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X35Y14"
)
port map (
ADR0 => SSeg_Result(2),
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_2
);
SSeg_count240hz_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X34Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_5,
O => SSeg_count240hz_5_DXMUX_2205
);
SSeg_count240hz_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X34Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_4,
O => SSeg_count240hz_5_DYMUX_2192
);
SSeg_count240hz_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X34Y19",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_5_CLKINV_2182
);
SSeg_Mcount_count240hz_eqn_41 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X34Y19"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(4),
ADR2 => VCC,
ADR3 => SSeg_count240hz_cmp_eq0000,
O => SSeg_Mcount_count240hz_eqn_4
);
SSeg_count240hz_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X35Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_7,
O => SSeg_count240hz_7_DXMUX_2239
);
SSeg_count240hz_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X35Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_6,
O => SSeg_count240hz_7_DYMUX_2226
);
SSeg_count240hz_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X35Y17",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_7_CLKINV_2216
);
SSeg_Mcount_count240hz_eqn_61 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X35Y17"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(6),
ADR2 => VCC,
ADR3 => SSeg_count240hz_cmp_eq0000,
O => SSeg_Mcount_count240hz_eqn_6
);
SSeg_count240hz_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X32Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_9,
O => SSeg_count240hz_9_DXMUX_2273
);
SSeg_count240hz_9_DYMUX : X_BUF
generic map(
LOC => "SLICE_X32Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_8,
O => SSeg_count240hz_9_DYMUX_2260
);
SSeg_count240hz_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X32Y19",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_9_CLKINV_2250
);
SSeg_Mcount_count240hz_eqn_81 : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X32Y19"
)
port map (
ADR0 => SSeg_Result(8),
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_8
);
N27_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y23",
PATHPULSE => 638 ps
)
port map (
I => N27,
O => N27_0
);
N27_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y23",
PATHPULSE => 638 ps
)
port map (
I => N94,
O => N94_0
);
SSeg_Mmux_hexnum_mux00014312_SW0_SW0 : X_LUT4
generic map(
INIT => X"757F",
LOC => "SLICE_X67Y23"
)
port map (
ADR0 => UXCntl_Unit_VALB(2),
ADR1 => UXCntl_Unit_VALA(0),
ADR2 => UXCntl_Unit_VALB(0),
ADR3 => UXCntl_Unit_VALA(1),
O => N94
);
UXCntl_Unit_VALA_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y39",
PATHPULSE => 638 ps
)
port map (
I => SW_1_IBUF_1740,
O => UXCntl_Unit_VALA_1_DXMUX_2313
);
UXCntl_Unit_VALA_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y39",
PATHPULSE => 638 ps
)
port map (
I => SW_0_IBUF_1741,
O => UXCntl_Unit_VALA_1_DYMUX_2308
);
UXCntl_Unit_VALA_1_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y39",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA_cmp_eq0000_0,
O => UXCntl_Unit_VALA_1_CLKINVNOT
);
UXCntl_Unit_VALA_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y23",
PATHPULSE => 638 ps
)
port map (
I => SW_3_IBUF_1743,
O => UXCntl_Unit_VALA_3_DXMUX_2329
);
UXCntl_Unit_VALA_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y23",
PATHPULSE => 638 ps
)
port map (
I => SW_2_IBUF_1744,
O => UXCntl_Unit_VALA_3_DYMUX_2324
);
UXCntl_Unit_VALA_3_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y23",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA_cmp_eq0000_0,
O => UXCntl_Unit_VALA_3_CLKINVNOT
);
UXCntl_Unit_VALB_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y38",
PATHPULSE => 638 ps
)
port map (
I => SW_1_IBUF_1740,
O => UXCntl_Unit_VALB_1_DXMUX_2345
);
UXCntl_Unit_VALB_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y38",
PATHPULSE => 638 ps
)
port map (
I => SW_0_IBUF_1741,
O => UXCntl_Unit_VALB_1_DYMUX_2340
);
UXCntl_Unit_VALB_1_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y38",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB_cmp_eq0000_0,
O => UXCntl_Unit_VALB_1_CLKINVNOT
);
UXCntl_Unit_VALA_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y19",
PATHPULSE => 638 ps
)
port map (
I => SW_5_IBUF_1748,
O => UXCntl_Unit_VALA_5_DXMUX_2361
);
UXCntl_Unit_VALA_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y19",
PATHPULSE => 638 ps
)
port map (
I => SW_4_IBUF_1749,
O => UXCntl_Unit_VALA_5_DYMUX_2356
);
UXCntl_Unit_VALA_5_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y19",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA_cmp_eq0000_0,
O => UXCntl_Unit_VALA_5_CLKINVNOT
);
UXCntl_Unit_VALB_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X64Y22",
PATHPULSE => 638 ps
)
port map (
I => SW_3_IBUF_1743,
O => UXCntl_Unit_VALB_3_DXMUX_2377
);
UXCntl_Unit_VALB_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y22",
PATHPULSE => 638 ps
)
port map (
I => SW_2_IBUF_1744,
O => UXCntl_Unit_VALB_3_DYMUX_2372
);
UXCntl_Unit_VALB_3_CLKINV : X_INV
generic map(
LOC => "SLICE_X64Y22",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB_cmp_eq0000_0,
O => UXCntl_Unit_VALB_3_CLKINVNOT
);
UXCntl_Unit_VALA_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y18",
PATHPULSE => 638 ps
)
port map (
I => SW_7_IBUF_1753,
O => UXCntl_Unit_VALA_7_DXMUX_2393
);
UXCntl_Unit_VALA_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y18",
PATHPULSE => 638 ps
)
port map (
I => SW_6_IBUF_1754,
O => UXCntl_Unit_VALA_7_DYMUX_2388
);
UXCntl_Unit_VALA_7_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y18",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA_cmp_eq0000_0,
O => UXCntl_Unit_VALA_7_CLKINVNOT
);
UXCntl_Unit_VALB_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X64Y20",
PATHPULSE => 638 ps
)
port map (
I => SW_5_IBUF_1748,
O => UXCntl_Unit_VALB_5_DXMUX_2409
);
UXCntl_Unit_VALB_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y20",
PATHPULSE => 638 ps
)
port map (
I => SW_4_IBUF_1749,
O => UXCntl_Unit_VALB_5_DYMUX_2404
);
UXCntl_Unit_VALB_5_CLKINV : X_INV
generic map(
LOC => "SLICE_X64Y20",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB_cmp_eq0000_0,
O => UXCntl_Unit_VALB_5_CLKINVNOT
);
UXCntl_Unit_VALB_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y21",
PATHPULSE => 638 ps
)
port map (
I => SW_7_IBUF_1753,
O => UXCntl_Unit_VALB_7_DXMUX_2425
);
UXCntl_Unit_VALB_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y21",
PATHPULSE => 638 ps
)
port map (
I => SW_6_IBUF_1754,
O => UXCntl_Unit_VALB_7_DYMUX_2420
);
UXCntl_Unit_VALB_7_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y21",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB_cmp_eq0000_0,
O => UXCntl_Unit_VALB_7_CLKINVNOT
);
Load_Store_Unit_w_en_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y30",
PATHPULSE => 638 ps
)
port map (
I => Load_Store_Unit_w_en,
O => Load_Store_Unit_w_en_0
);
Load_Store_Unit_w_en_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y30",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_arith_cmp_eq0000,
O => Arith_Unit_arith_cmp_eq0000_0
);
Arith_Unit_arith_cmp_eq00002 : X_LUT4
generic map(
INIT => X"0022",
LOC => "SLICE_X64Y30"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(0),
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => VCC,
ADR3 => UXCntl_Unit_OPCODE(1),
O => Arith_Unit_arith_cmp_eq0000
);
SSeg_Mrom_segnum111 : X_LUT4
generic map(
INIT => X"CA28",
LOC => "SLICE_X67Y48"
)
port map (
ADR0 => SSeg_hexnum(2),
ADR1 => SSeg_hexnum(3),
ADR2 => SSeg_hexnum(0),
ADR3 => SSeg_hexnum(1),
O => SEG_1_OBUF_2467
);
BTN_2_OUTPUT_not0001_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000,
O => BTN_2_Count_and0000_0
);
BTN_2_Count_and00001 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X64Y68"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_D_STATE(1),
ADR2 => VCC,
ADR3 => BTN_2_D_STATE(0),
O => BTN_2_Count_and0000
);
UXCntl_Unit_OPCODE_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X64Y39",
PATHPULSE => 638 ps
)
port map (
I => SW_1_IBUF_1740,
O => UXCntl_Unit_OPCODE_1_DXMUX_2513
);
UXCntl_Unit_OPCODE_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y39",
PATHPULSE => 638 ps
)
port map (
I => SW_0_IBUF_1741,
O => UXCntl_Unit_OPCODE_1_DYMUX_2508
);
UXCntl_Unit_OPCODE_1_CLKINV : X_INV
generic map(
LOC => "SLICE_X64Y39",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_OPCODE_cmp_eq0000_0,
O => UXCntl_Unit_OPCODE_1_CLKINVNOT
);
UXCntl_Unit_OPCODE_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y36",
PATHPULSE => 638 ps
)
port map (
I => SW_3_IBUF_1743,
O => UXCntl_Unit_OPCODE_3_DXMUX_2529
);
UXCntl_Unit_OPCODE_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y36",
PATHPULSE => 638 ps
)
port map (
I => SW_2_IBUF_1744,
O => UXCntl_Unit_OPCODE_3_DYMUX_2524
);
UXCntl_Unit_OPCODE_3_CLKINV : X_INV
generic map(
LOC => "SLICE_X65Y36",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_OPCODE_cmp_eq0000_0,
O => UXCntl_Unit_OPCODE_3_CLKINVNOT
);
SSeg_Mmux_hexnum_mux00014201_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y30",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014201_2554,
O => SSeg_Mmux_hexnum_mux00014201_0
);
SSeg_Mmux_hexnum_mux00014201_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y30",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux000126_2547,
O => SSeg_Mmux_hexnum_mux000126_0
);
SSeg_Mmux_hexnum_mux000126 : X_LUT4
generic map(
INIT => X"A8A0",
LOC => "SLICE_X66Y30"
)
port map (
ADR0 => UXCntl_Unit_VALA(0),
ADR1 => N28,
ADR2 => N21,
ADR3 => UXCntl_Unit_VALB(0),
O => SSeg_Mmux_hexnum_mux000126_2547
);
SSeg_Mmux_hexnum_mux0001422_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y36",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001422_2578,
O => SSeg_Mmux_hexnum_mux0001422_0
);
SSeg_Mmux_hexnum_mux0001422_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y36",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux000146_2570,
O => SSeg_Mmux_hexnum_mux000146_0
);
SSeg_Mmux_hexnum_mux000146 : X_LUT4
generic map(
INIT => X"A888",
LOC => "SLICE_X66Y36"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => N21,
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => N28,
O => SSeg_Mmux_hexnum_mux000146_2570
);
SSeg_Mmux_hexnum_mux0001476_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y30",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001476_2602,
O => SSeg_Mmux_hexnum_mux0001476_0
);
SSeg_Mmux_hexnum_mux0001476_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y30",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux000166_2594,
O => SSeg_Mmux_hexnum_mux000166_0
);
SSeg_Mmux_hexnum_mux000166 : X_LUT4
generic map(
INIT => X"E0C0",
LOC => "SLICE_X67Y30"
)
port map (
ADR0 => UXCntl_Unit_VALB(2),
ADR1 => N21,
ADR2 => UXCntl_Unit_VALA(2),
ADR3 => N28,
O => SSeg_Mmux_hexnum_mux000166_2594
);
SSeg_Mmux_hexnum_mux00016157_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y26",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016157_2626,
O => SSeg_Mmux_hexnum_mux00016157_0
);
SSeg_Mmux_hexnum_mux00016157_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y26",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux000186_2619,
O => SSeg_Mmux_hexnum_mux000186_0
);
SSeg_Mmux_hexnum_mux000186 : X_LUT4
generic map(
INIT => X"C8C0",
LOC => "SLICE_X66Y26"
)
port map (
ADR0 => UXCntl_Unit_VALB(3),
ADR1 => UXCntl_Unit_VALA(3),
ADR2 => N21,
ADR3 => N28,
O => SSeg_Mmux_hexnum_mux000186_2619
);
UXCntl_Unit_OPCODE_cmp_eq0000_XUSED : X_BUF
generic map(
LOC => "SLICE_X54Y52",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_OPCODE_cmp_eq0000,
O => UXCntl_Unit_OPCODE_cmp_eq0000_0
);
UXCntl_Unit_OPCODE_cmp_eq0000_YUSED : X_BUF
generic map(
LOC => "SLICE_X54Y52",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA_cmp_eq0000,
O => UXCntl_Unit_VALA_cmp_eq0000_0
);
UXCntl_Unit_VALA_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0004",
LOC => "SLICE_X54Y52"
)
port map (
ADR0 => BTN_0_OUTPUT_1789,
ADR1 => BTN_3_OUTPUT_1790,
ADR2 => BTN_1_OUTPUT_1792,
ADR3 => BTN_2_OUTPUT_1791,
O => UXCntl_Unit_VALA_cmp_eq0000
);
SSeg_clk240hz_DYMUX : X_INV
generic map(
LOC => "SLICE_X34Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_clk240hz_DYMUX_2660
);
SSeg_clk240hz_CLKINV : X_BUF
generic map(
LOC => "SLICE_X34Y22",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_clk240hz_CLKINV_2658
);
SSeg_clk240hz_CEINV : X_BUF
generic map(
LOC => "SLICE_X34Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000,
O => SSeg_clk240hz_CEINV_2657
);
SSeg_Mmux_hexnum_mux0001222_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y37",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001222_2686,
O => SSeg_Mmux_hexnum_mux0001222_0
);
SSeg_Mmux_hexnum_mux0001222_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y37",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001219_pack_1,
O => SSeg_Mmux_hexnum_mux0001219_1796
);
SSeg_Mmux_hexnum_mux0001219 : X_LUT4
generic map(
INIT => X"2220",
LOC => "SLICE_X66Y37"
)
port map (
ADR0 => N26_0,
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => UXCntl_Unit_VALA(0),
ADR3 => UXCntl_Unit_VALB(0),
O => SSeg_Mmux_hexnum_mux0001219_pack_1
);
N82_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y34",
PATHPULSE => 638 ps
)
port map (
I => N82,
O => N82_0
);
N82_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y34",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001417_2702,
O => SSeg_Mmux_hexnum_mux0001417_0
);
SSeg_Mmux_hexnum_mux0001417 : X_LUT4
generic map(
INIT => X"4400",
LOC => "SLICE_X67Y34"
)
port map (
ADR0 => UXCntl_Unit_VALB(1),
ADR1 => UXCntl_Unit_VALA(0),
ADR2 => VCC,
ADR3 => N25,
O => SSeg_Mmux_hexnum_mux0001417_2702
);
SSeg_Mmux_hexnum_mux00012111_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y35",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012111_2734,
O => SSeg_Mmux_hexnum_mux00012111_0
);
SSeg_Mmux_hexnum_mux00012111_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y35",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001285_pack_1,
O => SSeg_Mmux_hexnum_mux0001285_1805
);
SSeg_Mmux_hexnum_mux0001285 : X_LUT4
generic map(
INIT => X"FAF8",
LOC => "SLICE_X67Y35"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => N82_0,
ADR2 => SSeg_Mmux_hexnum_mux0001257,
ADR3 => SSeg_Mmux_hexnum_mux0001278_0,
O => SSeg_Mmux_hexnum_mux0001285_pack_1
);
SSeg_Mmux_hexnum_mux0001655_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y31",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001655_2758,
O => SSeg_Mmux_hexnum_mux0001655_0
);
SSeg_Mmux_hexnum_mux0001655_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y31",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001643_pack_1,
O => SSeg_Mmux_hexnum_mux0001643_1810
);
SSeg_Mmux_hexnum_mux0001643 : X_LUT4
generic map(
INIT => X"0200",
LOC => "SLICE_X64Y31"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(0),
ADR1 => UXCntl_Unit_OPCODE(3),
ADR2 => N88_0,
ADR3 => UXCntl_Unit_OPCODE(1),
O => SSeg_Mmux_hexnum_mux0001643_pack_1
);
SSeg_Mmux_hexnum_mux0001845_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y26",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001845_2782,
O => SSeg_Mmux_hexnum_mux0001845_0
);
SSeg_Mmux_hexnum_mux0001845_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y26",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001834_pack_1,
O => SSeg_Mmux_hexnum_mux0001834_1814
);
SSeg_Mmux_hexnum_mux0001834 : X_LUT4
generic map(
INIT => X"2000",
LOC => "SLICE_X67Y26"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux0001828,
ADR1 => UXCntl_Unit_OPCODE(3),
ADR2 => UXCntl_Unit_OPCODE(1),
ADR3 => UXCntl_Unit_OPCODE(0),
O => SSeg_Mmux_hexnum_mux0001834_pack_1
);
SSeg_Mmux_hexnum_mux00014256_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014256_2806,
O => SSeg_Mmux_hexnum_mux00014256_0
);
SSeg_Mmux_hexnum_mux00014256_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001860_2799,
O => SSeg_Mmux_hexnum_mux0001860_0
);
SSeg_Mmux_hexnum_mux0001860 : X_LUT4
generic map(
INIT => X"EAC0",
LOC => "SLICE_X66Y20"
)
port map (
ADR0 => N24,
ADR1 => UXCntl_Unit_VALA(5),
ADR2 => N22,
ADR3 => UXCntl_Unit_VALA(6),
O => SSeg_Mmux_hexnum_mux0001860_2799
);
N78_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y21",
PATHPULSE => 638 ps
)
port map (
I => N78,
O => N78_0
);
N78_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014272,
O => SSeg_Mmux_hexnum_mux00014272_0
);
SSeg_Mmux_hexnum_mux0001864 : X_LUT4
generic map(
INIT => X"0020",
LOC => "SLICE_X66Y21"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => UXCntl_Unit_VALA(4),
ADR3 => UXCntl_Unit_VALB(2),
O => SSeg_Mmux_hexnum_mux00014272
);
SSeg_Mmux_hexnum_mux0001878_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001878_2854,
O => SSeg_Mmux_hexnum_mux0001878_0
);
SSeg_Mmux_hexnum_mux0001878_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001866_pack_1,
O => SSeg_Mmux_hexnum_mux0001866_1823
);
SSeg_Mmux_hexnum_mux0001866 : X_LUT4
generic map(
INIT => X"FCCC",
LOC => "SLICE_X66Y22"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Mmux_hexnum_mux00014272_0,
ADR2 => UXCntl_Unit_VALA(7),
ADR3 => N27_0,
O => SSeg_Mmux_hexnum_mux0001866_pack_1
);
N80_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y24",
PATHPULSE => 638 ps
)
port map (
I => N80,
O => N80_0
);
N80_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y24",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012205_2871,
O => SSeg_Mmux_hexnum_mux00012205_0
);
SSeg_Mmux_hexnum_mux00012205 : X_LUT4
generic map(
INIT => X"3330",
LOC => "SLICE_X64Y24"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => UXCntl_Unit_VALA(4),
ADR3 => UXCntl_Unit_VALB(4),
O => SSeg_Mmux_hexnum_mux00012205_2871
);
SSeg_Mmux_hexnum_mux00012263_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y29",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012263_2902,
O => SSeg_Mmux_hexnum_mux00012263_0
);
SSeg_Mmux_hexnum_mux00012263_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y29",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012253_pack_1,
O => SSeg_Mmux_hexnum_mux00012253_1829
);
SSeg_Mmux_hexnum_mux00012253 : X_LUT4
generic map(
INIT => X"ECA0",
LOC => "SLICE_X64Y29"
)
port map (
ADR0 => N30,
ADR1 => N26_0,
ADR2 => arith(4),
ADR3 => SSeg_Mmux_hexnum_mux00012229_0,
O => SSeg_Mmux_hexnum_mux00012253_pack_1
);
SSeg_Mmux_hexnum_mux00012229_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y24",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012229_2926,
O => SSeg_Mmux_hexnum_mux00012229_0
);
SSeg_Mmux_hexnum_mux00012229_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y24",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012196_pack_1,
O => SSeg_Mmux_hexnum_mux00012196_1833
);
SSeg_Mmux_hexnum_mux00012196 : X_LUT4
generic map(
INIT => X"EAC0",
LOC => "SLICE_X66Y24"
)
port map (
ADR0 => UXCntl_Unit_VALA(0),
ADR1 => UXCntl_Unit_VALA(2),
ADR2 => N22,
ADR3 => N27_0,
O => SSeg_Mmux_hexnum_mux00012196_pack_1
);
SSeg_Mmux_hexnum_mux00018143_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y24",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018143_2950,
O => SSeg_Mmux_hexnum_mux00018143_0
);
SSeg_Mmux_hexnum_mux00018143_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y24",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014224_2943,
O => SSeg_Mmux_hexnum_mux00014224_0
);
SSeg_Mmux_hexnum_mux00014224 : X_LUT4
generic map(
INIT => X"6420",
LOC => "SLICE_X65Y24"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => UXCntl_Unit_VALA(6),
ADR3 => UXCntl_Unit_VALA(7),
O => SSeg_Mmux_hexnum_mux00014224_2943
);
N62_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y27",
PATHPULSE => 638 ps
)
port map (
I => N62,
O => N62_0
);
N62_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y27",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016107_pack_1,
O => SSeg_Mmux_hexnum_mux00016107_1838
);
SSeg_Mmux_hexnum_mux00016107 : X_LUT4
generic map(
INIT => X"AA88",
LOC => "SLICE_X67Y27"
)
port map (
ADR0 => N23,
ADR1 => SSeg_Mmux_hexnum_mux0001686,
ADR2 => VCC,
ADR3 => SSeg_Mmux_hexnum_mux0001669_0,
O => SSeg_Mmux_hexnum_mux00016107_pack_1
);
BTN_0_Count_and0000_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000,
O => BTN_0_Count_and0000_0
);
BTN_0_OUTPUT_not00011 : X_LUT4
generic map(
INIT => X"8822",
LOC => "SLICE_X66Y84"
)
port map (
ADR0 => BTN_0_Count(20),
ADR1 => BTN_0_D_STATE(0),
ADR2 => VCC,
ADR3 => BTN_0_D_STATE(1),
O => BTN_0_OUTPUT_not0001
);
SSeg_Mmux_hexnum_mux00018120_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y32",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018120_3022,
O => SSeg_Mmux_hexnum_mux00018120_0
);
SSeg_Mmux_hexnum_mux00018120_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y32",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016180_3013,
O => SSeg_Mmux_hexnum_mux00016180_0
);
SSeg_Mmux_hexnum_mux00016180 : X_LUT4
generic map(
INIT => X"FFEC",
LOC => "SLICE_X66Y32"
)
port map (
ADR0 => N31,
ADR1 => SSeg_Mmux_hexnum_mux00016175,
ADR2 => Load_Store_Unit_reg(6),
ADR3 => SSeg_Mmux_hexnum_mux00016157_0,
O => SSeg_Mmux_hexnum_mux00016180_3013
);
SSeg_Mmux_hexnum_mux00016289_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016289_3046,
O => SSeg_Mmux_hexnum_mux00016289_0
);
SSeg_Mmux_hexnum_mux00016289_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016263_pack_1,
O => SSeg_Mmux_hexnum_mux00016263_1853
);
SSeg_Mmux_hexnum_mux00016263 : X_LUT4
generic map(
INIT => X"AAFC",
LOC => "SLICE_X64Y28"
)
port map (
ADR0 => N68,
ADR1 => UXCntl_Unit_VALA(6),
ADR2 => UXCntl_Unit_VALB(6),
ADR3 => UXCntl_Unit_OPCODE(2),
O => SSeg_Mmux_hexnum_mux00016263_pack_1
);
N26_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y26",
PATHPULSE => 638 ps
)
port map (
I => N26,
O => N26_0
);
N26_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y26",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018124_3062,
O => SSeg_Mmux_hexnum_mux00018124_0
);
SSeg_Mmux_hexnum_mux00018124 : X_LUT4
generic map(
INIT => X"0020",
LOC => "SLICE_X64Y26"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(1),
ADR1 => UXCntl_Unit_OPCODE(0),
ADR2 => UXCntl_Unit_VALB(7),
ADR3 => UXCntl_Unit_OPCODE(3),
O => SSeg_Mmux_hexnum_mux00018124_3062
);
SSeg_Mmux_hexnum_mux00018252_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y25",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018252_3094,
O => SSeg_Mmux_hexnum_mux00018252_0
);
SSeg_Mmux_hexnum_mux00018252_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y25",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018240_pack_1,
O => SSeg_Mmux_hexnum_mux00018240_1857
);
SSeg_Mmux_hexnum_mux00018240 : X_LUT4
generic map(
INIT => X"1000",
LOC => "SLICE_X64Y25"
)
port map (
ADR0 => N80_0,
ADR1 => UXCntl_Unit_OPCODE(3),
ADR2 => UXCntl_Unit_OPCODE(0),
ADR3 => UXCntl_Unit_OPCODE(1),
O => SSeg_Mmux_hexnum_mux00018240_pack_1
);
BTN_3_OUTPUT_not0001_YUSED : X_BUF
generic map(
LOC => "SLICE_X53Y60",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000,
O => BTN_3_Count_and0000_0
);
BTN_3_Count_and00001 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X53Y60"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_3_D_STATE(0),
ADR3 => BTN_3_D_STATE(1),
O => BTN_3_Count_and0000
);
SSeg_DP_OUT_DYMUX : X_BUF
generic map(
LOC => "SLICE_X66Y39",
PATHPULSE => 638 ps
)
port map (
I => SSeg_DP_OUT_BYINV_3125,
O => SSeg_DP_OUT_DYMUX_3126
);
SSeg_DP_OUT_BYINV : X_BUF
generic map(
LOC => "SLICE_X66Y39",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => SSeg_DP_OUT_BYINV_3125
);
SSeg_DP_OUT_CLKINV : X_BUF
generic map(
LOC => "SLICE_X66Y39",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_DP_OUT_CLKINV_3124
);
N88_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y30",
PATHPULSE => 638 ps
)
port map (
I => N88,
O => N88_0
);
N88_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y30",
PATHPULSE => 638 ps
)
port map (
I => N92_pack_1,
O => N92
);
SSeg_Mmux_hexnum_mux0001643_SW0_SW0 : X_LUT4
generic map(
INIT => X"F53F",
LOC => "SLICE_X65Y30"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => UXCntl_Unit_VALA(0),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALB(0),
O => N92_pack_1
);
Load_Store_Unit_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y36",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(1),
O => Load_Store_Unit_reg_1_DXMUX_3169
);
Load_Store_Unit_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y36",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(0),
O => Load_Store_Unit_reg_1_DYMUX_3163
);
Load_Store_Unit_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y36",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => Load_Store_Unit_reg_1_CLKINV_3161
);
Load_Store_Unit_reg_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X67Y36",
PATHPULSE => 638 ps
)
port map (
I => Load_Store_Unit_w_en_0,
O => Load_Store_Unit_reg_1_CEINV_3160
);
Load_Store_Unit_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y31",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(3),
O => Load_Store_Unit_reg_3_DXMUX_3189
);
Load_Store_Unit_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y31",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(2),
O => Load_Store_Unit_reg_3_DYMUX_3183
);
Load_Store_Unit_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y31",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => Load_Store_Unit_reg_3_CLKINV_3181
);
Load_Store_Unit_reg_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X65Y31",
PATHPULSE => 638 ps
)
port map (
I => Load_Store_Unit_w_en_0,
O => Load_Store_Unit_reg_3_CEINV_3180
);
Load_Store_Unit_reg_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X64Y32",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(5),
O => Load_Store_Unit_reg_5_DXMUX_3209
);
Load_Store_Unit_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y32",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(4),
O => Load_Store_Unit_reg_5_DYMUX_3203
);
Load_Store_Unit_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X64Y32",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => Load_Store_Unit_reg_5_CLKINV_3201
);
Load_Store_Unit_reg_5_CEINV : X_BUF
generic map(
LOC => "SLICE_X64Y32",
PATHPULSE => 638 ps
)
port map (
I => Load_Store_Unit_w_en_0,
O => Load_Store_Unit_reg_5_CEINV_3200
);
Load_Store_Unit_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y32",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(7),
O => Load_Store_Unit_reg_7_DXMUX_3229
);
Load_Store_Unit_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y32",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(6),
O => Load_Store_Unit_reg_7_DYMUX_3223
);
Load_Store_Unit_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y32",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => Load_Store_Unit_reg_7_CLKINV_3221
);
Load_Store_Unit_reg_7_CEINV : X_BUF
generic map(
LOC => "SLICE_X67Y32",
PATHPULSE => 638 ps
)
port map (
I => Load_Store_Unit_w_en_0,
O => Load_Store_Unit_reg_7_CEINV_3220
);
BTN_0_D_STATE_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_D_STATE(0),
O => BTN_0_D_STATE_1_DXMUX_3246
);
BTN_0_D_STATE_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_INBUF,
O => BTN_0_D_STATE_1_DYMUX_3241
);
BTN_0_D_STATE_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y85",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_D_STATE_1_CLKINV_3239
);
SSeg_Mmux_hexnum_mux00014147_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y37",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014147_3271,
O => SSeg_Mmux_hexnum_mux00014147_0
);
SSeg_Mmux_hexnum_mux00014147_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y37",
PATHPULSE => 638 ps
)
port map (
I => N74_pack_1,
O => N74
);
SSeg_Mmux_hexnum_mux00014147_SW0 : X_LUT4
generic map(
INIT => X"FEEE",
LOC => "SLICE_X67Y37"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux000146_0,
ADR1 => SSeg_Mmux_hexnum_mux00014135_0,
ADR2 => N31,
ADR3 => Load_Store_Unit_reg(1),
O => N74_pack_1
);
SSeg_Mmux_hexnum_mux00014346_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y27",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014346_3295,
O => SSeg_Mmux_hexnum_mux00014346_0
);
SSeg_Mmux_hexnum_mux00014346_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y27",
PATHPULSE => 638 ps
)
port map (
I => N76_pack_1,
O => N76
);
SSeg_Mmux_hexnum_mux00014346_SW0 : X_LUT4
generic map(
INIT => X"AEAA",
LOC => "SLICE_X66Y27"
)
port map (
ADR0 => N90_0,
ADR1 => SSeg_Mmux_hexnum_mux00014224_0,
ADR2 => UXCntl_Unit_VALB(2),
ADR3 => N23,
O => N76_pack_1
);
SSeg_Mrom_segnum21 : X_LUT4
generic map(
INIT => X"B002",
LOC => "SLICE_X67Y63"
)
port map (
ADR0 => SSeg_hexnum(1),
ADR1 => SSeg_hexnum(0),
ADR2 => SSeg_hexnum(3),
ADR3 => SSeg_hexnum(2),
O => SEG_2_OBUF_3312
);
SSeg_Mrom_segnum41 : X_LUT4
generic map(
INIT => X"0C4E",
LOC => "SLICE_X67Y52"
)
port map (
ADR0 => SSeg_hexnum(2),
ADR1 => SSeg_hexnum(0),
ADR2 => SSeg_hexnum(3),
ADR3 => SSeg_hexnum(1),
O => SEG_4_OBUF_3336
);
SSeg_Mrom_segnum61 : X_LUT4
generic map(
INIT => X"2019",
LOC => "SLICE_X66Y63"
)
port map (
ADR0 => SSeg_hexnum(2),
ADR1 => SSeg_hexnum(3),
ADR2 => SSeg_hexnum(0),
ADR3 => SSeg_hexnum(1),
O => SEG_6_OBUF_3355
);
BTN_1_D_STATE_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X64Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_D_STATE(0),
O => BTN_1_D_STATE_1_DXMUX_3370
);
BTN_1_D_STATE_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_INBUF,
O => BTN_1_D_STATE_1_DYMUX_3365
);
BTN_1_D_STATE_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X64Y80",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_D_STATE_1_CLKINV_3363
);
UXCntl_Unit_VALB_cmp_eq0000_YUSED : X_BUF
generic map(
LOC => "SLICE_X55Y52",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB_cmp_eq0000,
O => UXCntl_Unit_VALB_cmp_eq0000_0
);
UXCntl_Unit_VALB_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0002",
LOC => "SLICE_X55Y52"
)
port map (
ADR0 => BTN_2_OUTPUT_1791,
ADR1 => BTN_0_OUTPUT_1789,
ADR2 => BTN_3_OUTPUT_1790,
ADR3 => BTN_1_OUTPUT_1792,
O => UXCntl_Unit_VALB_cmp_eq0000
);
BTN_2_D_STATE_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X64Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_D_STATE(0),
O => BTN_2_D_STATE_1_DXMUX_3398
);
BTN_2_D_STATE_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_INBUF,
O => BTN_2_D_STATE_1_DYMUX_3393
);
BTN_2_D_STATE_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X64Y69",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_D_STATE_1_CLKINV_3391
);
BTN_3_D_STATE_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X52Y60",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_D_STATE(0),
O => BTN_3_D_STATE_1_DXMUX_3414
);
BTN_3_D_STATE_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X52Y60",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_INBUF,
O => BTN_3_D_STATE_1_DYMUX_3409
);
BTN_3_D_STATE_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X52Y60",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_D_STATE_1_CLKINV_3407
);
SSeg_pos_0_DXMUX : X_INV
generic map(
LOC => "SLICE_X67Y39",
PATHPULSE => 638 ps
)
port map (
I => SSeg_pos(0),
O => SSeg_pos_0_DXMUX_3439
);
SSeg_pos_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y39",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_pos1,
O => SSeg_pos_0_DYMUX_3434
);
SSeg_pos_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y39",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_pos_0_CLKINV_3424
);
SSeg_Mcount_pos_xor_1_11 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X67Y39"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_pos(0),
ADR2 => VCC,
ADR3 => SSeg_pos(1),
O => SSeg_Mcount_pos1
);
SSeg_Mmux_hexnum_mux00012181_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y32",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012181_3464,
O => SSeg_Mmux_hexnum_mux00012181_0
);
SSeg_Mmux_hexnum_mux00012181_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y32",
PATHPULSE => 638 ps
)
port map (
I => N31_pack_1,
O => N31
);
ALU_Mux_ALU_OUT_0_101 : X_LUT4
generic map(
INIT => X"CCC8",
LOC => "SLICE_X65Y32"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(1),
ADR1 => UXCntl_Unit_OPCODE(3),
ADR2 => UXCntl_Unit_OPCODE(0),
ADR3 => UXCntl_Unit_OPCODE(2),
O => N31_pack_1
);
BTN_1_OUTPUT_not0001_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000,
O => BTN_1_Count_and0000_0
);
BTN_1_Count_and00001 : X_LUT4
generic map(
INIT => X"55AA",
LOC => "SLICE_X65Y80"
)
port map (
ADR0 => BTN_1_D_STATE(0),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_1_D_STATE(1),
O => BTN_1_Count_and0000
);
SSeg_Mmux_hexnum_mux00012226_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y25",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012226_3512,
O => SSeg_Mmux_hexnum_mux00012226_0
);
SSeg_Mmux_hexnum_mux00012226_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y25",
PATHPULSE => 638 ps
)
port map (
I => N25_pack_1,
O => N25
);
ALU_Mux_ALU_OUT_4_121 : X_LUT4
generic map(
INIT => X"0A00",
LOC => "SLICE_X66Y25"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => VCC,
ADR2 => UXCntl_Unit_VALB(2),
ADR3 => UXCntl_Unit_OPCODE(2),
O => N25_pack_1
);
SSeg_Mmux_hexnum_mux0001825_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y23",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001825_3536,
O => SSeg_Mmux_hexnum_mux0001825_0
);
SSeg_Mmux_hexnum_mux0001825_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y23",
PATHPULSE => 638 ps
)
port map (
I => N22_pack_1,
O => N22
);
ALU_Mux_ALU_OUT_5_111 : X_LUT4
generic map(
INIT => X"0404",
LOC => "SLICE_X66Y23"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => UXCntl_Unit_VALB(2),
ADR3 => VCC,
O => N22_pack_1
);
SSeg_Mmux_hexnum_mux0001669_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001669_3560,
O => SSeg_Mmux_hexnum_mux0001669_0
);
SSeg_Mmux_hexnum_mux0001669_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y21",
PATHPULSE => 638 ps
)
port map (
I => N24_pack_1,
O => N24
);
ALU_Mux_ALU_OUT_5_121 : X_LUT4
generic map(
INIT => X"3000",
LOC => "SLICE_X67Y21"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALB(0),
O => N24_pack_1
);
SSeg_Mmux_hexnum_mux00018187_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018187_3584,
O => SSeg_Mmux_hexnum_mux00018187_0
);
SSeg_Mmux_hexnum_mux00018187_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y22",
PATHPULSE => 638 ps
)
port map (
I => N12_pack_2,
O => N12
);
ALU_Mux_ALU_OUT_6_111 : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X65Y22"
)
port map (
ADR0 => UXCntl_Unit_VALA(2),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => UXCntl_Unit_VALA(0),
ADR3 => VCC,
O => N12_pack_2
);
SSeg_Mmux_hexnum_mux00014135_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y29",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014135_3608,
O => SSeg_Mmux_hexnum_mux00014135_0
);
SSeg_Mmux_hexnum_mux00014135_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y29",
PATHPULSE => 638 ps
)
port map (
I => N23_pack_1,
O => N23
);
ALU_Mux_ALU_OUT_0_61 : X_LUT4
generic map(
INIT => X"0010",
LOC => "SLICE_X66Y29"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(0),
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => UXCntl_Unit_OPCODE(3),
ADR3 => UXCntl_Unit_OPCODE(1),
O => N23_pack_1
);
SSeg_Mmux_hexnum_mux00012151_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y27",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012151_3632,
O => SSeg_Mmux_hexnum_mux00012151_0
);
SSeg_Mmux_hexnum_mux00012151_YUSED : X_BUF
generic map(
LOC => "SLICE_X64Y27",
PATHPULSE => 638 ps
)
port map (
I => N28_pack_1,
O => N28
);
ALU_Mux_ALU_OUT_0_81 : X_LUT4
generic map(
INIT => X"0022",
LOC => "SLICE_X64Y27"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(1),
ADR1 => UXCntl_Unit_OPCODE(0),
ADR2 => VCC,
ADR3 => UXCntl_Unit_OPCODE(3),
O => N28_pack_1
);
N90_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y33",
PATHPULSE => 638 ps
)
port map (
I => N90,
O => N90_0
);
N90_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y33",
PATHPULSE => 638 ps
)
port map (
I => N30_pack_1,
O => N30
);
ALU_Mux_ALU_OUT_0_91 : X_LUT4
generic map(
INIT => X"0023",
LOC => "SLICE_X67Y33"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(0),
ADR1 => UXCntl_Unit_OPCODE(3),
ADR2 => UXCntl_Unit_OPCODE(2),
ADR3 => UXCntl_Unit_OPCODE(1),
O => N30_pack_1
);
SSeg_Mmux_hexnum_mux0001278_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y34",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001278_3680,
O => SSeg_Mmux_hexnum_mux0001278_0
);
SSeg_Mmux_hexnum_mux0001278_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y34",
PATHPULSE => 638 ps
)
port map (
I => N11_pack_2,
O => N11
);
ALU_Mux_ALU_OUT_4_21 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X66Y34"
)
port map (
ADR0 => UXCntl_Unit_VALA(5),
ADR1 => VCC,
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALA(7),
O => N11_pack_2
);
BTN_0_OUTPUT_DYMUX : X_BUF
generic map(
LOC => "SLICE_X66Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_D_STATE(1),
O => BTN_0_OUTPUT_DYMUX_3690
);
BTN_0_OUTPUT_CLKINV : X_BUF
generic map(
LOC => "SLICE_X66Y85",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_OUTPUT_CLKINV_3688
);
BTN_0_OUTPUT_CEINV : X_BUF
generic map(
LOC => "SLICE_X66Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_OUTPUT_not0001,
O => BTN_0_OUTPUT_CEINV_3687
);
BTN_1_Count_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y70"
)
port map (
O => BTN_1_Count_0_LOGIC_ZERO_3717
);
BTN_1_Count_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X67Y70"
)
port map (
O => BTN_1_Count_0_LOGIC_ONE_3740
);
BTN_1_Count_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_0_XORF_3741,
O => BTN_1_Count_0_DXMUX_3743
);
BTN_1_Count_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y70"
)
port map (
I0 => BTN_1_Count_0_CYINIT_3739,
I1 => BTN_1_Mcount_Count_lut(0),
O => BTN_1_Count_0_XORF_3741
);
BTN_1_Count_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y70"
)
port map (
IA => BTN_1_Count_0_LOGIC_ONE_3740,
IB => BTN_1_Count_0_CYINIT_3739,
SEL => BTN_1_Count_0_CYSELF_3730,
O => BTN_1_Mcount_Count_cy(0)
);
BTN_1_Count_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_0_BXINV_3728,
O => BTN_1_Count_0_CYINIT_3739
);
BTN_1_Count_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_lut(0),
O => BTN_1_Count_0_CYSELF_3730
);
BTN_1_Count_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => BTN_1_Count_0_BXINV_3728
);
BTN_1_Count_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_0_XORG_3720,
O => BTN_1_Count_0_DYMUX_3722
);
BTN_1_Count_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y70"
)
port map (
I0 => BTN_1_Mcount_Count_cy(0),
I1 => BTN_1_Count_0_G,
O => BTN_1_Count_0_XORG_3720
);
BTN_1_Count_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_0_CYMUXG_3719,
O => BTN_1_Mcount_Count_cy(1)
);
BTN_1_Count_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X67Y70"
)
port map (
IA => BTN_1_Count_0_LOGIC_ZERO_3717,
IB => BTN_1_Mcount_Count_cy(0),
SEL => BTN_1_Count_0_CYSELG_3708,
O => BTN_1_Count_0_CYMUXG_3719
);
BTN_1_Count_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_0_G,
O => BTN_1_Count_0_CYSELG_3708
);
BTN_1_Count_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_0_SRINV_3706
);
BTN_1_Count_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_0_CLKINV_3705
);
BTN_1_Count_0_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_0_CEINVNOT
);
BTN_1_OUTPUT_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_D_STATE(1),
O => BTN_1_OUTPUT_DYMUX_3756
);
BTN_1_OUTPUT_CLKINV : X_BUF
generic map(
LOC => "SLICE_X64Y81",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_OUTPUT_CLKINV_3754
);
BTN_1_OUTPUT_CEINV : X_BUF
generic map(
LOC => "SLICE_X64Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_OUTPUT_not0001,
O => BTN_1_OUTPUT_CEINV_3753
);
BTN_1_Count_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y71"
)
port map (
O => BTN_1_Count_2_LOGIC_ZERO_3783
);
BTN_1_Count_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_2_XORF_3809,
O => BTN_1_Count_2_DXMUX_3811
);
BTN_1_Count_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
I0 => BTN_1_Count_2_CYINIT_3808,
I1 => BTN_1_Count_2_F,
O => BTN_1_Count_2_XORF_3809
);
BTN_1_Count_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
IA => BTN_1_Count_2_LOGIC_ZERO_3783,
IB => BTN_1_Count_2_CYINIT_3808,
SEL => BTN_1_Count_2_CYSELF_3789,
O => BTN_1_Mcount_Count_cy(2)
);
BTN_1_Count_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
IA => BTN_1_Count_2_LOGIC_ZERO_3783,
IB => BTN_1_Count_2_LOGIC_ZERO_3783,
SEL => BTN_1_Count_2_CYSELF_3789,
O => BTN_1_Count_2_CYMUXF2_3784
);
BTN_1_Count_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(1),
O => BTN_1_Count_2_CYINIT_3808
);
BTN_1_Count_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_2_F,
O => BTN_1_Count_2_CYSELF_3789
);
BTN_1_Count_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_2_XORG_3791,
O => BTN_1_Count_2_DYMUX_3793
);
BTN_1_Count_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
I0 => BTN_1_Mcount_Count_cy(2),
I1 => BTN_1_Count_2_G,
O => BTN_1_Count_2_XORG_3791
);
BTN_1_Count_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_2_CYMUXFAST_3788,
O => BTN_1_Mcount_Count_cy(3)
);
BTN_1_Count_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(1),
O => BTN_1_Count_2_FASTCARRY_3786
);
BTN_1_Count_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
I0 => BTN_1_Count_2_CYSELG_3774,
I1 => BTN_1_Count_2_CYSELF_3789,
O => BTN_1_Count_2_CYAND_3787
);
BTN_1_Count_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
IA => BTN_1_Count_2_CYMUXG2_3785,
IB => BTN_1_Count_2_FASTCARRY_3786,
SEL => BTN_1_Count_2_CYAND_3787,
O => BTN_1_Count_2_CYMUXFAST_3788
);
BTN_1_Count_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y71"
)
port map (
IA => BTN_1_Count_2_LOGIC_ZERO_3783,
IB => BTN_1_Count_2_CYMUXF2_3784,
SEL => BTN_1_Count_2_CYSELG_3774,
O => BTN_1_Count_2_CYMUXG2_3785
);
BTN_1_Count_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_2_G,
O => BTN_1_Count_2_CYSELG_3774
);
BTN_1_Count_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_2_SRINV_3772
);
BTN_1_Count_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_2_CLKINV_3771
);
BTN_1_Count_2_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_2_CEINVNOT
);
BTN_2_OUTPUT_DYMUX : X_BUF
generic map(
LOC => "SLICE_X64Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_D_STATE(1),
O => BTN_2_OUTPUT_DYMUX_3824
);
BTN_2_OUTPUT_CLKINV : X_BUF
generic map(
LOC => "SLICE_X64Y66",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_OUTPUT_CLKINV_3822
);
BTN_2_OUTPUT_CEINV : X_BUF
generic map(
LOC => "SLICE_X64Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_OUTPUT_not0001,
O => BTN_2_OUTPUT_CEINV_3821
);
BTN_1_Count_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y72"
)
port map (
O => BTN_1_Count_4_LOGIC_ZERO_3851
);
BTN_1_Count_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_4_XORF_3877,
O => BTN_1_Count_4_DXMUX_3879
);
BTN_1_Count_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
I0 => BTN_1_Count_4_CYINIT_3876,
I1 => BTN_1_Count_4_F,
O => BTN_1_Count_4_XORF_3877
);
BTN_1_Count_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
IA => BTN_1_Count_4_LOGIC_ZERO_3851,
IB => BTN_1_Count_4_CYINIT_3876,
SEL => BTN_1_Count_4_CYSELF_3857,
O => BTN_1_Mcount_Count_cy(4)
);
BTN_1_Count_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
IA => BTN_1_Count_4_LOGIC_ZERO_3851,
IB => BTN_1_Count_4_LOGIC_ZERO_3851,
SEL => BTN_1_Count_4_CYSELF_3857,
O => BTN_1_Count_4_CYMUXF2_3852
);
BTN_1_Count_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(3),
O => BTN_1_Count_4_CYINIT_3876
);
BTN_1_Count_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_4_F,
O => BTN_1_Count_4_CYSELF_3857
);
BTN_1_Count_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_4_XORG_3859,
O => BTN_1_Count_4_DYMUX_3861
);
BTN_1_Count_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
I0 => BTN_1_Mcount_Count_cy(4),
I1 => BTN_1_Count_4_G,
O => BTN_1_Count_4_XORG_3859
);
BTN_1_Count_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_4_CYMUXFAST_3856,
O => BTN_1_Mcount_Count_cy(5)
);
BTN_1_Count_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(3),
O => BTN_1_Count_4_FASTCARRY_3854
);
BTN_1_Count_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
I0 => BTN_1_Count_4_CYSELG_3842,
I1 => BTN_1_Count_4_CYSELF_3857,
O => BTN_1_Count_4_CYAND_3855
);
BTN_1_Count_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
IA => BTN_1_Count_4_CYMUXG2_3853,
IB => BTN_1_Count_4_FASTCARRY_3854,
SEL => BTN_1_Count_4_CYAND_3855,
O => BTN_1_Count_4_CYMUXFAST_3856
);
BTN_1_Count_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y72"
)
port map (
IA => BTN_1_Count_4_LOGIC_ZERO_3851,
IB => BTN_1_Count_4_CYMUXF2_3852,
SEL => BTN_1_Count_4_CYSELG_3842,
O => BTN_1_Count_4_CYMUXG2_3853
);
BTN_1_Count_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_4_G,
O => BTN_1_Count_4_CYSELG_3842
);
BTN_1_Count_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_4_SRINV_3840
);
BTN_1_Count_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_4_CLKINV_3839
);
BTN_1_Count_4_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_4_CEINVNOT
);
BTN_3_OUTPUT_DYMUX : X_BUF
generic map(
LOC => "SLICE_X52Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_D_STATE(1),
O => BTN_3_OUTPUT_DYMUX_3892
);
BTN_3_OUTPUT_CLKINV : X_BUF
generic map(
LOC => "SLICE_X52Y61",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_OUTPUT_CLKINV_3890
);
BTN_3_OUTPUT_CEINV : X_BUF
generic map(
LOC => "SLICE_X52Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_OUTPUT_not0001,
O => BTN_3_OUTPUT_CEINV_3889
);
BTN_1_Count_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y73"
)
port map (
O => BTN_1_Count_6_LOGIC_ZERO_3919
);
BTN_1_Count_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_6_XORF_3945,
O => BTN_1_Count_6_DXMUX_3947
);
BTN_1_Count_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
I0 => BTN_1_Count_6_CYINIT_3944,
I1 => BTN_1_Count_6_F,
O => BTN_1_Count_6_XORF_3945
);
BTN_1_Count_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
IA => BTN_1_Count_6_LOGIC_ZERO_3919,
IB => BTN_1_Count_6_CYINIT_3944,
SEL => BTN_1_Count_6_CYSELF_3925,
O => BTN_1_Mcount_Count_cy(6)
);
BTN_1_Count_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
IA => BTN_1_Count_6_LOGIC_ZERO_3919,
IB => BTN_1_Count_6_LOGIC_ZERO_3919,
SEL => BTN_1_Count_6_CYSELF_3925,
O => BTN_1_Count_6_CYMUXF2_3920
);
BTN_1_Count_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(5),
O => BTN_1_Count_6_CYINIT_3944
);
BTN_1_Count_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_6_F,
O => BTN_1_Count_6_CYSELF_3925
);
BTN_1_Count_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_6_XORG_3927,
O => BTN_1_Count_6_DYMUX_3929
);
BTN_1_Count_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
I0 => BTN_1_Mcount_Count_cy(6),
I1 => BTN_1_Count_6_G,
O => BTN_1_Count_6_XORG_3927
);
BTN_1_Count_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_6_CYMUXFAST_3924,
O => BTN_1_Mcount_Count_cy(7)
);
BTN_1_Count_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(5),
O => BTN_1_Count_6_FASTCARRY_3922
);
BTN_1_Count_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
I0 => BTN_1_Count_6_CYSELG_3910,
I1 => BTN_1_Count_6_CYSELF_3925,
O => BTN_1_Count_6_CYAND_3923
);
BTN_1_Count_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
IA => BTN_1_Count_6_CYMUXG2_3921,
IB => BTN_1_Count_6_FASTCARRY_3922,
SEL => BTN_1_Count_6_CYAND_3923,
O => BTN_1_Count_6_CYMUXFAST_3924
);
BTN_1_Count_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y73"
)
port map (
IA => BTN_1_Count_6_LOGIC_ZERO_3919,
IB => BTN_1_Count_6_CYMUXF2_3920,
SEL => BTN_1_Count_6_CYSELG_3910,
O => BTN_1_Count_6_CYMUXG2_3921
);
BTN_1_Count_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_6_G,
O => BTN_1_Count_6_CYSELG_3910
);
BTN_1_Count_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_6_SRINV_3908
);
BTN_1_Count_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_6_CLKINV_3907
);
BTN_1_Count_6_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_6_CEINVNOT
);
BTN_1_Count_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y74"
)
port map (
O => BTN_1_Count_8_LOGIC_ZERO_3975
);
BTN_1_Count_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_8_XORF_4001,
O => BTN_1_Count_8_DXMUX_4003
);
BTN_1_Count_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
I0 => BTN_1_Count_8_CYINIT_4000,
I1 => BTN_1_Count_8_F,
O => BTN_1_Count_8_XORF_4001
);
BTN_1_Count_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
IA => BTN_1_Count_8_LOGIC_ZERO_3975,
IB => BTN_1_Count_8_CYINIT_4000,
SEL => BTN_1_Count_8_CYSELF_3981,
O => BTN_1_Mcount_Count_cy(8)
);
BTN_1_Count_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
IA => BTN_1_Count_8_LOGIC_ZERO_3975,
IB => BTN_1_Count_8_LOGIC_ZERO_3975,
SEL => BTN_1_Count_8_CYSELF_3981,
O => BTN_1_Count_8_CYMUXF2_3976
);
BTN_1_Count_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(7),
O => BTN_1_Count_8_CYINIT_4000
);
BTN_1_Count_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_8_F,
O => BTN_1_Count_8_CYSELF_3981
);
BTN_1_Count_8_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_8_XORG_3983,
O => BTN_1_Count_8_DYMUX_3985
);
BTN_1_Count_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
I0 => BTN_1_Mcount_Count_cy(8),
I1 => BTN_1_Count_8_G,
O => BTN_1_Count_8_XORG_3983
);
BTN_1_Count_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_8_CYMUXFAST_3980,
O => BTN_1_Mcount_Count_cy(9)
);
BTN_1_Count_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(7),
O => BTN_1_Count_8_FASTCARRY_3978
);
BTN_1_Count_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
I0 => BTN_1_Count_8_CYSELG_3966,
I1 => BTN_1_Count_8_CYSELF_3981,
O => BTN_1_Count_8_CYAND_3979
);
BTN_1_Count_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
IA => BTN_1_Count_8_CYMUXG2_3977,
IB => BTN_1_Count_8_FASTCARRY_3978,
SEL => BTN_1_Count_8_CYAND_3979,
O => BTN_1_Count_8_CYMUXFAST_3980
);
BTN_1_Count_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y74"
)
port map (
IA => BTN_1_Count_8_LOGIC_ZERO_3975,
IB => BTN_1_Count_8_CYMUXF2_3976,
SEL => BTN_1_Count_8_CYSELG_3966,
O => BTN_1_Count_8_CYMUXG2_3977
);
BTN_1_Count_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_8_G,
O => BTN_1_Count_8_CYSELG_3966
);
BTN_1_Count_8_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_8_SRINV_3964
);
BTN_1_Count_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_8_CLKINV_3963
);
BTN_1_Count_8_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_8_CEINVNOT
);
BTN_1_Count_10_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y75"
)
port map (
O => BTN_1_Count_10_LOGIC_ZERO_4031
);
BTN_1_Count_10_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_10_XORF_4057,
O => BTN_1_Count_10_DXMUX_4059
);
BTN_1_Count_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
I0 => BTN_1_Count_10_CYINIT_4056,
I1 => BTN_1_Count_10_F,
O => BTN_1_Count_10_XORF_4057
);
BTN_1_Count_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
IA => BTN_1_Count_10_LOGIC_ZERO_4031,
IB => BTN_1_Count_10_CYINIT_4056,
SEL => BTN_1_Count_10_CYSELF_4037,
O => BTN_1_Mcount_Count_cy(10)
);
BTN_1_Count_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
IA => BTN_1_Count_10_LOGIC_ZERO_4031,
IB => BTN_1_Count_10_LOGIC_ZERO_4031,
SEL => BTN_1_Count_10_CYSELF_4037,
O => BTN_1_Count_10_CYMUXF2_4032
);
BTN_1_Count_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(9),
O => BTN_1_Count_10_CYINIT_4056
);
BTN_1_Count_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_10_F,
O => BTN_1_Count_10_CYSELF_4037
);
BTN_1_Count_10_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_10_XORG_4039,
O => BTN_1_Count_10_DYMUX_4041
);
BTN_1_Count_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
I0 => BTN_1_Mcount_Count_cy(10),
I1 => BTN_1_Count_10_G,
O => BTN_1_Count_10_XORG_4039
);
BTN_1_Count_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_10_CYMUXFAST_4036,
O => BTN_1_Mcount_Count_cy(11)
);
BTN_1_Count_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(9),
O => BTN_1_Count_10_FASTCARRY_4034
);
BTN_1_Count_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
I0 => BTN_1_Count_10_CYSELG_4022,
I1 => BTN_1_Count_10_CYSELF_4037,
O => BTN_1_Count_10_CYAND_4035
);
BTN_1_Count_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
IA => BTN_1_Count_10_CYMUXG2_4033,
IB => BTN_1_Count_10_FASTCARRY_4034,
SEL => BTN_1_Count_10_CYAND_4035,
O => BTN_1_Count_10_CYMUXFAST_4036
);
BTN_1_Count_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y75"
)
port map (
IA => BTN_1_Count_10_LOGIC_ZERO_4031,
IB => BTN_1_Count_10_CYMUXF2_4032,
SEL => BTN_1_Count_10_CYSELG_4022,
O => BTN_1_Count_10_CYMUXG2_4033
);
BTN_1_Count_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_10_G,
O => BTN_1_Count_10_CYSELG_4022
);
BTN_1_Count_10_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_10_SRINV_4020
);
BTN_1_Count_10_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_10_CLKINV_4019
);
BTN_1_Count_10_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_10_CEINVNOT
);
BTN_1_Count_12_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y76"
)
port map (
O => BTN_1_Count_12_LOGIC_ZERO_4087
);
BTN_1_Count_12_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_12_XORF_4113,
O => BTN_1_Count_12_DXMUX_4115
);
BTN_1_Count_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
I0 => BTN_1_Count_12_CYINIT_4112,
I1 => BTN_1_Count_12_F,
O => BTN_1_Count_12_XORF_4113
);
BTN_1_Count_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
IA => BTN_1_Count_12_LOGIC_ZERO_4087,
IB => BTN_1_Count_12_CYINIT_4112,
SEL => BTN_1_Count_12_CYSELF_4093,
O => BTN_1_Mcount_Count_cy(12)
);
BTN_1_Count_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
IA => BTN_1_Count_12_LOGIC_ZERO_4087,
IB => BTN_1_Count_12_LOGIC_ZERO_4087,
SEL => BTN_1_Count_12_CYSELF_4093,
O => BTN_1_Count_12_CYMUXF2_4088
);
BTN_1_Count_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(11),
O => BTN_1_Count_12_CYINIT_4112
);
BTN_1_Count_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_12_F,
O => BTN_1_Count_12_CYSELF_4093
);
BTN_1_Count_12_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_12_XORG_4095,
O => BTN_1_Count_12_DYMUX_4097
);
BTN_1_Count_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
I0 => BTN_1_Mcount_Count_cy(12),
I1 => BTN_1_Count_12_G,
O => BTN_1_Count_12_XORG_4095
);
BTN_1_Count_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_12_CYMUXFAST_4092,
O => BTN_1_Mcount_Count_cy(13)
);
BTN_1_Count_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(11),
O => BTN_1_Count_12_FASTCARRY_4090
);
BTN_1_Count_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
I0 => BTN_1_Count_12_CYSELG_4078,
I1 => BTN_1_Count_12_CYSELF_4093,
O => BTN_1_Count_12_CYAND_4091
);
BTN_1_Count_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
IA => BTN_1_Count_12_CYMUXG2_4089,
IB => BTN_1_Count_12_FASTCARRY_4090,
SEL => BTN_1_Count_12_CYAND_4091,
O => BTN_1_Count_12_CYMUXFAST_4092
);
BTN_1_Count_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y76"
)
port map (
IA => BTN_1_Count_12_LOGIC_ZERO_4087,
IB => BTN_1_Count_12_CYMUXF2_4088,
SEL => BTN_1_Count_12_CYSELG_4078,
O => BTN_1_Count_12_CYMUXG2_4089
);
BTN_1_Count_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_12_G,
O => BTN_1_Count_12_CYSELG_4078
);
BTN_1_Count_12_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_12_SRINV_4076
);
BTN_1_Count_12_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_12_CLKINV_4075
);
BTN_1_Count_12_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_12_CEINVNOT
);
BTN_1_Count_14_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y77"
)
port map (
O => BTN_1_Count_14_LOGIC_ZERO_4143
);
BTN_1_Count_14_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_14_XORF_4169,
O => BTN_1_Count_14_DXMUX_4171
);
BTN_1_Count_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
I0 => BTN_1_Count_14_CYINIT_4168,
I1 => BTN_1_Count_14_F,
O => BTN_1_Count_14_XORF_4169
);
BTN_1_Count_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
IA => BTN_1_Count_14_LOGIC_ZERO_4143,
IB => BTN_1_Count_14_CYINIT_4168,
SEL => BTN_1_Count_14_CYSELF_4149,
O => BTN_1_Mcount_Count_cy(14)
);
BTN_1_Count_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
IA => BTN_1_Count_14_LOGIC_ZERO_4143,
IB => BTN_1_Count_14_LOGIC_ZERO_4143,
SEL => BTN_1_Count_14_CYSELF_4149,
O => BTN_1_Count_14_CYMUXF2_4144
);
BTN_1_Count_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(13),
O => BTN_1_Count_14_CYINIT_4168
);
BTN_1_Count_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_14_F,
O => BTN_1_Count_14_CYSELF_4149
);
BTN_1_Count_14_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_14_XORG_4151,
O => BTN_1_Count_14_DYMUX_4153
);
BTN_1_Count_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
I0 => BTN_1_Mcount_Count_cy(14),
I1 => BTN_1_Count_14_G,
O => BTN_1_Count_14_XORG_4151
);
BTN_1_Count_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_14_CYMUXFAST_4148,
O => BTN_1_Mcount_Count_cy(15)
);
BTN_1_Count_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(13),
O => BTN_1_Count_14_FASTCARRY_4146
);
BTN_1_Count_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
I0 => BTN_1_Count_14_CYSELG_4134,
I1 => BTN_1_Count_14_CYSELF_4149,
O => BTN_1_Count_14_CYAND_4147
);
BTN_1_Count_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
IA => BTN_1_Count_14_CYMUXG2_4145,
IB => BTN_1_Count_14_FASTCARRY_4146,
SEL => BTN_1_Count_14_CYAND_4147,
O => BTN_1_Count_14_CYMUXFAST_4148
);
BTN_1_Count_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y77"
)
port map (
IA => BTN_1_Count_14_LOGIC_ZERO_4143,
IB => BTN_1_Count_14_CYMUXF2_4144,
SEL => BTN_1_Count_14_CYSELG_4134,
O => BTN_1_Count_14_CYMUXG2_4145
);
BTN_1_Count_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_14_G,
O => BTN_1_Count_14_CYSELG_4134
);
BTN_1_Count_14_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_14_SRINV_4132
);
BTN_1_Count_14_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_14_CLKINV_4131
);
BTN_1_Count_14_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_14_CEINVNOT
);
BTN_1_Count_16_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y78"
)
port map (
O => BTN_1_Count_16_LOGIC_ZERO_4199
);
BTN_1_Count_16_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_16_XORF_4225,
O => BTN_1_Count_16_DXMUX_4227
);
BTN_1_Count_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
I0 => BTN_1_Count_16_CYINIT_4224,
I1 => BTN_1_Count_16_F,
O => BTN_1_Count_16_XORF_4225
);
BTN_1_Count_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
IA => BTN_1_Count_16_LOGIC_ZERO_4199,
IB => BTN_1_Count_16_CYINIT_4224,
SEL => BTN_1_Count_16_CYSELF_4205,
O => BTN_1_Mcount_Count_cy(16)
);
BTN_1_Count_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
IA => BTN_1_Count_16_LOGIC_ZERO_4199,
IB => BTN_1_Count_16_LOGIC_ZERO_4199,
SEL => BTN_1_Count_16_CYSELF_4205,
O => BTN_1_Count_16_CYMUXF2_4200
);
BTN_1_Count_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(15),
O => BTN_1_Count_16_CYINIT_4224
);
BTN_1_Count_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_16_F,
O => BTN_1_Count_16_CYSELF_4205
);
BTN_1_Count_16_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_16_XORG_4207,
O => BTN_1_Count_16_DYMUX_4209
);
BTN_1_Count_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
I0 => BTN_1_Mcount_Count_cy(16),
I1 => BTN_1_Count_16_G,
O => BTN_1_Count_16_XORG_4207
);
BTN_1_Count_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_16_CYMUXFAST_4204,
O => BTN_1_Mcount_Count_cy(17)
);
BTN_1_Count_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(15),
O => BTN_1_Count_16_FASTCARRY_4202
);
BTN_1_Count_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
I0 => BTN_1_Count_16_CYSELG_4190,
I1 => BTN_1_Count_16_CYSELF_4205,
O => BTN_1_Count_16_CYAND_4203
);
BTN_1_Count_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
IA => BTN_1_Count_16_CYMUXG2_4201,
IB => BTN_1_Count_16_FASTCARRY_4202,
SEL => BTN_1_Count_16_CYAND_4203,
O => BTN_1_Count_16_CYMUXFAST_4204
);
BTN_1_Count_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y78"
)
port map (
IA => BTN_1_Count_16_LOGIC_ZERO_4199,
IB => BTN_1_Count_16_CYMUXF2_4200,
SEL => BTN_1_Count_16_CYSELG_4190,
O => BTN_1_Count_16_CYMUXG2_4201
);
BTN_1_Count_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_16_G,
O => BTN_1_Count_16_CYSELG_4190
);
BTN_1_Count_16_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_16_SRINV_4188
);
BTN_1_Count_16_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_16_CLKINV_4187
);
BTN_1_Count_16_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y78",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_16_CEINVNOT
);
BTN_1_Count_18_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X67Y79"
)
port map (
O => BTN_1_Count_18_LOGIC_ZERO_4255
);
BTN_1_Count_18_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_18_XORF_4281,
O => BTN_1_Count_18_DXMUX_4283
);
BTN_1_Count_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
I0 => BTN_1_Count_18_CYINIT_4280,
I1 => BTN_1_Count_18_F,
O => BTN_1_Count_18_XORF_4281
);
BTN_1_Count_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
IA => BTN_1_Count_18_LOGIC_ZERO_4255,
IB => BTN_1_Count_18_CYINIT_4280,
SEL => BTN_1_Count_18_CYSELF_4261,
O => BTN_1_Mcount_Count_cy(18)
);
BTN_1_Count_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
IA => BTN_1_Count_18_LOGIC_ZERO_4255,
IB => BTN_1_Count_18_LOGIC_ZERO_4255,
SEL => BTN_1_Count_18_CYSELF_4261,
O => BTN_1_Count_18_CYMUXF2_4256
);
BTN_1_Count_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(17),
O => BTN_1_Count_18_CYINIT_4280
);
BTN_1_Count_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_18_F,
O => BTN_1_Count_18_CYSELF_4261
);
BTN_1_Count_18_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_18_XORG_4263,
O => BTN_1_Count_18_DYMUX_4265
);
BTN_1_Count_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
I0 => BTN_1_Mcount_Count_cy(18),
I1 => BTN_1_Count_18_G,
O => BTN_1_Count_18_XORG_4263
);
BTN_1_Count_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Mcount_Count_cy(17),
O => BTN_1_Count_18_FASTCARRY_4258
);
BTN_1_Count_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
I0 => BTN_1_Count_18_CYSELG_4246,
I1 => BTN_1_Count_18_CYSELF_4261,
O => BTN_1_Count_18_CYAND_4259
);
BTN_1_Count_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
IA => BTN_1_Count_18_CYMUXG2_4257,
IB => BTN_1_Count_18_FASTCARRY_4258,
SEL => BTN_1_Count_18_CYAND_4259,
O => BTN_1_Count_18_CYMUXFAST_4260
);
BTN_1_Count_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X67Y79"
)
port map (
IA => BTN_1_Count_18_LOGIC_ZERO_4255,
IB => BTN_1_Count_18_CYMUXF2_4256,
SEL => BTN_1_Count_18_CYSELG_4246,
O => BTN_1_Count_18_CYMUXG2_4257
);
BTN_1_Count_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_18_G,
O => BTN_1_Count_18_CYSELG_4246
);
BTN_1_Count_18_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_18_SRINV_4244
);
BTN_1_Count_18_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_18_CLKINV_4243
);
BTN_1_Count_18_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y79",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_18_CEINVNOT
);
BTN_1_Count_20_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_20_XORF_4308,
O => BTN_1_Count_20_DXMUX_4310
);
BTN_1_Count_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X67Y80"
)
port map (
I0 => BTN_1_Count_20_CYINIT_4307,
I1 => BTN_1_Count_20_rt_4305,
O => BTN_1_Count_20_XORF_4308
);
BTN_1_Count_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X67Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_18_CYMUXFAST_4260,
O => BTN_1_Count_20_CYINIT_4307
);
BTN_1_Count_20_SRINV : X_BUF
generic map(
LOC => "SLICE_X67Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count_and0000_0,
O => BTN_1_Count_20_SRINV_4297
);
BTN_1_Count_20_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y80",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_1_Count_20_CLKINV_4296
);
BTN_1_Count_20_CEINV : X_INV
generic map(
LOC => "SLICE_X67Y80",
PATHPULSE => 638 ps
)
port map (
I => BTN_1_Count(20),
O => BTN_1_Count_20_CEINVNOT
);
arith_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => arith_0_XORF_4350,
O => arith(0)
);
arith_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y26"
)
port map (
I0 => arith_0_CYINIT_4349,
I1 => Arith_Unit_Maddsub_arith_lut(0),
O => arith_0_XORF_4350
);
arith_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y26"
)
port map (
IA => arith_0_CY0F_4348,
IB => arith_0_CYINIT_4349,
SEL => arith_0_CYSELF_4341,
O => Arith_Unit_Maddsub_arith_cy_0_Q
);
arith_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_arith_cmp_eq0000_0,
O => arith_0_CYINIT_4349
);
arith_0_CY0F : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(0),
O => arith_0_CY0F_4348
);
arith_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(0),
O => arith_0_CYSELF_4341
);
arith_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => arith_0_XORG_4337,
O => arith(1)
);
arith_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y26"
)
port map (
I0 => Arith_Unit_Maddsub_arith_cy_0_Q,
I1 => Arith_Unit_Maddsub_arith_lut(1),
O => arith_0_XORG_4337
);
arith_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => arith_0_CYMUXG_4336,
O => Arith_Unit_Maddsub_arith_cy_1_Q
);
arith_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X65Y26"
)
port map (
IA => arith_0_CY0G_4334,
IB => Arith_Unit_Maddsub_arith_cy_0_Q,
SEL => arith_0_CYSELG_4327,
O => arith_0_CYMUXG_4336
);
arith_0_CY0G : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(1),
O => arith_0_CY0G_4334
);
arith_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y26",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(1),
O => arith_0_CYSELG_4327
);
Arith_Unit_Maddsub_arith_lut_1_Q : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X65Y26"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => VCC,
ADR3 => Arith_Unit_arith_cmp_eq0000_0,
O => Arith_Unit_Maddsub_arith_lut(1)
);
arith_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => arith_2_XORF_4389,
O => arith(2)
);
arith_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
I0 => arith_2_CYINIT_4388,
I1 => Arith_Unit_Maddsub_arith_lut(2),
O => arith_2_XORF_4389
);
arith_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
IA => arith_2_CY0F_4387,
IB => arith_2_CYINIT_4388,
SEL => arith_2_CYSELF_4376,
O => Arith_Unit_Maddsub_arith_cy_2_Q
);
arith_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
IA => arith_2_CY0F_4387,
IB => arith_2_CY0F_4387,
SEL => arith_2_CYSELF_4376,
O => arith_2_CYMUXF2_4371
);
arith_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_cy_1_Q,
O => arith_2_CYINIT_4388
);
arith_2_CY0F : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(2),
O => arith_2_CY0F_4387
);
arith_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(2),
O => arith_2_CYSELF_4376
);
arith_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => arith_2_XORG_4378,
O => arith(3)
);
arith_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
I0 => Arith_Unit_Maddsub_arith_cy_2_Q,
I1 => Arith_Unit_Maddsub_arith_lut(3),
O => arith_2_XORG_4378
);
arith_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => arith_2_CYMUXFAST_4375,
O => Arith_Unit_Maddsub_arith_cy_3_Q
);
arith_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_cy_1_Q,
O => arith_2_FASTCARRY_4373
);
arith_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
I0 => arith_2_CYSELG_4363,
I1 => arith_2_CYSELF_4376,
O => arith_2_CYAND_4374
);
arith_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
IA => arith_2_CYMUXG2_4372,
IB => arith_2_FASTCARRY_4373,
SEL => arith_2_CYAND_4374,
O => arith_2_CYMUXFAST_4375
);
arith_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y27"
)
port map (
IA => arith_2_CY0G_4370,
IB => arith_2_CYMUXF2_4371,
SEL => arith_2_CYSELG_4363,
O => arith_2_CYMUXG2_4372
);
arith_2_CY0G : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(3),
O => arith_2_CY0G_4370
);
arith_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y27",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(3),
O => arith_2_CYSELG_4363
);
Arith_Unit_Maddsub_arith_lut_3_Q : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X65Y27"
)
port map (
ADR0 => UXCntl_Unit_VALA(3),
ADR1 => UXCntl_Unit_VALB(3),
ADR2 => VCC,
ADR3 => Arith_Unit_arith_cmp_eq0000_0,
O => Arith_Unit_Maddsub_arith_lut(3)
);
arith_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => arith_4_XORF_4428,
O => arith(4)
);
arith_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
I0 => arith_4_CYINIT_4427,
I1 => Arith_Unit_Maddsub_arith_lut(4),
O => arith_4_XORF_4428
);
arith_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
IA => arith_4_CY0F_4426,
IB => arith_4_CYINIT_4427,
SEL => arith_4_CYSELF_4415,
O => Arith_Unit_Maddsub_arith_cy_4_Q
);
arith_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
IA => arith_4_CY0F_4426,
IB => arith_4_CY0F_4426,
SEL => arith_4_CYSELF_4415,
O => arith_4_CYMUXF2_4410
);
arith_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_cy_3_Q,
O => arith_4_CYINIT_4427
);
arith_4_CY0F : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(4),
O => arith_4_CY0F_4426
);
arith_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(4),
O => arith_4_CYSELF_4415
);
arith_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => arith_4_XORG_4417,
O => arith(5)
);
arith_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
I0 => Arith_Unit_Maddsub_arith_cy_4_Q,
I1 => Arith_Unit_Maddsub_arith_lut(5),
O => arith_4_XORG_4417
);
arith_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_cy_3_Q,
O => arith_4_FASTCARRY_4412
);
arith_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
I0 => arith_4_CYSELG_4402,
I1 => arith_4_CYSELF_4415,
O => arith_4_CYAND_4413
);
arith_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
IA => arith_4_CYMUXG2_4411,
IB => arith_4_FASTCARRY_4412,
SEL => arith_4_CYAND_4413,
O => arith_4_CYMUXFAST_4414
);
arith_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y28"
)
port map (
IA => arith_4_CY0G_4409,
IB => arith_4_CYMUXF2_4410,
SEL => arith_4_CYSELG_4402,
O => arith_4_CYMUXG2_4411
);
arith_4_CY0G : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(5),
O => arith_4_CY0G_4409
);
arith_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y28",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(5),
O => arith_4_CYSELG_4402
);
Arith_Unit_Maddsub_arith_lut_5_Q : X_LUT4
generic map(
INIT => X"9696",
LOC => "SLICE_X65Y28"
)
port map (
ADR0 => UXCntl_Unit_VALB(5),
ADR1 => UXCntl_Unit_VALA(5),
ADR2 => Arith_Unit_arith_cmp_eq0000_0,
ADR3 => VCC,
O => Arith_Unit_Maddsub_arith_lut(5)
);
arith_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y29",
PATHPULSE => 638 ps
)
port map (
I => arith_6_XORF_4459,
O => arith(6)
);
arith_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y29"
)
port map (
I0 => arith_6_CYINIT_4458,
I1 => Arith_Unit_Maddsub_arith_lut(6),
O => arith_6_XORF_4459
);
arith_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y29"
)
port map (
IA => arith_6_CY0F_4457,
IB => arith_6_CYINIT_4458,
SEL => arith_6_CYSELF_4450,
O => Arith_Unit_Maddsub_arith_cy_6_Q
);
arith_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y29",
PATHPULSE => 638 ps
)
port map (
I => arith_4_CYMUXFAST_4414,
O => arith_6_CYINIT_4458
);
arith_6_CY0F : X_BUF
generic map(
LOC => "SLICE_X65Y29",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALA(6),
O => arith_6_CY0F_4457
);
arith_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y29",
PATHPULSE => 638 ps
)
port map (
I => Arith_Unit_Maddsub_arith_lut(6),
O => arith_6_CYSELF_4450
);
arith_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X65Y29",
PATHPULSE => 638 ps
)
port map (
I => arith_6_XORG_4447,
O => arith(7)
);
arith_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y29"
)
port map (
I0 => Arith_Unit_Maddsub_arith_cy_6_Q,
I1 => Arith_Unit_Maddsub_arith_lut(7),
O => arith_6_XORG_4447
);
Arith_Unit_Maddsub_arith_lut_7_Q : X_LUT4
generic map(
INIT => X"9696",
LOC => "SLICE_X65Y29"
)
port map (
ADR0 => UXCntl_Unit_VALA(7),
ADR1 => UXCntl_Unit_VALB(7),
ADR2 => Arith_Unit_arith_cmp_eq0000_0,
ADR3 => VCC,
O => Arith_Unit_Maddsub_arith_lut(7)
);
BTN_0_Count_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y81"
)
port map (
O => BTN_0_Count_0_LOGIC_ZERO_4483
);
BTN_0_Count_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X65Y81"
)
port map (
O => BTN_0_Count_0_LOGIC_ONE_4506
);
BTN_0_Count_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_0_XORF_4507,
O => BTN_0_Count_0_DXMUX_4509
);
BTN_0_Count_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y81"
)
port map (
I0 => BTN_0_Count_0_CYINIT_4505,
I1 => BTN_0_Mcount_Count_lut(0),
O => BTN_0_Count_0_XORF_4507
);
BTN_0_Count_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y81"
)
port map (
IA => BTN_0_Count_0_LOGIC_ONE_4506,
IB => BTN_0_Count_0_CYINIT_4505,
SEL => BTN_0_Count_0_CYSELF_4496,
O => BTN_0_Mcount_Count_cy(0)
);
BTN_0_Count_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_0_BXINV_4494,
O => BTN_0_Count_0_CYINIT_4505
);
BTN_0_Count_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_lut(0),
O => BTN_0_Count_0_CYSELF_4496
);
BTN_0_Count_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => BTN_0_Count_0_BXINV_4494
);
BTN_0_Count_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_0_XORG_4486,
O => BTN_0_Count_0_DYMUX_4488
);
BTN_0_Count_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y81"
)
port map (
I0 => BTN_0_Mcount_Count_cy(0),
I1 => BTN_0_Count_0_G,
O => BTN_0_Count_0_XORG_4486
);
BTN_0_Count_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_0_CYMUXG_4485,
O => BTN_0_Mcount_Count_cy(1)
);
BTN_0_Count_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X65Y81"
)
port map (
IA => BTN_0_Count_0_LOGIC_ZERO_4483,
IB => BTN_0_Mcount_Count_cy(0),
SEL => BTN_0_Count_0_CYSELG_4474,
O => BTN_0_Count_0_CYMUXG_4485
);
BTN_0_Count_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_0_G,
O => BTN_0_Count_0_CYSELG_4474
);
BTN_0_Count_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_0_SRINV_4472
);
BTN_0_Count_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_0_CLKINV_4471
);
BTN_0_Count_0_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y81",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_0_CEINVNOT
);
BTN_0_Count_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y82"
)
port map (
O => BTN_0_Count_2_LOGIC_ZERO_4537
);
BTN_0_Count_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_2_XORF_4563,
O => BTN_0_Count_2_DXMUX_4565
);
BTN_0_Count_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
I0 => BTN_0_Count_2_CYINIT_4562,
I1 => BTN_0_Count_2_F,
O => BTN_0_Count_2_XORF_4563
);
BTN_0_Count_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
IA => BTN_0_Count_2_LOGIC_ZERO_4537,
IB => BTN_0_Count_2_CYINIT_4562,
SEL => BTN_0_Count_2_CYSELF_4543,
O => BTN_0_Mcount_Count_cy(2)
);
BTN_0_Count_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
IA => BTN_0_Count_2_LOGIC_ZERO_4537,
IB => BTN_0_Count_2_LOGIC_ZERO_4537,
SEL => BTN_0_Count_2_CYSELF_4543,
O => BTN_0_Count_2_CYMUXF2_4538
);
BTN_0_Count_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(1),
O => BTN_0_Count_2_CYINIT_4562
);
BTN_0_Count_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_2_F,
O => BTN_0_Count_2_CYSELF_4543
);
BTN_0_Count_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_2_XORG_4545,
O => BTN_0_Count_2_DYMUX_4547
);
BTN_0_Count_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
I0 => BTN_0_Mcount_Count_cy(2),
I1 => BTN_0_Count_2_G,
O => BTN_0_Count_2_XORG_4545
);
BTN_0_Count_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_2_CYMUXFAST_4542,
O => BTN_0_Mcount_Count_cy(3)
);
BTN_0_Count_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(1),
O => BTN_0_Count_2_FASTCARRY_4540
);
BTN_0_Count_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
I0 => BTN_0_Count_2_CYSELG_4528,
I1 => BTN_0_Count_2_CYSELF_4543,
O => BTN_0_Count_2_CYAND_4541
);
BTN_0_Count_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
IA => BTN_0_Count_2_CYMUXG2_4539,
IB => BTN_0_Count_2_FASTCARRY_4540,
SEL => BTN_0_Count_2_CYAND_4541,
O => BTN_0_Count_2_CYMUXFAST_4542
);
BTN_0_Count_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y82"
)
port map (
IA => BTN_0_Count_2_LOGIC_ZERO_4537,
IB => BTN_0_Count_2_CYMUXF2_4538,
SEL => BTN_0_Count_2_CYSELG_4528,
O => BTN_0_Count_2_CYMUXG2_4539
);
BTN_0_Count_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_2_G,
O => BTN_0_Count_2_CYSELG_4528
);
BTN_0_Count_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_2_SRINV_4526
);
BTN_0_Count_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_2_CLKINV_4525
);
BTN_0_Count_2_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y82",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_2_CEINVNOT
);
BTN_0_Count_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y83"
)
port map (
O => BTN_0_Count_4_LOGIC_ZERO_4593
);
BTN_0_Count_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_4_XORF_4619,
O => BTN_0_Count_4_DXMUX_4621
);
BTN_0_Count_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
I0 => BTN_0_Count_4_CYINIT_4618,
I1 => BTN_0_Count_4_F,
O => BTN_0_Count_4_XORF_4619
);
BTN_0_Count_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
IA => BTN_0_Count_4_LOGIC_ZERO_4593,
IB => BTN_0_Count_4_CYINIT_4618,
SEL => BTN_0_Count_4_CYSELF_4599,
O => BTN_0_Mcount_Count_cy(4)
);
BTN_0_Count_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
IA => BTN_0_Count_4_LOGIC_ZERO_4593,
IB => BTN_0_Count_4_LOGIC_ZERO_4593,
SEL => BTN_0_Count_4_CYSELF_4599,
O => BTN_0_Count_4_CYMUXF2_4594
);
BTN_0_Count_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(3),
O => BTN_0_Count_4_CYINIT_4618
);
BTN_0_Count_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_4_F,
O => BTN_0_Count_4_CYSELF_4599
);
BTN_0_Count_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_4_XORG_4601,
O => BTN_0_Count_4_DYMUX_4603
);
BTN_0_Count_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
I0 => BTN_0_Mcount_Count_cy(4),
I1 => BTN_0_Count_4_G,
O => BTN_0_Count_4_XORG_4601
);
BTN_0_Count_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_4_CYMUXFAST_4598,
O => BTN_0_Mcount_Count_cy(5)
);
BTN_0_Count_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(3),
O => BTN_0_Count_4_FASTCARRY_4596
);
BTN_0_Count_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
I0 => BTN_0_Count_4_CYSELG_4584,
I1 => BTN_0_Count_4_CYSELF_4599,
O => BTN_0_Count_4_CYAND_4597
);
BTN_0_Count_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
IA => BTN_0_Count_4_CYMUXG2_4595,
IB => BTN_0_Count_4_FASTCARRY_4596,
SEL => BTN_0_Count_4_CYAND_4597,
O => BTN_0_Count_4_CYMUXFAST_4598
);
BTN_0_Count_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y83"
)
port map (
IA => BTN_0_Count_4_LOGIC_ZERO_4593,
IB => BTN_0_Count_4_CYMUXF2_4594,
SEL => BTN_0_Count_4_CYSELG_4584,
O => BTN_0_Count_4_CYMUXG2_4595
);
BTN_0_Count_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_4_G,
O => BTN_0_Count_4_CYSELG_4584
);
BTN_0_Count_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_4_SRINV_4582
);
BTN_0_Count_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_4_CLKINV_4581
);
BTN_0_Count_4_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y83",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_4_CEINVNOT
);
BTN_0_Count_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y84"
)
port map (
O => BTN_0_Count_6_LOGIC_ZERO_4649
);
BTN_0_Count_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_6_XORF_4675,
O => BTN_0_Count_6_DXMUX_4677
);
BTN_0_Count_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
I0 => BTN_0_Count_6_CYINIT_4674,
I1 => BTN_0_Count_6_F,
O => BTN_0_Count_6_XORF_4675
);
BTN_0_Count_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
IA => BTN_0_Count_6_LOGIC_ZERO_4649,
IB => BTN_0_Count_6_CYINIT_4674,
SEL => BTN_0_Count_6_CYSELF_4655,
O => BTN_0_Mcount_Count_cy(6)
);
BTN_0_Count_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
IA => BTN_0_Count_6_LOGIC_ZERO_4649,
IB => BTN_0_Count_6_LOGIC_ZERO_4649,
SEL => BTN_0_Count_6_CYSELF_4655,
O => BTN_0_Count_6_CYMUXF2_4650
);
BTN_0_Count_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(5),
O => BTN_0_Count_6_CYINIT_4674
);
BTN_0_Count_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_6_F,
O => BTN_0_Count_6_CYSELF_4655
);
BTN_0_Count_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_6_XORG_4657,
O => BTN_0_Count_6_DYMUX_4659
);
BTN_0_Count_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
I0 => BTN_0_Mcount_Count_cy(6),
I1 => BTN_0_Count_6_G,
O => BTN_0_Count_6_XORG_4657
);
BTN_0_Count_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_6_CYMUXFAST_4654,
O => BTN_0_Mcount_Count_cy(7)
);
BTN_0_Count_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(5),
O => BTN_0_Count_6_FASTCARRY_4652
);
BTN_0_Count_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
I0 => BTN_0_Count_6_CYSELG_4640,
I1 => BTN_0_Count_6_CYSELF_4655,
O => BTN_0_Count_6_CYAND_4653
);
BTN_0_Count_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
IA => BTN_0_Count_6_CYMUXG2_4651,
IB => BTN_0_Count_6_FASTCARRY_4652,
SEL => BTN_0_Count_6_CYAND_4653,
O => BTN_0_Count_6_CYMUXFAST_4654
);
BTN_0_Count_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y84"
)
port map (
IA => BTN_0_Count_6_LOGIC_ZERO_4649,
IB => BTN_0_Count_6_CYMUXF2_4650,
SEL => BTN_0_Count_6_CYSELG_4640,
O => BTN_0_Count_6_CYMUXG2_4651
);
BTN_0_Count_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_6_G,
O => BTN_0_Count_6_CYSELG_4640
);
BTN_0_Count_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_6_SRINV_4638
);
BTN_0_Count_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_6_CLKINV_4637
);
BTN_0_Count_6_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y84",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_6_CEINVNOT
);
BTN_0_Count_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y85"
)
port map (
O => BTN_0_Count_8_LOGIC_ZERO_4705
);
BTN_0_Count_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_8_XORF_4731,
O => BTN_0_Count_8_DXMUX_4733
);
BTN_0_Count_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
I0 => BTN_0_Count_8_CYINIT_4730,
I1 => BTN_0_Count_8_F,
O => BTN_0_Count_8_XORF_4731
);
BTN_0_Count_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
IA => BTN_0_Count_8_LOGIC_ZERO_4705,
IB => BTN_0_Count_8_CYINIT_4730,
SEL => BTN_0_Count_8_CYSELF_4711,
O => BTN_0_Mcount_Count_cy(8)
);
BTN_0_Count_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
IA => BTN_0_Count_8_LOGIC_ZERO_4705,
IB => BTN_0_Count_8_LOGIC_ZERO_4705,
SEL => BTN_0_Count_8_CYSELF_4711,
O => BTN_0_Count_8_CYMUXF2_4706
);
BTN_0_Count_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(7),
O => BTN_0_Count_8_CYINIT_4730
);
BTN_0_Count_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_8_F,
O => BTN_0_Count_8_CYSELF_4711
);
BTN_0_Count_8_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_8_XORG_4713,
O => BTN_0_Count_8_DYMUX_4715
);
BTN_0_Count_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
I0 => BTN_0_Mcount_Count_cy(8),
I1 => BTN_0_Count_8_G,
O => BTN_0_Count_8_XORG_4713
);
BTN_0_Count_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_8_CYMUXFAST_4710,
O => BTN_0_Mcount_Count_cy(9)
);
BTN_0_Count_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(7),
O => BTN_0_Count_8_FASTCARRY_4708
);
BTN_0_Count_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
I0 => BTN_0_Count_8_CYSELG_4696,
I1 => BTN_0_Count_8_CYSELF_4711,
O => BTN_0_Count_8_CYAND_4709
);
BTN_0_Count_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
IA => BTN_0_Count_8_CYMUXG2_4707,
IB => BTN_0_Count_8_FASTCARRY_4708,
SEL => BTN_0_Count_8_CYAND_4709,
O => BTN_0_Count_8_CYMUXFAST_4710
);
BTN_0_Count_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y85"
)
port map (
IA => BTN_0_Count_8_LOGIC_ZERO_4705,
IB => BTN_0_Count_8_CYMUXF2_4706,
SEL => BTN_0_Count_8_CYSELG_4696,
O => BTN_0_Count_8_CYMUXG2_4707
);
BTN_0_Count_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_8_G,
O => BTN_0_Count_8_CYSELG_4696
);
BTN_0_Count_8_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_8_SRINV_4694
);
BTN_0_Count_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_8_CLKINV_4693
);
BTN_0_Count_8_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y85",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_8_CEINVNOT
);
BTN_0_Count_10_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y86"
)
port map (
O => BTN_0_Count_10_LOGIC_ZERO_4761
);
BTN_0_Count_10_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_10_XORF_4787,
O => BTN_0_Count_10_DXMUX_4789
);
BTN_0_Count_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
I0 => BTN_0_Count_10_CYINIT_4786,
I1 => BTN_0_Count_10_F,
O => BTN_0_Count_10_XORF_4787
);
BTN_0_Count_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
IA => BTN_0_Count_10_LOGIC_ZERO_4761,
IB => BTN_0_Count_10_CYINIT_4786,
SEL => BTN_0_Count_10_CYSELF_4767,
O => BTN_0_Mcount_Count_cy(10)
);
BTN_0_Count_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
IA => BTN_0_Count_10_LOGIC_ZERO_4761,
IB => BTN_0_Count_10_LOGIC_ZERO_4761,
SEL => BTN_0_Count_10_CYSELF_4767,
O => BTN_0_Count_10_CYMUXF2_4762
);
BTN_0_Count_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(9),
O => BTN_0_Count_10_CYINIT_4786
);
BTN_0_Count_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_10_F,
O => BTN_0_Count_10_CYSELF_4767
);
BTN_0_Count_10_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_10_XORG_4769,
O => BTN_0_Count_10_DYMUX_4771
);
BTN_0_Count_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
I0 => BTN_0_Mcount_Count_cy(10),
I1 => BTN_0_Count_10_G,
O => BTN_0_Count_10_XORG_4769
);
BTN_0_Count_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_10_CYMUXFAST_4766,
O => BTN_0_Mcount_Count_cy(11)
);
BTN_0_Count_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(9),
O => BTN_0_Count_10_FASTCARRY_4764
);
BTN_0_Count_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
I0 => BTN_0_Count_10_CYSELG_4752,
I1 => BTN_0_Count_10_CYSELF_4767,
O => BTN_0_Count_10_CYAND_4765
);
BTN_0_Count_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
IA => BTN_0_Count_10_CYMUXG2_4763,
IB => BTN_0_Count_10_FASTCARRY_4764,
SEL => BTN_0_Count_10_CYAND_4765,
O => BTN_0_Count_10_CYMUXFAST_4766
);
BTN_0_Count_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y86"
)
port map (
IA => BTN_0_Count_10_LOGIC_ZERO_4761,
IB => BTN_0_Count_10_CYMUXF2_4762,
SEL => BTN_0_Count_10_CYSELG_4752,
O => BTN_0_Count_10_CYMUXG2_4763
);
BTN_0_Count_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_10_G,
O => BTN_0_Count_10_CYSELG_4752
);
BTN_0_Count_10_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_10_SRINV_4750
);
BTN_0_Count_10_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_10_CLKINV_4749
);
BTN_0_Count_10_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y86",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_10_CEINVNOT
);
BTN_0_Count_12_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y87"
)
port map (
O => BTN_0_Count_12_LOGIC_ZERO_4817
);
BTN_0_Count_12_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_12_XORF_4843,
O => BTN_0_Count_12_DXMUX_4845
);
BTN_0_Count_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
I0 => BTN_0_Count_12_CYINIT_4842,
I1 => BTN_0_Count_12_F,
O => BTN_0_Count_12_XORF_4843
);
BTN_0_Count_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
IA => BTN_0_Count_12_LOGIC_ZERO_4817,
IB => BTN_0_Count_12_CYINIT_4842,
SEL => BTN_0_Count_12_CYSELF_4823,
O => BTN_0_Mcount_Count_cy(12)
);
BTN_0_Count_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
IA => BTN_0_Count_12_LOGIC_ZERO_4817,
IB => BTN_0_Count_12_LOGIC_ZERO_4817,
SEL => BTN_0_Count_12_CYSELF_4823,
O => BTN_0_Count_12_CYMUXF2_4818
);
BTN_0_Count_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(11),
O => BTN_0_Count_12_CYINIT_4842
);
BTN_0_Count_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_12_F,
O => BTN_0_Count_12_CYSELF_4823
);
BTN_0_Count_12_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_12_XORG_4825,
O => BTN_0_Count_12_DYMUX_4827
);
BTN_0_Count_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
I0 => BTN_0_Mcount_Count_cy(12),
I1 => BTN_0_Count_12_G,
O => BTN_0_Count_12_XORG_4825
);
BTN_0_Count_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_12_CYMUXFAST_4822,
O => BTN_0_Mcount_Count_cy(13)
);
BTN_0_Count_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(11),
O => BTN_0_Count_12_FASTCARRY_4820
);
BTN_0_Count_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
I0 => BTN_0_Count_12_CYSELG_4808,
I1 => BTN_0_Count_12_CYSELF_4823,
O => BTN_0_Count_12_CYAND_4821
);
BTN_0_Count_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
IA => BTN_0_Count_12_CYMUXG2_4819,
IB => BTN_0_Count_12_FASTCARRY_4820,
SEL => BTN_0_Count_12_CYAND_4821,
O => BTN_0_Count_12_CYMUXFAST_4822
);
BTN_0_Count_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y87"
)
port map (
IA => BTN_0_Count_12_LOGIC_ZERO_4817,
IB => BTN_0_Count_12_CYMUXF2_4818,
SEL => BTN_0_Count_12_CYSELG_4808,
O => BTN_0_Count_12_CYMUXG2_4819
);
BTN_0_Count_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_12_G,
O => BTN_0_Count_12_CYSELG_4808
);
BTN_0_Count_12_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_12_SRINV_4806
);
BTN_0_Count_12_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_12_CLKINV_4805
);
BTN_0_Count_12_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y87",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_12_CEINVNOT
);
BTN_0_Count_14_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y88"
)
port map (
O => BTN_0_Count_14_LOGIC_ZERO_4873
);
BTN_0_Count_14_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_14_XORF_4899,
O => BTN_0_Count_14_DXMUX_4901
);
BTN_0_Count_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
I0 => BTN_0_Count_14_CYINIT_4898,
I1 => BTN_0_Count_14_F,
O => BTN_0_Count_14_XORF_4899
);
BTN_0_Count_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
IA => BTN_0_Count_14_LOGIC_ZERO_4873,
IB => BTN_0_Count_14_CYINIT_4898,
SEL => BTN_0_Count_14_CYSELF_4879,
O => BTN_0_Mcount_Count_cy(14)
);
BTN_0_Count_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
IA => BTN_0_Count_14_LOGIC_ZERO_4873,
IB => BTN_0_Count_14_LOGIC_ZERO_4873,
SEL => BTN_0_Count_14_CYSELF_4879,
O => BTN_0_Count_14_CYMUXF2_4874
);
BTN_0_Count_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(13),
O => BTN_0_Count_14_CYINIT_4898
);
BTN_0_Count_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_14_F,
O => BTN_0_Count_14_CYSELF_4879
);
BTN_0_Count_14_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_14_XORG_4881,
O => BTN_0_Count_14_DYMUX_4883
);
BTN_0_Count_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
I0 => BTN_0_Mcount_Count_cy(14),
I1 => BTN_0_Count_14_G,
O => BTN_0_Count_14_XORG_4881
);
BTN_0_Count_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_14_CYMUXFAST_4878,
O => BTN_0_Mcount_Count_cy(15)
);
BTN_0_Count_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(13),
O => BTN_0_Count_14_FASTCARRY_4876
);
BTN_0_Count_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
I0 => BTN_0_Count_14_CYSELG_4864,
I1 => BTN_0_Count_14_CYSELF_4879,
O => BTN_0_Count_14_CYAND_4877
);
BTN_0_Count_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
IA => BTN_0_Count_14_CYMUXG2_4875,
IB => BTN_0_Count_14_FASTCARRY_4876,
SEL => BTN_0_Count_14_CYAND_4877,
O => BTN_0_Count_14_CYMUXFAST_4878
);
BTN_0_Count_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y88"
)
port map (
IA => BTN_0_Count_14_LOGIC_ZERO_4873,
IB => BTN_0_Count_14_CYMUXF2_4874,
SEL => BTN_0_Count_14_CYSELG_4864,
O => BTN_0_Count_14_CYMUXG2_4875
);
BTN_0_Count_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_14_G,
O => BTN_0_Count_14_CYSELG_4864
);
BTN_0_Count_14_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_14_SRINV_4862
);
BTN_0_Count_14_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_14_CLKINV_4861
);
BTN_0_Count_14_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y88",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_14_CEINVNOT
);
BTN_0_Count_16_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y89"
)
port map (
O => BTN_0_Count_16_LOGIC_ZERO_4929
);
BTN_0_Count_16_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_16_XORF_4955,
O => BTN_0_Count_16_DXMUX_4957
);
BTN_0_Count_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
I0 => BTN_0_Count_16_CYINIT_4954,
I1 => BTN_0_Count_16_F,
O => BTN_0_Count_16_XORF_4955
);
BTN_0_Count_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
IA => BTN_0_Count_16_LOGIC_ZERO_4929,
IB => BTN_0_Count_16_CYINIT_4954,
SEL => BTN_0_Count_16_CYSELF_4935,
O => BTN_0_Mcount_Count_cy(16)
);
BTN_0_Count_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
IA => BTN_0_Count_16_LOGIC_ZERO_4929,
IB => BTN_0_Count_16_LOGIC_ZERO_4929,
SEL => BTN_0_Count_16_CYSELF_4935,
O => BTN_0_Count_16_CYMUXF2_4930
);
BTN_0_Count_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(15),
O => BTN_0_Count_16_CYINIT_4954
);
BTN_0_Count_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_16_F,
O => BTN_0_Count_16_CYSELF_4935
);
BTN_0_Count_16_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_16_XORG_4937,
O => BTN_0_Count_16_DYMUX_4939
);
BTN_0_Count_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
I0 => BTN_0_Mcount_Count_cy(16),
I1 => BTN_0_Count_16_G,
O => BTN_0_Count_16_XORG_4937
);
BTN_0_Count_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_16_CYMUXFAST_4934,
O => BTN_0_Mcount_Count_cy(17)
);
BTN_0_Count_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(15),
O => BTN_0_Count_16_FASTCARRY_4932
);
BTN_0_Count_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
I0 => BTN_0_Count_16_CYSELG_4920,
I1 => BTN_0_Count_16_CYSELF_4935,
O => BTN_0_Count_16_CYAND_4933
);
BTN_0_Count_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
IA => BTN_0_Count_16_CYMUXG2_4931,
IB => BTN_0_Count_16_FASTCARRY_4932,
SEL => BTN_0_Count_16_CYAND_4933,
O => BTN_0_Count_16_CYMUXFAST_4934
);
BTN_0_Count_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y89"
)
port map (
IA => BTN_0_Count_16_LOGIC_ZERO_4929,
IB => BTN_0_Count_16_CYMUXF2_4930,
SEL => BTN_0_Count_16_CYSELG_4920,
O => BTN_0_Count_16_CYMUXG2_4931
);
BTN_0_Count_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_16_G,
O => BTN_0_Count_16_CYSELG_4920
);
BTN_0_Count_16_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_16_SRINV_4918
);
BTN_0_Count_16_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_16_CLKINV_4917
);
BTN_0_Count_16_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y89",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_16_CEINVNOT
);
BTN_0_Count_18_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y90"
)
port map (
O => BTN_0_Count_18_LOGIC_ZERO_4985
);
BTN_0_Count_18_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_18_XORF_5011,
O => BTN_0_Count_18_DXMUX_5013
);
BTN_0_Count_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
I0 => BTN_0_Count_18_CYINIT_5010,
I1 => BTN_0_Count_18_F,
O => BTN_0_Count_18_XORF_5011
);
BTN_0_Count_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
IA => BTN_0_Count_18_LOGIC_ZERO_4985,
IB => BTN_0_Count_18_CYINIT_5010,
SEL => BTN_0_Count_18_CYSELF_4991,
O => BTN_0_Mcount_Count_cy(18)
);
BTN_0_Count_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
IA => BTN_0_Count_18_LOGIC_ZERO_4985,
IB => BTN_0_Count_18_LOGIC_ZERO_4985,
SEL => BTN_0_Count_18_CYSELF_4991,
O => BTN_0_Count_18_CYMUXF2_4986
);
BTN_0_Count_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(17),
O => BTN_0_Count_18_CYINIT_5010
);
BTN_0_Count_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_18_F,
O => BTN_0_Count_18_CYSELF_4991
);
BTN_0_Count_18_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_18_XORG_4993,
O => BTN_0_Count_18_DYMUX_4995
);
BTN_0_Count_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
I0 => BTN_0_Mcount_Count_cy(18),
I1 => BTN_0_Count_18_G,
O => BTN_0_Count_18_XORG_4993
);
BTN_0_Count_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Mcount_Count_cy(17),
O => BTN_0_Count_18_FASTCARRY_4988
);
BTN_0_Count_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
I0 => BTN_0_Count_18_CYSELG_4976,
I1 => BTN_0_Count_18_CYSELF_4991,
O => BTN_0_Count_18_CYAND_4989
);
BTN_0_Count_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
IA => BTN_0_Count_18_CYMUXG2_4987,
IB => BTN_0_Count_18_FASTCARRY_4988,
SEL => BTN_0_Count_18_CYAND_4989,
O => BTN_0_Count_18_CYMUXFAST_4990
);
BTN_0_Count_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y90"
)
port map (
IA => BTN_0_Count_18_LOGIC_ZERO_4985,
IB => BTN_0_Count_18_CYMUXF2_4986,
SEL => BTN_0_Count_18_CYSELG_4976,
O => BTN_0_Count_18_CYMUXG2_4987
);
BTN_0_Count_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_18_G,
O => BTN_0_Count_18_CYSELG_4976
);
BTN_0_Count_18_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_18_SRINV_4974
);
BTN_0_Count_18_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_18_CLKINV_4973
);
BTN_0_Count_18_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y90",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_18_CEINVNOT
);
BTN_0_Count_20_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y91",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_20_XORF_5038,
O => BTN_0_Count_20_DXMUX_5040
);
BTN_0_Count_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y91"
)
port map (
I0 => BTN_0_Count_20_CYINIT_5037,
I1 => BTN_0_Count_20_rt_5035,
O => BTN_0_Count_20_XORF_5038
);
BTN_0_Count_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y91",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_18_CYMUXFAST_4990,
O => BTN_0_Count_20_CYINIT_5037
);
BTN_0_Count_20_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y91",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count_and0000_0,
O => BTN_0_Count_20_SRINV_5027
);
BTN_0_Count_20_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y91",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_0_Count_20_CLKINV_5026
);
BTN_0_Count_20_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y91",
PATHPULSE => 638 ps
)
port map (
I => BTN_0_Count(20),
O => BTN_0_Count_20_CEINVNOT
);
SSeg_Result_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y14"
)
port map (
O => SSeg_Result_0_LOGIC_ZERO_5062
);
SSeg_Result_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X33Y14"
)
port map (
O => SSeg_Result_0_LOGIC_ONE_5079
);
SSeg_Result_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_0_XORF_5080,
O => SSeg_Result(0)
);
SSeg_Result_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y14"
)
port map (
I0 => SSeg_Result_0_CYINIT_5078,
I1 => SSeg_Mcount_count240hz_lut(0),
O => SSeg_Result_0_XORF_5080
);
SSeg_Result_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y14"
)
port map (
IA => SSeg_Result_0_LOGIC_ONE_5079,
IB => SSeg_Result_0_CYINIT_5078,
SEL => SSeg_Result_0_CYSELF_5069,
O => SSeg_Mcount_count240hz_cy(0)
);
SSeg_Result_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_0_BXINV_5067,
O => SSeg_Result_0_CYINIT_5078
);
SSeg_Result_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_lut(0),
O => SSeg_Result_0_CYSELF_5069
);
SSeg_Result_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => SSeg_Result_0_BXINV_5067
);
SSeg_Result_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_0_XORG_5065,
O => SSeg_Result(1)
);
SSeg_Result_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y14"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(0),
I1 => SSeg_Result_0_G,
O => SSeg_Result_0_XORG_5065
);
SSeg_Result_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_0_CYMUXG_5064,
O => SSeg_Mcount_count240hz_cy(1)
);
SSeg_Result_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X33Y14"
)
port map (
IA => SSeg_Result_0_LOGIC_ZERO_5062,
IB => SSeg_Mcount_count240hz_cy(0),
SEL => SSeg_Result_0_CYSELG_5053,
O => SSeg_Result_0_CYMUXG_5064
);
SSeg_Result_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y14",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_0_G,
O => SSeg_Result_0_CYSELG_5053
);
SSeg_Result_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y15"
)
port map (
O => SSeg_Result_2_LOGIC_ZERO_5098
);
SSeg_Result_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_2_XORF_5118,
O => SSeg_Result(2)
);
SSeg_Result_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
I0 => SSeg_Result_2_CYINIT_5117,
I1 => SSeg_Result_2_F,
O => SSeg_Result_2_XORF_5118
);
SSeg_Result_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
IA => SSeg_Result_2_LOGIC_ZERO_5098,
IB => SSeg_Result_2_CYINIT_5117,
SEL => SSeg_Result_2_CYSELF_5104,
O => SSeg_Mcount_count240hz_cy(2)
);
SSeg_Result_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
IA => SSeg_Result_2_LOGIC_ZERO_5098,
IB => SSeg_Result_2_LOGIC_ZERO_5098,
SEL => SSeg_Result_2_CYSELF_5104,
O => SSeg_Result_2_CYMUXF2_5099
);
SSeg_Result_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(1),
O => SSeg_Result_2_CYINIT_5117
);
SSeg_Result_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_2_F,
O => SSeg_Result_2_CYSELF_5104
);
SSeg_Result_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_2_XORG_5106,
O => SSeg_Result(3)
);
SSeg_Result_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(2),
I1 => SSeg_Result_2_G,
O => SSeg_Result_2_XORG_5106
);
SSeg_Result_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_2_CYMUXFAST_5103,
O => SSeg_Mcount_count240hz_cy(3)
);
SSeg_Result_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(1),
O => SSeg_Result_2_FASTCARRY_5101
);
SSeg_Result_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
I0 => SSeg_Result_2_CYSELG_5089,
I1 => SSeg_Result_2_CYSELF_5104,
O => SSeg_Result_2_CYAND_5102
);
SSeg_Result_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
IA => SSeg_Result_2_CYMUXG2_5100,
IB => SSeg_Result_2_FASTCARRY_5101,
SEL => SSeg_Result_2_CYAND_5102,
O => SSeg_Result_2_CYMUXFAST_5103
);
SSeg_Result_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y15"
)
port map (
IA => SSeg_Result_2_LOGIC_ZERO_5098,
IB => SSeg_Result_2_CYMUXF2_5099,
SEL => SSeg_Result_2_CYSELG_5089,
O => SSeg_Result_2_CYMUXG2_5100
);
SSeg_Result_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y15",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_2_G,
O => SSeg_Result_2_CYSELG_5089
);
SSeg_Result_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y16"
)
port map (
O => SSeg_Result_4_LOGIC_ZERO_5136
);
SSeg_Result_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_4_XORF_5156,
O => SSeg_Result(4)
);
SSeg_Result_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
I0 => SSeg_Result_4_CYINIT_5155,
I1 => SSeg_Result_4_F,
O => SSeg_Result_4_XORF_5156
);
SSeg_Result_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
IA => SSeg_Result_4_LOGIC_ZERO_5136,
IB => SSeg_Result_4_CYINIT_5155,
SEL => SSeg_Result_4_CYSELF_5142,
O => SSeg_Mcount_count240hz_cy(4)
);
SSeg_Result_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
IA => SSeg_Result_4_LOGIC_ZERO_5136,
IB => SSeg_Result_4_LOGIC_ZERO_5136,
SEL => SSeg_Result_4_CYSELF_5142,
O => SSeg_Result_4_CYMUXF2_5137
);
SSeg_Result_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(3),
O => SSeg_Result_4_CYINIT_5155
);
SSeg_Result_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_4_F,
O => SSeg_Result_4_CYSELF_5142
);
SSeg_Result_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_4_XORG_5144,
O => SSeg_Result(5)
);
SSeg_Result_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(4),
I1 => SSeg_Result_4_G,
O => SSeg_Result_4_XORG_5144
);
SSeg_Result_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_4_CYMUXFAST_5141,
O => SSeg_Mcount_count240hz_cy(5)
);
SSeg_Result_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(3),
O => SSeg_Result_4_FASTCARRY_5139
);
SSeg_Result_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
I0 => SSeg_Result_4_CYSELG_5127,
I1 => SSeg_Result_4_CYSELF_5142,
O => SSeg_Result_4_CYAND_5140
);
SSeg_Result_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
IA => SSeg_Result_4_CYMUXG2_5138,
IB => SSeg_Result_4_FASTCARRY_5139,
SEL => SSeg_Result_4_CYAND_5140,
O => SSeg_Result_4_CYMUXFAST_5141
);
SSeg_Result_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y16"
)
port map (
IA => SSeg_Result_4_LOGIC_ZERO_5136,
IB => SSeg_Result_4_CYMUXF2_5137,
SEL => SSeg_Result_4_CYSELG_5127,
O => SSeg_Result_4_CYMUXG2_5138
);
SSeg_Result_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y16",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_4_G,
O => SSeg_Result_4_CYSELG_5127
);
SSeg_Result_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y17"
)
port map (
O => SSeg_Result_6_LOGIC_ZERO_5174
);
SSeg_Result_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_6_XORF_5194,
O => SSeg_Result(6)
);
SSeg_Result_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
I0 => SSeg_Result_6_CYINIT_5193,
I1 => SSeg_Result_6_F,
O => SSeg_Result_6_XORF_5194
);
SSeg_Result_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
IA => SSeg_Result_6_LOGIC_ZERO_5174,
IB => SSeg_Result_6_CYINIT_5193,
SEL => SSeg_Result_6_CYSELF_5180,
O => SSeg_Mcount_count240hz_cy(6)
);
SSeg_Result_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
IA => SSeg_Result_6_LOGIC_ZERO_5174,
IB => SSeg_Result_6_LOGIC_ZERO_5174,
SEL => SSeg_Result_6_CYSELF_5180,
O => SSeg_Result_6_CYMUXF2_5175
);
SSeg_Result_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(5),
O => SSeg_Result_6_CYINIT_5193
);
SSeg_Result_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_6_F,
O => SSeg_Result_6_CYSELF_5180
);
SSeg_Result_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_6_XORG_5182,
O => SSeg_Result(7)
);
SSeg_Result_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(6),
I1 => SSeg_Result_6_G,
O => SSeg_Result_6_XORG_5182
);
SSeg_Result_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_6_CYMUXFAST_5179,
O => SSeg_Mcount_count240hz_cy(7)
);
SSeg_Result_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(5),
O => SSeg_Result_6_FASTCARRY_5177
);
SSeg_Result_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
I0 => SSeg_Result_6_CYSELG_5165,
I1 => SSeg_Result_6_CYSELF_5180,
O => SSeg_Result_6_CYAND_5178
);
SSeg_Result_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
IA => SSeg_Result_6_CYMUXG2_5176,
IB => SSeg_Result_6_FASTCARRY_5177,
SEL => SSeg_Result_6_CYAND_5178,
O => SSeg_Result_6_CYMUXFAST_5179
);
SSeg_Result_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y17"
)
port map (
IA => SSeg_Result_6_LOGIC_ZERO_5174,
IB => SSeg_Result_6_CYMUXF2_5175,
SEL => SSeg_Result_6_CYSELG_5165,
O => SSeg_Result_6_CYMUXG2_5176
);
SSeg_Result_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y17",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_6_G,
O => SSeg_Result_6_CYSELG_5165
);
SSeg_Result_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y18"
)
port map (
O => SSeg_Result_8_LOGIC_ZERO_5212
);
SSeg_Result_8_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_8_XORF_5232,
O => SSeg_Result(8)
);
SSeg_Result_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
I0 => SSeg_Result_8_CYINIT_5231,
I1 => SSeg_Result_8_F,
O => SSeg_Result_8_XORF_5232
);
SSeg_Result_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
IA => SSeg_Result_8_LOGIC_ZERO_5212,
IB => SSeg_Result_8_CYINIT_5231,
SEL => SSeg_Result_8_CYSELF_5218,
O => SSeg_Mcount_count240hz_cy(8)
);
SSeg_Result_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
IA => SSeg_Result_8_LOGIC_ZERO_5212,
IB => SSeg_Result_8_LOGIC_ZERO_5212,
SEL => SSeg_Result_8_CYSELF_5218,
O => SSeg_Result_8_CYMUXF2_5213
);
SSeg_Result_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(7),
O => SSeg_Result_8_CYINIT_5231
);
SSeg_Result_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_8_F,
O => SSeg_Result_8_CYSELF_5218
);
SSeg_Result_8_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_8_XORG_5220,
O => SSeg_Result(9)
);
SSeg_Result_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(8),
I1 => SSeg_Result_8_G,
O => SSeg_Result_8_XORG_5220
);
SSeg_Result_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_8_CYMUXFAST_5217,
O => SSeg_Mcount_count240hz_cy(9)
);
SSeg_Result_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(7),
O => SSeg_Result_8_FASTCARRY_5215
);
SSeg_Result_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
I0 => SSeg_Result_8_CYSELG_5203,
I1 => SSeg_Result_8_CYSELF_5218,
O => SSeg_Result_8_CYAND_5216
);
SSeg_Result_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
IA => SSeg_Result_8_CYMUXG2_5214,
IB => SSeg_Result_8_FASTCARRY_5215,
SEL => SSeg_Result_8_CYAND_5216,
O => SSeg_Result_8_CYMUXFAST_5217
);
SSeg_Result_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y18"
)
port map (
IA => SSeg_Result_8_LOGIC_ZERO_5212,
IB => SSeg_Result_8_CYMUXF2_5213,
SEL => SSeg_Result_8_CYSELG_5203,
O => SSeg_Result_8_CYMUXG2_5214
);
SSeg_Result_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_8_G,
O => SSeg_Result_8_CYSELG_5203
);
SSeg_Result_10_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y19"
)
port map (
O => SSeg_Result_10_LOGIC_ZERO_5250
);
SSeg_Result_10_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_10_XORF_5270,
O => SSeg_Result(10)
);
SSeg_Result_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
I0 => SSeg_Result_10_CYINIT_5269,
I1 => SSeg_Result_10_F,
O => SSeg_Result_10_XORF_5270
);
SSeg_Result_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
IA => SSeg_Result_10_LOGIC_ZERO_5250,
IB => SSeg_Result_10_CYINIT_5269,
SEL => SSeg_Result_10_CYSELF_5256,
O => SSeg_Mcount_count240hz_cy(10)
);
SSeg_Result_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
IA => SSeg_Result_10_LOGIC_ZERO_5250,
IB => SSeg_Result_10_LOGIC_ZERO_5250,
SEL => SSeg_Result_10_CYSELF_5256,
O => SSeg_Result_10_CYMUXF2_5251
);
SSeg_Result_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(9),
O => SSeg_Result_10_CYINIT_5269
);
SSeg_Result_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_10_F,
O => SSeg_Result_10_CYSELF_5256
);
SSeg_Result_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_10_XORG_5258,
O => SSeg_Result(11)
);
SSeg_Result_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(10),
I1 => SSeg_Result_10_G,
O => SSeg_Result_10_XORG_5258
);
SSeg_Result_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_10_CYMUXFAST_5255,
O => SSeg_Mcount_count240hz_cy(11)
);
SSeg_Result_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(9),
O => SSeg_Result_10_FASTCARRY_5253
);
SSeg_Result_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
I0 => SSeg_Result_10_CYSELG_5241,
I1 => SSeg_Result_10_CYSELF_5256,
O => SSeg_Result_10_CYAND_5254
);
SSeg_Result_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
IA => SSeg_Result_10_CYMUXG2_5252,
IB => SSeg_Result_10_FASTCARRY_5253,
SEL => SSeg_Result_10_CYAND_5254,
O => SSeg_Result_10_CYMUXFAST_5255
);
SSeg_Result_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y19"
)
port map (
IA => SSeg_Result_10_LOGIC_ZERO_5250,
IB => SSeg_Result_10_CYMUXF2_5251,
SEL => SSeg_Result_10_CYSELG_5241,
O => SSeg_Result_10_CYMUXG2_5252
);
SSeg_Result_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_10_G,
O => SSeg_Result_10_CYSELG_5241
);
SSeg_Result_12_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y20"
)
port map (
O => SSeg_Result_12_LOGIC_ZERO_5288
);
SSeg_Result_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_12_XORF_5308,
O => SSeg_Result(12)
);
SSeg_Result_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
I0 => SSeg_Result_12_CYINIT_5307,
I1 => SSeg_Result_12_F,
O => SSeg_Result_12_XORF_5308
);
SSeg_Result_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
IA => SSeg_Result_12_LOGIC_ZERO_5288,
IB => SSeg_Result_12_CYINIT_5307,
SEL => SSeg_Result_12_CYSELF_5294,
O => SSeg_Mcount_count240hz_cy(12)
);
SSeg_Result_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
IA => SSeg_Result_12_LOGIC_ZERO_5288,
IB => SSeg_Result_12_LOGIC_ZERO_5288,
SEL => SSeg_Result_12_CYSELF_5294,
O => SSeg_Result_12_CYMUXF2_5289
);
SSeg_Result_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(11),
O => SSeg_Result_12_CYINIT_5307
);
SSeg_Result_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_12_F,
O => SSeg_Result_12_CYSELF_5294
);
SSeg_Result_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_12_XORG_5296,
O => SSeg_Result(13)
);
SSeg_Result_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(12),
I1 => SSeg_Result_12_G,
O => SSeg_Result_12_XORG_5296
);
SSeg_Result_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_12_CYMUXFAST_5293,
O => SSeg_Mcount_count240hz_cy(13)
);
SSeg_Result_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(11),
O => SSeg_Result_12_FASTCARRY_5291
);
SSeg_Result_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
I0 => SSeg_Result_12_CYSELG_5279,
I1 => SSeg_Result_12_CYSELF_5294,
O => SSeg_Result_12_CYAND_5292
);
SSeg_Result_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
IA => SSeg_Result_12_CYMUXG2_5290,
IB => SSeg_Result_12_FASTCARRY_5291,
SEL => SSeg_Result_12_CYAND_5292,
O => SSeg_Result_12_CYMUXFAST_5293
);
SSeg_Result_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y20"
)
port map (
IA => SSeg_Result_12_LOGIC_ZERO_5288,
IB => SSeg_Result_12_CYMUXF2_5289,
SEL => SSeg_Result_12_CYSELG_5279,
O => SSeg_Result_12_CYMUXG2_5290
);
SSeg_Result_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_12_G,
O => SSeg_Result_12_CYSELG_5279
);
SSeg_Result_14_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X33Y21"
)
port map (
O => SSeg_Result_14_LOGIC_ZERO_5326
);
SSeg_Result_14_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_14_XORF_5346,
O => SSeg_Result(14)
);
SSeg_Result_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
I0 => SSeg_Result_14_CYINIT_5345,
I1 => SSeg_Result_14_F,
O => SSeg_Result_14_XORF_5346
);
SSeg_Result_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
IA => SSeg_Result_14_LOGIC_ZERO_5326,
IB => SSeg_Result_14_CYINIT_5345,
SEL => SSeg_Result_14_CYSELF_5332,
O => SSeg_Mcount_count240hz_cy(14)
);
SSeg_Result_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
IA => SSeg_Result_14_LOGIC_ZERO_5326,
IB => SSeg_Result_14_LOGIC_ZERO_5326,
SEL => SSeg_Result_14_CYSELF_5332,
O => SSeg_Result_14_CYMUXF2_5327
);
SSeg_Result_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(13),
O => SSeg_Result_14_CYINIT_5345
);
SSeg_Result_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X33Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_14_F,
O => SSeg_Result_14_CYSELF_5332
);
SSeg_Result_14_YUSED : X_BUF
generic map(
LOC => "SLICE_X33Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_14_XORG_5334,
O => SSeg_Result(15)
);
SSeg_Result_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
I0 => SSeg_Mcount_count240hz_cy(14),
I1 => SSeg_Result_14_G,
O => SSeg_Result_14_XORG_5334
);
SSeg_Result_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X33Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_cy(13),
O => SSeg_Result_14_FASTCARRY_5329
);
SSeg_Result_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
I0 => SSeg_Result_14_CYSELG_5317,
I1 => SSeg_Result_14_CYSELF_5332,
O => SSeg_Result_14_CYAND_5330
);
SSeg_Result_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
IA => SSeg_Result_14_CYMUXG2_5328,
IB => SSeg_Result_14_FASTCARRY_5329,
SEL => SSeg_Result_14_CYAND_5330,
O => SSeg_Result_14_CYMUXFAST_5331
);
SSeg_Result_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X33Y21"
)
port map (
IA => SSeg_Result_14_LOGIC_ZERO_5326,
IB => SSeg_Result_14_CYMUXF2_5327,
SEL => SSeg_Result_14_CYSELG_5317,
O => SSeg_Result_14_CYMUXG2_5328
);
SSeg_Result_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X33Y21",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_14_G,
O => SSeg_Result_14_CYSELG_5317
);
SSeg_Result_16_XUSED : X_BUF
generic map(
LOC => "SLICE_X33Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_16_XORF_5361,
O => SSeg_Result(16)
);
SSeg_Result_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X33Y22"
)
port map (
I0 => SSeg_Result_16_CYINIT_5360,
I1 => SSeg_count240hz_16_rt_5358,
O => SSeg_Result_16_XORF_5361
);
SSeg_Result_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X33Y22",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Result_14_CYMUXFAST_5331,
O => SSeg_Result_16_CYINIT_5360
);
SSeg_count240hz_16_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X33Y22"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz(16),
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_count240hz_16_rt_5358
);
BTN_2_Count_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y67"
)
port map (
O => BTN_2_Count_0_LOGIC_ZERO_5385
);
BTN_2_Count_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X65Y67"
)
port map (
O => BTN_2_Count_0_LOGIC_ONE_5408
);
BTN_2_Count_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_0_XORF_5409,
O => BTN_2_Count_0_DXMUX_5411
);
BTN_2_Count_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y67"
)
port map (
I0 => BTN_2_Count_0_CYINIT_5407,
I1 => BTN_2_Mcount_Count_lut(0),
O => BTN_2_Count_0_XORF_5409
);
BTN_2_Count_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y67"
)
port map (
IA => BTN_2_Count_0_LOGIC_ONE_5408,
IB => BTN_2_Count_0_CYINIT_5407,
SEL => BTN_2_Count_0_CYSELF_5398,
O => BTN_2_Mcount_Count_cy(0)
);
BTN_2_Count_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_0_BXINV_5396,
O => BTN_2_Count_0_CYINIT_5407
);
BTN_2_Count_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_lut(0),
O => BTN_2_Count_0_CYSELF_5398
);
BTN_2_Count_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => BTN_2_Count_0_BXINV_5396
);
BTN_2_Count_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_0_XORG_5388,
O => BTN_2_Count_0_DYMUX_5390
);
BTN_2_Count_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y67"
)
port map (
I0 => BTN_2_Mcount_Count_cy(0),
I1 => BTN_2_Count_0_G,
O => BTN_2_Count_0_XORG_5388
);
BTN_2_Count_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_0_CYMUXG_5387,
O => BTN_2_Mcount_Count_cy(1)
);
BTN_2_Count_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X65Y67"
)
port map (
IA => BTN_2_Count_0_LOGIC_ZERO_5385,
IB => BTN_2_Mcount_Count_cy(0),
SEL => BTN_2_Count_0_CYSELG_5376,
O => BTN_2_Count_0_CYMUXG_5387
);
BTN_2_Count_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_0_G,
O => BTN_2_Count_0_CYSELG_5376
);
BTN_2_Count_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_0_SRINV_5374
);
BTN_2_Count_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_0_CLKINV_5373
);
BTN_2_Count_0_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_0_CEINVNOT
);
BTN_2_Count_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y68"
)
port map (
O => BTN_2_Count_2_LOGIC_ZERO_5439
);
BTN_2_Count_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_2_XORF_5465,
O => BTN_2_Count_2_DXMUX_5467
);
BTN_2_Count_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
I0 => BTN_2_Count_2_CYINIT_5464,
I1 => BTN_2_Count_2_F,
O => BTN_2_Count_2_XORF_5465
);
BTN_2_Count_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
IA => BTN_2_Count_2_LOGIC_ZERO_5439,
IB => BTN_2_Count_2_CYINIT_5464,
SEL => BTN_2_Count_2_CYSELF_5445,
O => BTN_2_Mcount_Count_cy(2)
);
BTN_2_Count_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
IA => BTN_2_Count_2_LOGIC_ZERO_5439,
IB => BTN_2_Count_2_LOGIC_ZERO_5439,
SEL => BTN_2_Count_2_CYSELF_5445,
O => BTN_2_Count_2_CYMUXF2_5440
);
BTN_2_Count_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(1),
O => BTN_2_Count_2_CYINIT_5464
);
BTN_2_Count_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_2_F,
O => BTN_2_Count_2_CYSELF_5445
);
BTN_2_Count_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_2_XORG_5447,
O => BTN_2_Count_2_DYMUX_5449
);
BTN_2_Count_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
I0 => BTN_2_Mcount_Count_cy(2),
I1 => BTN_2_Count_2_G,
O => BTN_2_Count_2_XORG_5447
);
BTN_2_Count_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_2_CYMUXFAST_5444,
O => BTN_2_Mcount_Count_cy(3)
);
BTN_2_Count_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(1),
O => BTN_2_Count_2_FASTCARRY_5442
);
BTN_2_Count_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
I0 => BTN_2_Count_2_CYSELG_5430,
I1 => BTN_2_Count_2_CYSELF_5445,
O => BTN_2_Count_2_CYAND_5443
);
BTN_2_Count_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
IA => BTN_2_Count_2_CYMUXG2_5441,
IB => BTN_2_Count_2_FASTCARRY_5442,
SEL => BTN_2_Count_2_CYAND_5443,
O => BTN_2_Count_2_CYMUXFAST_5444
);
BTN_2_Count_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y68"
)
port map (
IA => BTN_2_Count_2_LOGIC_ZERO_5439,
IB => BTN_2_Count_2_CYMUXF2_5440,
SEL => BTN_2_Count_2_CYSELG_5430,
O => BTN_2_Count_2_CYMUXG2_5441
);
BTN_2_Count_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_2_G,
O => BTN_2_Count_2_CYSELG_5430
);
BTN_2_Count_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_2_SRINV_5428
);
BTN_2_Count_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_2_CLKINV_5427
);
BTN_2_Count_2_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_2_CEINVNOT
);
BTN_2_Count_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y69"
)
port map (
O => BTN_2_Count_4_LOGIC_ZERO_5495
);
BTN_2_Count_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_4_XORF_5521,
O => BTN_2_Count_4_DXMUX_5523
);
BTN_2_Count_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
I0 => BTN_2_Count_4_CYINIT_5520,
I1 => BTN_2_Count_4_F,
O => BTN_2_Count_4_XORF_5521
);
BTN_2_Count_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
IA => BTN_2_Count_4_LOGIC_ZERO_5495,
IB => BTN_2_Count_4_CYINIT_5520,
SEL => BTN_2_Count_4_CYSELF_5501,
O => BTN_2_Mcount_Count_cy(4)
);
BTN_2_Count_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
IA => BTN_2_Count_4_LOGIC_ZERO_5495,
IB => BTN_2_Count_4_LOGIC_ZERO_5495,
SEL => BTN_2_Count_4_CYSELF_5501,
O => BTN_2_Count_4_CYMUXF2_5496
);
BTN_2_Count_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(3),
O => BTN_2_Count_4_CYINIT_5520
);
BTN_2_Count_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_4_F,
O => BTN_2_Count_4_CYSELF_5501
);
BTN_2_Count_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_4_XORG_5503,
O => BTN_2_Count_4_DYMUX_5505
);
BTN_2_Count_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
I0 => BTN_2_Mcount_Count_cy(4),
I1 => BTN_2_Count_4_G,
O => BTN_2_Count_4_XORG_5503
);
BTN_2_Count_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_4_CYMUXFAST_5500,
O => BTN_2_Mcount_Count_cy(5)
);
BTN_2_Count_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(3),
O => BTN_2_Count_4_FASTCARRY_5498
);
BTN_2_Count_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
I0 => BTN_2_Count_4_CYSELG_5486,
I1 => BTN_2_Count_4_CYSELF_5501,
O => BTN_2_Count_4_CYAND_5499
);
BTN_2_Count_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
IA => BTN_2_Count_4_CYMUXG2_5497,
IB => BTN_2_Count_4_FASTCARRY_5498,
SEL => BTN_2_Count_4_CYAND_5499,
O => BTN_2_Count_4_CYMUXFAST_5500
);
BTN_2_Count_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y69"
)
port map (
IA => BTN_2_Count_4_LOGIC_ZERO_5495,
IB => BTN_2_Count_4_CYMUXF2_5496,
SEL => BTN_2_Count_4_CYSELG_5486,
O => BTN_2_Count_4_CYMUXG2_5497
);
BTN_2_Count_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_4_G,
O => BTN_2_Count_4_CYSELG_5486
);
BTN_2_Count_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_4_SRINV_5484
);
BTN_2_Count_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_4_CLKINV_5483
);
BTN_2_Count_4_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_4_CEINVNOT
);
BTN_2_Count_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y70"
)
port map (
O => BTN_2_Count_6_LOGIC_ZERO_5551
);
BTN_2_Count_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_6_XORF_5577,
O => BTN_2_Count_6_DXMUX_5579
);
BTN_2_Count_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
I0 => BTN_2_Count_6_CYINIT_5576,
I1 => BTN_2_Count_6_F,
O => BTN_2_Count_6_XORF_5577
);
BTN_2_Count_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
IA => BTN_2_Count_6_LOGIC_ZERO_5551,
IB => BTN_2_Count_6_CYINIT_5576,
SEL => BTN_2_Count_6_CYSELF_5557,
O => BTN_2_Mcount_Count_cy(6)
);
BTN_2_Count_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
IA => BTN_2_Count_6_LOGIC_ZERO_5551,
IB => BTN_2_Count_6_LOGIC_ZERO_5551,
SEL => BTN_2_Count_6_CYSELF_5557,
O => BTN_2_Count_6_CYMUXF2_5552
);
BTN_2_Count_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(5),
O => BTN_2_Count_6_CYINIT_5576
);
BTN_2_Count_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_6_F,
O => BTN_2_Count_6_CYSELF_5557
);
BTN_2_Count_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_6_XORG_5559,
O => BTN_2_Count_6_DYMUX_5561
);
BTN_2_Count_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
I0 => BTN_2_Mcount_Count_cy(6),
I1 => BTN_2_Count_6_G,
O => BTN_2_Count_6_XORG_5559
);
BTN_2_Count_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_6_CYMUXFAST_5556,
O => BTN_2_Mcount_Count_cy(7)
);
BTN_2_Count_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(5),
O => BTN_2_Count_6_FASTCARRY_5554
);
BTN_2_Count_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
I0 => BTN_2_Count_6_CYSELG_5542,
I1 => BTN_2_Count_6_CYSELF_5557,
O => BTN_2_Count_6_CYAND_5555
);
BTN_2_Count_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
IA => BTN_2_Count_6_CYMUXG2_5553,
IB => BTN_2_Count_6_FASTCARRY_5554,
SEL => BTN_2_Count_6_CYAND_5555,
O => BTN_2_Count_6_CYMUXFAST_5556
);
BTN_2_Count_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y70"
)
port map (
IA => BTN_2_Count_6_LOGIC_ZERO_5551,
IB => BTN_2_Count_6_CYMUXF2_5552,
SEL => BTN_2_Count_6_CYSELG_5542,
O => BTN_2_Count_6_CYMUXG2_5553
);
BTN_2_Count_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_6_G,
O => BTN_2_Count_6_CYSELG_5542
);
BTN_2_Count_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_6_SRINV_5540
);
BTN_2_Count_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_6_CLKINV_5539
);
BTN_2_Count_6_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_6_CEINVNOT
);
BTN_2_Count_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y71"
)
port map (
O => BTN_2_Count_8_LOGIC_ZERO_5607
);
BTN_2_Count_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_8_XORF_5633,
O => BTN_2_Count_8_DXMUX_5635
);
BTN_2_Count_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
I0 => BTN_2_Count_8_CYINIT_5632,
I1 => BTN_2_Count_8_F,
O => BTN_2_Count_8_XORF_5633
);
BTN_2_Count_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
IA => BTN_2_Count_8_LOGIC_ZERO_5607,
IB => BTN_2_Count_8_CYINIT_5632,
SEL => BTN_2_Count_8_CYSELF_5613,
O => BTN_2_Mcount_Count_cy(8)
);
BTN_2_Count_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
IA => BTN_2_Count_8_LOGIC_ZERO_5607,
IB => BTN_2_Count_8_LOGIC_ZERO_5607,
SEL => BTN_2_Count_8_CYSELF_5613,
O => BTN_2_Count_8_CYMUXF2_5608
);
BTN_2_Count_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(7),
O => BTN_2_Count_8_CYINIT_5632
);
BTN_2_Count_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_8_F,
O => BTN_2_Count_8_CYSELF_5613
);
BTN_2_Count_8_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_8_XORG_5615,
O => BTN_2_Count_8_DYMUX_5617
);
BTN_2_Count_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
I0 => BTN_2_Mcount_Count_cy(8),
I1 => BTN_2_Count_8_G,
O => BTN_2_Count_8_XORG_5615
);
BTN_2_Count_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_8_CYMUXFAST_5612,
O => BTN_2_Mcount_Count_cy(9)
);
BTN_2_Count_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(7),
O => BTN_2_Count_8_FASTCARRY_5610
);
BTN_2_Count_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
I0 => BTN_2_Count_8_CYSELG_5598,
I1 => BTN_2_Count_8_CYSELF_5613,
O => BTN_2_Count_8_CYAND_5611
);
BTN_2_Count_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
IA => BTN_2_Count_8_CYMUXG2_5609,
IB => BTN_2_Count_8_FASTCARRY_5610,
SEL => BTN_2_Count_8_CYAND_5611,
O => BTN_2_Count_8_CYMUXFAST_5612
);
BTN_2_Count_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y71"
)
port map (
IA => BTN_2_Count_8_LOGIC_ZERO_5607,
IB => BTN_2_Count_8_CYMUXF2_5608,
SEL => BTN_2_Count_8_CYSELG_5598,
O => BTN_2_Count_8_CYMUXG2_5609
);
BTN_2_Count_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_8_G,
O => BTN_2_Count_8_CYSELG_5598
);
BTN_2_Count_8_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_8_SRINV_5596
);
BTN_2_Count_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_8_CLKINV_5595
);
BTN_2_Count_8_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_8_CEINVNOT
);
BTN_2_Count_10_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y72"
)
port map (
O => BTN_2_Count_10_LOGIC_ZERO_5663
);
BTN_2_Count_10_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_10_XORF_5689,
O => BTN_2_Count_10_DXMUX_5691
);
BTN_2_Count_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
I0 => BTN_2_Count_10_CYINIT_5688,
I1 => BTN_2_Count_10_F,
O => BTN_2_Count_10_XORF_5689
);
BTN_2_Count_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
IA => BTN_2_Count_10_LOGIC_ZERO_5663,
IB => BTN_2_Count_10_CYINIT_5688,
SEL => BTN_2_Count_10_CYSELF_5669,
O => BTN_2_Mcount_Count_cy(10)
);
BTN_2_Count_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
IA => BTN_2_Count_10_LOGIC_ZERO_5663,
IB => BTN_2_Count_10_LOGIC_ZERO_5663,
SEL => BTN_2_Count_10_CYSELF_5669,
O => BTN_2_Count_10_CYMUXF2_5664
);
BTN_2_Count_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(9),
O => BTN_2_Count_10_CYINIT_5688
);
BTN_2_Count_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_10_F,
O => BTN_2_Count_10_CYSELF_5669
);
BTN_2_Count_10_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_10_XORG_5671,
O => BTN_2_Count_10_DYMUX_5673
);
BTN_2_Count_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
I0 => BTN_2_Mcount_Count_cy(10),
I1 => BTN_2_Count_10_G,
O => BTN_2_Count_10_XORG_5671
);
BTN_2_Count_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_10_CYMUXFAST_5668,
O => BTN_2_Mcount_Count_cy(11)
);
BTN_2_Count_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(9),
O => BTN_2_Count_10_FASTCARRY_5666
);
BTN_2_Count_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
I0 => BTN_2_Count_10_CYSELG_5654,
I1 => BTN_2_Count_10_CYSELF_5669,
O => BTN_2_Count_10_CYAND_5667
);
BTN_2_Count_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
IA => BTN_2_Count_10_CYMUXG2_5665,
IB => BTN_2_Count_10_FASTCARRY_5666,
SEL => BTN_2_Count_10_CYAND_5667,
O => BTN_2_Count_10_CYMUXFAST_5668
);
BTN_2_Count_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y72"
)
port map (
IA => BTN_2_Count_10_LOGIC_ZERO_5663,
IB => BTN_2_Count_10_CYMUXF2_5664,
SEL => BTN_2_Count_10_CYSELG_5654,
O => BTN_2_Count_10_CYMUXG2_5665
);
BTN_2_Count_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_10_G,
O => BTN_2_Count_10_CYSELG_5654
);
BTN_2_Count_10_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_10_SRINV_5652
);
BTN_2_Count_10_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_10_CLKINV_5651
);
BTN_2_Count_10_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y72",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_10_CEINVNOT
);
BTN_2_Count_12_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y73"
)
port map (
O => BTN_2_Count_12_LOGIC_ZERO_5719
);
BTN_2_Count_12_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_12_XORF_5745,
O => BTN_2_Count_12_DXMUX_5747
);
BTN_2_Count_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
I0 => BTN_2_Count_12_CYINIT_5744,
I1 => BTN_2_Count_12_F,
O => BTN_2_Count_12_XORF_5745
);
BTN_2_Count_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
IA => BTN_2_Count_12_LOGIC_ZERO_5719,
IB => BTN_2_Count_12_CYINIT_5744,
SEL => BTN_2_Count_12_CYSELF_5725,
O => BTN_2_Mcount_Count_cy(12)
);
BTN_2_Count_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
IA => BTN_2_Count_12_LOGIC_ZERO_5719,
IB => BTN_2_Count_12_LOGIC_ZERO_5719,
SEL => BTN_2_Count_12_CYSELF_5725,
O => BTN_2_Count_12_CYMUXF2_5720
);
BTN_2_Count_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(11),
O => BTN_2_Count_12_CYINIT_5744
);
BTN_2_Count_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_12_F,
O => BTN_2_Count_12_CYSELF_5725
);
BTN_2_Count_12_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_12_XORG_5727,
O => BTN_2_Count_12_DYMUX_5729
);
BTN_2_Count_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
I0 => BTN_2_Mcount_Count_cy(12),
I1 => BTN_2_Count_12_G,
O => BTN_2_Count_12_XORG_5727
);
BTN_2_Count_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_12_CYMUXFAST_5724,
O => BTN_2_Mcount_Count_cy(13)
);
BTN_2_Count_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(11),
O => BTN_2_Count_12_FASTCARRY_5722
);
BTN_2_Count_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
I0 => BTN_2_Count_12_CYSELG_5710,
I1 => BTN_2_Count_12_CYSELF_5725,
O => BTN_2_Count_12_CYAND_5723
);
BTN_2_Count_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
IA => BTN_2_Count_12_CYMUXG2_5721,
IB => BTN_2_Count_12_FASTCARRY_5722,
SEL => BTN_2_Count_12_CYAND_5723,
O => BTN_2_Count_12_CYMUXFAST_5724
);
BTN_2_Count_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y73"
)
port map (
IA => BTN_2_Count_12_LOGIC_ZERO_5719,
IB => BTN_2_Count_12_CYMUXF2_5720,
SEL => BTN_2_Count_12_CYSELG_5710,
O => BTN_2_Count_12_CYMUXG2_5721
);
BTN_2_Count_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_12_G,
O => BTN_2_Count_12_CYSELG_5710
);
BTN_2_Count_12_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_12_SRINV_5708
);
BTN_2_Count_12_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_12_CLKINV_5707
);
BTN_2_Count_12_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y73",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_12_CEINVNOT
);
BTN_2_Count_14_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y74"
)
port map (
O => BTN_2_Count_14_LOGIC_ZERO_5775
);
BTN_2_Count_14_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_14_XORF_5801,
O => BTN_2_Count_14_DXMUX_5803
);
BTN_2_Count_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
I0 => BTN_2_Count_14_CYINIT_5800,
I1 => BTN_2_Count_14_F,
O => BTN_2_Count_14_XORF_5801
);
BTN_2_Count_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
IA => BTN_2_Count_14_LOGIC_ZERO_5775,
IB => BTN_2_Count_14_CYINIT_5800,
SEL => BTN_2_Count_14_CYSELF_5781,
O => BTN_2_Mcount_Count_cy(14)
);
BTN_2_Count_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
IA => BTN_2_Count_14_LOGIC_ZERO_5775,
IB => BTN_2_Count_14_LOGIC_ZERO_5775,
SEL => BTN_2_Count_14_CYSELF_5781,
O => BTN_2_Count_14_CYMUXF2_5776
);
BTN_2_Count_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(13),
O => BTN_2_Count_14_CYINIT_5800
);
BTN_2_Count_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_14_F,
O => BTN_2_Count_14_CYSELF_5781
);
BTN_2_Count_14_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_14_XORG_5783,
O => BTN_2_Count_14_DYMUX_5785
);
BTN_2_Count_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
I0 => BTN_2_Mcount_Count_cy(14),
I1 => BTN_2_Count_14_G,
O => BTN_2_Count_14_XORG_5783
);
BTN_2_Count_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_14_CYMUXFAST_5780,
O => BTN_2_Mcount_Count_cy(15)
);
BTN_2_Count_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(13),
O => BTN_2_Count_14_FASTCARRY_5778
);
BTN_2_Count_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
I0 => BTN_2_Count_14_CYSELG_5766,
I1 => BTN_2_Count_14_CYSELF_5781,
O => BTN_2_Count_14_CYAND_5779
);
BTN_2_Count_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
IA => BTN_2_Count_14_CYMUXG2_5777,
IB => BTN_2_Count_14_FASTCARRY_5778,
SEL => BTN_2_Count_14_CYAND_5779,
O => BTN_2_Count_14_CYMUXFAST_5780
);
BTN_2_Count_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y74"
)
port map (
IA => BTN_2_Count_14_LOGIC_ZERO_5775,
IB => BTN_2_Count_14_CYMUXF2_5776,
SEL => BTN_2_Count_14_CYSELG_5766,
O => BTN_2_Count_14_CYMUXG2_5777
);
BTN_2_Count_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_14_G,
O => BTN_2_Count_14_CYSELG_5766
);
BTN_2_Count_14_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_14_SRINV_5764
);
BTN_2_Count_14_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_14_CLKINV_5763
);
BTN_2_Count_14_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y74",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_14_CEINVNOT
);
BTN_2_Count_16_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y75"
)
port map (
O => BTN_2_Count_16_LOGIC_ZERO_5831
);
BTN_2_Count_16_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_16_XORF_5857,
O => BTN_2_Count_16_DXMUX_5859
);
BTN_2_Count_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
I0 => BTN_2_Count_16_CYINIT_5856,
I1 => BTN_2_Count_16_F,
O => BTN_2_Count_16_XORF_5857
);
BTN_2_Count_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
IA => BTN_2_Count_16_LOGIC_ZERO_5831,
IB => BTN_2_Count_16_CYINIT_5856,
SEL => BTN_2_Count_16_CYSELF_5837,
O => BTN_2_Mcount_Count_cy(16)
);
BTN_2_Count_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
IA => BTN_2_Count_16_LOGIC_ZERO_5831,
IB => BTN_2_Count_16_LOGIC_ZERO_5831,
SEL => BTN_2_Count_16_CYSELF_5837,
O => BTN_2_Count_16_CYMUXF2_5832
);
BTN_2_Count_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(15),
O => BTN_2_Count_16_CYINIT_5856
);
BTN_2_Count_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_16_F,
O => BTN_2_Count_16_CYSELF_5837
);
BTN_2_Count_16_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_16_XORG_5839,
O => BTN_2_Count_16_DYMUX_5841
);
BTN_2_Count_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
I0 => BTN_2_Mcount_Count_cy(16),
I1 => BTN_2_Count_16_G,
O => BTN_2_Count_16_XORG_5839
);
BTN_2_Count_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_16_CYMUXFAST_5836,
O => BTN_2_Mcount_Count_cy(17)
);
BTN_2_Count_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(15),
O => BTN_2_Count_16_FASTCARRY_5834
);
BTN_2_Count_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
I0 => BTN_2_Count_16_CYSELG_5822,
I1 => BTN_2_Count_16_CYSELF_5837,
O => BTN_2_Count_16_CYAND_5835
);
BTN_2_Count_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
IA => BTN_2_Count_16_CYMUXG2_5833,
IB => BTN_2_Count_16_FASTCARRY_5834,
SEL => BTN_2_Count_16_CYAND_5835,
O => BTN_2_Count_16_CYMUXFAST_5836
);
BTN_2_Count_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y75"
)
port map (
IA => BTN_2_Count_16_LOGIC_ZERO_5831,
IB => BTN_2_Count_16_CYMUXF2_5832,
SEL => BTN_2_Count_16_CYSELG_5822,
O => BTN_2_Count_16_CYMUXG2_5833
);
BTN_2_Count_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_16_G,
O => BTN_2_Count_16_CYSELG_5822
);
BTN_2_Count_16_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_16_SRINV_5820
);
BTN_2_Count_16_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_16_CLKINV_5819
);
BTN_2_Count_16_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y75",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_16_CEINVNOT
);
BTN_2_Count_18_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X65Y76"
)
port map (
O => BTN_2_Count_18_LOGIC_ZERO_5887
);
BTN_2_Count_18_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_18_XORF_5913,
O => BTN_2_Count_18_DXMUX_5915
);
BTN_2_Count_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
I0 => BTN_2_Count_18_CYINIT_5912,
I1 => BTN_2_Count_18_F,
O => BTN_2_Count_18_XORF_5913
);
BTN_2_Count_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
IA => BTN_2_Count_18_LOGIC_ZERO_5887,
IB => BTN_2_Count_18_CYINIT_5912,
SEL => BTN_2_Count_18_CYSELF_5893,
O => BTN_2_Mcount_Count_cy(18)
);
BTN_2_Count_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
IA => BTN_2_Count_18_LOGIC_ZERO_5887,
IB => BTN_2_Count_18_LOGIC_ZERO_5887,
SEL => BTN_2_Count_18_CYSELF_5893,
O => BTN_2_Count_18_CYMUXF2_5888
);
BTN_2_Count_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(17),
O => BTN_2_Count_18_CYINIT_5912
);
BTN_2_Count_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_18_F,
O => BTN_2_Count_18_CYSELF_5893
);
BTN_2_Count_18_DYMUX : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_18_XORG_5895,
O => BTN_2_Count_18_DYMUX_5897
);
BTN_2_Count_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
I0 => BTN_2_Mcount_Count_cy(18),
I1 => BTN_2_Count_18_G,
O => BTN_2_Count_18_XORG_5895
);
BTN_2_Count_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Mcount_Count_cy(17),
O => BTN_2_Count_18_FASTCARRY_5890
);
BTN_2_Count_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
I0 => BTN_2_Count_18_CYSELG_5878,
I1 => BTN_2_Count_18_CYSELF_5893,
O => BTN_2_Count_18_CYAND_5891
);
BTN_2_Count_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
IA => BTN_2_Count_18_CYMUXG2_5889,
IB => BTN_2_Count_18_FASTCARRY_5890,
SEL => BTN_2_Count_18_CYAND_5891,
O => BTN_2_Count_18_CYMUXFAST_5892
);
BTN_2_Count_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X65Y76"
)
port map (
IA => BTN_2_Count_18_LOGIC_ZERO_5887,
IB => BTN_2_Count_18_CYMUXF2_5888,
SEL => BTN_2_Count_18_CYSELG_5878,
O => BTN_2_Count_18_CYMUXG2_5889
);
BTN_2_Count_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_18_G,
O => BTN_2_Count_18_CYSELG_5878
);
BTN_2_Count_18_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_18_SRINV_5876
);
BTN_2_Count_18_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_18_CLKINV_5875
);
BTN_2_Count_18_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y76",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_18_CEINVNOT
);
BTN_2_Count_20_DXMUX : X_BUF
generic map(
LOC => "SLICE_X65Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_20_XORF_5940,
O => BTN_2_Count_20_DXMUX_5942
);
BTN_2_Count_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X65Y77"
)
port map (
I0 => BTN_2_Count_20_CYINIT_5939,
I1 => BTN_2_Count_20_rt_5937,
O => BTN_2_Count_20_XORF_5940
);
BTN_2_Count_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X65Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_18_CYMUXFAST_5892,
O => BTN_2_Count_20_CYINIT_5939
);
BTN_2_Count_20_SRINV : X_BUF
generic map(
LOC => "SLICE_X65Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count_and0000_0,
O => BTN_2_Count_20_SRINV_5929
);
BTN_2_Count_20_CLKINV : X_BUF
generic map(
LOC => "SLICE_X65Y77",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_2_Count_20_CLKINV_5928
);
BTN_2_Count_20_CEINV : X_INV
generic map(
LOC => "SLICE_X65Y77",
PATHPULSE => 638 ps
)
port map (
I => BTN_2_Count(20),
O => BTN_2_Count_20_CEINVNOT
);
BTN_3_Count_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y61"
)
port map (
O => BTN_3_Count_0_LOGIC_ZERO_5970
);
BTN_3_Count_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X53Y61"
)
port map (
O => BTN_3_Count_0_LOGIC_ONE_5993
);
BTN_3_Count_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_0_XORF_5994,
O => BTN_3_Count_0_DXMUX_5996
);
BTN_3_Count_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y61"
)
port map (
I0 => BTN_3_Count_0_CYINIT_5992,
I1 => BTN_3_Mcount_Count_lut(0),
O => BTN_3_Count_0_XORF_5994
);
BTN_3_Count_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y61"
)
port map (
IA => BTN_3_Count_0_LOGIC_ONE_5993,
IB => BTN_3_Count_0_CYINIT_5992,
SEL => BTN_3_Count_0_CYSELF_5983,
O => BTN_3_Mcount_Count_cy(0)
);
BTN_3_Count_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_0_BXINV_5981,
O => BTN_3_Count_0_CYINIT_5992
);
BTN_3_Count_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_lut(0),
O => BTN_3_Count_0_CYSELF_5983
);
BTN_3_Count_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => BTN_3_Count_0_BXINV_5981
);
BTN_3_Count_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_0_XORG_5973,
O => BTN_3_Count_0_DYMUX_5975
);
BTN_3_Count_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y61"
)
port map (
I0 => BTN_3_Mcount_Count_cy(0),
I1 => BTN_3_Count_0_G,
O => BTN_3_Count_0_XORG_5973
);
BTN_3_Count_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_0_CYMUXG_5972,
O => BTN_3_Mcount_Count_cy(1)
);
BTN_3_Count_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X53Y61"
)
port map (
IA => BTN_3_Count_0_LOGIC_ZERO_5970,
IB => BTN_3_Mcount_Count_cy(0),
SEL => BTN_3_Count_0_CYSELG_5961,
O => BTN_3_Count_0_CYMUXG_5972
);
BTN_3_Count_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_0_G,
O => BTN_3_Count_0_CYSELG_5961
);
BTN_3_Count_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_0_SRINV_5959
);
BTN_3_Count_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_0_CLKINV_5958
);
BTN_3_Count_0_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y61",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_0_CEINVNOT
);
BTN_3_Count_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y62"
)
port map (
O => BTN_3_Count_2_LOGIC_ZERO_6024
);
BTN_3_Count_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_2_XORF_6050,
O => BTN_3_Count_2_DXMUX_6052
);
BTN_3_Count_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
I0 => BTN_3_Count_2_CYINIT_6049,
I1 => BTN_3_Count_2_F,
O => BTN_3_Count_2_XORF_6050
);
BTN_3_Count_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
IA => BTN_3_Count_2_LOGIC_ZERO_6024,
IB => BTN_3_Count_2_CYINIT_6049,
SEL => BTN_3_Count_2_CYSELF_6030,
O => BTN_3_Mcount_Count_cy(2)
);
BTN_3_Count_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
IA => BTN_3_Count_2_LOGIC_ZERO_6024,
IB => BTN_3_Count_2_LOGIC_ZERO_6024,
SEL => BTN_3_Count_2_CYSELF_6030,
O => BTN_3_Count_2_CYMUXF2_6025
);
BTN_3_Count_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(1),
O => BTN_3_Count_2_CYINIT_6049
);
BTN_3_Count_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_2_F,
O => BTN_3_Count_2_CYSELF_6030
);
BTN_3_Count_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_2_XORG_6032,
O => BTN_3_Count_2_DYMUX_6034
);
BTN_3_Count_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
I0 => BTN_3_Mcount_Count_cy(2),
I1 => BTN_3_Count_2_G,
O => BTN_3_Count_2_XORG_6032
);
BTN_3_Count_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_2_CYMUXFAST_6029,
O => BTN_3_Mcount_Count_cy(3)
);
BTN_3_Count_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(1),
O => BTN_3_Count_2_FASTCARRY_6027
);
BTN_3_Count_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
I0 => BTN_3_Count_2_CYSELG_6015,
I1 => BTN_3_Count_2_CYSELF_6030,
O => BTN_3_Count_2_CYAND_6028
);
BTN_3_Count_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
IA => BTN_3_Count_2_CYMUXG2_6026,
IB => BTN_3_Count_2_FASTCARRY_6027,
SEL => BTN_3_Count_2_CYAND_6028,
O => BTN_3_Count_2_CYMUXFAST_6029
);
BTN_3_Count_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y62"
)
port map (
IA => BTN_3_Count_2_LOGIC_ZERO_6024,
IB => BTN_3_Count_2_CYMUXF2_6025,
SEL => BTN_3_Count_2_CYSELG_6015,
O => BTN_3_Count_2_CYMUXG2_6026
);
BTN_3_Count_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_2_G,
O => BTN_3_Count_2_CYSELG_6015
);
BTN_3_Count_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_2_SRINV_6013
);
BTN_3_Count_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_2_CLKINV_6012
);
BTN_3_Count_2_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y62",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_2_CEINVNOT
);
BTN_3_Count_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y63"
)
port map (
O => BTN_3_Count_4_LOGIC_ZERO_6080
);
BTN_3_Count_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_4_XORF_6106,
O => BTN_3_Count_4_DXMUX_6108
);
BTN_3_Count_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
I0 => BTN_3_Count_4_CYINIT_6105,
I1 => BTN_3_Count_4_F,
O => BTN_3_Count_4_XORF_6106
);
BTN_3_Count_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
IA => BTN_3_Count_4_LOGIC_ZERO_6080,
IB => BTN_3_Count_4_CYINIT_6105,
SEL => BTN_3_Count_4_CYSELF_6086,
O => BTN_3_Mcount_Count_cy(4)
);
BTN_3_Count_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
IA => BTN_3_Count_4_LOGIC_ZERO_6080,
IB => BTN_3_Count_4_LOGIC_ZERO_6080,
SEL => BTN_3_Count_4_CYSELF_6086,
O => BTN_3_Count_4_CYMUXF2_6081
);
BTN_3_Count_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(3),
O => BTN_3_Count_4_CYINIT_6105
);
BTN_3_Count_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_4_F,
O => BTN_3_Count_4_CYSELF_6086
);
BTN_3_Count_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_4_XORG_6088,
O => BTN_3_Count_4_DYMUX_6090
);
BTN_3_Count_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
I0 => BTN_3_Mcount_Count_cy(4),
I1 => BTN_3_Count_4_G,
O => BTN_3_Count_4_XORG_6088
);
BTN_3_Count_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_4_CYMUXFAST_6085,
O => BTN_3_Mcount_Count_cy(5)
);
BTN_3_Count_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(3),
O => BTN_3_Count_4_FASTCARRY_6083
);
BTN_3_Count_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
I0 => BTN_3_Count_4_CYSELG_6071,
I1 => BTN_3_Count_4_CYSELF_6086,
O => BTN_3_Count_4_CYAND_6084
);
BTN_3_Count_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
IA => BTN_3_Count_4_CYMUXG2_6082,
IB => BTN_3_Count_4_FASTCARRY_6083,
SEL => BTN_3_Count_4_CYAND_6084,
O => BTN_3_Count_4_CYMUXFAST_6085
);
BTN_3_Count_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y63"
)
port map (
IA => BTN_3_Count_4_LOGIC_ZERO_6080,
IB => BTN_3_Count_4_CYMUXF2_6081,
SEL => BTN_3_Count_4_CYSELG_6071,
O => BTN_3_Count_4_CYMUXG2_6082
);
BTN_3_Count_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_4_G,
O => BTN_3_Count_4_CYSELG_6071
);
BTN_3_Count_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_4_SRINV_6069
);
BTN_3_Count_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_4_CLKINV_6068
);
BTN_3_Count_4_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y63",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_4_CEINVNOT
);
BTN_3_Count_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y64"
)
port map (
O => BTN_3_Count_6_LOGIC_ZERO_6136
);
BTN_3_Count_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_6_XORF_6162,
O => BTN_3_Count_6_DXMUX_6164
);
BTN_3_Count_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
I0 => BTN_3_Count_6_CYINIT_6161,
I1 => BTN_3_Count_6_F,
O => BTN_3_Count_6_XORF_6162
);
BTN_3_Count_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
IA => BTN_3_Count_6_LOGIC_ZERO_6136,
IB => BTN_3_Count_6_CYINIT_6161,
SEL => BTN_3_Count_6_CYSELF_6142,
O => BTN_3_Mcount_Count_cy(6)
);
BTN_3_Count_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
IA => BTN_3_Count_6_LOGIC_ZERO_6136,
IB => BTN_3_Count_6_LOGIC_ZERO_6136,
SEL => BTN_3_Count_6_CYSELF_6142,
O => BTN_3_Count_6_CYMUXF2_6137
);
BTN_3_Count_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(5),
O => BTN_3_Count_6_CYINIT_6161
);
BTN_3_Count_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_6_F,
O => BTN_3_Count_6_CYSELF_6142
);
BTN_3_Count_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_6_XORG_6144,
O => BTN_3_Count_6_DYMUX_6146
);
BTN_3_Count_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
I0 => BTN_3_Mcount_Count_cy(6),
I1 => BTN_3_Count_6_G,
O => BTN_3_Count_6_XORG_6144
);
BTN_3_Count_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_6_CYMUXFAST_6141,
O => BTN_3_Mcount_Count_cy(7)
);
BTN_3_Count_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(5),
O => BTN_3_Count_6_FASTCARRY_6139
);
BTN_3_Count_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
I0 => BTN_3_Count_6_CYSELG_6127,
I1 => BTN_3_Count_6_CYSELF_6142,
O => BTN_3_Count_6_CYAND_6140
);
BTN_3_Count_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
IA => BTN_3_Count_6_CYMUXG2_6138,
IB => BTN_3_Count_6_FASTCARRY_6139,
SEL => BTN_3_Count_6_CYAND_6140,
O => BTN_3_Count_6_CYMUXFAST_6141
);
BTN_3_Count_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y64"
)
port map (
IA => BTN_3_Count_6_LOGIC_ZERO_6136,
IB => BTN_3_Count_6_CYMUXF2_6137,
SEL => BTN_3_Count_6_CYSELG_6127,
O => BTN_3_Count_6_CYMUXG2_6138
);
BTN_3_Count_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_6_G,
O => BTN_3_Count_6_CYSELG_6127
);
BTN_3_Count_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_6_SRINV_6125
);
BTN_3_Count_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_6_CLKINV_6124
);
BTN_3_Count_6_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y64",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_6_CEINVNOT
);
BTN_3_Count_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y65"
)
port map (
O => BTN_3_Count_8_LOGIC_ZERO_6192
);
BTN_3_Count_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_8_XORF_6218,
O => BTN_3_Count_8_DXMUX_6220
);
BTN_3_Count_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
I0 => BTN_3_Count_8_CYINIT_6217,
I1 => BTN_3_Count_8_F,
O => BTN_3_Count_8_XORF_6218
);
BTN_3_Count_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
IA => BTN_3_Count_8_LOGIC_ZERO_6192,
IB => BTN_3_Count_8_CYINIT_6217,
SEL => BTN_3_Count_8_CYSELF_6198,
O => BTN_3_Mcount_Count_cy(8)
);
BTN_3_Count_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
IA => BTN_3_Count_8_LOGIC_ZERO_6192,
IB => BTN_3_Count_8_LOGIC_ZERO_6192,
SEL => BTN_3_Count_8_CYSELF_6198,
O => BTN_3_Count_8_CYMUXF2_6193
);
BTN_3_Count_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(7),
O => BTN_3_Count_8_CYINIT_6217
);
BTN_3_Count_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_8_F,
O => BTN_3_Count_8_CYSELF_6198
);
BTN_3_Count_8_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_8_XORG_6200,
O => BTN_3_Count_8_DYMUX_6202
);
BTN_3_Count_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
I0 => BTN_3_Mcount_Count_cy(8),
I1 => BTN_3_Count_8_G,
O => BTN_3_Count_8_XORG_6200
);
BTN_3_Count_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_8_CYMUXFAST_6197,
O => BTN_3_Mcount_Count_cy(9)
);
BTN_3_Count_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(7),
O => BTN_3_Count_8_FASTCARRY_6195
);
BTN_3_Count_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
I0 => BTN_3_Count_8_CYSELG_6183,
I1 => BTN_3_Count_8_CYSELF_6198,
O => BTN_3_Count_8_CYAND_6196
);
BTN_3_Count_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
IA => BTN_3_Count_8_CYMUXG2_6194,
IB => BTN_3_Count_8_FASTCARRY_6195,
SEL => BTN_3_Count_8_CYAND_6196,
O => BTN_3_Count_8_CYMUXFAST_6197
);
BTN_3_Count_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y65"
)
port map (
IA => BTN_3_Count_8_LOGIC_ZERO_6192,
IB => BTN_3_Count_8_CYMUXF2_6193,
SEL => BTN_3_Count_8_CYSELG_6183,
O => BTN_3_Count_8_CYMUXG2_6194
);
BTN_3_Count_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_8_G,
O => BTN_3_Count_8_CYSELG_6183
);
BTN_3_Count_8_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_8_SRINV_6181
);
BTN_3_Count_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_8_CLKINV_6180
);
BTN_3_Count_8_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y65",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_8_CEINVNOT
);
BTN_3_Count_10_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y66"
)
port map (
O => BTN_3_Count_10_LOGIC_ZERO_6248
);
BTN_3_Count_10_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_10_XORF_6274,
O => BTN_3_Count_10_DXMUX_6276
);
BTN_3_Count_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
I0 => BTN_3_Count_10_CYINIT_6273,
I1 => BTN_3_Count_10_F,
O => BTN_3_Count_10_XORF_6274
);
BTN_3_Count_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
IA => BTN_3_Count_10_LOGIC_ZERO_6248,
IB => BTN_3_Count_10_CYINIT_6273,
SEL => BTN_3_Count_10_CYSELF_6254,
O => BTN_3_Mcount_Count_cy(10)
);
BTN_3_Count_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
IA => BTN_3_Count_10_LOGIC_ZERO_6248,
IB => BTN_3_Count_10_LOGIC_ZERO_6248,
SEL => BTN_3_Count_10_CYSELF_6254,
O => BTN_3_Count_10_CYMUXF2_6249
);
BTN_3_Count_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(9),
O => BTN_3_Count_10_CYINIT_6273
);
BTN_3_Count_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_10_F,
O => BTN_3_Count_10_CYSELF_6254
);
BTN_3_Count_10_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_10_XORG_6256,
O => BTN_3_Count_10_DYMUX_6258
);
BTN_3_Count_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
I0 => BTN_3_Mcount_Count_cy(10),
I1 => BTN_3_Count_10_G,
O => BTN_3_Count_10_XORG_6256
);
BTN_3_Count_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_10_CYMUXFAST_6253,
O => BTN_3_Mcount_Count_cy(11)
);
BTN_3_Count_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(9),
O => BTN_3_Count_10_FASTCARRY_6251
);
BTN_3_Count_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
I0 => BTN_3_Count_10_CYSELG_6239,
I1 => BTN_3_Count_10_CYSELF_6254,
O => BTN_3_Count_10_CYAND_6252
);
BTN_3_Count_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
IA => BTN_3_Count_10_CYMUXG2_6250,
IB => BTN_3_Count_10_FASTCARRY_6251,
SEL => BTN_3_Count_10_CYAND_6252,
O => BTN_3_Count_10_CYMUXFAST_6253
);
BTN_3_Count_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y66"
)
port map (
IA => BTN_3_Count_10_LOGIC_ZERO_6248,
IB => BTN_3_Count_10_CYMUXF2_6249,
SEL => BTN_3_Count_10_CYSELG_6239,
O => BTN_3_Count_10_CYMUXG2_6250
);
BTN_3_Count_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_10_G,
O => BTN_3_Count_10_CYSELG_6239
);
BTN_3_Count_10_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_10_SRINV_6237
);
BTN_3_Count_10_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_10_CLKINV_6236
);
BTN_3_Count_10_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y66",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_10_CEINVNOT
);
BTN_3_Count_12_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y67"
)
port map (
O => BTN_3_Count_12_LOGIC_ZERO_6304
);
BTN_3_Count_12_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_12_XORF_6330,
O => BTN_3_Count_12_DXMUX_6332
);
BTN_3_Count_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
I0 => BTN_3_Count_12_CYINIT_6329,
I1 => BTN_3_Count_12_F,
O => BTN_3_Count_12_XORF_6330
);
BTN_3_Count_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
IA => BTN_3_Count_12_LOGIC_ZERO_6304,
IB => BTN_3_Count_12_CYINIT_6329,
SEL => BTN_3_Count_12_CYSELF_6310,
O => BTN_3_Mcount_Count_cy(12)
);
BTN_3_Count_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
IA => BTN_3_Count_12_LOGIC_ZERO_6304,
IB => BTN_3_Count_12_LOGIC_ZERO_6304,
SEL => BTN_3_Count_12_CYSELF_6310,
O => BTN_3_Count_12_CYMUXF2_6305
);
BTN_3_Count_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(11),
O => BTN_3_Count_12_CYINIT_6329
);
BTN_3_Count_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_12_F,
O => BTN_3_Count_12_CYSELF_6310
);
BTN_3_Count_12_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_12_XORG_6312,
O => BTN_3_Count_12_DYMUX_6314
);
BTN_3_Count_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
I0 => BTN_3_Mcount_Count_cy(12),
I1 => BTN_3_Count_12_G,
O => BTN_3_Count_12_XORG_6312
);
BTN_3_Count_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_12_CYMUXFAST_6309,
O => BTN_3_Mcount_Count_cy(13)
);
BTN_3_Count_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(11),
O => BTN_3_Count_12_FASTCARRY_6307
);
BTN_3_Count_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
I0 => BTN_3_Count_12_CYSELG_6295,
I1 => BTN_3_Count_12_CYSELF_6310,
O => BTN_3_Count_12_CYAND_6308
);
BTN_3_Count_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
IA => BTN_3_Count_12_CYMUXG2_6306,
IB => BTN_3_Count_12_FASTCARRY_6307,
SEL => BTN_3_Count_12_CYAND_6308,
O => BTN_3_Count_12_CYMUXFAST_6309
);
BTN_3_Count_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y67"
)
port map (
IA => BTN_3_Count_12_LOGIC_ZERO_6304,
IB => BTN_3_Count_12_CYMUXF2_6305,
SEL => BTN_3_Count_12_CYSELG_6295,
O => BTN_3_Count_12_CYMUXG2_6306
);
BTN_3_Count_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_12_G,
O => BTN_3_Count_12_CYSELG_6295
);
BTN_3_Count_12_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_12_SRINV_6293
);
BTN_3_Count_12_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_12_CLKINV_6292
);
BTN_3_Count_12_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y67",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_12_CEINVNOT
);
BTN_3_Count_14_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y68"
)
port map (
O => BTN_3_Count_14_LOGIC_ZERO_6360
);
BTN_3_Count_14_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_14_XORF_6386,
O => BTN_3_Count_14_DXMUX_6388
);
BTN_3_Count_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
I0 => BTN_3_Count_14_CYINIT_6385,
I1 => BTN_3_Count_14_F,
O => BTN_3_Count_14_XORF_6386
);
BTN_3_Count_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
IA => BTN_3_Count_14_LOGIC_ZERO_6360,
IB => BTN_3_Count_14_CYINIT_6385,
SEL => BTN_3_Count_14_CYSELF_6366,
O => BTN_3_Mcount_Count_cy(14)
);
BTN_3_Count_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
IA => BTN_3_Count_14_LOGIC_ZERO_6360,
IB => BTN_3_Count_14_LOGIC_ZERO_6360,
SEL => BTN_3_Count_14_CYSELF_6366,
O => BTN_3_Count_14_CYMUXF2_6361
);
BTN_3_Count_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(13),
O => BTN_3_Count_14_CYINIT_6385
);
BTN_3_Count_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_14_F,
O => BTN_3_Count_14_CYSELF_6366
);
BTN_3_Count_14_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_14_XORG_6368,
O => BTN_3_Count_14_DYMUX_6370
);
BTN_3_Count_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
I0 => BTN_3_Mcount_Count_cy(14),
I1 => BTN_3_Count_14_G,
O => BTN_3_Count_14_XORG_6368
);
BTN_3_Count_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_14_CYMUXFAST_6365,
O => BTN_3_Mcount_Count_cy(15)
);
BTN_3_Count_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(13),
O => BTN_3_Count_14_FASTCARRY_6363
);
BTN_3_Count_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
I0 => BTN_3_Count_14_CYSELG_6351,
I1 => BTN_3_Count_14_CYSELF_6366,
O => BTN_3_Count_14_CYAND_6364
);
BTN_3_Count_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
IA => BTN_3_Count_14_CYMUXG2_6362,
IB => BTN_3_Count_14_FASTCARRY_6363,
SEL => BTN_3_Count_14_CYAND_6364,
O => BTN_3_Count_14_CYMUXFAST_6365
);
BTN_3_Count_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y68"
)
port map (
IA => BTN_3_Count_14_LOGIC_ZERO_6360,
IB => BTN_3_Count_14_CYMUXF2_6361,
SEL => BTN_3_Count_14_CYSELG_6351,
O => BTN_3_Count_14_CYMUXG2_6362
);
BTN_3_Count_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_14_G,
O => BTN_3_Count_14_CYSELG_6351
);
BTN_3_Count_14_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_14_SRINV_6349
);
BTN_3_Count_14_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_14_CLKINV_6348
);
BTN_3_Count_14_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y68",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_14_CEINVNOT
);
BTN_3_Count_16_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y69"
)
port map (
O => BTN_3_Count_16_LOGIC_ZERO_6416
);
BTN_3_Count_16_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_16_XORF_6442,
O => BTN_3_Count_16_DXMUX_6444
);
BTN_3_Count_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
I0 => BTN_3_Count_16_CYINIT_6441,
I1 => BTN_3_Count_16_F,
O => BTN_3_Count_16_XORF_6442
);
BTN_3_Count_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
IA => BTN_3_Count_16_LOGIC_ZERO_6416,
IB => BTN_3_Count_16_CYINIT_6441,
SEL => BTN_3_Count_16_CYSELF_6422,
O => BTN_3_Mcount_Count_cy(16)
);
BTN_3_Count_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
IA => BTN_3_Count_16_LOGIC_ZERO_6416,
IB => BTN_3_Count_16_LOGIC_ZERO_6416,
SEL => BTN_3_Count_16_CYSELF_6422,
O => BTN_3_Count_16_CYMUXF2_6417
);
BTN_3_Count_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(15),
O => BTN_3_Count_16_CYINIT_6441
);
BTN_3_Count_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_16_F,
O => BTN_3_Count_16_CYSELF_6422
);
BTN_3_Count_16_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_16_XORG_6424,
O => BTN_3_Count_16_DYMUX_6426
);
BTN_3_Count_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
I0 => BTN_3_Mcount_Count_cy(16),
I1 => BTN_3_Count_16_G,
O => BTN_3_Count_16_XORG_6424
);
BTN_3_Count_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_16_CYMUXFAST_6421,
O => BTN_3_Mcount_Count_cy(17)
);
BTN_3_Count_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(15),
O => BTN_3_Count_16_FASTCARRY_6419
);
BTN_3_Count_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
I0 => BTN_3_Count_16_CYSELG_6407,
I1 => BTN_3_Count_16_CYSELF_6422,
O => BTN_3_Count_16_CYAND_6420
);
BTN_3_Count_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
IA => BTN_3_Count_16_CYMUXG2_6418,
IB => BTN_3_Count_16_FASTCARRY_6419,
SEL => BTN_3_Count_16_CYAND_6420,
O => BTN_3_Count_16_CYMUXFAST_6421
);
BTN_3_Count_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y69"
)
port map (
IA => BTN_3_Count_16_LOGIC_ZERO_6416,
IB => BTN_3_Count_16_CYMUXF2_6417,
SEL => BTN_3_Count_16_CYSELG_6407,
O => BTN_3_Count_16_CYMUXG2_6418
);
BTN_3_Count_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_16_G,
O => BTN_3_Count_16_CYSELG_6407
);
BTN_3_Count_16_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_16_SRINV_6405
);
BTN_3_Count_16_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_16_CLKINV_6404
);
BTN_3_Count_16_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y69",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_16_CEINVNOT
);
BTN_3_Count_18_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X53Y70"
)
port map (
O => BTN_3_Count_18_LOGIC_ZERO_6472
);
BTN_3_Count_18_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_18_XORF_6498,
O => BTN_3_Count_18_DXMUX_6500
);
BTN_3_Count_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
I0 => BTN_3_Count_18_CYINIT_6497,
I1 => BTN_3_Count_18_F,
O => BTN_3_Count_18_XORF_6498
);
BTN_3_Count_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
IA => BTN_3_Count_18_LOGIC_ZERO_6472,
IB => BTN_3_Count_18_CYINIT_6497,
SEL => BTN_3_Count_18_CYSELF_6478,
O => BTN_3_Mcount_Count_cy(18)
);
BTN_3_Count_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
IA => BTN_3_Count_18_LOGIC_ZERO_6472,
IB => BTN_3_Count_18_LOGIC_ZERO_6472,
SEL => BTN_3_Count_18_CYSELF_6478,
O => BTN_3_Count_18_CYMUXF2_6473
);
BTN_3_Count_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(17),
O => BTN_3_Count_18_CYINIT_6497
);
BTN_3_Count_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_18_F,
O => BTN_3_Count_18_CYSELF_6478
);
BTN_3_Count_18_DYMUX : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_18_XORG_6480,
O => BTN_3_Count_18_DYMUX_6482
);
BTN_3_Count_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
I0 => BTN_3_Mcount_Count_cy(18),
I1 => BTN_3_Count_18_G,
O => BTN_3_Count_18_XORG_6480
);
BTN_3_Count_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Mcount_Count_cy(17),
O => BTN_3_Count_18_FASTCARRY_6475
);
BTN_3_Count_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
I0 => BTN_3_Count_18_CYSELG_6463,
I1 => BTN_3_Count_18_CYSELF_6478,
O => BTN_3_Count_18_CYAND_6476
);
BTN_3_Count_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
IA => BTN_3_Count_18_CYMUXG2_6474,
IB => BTN_3_Count_18_FASTCARRY_6475,
SEL => BTN_3_Count_18_CYAND_6476,
O => BTN_3_Count_18_CYMUXFAST_6477
);
BTN_3_Count_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X53Y70"
)
port map (
IA => BTN_3_Count_18_LOGIC_ZERO_6472,
IB => BTN_3_Count_18_CYMUXF2_6473,
SEL => BTN_3_Count_18_CYSELG_6463,
O => BTN_3_Count_18_CYMUXG2_6474
);
BTN_3_Count_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_18_G,
O => BTN_3_Count_18_CYSELG_6463
);
BTN_3_Count_18_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_18_SRINV_6461
);
BTN_3_Count_18_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_18_CLKINV_6460
);
BTN_3_Count_18_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y70",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_18_CEINVNOT
);
BTN_3_Count_20_DXMUX : X_BUF
generic map(
LOC => "SLICE_X53Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_20_XORF_6525,
O => BTN_3_Count_20_DXMUX_6527
);
BTN_3_Count_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X53Y71"
)
port map (
I0 => BTN_3_Count_20_CYINIT_6524,
I1 => BTN_3_Count_20_rt_6522,
O => BTN_3_Count_20_XORF_6525
);
BTN_3_Count_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X53Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_18_CYMUXFAST_6477,
O => BTN_3_Count_20_CYINIT_6524
);
BTN_3_Count_20_SRINV : X_BUF
generic map(
LOC => "SLICE_X53Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count_and0000_0,
O => BTN_3_Count_20_SRINV_6514
);
BTN_3_Count_20_CLKINV : X_BUF
generic map(
LOC => "SLICE_X53Y71",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => BTN_3_Count_20_CLKINV_6513
);
BTN_3_Count_20_CEINV : X_INV
generic map(
LOC => "SLICE_X53Y71",
PATHPULSE => 638 ps
)
port map (
I => BTN_3_Count(20),
O => BTN_3_Count_20_CEINVNOT
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X35Y18"
)
port map (
O => SSeg_count240hz_cmp_eq0000_wg_cy_1_LOGIC_ZERO_6547
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X35Y18"
)
port map (
IA => SSeg_count240hz_cmp_eq0000_wg_cy_1_LOGIC_ZERO_6547,
IB => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYINIT_6561,
SEL => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELF_6552,
O => SSeg_count240hz_cmp_eq0000_wg_cy(0)
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_CYINIT : X_BUF
generic map(
LOC => "SLICE_X35Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_cy_1_BXINV_6550,
O => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYINIT_6561
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELF : X_BUF
generic map(
LOC => "SLICE_X35Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_lut(0),
O => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELF_6552
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X35Y18",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => SSeg_count240hz_cmp_eq0000_wg_cy_1_BXINV_6550
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X35Y18"
)
port map (
IA => SSeg_count240hz_cmp_eq0000_wg_cy_1_LOGIC_ZERO_6547,
IB => SSeg_count240hz_cmp_eq0000_wg_cy(0),
SEL => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELG_6541,
O => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYMUXG_6549
);
SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELG : X_BUF
generic map(
LOC => "SLICE_X35Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_lut(1),
O => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYSELG_6541
);
SSeg_count240hz_cmp_eq0000_wg_lut_1_Q : X_LUT4
generic map(
INIT => X"2000",
LOC => "SLICE_X35Y18"
)
port map (
ADR0 => SSeg_count240hz(5),
ADR1 => SSeg_count240hz(3),
ADR2 => SSeg_count240hz(7),
ADR3 => SSeg_count240hz(6),
O => SSeg_count240hz_cmp_eq0000_wg_lut(1)
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X35Y19"
)
port map (
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_LOGIC_ZERO_6579
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X35Y19"
)
port map (
IA => SSeg_count240hz_cmp_eq0000_wg_cy_3_LOGIC_ZERO_6579,
IB => SSeg_count240hz_cmp_eq0000_wg_cy_3_LOGIC_ZERO_6579,
SEL => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELF_6585,
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXF2_6580
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELF : X_BUF
generic map(
LOC => "SLICE_X35Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_lut(2),
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELF_6585
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X35Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_cy_1_CYMUXG_6549,
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_FASTCARRY_6582
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_CYAND : X_AND2
generic map(
LOC => "SLICE_X35Y19"
)
port map (
I0 => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELG_6573,
I1 => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELF_6585,
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYAND_6583
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X35Y19"
)
port map (
IA => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXG2_6581,
IB => SSeg_count240hz_cmp_eq0000_wg_cy_3_FASTCARRY_6582,
SEL => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYAND_6583,
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXFAST_6584
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X35Y19"
)
port map (
IA => SSeg_count240hz_cmp_eq0000_wg_cy_3_LOGIC_ZERO_6579,
IB => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXF2_6580,
SEL => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELG_6573,
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXG2_6581
);
SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELG : X_BUF
generic map(
LOC => "SLICE_X35Y19",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_lut(3),
O => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYSELG_6573
);
SSeg_count240hz_cmp_eq0000_wg_lut_3_Q : X_LUT4
generic map(
INIT => X"0100",
LOC => "SLICE_X35Y19"
)
port map (
ADR0 => SSeg_count240hz(0),
ADR1 => SSeg_count240hz(13),
ADR2 => SSeg_count240hz(11),
ADR3 => SSeg_count240hz(12),
O => SSeg_count240hz_cmp_eq0000_wg_lut(3)
);
SSeg_count240hz_cmp_eq0000_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X35Y20"
)
port map (
O => SSeg_count240hz_cmp_eq0000_LOGIC_ZERO_6606
);
SSeg_count240hz_cmp_eq0000_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X35Y20"
)
port map (
IA => SSeg_count240hz_cmp_eq0000_LOGIC_ZERO_6606,
IB => SSeg_count240hz_cmp_eq0000_CYINIT_6605,
SEL => SSeg_count240hz_cmp_eq0000_CYSELF_6599,
O => SSeg_count240hz_cmp_eq0000
);
SSeg_count240hz_cmp_eq0000_CYINIT : X_BUF
generic map(
LOC => "SLICE_X35Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_cy_3_CYMUXFAST_6584,
O => SSeg_count240hz_cmp_eq0000_CYINIT_6605
);
SSeg_count240hz_cmp_eq0000_CYSELF : X_BUF
generic map(
LOC => "SLICE_X35Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_count240hz_cmp_eq0000_wg_lut(4),
O => SSeg_count240hz_cmp_eq0000_CYSELF_6599
);
SSeg_count240hz_cmp_eq0000_wg_lut_4_Q : X_LUT4
generic map(
INIT => X"0080",
LOC => "SLICE_X35Y20"
)
port map (
ADR0 => SSeg_count240hz(16),
ADR1 => SSeg_count240hz(2),
ADR2 => SSeg_count240hz(15),
ADR3 => SSeg_count240hz(14),
O => SSeg_count240hz_cmp_eq0000_wg_lut(4)
);
CLK_BUFGP_IBUFG : X_BUF
generic map(
LOC => "IPAD29",
PATHPULSE => 638 ps
)
port map (
I => CLK,
O => CLK_INBUF
);
AN_0_OBUF : X_OBUF
generic map(
LOC => "PAD71"
)
port map (
I => AN_0_O,
O => AN(0)
);
AN_1_OBUF : X_OBUF
generic map(
LOC => "PAD79"
)
port map (
I => AN_1_O,
O => AN(1)
);
AN_2_OBUF : X_OBUF
generic map(
LOC => "PAD61"
)
port map (
I => AN_2_O,
O => AN(2)
);
AN_3_OBUF : X_OBUF
generic map(
LOC => "PAD67"
)
port map (
I => AN_3_O,
O => AN(3)
);
SW_0_IBUF : X_BUF
generic map(
LOC => "IPAD78",
PATHPULSE => 638 ps
)
port map (
I => SW(0),
O => SW_0_INBUF
);
SW_0_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD78",
PATHPULSE => 638 ps
)
port map (
I => SW_0_INBUF,
O => SW_0_IBUF_1741
);
SW_1_IBUF : X_BUF
generic map(
LOC => "IPAD83",
PATHPULSE => 638 ps
)
port map (
I => SW(1),
O => SW_1_INBUF
);
SW_1_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD83",
PATHPULSE => 638 ps
)
port map (
I => SW_1_INBUF,
O => SW_1_IBUF_1740
);
SW_2_IBUF : X_BUF
generic map(
LOC => "IPAD88",
PATHPULSE => 638 ps
)
port map (
I => SW(2),
O => SW_2_INBUF
);
SW_2_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD88",
PATHPULSE => 638 ps
)
port map (
I => SW_2_INBUF,
O => SW_2_IBUF_1744
);
SW_3_IBUF : X_BUF
generic map(
LOC => "IPAD93",
PATHPULSE => 638 ps
)
port map (
I => SW(3),
O => SW_3_INBUF
);
SW_3_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD93",
PATHPULSE => 638 ps
)
port map (
I => SW_3_INBUF,
O => SW_3_IBUF_1743
);
SW_4_IBUF : X_BUF
generic map(
LOC => "IPAD103",
PATHPULSE => 638 ps
)
port map (
I => SW(4),
O => SW_4_INBUF
);
SW_4_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD103",
PATHPULSE => 638 ps
)
port map (
I => SW_4_INBUF,
O => SW_4_IBUF_1749
);
SW_5_IBUF : X_BUF
generic map(
LOC => "IPAD98",
PATHPULSE => 638 ps
)
port map (
I => SW(5),
O => SW_5_INBUF
);
SW_5_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD98",
PATHPULSE => 638 ps
)
port map (
I => SW_5_INBUF,
O => SW_5_IBUF_1748
);
SW_6_IBUF : X_BUF
generic map(
LOC => "IPAD108",
PATHPULSE => 638 ps
)
port map (
I => SW(6),
O => SW_6_INBUF
);
SW_6_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD108",
PATHPULSE => 638 ps
)
port map (
I => SW_6_INBUF,
O => SW_6_IBUF_1754
);
SW_7_IBUF : X_BUF
generic map(
LOC => "IPAD112",
PATHPULSE => 638 ps
)
port map (
I => SW(7),
O => SW_7_INBUF
);
SW_7_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD112",
PATHPULSE => 638 ps
)
port map (
I => SW_7_INBUF,
O => SW_7_IBUF_1753
);
BTN_0_IBUF : X_BUF
generic map(
LOC => "IPAD59",
PATHPULSE => 638 ps
)
port map (
I => BTN(0),
O => BTN_0_INBUF
);
BTN_1_IBUF : X_BUF
generic map(
LOC => "IPAD64",
PATHPULSE => 638 ps
)
port map (
I => BTN(1),
O => BTN_1_INBUF
);
BTN_2_IBUF : X_BUF
generic map(
LOC => "IPAD68",
PATHPULSE => 638 ps
)
port map (
I => BTN(2),
O => BTN_2_INBUF
);
BTN_3_IBUF : X_BUF
generic map(
LOC => "IPAD73",
PATHPULSE => 638 ps
)
port map (
I => BTN(3),
O => BTN_3_INBUF
);
SEG_0_OBUF : X_OBUF
generic map(
LOC => "PAD95"
)
port map (
I => SEG_0_O,
O => SEG(0)
);
SEG_1_OBUF : X_OBUF
generic map(
LOC => "PAD72"
)
port map (
I => SEG_1_O,
O => SEG(1)
);
SEG_2_OBUF : X_OBUF
generic map(
LOC => "PAD63"
)
port map (
I => SEG_2_O,
O => SEG(2)
);
SEG_3_OBUF : X_OBUF
generic map(
LOC => "PAD62"
)
port map (
I => SEG_3_O,
O => SEG(3)
);
SEG_4_OBUF : X_OBUF
generic map(
LOC => "PAD70"
)
port map (
I => SEG_4_O,
O => SEG(4)
);
SEG_5_OBUF : X_OBUF
generic map(
LOC => "PAD87"
)
port map (
I => SEG_5_O,
O => SEG(5)
);
SEG_6_OBUF : X_OBUF
generic map(
LOC => "PAD77"
)
port map (
I => SEG_6_O,
O => SEG(6)
);
CLK_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX_X2Y11"
)
port map (
I0 => CLK_BUFGP_BUFG_I0_INV,
I1 => GND,
S => CLK_BUFGP_BUFG_S_INVNOT,
O => CLK_BUFGP
);
CLK_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX_X2Y11",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => CLK_BUFGP_BUFG_S_INVNOT
);
CLK_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX_X2Y11",
PATHPULSE => 638 ps
)
port map (
I => CLK_INBUF,
O => CLK_BUFGP_BUFG_I0_INV
);
N21_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y79",
PATHPULSE => 638 ps
)
port map (
I => N21_F5MUX_6801,
O => N21
);
N21_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X66Y79"
)
port map (
IA => ALU_Mux_ALU_OUT_0_51,
IB => N21_F,
SEL => N21_BXINV_6790,
O => N21_F5MUX_6801
);
N21_BXINV : X_BUF
generic map(
LOC => "SLICE_X66Y79",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(2),
O => N21_BXINV_6790
);
ALU_Mux_ALU_OUT_0_511 : X_LUT4
generic map(
INIT => X"0032",
LOC => "SLICE_X66Y79"
)
port map (
ADR0 => N26_0,
ADR1 => UXCntl_Unit_VALB(0),
ADR2 => N23,
ADR3 => UXCntl_Unit_VALB(1),
O => ALU_Mux_ALU_OUT_0_51
);
SSeg_Mmux_hexnum_mux0001257_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y35",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001257_F5MUX_6826,
O => SSeg_Mmux_hexnum_mux0001257
);
SSeg_Mmux_hexnum_mux0001257_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X66Y35"
)
port map (
IA => N100,
IB => N101,
SEL => SSeg_Mmux_hexnum_mux0001257_BXINV_6819,
O => SSeg_Mmux_hexnum_mux0001257_F5MUX_6826
);
SSeg_Mmux_hexnum_mux0001257_BXINV : X_BUF
generic map(
LOC => "SLICE_X66Y35",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(1),
O => SSeg_Mmux_hexnum_mux0001257_BXINV_6819
);
SSeg_Mmux_hexnum_mux0001257_F : X_LUT4
generic map(
INIT => X"0C00",
LOC => "SLICE_X66Y35"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => UXCntl_Unit_VALB(0),
ADR3 => UXCntl_Unit_VALA(4),
O => N100
);
SSeg_Mmux_hexnum_mux0001828_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y23",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001828_F5MUX_6851,
O => SSeg_Mmux_hexnum_mux0001828
);
SSeg_Mmux_hexnum_mux0001828_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X64Y23"
)
port map (
IA => N98,
IB => N99,
SEL => SSeg_Mmux_hexnum_mux0001828_BXINV_6844,
O => SSeg_Mmux_hexnum_mux0001828_F5MUX_6851
);
SSeg_Mmux_hexnum_mux0001828_BXINV : X_BUF
generic map(
LOC => "SLICE_X64Y23",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_OPCODE(2),
O => SSeg_Mmux_hexnum_mux0001828_BXINV_6844
);
SSeg_Mmux_hexnum_mux0001828_F : X_LUT4
generic map(
INIT => X"FFEE",
LOC => "SLICE_X64Y23"
)
port map (
ADR0 => UXCntl_Unit_VALA(3),
ADR1 => UXCntl_Unit_VALB(3),
ADR2 => VCC,
ADR3 => SSeg_Mmux_hexnum_mux0001825_0,
O => N98
);
SSeg_Mmux_hexnum_mux0001686_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y25",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux0001686_F5MUX_6876,
O => SSeg_Mmux_hexnum_mux0001686
);
SSeg_Mmux_hexnum_mux0001686_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X67Y25"
)
port map (
IA => N108,
IB => N109,
SEL => SSeg_Mmux_hexnum_mux0001686_BXINV_6869,
O => SSeg_Mmux_hexnum_mux0001686_F5MUX_6876
);
SSeg_Mmux_hexnum_mux0001686_BXINV : X_BUF
generic map(
LOC => "SLICE_X67Y25",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(2),
O => SSeg_Mmux_hexnum_mux0001686_BXINV_6869
);
SSeg_Mmux_hexnum_mux0001686_F : X_LUT4
generic map(
INIT => X"0C00",
LOC => "SLICE_X67Y25"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALA(3),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALB(0),
O => N108
);
SSeg_Mmux_hexnum_mux00014107_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y31",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014107_F5MUX_6901,
O => SSeg_Mmux_hexnum_mux00014107
);
SSeg_Mmux_hexnum_mux00014107_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X66Y31"
)
port map (
IA => N102,
IB => N103,
SEL => SSeg_Mmux_hexnum_mux00014107_BXINV_6894,
O => SSeg_Mmux_hexnum_mux00014107_F5MUX_6901
);
SSeg_Mmux_hexnum_mux00014107_BXINV : X_BUF
generic map(
LOC => "SLICE_X66Y31",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(0),
O => SSeg_Mmux_hexnum_mux00014107_BXINV_6894
);
SSeg_Mmux_hexnum_mux00014107_F : X_LUT4
generic map(
INIT => X"EC20",
LOC => "SLICE_X66Y31"
)
port map (
ADR0 => UXCntl_Unit_VALB(1),
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => UXCntl_Unit_VALA(3),
ADR3 => N11,
O => N102
);
SSeg_Mmux_hexnum_mux00014107_G : X_LUT4
generic map(
INIT => X"7250",
LOC => "SLICE_X66Y31"
)
port map (
ADR0 => UXCntl_Unit_VALB(1),
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => SSeg_Mmux_hexnum_mux0001476_0,
ADR3 => UXCntl_Unit_VALA(4),
O => N103
);
SSeg_Mmux_hexnum_mux00018194_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y25",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018194_F5MUX_6926,
O => SSeg_Mmux_hexnum_mux00018194
);
SSeg_Mmux_hexnum_mux00018194_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X65Y25"
)
port map (
IA => N104,
IB => N105,
SEL => SSeg_Mmux_hexnum_mux00018194_BXINV_6919,
O => SSeg_Mmux_hexnum_mux00018194_F5MUX_6926
);
SSeg_Mmux_hexnum_mux00018194_BXINV : X_BUF
generic map(
LOC => "SLICE_X65Y25",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(0),
O => SSeg_Mmux_hexnum_mux00018194_BXINV_6919
);
SSeg_Mmux_hexnum_mux00018194_F : X_LUT4
generic map(
INIT => X"F2F0",
LOC => "SLICE_X65Y25"
)
port map (
ADR0 => UXCntl_Unit_VALA(3),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => SSeg_Mmux_hexnum_mux00018143_0,
ADR3 => UXCntl_Unit_VALB(2),
O => N104
);
SSeg_Mmux_hexnum_mux00018194_G : X_LUT4
generic map(
INIT => X"F0F8",
LOC => "SLICE_X65Y25"
)
port map (
ADR0 => UXCntl_Unit_VALA(4),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => SSeg_Mmux_hexnum_mux00018187_0,
ADR3 => UXCntl_Unit_VALB(2),
O => N105
);
SSeg_Mmux_hexnum_mux00018290_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00018290_F5MUX_6951,
O => SSeg_Mmux_hexnum_mux00018290
);
SSeg_Mmux_hexnum_mux00018290_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X67Y28"
)
port map (
IA => N96,
IB => N97,
SEL => SSeg_Mmux_hexnum_mux00018290_BXINV_6944,
O => SSeg_Mmux_hexnum_mux00018290_F5MUX_6951
);
SSeg_Mmux_hexnum_mux00018290_BXINV : X_BUF
generic map(
LOC => "SLICE_X67Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_pos(0),
O => SSeg_Mmux_hexnum_mux00018290_BXINV_6944
);
SSeg_Mmux_hexnum_mux00018290_G : X_LUT4
generic map(
INIT => X"FFEC",
LOC => "SLICE_X67Y28"
)
port map (
ADR0 => arith(3),
ADR1 => SSeg_Mmux_hexnum_mux0001878_0,
ADR2 => N30,
ADR3 => SSeg_Mmux_hexnum_mux0001845_0,
O => N97
);
SSeg_Mmux_hexnum_mux00018290_F : X_LUT4
generic map(
INIT => X"FFEC",
LOC => "SLICE_X67Y28"
)
port map (
ADR0 => arith(7),
ADR1 => SSeg_Mmux_hexnum_mux00018252_0,
ADR2 => N30,
ADR3 => SSeg_Mmux_hexnum_mux00018120_0,
O => N96
);
N68_XUSED : X_BUF
generic map(
LOC => "SLICE_X65Y20",
PATHPULSE => 638 ps
)
port map (
I => N68_F5MUX_6976,
O => N68
);
N68_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X65Y20"
)
port map (
IA => N106,
IB => N107,
SEL => N68_BXINV_6969,
O => N68_F5MUX_6976
);
N68_BXINV : X_BUF
generic map(
LOC => "SLICE_X65Y20",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(2),
O => N68_BXINV_6969
);
SSeg_Mmux_hexnum_mux00016263_SW0_F : X_LUT4
generic map(
INIT => X"08FF",
LOC => "SLICE_X65Y20"
)
port map (
ADR0 => UXCntl_Unit_VALA(5),
ADR1 => UXCntl_Unit_VALB(0),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => N78_0,
O => N106
);
SSeg_Mmux_hexnum_mux00016263_SW0_G : X_LUT4
generic map(
INIT => X"0ACC",
LOC => "SLICE_X65Y20"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => N12,
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALB(0),
O => N107
);
SSeg_Mmux_hexnum_mux00012171_XUSED : X_BUF
generic map(
LOC => "SLICE_X64Y34",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012171_F5MUX_7001,
O => SSeg_Mmux_hexnum_mux00012171
);
SSeg_Mmux_hexnum_mux00012171_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X64Y34"
)
port map (
IA => SSeg_Mmux_hexnum_mux000121712_6991,
IB => SSeg_Mmux_hexnum_mux000121711_6999,
SEL => SSeg_Mmux_hexnum_mux00012171_BXINV_6993,
O => SSeg_Mmux_hexnum_mux00012171_F5MUX_7001
);
SSeg_Mmux_hexnum_mux00012171_BXINV : X_BUF
generic map(
LOC => "SLICE_X64Y34",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(0),
O => SSeg_Mmux_hexnum_mux00012171_BXINV_6993
);
SSeg_Mmux_hexnum_mux000121712 : X_LUT4
generic map(
INIT => X"4000",
LOC => "SLICE_X64Y34"
)
port map (
ADR0 => UXCntl_Unit_VALB(2),
ADR1 => UXCntl_Unit_VALA(6),
ADR2 => N23,
ADR3 => UXCntl_Unit_VALB(1),
O => SSeg_Mmux_hexnum_mux000121712_6991
);
SSeg_Mmux_hexnum_mux00014312_XUSED : X_BUF
generic map(
LOC => "SLICE_X67Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014312_F5MUX_7026,
O => SSeg_Mmux_hexnum_mux00014312
);
SSeg_Mmux_hexnum_mux00014312_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X67Y20"
)
port map (
IA => SSeg_Mmux_hexnum_mux000143122_7017,
IB => SSeg_Mmux_hexnum_mux000143121_7024,
SEL => SSeg_Mmux_hexnum_mux00014312_BXINV_7019,
O => SSeg_Mmux_hexnum_mux00014312_F5MUX_7026
);
SSeg_Mmux_hexnum_mux00014312_BXINV : X_BUF
generic map(
LOC => "SLICE_X67Y20",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_OPCODE(2),
O => SSeg_Mmux_hexnum_mux00014312_BXINV_7019
);
SSeg_Mmux_hexnum_mux000143122 : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X67Y20"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALB(5),
ADR2 => VCC,
ADR3 => UXCntl_Unit_VALA(5),
O => SSeg_Mmux_hexnum_mux000143122_7017
);
SSeg_Mmux_hexnum_mux00016175_XUSED : X_BUF
generic map(
LOC => "SLICE_X66Y33",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016175_F5MUX_7051,
O => SSeg_Mmux_hexnum_mux00016175
);
SSeg_Mmux_hexnum_mux00016175_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X66Y33"
)
port map (
IA => SSeg_Mmux_hexnum_mux000161751_7038,
IB => SSeg_Mmux_hexnum_mux00016175_F,
SEL => SSeg_Mmux_hexnum_mux00016175_BXINV_7040,
O => SSeg_Mmux_hexnum_mux00016175_F5MUX_7051
);
SSeg_Mmux_hexnum_mux00016175_BXINV : X_BUF
generic map(
LOC => "SLICE_X66Y33",
PATHPULSE => 638 ps
)
port map (
I => UXCntl_Unit_VALB(2),
O => SSeg_Mmux_hexnum_mux00016175_BXINV_7040
);
SSeg_Mmux_hexnum_mux000161751 : X_LUT4
generic map(
INIT => X"0800",
LOC => "SLICE_X66Y33"
)
port map (
ADR0 => N23,
ADR1 => UXCntl_Unit_VALB(0),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALA(7),
O => SSeg_Mmux_hexnum_mux000161751_7038
);
SSeg_hexnum_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y29",
PATHPULSE => 638 ps
)
port map (
I => SSeg_hexnum_mux0001(0),
O => SSeg_hexnum_0_DXMUX_7079
);
SSeg_hexnum_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X67Y29",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00012292_O_pack_1,
O => SSeg_Mmux_hexnum_mux00012292_O
);
SSeg_hexnum_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y29",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_hexnum_0_CLKINV_7062
);
SSeg_Mmux_hexnum_mux00012292 : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X67Y29"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux00012111_0,
ADR1 => SSeg_pos(0),
ADR2 => SSeg_Mmux_hexnum_mux00012263_0,
ADR3 => SSeg_Mmux_hexnum_mux0001222_0,
O => SSeg_Mmux_hexnum_mux00012292_O_pack_1
);
SSeg_hexnum_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X66Y38",
PATHPULSE => 638 ps
)
port map (
I => SSeg_hexnum_mux0001(1),
O => SSeg_hexnum_1_DXMUX_7109
);
SSeg_hexnum_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y38",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00014384_SW0_O_pack_2,
O => SSeg_Mmux_hexnum_mux00014384_SW0_O
);
SSeg_hexnum_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X66Y38",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_hexnum_1_CLKINV_7093
);
SSeg_Mmux_hexnum_mux00014384_SW0 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X66Y38"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux00014147_0,
ADR1 => VCC,
ADR2 => SSeg_pos(1),
ADR3 => SSeg_DP_OUT_1865,
O => SSeg_Mmux_hexnum_mux00014384_SW0_O_pack_2
);
SSeg_hexnum_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X66Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_hexnum_mux0001(2),
O => SSeg_hexnum_2_DXMUX_7139
);
SSeg_hexnum_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X66Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mmux_hexnum_mux00016330_O_pack_1,
O => SSeg_Mmux_hexnum_mux00016330_O
);
SSeg_hexnum_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X66Y28",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_hexnum_2_CLKINV_7122
);
SSeg_Mmux_hexnum_mux00016330 : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X66Y28"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux00016180_0,
ADR1 => SSeg_Mmux_hexnum_mux00016289_0,
ADR2 => SSeg_pos(0),
ADR3 => N62_0,
O => SSeg_Mmux_hexnum_mux00016330_O_pack_1
);
SSeg_hexnum_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y31",
PATHPULSE => 638 ps
)
port map (
I => SSeg_hexnum_mux0001(3),
O => SSeg_hexnum_3_DYMUX_7157
);
SSeg_hexnum_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y31",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_hexnum_3_CLKINV_7147
);
SSeg_Mmux_hexnum_mux00018298 : X_LUT4
generic map(
INIT => X"AA00",
LOC => "SLICE_X67Y31"
)
port map (
ADR0 => SSeg_pos(1),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_Mmux_hexnum_mux00018290,
O => SSeg_hexnum_mux0001(3)
);
SSeg_AN_OUT_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X67Y61",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mrom_AN_OUT_mux00011,
O => SSeg_AN_OUT_1_DXMUX_7191
);
SSeg_AN_OUT_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X67Y61",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mrom_AN_OUT_mux0001,
O => SSeg_AN_OUT_1_DYMUX_7178
);
SSeg_AN_OUT_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X67Y61",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_AN_OUT_1_CLKINV_7168
);
SSeg_Mrom_AN_OUT_mux000111 : X_LUT4
generic map(
INIT => X"0FFF",
LOC => "SLICE_X67Y61"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => SSeg_pos(0),
ADR3 => SSeg_pos(1),
O => SSeg_Mrom_AN_OUT_mux0001
);
SSeg_AN_OUT_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X66Y81",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mrom_AN_OUT_mux00013,
O => SSeg_AN_OUT_3_DXMUX_7225
);
SSeg_AN_OUT_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X66Y81",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mrom_AN_OUT_mux00012,
O => SSeg_AN_OUT_3_DYMUX_7212
);
SSeg_AN_OUT_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X66Y81",
PATHPULSE => 638 ps
)
port map (
I => SSeg_clk240hz_1793,
O => SSeg_AN_OUT_3_CLKINV_7202
);
SSeg_Mrom_AN_OUT_mux000121 : X_LUT4
generic map(
INIT => X"CCFF",
LOC => "SLICE_X66Y81"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_pos(1),
ADR2 => VCC,
ADR3 => SSeg_pos(0),
O => SSeg_Mrom_AN_OUT_mux00012
);
SSeg_count240hz_11_DXMUX : X_BUF
generic map(
LOC => "SLICE_X32Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_11,
O => SSeg_count240hz_11_DXMUX_7259
);
SSeg_count240hz_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X32Y18",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_10,
O => SSeg_count240hz_11_DYMUX_7246
);
SSeg_count240hz_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X32Y18",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_11_CLKINV_7236
);
SSeg_Mcount_count240hz_eqn_101 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X32Y18"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => SSeg_Result(10),
O => SSeg_Mcount_count240hz_eqn_10
);
SSeg_count240hz_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X32Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_13,
O => SSeg_count240hz_13_DXMUX_7293
);
SSeg_count240hz_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X32Y20",
PATHPULSE => 638 ps
)
port map (
I => SSeg_Mcount_count240hz_eqn_12,
O => SSeg_count240hz_13_DYMUX_7280
);
SSeg_count240hz_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X32Y20",
PATHPULSE => 638 ps
)
port map (
I => CLK_BUFGP,
O => SSeg_count240hz_13_CLKINV_7270
);
SSeg_Mcount_count240hz_eqn_121 : X_LUT4
generic map(
INIT => X"0C0C",
LOC => "SLICE_X32Y20"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(12),
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_12
);
SSeg_count240hz_14 : X_FF
generic map(
LOC => "SLICE_X32Y21",
INIT => '0'
)
port map (
I => SSeg_count240hz_15_DYMUX_2072,
CE => VCC,
CLK => SSeg_count240hz_15_CLKINV_2062,
SET => GND,
RST => GND,
O => SSeg_count240hz(14)
);
SSeg_Mcount_count240hz_eqn_151 : X_LUT4
generic map(
INIT => X"00AA",
LOC => "SLICE_X32Y21"
)
port map (
ADR0 => SSeg_Result(15),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz_cmp_eq0000,
O => SSeg_Mcount_count240hz_eqn_15
);
SSeg_count240hz_15 : X_FF
generic map(
LOC => "SLICE_X32Y21",
INIT => '0'
)
port map (
I => SSeg_count240hz_15_DXMUX_2085,
CE => VCC,
CLK => SSeg_count240hz_15_CLKINV_2062,
SET => GND,
RST => GND,
O => SSeg_count240hz(15)
);
SSeg_count240hz_16 : X_FF
generic map(
LOC => "SLICE_X35Y22",
INIT => '0'
)
port map (
I => SSeg_count240hz_16_DYMUX_2103,
CE => VCC,
CLK => SSeg_count240hz_16_CLKINV_2093,
SET => GND,
RST => GND,
O => SSeg_count240hz(16)
);
SSeg_Mmux_hexnum_mux0001845 : X_LUT4
generic map(
INIT => X"FEFA",
LOC => "SLICE_X67Y26"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux000186_0,
ADR1 => Load_Store_Unit_reg(3),
ADR2 => SSeg_Mmux_hexnum_mux0001834_1814,
ADR3 => N31,
O => SSeg_Mmux_hexnum_mux0001845_2782
);
SSeg_Mmux_hexnum_mux00014256 : X_LUT4
generic map(
INIT => X"EAC0",
LOC => "SLICE_X66Y20"
)
port map (
ADR0 => N24,
ADR1 => N22,
ADR2 => UXCntl_Unit_VALA(3),
ADR3 => UXCntl_Unit_VALA(2),
O => SSeg_Mmux_hexnum_mux00014256_2806
);
SSeg_Mmux_hexnum_mux00016215_SW0 : X_LUT4
generic map(
INIT => X"47FF",
LOC => "SLICE_X66Y21"
)
port map (
ADR0 => UXCntl_Unit_VALA(3),
ADR1 => UXCntl_Unit_VALB(0),
ADR2 => UXCntl_Unit_VALA(4),
ADR3 => UXCntl_Unit_VALB(1),
O => N78
);
SSeg_Mmux_hexnum_mux0001878 : X_LUT4
generic map(
INIT => X"CC88",
LOC => "SLICE_X66Y22"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux0001860_0,
ADR1 => N23,
ADR2 => VCC,
ADR3 => SSeg_Mmux_hexnum_mux0001866_1823,
O => SSeg_Mmux_hexnum_mux0001878_2854
);
SSeg_Mmux_hexnum_mux00018240_SW0 : X_LUT4
generic map(
INIT => X"01CD",
LOC => "SLICE_X64Y24"
)
port map (
ADR0 => UXCntl_Unit_VALB(7),
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => UXCntl_Unit_VALA(7),
ADR3 => SSeg_Mmux_hexnum_mux00018194,
O => N80
);
SSeg_Mmux_hexnum_mux00012263 : X_LUT4
generic map(
INIT => X"FCFC",
LOC => "SLICE_X64Y29"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Mmux_hexnum_mux00012181_0,
ADR2 => SSeg_Mmux_hexnum_mux00012253_1829,
ADR3 => VCC,
O => SSeg_Mmux_hexnum_mux00012263_2902
);
SSeg_Mmux_hexnum_mux00012229 : X_LUT4
generic map(
INIT => X"FEEE",
LOC => "SLICE_X66Y24"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux00012205_0,
ADR1 => SSeg_Mmux_hexnum_mux00012226_0,
ADR2 => UXCntl_Unit_OPCODE(2),
ADR3 => SSeg_Mmux_hexnum_mux00012196_1833,
O => SSeg_Mmux_hexnum_mux00012229_2926
);
UXCntl_Unit_VALB_2 : X_LATCHE
generic map(
LOC => "SLICE_X64Y22",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_3_DYMUX_2372,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_2_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(2)
);
UXCntl_Unit_VALB_3 : X_LATCHE
generic map(
LOC => "SLICE_X64Y22",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_3_DXMUX_2377,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_3_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(3)
);
UXCntl_Unit_VALA_6 : X_LATCHE
generic map(
LOC => "SLICE_X65Y18",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_7_DYMUX_2388,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_6_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(6)
);
UXCntl_Unit_VALA_7 : X_LATCHE
generic map(
LOC => "SLICE_X65Y18",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_7_DXMUX_2393,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_7_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(7)
);
UXCntl_Unit_VALB_4 : X_LATCHE
generic map(
LOC => "SLICE_X64Y20",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_5_DYMUX_2404,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_4_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(4)
);
UXCntl_Unit_VALB_5 : X_LATCHE
generic map(
LOC => "SLICE_X64Y20",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_5_DXMUX_2409,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_5_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(5)
);
UXCntl_Unit_VALB_6 : X_LATCHE
generic map(
LOC => "SLICE_X65Y21",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_7_DYMUX_2420,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_6_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(6)
);
UXCntl_Unit_VALB_7 : X_LATCHE
generic map(
LOC => "SLICE_X65Y21",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_7_DXMUX_2425,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_7_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(7)
);
Load_Store_Unit_w_en_cmp_eq00001 : X_LUT4
generic map(
INIT => X"1000",
LOC => "SLICE_X64Y30"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(0),
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => UXCntl_Unit_OPCODE(3),
ADR3 => UXCntl_Unit_OPCODE(1),
O => Load_Store_Unit_w_en
);
SSeg_Mrom_segnum11 : X_LUT4
generic map(
INIT => X"4086",
LOC => "SLICE_X67Y48"
)
port map (
ADR0 => SSeg_hexnum(2),
ADR1 => SSeg_hexnum(0),
ADR2 => SSeg_hexnum(3),
ADR3 => SSeg_hexnum(1),
O => SEG_0_OBUF_2474
);
BTN_2_OUTPUT_not00011 : X_LUT4
generic map(
INIT => X"C030",
LOC => "SLICE_X64Y68"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_D_STATE(1),
ADR2 => BTN_2_Count(20),
ADR3 => BTN_2_D_STATE(0),
O => BTN_2_OUTPUT_not0001
);
UXCntl_Unit_OPCODE_0 : X_LATCHE
generic map(
LOC => "SLICE_X64Y39",
INIT => '0'
)
port map (
I => UXCntl_Unit_OPCODE_1_DYMUX_2508,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_OPCODE_0_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_OPCODE(0)
);
UXCntl_Unit_OPCODE_1 : X_LATCHE
generic map(
LOC => "SLICE_X64Y39",
INIT => '0'
)
port map (
I => UXCntl_Unit_OPCODE_1_DXMUX_2513,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_OPCODE_1_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_OPCODE(1)
);
UXCntl_Unit_OPCODE_2 : X_LATCHE
generic map(
LOC => "SLICE_X65Y36",
INIT => '0'
)
port map (
I => UXCntl_Unit_OPCODE_3_DYMUX_2524,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_OPCODE_2_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_OPCODE(2)
);
UXCntl_Unit_OPCODE_3 : X_LATCHE
generic map(
LOC => "SLICE_X65Y36",
INIT => '0'
)
port map (
I => UXCntl_Unit_OPCODE_3_DXMUX_2529,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_OPCODE_3_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_OPCODE(3)
);
SSeg_Mmux_hexnum_mux00014201 : X_LUT4
generic map(
INIT => X"F800",
LOC => "SLICE_X66Y30"
)
port map (
ADR0 => N28,
ADR1 => UXCntl_Unit_VALB(5),
ADR2 => N21,
ADR3 => UXCntl_Unit_VALA(5),
O => SSeg_Mmux_hexnum_mux00014201_2554
);
SSeg_Mmux_hexnum_mux0001422 : X_LUT4
generic map(
INIT => X"3232",
LOC => "SLICE_X66Y36"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => UXCntl_Unit_OPCODE(2),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => VCC,
O => SSeg_Mmux_hexnum_mux0001422_2578
);
SSeg_Mmux_hexnum_mux0001476 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X67Y30"
)
port map (
ADR0 => UXCntl_Unit_VALB(2),
ADR1 => UXCntl_Unit_VALA(2),
ADR2 => UXCntl_Unit_VALA(6),
ADR3 => VCC,
O => SSeg_Mmux_hexnum_mux0001476_2602
);
SSeg_Mmux_hexnum_mux00016157 : X_LUT4
generic map(
INIT => X"F800",
LOC => "SLICE_X66Y26"
)
port map (
ADR0 => N28,
ADR1 => UXCntl_Unit_VALB(6),
ADR2 => N21,
ADR3 => UXCntl_Unit_VALA(6),
O => SSeg_Mmux_hexnum_mux00016157_2626
);
SSeg_count240hz_0 : X_FF
generic map(
LOC => "SLICE_X35Y15",
INIT => '0'
)
port map (
I => SSeg_count240hz_1_DYMUX_2124,
CE => VCC,
CLK => SSeg_count240hz_1_CLKINV_2114,
SET => GND,
RST => GND,
O => SSeg_count240hz(0)
);
SSeg_Mcount_count240hz_eqn_17 : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X35Y15"
)
port map (
ADR0 => SSeg_Result(1),
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_1
);
SSeg_count240hz_1 : X_FF
generic map(
LOC => "SLICE_X35Y15",
INIT => '0'
)
port map (
I => SSeg_count240hz_1_DXMUX_2137,
CE => VCC,
CLK => SSeg_count240hz_1_CLKINV_2114,
SET => GND,
RST => GND,
O => SSeg_count240hz(1)
);
SSeg_count240hz_2 : X_FF
generic map(
LOC => "SLICE_X35Y14",
INIT => '0'
)
port map (
I => SSeg_count240hz_3_DYMUX_2158,
CE => VCC,
CLK => SSeg_count240hz_3_CLKINV_2148,
SET => GND,
RST => GND,
O => SSeg_count240hz(2)
);
SSeg_Mcount_count240hz_eqn_31 : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X35Y14"
)
port map (
ADR0 => SSeg_Result(3),
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_3
);
SSeg_count240hz_3 : X_FF
generic map(
LOC => "SLICE_X35Y14",
INIT => '0'
)
port map (
I => SSeg_count240hz_3_DXMUX_2171,
CE => VCC,
CLK => SSeg_count240hz_3_CLKINV_2148,
SET => GND,
RST => GND,
O => SSeg_count240hz(3)
);
SSeg_count240hz_4 : X_FF
generic map(
LOC => "SLICE_X34Y19",
INIT => '0'
)
port map (
I => SSeg_count240hz_5_DYMUX_2192,
CE => VCC,
CLK => SSeg_count240hz_5_CLKINV_2182,
SET => GND,
RST => GND,
O => SSeg_count240hz(4)
);
SSeg_Mcount_count240hz_eqn_51 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X34Y19"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz_cmp_eq0000,
ADR2 => VCC,
ADR3 => SSeg_Result(5),
O => SSeg_Mcount_count240hz_eqn_5
);
SSeg_count240hz_5 : X_FF
generic map(
LOC => "SLICE_X34Y19",
INIT => '0'
)
port map (
I => SSeg_count240hz_5_DXMUX_2205,
CE => VCC,
CLK => SSeg_count240hz_5_CLKINV_2182,
SET => GND,
RST => GND,
O => SSeg_count240hz(5)
);
SSeg_count240hz_6 : X_FF
generic map(
LOC => "SLICE_X35Y17",
INIT => '0'
)
port map (
I => SSeg_count240hz_7_DYMUX_2226,
CE => VCC,
CLK => SSeg_count240hz_7_CLKINV_2216,
SET => GND,
RST => GND,
O => SSeg_count240hz(6)
);
SSeg_Mcount_count240hz_eqn_71 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X35Y17"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(7),
ADR2 => VCC,
ADR3 => SSeg_count240hz_cmp_eq0000,
O => SSeg_Mcount_count240hz_eqn_7
);
SSeg_count240hz_7 : X_FF
generic map(
LOC => "SLICE_X35Y17",
INIT => '0'
)
port map (
I => SSeg_count240hz_7_DXMUX_2239,
CE => VCC,
CLK => SSeg_count240hz_7_CLKINV_2216,
SET => GND,
RST => GND,
O => SSeg_count240hz(7)
);
SSeg_count240hz_8 : X_FF
generic map(
LOC => "SLICE_X32Y19",
INIT => '0'
)
port map (
I => SSeg_count240hz_9_DYMUX_2260,
CE => VCC,
CLK => SSeg_count240hz_9_CLKINV_2250,
SET => GND,
RST => GND,
O => SSeg_count240hz(8)
);
SSeg_Mcount_count240hz_eqn_91 : X_LUT4
generic map(
INIT => X"0C0C",
LOC => "SLICE_X32Y19"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(9),
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_9
);
SSeg_count240hz_9 : X_FF
generic map(
LOC => "SLICE_X32Y19",
INIT => '0'
)
port map (
I => SSeg_count240hz_9_DXMUX_2273,
CE => VCC,
CLK => SSeg_count240hz_9_CLKINV_2250,
SET => GND,
RST => GND,
O => SSeg_count240hz(9)
);
ALU_Mux_ALU_OUT_5_131 : X_LUT4
generic map(
INIT => X"000C",
LOC => "SLICE_X67Y23"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => UXCntl_Unit_VALB(0),
O => N27
);
UXCntl_Unit_VALA_0 : X_LATCHE
generic map(
LOC => "SLICE_X65Y39",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_1_DYMUX_2308,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_0_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(0)
);
UXCntl_Unit_VALA_1 : X_LATCHE
generic map(
LOC => "SLICE_X65Y39",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_1_DXMUX_2313,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_1_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(1)
);
UXCntl_Unit_VALA_2 : X_LATCHE
generic map(
LOC => "SLICE_X65Y23",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_3_DYMUX_2324,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_2_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(2)
);
UXCntl_Unit_VALA_3 : X_LATCHE
generic map(
LOC => "SLICE_X65Y23",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_3_DXMUX_2329,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_3_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(3)
);
UXCntl_Unit_VALB_0 : X_LATCHE
generic map(
LOC => "SLICE_X65Y38",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_1_DYMUX_2340,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_0_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(0)
);
UXCntl_Unit_VALB_1 : X_LATCHE
generic map(
LOC => "SLICE_X65Y38",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALB_1_DXMUX_2345,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALB_1_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALB(1)
);
UXCntl_Unit_VALA_4 : X_LATCHE
generic map(
LOC => "SLICE_X65Y19",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_5_DYMUX_2356,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_4_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(4)
);
UXCntl_Unit_VALA_5 : X_LATCHE
generic map(
LOC => "SLICE_X65Y19",
INIT => '0'
)
port map (
I => UXCntl_Unit_VALA_5_DXMUX_2361,
GE => VCC,
CLK => NlwInverterSignal_UXCntl_Unit_VALA_5_CLK,
SET => GND,
RST => GND,
O => UXCntl_Unit_VALA(5)
);
UXCntl_Unit_OPCODE_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0002",
LOC => "SLICE_X54Y52"
)
port map (
ADR0 => BTN_1_OUTPUT_1792,
ADR1 => BTN_3_OUTPUT_1790,
ADR2 => BTN_2_OUTPUT_1791,
ADR3 => BTN_0_OUTPUT_1789,
O => UXCntl_Unit_OPCODE_cmp_eq0000
);
SSeg_clk240hz : X_FF
generic map(
LOC => "SLICE_X34Y22",
INIT => '0'
)
port map (
I => SSeg_clk240hz_DYMUX_2660,
CE => SSeg_clk240hz_CEINV_2657,
CLK => SSeg_clk240hz_CLKINV_2658,
SET => GND,
RST => GND,
O => SSeg_clk240hz_1793
);
SSeg_Mmux_hexnum_mux0001222 : X_LUT4
generic map(
INIT => X"FEFA",
LOC => "SLICE_X66Y37"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux000126_0,
ADR1 => N31,
ADR2 => SSeg_Mmux_hexnum_mux0001219_1796,
ADR3 => Load_Store_Unit_reg(0),
O => SSeg_Mmux_hexnum_mux0001222_2686
);
SSeg_Mmux_hexnum_mux0001285_SW0 : X_LUT4
generic map(
INIT => X"0C00",
LOC => "SLICE_X67Y34"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => UXCntl_Unit_VALB(2),
ADR3 => UXCntl_Unit_VALA(3),
O => N82
);
SSeg_Mmux_hexnum_mux00012111 : X_LUT4
generic map(
INIT => X"ECA0",
LOC => "SLICE_X67Y35"
)
port map (
ADR0 => N30,
ADR1 => N23,
ADR2 => arith(0),
ADR3 => SSeg_Mmux_hexnum_mux0001285_1805,
O => SSeg_Mmux_hexnum_mux00012111_2734
);
SSeg_Mmux_hexnum_mux0001655 : X_LUT4
generic map(
INIT => X"FEFC",
LOC => "SLICE_X64Y31"
)
port map (
ADR0 => Load_Store_Unit_reg(2),
ADR1 => SSeg_Mmux_hexnum_mux000166_0,
ADR2 => SSeg_Mmux_hexnum_mux0001643_1810,
ADR3 => N31,
O => SSeg_Mmux_hexnum_mux0001655_2758
);
SSeg_Mmux_hexnum_mux00018143 : X_LUT4
generic map(
INIT => X"88C0",
LOC => "SLICE_X65Y24"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => UXCntl_Unit_VALA(5),
ADR3 => UXCntl_Unit_VALB(2),
O => SSeg_Mmux_hexnum_mux00018143_2950
);
SSeg_Mmux_hexnum_mux00016330_SW0 : X_LUT4
generic map(
INIT => X"FFEC",
LOC => "SLICE_X67Y27"
)
port map (
ADR0 => N30,
ADR1 => SSeg_Mmux_hexnum_mux0001655_0,
ADR2 => arith(2),
ADR3 => SSeg_Mmux_hexnum_mux00016107_1838,
O => N62
);
BTN_0_Count_and00001 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X66Y84"
)
port map (
ADR0 => VCC,
ADR1 => BTN_0_D_STATE(0),
ADR2 => VCC,
ADR3 => BTN_0_D_STATE(1),
O => BTN_0_Count_and0000
);
SSeg_Mmux_hexnum_mux00018120 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X66Y32"
)
port map (
ADR0 => VCC,
ADR1 => N31,
ADR2 => VCC,
ADR3 => Load_Store_Unit_reg(7),
O => SSeg_Mmux_hexnum_mux00018120_3022
);
SSeg_Mmux_hexnum_mux00016289 : X_LUT4
generic map(
INIT => X"EAC0",
LOC => "SLICE_X64Y28"
)
port map (
ADR0 => N26_0,
ADR1 => arith(6),
ADR2 => N30,
ADR3 => SSeg_Mmux_hexnum_mux00016263_1853,
O => SSeg_Mmux_hexnum_mux00016289_3046
);
ALU_Mux_ALU_OUT_0_71 : X_LUT4
generic map(
INIT => X"0808",
LOC => "SLICE_X64Y26"
)
port map (
ADR0 => UXCntl_Unit_OPCODE(1),
ADR1 => UXCntl_Unit_OPCODE(0),
ADR2 => UXCntl_Unit_OPCODE(3),
ADR3 => VCC,
O => N26
);
SSeg_Mmux_hexnum_mux00018252 : X_LUT4
generic map(
INIT => X"FAF8",
LOC => "SLICE_X64Y25"
)
port map (
ADR0 => UXCntl_Unit_VALA(7),
ADR1 => N21,
ADR2 => SSeg_Mmux_hexnum_mux00018240_1857,
ADR3 => SSeg_Mmux_hexnum_mux00018124_0,
O => SSeg_Mmux_hexnum_mux00018252_3094
);
BTN_1_Count_15 : X_SFF
generic map(
LOC => "SLICE_X67Y77",
INIT => '0'
)
port map (
I => BTN_1_Count_14_DYMUX_4153,
CE => BTN_1_Count_14_CEINVNOT,
CLK => BTN_1_Count_14_CLKINV_4131,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_14_SRINV_4132,
O => BTN_1_Count(15)
);
BTN_1_Count_14 : X_SFF
generic map(
LOC => "SLICE_X67Y77",
INIT => '0'
)
port map (
I => BTN_1_Count_14_DXMUX_4171,
CE => BTN_1_Count_14_CEINVNOT,
CLK => BTN_1_Count_14_CLKINV_4131,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_14_SRINV_4132,
O => BTN_1_Count(14)
);
BTN_1_Count_17 : X_SFF
generic map(
LOC => "SLICE_X67Y78",
INIT => '0'
)
port map (
I => BTN_1_Count_16_DYMUX_4209,
CE => BTN_1_Count_16_CEINVNOT,
CLK => BTN_1_Count_16_CLKINV_4187,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_16_SRINV_4188,
O => BTN_1_Count(17)
);
BTN_1_Count_16 : X_SFF
generic map(
LOC => "SLICE_X67Y78",
INIT => '0'
)
port map (
I => BTN_1_Count_16_DXMUX_4227,
CE => BTN_1_Count_16_CEINVNOT,
CLK => BTN_1_Count_16_CLKINV_4187,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_16_SRINV_4188,
O => BTN_1_Count(16)
);
BTN_3_OUTPUT_not00011 : X_LUT4
generic map(
INIT => X"A00A",
LOC => "SLICE_X53Y60"
)
port map (
ADR0 => BTN_3_Count(20),
ADR1 => VCC,
ADR2 => BTN_3_D_STATE(0),
ADR3 => BTN_3_D_STATE(1),
O => BTN_3_OUTPUT_not0001
);
SSeg_DP_OUT : X_FF
generic map(
LOC => "SLICE_X66Y39",
INIT => '1'
)
port map (
I => SSeg_DP_OUT_DYMUX_3126,
CE => VCC,
CLK => SSeg_DP_OUT_CLKINV_3124,
SET => GND,
RST => GND,
O => SSeg_DP_OUT_1865
);
SSeg_Mmux_hexnum_mux0001643_SW0 : X_LUT4
generic map(
INIT => X"FA11",
LOC => "SLICE_X65Y30"
)
port map (
ADR0 => UXCntl_Unit_VALB(2),
ADR1 => UXCntl_Unit_VALA(2),
ADR2 => N92,
ADR3 => UXCntl_Unit_OPCODE(2),
O => N88
);
Load_Store_Unit_reg_0 : X_FF
generic map(
LOC => "SLICE_X67Y36",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_1_DYMUX_3163,
CE => Load_Store_Unit_reg_1_CEINV_3160,
CLK => Load_Store_Unit_reg_1_CLKINV_3161,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(0)
);
Load_Store_Unit_reg_1 : X_FF
generic map(
LOC => "SLICE_X67Y36",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_1_DXMUX_3169,
CE => Load_Store_Unit_reg_1_CEINV_3160,
CLK => Load_Store_Unit_reg_1_CLKINV_3161,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(1)
);
Load_Store_Unit_reg_2 : X_FF
generic map(
LOC => "SLICE_X65Y31",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_3_DYMUX_3183,
CE => Load_Store_Unit_reg_3_CEINV_3180,
CLK => Load_Store_Unit_reg_3_CLKINV_3181,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(2)
);
Load_Store_Unit_reg_3 : X_FF
generic map(
LOC => "SLICE_X65Y31",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_3_DXMUX_3189,
CE => Load_Store_Unit_reg_3_CEINV_3180,
CLK => Load_Store_Unit_reg_3_CLKINV_3181,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(3)
);
Load_Store_Unit_reg_4 : X_FF
generic map(
LOC => "SLICE_X64Y32",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_5_DYMUX_3203,
CE => Load_Store_Unit_reg_5_CEINV_3200,
CLK => Load_Store_Unit_reg_5_CLKINV_3201,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(4)
);
BTN_1_OUTPUT_not00011 : X_LUT4
generic map(
INIT => X"8844",
LOC => "SLICE_X65Y80"
)
port map (
ADR0 => BTN_1_D_STATE(0),
ADR1 => BTN_1_Count(20),
ADR2 => VCC,
ADR3 => BTN_1_D_STATE(1),
O => BTN_1_OUTPUT_not0001
);
SSeg_Mmux_hexnum_mux00012226 : X_LUT4
generic map(
INIT => X"B080",
LOC => "SLICE_X66Y25"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => UXCntl_Unit_VALB(1),
ADR2 => N25,
ADR3 => UXCntl_Unit_VALA(3),
O => SSeg_Mmux_hexnum_mux00012226_3512
);
SSeg_Mmux_hexnum_mux0001825 : X_LUT4
generic map(
INIT => X"A000",
LOC => "SLICE_X66Y23"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => VCC,
ADR2 => N22,
ADR3 => UXCntl_Unit_OPCODE(2),
O => SSeg_Mmux_hexnum_mux0001825_3536
);
SSeg_Mmux_hexnum_mux0001669 : X_LUT4
generic map(
INIT => X"F888",
LOC => "SLICE_X67Y21"
)
port map (
ADR0 => N22,
ADR1 => UXCntl_Unit_VALA(4),
ADR2 => UXCntl_Unit_VALA(5),
ADR3 => N24,
O => SSeg_Mmux_hexnum_mux0001669_3560
);
SSeg_Mmux_hexnum_mux00018187 : X_LUT4
generic map(
INIT => X"D1C0",
LOC => "SLICE_X65Y22"
)
port map (
ADR0 => UXCntl_Unit_VALB(1),
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => N12,
ADR3 => UXCntl_Unit_VALA(6),
O => SSeg_Mmux_hexnum_mux00018187_3584
);
SSeg_Mmux_hexnum_mux00014135 : X_LUT4
generic map(
INIT => X"ECA0",
LOC => "SLICE_X66Y29"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux00014107,
ADR1 => N30,
ADR2 => N23,
ADR3 => arith(1),
O => SSeg_Mmux_hexnum_mux00014135_3608
);
Load_Store_Unit_reg_5 : X_FF
generic map(
LOC => "SLICE_X64Y32",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_5_DXMUX_3209,
CE => Load_Store_Unit_reg_5_CEINV_3200,
CLK => Load_Store_Unit_reg_5_CLKINV_3201,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(5)
);
Load_Store_Unit_reg_6 : X_FF
generic map(
LOC => "SLICE_X67Y32",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_7_DYMUX_3223,
CE => Load_Store_Unit_reg_7_CEINV_3220,
CLK => Load_Store_Unit_reg_7_CLKINV_3221,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(6)
);
Load_Store_Unit_reg_7 : X_FF
generic map(
LOC => "SLICE_X67Y32",
INIT => '0'
)
port map (
I => Load_Store_Unit_reg_7_DXMUX_3229,
CE => Load_Store_Unit_reg_7_CEINV_3220,
CLK => Load_Store_Unit_reg_7_CLKINV_3221,
SET => GND,
RST => GND,
O => Load_Store_Unit_reg(7)
);
BTN_0_D_STATE_0 : X_FF
generic map(
LOC => "SLICE_X67Y85",
INIT => '0'
)
port map (
I => BTN_0_D_STATE_1_DYMUX_3241,
CE => VCC,
CLK => BTN_0_D_STATE_1_CLKINV_3239,
SET => GND,
RST => GND,
O => BTN_0_D_STATE(0)
);
BTN_0_D_STATE_1 : X_FF
generic map(
LOC => "SLICE_X67Y85",
INIT => '0'
)
port map (
I => BTN_0_D_STATE_1_DXMUX_3246,
CE => VCC,
CLK => BTN_0_D_STATE_1_CLKINV_3239,
SET => GND,
RST => GND,
O => BTN_0_D_STATE(1)
);
SSeg_Mmux_hexnum_mux00014147 : X_LUT4
generic map(
INIT => X"FEF0",
LOC => "SLICE_X67Y37"
)
port map (
ADR0 => SSeg_Mmux_hexnum_mux0001417_0,
ADR1 => SSeg_Mmux_hexnum_mux0001422_0,
ADR2 => N74,
ADR3 => N26_0,
O => SSeg_Mmux_hexnum_mux00014147_3271
);
SSeg_Mmux_hexnum_mux00014346 : X_LUT4
generic map(
INIT => X"FFF8",
LOC => "SLICE_X66Y27"
)
port map (
ADR0 => Load_Store_Unit_reg(5),
ADR1 => N31,
ADR2 => N76,
ADR3 => SSeg_Mmux_hexnum_mux00014201_0,
O => SSeg_Mmux_hexnum_mux00014346_3295
);
SSeg_Mrom_segnum31 : X_LUT4
generic map(
INIT => X"8924",
LOC => "SLICE_X67Y63"
)
port map (
ADR0 => SSeg_hexnum(1),
ADR1 => SSeg_hexnum(0),
ADR2 => SSeg_hexnum(3),
ADR3 => SSeg_hexnum(2),
O => SEG_3_OBUF_3319
);
SSeg_Mrom_segnum51 : X_LUT4
generic map(
INIT => X"0D84",
LOC => "SLICE_X67Y52"
)
port map (
ADR0 => SSeg_hexnum(2),
ADR1 => SSeg_hexnum(0),
ADR2 => SSeg_hexnum(3),
ADR3 => SSeg_hexnum(1),
O => SEG_5_OBUF_3343
);
BTN_1_D_STATE_0 : X_FF
generic map(
LOC => "SLICE_X64Y80",
INIT => '0'
)
port map (
I => BTN_1_D_STATE_1_DYMUX_3365,
CE => VCC,
CLK => BTN_1_D_STATE_1_CLKINV_3363,
SET => GND,
RST => GND,
O => BTN_1_D_STATE(0)
);
BTN_1_D_STATE_1 : X_FF
generic map(
LOC => "SLICE_X64Y80",
INIT => '0'
)
port map (
I => BTN_1_D_STATE_1_DXMUX_3370,
CE => VCC,
CLK => BTN_1_D_STATE_1_CLKINV_3363,
SET => GND,
RST => GND,
O => BTN_1_D_STATE(1)
);
BTN_2_D_STATE_0 : X_FF
generic map(
LOC => "SLICE_X64Y69",
INIT => '0'
)
port map (
I => BTN_2_D_STATE_1_DYMUX_3393,
CE => VCC,
CLK => BTN_2_D_STATE_1_CLKINV_3391,
SET => GND,
RST => GND,
O => BTN_2_D_STATE(0)
);
BTN_2_D_STATE_1 : X_FF
generic map(
LOC => "SLICE_X64Y69",
INIT => '0'
)
port map (
I => BTN_2_D_STATE_1_DXMUX_3398,
CE => VCC,
CLK => BTN_2_D_STATE_1_CLKINV_3391,
SET => GND,
RST => GND,
O => BTN_2_D_STATE(1)
);
BTN_3_D_STATE_0 : X_FF
generic map(
LOC => "SLICE_X52Y60",
INIT => '0'
)
port map (
I => BTN_3_D_STATE_1_DYMUX_3409,
CE => VCC,
CLK => BTN_3_D_STATE_1_CLKINV_3407,
SET => GND,
RST => GND,
O => BTN_3_D_STATE(0)
);
BTN_3_D_STATE_1 : X_FF
generic map(
LOC => "SLICE_X52Y60",
INIT => '0'
)
port map (
I => BTN_3_D_STATE_1_DXMUX_3414,
CE => VCC,
CLK => BTN_3_D_STATE_1_CLKINV_3407,
SET => GND,
RST => GND,
O => BTN_3_D_STATE(1)
);
SSeg_pos_1 : X_FF
generic map(
LOC => "SLICE_X67Y39",
INIT => '0'
)
port map (
I => SSeg_pos_0_DYMUX_3434,
CE => VCC,
CLK => SSeg_pos_0_CLKINV_3424,
SET => GND,
RST => GND,
O => SSeg_pos(1)
);
SSeg_pos_0 : X_FF
generic map(
LOC => "SLICE_X67Y39",
INIT => '0'
)
port map (
I => SSeg_pos_0_DXMUX_3439,
CE => VCC,
CLK => SSeg_pos_0_CLKINV_3424,
SET => GND,
RST => GND,
O => SSeg_pos(0)
);
SSeg_Mmux_hexnum_mux00012181 : X_LUT4
generic map(
INIT => X"FFEC",
LOC => "SLICE_X65Y32"
)
port map (
ADR0 => Load_Store_Unit_reg(4),
ADR1 => SSeg_Mmux_hexnum_mux00012171,
ADR2 => N31,
ADR3 => SSeg_Mmux_hexnum_mux00012151_0,
O => SSeg_Mmux_hexnum_mux00012181_3464
);
SSeg_Mmux_hexnum_mux00012151 : X_LUT4
generic map(
INIT => X"C888",
LOC => "SLICE_X64Y27"
)
port map (
ADR0 => N21,
ADR1 => UXCntl_Unit_VALA(4),
ADR2 => N28,
ADR3 => UXCntl_Unit_VALB(4),
O => SSeg_Mmux_hexnum_mux00012151_3632
);
SSeg_Mmux_hexnum_mux00014346_SW0_SW0 : X_LUT4
generic map(
INIT => X"ECA0",
LOC => "SLICE_X67Y33"
)
port map (
ADR0 => arith(5),
ADR1 => SSeg_Mmux_hexnum_mux00014312,
ADR2 => N30,
ADR3 => N26_0,
O => N90
);
SSeg_Mmux_hexnum_mux0001278 : X_LUT4
generic map(
INIT => X"CE02",
LOC => "SLICE_X66Y34"
)
port map (
ADR0 => UXCntl_Unit_VALA(1),
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => UXCntl_Unit_VALB(1),
ADR3 => N11,
O => SSeg_Mmux_hexnum_mux0001278_3680
);
BTN_0_OUTPUT : X_FF
generic map(
LOC => "SLICE_X66Y85",
INIT => '0'
)
port map (
I => BTN_0_OUTPUT_DYMUX_3690,
CE => BTN_0_OUTPUT_CEINV_3687,
CLK => BTN_0_OUTPUT_CLKINV_3688,
SET => GND,
RST => GND,
O => BTN_0_OUTPUT_1789
);
BTN_1_Count_1 : X_SFF
generic map(
LOC => "SLICE_X67Y70",
INIT => '0'
)
port map (
I => BTN_1_Count_0_DYMUX_3722,
CE => BTN_1_Count_0_CEINVNOT,
CLK => BTN_1_Count_0_CLKINV_3705,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_0_SRINV_3706,
O => BTN_1_Count(1)
);
BTN_1_Mcount_Count_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X67Y70"
)
port map (
ADR0 => BTN_1_Count(0),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Mcount_Count_lut(0)
);
BTN_1_Count_0 : X_SFF
generic map(
LOC => "SLICE_X67Y70",
INIT => '0'
)
port map (
I => BTN_1_Count_0_DXMUX_3743,
CE => BTN_1_Count_0_CEINVNOT,
CLK => BTN_1_Count_0_CLKINV_3705,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_0_SRINV_3706,
O => BTN_1_Count(0)
);
BTN_1_Count_4 : X_SFF
generic map(
LOC => "SLICE_X67Y72",
INIT => '0'
)
port map (
I => BTN_1_Count_4_DXMUX_3879,
CE => BTN_1_Count_4_CEINVNOT,
CLK => BTN_1_Count_4_CLKINV_3839,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_4_SRINV_3840,
O => BTN_1_Count(4)
);
BTN_3_OUTPUT : X_FF
generic map(
LOC => "SLICE_X52Y61",
INIT => '0'
)
port map (
I => BTN_3_OUTPUT_DYMUX_3892,
CE => BTN_3_OUTPUT_CEINV_3889,
CLK => BTN_3_OUTPUT_CLKINV_3890,
SET => GND,
RST => GND,
O => BTN_3_OUTPUT_1790
);
BTN_1_Count_7 : X_SFF
generic map(
LOC => "SLICE_X67Y73",
INIT => '0'
)
port map (
I => BTN_1_Count_6_DYMUX_3929,
CE => BTN_1_Count_6_CEINVNOT,
CLK => BTN_1_Count_6_CLKINV_3907,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_6_SRINV_3908,
O => BTN_1_Count(7)
);
BTN_1_Count_6 : X_SFF
generic map(
LOC => "SLICE_X67Y73",
INIT => '0'
)
port map (
I => BTN_1_Count_6_DXMUX_3947,
CE => BTN_1_Count_6_CEINVNOT,
CLK => BTN_1_Count_6_CLKINV_3907,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_6_SRINV_3908,
O => BTN_1_Count(6)
);
BTN_1_Count_9 : X_SFF
generic map(
LOC => "SLICE_X67Y74",
INIT => '0'
)
port map (
I => BTN_1_Count_8_DYMUX_3985,
CE => BTN_1_Count_8_CEINVNOT,
CLK => BTN_1_Count_8_CLKINV_3963,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_8_SRINV_3964,
O => BTN_1_Count(9)
);
BTN_1_OUTPUT : X_FF
generic map(
LOC => "SLICE_X64Y81",
INIT => '0'
)
port map (
I => BTN_1_OUTPUT_DYMUX_3756,
CE => BTN_1_OUTPUT_CEINV_3753,
CLK => BTN_1_OUTPUT_CLKINV_3754,
SET => GND,
RST => GND,
O => BTN_1_OUTPUT_1792
);
BTN_1_Count_3 : X_SFF
generic map(
LOC => "SLICE_X67Y71",
INIT => '0'
)
port map (
I => BTN_1_Count_2_DYMUX_3793,
CE => BTN_1_Count_2_CEINVNOT,
CLK => BTN_1_Count_2_CLKINV_3771,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_2_SRINV_3772,
O => BTN_1_Count(3)
);
BTN_1_Count_2 : X_SFF
generic map(
LOC => "SLICE_X67Y71",
INIT => '0'
)
port map (
I => BTN_1_Count_2_DXMUX_3811,
CE => BTN_1_Count_2_CEINVNOT,
CLK => BTN_1_Count_2_CLKINV_3771,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_2_SRINV_3772,
O => BTN_1_Count(2)
);
BTN_2_OUTPUT : X_FF
generic map(
LOC => "SLICE_X64Y66",
INIT => '0'
)
port map (
I => BTN_2_OUTPUT_DYMUX_3824,
CE => BTN_2_OUTPUT_CEINV_3821,
CLK => BTN_2_OUTPUT_CLKINV_3822,
SET => GND,
RST => GND,
O => BTN_2_OUTPUT_1791
);
BTN_1_Count_5 : X_SFF
generic map(
LOC => "SLICE_X67Y72",
INIT => '0'
)
port map (
I => BTN_1_Count_4_DYMUX_3861,
CE => BTN_1_Count_4_CEINVNOT,
CLK => BTN_1_Count_4_CLKINV_3839,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_4_SRINV_3840,
O => BTN_1_Count(5)
);
BTN_3_Count_11 : X_SFF
generic map(
LOC => "SLICE_X53Y66",
INIT => '0'
)
port map (
I => BTN_3_Count_10_DYMUX_6258,
CE => BTN_3_Count_10_CEINVNOT,
CLK => BTN_3_Count_10_CLKINV_6236,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_10_SRINV_6237,
O => BTN_3_Count(11)
);
BTN_3_Count_10 : X_SFF
generic map(
LOC => "SLICE_X53Y66",
INIT => '0'
)
port map (
I => BTN_3_Count_10_DXMUX_6276,
CE => BTN_3_Count_10_CEINVNOT,
CLK => BTN_3_Count_10_CLKINV_6236,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_10_SRINV_6237,
O => BTN_3_Count(10)
);
BTN_3_Count_13 : X_SFF
generic map(
LOC => "SLICE_X53Y67",
INIT => '0'
)
port map (
I => BTN_3_Count_12_DYMUX_6314,
CE => BTN_3_Count_12_CEINVNOT,
CLK => BTN_3_Count_12_CLKINV_6292,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_12_SRINV_6293,
O => BTN_3_Count(13)
);
BTN_3_Count_12 : X_SFF
generic map(
LOC => "SLICE_X53Y67",
INIT => '0'
)
port map (
I => BTN_3_Count_12_DXMUX_6332,
CE => BTN_3_Count_12_CEINVNOT,
CLK => BTN_3_Count_12_CLKINV_6292,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_12_SRINV_6293,
O => BTN_3_Count(12)
);
BTN_1_Count_8 : X_SFF
generic map(
LOC => "SLICE_X67Y74",
INIT => '0'
)
port map (
I => BTN_1_Count_8_DXMUX_4003,
CE => BTN_1_Count_8_CEINVNOT,
CLK => BTN_1_Count_8_CLKINV_3963,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_8_SRINV_3964,
O => BTN_1_Count(8)
);
BTN_1_Count_11 : X_SFF
generic map(
LOC => "SLICE_X67Y75",
INIT => '0'
)
port map (
I => BTN_1_Count_10_DYMUX_4041,
CE => BTN_1_Count_10_CEINVNOT,
CLK => BTN_1_Count_10_CLKINV_4019,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_10_SRINV_4020,
O => BTN_1_Count(11)
);
BTN_1_Count_10 : X_SFF
generic map(
LOC => "SLICE_X67Y75",
INIT => '0'
)
port map (
I => BTN_1_Count_10_DXMUX_4059,
CE => BTN_1_Count_10_CEINVNOT,
CLK => BTN_1_Count_10_CLKINV_4019,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_10_SRINV_4020,
O => BTN_1_Count(10)
);
BTN_1_Count_13 : X_SFF
generic map(
LOC => "SLICE_X67Y76",
INIT => '0'
)
port map (
I => BTN_1_Count_12_DYMUX_4097,
CE => BTN_1_Count_12_CEINVNOT,
CLK => BTN_1_Count_12_CLKINV_4075,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_12_SRINV_4076,
O => BTN_1_Count(13)
);
BTN_1_Count_12 : X_SFF
generic map(
LOC => "SLICE_X67Y76",
INIT => '0'
)
port map (
I => BTN_1_Count_12_DXMUX_4115,
CE => BTN_1_Count_12_CEINVNOT,
CLK => BTN_1_Count_12_CLKINV_4075,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_12_SRINV_4076,
O => BTN_1_Count(12)
);
BTN_1_Count_19 : X_SFF
generic map(
LOC => "SLICE_X67Y79",
INIT => '0'
)
port map (
I => BTN_1_Count_18_DYMUX_4265,
CE => BTN_1_Count_18_CEINVNOT,
CLK => BTN_1_Count_18_CLKINV_4243,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_18_SRINV_4244,
O => BTN_1_Count(19)
);
BTN_1_Count_18 : X_SFF
generic map(
LOC => "SLICE_X67Y79",
INIT => '0'
)
port map (
I => BTN_1_Count_18_DXMUX_4283,
CE => BTN_1_Count_18_CEINVNOT,
CLK => BTN_1_Count_18_CLKINV_4243,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_18_SRINV_4244,
O => BTN_1_Count(18)
);
BTN_1_Count_20_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X67Y80"
)
port map (
ADR0 => BTN_1_Count(20),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_20_rt_4305
);
BTN_1_Count_20 : X_SFF
generic map(
LOC => "SLICE_X67Y80",
INIT => '0'
)
port map (
I => BTN_1_Count_20_DXMUX_4310,
CE => BTN_1_Count_20_CEINVNOT,
CLK => BTN_1_Count_20_CLKINV_4296,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_1_Count_20_SRINV_4297,
O => BTN_1_Count(20)
);
Arith_Unit_Maddsub_arith_lut_0_Q : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X65Y26"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => UXCntl_Unit_VALA(0),
ADR2 => VCC,
ADR3 => Arith_Unit_arith_cmp_eq0000_0,
O => Arith_Unit_Maddsub_arith_lut(0)
);
Arith_Unit_Maddsub_arith_lut_2_Q : X_LUT4
generic map(
INIT => X"9966",
LOC => "SLICE_X65Y27"
)
port map (
ADR0 => UXCntl_Unit_VALA(2),
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => VCC,
ADR3 => Arith_Unit_arith_cmp_eq0000_0,
O => Arith_Unit_Maddsub_arith_lut(2)
);
Arith_Unit_Maddsub_arith_lut_4_Q : X_LUT4
generic map(
INIT => X"9696",
LOC => "SLICE_X65Y28"
)
port map (
ADR0 => UXCntl_Unit_VALB(4),
ADR1 => UXCntl_Unit_VALA(4),
ADR2 => Arith_Unit_arith_cmp_eq0000_0,
ADR3 => VCC,
O => Arith_Unit_Maddsub_arith_lut(4)
);
Arith_Unit_Maddsub_arith_lut_6_Q : X_LUT4
generic map(
INIT => X"9696",
LOC => "SLICE_X65Y29"
)
port map (
ADR0 => UXCntl_Unit_VALA(6),
ADR1 => UXCntl_Unit_VALB(6),
ADR2 => Arith_Unit_arith_cmp_eq0000_0,
ADR3 => VCC,
O => Arith_Unit_Maddsub_arith_lut(6)
);
BTN_0_Count_1 : X_SFF
generic map(
LOC => "SLICE_X65Y81",
INIT => '0'
)
port map (
I => BTN_0_Count_0_DYMUX_4488,
CE => BTN_0_Count_0_CEINVNOT,
CLK => BTN_0_Count_0_CLKINV_4471,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_0_SRINV_4472,
O => BTN_0_Count(1)
);
BTN_0_Count_8 : X_SFF
generic map(
LOC => "SLICE_X65Y85",
INIT => '0'
)
port map (
I => BTN_0_Count_8_DXMUX_4733,
CE => BTN_0_Count_8_CEINVNOT,
CLK => BTN_0_Count_8_CLKINV_4693,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_8_SRINV_4694,
O => BTN_0_Count(8)
);
BTN_0_Count_11 : X_SFF
generic map(
LOC => "SLICE_X65Y86",
INIT => '0'
)
port map (
I => BTN_0_Count_10_DYMUX_4771,
CE => BTN_0_Count_10_CEINVNOT,
CLK => BTN_0_Count_10_CLKINV_4749,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_10_SRINV_4750,
O => BTN_0_Count(11)
);
BTN_0_Count_10 : X_SFF
generic map(
LOC => "SLICE_X65Y86",
INIT => '0'
)
port map (
I => BTN_0_Count_10_DXMUX_4789,
CE => BTN_0_Count_10_CEINVNOT,
CLK => BTN_0_Count_10_CLKINV_4749,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_10_SRINV_4750,
O => BTN_0_Count(10)
);
BTN_0_Count_13 : X_SFF
generic map(
LOC => "SLICE_X65Y87",
INIT => '0'
)
port map (
I => BTN_0_Count_12_DYMUX_4827,
CE => BTN_0_Count_12_CEINVNOT,
CLK => BTN_0_Count_12_CLKINV_4805,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_12_SRINV_4806,
O => BTN_0_Count(13)
);
BTN_0_Count_12 : X_SFF
generic map(
LOC => "SLICE_X65Y87",
INIT => '0'
)
port map (
I => BTN_0_Count_12_DXMUX_4845,
CE => BTN_0_Count_12_CEINVNOT,
CLK => BTN_0_Count_12_CLKINV_4805,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_12_SRINV_4806,
O => BTN_0_Count(12)
);
BTN_0_Count_4 : X_SFF
generic map(
LOC => "SLICE_X65Y83",
INIT => '0'
)
port map (
I => BTN_0_Count_4_DXMUX_4621,
CE => BTN_0_Count_4_CEINVNOT,
CLK => BTN_0_Count_4_CLKINV_4581,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_4_SRINV_4582,
O => BTN_0_Count(4)
);
BTN_0_Count_7 : X_SFF
generic map(
LOC => "SLICE_X65Y84",
INIT => '0'
)
port map (
I => BTN_0_Count_6_DYMUX_4659,
CE => BTN_0_Count_6_CEINVNOT,
CLK => BTN_0_Count_6_CLKINV_4637,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_6_SRINV_4638,
O => BTN_0_Count(7)
);
BTN_0_Count_6 : X_SFF
generic map(
LOC => "SLICE_X65Y84",
INIT => '0'
)
port map (
I => BTN_0_Count_6_DXMUX_4677,
CE => BTN_0_Count_6_CEINVNOT,
CLK => BTN_0_Count_6_CLKINV_4637,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_6_SRINV_4638,
O => BTN_0_Count(6)
);
BTN_0_Count_9 : X_SFF
generic map(
LOC => "SLICE_X65Y85",
INIT => '0'
)
port map (
I => BTN_0_Count_8_DYMUX_4715,
CE => BTN_0_Count_8_CEINVNOT,
CLK => BTN_0_Count_8_CLKINV_4693,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_8_SRINV_4694,
O => BTN_0_Count(9)
);
BTN_0_Mcount_Count_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"5555",
LOC => "SLICE_X65Y81"
)
port map (
ADR0 => BTN_0_Count(0),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Mcount_Count_lut(0)
);
BTN_0_Count_0 : X_SFF
generic map(
LOC => "SLICE_X65Y81",
INIT => '0'
)
port map (
I => BTN_0_Count_0_DXMUX_4509,
CE => BTN_0_Count_0_CEINVNOT,
CLK => BTN_0_Count_0_CLKINV_4471,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_0_SRINV_4472,
O => BTN_0_Count(0)
);
BTN_0_Count_3 : X_SFF
generic map(
LOC => "SLICE_X65Y82",
INIT => '0'
)
port map (
I => BTN_0_Count_2_DYMUX_4547,
CE => BTN_0_Count_2_CEINVNOT,
CLK => BTN_0_Count_2_CLKINV_4525,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_2_SRINV_4526,
O => BTN_0_Count(3)
);
BTN_0_Count_2 : X_SFF
generic map(
LOC => "SLICE_X65Y82",
INIT => '0'
)
port map (
I => BTN_0_Count_2_DXMUX_4565,
CE => BTN_0_Count_2_CEINVNOT,
CLK => BTN_0_Count_2_CLKINV_4525,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_2_SRINV_4526,
O => BTN_0_Count(2)
);
BTN_0_Count_5 : X_SFF
generic map(
LOC => "SLICE_X65Y83",
INIT => '0'
)
port map (
I => BTN_0_Count_4_DYMUX_4603,
CE => BTN_0_Count_4_CEINVNOT,
CLK => BTN_0_Count_4_CLKINV_4581,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_4_SRINV_4582,
O => BTN_0_Count(5)
);
BTN_2_Count_5 : X_SFF
generic map(
LOC => "SLICE_X65Y69",
INIT => '0'
)
port map (
I => BTN_2_Count_4_DYMUX_5505,
CE => BTN_2_Count_4_CEINVNOT,
CLK => BTN_2_Count_4_CLKINV_5483,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_4_SRINV_5484,
O => BTN_2_Count(5)
);
BTN_2_Count_4 : X_SFF
generic map(
LOC => "SLICE_X65Y69",
INIT => '0'
)
port map (
I => BTN_2_Count_4_DXMUX_5523,
CE => BTN_2_Count_4_CEINVNOT,
CLK => BTN_2_Count_4_CLKINV_5483,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_4_SRINV_5484,
O => BTN_2_Count(4)
);
BTN_2_Count_7 : X_SFF
generic map(
LOC => "SLICE_X65Y70",
INIT => '0'
)
port map (
I => BTN_2_Count_6_DYMUX_5561,
CE => BTN_2_Count_6_CEINVNOT,
CLK => BTN_2_Count_6_CLKINV_5539,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_6_SRINV_5540,
O => BTN_2_Count(7)
);
BTN_2_Count_6 : X_SFF
generic map(
LOC => "SLICE_X65Y70",
INIT => '0'
)
port map (
I => BTN_2_Count_6_DXMUX_5579,
CE => BTN_2_Count_6_CEINVNOT,
CLK => BTN_2_Count_6_CLKINV_5539,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_6_SRINV_5540,
O => BTN_2_Count(6)
);
BTN_0_Count_18 : X_SFF
generic map(
LOC => "SLICE_X65Y90",
INIT => '0'
)
port map (
I => BTN_0_Count_18_DXMUX_5013,
CE => BTN_0_Count_18_CEINVNOT,
CLK => BTN_0_Count_18_CLKINV_4973,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_18_SRINV_4974,
O => BTN_0_Count(18)
);
BTN_0_Count_20_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y91"
)
port map (
ADR0 => VCC,
ADR1 => BTN_0_Count(20),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_20_rt_5035
);
BTN_0_Count_20 : X_SFF
generic map(
LOC => "SLICE_X65Y91",
INIT => '0'
)
port map (
I => BTN_0_Count_20_DXMUX_5040,
CE => BTN_0_Count_20_CEINVNOT,
CLK => BTN_0_Count_20_CLKINV_5026,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_20_SRINV_5027,
O => BTN_0_Count(20)
);
SSeg_Mcount_count240hz_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X33Y14"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(0),
O => SSeg_Mcount_count240hz_lut(0)
);
BTN_0_Count_15 : X_SFF
generic map(
LOC => "SLICE_X65Y88",
INIT => '0'
)
port map (
I => BTN_0_Count_14_DYMUX_4883,
CE => BTN_0_Count_14_CEINVNOT,
CLK => BTN_0_Count_14_CLKINV_4861,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_14_SRINV_4862,
O => BTN_0_Count(15)
);
BTN_0_Count_14 : X_SFF
generic map(
LOC => "SLICE_X65Y88",
INIT => '0'
)
port map (
I => BTN_0_Count_14_DXMUX_4901,
CE => BTN_0_Count_14_CEINVNOT,
CLK => BTN_0_Count_14_CLKINV_4861,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_14_SRINV_4862,
O => BTN_0_Count(14)
);
BTN_0_Count_17 : X_SFF
generic map(
LOC => "SLICE_X65Y89",
INIT => '0'
)
port map (
I => BTN_0_Count_16_DYMUX_4939,
CE => BTN_0_Count_16_CEINVNOT,
CLK => BTN_0_Count_16_CLKINV_4917,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_16_SRINV_4918,
O => BTN_0_Count(17)
);
BTN_0_Count_16 : X_SFF
generic map(
LOC => "SLICE_X65Y89",
INIT => '0'
)
port map (
I => BTN_0_Count_16_DXMUX_4957,
CE => BTN_0_Count_16_CEINVNOT,
CLK => BTN_0_Count_16_CLKINV_4917,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_16_SRINV_4918,
O => BTN_0_Count(16)
);
BTN_0_Count_19 : X_SFF
generic map(
LOC => "SLICE_X65Y90",
INIT => '0'
)
port map (
I => BTN_0_Count_18_DYMUX_4995,
CE => BTN_0_Count_18_CEINVNOT,
CLK => BTN_0_Count_18_CLKINV_4973,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_0_Count_18_SRINV_4974,
O => BTN_0_Count(19)
);
BTN_2_Count_12 : X_SFF
generic map(
LOC => "SLICE_X65Y73",
INIT => '0'
)
port map (
I => BTN_2_Count_12_DXMUX_5747,
CE => BTN_2_Count_12_CEINVNOT,
CLK => BTN_2_Count_12_CLKINV_5707,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_12_SRINV_5708,
O => BTN_2_Count(12)
);
BTN_2_Count_15 : X_SFF
generic map(
LOC => "SLICE_X65Y74",
INIT => '0'
)
port map (
I => BTN_2_Count_14_DYMUX_5785,
CE => BTN_2_Count_14_CEINVNOT,
CLK => BTN_2_Count_14_CLKINV_5763,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_14_SRINV_5764,
O => BTN_2_Count(15)
);
BTN_2_Count_14 : X_SFF
generic map(
LOC => "SLICE_X65Y74",
INIT => '0'
)
port map (
I => BTN_2_Count_14_DXMUX_5803,
CE => BTN_2_Count_14_CEINVNOT,
CLK => BTN_2_Count_14_CLKINV_5763,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_14_SRINV_5764,
O => BTN_2_Count(14)
);
BTN_2_Count_17 : X_SFF
generic map(
LOC => "SLICE_X65Y75",
INIT => '0'
)
port map (
I => BTN_2_Count_16_DYMUX_5841,
CE => BTN_2_Count_16_CEINVNOT,
CLK => BTN_2_Count_16_CLKINV_5819,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_16_SRINV_5820,
O => BTN_2_Count(17)
);
BTN_2_Count_1 : X_SFF
generic map(
LOC => "SLICE_X65Y67",
INIT => '0'
)
port map (
I => BTN_2_Count_0_DYMUX_5390,
CE => BTN_2_Count_0_CEINVNOT,
CLK => BTN_2_Count_0_CLKINV_5373,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_0_SRINV_5374,
O => BTN_2_Count(1)
);
BTN_2_Mcount_Count_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X65Y67"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(0),
O => BTN_2_Mcount_Count_lut(0)
);
BTN_2_Count_0 : X_SFF
generic map(
LOC => "SLICE_X65Y67",
INIT => '0'
)
port map (
I => BTN_2_Count_0_DXMUX_5411,
CE => BTN_2_Count_0_CEINVNOT,
CLK => BTN_2_Count_0_CLKINV_5373,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_0_SRINV_5374,
O => BTN_2_Count(0)
);
BTN_2_Count_3 : X_SFF
generic map(
LOC => "SLICE_X65Y68",
INIT => '0'
)
port map (
I => BTN_2_Count_2_DYMUX_5449,
CE => BTN_2_Count_2_CEINVNOT,
CLK => BTN_2_Count_2_CLKINV_5427,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_2_SRINV_5428,
O => BTN_2_Count(3)
);
BTN_2_Count_2 : X_SFF
generic map(
LOC => "SLICE_X65Y68",
INIT => '0'
)
port map (
I => BTN_2_Count_2_DXMUX_5467,
CE => BTN_2_Count_2_CEINVNOT,
CLK => BTN_2_Count_2_CLKINV_5427,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_2_SRINV_5428,
O => BTN_2_Count(2)
);
BTN_3_Count_18 : X_SFF
generic map(
LOC => "SLICE_X53Y70",
INIT => '0'
)
port map (
I => BTN_3_Count_18_DXMUX_6500,
CE => BTN_3_Count_18_CEINVNOT,
CLK => BTN_3_Count_18_CLKINV_6460,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_18_SRINV_6461,
O => BTN_3_Count(18)
);
BTN_3_Count_20_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X53Y71"
)
port map (
ADR0 => VCC,
ADR1 => BTN_3_Count(20),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_20_rt_6522
);
BTN_3_Count_20 : X_SFF
generic map(
LOC => "SLICE_X53Y71",
INIT => '0'
)
port map (
I => BTN_3_Count_20_DXMUX_6527,
CE => BTN_3_Count_20_CEINVNOT,
CLK => BTN_3_Count_20_CLKINV_6513,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_20_SRINV_6514,
O => BTN_3_Count(20)
);
SSeg_count240hz_cmp_eq0000_wg_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"00FF",
LOC => "SLICE_X35Y18"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(4),
O => SSeg_count240hz_cmp_eq0000_wg_lut(0)
);
SSeg_count240hz_cmp_eq0000_wg_lut_2_Q : X_LUT4
generic map(
INIT => X"0800",
LOC => "SLICE_X35Y19"
)
port map (
ADR0 => SSeg_count240hz(9),
ADR1 => SSeg_count240hz(10),
ADR2 => SSeg_count240hz(8),
ADR3 => SSeg_count240hz(1),
O => SSeg_count240hz_cmp_eq0000_wg_lut(2)
);
BTN_2_Count_9 : X_SFF
generic map(
LOC => "SLICE_X65Y71",
INIT => '0'
)
port map (
I => BTN_2_Count_8_DYMUX_5617,
CE => BTN_2_Count_8_CEINVNOT,
CLK => BTN_2_Count_8_CLKINV_5595,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_8_SRINV_5596,
O => BTN_2_Count(9)
);
BTN_2_Count_8 : X_SFF
generic map(
LOC => "SLICE_X65Y71",
INIT => '0'
)
port map (
I => BTN_2_Count_8_DXMUX_5635,
CE => BTN_2_Count_8_CEINVNOT,
CLK => BTN_2_Count_8_CLKINV_5595,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_8_SRINV_5596,
O => BTN_2_Count(8)
);
BTN_2_Count_11 : X_SFF
generic map(
LOC => "SLICE_X65Y72",
INIT => '0'
)
port map (
I => BTN_2_Count_10_DYMUX_5673,
CE => BTN_2_Count_10_CEINVNOT,
CLK => BTN_2_Count_10_CLKINV_5651,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_10_SRINV_5652,
O => BTN_2_Count(11)
);
BTN_2_Count_10 : X_SFF
generic map(
LOC => "SLICE_X65Y72",
INIT => '0'
)
port map (
I => BTN_2_Count_10_DXMUX_5691,
CE => BTN_2_Count_10_CEINVNOT,
CLK => BTN_2_Count_10_CLKINV_5651,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_10_SRINV_5652,
O => BTN_2_Count(10)
);
BTN_2_Count_13 : X_SFF
generic map(
LOC => "SLICE_X65Y73",
INIT => '0'
)
port map (
I => BTN_2_Count_12_DYMUX_5729,
CE => BTN_2_Count_12_CEINVNOT,
CLK => BTN_2_Count_12_CLKINV_5707,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_12_SRINV_5708,
O => BTN_2_Count(13)
);
BTN_2_Count_16 : X_SFF
generic map(
LOC => "SLICE_X65Y75",
INIT => '0'
)
port map (
I => BTN_2_Count_16_DXMUX_5859,
CE => BTN_2_Count_16_CEINVNOT,
CLK => BTN_2_Count_16_CLKINV_5819,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_16_SRINV_5820,
O => BTN_2_Count(16)
);
BTN_2_Count_19 : X_SFF
generic map(
LOC => "SLICE_X65Y76",
INIT => '0'
)
port map (
I => BTN_2_Count_18_DYMUX_5897,
CE => BTN_2_Count_18_CEINVNOT,
CLK => BTN_2_Count_18_CLKINV_5875,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_18_SRINV_5876,
O => BTN_2_Count(19)
);
BTN_2_Count_18 : X_SFF
generic map(
LOC => "SLICE_X65Y76",
INIT => '0'
)
port map (
I => BTN_2_Count_18_DXMUX_5915,
CE => BTN_2_Count_18_CEINVNOT,
CLK => BTN_2_Count_18_CLKINV_5875,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_18_SRINV_5876,
O => BTN_2_Count(18)
);
BTN_2_Count_20_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y77"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(20),
O => BTN_2_Count_20_rt_5937
);
BTN_2_Count_20 : X_SFF
generic map(
LOC => "SLICE_X65Y77",
INIT => '0'
)
port map (
I => BTN_2_Count_20_DXMUX_5942,
CE => BTN_2_Count_20_CEINVNOT,
CLK => BTN_2_Count_20_CLKINV_5928,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_2_Count_20_SRINV_5929,
O => BTN_2_Count(20)
);
BTN_3_Count_1 : X_SFF
generic map(
LOC => "SLICE_X53Y61",
INIT => '0'
)
port map (
I => BTN_3_Count_0_DYMUX_5975,
CE => BTN_3_Count_0_CEINVNOT,
CLK => BTN_3_Count_0_CLKINV_5958,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_0_SRINV_5959,
O => BTN_3_Count(1)
);
BTN_3_Mcount_Count_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"3333",
LOC => "SLICE_X53Y61"
)
port map (
ADR0 => VCC,
ADR1 => BTN_3_Count(0),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Mcount_Count_lut(0)
);
BTN_3_Count_0 : X_SFF
generic map(
LOC => "SLICE_X53Y61",
INIT => '0'
)
port map (
I => BTN_3_Count_0_DXMUX_5996,
CE => BTN_3_Count_0_CEINVNOT,
CLK => BTN_3_Count_0_CLKINV_5958,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_0_SRINV_5959,
O => BTN_3_Count(0)
);
BTN_3_Count_3 : X_SFF
generic map(
LOC => "SLICE_X53Y62",
INIT => '0'
)
port map (
I => BTN_3_Count_2_DYMUX_6034,
CE => BTN_3_Count_2_CEINVNOT,
CLK => BTN_3_Count_2_CLKINV_6012,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_2_SRINV_6013,
O => BTN_3_Count(3)
);
BTN_3_Count_2 : X_SFF
generic map(
LOC => "SLICE_X53Y62",
INIT => '0'
)
port map (
I => BTN_3_Count_2_DXMUX_6052,
CE => BTN_3_Count_2_CEINVNOT,
CLK => BTN_3_Count_2_CLKINV_6012,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_2_SRINV_6013,
O => BTN_3_Count(2)
);
BTN_3_Count_5 : X_SFF
generic map(
LOC => "SLICE_X53Y63",
INIT => '0'
)
port map (
I => BTN_3_Count_4_DYMUX_6090,
CE => BTN_3_Count_4_CEINVNOT,
CLK => BTN_3_Count_4_CLKINV_6068,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_4_SRINV_6069,
O => BTN_3_Count(5)
);
BTN_3_Count_4 : X_SFF
generic map(
LOC => "SLICE_X53Y63",
INIT => '0'
)
port map (
I => BTN_3_Count_4_DXMUX_6108,
CE => BTN_3_Count_4_CEINVNOT,
CLK => BTN_3_Count_4_CLKINV_6068,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_4_SRINV_6069,
O => BTN_3_Count(4)
);
BTN_3_Count_7 : X_SFF
generic map(
LOC => "SLICE_X53Y64",
INIT => '0'
)
port map (
I => BTN_3_Count_6_DYMUX_6146,
CE => BTN_3_Count_6_CEINVNOT,
CLK => BTN_3_Count_6_CLKINV_6124,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_6_SRINV_6125,
O => BTN_3_Count(7)
);
BTN_3_Count_6 : X_SFF
generic map(
LOC => "SLICE_X53Y64",
INIT => '0'
)
port map (
I => BTN_3_Count_6_DXMUX_6164,
CE => BTN_3_Count_6_CEINVNOT,
CLK => BTN_3_Count_6_CLKINV_6124,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_6_SRINV_6125,
O => BTN_3_Count(6)
);
BTN_3_Count_9 : X_SFF
generic map(
LOC => "SLICE_X53Y65",
INIT => '0'
)
port map (
I => BTN_3_Count_8_DYMUX_6202,
CE => BTN_3_Count_8_CEINVNOT,
CLK => BTN_3_Count_8_CLKINV_6180,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_8_SRINV_6181,
O => BTN_3_Count(9)
);
BTN_3_Count_8 : X_SFF
generic map(
LOC => "SLICE_X53Y65",
INIT => '0'
)
port map (
I => BTN_3_Count_8_DXMUX_6220,
CE => BTN_3_Count_8_CEINVNOT,
CLK => BTN_3_Count_8_CLKINV_6180,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_8_SRINV_6181,
O => BTN_3_Count(8)
);
BTN_3_Count_15 : X_SFF
generic map(
LOC => "SLICE_X53Y68",
INIT => '0'
)
port map (
I => BTN_3_Count_14_DYMUX_6370,
CE => BTN_3_Count_14_CEINVNOT,
CLK => BTN_3_Count_14_CLKINV_6348,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_14_SRINV_6349,
O => BTN_3_Count(15)
);
BTN_3_Count_14 : X_SFF
generic map(
LOC => "SLICE_X53Y68",
INIT => '0'
)
port map (
I => BTN_3_Count_14_DXMUX_6388,
CE => BTN_3_Count_14_CEINVNOT,
CLK => BTN_3_Count_14_CLKINV_6348,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_14_SRINV_6349,
O => BTN_3_Count(14)
);
BTN_3_Count_17 : X_SFF
generic map(
LOC => "SLICE_X53Y69",
INIT => '0'
)
port map (
I => BTN_3_Count_16_DYMUX_6426,
CE => BTN_3_Count_16_CEINVNOT,
CLK => BTN_3_Count_16_CLKINV_6404,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_16_SRINV_6405,
O => BTN_3_Count(17)
);
BTN_3_Count_16 : X_SFF
generic map(
LOC => "SLICE_X53Y69",
INIT => '0'
)
port map (
I => BTN_3_Count_16_DXMUX_6444,
CE => BTN_3_Count_16_CEINVNOT,
CLK => BTN_3_Count_16_CLKINV_6404,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_16_SRINV_6405,
O => BTN_3_Count(16)
);
BTN_3_Count_19 : X_SFF
generic map(
LOC => "SLICE_X53Y70",
INIT => '0'
)
port map (
I => BTN_3_Count_18_DYMUX_6482,
CE => BTN_3_Count_18_CEINVNOT,
CLK => BTN_3_Count_18_CLKINV_6460,
SET => GND,
RST => GND,
SSET => GND,
SRST => BTN_3_Count_18_SRINV_6461,
O => BTN_3_Count(19)
);
SSeg_Mmux_hexnum_mux0001257_G : X_LUT4
generic map(
INIT => X"5410",
LOC => "SLICE_X66Y35"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => UXCntl_Unit_VALA(2),
ADR3 => UXCntl_Unit_VALA(6),
O => N101
);
SSeg_Mmux_hexnum_mux0001828_G : X_LUT4
generic map(
INIT => X"FF08",
LOC => "SLICE_X64Y23"
)
port map (
ADR0 => UXCntl_Unit_VALB(0),
ADR1 => N12,
ADR2 => UXCntl_Unit_VALB(2),
ADR3 => SSeg_Mmux_hexnum_mux0001825_0,
O => N99
);
SSeg_Mmux_hexnum_mux0001686_G : X_LUT4
generic map(
INIT => X"4450",
LOC => "SLICE_X67Y25"
)
port map (
ADR0 => UXCntl_Unit_VALB(1),
ADR1 => UXCntl_Unit_VALA(7),
ADR2 => UXCntl_Unit_VALA(6),
ADR3 => UXCntl_Unit_VALB(0),
O => N109
);
SSeg_Mmux_hexnum_mux000121711 : X_LUT4
generic map(
INIT => X"3000",
LOC => "SLICE_X64Y34"
)
port map (
ADR0 => VCC,
ADR1 => UXCntl_Unit_VALB(2),
ADR2 => N23,
ADR3 => N11,
O => SSeg_Mmux_hexnum_mux000121711_6999
);
SSeg_Mmux_hexnum_mux000143121 : X_LUT4
generic map(
INIT => X"FFCD",
LOC => "SLICE_X67Y20"
)
port map (
ADR0 => UXCntl_Unit_VALB(1),
ADR1 => SSeg_Mmux_hexnum_mux00014272_0,
ADR2 => N94_0,
ADR3 => SSeg_Mmux_hexnum_mux00014256_0,
O => SSeg_Mmux_hexnum_mux000143121_7024
);
SSeg_Mrom_AN_OUT_mux0001111 : X_LUT4
generic map(
INIT => X"F0FF",
LOC => "SLICE_X67Y61"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => SSeg_pos(0),
ADR3 => SSeg_pos(1),
O => SSeg_Mrom_AN_OUT_mux00011
);
SSeg_AN_OUT_1 : X_FF
generic map(
LOC => "SLICE_X67Y61",
INIT => '0'
)
port map (
I => SSeg_AN_OUT_1_DXMUX_7191,
CE => VCC,
CLK => SSeg_AN_OUT_1_CLKINV_7168,
SET => GND,
RST => GND,
O => SSeg_AN_OUT(1)
);
SSeg_AN_OUT_2 : X_FF
generic map(
LOC => "SLICE_X66Y81",
INIT => '0'
)
port map (
I => SSeg_AN_OUT_3_DYMUX_7212,
CE => VCC,
CLK => SSeg_AN_OUT_3_CLKINV_7202,
SET => GND,
RST => GND,
O => SSeg_AN_OUT(2)
);
SSeg_Mrom_AN_OUT_mux000131 : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X66Y81"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_pos(1),
ADR2 => VCC,
ADR3 => SSeg_pos(0),
O => SSeg_Mrom_AN_OUT_mux00013
);
SSeg_AN_OUT_3 : X_FF
generic map(
LOC => "SLICE_X66Y81",
INIT => '0'
)
port map (
I => SSeg_AN_OUT_3_DXMUX_7225,
CE => VCC,
CLK => SSeg_AN_OUT_3_CLKINV_7202,
SET => GND,
RST => GND,
O => SSeg_AN_OUT(3)
);
SSeg_count240hz_10 : X_FF
generic map(
LOC => "SLICE_X32Y18",
INIT => '0'
)
port map (
I => SSeg_count240hz_11_DYMUX_7246,
CE => VCC,
CLK => SSeg_count240hz_11_CLKINV_7236,
SET => GND,
RST => GND,
O => SSeg_count240hz(10)
);
SSeg_Mcount_count240hz_eqn_111 : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X32Y18"
)
port map (
ADR0 => SSeg_Result(11),
ADR1 => VCC,
ADR2 => SSeg_count240hz_cmp_eq0000,
ADR3 => VCC,
O => SSeg_Mcount_count240hz_eqn_11
);
SSeg_count240hz_11 : X_FF
generic map(
LOC => "SLICE_X32Y18",
INIT => '0'
)
port map (
I => SSeg_count240hz_11_DXMUX_7259,
CE => VCC,
CLK => SSeg_count240hz_11_CLKINV_7236,
SET => GND,
RST => GND,
O => SSeg_count240hz(11)
);
SSeg_count240hz_12 : X_FF
generic map(
LOC => "SLICE_X32Y20",
INIT => '0'
)
port map (
I => SSeg_count240hz_13_DYMUX_7280,
CE => VCC,
CLK => SSeg_count240hz_13_CLKINV_7270,
SET => GND,
RST => GND,
O => SSeg_count240hz(12)
);
SSeg_Mcount_count240hz_eqn_131 : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X32Y20"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_Result(13),
ADR2 => VCC,
ADR3 => SSeg_count240hz_cmp_eq0000,
O => SSeg_Mcount_count240hz_eqn_13
);
SSeg_count240hz_13 : X_FF
generic map(
LOC => "SLICE_X32Y20",
INIT => '0'
)
port map (
I => SSeg_count240hz_13_DXMUX_7293,
CE => VCC,
CLK => SSeg_count240hz_13_CLKINV_7270,
SET => GND,
RST => GND,
O => SSeg_count240hz(13)
);
SSeg_Mmux_hexnum_mux00012300 : X_LUT4
generic map(
INIT => X"AA00",
LOC => "SLICE_X67Y29"
)
port map (
ADR0 => SSeg_pos(1),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_Mmux_hexnum_mux00012292_O,
O => SSeg_hexnum_mux0001(0)
);
SSeg_hexnum_0 : X_FF
generic map(
LOC => "SLICE_X67Y29",
INIT => '0'
)
port map (
I => SSeg_hexnum_0_DXMUX_7079,
CE => VCC,
CLK => SSeg_hexnum_0_CLKINV_7062,
SET => GND,
RST => GND,
O => SSeg_hexnum(0)
);
SSeg_Mmux_hexnum_mux00014384 : X_LUT4
generic map(
INIT => X"F808",
LOC => "SLICE_X66Y38"
)
port map (
ADR0 => SSeg_pos(1),
ADR1 => SSeg_Mmux_hexnum_mux00014346_0,
ADR2 => SSeg_pos(0),
ADR3 => SSeg_Mmux_hexnum_mux00014384_SW0_O,
O => SSeg_hexnum_mux0001(1)
);
SSeg_hexnum_1 : X_FF
generic map(
LOC => "SLICE_X66Y38",
INIT => '0'
)
port map (
I => SSeg_hexnum_1_DXMUX_7109,
CE => VCC,
CLK => SSeg_hexnum_1_CLKINV_7093,
SET => GND,
RST => GND,
O => SSeg_hexnum(1)
);
SSeg_Mmux_hexnum_mux00016338 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X66Y28"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_pos(1),
ADR2 => VCC,
ADR3 => SSeg_Mmux_hexnum_mux00016330_O,
O => SSeg_hexnum_mux0001(2)
);
SSeg_hexnum_2 : X_FF
generic map(
LOC => "SLICE_X66Y28",
INIT => '0'
)
port map (
I => SSeg_hexnum_2_DXMUX_7139,
CE => VCC,
CLK => SSeg_hexnum_2_CLKINV_7122,
SET => GND,
RST => GND,
O => SSeg_hexnum(2)
);
SSeg_hexnum_3 : X_FF
generic map(
LOC => "SLICE_X67Y31",
INIT => '0'
)
port map (
I => SSeg_hexnum_3_DYMUX_7157,
CE => VCC,
CLK => SSeg_hexnum_3_CLKINV_7147,
SET => GND,
RST => GND,
O => SSeg_hexnum(3)
);
SSeg_AN_OUT_0 : X_FF
generic map(
LOC => "SLICE_X67Y61",
INIT => '0'
)
port map (
I => SSeg_AN_OUT_1_DYMUX_7178,
CE => VCC,
CLK => SSeg_AN_OUT_1_CLKINV_7168,
SET => GND,
RST => GND,
O => SSeg_AN_OUT(0)
);
BTN_1_Count_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X67Y70"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_1_Count(1),
O => BTN_1_Count_0_G
);
BTN_1_Count_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X67Y71"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_1_Count(2),
ADR3 => VCC,
O => BTN_1_Count_2_F
);
BTN_1_Count_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X67Y71"
)
port map (
ADR0 => VCC,
ADR1 => BTN_1_Count(3),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_2_G
);
BTN_1_Count_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X67Y72"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_1_Count(4),
ADR3 => VCC,
O => BTN_1_Count_4_F
);
BTN_1_Count_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X67Y72"
)
port map (
ADR0 => VCC,
ADR1 => BTN_1_Count(5),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_4_G
);
BTN_1_Count_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X67Y73"
)
port map (
ADR0 => BTN_1_Count(6),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_6_F
);
BTN_1_Count_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X67Y73"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_1_Count(7),
O => BTN_1_Count_6_G
);
BTN_1_Count_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X67Y74"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_1_Count(8),
ADR3 => VCC,
O => BTN_1_Count_8_F
);
BTN_1_Count_8_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X67Y74"
)
port map (
ADR0 => VCC,
ADR1 => BTN_1_Count(9),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_8_G
);
BTN_1_Count_10_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X67Y75"
)
port map (
ADR0 => BTN_1_Count(10),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_10_F
);
BTN_1_Count_10_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X67Y75"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_1_Count(11),
O => BTN_1_Count_10_G
);
BTN_1_Count_12_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X67Y76"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_1_Count(12),
ADR3 => VCC,
O => BTN_1_Count_12_F
);
BTN_1_Count_12_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X67Y76"
)
port map (
ADR0 => VCC,
ADR1 => BTN_1_Count(13),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_12_G
);
BTN_1_Count_14_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X67Y77"
)
port map (
ADR0 => BTN_1_Count(14),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_14_F
);
BTN_1_Count_14_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X67Y77"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_1_Count(15),
O => BTN_1_Count_14_G
);
BTN_1_Count_16_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X67Y78"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_1_Count(16),
ADR3 => VCC,
O => BTN_1_Count_16_F
);
BTN_1_Count_16_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X67Y78"
)
port map (
ADR0 => VCC,
ADR1 => BTN_1_Count(17),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_16_G
);
BTN_1_Count_18_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X67Y79"
)
port map (
ADR0 => BTN_1_Count(18),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_1_Count_18_F
);
BTN_1_Count_18_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X67Y79"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_1_Count(19),
O => BTN_1_Count_18_G
);
BTN_0_Count_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y81"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_0_Count(1),
O => BTN_0_Count_0_G
);
BTN_0_Count_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y82"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_0_Count(2),
ADR3 => VCC,
O => BTN_0_Count_2_F
);
BTN_0_Count_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y82"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_0_Count(3),
O => BTN_0_Count_2_G
);
BTN_0_Count_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y83"
)
port map (
ADR0 => BTN_0_Count(4),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_4_F
);
BTN_0_Count_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y83"
)
port map (
ADR0 => VCC,
ADR1 => BTN_0_Count(5),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_4_G
);
BTN_0_Count_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y84"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_0_Count(6),
O => BTN_0_Count_6_F
);
BTN_0_Count_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y84"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_0_Count(7),
ADR3 => VCC,
O => BTN_0_Count_6_G
);
BTN_0_Count_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y85"
)
port map (
ADR0 => BTN_0_Count(8),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_8_F
);
BTN_0_Count_8_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y85"
)
port map (
ADR0 => VCC,
ADR1 => BTN_0_Count(9),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_8_G
);
BTN_0_Count_10_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y86"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_0_Count(10),
O => BTN_0_Count_10_F
);
BTN_0_Count_10_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y86"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_0_Count(11),
ADR3 => VCC,
O => BTN_0_Count_10_G
);
BTN_0_Count_12_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y87"
)
port map (
ADR0 => BTN_0_Count(12),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_12_F
);
BTN_0_Count_12_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y87"
)
port map (
ADR0 => VCC,
ADR1 => BTN_0_Count(13),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_12_G
);
BTN_0_Count_14_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y88"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_0_Count(14),
ADR3 => VCC,
O => BTN_0_Count_14_F
);
BTN_0_Count_14_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y88"
)
port map (
ADR0 => VCC,
ADR1 => BTN_0_Count(15),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_14_G
);
BTN_0_Count_16_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y89"
)
port map (
ADR0 => BTN_0_Count(16),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_16_F
);
BTN_0_Count_16_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y89"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_0_Count(17),
O => BTN_0_Count_16_G
);
BTN_0_Count_18_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y90"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_0_Count(18),
O => BTN_0_Count_18_F
);
BTN_0_Count_18_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y90"
)
port map (
ADR0 => BTN_0_Count(19),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_0_Count_18_G
);
SSeg_Result_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X33Y14"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz(1),
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_0_G
);
SSeg_Result_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X33Y15"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => SSeg_count240hz(2),
ADR3 => VCC,
O => SSeg_Result_2_F
);
SSeg_Result_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X33Y15"
)
port map (
ADR0 => SSeg_count240hz(3),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_2_G
);
SSeg_Result_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X33Y16"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(4),
O => SSeg_Result_4_F
);
SSeg_Result_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X33Y16"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz(5),
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_4_G
);
SSeg_Result_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X33Y17"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(6),
O => SSeg_Result_6_F
);
SSeg_Result_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X33Y17"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz(7),
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_6_G
);
SSeg_Result_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X33Y18"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz(8),
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_8_F
);
SSeg_Result_8_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X33Y18"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(9),
O => SSeg_Result_8_G
);
SSeg_Result_10_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X33Y19"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => SSeg_count240hz(10),
ADR3 => VCC,
O => SSeg_Result_10_F
);
SSeg_Result_10_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X33Y19"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(11),
O => SSeg_Result_10_G
);
SSeg_Result_12_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X33Y20"
)
port map (
ADR0 => SSeg_count240hz(12),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_12_F
);
SSeg_Result_12_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X33Y20"
)
port map (
ADR0 => SSeg_count240hz(13),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_12_G
);
SSeg_Result_14_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X33Y21"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => SSeg_count240hz(14),
O => SSeg_Result_14_F
);
SSeg_Result_14_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X33Y21"
)
port map (
ADR0 => VCC,
ADR1 => SSeg_count240hz(15),
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Result_14_G
);
BTN_2_Count_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y67"
)
port map (
ADR0 => BTN_2_Count(1),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_0_G
);
BTN_2_Count_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y68"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(2),
O => BTN_2_Count_2_F
);
BTN_2_Count_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y68"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(3),
O => BTN_2_Count_2_G
);
BTN_2_Count_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y69"
)
port map (
ADR0 => BTN_2_Count(4),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_4_F
);
BTN_2_Count_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y69"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_Count(5),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_4_G
);
BTN_2_Count_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y70"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(6),
O => BTN_2_Count_6_F
);
BTN_2_Count_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y70"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_2_Count(7),
ADR3 => VCC,
O => BTN_2_Count_6_G
);
BTN_2_Count_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y71"
)
port map (
ADR0 => BTN_2_Count(8),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_8_F
);
BTN_2_Count_8_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y71"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_Count(9),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_8_G
);
BTN_2_Count_10_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y72"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(10),
O => BTN_2_Count_10_F
);
BTN_2_Count_10_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y72"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_2_Count(11),
ADR3 => VCC,
O => BTN_2_Count_10_G
);
BTN_2_Count_12_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y73"
)
port map (
ADR0 => BTN_2_Count(12),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_12_F
);
BTN_2_Count_12_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y73"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_Count(13),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_12_G
);
BTN_2_Count_14_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X65Y74"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_2_Count(14),
O => BTN_2_Count_14_F
);
BTN_2_Count_14_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X65Y74"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_2_Count(15),
ADR3 => VCC,
O => BTN_2_Count_14_G
);
BTN_2_Count_16_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y75"
)
port map (
ADR0 => BTN_2_Count(16),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_16_F
);
BTN_2_Count_16_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y75"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_Count(17),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_16_G
);
BTN_2_Count_18_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X65Y76"
)
port map (
ADR0 => BTN_2_Count(18),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_18_F
);
BTN_2_Count_18_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X65Y76"
)
port map (
ADR0 => VCC,
ADR1 => BTN_2_Count(19),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_2_Count_18_G
);
BTN_3_Count_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X53Y61"
)
port map (
ADR0 => BTN_3_Count(1),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_0_G
);
BTN_3_Count_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X53Y62"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_3_Count(2),
ADR3 => VCC,
O => BTN_3_Count_2_F
);
BTN_3_Count_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X53Y62"
)
port map (
ADR0 => VCC,
ADR1 => BTN_3_Count(3),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_2_G
);
BTN_3_Count_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X53Y63"
)
port map (
ADR0 => BTN_3_Count(4),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_4_F
);
BTN_3_Count_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X53Y63"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_3_Count(5),
O => BTN_3_Count_4_G
);
BTN_3_Count_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X53Y64"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_3_Count(6),
ADR3 => VCC,
O => BTN_3_Count_6_F
);
BTN_3_Count_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X53Y64"
)
port map (
ADR0 => VCC,
ADR1 => BTN_3_Count(7),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_6_G
);
BTN_3_Count_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X53Y65"
)
port map (
ADR0 => BTN_3_Count(8),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_8_F
);
BTN_3_Count_8_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X53Y65"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_3_Count(9),
O => BTN_3_Count_8_G
);
BTN_3_Count_10_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X53Y66"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_3_Count(10),
O => BTN_3_Count_10_F
);
BTN_3_Count_10_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X53Y66"
)
port map (
ADR0 => BTN_3_Count(11),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_10_G
);
BTN_3_Count_12_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X53Y67"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_3_Count(12),
ADR3 => VCC,
O => BTN_3_Count_12_F
);
BTN_3_Count_12_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X53Y67"
)
port map (
ADR0 => VCC,
ADR1 => BTN_3_Count(13),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_12_G
);
BTN_3_Count_14_F_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X53Y68"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => BTN_3_Count(14),
ADR3 => VCC,
O => BTN_3_Count_14_F
);
BTN_3_Count_14_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X53Y68"
)
port map (
ADR0 => VCC,
ADR1 => BTN_3_Count(15),
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_14_G
);
BTN_3_Count_16_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X53Y69"
)
port map (
ADR0 => BTN_3_Count(16),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_16_F
);
BTN_3_Count_16_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X53Y69"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_3_Count(17),
O => BTN_3_Count_16_G
);
BTN_3_Count_18_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X53Y70"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => BTN_3_Count(18),
O => BTN_3_Count_18_F
);
BTN_3_Count_18_G_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X53Y70"
)
port map (
ADR0 => BTN_3_Count(19),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => BTN_3_Count_18_G
);
AN_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD71",
PATHPULSE => 638 ps
)
port map (
I => SSeg_AN_OUT(0),
O => AN_0_O
);
AN_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD79",
PATHPULSE => 638 ps
)
port map (
I => SSeg_AN_OUT(1),
O => AN_1_O
);
AN_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD61",
PATHPULSE => 638 ps
)
port map (
I => SSeg_AN_OUT(2),
O => AN_2_O
);
AN_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD67",
PATHPULSE => 638 ps
)
port map (
I => SSeg_AN_OUT(3),
O => AN_3_O
);
SEG_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD95",
PATHPULSE => 638 ps
)
port map (
I => SEG_0_OBUF_2474,
O => SEG_0_O
);
SEG_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD72",
PATHPULSE => 638 ps
)
port map (
I => SEG_1_OBUF_2467,
O => SEG_1_O
);
SEG_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD63",
PATHPULSE => 638 ps
)
port map (
I => SEG_2_OBUF_3312,
O => SEG_2_O
);
SEG_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD62",
PATHPULSE => 638 ps
)
port map (
I => SEG_3_OBUF_3319,
O => SEG_3_O
);
SEG_4_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD70",
PATHPULSE => 638 ps
)
port map (
I => SEG_4_OBUF_3336,
O => SEG_4_O
);
SEG_5_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD87",
PATHPULSE => 638 ps
)
port map (
I => SEG_5_OBUF_3343,
O => SEG_5_O
);
SEG_6_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD77",
PATHPULSE => 638 ps
)
port map (
I => SEG_6_OBUF_3355,
O => SEG_6_O
);
N21_F_X_LUT4 : X_LUT4
generic map(
INIT => X"0000",
LOC => "SLICE_X66Y79"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => N21_F
);
SSeg_Mmux_hexnum_mux00016175_F_X_LUT4 : X_LUT4
generic map(
INIT => X"0000",
LOC => "SLICE_X66Y33"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => SSeg_Mmux_hexnum_mux00016175_F
);
NlwBlock_RPN_toplevel_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_RPN_toplevel_GND : X_ZERO
port map (
O => GND
);
NlwInverterBlock_UXCntl_Unit_VALB_2_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_3_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_2_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_3_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_3_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_3_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_6_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_7_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_6_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_7_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_7_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_7_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_4_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_5_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_4_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_5_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_5_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_5_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_6_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_7_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_6_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_7_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_7_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_7_CLK
);
NlwInverterBlock_UXCntl_Unit_OPCODE_0_CLK : X_INV
port map (
I => UXCntl_Unit_OPCODE_1_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_OPCODE_0_CLK
);
NlwInverterBlock_UXCntl_Unit_OPCODE_1_CLK : X_INV
port map (
I => UXCntl_Unit_OPCODE_1_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_OPCODE_1_CLK
);
NlwInverterBlock_UXCntl_Unit_OPCODE_2_CLK : X_INV
port map (
I => UXCntl_Unit_OPCODE_3_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_OPCODE_2_CLK
);
NlwInverterBlock_UXCntl_Unit_OPCODE_3_CLK : X_INV
port map (
I => UXCntl_Unit_OPCODE_3_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_OPCODE_3_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_0_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_1_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_0_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_1_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_1_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_1_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_2_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_3_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_2_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_3_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_3_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_3_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_0_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_1_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_0_CLK
);
NlwInverterBlock_UXCntl_Unit_VALB_1_CLK : X_INV
port map (
I => UXCntl_Unit_VALB_1_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALB_1_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_4_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_5_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_4_CLK
);
NlwInverterBlock_UXCntl_Unit_VALA_5_CLK : X_INV
port map (
I => UXCntl_Unit_VALA_5_CLKINVNOT,
O => NlwInverterSignal_UXCntl_Unit_VALA_5_CLK
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| gpl-3.0 | 044007abd47b4bd133757e9fb980b969 | 0.545215 | 2.817438 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_log/flt_log_shift_msb_first.vhd | 2 | 18,279 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| gpl-2.0 | 03c534d3cbd775eadad74c659efe24fe | 0.939001 | 1.857811 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/so_xk_counter.vhd | 2 | 301,985 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 221808)
`protect data_block
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| gpl-2.0 | a9d53cee1dd37e9c492c878ea7405ce2 | 0.955703 | 1.809041 | false | false | false | false |
fafaldo/ethernet | ethernet4b/CU.vhd | 1 | 3,283 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CU is
port( clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
empty : in std_logic;
EOF : in std_logic;
ICMP_recognized : in std_logic;
reset : in std_logic;
frame_reset : out std_logic;
enable : out std_logic;
POP : out std_logic
);
end CU;
architecture Behavioral of CU is
type state_type is (IDLE, POP_ON, ENABLE_ON, WAIT_FOR_NEXT, UNKNOWN_WAIT_FOR_NEXT, UNKNOWN_POP_ON, UNKNOWN_ENABLE_ON, RESET_ON);
signal state, next_state : state_type;
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
enable <= '0';
elsif state = ENABLE_ON then
enable <= '1';
else
enable <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
frame_reset <= '0';
elsif state = RESET_ON then
frame_reset <= '1';
else
frame_reset <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
POP <= '0';
elsif state = POP_ON or state = UNKNOWN_POP_ON then
POP <= '1';
else
POP <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif state = ENABLE_ON or state = UNKNOWN_ENABLE_ON then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (state, empty, EOF, address_counter, ICMP_recognized)
begin
next_state <= state;
case (state) is
when IDLE =>
if empty = '0' then
next_state <= POP_ON;
end if;
when POP_ON =>
next_state <= ENABLE_ON;
when ENABLE_ON =>
next_state <= WAIT_FOR_NEXT;
when WAIT_FOR_NEXT =>
if (address_counter < 30 or (address_counter >= 30 and ICMP_recognized = '1')) and empty = '0' and EOF = '0' then
next_state <= POP_ON;
elsif EOF = '1' then
next_state <= RESET_ON;
elsif address_counter >= 30 and ICMP_recognized = '0' then
next_state <= UNKNOWN_WAIT_FOR_NEXT;
end if;
when RESET_ON =>
next_state <= IDLE;
when UNKNOWN_WAIT_FOR_NEXT =>
if EOF = '1' then
next_state <= RESET_ON;
elsif empty = '0' and EOF = '0' then
next_state <= UNKNOWN_POP_ON;
end if;
when UNKNOWN_POP_ON =>
next_state <= UNKNOWN_ENABLE_ON;
when UNKNOWN_ENABLE_ON =>
next_state <= UNKNOWN_WAIT_FOR_NEXT;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral; | apache-2.0 | 0d33abd3c5b42e444981c92f61439877 | 0.587268 | 3.260179 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/mult_gen_v12_0/hdl/dsp.vhd | 12 | 181,273 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | 6fdbc9caeb0a04aa2a3daeb754ceba4e | 0.954042 | 1.812114 | false | false | false | false |
UVVM/UVVM_All | uvvm_vvc_framework/src_target_dependent/td_queue_pkg.vhd | 1 | 2,295 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
--===============================================================================================
-- td_cmd_queue_pkg
-- - Target dependent command queue package
--===============================================================================================
library uvvm_util;
use uvvm_util.generic_queue_pkg;
use work.vvc_cmd_pkg.all;
package td_cmd_queue_pkg is new uvvm_util.generic_queue_pkg
generic map (t_generic_element => t_vvc_cmd_record);
--===============================================================================================
-- td_result_queue_pkg
-- - Target dependent result queue package
--===============================================================================================
library uvvm_util;
use uvvm_util.generic_queue_pkg;
use work.vvc_cmd_pkg.all;
package td_result_queue_pkg is new uvvm_util.generic_queue_pkg
generic map (t_generic_element => t_vvc_result_queue_element);
| mit | 5196f85d77c509207f82da82febaebc1 | 0.437473 | 6.136364 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_wishbone/src/vvc_cmd_pkg.vhd | 1 | 7,455 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
WRITE, READ, CHECK
);
--<USER_INPUT> Create constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- For example, given a VVC with parallel data bus and address bus, constraints should be added for maximum data length
-- and address length
-- Example:
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 1024;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 64;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
max_receptions : integer;
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
addr => (others => '0'),
data => (others => '0'),
max_receptions => 1,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - These are used for storing the result of the read/receive BFM commands issued by the VVC,
-- - so that the result can be transported from the VVC to the sequencer via a
-- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result matches the return value of read/receive procedure in the BFM.
-- It can also be defined as a record if multiple return values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | 50c9c0316b26b5d9464964edb797dfec | 0.452046 | 5.187891 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/Instr_Mem1/simulation/bmg_stim_gen.vhd | 8 | 7,566 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| gpl-3.0 | 966c8dcc187a12f37a20a4cd7b0f688c | 0.557891 | 3.773566 | false | false | false | false |
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| gpl-2.0 | a325c1aba247b7bb535ffa48305dc70d | 0.951743 | 1.825951 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_i2c/src/vvc_methods_pkg.vhd | 1 | 48,443 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
use work.i2c_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the I2C VVC
--===============================================================================================
constant C_VVC_NAME : string := "I2C_VVC";
signal I2C_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is I2C_VVCT;
alias t_bfm_config is t_i2c_bfm_config;
constant C_I2C_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_i2c_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
parent_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_I2C_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_I2C_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_I2C_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0);
data : t_byte_array(0 to C_VVC_CMD_DATA_MAX_LENGTH-1);
num_bytes : natural;
action_when_transfer_is_done : t_action_when_transfer_is_done;
exp_ack : boolean;
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
addr => (others => '0'),
data => (others => (others => '0')),
num_bytes => 0,
operation => NO_OPERATION,
msg => (others => ' '),
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
exp_ack => true
);
shared variable shared_i2c_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_I2C_VVC_CONFIG_DEFAULT);
shared variable shared_i2c_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_i2c_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
-- Scoreboard
package i2c_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0),
element_match => std_match,
to_string_element => to_string);
use i2c_sb_pkg.all;
shared variable I2C_VVC_SB : i2c_sb_pkg.t_generic_sb;
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
-- *****************************************************************************
--
-- master transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- slave transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- master receive
--
-- *****************************************************************************
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- master check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- slave receive
--
-- *****************************************************************************
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- slave check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT);
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record);
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME);
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_i2c_sb(
constant data : in std_logic_vector
) return std_logic_vector;
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
-- master transmit
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_transmit(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, scope, parent_msg_id_panel);
end procedure;
-- slave transmit
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_transmit(VVCT, vvc_instance_idx, v_byte_array, msg, scope, parent_msg_id_panel);
end procedure;
-- master receive
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_NARROWER, "addr", "shared_vvc_cmd.addr", msg);
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.num_bytes := num_bytes;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
i2c_master_receive(VVCT, vvc_instance_idx, addr, num_bytes, NA, msg, action_when_transfer_is_done, scope, parent_msg_id_panel);
end procedure;
-- slave receive
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE);
shared_vvc_cmd.num_bytes := num_bytes;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
i2c_slave_receive(VVCT, vvc_instance_idx, num_bytes, NA, msg, scope, parent_msg_id_panel);
end procedure;
-- master check
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_check(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, alert_level, scope, parent_msg_id_panel);
end procedure;
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_QUICK_CMD);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.exp_ack := exp_ack;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_byte_array, msg, alert_level, rw_bit, scope, parent_msg_id_panel);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_dummy_byte_array : t_byte_array(0 to -1); -- Empty byte array to indicate that data is not checked
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_dummy_byte_array, msg, alert_level, rw_bit, scope, parent_msg_id_panel);
end procedure;
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is
begin
case vvc_cmd.operation is
when MASTER_TRANSMIT | MASTER_RECEIVE | MASTER_CHECK |
SLAVE_TRANSMIT | SLAVE_RECEIVE | SLAVE_CHECK | MASTER_QUICK_CMD =>
vvc_transaction_info_group.bt.operation := vvc_cmd.operation;
vvc_transaction_info_group.bt.addr(vvc_cmd.addr'length-1 downto 0) := vvc_cmd.addr;
vvc_transaction_info_group.bt.data := vvc_cmd.data;
vvc_transaction_info_group.bt.num_bytes := vvc_cmd.num_bytes;
vvc_transaction_info_group.bt.action_when_transfer_is_done := vvc_cmd.action_when_transfer_is_done;
vvc_transaction_info_group.bt.exp_ack := vvc_cmd.exp_ack;
vvc_transaction_info_group.bt.rw_bit := vvc_cmd.rw_bit;
vvc_transaction_info_group.bt.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.bt.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.bt.transaction_status := IN_PROGRESS;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
when others =>
alert(TB_ERROR, "VVC operation not recognized");
end case;
wait for 0 ns;
end procedure set_global_vvc_transaction_info;
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record) is
begin
case vvc_cmd.operation is
when MASTER_TRANSMIT | MASTER_RECEIVE | MASTER_CHECK |
SLAVE_TRANSMIT | SLAVE_RECEIVE | SLAVE_CHECK | MASTER_QUICK_CMD =>
vvc_transaction_info_group.bt := C_BASE_TRANSACTION_SET_DEFAULT;
when others =>
null;
end case;
wait for 0 ns;
end procedure reset_vvc_transaction_info;
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME) is
variable v_activity : t_activity := activity;
begin
-- Update vvc_status after a command has finished (during same delta cycle the activity register is updated)
if activity = INACTIVE then
vvc_status.previous_cmd_idx := last_cmd_idx_executed;
vvc_status.current_cmd_idx := 0;
end if;
if v_activity = INACTIVE and not(command_queue_is_empty) then
v_activity := ACTIVE;
end if;
shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register,
activity => v_activity,
last_cmd_idx_executed => last_cmd_idx_executed);
if global_trigger_vvc_activity_register /= 'L' then
wait until global_trigger_vvc_activity_register = 'L';
end if;
gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER);
end procedure;
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_i2c_sb(
constant data : in std_logic_vector
) return std_logic_vector is
begin
return pad_sb_slv(data, C_VVC_CMD_DATA_MAX_LENGTH);
end function pad_i2c_sb;
end package body vvc_methods_pkg;
| mit | 67ad25bd5b5e91f68fa94d3ceea8f012 | 0.544 | 4.11196 | false | false | false | false |
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| gpl-2.0 | a7064be3c0ecc5d4e51b84d84b8d94da | 0.949072 | 1.832342 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/NewCombined/word_unit.vhd | 2 | 1,893 | ----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
| gpl-3.0 | e5b57143b56e914fdef8d8b885b09d98 | 0.574749 | 3.647399 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 32f304360aad44bd192ccac86695b317 | 0.952777 | 1.818812 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_ethernet/src/ethernet_sb_pkg.vhd | 1 | 1,974 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_pkg;
use work.support_pkg.all;
--==========================================================================================
--==========================================================================================
package ethernet_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map ( t_element => t_ethernet_frame,
element_match => ethernet_match,
to_string_element => to_string); | mit | 74913c3c6c3a0f61f0be5847c614f322 | 0.454914 | 6.246835 | false | false | false | false |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/ip/HLS_accel_ap_fmul_2_max_dsp_32.vhd | 2 | 12,927 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END HLS_accel_ap_fmul_2_max_dsp_32;
ARCHITECTURE HLS_accel_ap_fmul_2_max_dsp_32_arch OF HLS_accel_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_fmul_2_max_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_fmul_2_max_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_fmul_2_max_dsp_32_arch;
| mit | 9a81fb26de8902878336761f8b7f9c14 | 0.636033 | 3.04523 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_mult/flt_mult_exp.vhd | 3 | 43,179 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30224)
`protect data_block
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`protect end_protected
| gpl-2.0 | eee83b4234f85370c99b9822b6f03e92 | 0.94891 | 1.830472 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/compare_eq.vhd | 3 | 10,647 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6144)
`protect data_block
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| gpl-2.0 | 8d4e041c5d10daa8278f84888475a7c7 | 0.925895 | 1.890447 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_ethernet/src/ethernet_tx_vvc.vhd | 1 | 20,078 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_hvvc_to_vvc_bridge;
use work.support_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--==========================================================================================
entity ethernet_tx_vvc is
generic(
GC_INSTANCE_IDX : natural;
GC_CHANNEL : t_channel;
GC_PHY_INTERFACE : t_interface;
GC_PHY_VVC_INSTANCE_IDX : natural;
GC_PHY_MAX_ACCESS_TIME : time := 1 us;
GC_DUT_IF_FIELD_CONFIG : t_dut_if_field_config_direction_array := C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY_DEFAULT;
GC_ETHERNET_PROTOCOL_CONFIG : t_ethernet_protocol_config := C_ETHERNET_PROTOCOL_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
end entity ethernet_tx_vvc;
--==========================================================================================
--==========================================================================================
architecture behave of ethernet_tx_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, GC_CHANNEL);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
signal hvvc_to_bridge : t_hvvc_to_bridge(data_words(0 to C_MAX_PACKET_LENGTH-1)(7 downto 0));
signal bridge_to_hvvc : t_bridge_to_hvvc(data_words(0 to C_MAX_PACKET_LENGTH-1)(7 downto 0));
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_ethernet_vvc_config(GC_CHANNEL, GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_ethernet_vvc_status(GC_CHANNEL, GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_ethernet_vvc_transaction_trigger(GC_CHANNEL, GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_ethernet_vvc_transaction_info(GC_CHANNEL, GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
begin
--==========================================================================================
-- HVVC-to-VVC Bridge
-- Choose the correct architecture with the generic GC_PHY_INTERFACE
--==========================================================================================
gen_hvvc_bridge : if GC_PHY_INTERFACE = GMII generate
i_hvvc_to_vvc_bridge : entity bitvis_vip_hvvc_to_vvc_bridge.hvvc_to_vvc_bridge(GMII)
generic map(
GC_INSTANCE_IDX => GC_PHY_VVC_INSTANCE_IDX,
GC_DUT_IF_FIELD_CONFIG => GC_DUT_IF_FIELD_CONFIG,
GC_MAX_NUM_WORDS => C_MAX_PACKET_LENGTH,
GC_PHY_MAX_ACCESS_TIME => GC_PHY_MAX_ACCESS_TIME,
GC_SCOPE => C_SCOPE
)
port map(
hvvc_to_bridge => hvvc_to_bridge,
bridge_to_hvvc => bridge_to_hvvc
);
elsif GC_PHY_INTERFACE = SBI generate
i_hvvc_to_vvc_bridge : entity bitvis_vip_hvvc_to_vvc_bridge.hvvc_to_vvc_bridge(SBI)
generic map(
GC_INSTANCE_IDX => GC_PHY_VVC_INSTANCE_IDX,
GC_DUT_IF_FIELD_CONFIG => GC_DUT_IF_FIELD_CONFIG,
GC_MAX_NUM_WORDS => C_MAX_PACKET_LENGTH,
GC_PHY_MAX_ACCESS_TIME => GC_PHY_MAX_ACCESS_TIME,
GC_SCOPE => C_SCOPE
)
port map(
hvvc_to_bridge => hvvc_to_bridge,
bridge_to_hvvc => bridge_to_hvvc
);
else generate
alert(TB_FAILURE, "Unsupported interface");
end generate gen_hvvc_bridge;
--==========================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--==========================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_ETHERNET_PROTOCOL_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--==========================================================================================
--==========================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--==========================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(GC_CHANNEL, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc(name => C_VVC_NAME,
channel => GC_CHANNEL,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- Update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(GC_CHANNEL, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor executor
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command executor
-- - Fetch and execute the commands
--==========================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = TRANSMIT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when TRANSMIT =>
-- Set vvc_transaction_info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Call the corresponding procedure in the vvc_methods_pkg.
priv_ethernet_transmit_to_bridge(interpacket_gap_time => vvc_config.bfm_config.interpacket_gap_time,
vvc_cmd => v_cmd,
hvvc_to_bridge => hvvc_to_bridge,
dut_if_field_config => GC_DUT_IF_FIELD_CONFIG(TRANSMIT),
bridge_to_hvvc => bridge_to_hvvc,
vvc_transaction_info => vvc_transaction_info,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
--<USER_INPUT> Uncomment if BFM has clock_period config
-- check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
-- C_SCOPE, ID_NEVER, v_msg_id_panel);
-- wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--==========================================================================================
--==========================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--==========================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--==========================================================================================
end behave; | mit | 3c9dec0e2e0ce2619f5eb87b653837b4 | 0.536856 | 4.26194 | false | true | false | false |
UVVM/uvvm_vvc_framework | bitvis_vip_scoreboard/src/generic_sb_pkg.vhd | 1 | 102,291 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.generic_sb_support_pkg.all;
package generic_sb_pkg is
generic (type t_expected_element;
type t_actual_element;
function match(expected_element : t_expected_element;
actual_element : t_actual_element) return boolean;
function expected_to_string(expected_element : t_expected_element) return string;
function actual_to_string( actual_element : t_actual_element) return string;
constant sb_config_default : t_sb_config := C_SB_CONFIG_DEFAULT;
constant GC_QUEUE_COUNT_MAX : natural := 1000;
constant GC_QUEUE_COUNT_THRESHOLD : natural := 950);
type t_generic_sb is protected
procedure config(
constant sb_config_array : in t_sb_config_array;
constant msg : in string := "");
procedure config(
constant instance : in integer;
constant sb_config : in t_sb_config;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure config(
constant sb_config : in t_sb_config;
constant msg : in string := "");
procedure enable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure enable(
constant msg : in string);
procedure enable(
constant void : in t_void);
procedure disable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure disable(
constant msg : in string);
procedure disable(
constant void : in t_void);
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := "");
procedure add_expected(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "");
procedure add_expected(
constant expected_element : in t_expected_element;
constant msg : in string := "";
constant source : in string := "");
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant msg : in string := "";
constant source : in string := "");
procedure check_actual(
constant instance : in integer;
constant actual_element : in t_actual_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure check_actual(
constant actual_element : in t_actual_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure check_actual(
constant instance : in integer;
constant actual_element : in t_actual_element;
constant msg : in string := "");
procedure check_actual(
constant actual_element : in t_actual_element;
constant msg : in string := "");
procedure flush(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure flush(
constant msg : in string);
procedure flush(
constant void : in t_void);
procedure reset(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure reset(
constant msg : in string);
procedure reset(
constant void : in t_void);
impure function is_empty(
constant instance : in integer) return boolean;
impure function is_empty(
constant void : in t_void) return boolean;
impure function get_entered_count(
constant instance : in integer) return integer;
impure function get_entered_count(
constant void : in t_void) return integer;
impure function get_pending_count(
constant instance : in integer) return integer;
impure function get_pending_count(
constant void : in t_void) return integer;
impure function get_match_count(
constant instance : in integer) return integer;
impure function get_match_count(
constant void : in t_void) return integer;
impure function get_mismatch_count(
constant instance : in integer) return integer;
impure function get_mismatch_count(
constant void : in t_void) return integer;
impure function get_drop_count(
constant instance : in integer) return integer;
impure function get_drop_count(
constant void : in t_void) return integer;
impure function get_initial_garbage_count(
constant instance : in integer) return integer;
impure function get_initial_garbage_count(
constant void : in t_void) return integer;
impure function get_delete_count(
constant instance : in integer) return integer;
impure function get_delete_count(
constant void : in t_void) return integer;
impure function get_overdue_check_count(
constant instance : in integer) return integer;
impure function get_overdue_check_count(
constant void : in t_void) return integer;
procedure set_scope(
constant scope : in string);
impure function get_scope(
constant void : in t_void) return string;
procedure enable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := "");
procedure enable_log_msg(
constant msg_id : in t_msg_id);
procedure disable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := "");
procedure disable_log_msg(
constant msg_id : in t_msg_id);
procedure report_counters(
constant instance : in integer;
constant ext_proc_call : in string := "");
procedure report_counters(
constant void : in t_void);
procedure insert_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := "");
procedure insert_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "");
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant msg : in string := "");
procedure delete_expected(
constant expected_element : in t_expected_element;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "");
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "";
constant ext_proc_call : in string := "");
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "");
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_expected_element) return integer;
impure function find_expected_entry_num(
constant expected_element : in t_expected_element) return integer;
impure function find_expected_entry_num(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_entry_num(
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_expected_element) return integer;
impure function find_expected_position(
constant expected_element : in t_expected_element) return integer;
impure function find_expected_position(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function find_expected_position(
constant tag_usage : in t_tag_usage;
constant tag : in string) return integer;
impure function peek_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return t_expected_element;
impure function peek_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive) return t_expected_element;
impure function peek_expected(
constant instance : integer) return t_expected_element;
impure function peek_expected(
constant void : t_void) return t_expected_element;
impure function peek_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_source(
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_source(
constant instance : integer) return string;
impure function peek_source(
constant void : t_void) return string;
impure function peek_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive) return string;
impure function peek_tag(
constant instance : integer) return string;
impure function peek_tag(
constant void : t_void) return string;
impure function fetch_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return t_expected_element;
impure function fetch_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return t_expected_element;
impure function fetch_expected(
constant instance : integer;
constant msg : string := "") return t_expected_element;
impure function fetch_expected(
constant msg : string) return t_expected_element;
impure function fetch_expected(
constant void : t_void) return t_expected_element;
impure function fetch_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return string;
impure function fetch_source(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return string;
impure function fetch_source(
constant instance : integer;
constant msg : string := "") return string;
impure function fetch_source(
constant msg : string) return string;
impure function fetch_source(
constant void : t_void) return string;
impure function fetch_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := "") return string;
impure function fetch_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "") return string;
impure function fetch_tag(
constant instance : integer;
constant msg : string := "") return string;
impure function fetch_tag(
constant msg : string) return string;
impure function fetch_tag(
constant void : t_void) return string;
impure function exists(
constant instance : integer;
constant expected_element : t_expected_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := "") return boolean;
impure function exists(
constant expected_element : t_expected_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := "") return boolean;
impure function exists(
constant instance : integer;
constant tag_usage : t_tag_usage;
constant tag : string) return boolean;
impure function exists(
constant tag_usage : t_tag_usage;
constant tag : string) return boolean;
end protected t_generic_sb;
end package generic_sb_pkg;
package body generic_sb_pkg is
-- SB type declaration
type t_sb_entry is record
expected_element : t_expected_element;
source : string(1 to C_SB_SOURCE_WIDTH);
tag : string(1 to C_SB_TAG_WIDTH);
entry_time : time;
end record;
-- Declaration of sb_queue_pkg used to store all entries
package sb_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (
t_generic_element => t_sb_entry,
scope => "SB_queue",
GC_QUEUE_COUNT_MAX => 1000,
GC_QUEUE_COUNT_THRESHOLD => 750);
use sb_queue_pkg.all;
type t_generic_sb is protected body
----------------------------------------------------------------------------------------------------
-- Variables
----------------------------------------------------------------------------------------------------
variable vr_scope : string(1 to C_LOG_SCOPE_WIDTH) := (1 to 4 => "?_SB", others => NUL);
variable vr_config : t_sb_config_array(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => sb_config_default);
variable vr_instance_enabled : boolean_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
variable vr_sb_queue : sb_queue_pkg.t_generic_queue;
type t_msg_id_panel_array is array(1 to C_MAX_QUEUE_INSTANCE_NUM) of t_msg_id_panel;
variable vr_msg_id_panel_array : t_msg_id_panel_array := (others => C_SB_MSG_ID_PANEL_DEFAULT);
-- Counters
variable vr_entered_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_match_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_mismatch_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_drop_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_initial_garbage_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_delete_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
variable vr_overdue_check_cnt : integer_vector(1 to C_MAX_QUEUE_INSTANCE_NUM) := (others => -1);
--==================================================================================================
-- NON PUBLIC METHODS
--==================================================================================================
procedure check_instance_in_range(
constant instance : in integer
) is
begin
check_value_in_range(instance, 1, C_MAX_QUEUE_INSTANCE_NUM, TB_ERROR,
"Instance must be within range 1 to C_MAX_QUEUE_INSTANCE_NUM, " & to_string(C_MAX_QUEUE_INSTANCE_NUM) & ".", vr_scope, ID_NEVER);
end procedure check_instance_in_range;
procedure check_instance_enabled(
constant instance : in integer
) is
begin
check_value(vr_instance_enabled(instance), TB_ERROR, "The instance is not enabled", vr_scope, ID_NEVER);
end procedure check_instance_enabled;
procedure check_queue_empty(
constant instance : in positive
) is
begin
check_value(not vr_sb_queue.is_empty(instance), TB_ERROR, "The queue is empty", vr_scope, ID_NEVER);
end procedure check_queue_empty;
procedure check_config_validity(
constant config : in t_sb_config
) is
begin
check_value(config.allow_out_of_order and config.allow_lossy, false, TB_ERROR,
"allow_out_of_order and allow_lossy cannot both be enabled. Se documentation for how to handle both modes.", vr_scope, ID_NEVER);
check_value(config.overdue_check_time_limit >= 0 ns, TB_ERROR,
"overdue_check_time_limit cannot be less than 0 ns.", vr_scope, ID_NEVER);
end procedure;
impure function entry_match_actual (
constant sb_entry : in t_sb_entry;
constant actual_element : in t_actual_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return boolean is
begin
-- If TAG then check if tag match
if tag_usage = uvvm_util.types_pkg.TAG then
if pad_string(tag, NUL, C_SB_TAG_WIDTH) /= sb_entry.tag then
return false;
end if;
end if;
return match(sb_entry.expected_element, actual_element);
end function entry_match_actual;
impure function entry_match_expected (
constant sb_entry : in t_sb_entry;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return boolean is
begin
-- If TAG then check if tag match
if tag_usage = uvvm_util.types_pkg.TAG then
if pad_string(tag, NUL, C_SB_TAG_WIDTH) /= sb_entry.tag then
return false;
end if;
end if;
return sb_entry.expected_element = expected_element;
end function entry_match_expected;
procedure log(
instance : positive;
msg_id : t_msg_id;
msg : string;
scope : string
) is
begin
if vr_msg_id_panel_array(instance)(msg_id) = ENABLED then
log(msg_id, msg, scope, C_MSG_ID_PANEL_DEFAULT);
end if;
end procedure;
--==================================================================================================
-- PUBLIC METHODS
--==================================================================================================
----------------------------------------------------------------------------------------------------
--
-- config
--
-- Sets config for each instance, by array or instance parameter
--
----------------------------------------------------------------------------------------------------
procedure config(
constant sb_config_array : in t_sb_config_array;
constant msg : in string := ""
) is
begin
-- Check if range is within limits
check_value(sb_config_array'low > 0 and sb_config_array'high <= C_MAX_QUEUE_INSTANCE_NUM, TB_ERROR,
"Configuration array must be within range 1 to C_MAX_QUEUE_INSTANCE_NUM, " & to_string(C_MAX_QUEUE_INSTANCE_NUM) & ".", vr_scope, ID_NEVER);
-- Apply config to the defined range
for i in sb_config_array'low to sb_config_array'high loop
check_config_validity(sb_config_array(i));
log(i, ID_CTRL, "config: config applied to instance " & to_string(i) & "." & add_msg_delimiter(msg), vr_scope);
vr_config(i) := sb_config_array(i);
end loop;
end procedure config;
procedure config(
constant instance : in integer;
constant sb_config : in t_sb_config;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
constant proc_name : string := "config";
begin
-- Sanity checks
check_instance_in_range(instance);
check_config_validity(sb_config);
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
log(instance, ID_CTRL, proc_name & ": config applied to instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
vr_config(instance) := sb_config;
end procedure config;
procedure config(
constant sb_config : in t_sb_config;
constant msg : in string := ""
) is
begin
config(1, sb_config, msg, "config: config applied to SB.");
end procedure config;
----------------------------------------------------------------------------------------------------
--
-- enable
--
-- Enable one instance or all instances. Counters is set froom -1 to 0 When enabled for the
-- first time.
--
----------------------------------------------------------------------------------------------------
procedure enable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
constant proc_name : string := "enable";
begin
-- Check if instance is within range
if instance /= ALL_INSTANCES then
check_instance_in_range(instance);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": all instances enabled." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, proc_name & ": instance " & to_string(instance) & " enabled." & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
if instance = ALL_INSTANCES then
vr_instance_enabled := (others => true);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_entered_cnt(i) = -1 then
vr_entered_cnt(i) := 0;
vr_match_cnt(i) := 0;
vr_mismatch_cnt(i) := 0;
vr_drop_cnt(i) := 0;
vr_initial_garbage_cnt(i) := 0;
vr_delete_cnt(i) := 0;
vr_overdue_check_cnt(i) := 0;
end if;
end loop;
else
vr_instance_enabled(instance) := true;
if vr_entered_cnt(instance) = -1 then
vr_entered_cnt(instance) := 0;
vr_match_cnt(instance) := 0;
vr_mismatch_cnt(instance) := 0;
vr_drop_cnt(instance) := 0;
vr_initial_garbage_cnt(instance) := 0;
vr_delete_cnt(instance) := 0;
vr_overdue_check_cnt(instance) := 0;
end if;
end if;
vr_sb_queue.set_scope(instance, "SB queue");
end procedure enable;
procedure enable(
constant msg : in string
) is
begin
enable(1, msg, "enable: SB enabled.");
end procedure enable;
procedure enable(
constant void : in t_void
) is
begin
enable(1, "", "enable: SB enabled.");
end procedure enable;
----------------------------------------------------------------------------------------------------
--
-- disable
--
-- Disable one instance or all instances.
--
----------------------------------------------------------------------------------------------------
procedure disable(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := "" -- not proc???
) is
begin
-- Check if instance is within range
if instance /= ALL_INSTANCES then
check_instance_in_range(instance);
end if;
if instance = ALL_INSTANCES then
vr_instance_enabled := (others => false);
else
vr_instance_enabled(instance) := false;
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC.
if instance = ALL_INSTANCES then
log(ID_CTRL, "disable: all instances disabled." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, "disable: instance " & to_string(instance) & " disabled." & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end procedure disable;
procedure disable(
constant msg : in string
) is
begin
disable(1, msg, "disable: SB disabled.");
end procedure disable;
procedure disable(
constant void : in t_void
) is
begin
disable(1, "", "disable: SB disabled.");
end procedure disable;
----------------------------------------------------------------------------------------------------
--
-- add_expected
--
-- Adds expected element at the back of queue. Optional tag and source.
--
----------------------------------------------------------------------------------------------------
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "add_expected";
variable v_sb_entry : t_sb_entry;
begin
v_sb_entry := (expected_element => expected_element,
source => pad_string(source, NUL, C_SB_SOURCE_WIDTH),
tag => pad_string(tag, NUL, C_SB_TAG_WIDTH),
entry_time => now);
if instance = ALL_ENABLED_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- add entry
vr_sb_queue.add(i, v_sb_entry);
-- increment counters
vr_entered_cnt(i) := vr_entered_cnt(i)+1;
if tag_usage = NO_TAG then
log(i, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & expected_to_string(expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(i, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & expected_to_string(expected_element) & ", tag: " & to_string(tag) &
". " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end loop;
else
-- Sanity checks
check_instance_in_range(instance);
check_instance_enabled(instance);
-- add entry
vr_sb_queue.add(instance, v_sb_entry);
-- increment counters
vr_entered_cnt(instance) := vr_entered_cnt(instance)+1;
if ext_proc_call = "" then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & expected_to_string(expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() => instance " & to_string(instance) & ", value: " & expected_to_string(expected_element) & ", tag: " & to_string(tag) &
". " & add_msg_delimiter(msg), vr_scope);
end if;
else
-- Called from other SB method
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure add_expected;
procedure add_expected(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := ""
) is
begin
if tag_usage = NO_TAG then
add_expected(1, expected_element, tag_usage, tag, msg, source, "add_expected() => expected: " & expected_to_string(expected_element) & ". ");
else
add_expected(1, expected_element, tag_usage, tag, msg, source, "add_expected() => expected: " & expected_to_string(expected_element) & ", tag: " & to_string(tag) & ". ");
end if;
end procedure add_expected;
procedure add_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant msg : in string := "";
constant source : in string := ""
) is
begin
add_expected(instance, expected_element, NO_TAG, "", msg, source);
end procedure add_expected;
procedure add_expected(
constant expected_element : in t_expected_element;
constant msg : in string := "";
constant source : in string := ""
) is
begin
add_expected(expected_element, NO_TAG, "", msg, source);
end procedure add_expected;
----------------------------------------------------------------------------------------------------
--
-- check_actual
--
-- Checks actual against expected. Updates counters acording to match/mismatch and configuration.
--
----------------------------------------------------------------------------------------------------
procedure check_actual(
constant instance : in integer;
constant actual_element : in t_actual_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "check_actual";
procedure check_pending_exists(
constant instance : in integer
) is
begin
check_value(not vr_sb_queue.is_empty(instance), TB_ERROR, "instance " & to_string(instance) & ": no pending entries to check.", vr_scope, ID_NEVER);
end procedure check_pending_exists;
procedure check_actual_instance(
constant instance : in integer
) is
variable v_matched : boolean := false;
variable v_entry : t_sb_entry;
variable v_dropped_num : natural := 0;
begin
check_pending_exists(instance);
-- If OOB
if vr_config(instance).allow_out_of_order then
-- Loop through entries in queue until match
for i in 1 to get_pending_count(instance) loop
v_entry := vr_sb_queue.peek(instance, POSITION, i);
if entry_match_actual(v_entry, actual_element, tag_usage, tag) then
v_matched := true;
-- Delete entry
vr_sb_queue.delete(instance, POSITION, i, SINGLE);
exit;
end if;
end loop;
-- If LOSSY
elsif vr_config(instance).allow_lossy then
-- Loop through entries in queue until match
for i in 1 to get_pending_count(instance) loop
v_entry := vr_sb_queue.peek(instance, POSITION, i);
if entry_match_actual(v_entry, actual_element, tag_usage, tag) then
v_matched := true;
-- Delete matching entry and preceding entries
for j in i downto 1 loop
vr_sb_queue.delete(instance, POSITION, j, SINGLE);
end loop;
v_dropped_num := i - 1;
exit;
end if;
end loop;
-- Not OOB or LOSSY
else
v_entry := vr_sb_queue.peek(instance);
if entry_match_actual(v_entry, actual_element, tag_usage, tag) then
v_matched := true;
-- delete entry
vr_sb_queue.delete(instance, POSITION, 1, SINGLE);
elsif not(vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage) then
vr_sb_queue.delete(instance, POSITION, 1, SINGLE);
end if;
end if;
-- Update counters
vr_drop_cnt(instance) := vr_drop_cnt(instance) + v_dropped_num;
if v_matched then
vr_match_cnt(instance) := vr_match_cnt(instance) + 1;
elsif vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage then
vr_initial_garbage_cnt(instance) := vr_initial_garbage_cnt(instance) + 1;
else
vr_mismatch_cnt(instance) := vr_mismatch_cnt(instance) + 1;
end if;
-- Check if overdue time
if v_matched and (vr_config(instance).overdue_check_time_limit /= 0 ns) and (now-v_entry.entry_time > vr_config(instance).overdue_check_time_limit) then
if ext_proc_call = "" then
alert(vr_config(instance).overdue_check_alert_level, proc_name & "() instance " & to_string(instance) &" => TIME LIMIT OVERDUE: time limit is "
& to_string(vr_config(instance).overdue_check_time_limit) & ", time from entry is " & to_string(now-v_entry.entry_time) & ". " & add_msg_delimiter(msg) , vr_scope);
else
alert(vr_config(instance).overdue_check_alert_level, ext_proc_call & " => TIME LIMIT OVERDUE: time limit is " & to_string(vr_config(instance).overdue_check_time_limit) &
", time from entry is " & to_string(now-v_entry.entry_time) & ". " & add_msg_delimiter(msg) , vr_scope);
end if;
-- Update counter
vr_overdue_check_cnt(instance) := vr_overdue_check_cnt(instance) + 1;
end if;
-- Logging
if v_matched then
if ext_proc_call = "" then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() instance " & to_string(instance) & " => MATCH, for value: " & expected_to_string(v_entry.expected_element) &
". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() instance " & to_string(instance) & " => MATCH, for value: " & expected_to_string(v_entry.expected_element) &
". tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
-- Called from other SB method
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, ext_proc_call & " => MATCH, for actual: " & actual_to_string(actual_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & " => MATCH, for actual: " & actual_to_string(actual_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
-- Initial garbage
elsif not(vr_match_cnt(instance) = 0 and vr_config(instance).ignore_initial_garbage) then
if ext_proc_call = "" then
if tag_usage = NO_TAG then
alert(vr_config(instance).mismatch_alert_level, proc_name & "() instance " & to_string(instance) & " => MISMATCH, expected: " & expected_to_string(v_entry.expected_element) &
"; actual: " & actual_to_string(actual_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
alert(vr_config(instance).mismatch_alert_level, proc_name & "() instance " & to_string(instance) & " => MISMATCH, expected: " & expected_to_string(v_entry.expected_element) & ", tag: '" & to_string(v_entry.tag) &
"'; actual: " & actual_to_string(actual_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
else
if tag_usage = NO_TAG then
alert(vr_config(instance).mismatch_alert_level, ext_proc_call & " => MISMATCH, expected: " & expected_to_string(v_entry.expected_element) &
"; actual: " & actual_to_string(actual_element) & add_msg_delimiter(msg), vr_scope);
else
alert(vr_config(instance).mismatch_alert_level, ext_proc_call & " => MISMATCH, expected: " & expected_to_string(v_entry.expected_element) & ", tag: " & to_string(v_entry.tag) &
"; actual: " & actual_to_string(actual_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end if;
end procedure check_actual_instance;
begin
-- Check if instance is within range
if instance /= ALL_ENABLED_INSTANCES then
check_instance_in_range(instance);
end if;
if instance = ALL_ENABLED_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
check_actual_instance(i);
end if;
end loop;
else
check_instance_enabled(instance);
check_actual_instance(instance);
end if;
end procedure check_actual;
procedure check_actual(
constant actual_element : in t_actual_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
check_actual(1, actual_element, tag_usage, tag, msg, "check_actual()");
end procedure check_actual;
procedure check_actual(
constant instance : in integer;
constant actual_element : in t_actual_element;
constant msg : in string := ""
) is
begin
check_actual(instance, actual_element, NO_TAG, "", msg);
end procedure check_actual;
procedure check_actual(
constant actual_element : in t_actual_element;
constant msg : in string := ""
) is
begin
check_actual(actual_element, NO_TAG, "", msg);
end procedure check_actual;
----------------------------------------------------------------------------------------------------
--
-- flush
--
-- Deletes all entries in queue and updates delete counter.
--
----------------------------------------------------------------------------------------------------
procedure flush(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "flush";
begin
if instance = ALL_INSTANCES then
log(ID_DATA, proc_name & ": flushing all instances." & add_msg_delimiter(msg), vr_scope);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
-- update counters
vr_delete_cnt(i) := vr_delete_cnt(i) + vr_sb_queue.get_count(i);
-- flush queue
vr_sb_queue.flush(i);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
log(ID_DATA, proc_name & ": flushing all enabled instances." & add_msg_delimiter(msg), vr_scope);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- update counters
vr_delete_cnt(i) := vr_delete_cnt(i) + vr_sb_queue.get_count(i);
-- flush queue
vr_sb_queue.flush(i);
end if;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": flushing instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
check_instance_in_range(instance);
check_instance_enabled(instance);
-- update counters
vr_delete_cnt(instance) := vr_delete_cnt(instance) + vr_sb_queue.get_count(instance);
-- flush queue
vr_sb_queue.flush(instance);
end if;
end procedure flush;
procedure flush(
constant msg : in string
) is
begin
flush(1, msg, "flush: flushing SB.");
end procedure flush;
procedure flush(
constant void : in t_void
) is
begin
flush("");
end procedure flush;
----------------------------------------------------------------------------------------------------
--
-- reset
--
-- Resets all counters and flushes queue. Also resets entry number count.
--
----------------------------------------------------------------------------------------------------
procedure reset(
constant instance : in integer;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "reset";
procedure reset_instance(
constant instance : positive
) is
begin
vr_sb_queue.reset(instance);
vr_entered_cnt(instance) := 0;
vr_match_cnt(instance) := 0;
vr_mismatch_cnt(instance) := 0;
vr_drop_cnt(instance) := 0;
vr_initial_garbage_cnt(instance) := 0;
vr_delete_cnt(instance) := 0;
vr_overdue_check_cnt(instance) := 0;
end procedure reset_instance;
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": reseting all instances. " & add_msg_delimiter(msg), vr_scope);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
reset_instance(i);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
log(ID_CTRL, proc_name & ": reseting all enabled instances. " & add_msg_delimiter(msg), vr_scope);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
reset_instance(i);
end if;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": reseting instance " & to_string(instance) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
check_instance_in_range(instance);
check_instance_enabled(instance);
reset_instance(instance);
end if;
end procedure reset;
procedure reset(
constant msg : in string
) is
begin
reset(1, msg, "reset: reseting SB.");
end procedure reset;
procedure reset(
constant void : in t_void
) is
begin
reset("");
end procedure reset;
----------------------------------------------------------------------------------------------------
--
-- is_empty
--
-- Returns true if scoreboard instance is empty, false if not.
--
----------------------------------------------------------------------------------------------------
impure function is_empty(
constant instance : in integer
) return boolean is
begin
return vr_sb_queue.is_empty(instance);
end function is_empty;
impure function is_empty(
constant void : in t_void
) return boolean is
begin
return is_empty(1);
end function is_empty;
----------------------------------------------------------------------------------------------------
--
-- get_entered_count
--
-- Returns total number of entries made to scoreboard instance.
-- Added + inserted.
--
----------------------------------------------------------------------------------------------------
impure function get_entered_count(
constant instance : in integer
) return integer is
begin
return vr_entered_cnt(instance);
end function get_entered_count;
impure function get_entered_count(
constant void : in t_void
) return integer is
begin
return get_entered_count(1);
end function get_entered_count;
----------------------------------------------------------------------------------------------------
--
-- get_pending_count
--
-- Returns number of entries en scoreboard instance at the moment.
-- Added + inserted - checked - deleted.
--
----------------------------------------------------------------------------------------------------
impure function get_pending_count(
constant instance : in integer
) return integer is
begin
if vr_entered_cnt(instance) = -1 then
return -1;
else
return vr_sb_queue.get_count(instance);
end if;
end function get_pending_count;
impure function get_pending_count(
constant void : in t_void
) return integer is
begin
return get_pending_count(1);
end function get_pending_count;
----------------------------------------------------------------------------------------------------
--
-- get_match_count
--
-- Returns number of entries checked and matched against an actual.
--
----------------------------------------------------------------------------------------------------
impure function get_match_count(
constant instance : in integer
) return integer is
begin
return vr_match_cnt(instance);
end function get_match_count;
impure function get_match_count(
constant void : in t_void
) return integer is
begin
return get_match_count(1);
end function get_match_count;
----------------------------------------------------------------------------------------------------
--
-- get_mismatch_count
--
-- Returns number of entries checked and not matched against an actual.
--
----------------------------------------------------------------------------------------------------
impure function get_mismatch_count(
constant instance : in integer
) return integer is
begin
return vr_mismatch_cnt(instance);
end function get_mismatch_count;
impure function get_mismatch_count(
constant void : in t_void
) return integer is
begin
return get_mismatch_count(1);
end function get_mismatch_count;
----------------------------------------------------------------------------------------------------
--
-- get_drop_count
--
-- Returns number of entries dropped, total number of preceding entries before match.
-- Only relevant during lossy mode.
--
----------------------------------------------------------------------------------------------------
impure function get_drop_count(
constant instance : in integer
) return integer is
begin
return vr_drop_cnt(instance);
end function get_drop_count;
impure function get_drop_count(
constant void : in t_void
) return integer is
begin
return get_drop_count(1);
end function get_drop_count;
----------------------------------------------------------------------------------------------------
--
-- get_initial_garbage_count
--
-- Returns number of actuals checked before first match.
-- Only relevant when allow_initial_garbage is enabled.
--
----------------------------------------------------------------------------------------------------
impure function get_initial_garbage_count(
constant instance : in integer
) return integer is
begin
return vr_initial_garbage_cnt(instance);
end function get_initial_garbage_count;
impure function get_initial_garbage_count(
constant void : in t_void
) return integer is
begin
return get_initial_garbage_count(1);
end function get_initial_garbage_count;
----------------------------------------------------------------------------------------------------
--
-- get_delete_count
--
-- Returns number of deleted entries.
-- Delete + fetch + flush.
--
----------------------------------------------------------------------------------------------------
impure function get_delete_count(
constant instance : in integer
) return integer is
begin
return vr_delete_cnt(instance);
end function get_delete_count;
impure function get_delete_count(
constant void : in t_void
) return integer is
begin
return get_delete_count(1);
end function get_delete_count;
----------------------------------------------------------------------------------------------------
--
-- get_overdue_check_count
--
-- Returns number of actuals checked when time limit is overdue.
-- Only relevant when overdue_check_time_limit is set.
--
----------------------------------------------------------------------------------------------------
impure function get_overdue_check_count(
constant instance : in integer
) return integer is
begin
return vr_overdue_check_cnt(instance);
end function get_overdue_check_count;
impure function get_overdue_check_count(
constant void : in t_void
) return integer is
begin
return get_overdue_check_count(1);
end function get_overdue_check_count;
----------------------------------------------------------------------------------------------------
--
-- set_scope / get_scope
--
-- Set/Get the scope of the scoreboard.
--
----------------------------------------------------------------------------------------------------
procedure set_scope(
constant scope : in string
) is
begin
vr_scope := pad_string(scope, NUL, C_LOG_SCOPE_WIDTH);
end procedure set_scope;
impure function get_scope(
constant void : in t_void
) return string is
begin
return vr_scope;
end function get_scope;
----------------------------------------------------------------------------------------------------
--
-- enable_log_msg
--
-- Enables the specified message id for the instance.
--
----------------------------------------------------------------------------------------------------
procedure enable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "enable_log_msg";
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " enabled for all instances", vr_scope);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
vr_msg_id_panel_array(i)(msg_id) := ENABLED;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " enabled for instance " & to_string(instance), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call, vr_scope);
end if;
vr_msg_id_panel_array(instance)(msg_id) := ENABLED;
end if;
end procedure enable_log_msg;
procedure enable_log_msg(
constant msg_id : in t_msg_id
) is
begin
enable_log_msg(1, msg_id, "enable_log_msg: "& ": message id " & to_string(msg_id) & " enabled");
end procedure enable_log_msg;
----------------------------------------------------------------------------------------------------
--
-- disable_log_msg
--
-- Disables the specified message id for the instance.
--
----------------------------------------------------------------------------------------------------
procedure disable_log_msg(
constant instance : in integer;
constant msg_id : in t_msg_id;
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "disable_log_msg";
begin
if instance = ALL_INSTANCES then
log(ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " disabled for all instances", vr_scope);
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
vr_msg_id_panel_array(i)(msg_id) := DISABLED;
end loop;
else
if ext_proc_call = "" then
log(instance, ID_CTRL, proc_name & ": message id " & to_string(msg_id) & " disabled for instance " & to_string(instance), vr_scope);
else
log(instance, ID_CTRL, ext_proc_call, vr_scope);
end if;
vr_msg_id_panel_array(instance)(msg_id) := DISABLED;
end if;
end procedure disable_log_msg;
procedure disable_log_msg(
constant msg_id : in t_msg_id
) is
begin
disable_log_msg(1, msg_id, "disable_log_msg: "& ": message id " & to_string(msg_id) & " disabled");
end procedure disable_log_msg;
----------------------------------------------------------------------------------------------------
--
-- report_conters
--
-- Prints a report of all counters to transcript for either specified instance, all enabled
-- instances or all instances.
--
----------------------------------------------------------------------------------------------------
procedure report_counters(
constant instance : in integer;
constant ext_proc_call : in string := ""
) is
variable v_line : line;
variable v_line_copy : line;
variable v_status_failed : boolean := true;
variable v_mismatch : boolean := false;
constant C_HEADER : string := "*** SCOREBOARD COUNTERS SUMMARY: " & to_string(vr_scope) & " ***";
constant prefix : string := C_LOG_PREFIX & " ";
constant log_counter_width : positive := 15;
begin
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
justify(C_HEADER, center, C_LOG_LINE_WIDTH - prefix'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
write(v_line,
justify(
justify("ENTERED", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("PENDING", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("MATCH", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("MISMATCH", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("DROP", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("INITIAL_GARBAGE", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("DELETE", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("OVERDUE CHECK", center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE),
center, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
if instance = ALL_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
write(v_line,
justify(
fill_string(' ', 4) &
"instance: " &
justify(to_string(i), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_pending_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_match_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_mismatch_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_drop_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_initial_garbage_count(i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_delete_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_overdue_check_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20),
center, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end loop;
elsif instance = ALL_ENABLED_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
write(v_line,
justify(
fill_string(' ', 4) &
"instance: " &
justify(to_string(i), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_pending_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_match_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_mismatch_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_drop_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_initial_garbage_count(i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_delete_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_overdue_check_count( i)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20),
center, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
elsif ext_proc_call = "" then
write(v_line,
justify(
fill_string(' ', 4) &
"instance: " &
justify(to_string(instance), right, to_string(C_MAX_QUEUE_INSTANCE_NUM)'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20-4-10-to_string(C_MAX_QUEUE_INSTANCE_NUM)'length) &
justify(to_string(get_entered_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_pending_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_match_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_mismatch_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_drop_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_initial_garbage_count(instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_delete_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_overdue_check_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
fill_string(' ', 20),
center, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
else
write(v_line,
justify(
justify(to_string(get_entered_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_pending_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_match_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_mismatch_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_drop_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_initial_garbage_count(instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_delete_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify(to_string(get_overdue_check_count( instance)), center, log_counter_width, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE),
center, C_LOG_LINE_WIDTH - prefix'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to transcript
writeline(OUTPUT, v_line);
end procedure report_counters;
procedure report_counters(
constant void : in t_void
) is
begin
report_counters(1, "no instance label");
end procedure report_counters;
--==================================================================================================
-- ADVANCED METHODS
--==================================================================================================
----------------------------------------------------------------------------------------------------
--
-- insert_expected
--
-- Inserts expected element to the queue based on position or entry number
--
----------------------------------------------------------------------------------------------------
procedure insert_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "insert_expected";
variable v_sb_entry : t_sb_entry;
begin
-- Check if instance is within range
if instance /= ALL_ENABLED_INSTANCES then
check_instance_in_range(instance);
end if;
v_sb_entry := (expected_element => expected_element,
source => pad_string(source, NUL, C_SB_SOURCE_WIDTH),
tag => pad_string(tag, NUL, C_SB_TAG_WIDTH),
entry_time => now);
if instance = ALL_ENABLED_INSTANCES then
for i in 1 to C_MAX_QUEUE_INSTANCE_NUM loop
if vr_instance_enabled(i) then
-- Check that instance is enabled
check_queue_empty(instance);
-- add entry
vr_sb_queue.insert(i, identifier_option, identifier, v_sb_entry);
-- increment counters
vr_entered_cnt(i) := vr_entered_cnt(i)+1;
end if;
end loop;
else
-- Check that instance is in valid range and enabled
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- add entry
vr_sb_queue.insert(instance, identifier_option, identifier, v_sb_entry);
-- increment counters
vr_entered_cnt(instance) := vr_entered_cnt(instance)+1;
end if;
-- Logging
if ext_proc_call = "" then
if instance = ALL_ENABLED_INSTANCES then
if identifier_option = POSITION then
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for all enabled instances. Expected: "
& expected_to_string(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for all enabled instances. Expected: "
& expected_to_string(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for all enabled instances. Expected: "
& expected_to_string(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for all enabled instances. Expected: "
& expected_to_string(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
else
if identifier_option = POSITION then
log(instance, ID_DATA, proc_name & "() inserted expected after entry with position " & to_string(identifier) & " for instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & "() inserted expected after entry with entry number " & to_string(identifier) & " for instance " & to_string(instance) & "." & add_msg_delimiter(msg), vr_scope);
end if;
end if;
else
if tag_usage = NO_TAG then
log(instance, ID_DATA, ext_proc_call & " Expected: " & expected_to_string(expected_element) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & " Expected: " & expected_to_string(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure insert_expected;
procedure insert_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant source : in string := ""
) is
begin
if identifier_option = POSITION then
insert_expected(1, identifier_option, identifier, expected_element, tag_usage, tag, msg, source, "insert_expected() inserted expected after entry with position " & to_string(identifier) & ".");
else
insert_expected(1, identifier_option, identifier, expected_element, tag_usage, tag, msg, source, "insert_expected() inserted expected after entry with entry number " & to_string(identifier) & ".");
end if;
end procedure insert_expected;
----------------------------------------------------------------------------------------------------
--
-- find_expected_entry_num
--
-- Returns entry number of matching entry, no match returns -1
--
----------------------------------------------------------------------------------------------------
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if entry_match_expected(v_sb_entry, expected_element, tag_usage, tag) then
return vr_sb_queue.get_entry_num(instance, i);
end if;
end loop;
return -1;
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_entry_num(1, expected_element, tag_usage, tag);
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant instance : in integer;
constant expected_element : in t_expected_element
) return integer is
begin
return find_expected_entry_num(instance, expected_element, NO_TAG, "");
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant expected_element : in t_expected_element
) return integer is
begin
return find_expected_entry_num(1, expected_element, NO_TAG, "");
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if v_sb_entry.tag = pad_string(tag, NUL, C_SB_TAG_WIDTH) then
return vr_sb_queue.get_entry_num(instance, i);
end if;
end loop;
return -1;
end function find_expected_entry_num;
impure function find_expected_entry_num(
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_entry_num(1, tag_usage, tag);
end function find_expected_entry_num;
----------------------------------------------------------------------------------------------------
--
-- find_expected_position
--
-- Returns position of matching entry, no match returns -1
--
----------------------------------------------------------------------------------------------------
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if entry_match_expected(v_sb_entry, expected_element, tag_usage, tag) then
return i;
end if;
end loop;
return -1;
end function find_expected_position;
impure function find_expected_position(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_position(1, expected_element, tag_usage, tag);
end function find_expected_position;
impure function find_expected_position(
constant instance : in integer;
constant expected_element : in t_expected_element
) return integer is
begin
return find_expected_position(instance, expected_element, NO_TAG, "");
end function find_expected_position;
impure function find_expected_position(
constant expected_element : in t_expected_element
) return integer is
begin
return find_expected_position(1, expected_element, NO_TAG, "");
end function find_expected_position;
impure function find_expected_position(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
for i in 1 to get_pending_count(instance) loop
-- get entry i
v_sb_entry := vr_sb_queue.peek(instance, POSITION, i);
-- check if match
if v_sb_entry.tag = pad_string(tag, NUL, C_SB_TAG_WIDTH) then
return i;
end if;
end loop;
return -1;
end function find_expected_position;
impure function find_expected_position(
constant tag_usage : in t_tag_usage;
constant tag : in string
) return integer is
begin
return find_expected_position(1, tag_usage, tag);
end function find_expected_position;
----------------------------------------------------------------------------------------------------
--
-- delete_expected
--
-- Deletes expected element in queue based on specified element, position or entry number
--
----------------------------------------------------------------------------------------------------
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
variable v_position : integer;
begin
-- Sanity checks done in find_expected_position
v_position := find_expected_position(instance, expected_element, tag_usage, tag);
if v_position /= -1 then
vr_sb_queue.delete(instance, POSITION, v_position, SINGLE);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", value: " & expected_to_string(expected_element) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
end if;
end procedure delete_expected;
procedure delete_expected(
constant expected_element : in t_expected_element;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
delete_expected(1, expected_element, tag_usage, tag, msg, "delete_expected: value: " & expected_to_string(expected_element) & ", tag: '" & to_string(tag) & "'. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant expected_element : in t_expected_element;
constant msg : in string := ""
) is
begin
delete_expected(instance, expected_element, NO_TAG, "", msg, "delete_expected: instance " & to_string(instance) & ", value: " & expected_to_string(expected_element) & ". ");
end procedure delete_expected;
procedure delete_expected(
constant expected_element : in t_expected_element;
constant msg : in string := ""
) is
begin
delete_expected(1, expected_element, NO_TAG, "", msg, "delete_expected: instance value: " & expected_to_string(expected_element) & ". ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
variable v_position : integer;
begin
-- Sanity checks done in find_expected_position
v_position := find_expected_position(instance, tag_usage, tag);
if v_position /= -1 then
vr_sb_queue.delete(instance, POSITION, v_position, SINGLE);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", tag: '" & to_string(tag) & "'. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
end if;
end procedure delete_expected;
procedure delete_expected(
constant tag_usage : in t_tag_usage;
constant tag : in string;
constant msg : in string := ""
) is
begin
delete_expected(1, tag_usage, tag, msg, "delete_expected: tag: '" & to_string(tag) & "'. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
constant C_PRE_DELETE_PENDING_CNT : natural := vr_sb_queue.get_count(instance);
variable v_num_deleted : natural;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- Delete entries
vr_sb_queue.delete(instance, identifier_option, identifier_min, identifier_max);
v_num_deleted := C_PRE_DELETE_PENDING_CNT - vr_sb_queue.get_count(instance);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + v_num_deleted;
-- If error
if v_num_deleted = 0 then
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
else
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier_min) & " to " & to_string(identifier_max) & " deleted. " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure delete_expected;
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive;
constant msg : in string := ""
) is
begin
delete_expected(1, identifier_option, identifier_min, identifier_max, msg, "delete_expected: entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier_min) & " to " & to_string(identifier_max) & " deleted. ");
end procedure delete_expected;
procedure delete_expected(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := "";
constant ext_proc_call : in string := ""
) is
constant proc_name : string := "delete_expected";
constant C_PRE_DELETE_PENDING_CNT : natural := vr_sb_queue.get_count(instance);
variable v_num_deleted : natural;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
-- Delete entries
vr_sb_queue.delete(instance, identifier_option, identifier, range_option);
v_num_deleted := C_PRE_DELETE_PENDING_CNT - vr_sb_queue.get_count(instance);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + v_num_deleted;
-- If error
if v_num_deleted = 0 then
log(instance, ID_DATA, proc_name & ": NO DELETION. Did not find matching entry. " & add_msg_delimiter(msg), vr_scope);
else
if ext_proc_call = "" then
if range_option = SINGLE then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entry with identifier " & to_string(identifier_option) &
" " & to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", entries with identifier " & to_string(identifier_option) &
" range " & to_string(identifier) & " " & to_string(range_option) & " deleted. " & add_msg_delimiter(msg), vr_scope);
end if;
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
end if;
end procedure delete_expected;
procedure delete_expected(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option;
constant msg : in string := ""
) is
begin
if range_option = SINGLE then
delete_expected(1, identifier_option, identifier, range_option, msg, "delete_expected: entry with identifier '" & to_string(identifier_option) &
" " & to_string(identifier) & " deleted. ");
else
delete_expected(1, identifier_option, identifier, range_option, msg, "delete_expected: entries with identifier '" & to_string(identifier_option) &
" range " & to_string(identifier) & " to " & to_string(range_option) & " deleted. ");
end if;
end procedure delete_expected;
----------------------------------------------------------------------------------------------------
-- non public local_entry
-- Used by all peek functions
----------------------------------------------------------------------------------------------------
impure function peek_entry(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_sb_entry is
begin
-- Check that instance is in valid range and enabled
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
return vr_sb_queue.peek(instance, identifier_option, identifier);
end function peek_entry;
----------------------------------------------------------------------------------------------------
--
-- peek_expected
--
-- Returns expected element from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_expected_element is
begin
return peek_entry(instance, identifier_option, identifier).expected_element;
end function peek_expected;
impure function peek_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_expected_element is
begin
return peek_entry(1, identifier_option, identifier).expected_element;
end function peek_expected;
impure function peek_expected(
constant instance : integer
) return t_expected_element is
begin
return peek_entry(instance, POSITION, 1).expected_element;
end function peek_expected;
impure function peek_expected(
constant void : t_void
) return t_expected_element is
begin
return peek_entry(1, POSITION, 1).expected_element;
end function peek_expected;
----------------------------------------------------------------------------------------------------
--
-- peek_source
--
-- Returns source element from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return to_string(peek_entry(instance, identifier_option, identifier).source);
end function peek_source;
impure function peek_source(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return peek_source(1, identifier_option, identifier);
end function peek_source;
impure function peek_source(
constant instance : integer
) return string is
begin
return peek_source(instance, POSITION, 1);
end function peek_source;
impure function peek_source(
constant void : t_void
) return string is
begin
return peek_source(1, POSITION, 1);
end function peek_source;
----------------------------------------------------------------------------------------------------
--
-- peek_tag
--
-- Returns tag from queue entry based on position or entry number without deleting entry
--
----------------------------------------------------------------------------------------------------
impure function peek_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return to_string(peek_entry(instance, identifier_option, identifier).tag);
end function peek_tag;
impure function peek_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive
) return string is
begin
return peek_tag(1, identifier_option, identifier);
end function peek_tag;
impure function peek_tag(
constant instance : integer
) return string is
begin
return peek_tag(instance, POSITION, 1);
end function peek_tag;
impure function peek_tag(
constant void : t_void
) return string is
begin
return peek_tag(1, POSITION, 1);
end function peek_tag;
----------------------------------------------------------------------------------------------------
-- Non public fetch_entry
-- Used by all fetch functions
----------------------------------------------------------------------------------------------------
impure function fetch_entry(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive
) return t_sb_entry is
variable v_sb_entry : t_sb_entry;
begin
-- Sanity check
check_instance_in_range(instance);
check_instance_enabled(instance);
check_queue_empty(instance);
v_sb_entry := vr_sb_queue.fetch(instance, identifier_option, identifier);
vr_delete_cnt(instance) := vr_delete_cnt(instance) + 1;
return v_sb_entry;
end function fetch_entry;
----------------------------------------------------------------------------------------------------
--
-- fetch_expected
--
-- Returns expected element from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_expected(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return t_expected_element is
constant proc_name : string := "fetch_expected";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching expected by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return fetch_entry(instance, identifier_option, identifier).expected_element;
end function fetch_expected;
impure function fetch_expected(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return t_expected_element is
begin
return fetch_expected(1, identifier_option, identifier, msg, "fetch_expected: fetching expected by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_expected;
impure function fetch_expected(
constant instance : integer;
constant msg : string := ""
) return t_expected_element is
begin
return fetch_expected(instance, POSITION, 1, msg);
end function fetch_expected;
impure function fetch_expected(
constant msg : string
) return t_expected_element is
begin
return fetch_expected(POSITION, 1, msg);
end function fetch_expected;
impure function fetch_expected(
constant void : t_void
) return t_expected_element is
begin
return fetch_expected(POSITION, 1);
end function fetch_expected;
----------------------------------------------------------------------------------------------------
--
-- fetch_source
--
-- Returns source element from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_source(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return string is
constant proc_name : string := "fetch_source";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching source by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return to_string(fetch_entry(instance, identifier_option, identifier).source);
end function fetch_source;
impure function fetch_source(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return string is
begin
return fetch_source(1, identifier_option, identifier, msg, "fetch_source: fetching source by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_source;
impure function fetch_source(
constant instance : integer;
constant msg : string := ""
) return string is
begin
return fetch_source(instance, POSITION, 1, msg);
end function fetch_source;
impure function fetch_source(
constant msg : string
) return string is
begin
return fetch_source(POSITION, 1, msg);
end function fetch_source;
impure function fetch_source(
constant void : t_void
) return string is
begin
return fetch_source(POSITION, 1);
end function fetch_source;
----------------------------------------------------------------------------------------------------
--
-- fetch_tag
--
-- Returns tag from queue entry based on position or entry number and deleting entry
--
----------------------------------------------------------------------------------------------------
impure function fetch_tag(
constant instance : integer;
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := "";
constant ext_proc_call : string := ""
) return string is
constant proc_name : string := "fetch_tag";
begin
-- Sanity checks in fetch entry
-- Logging
if ext_proc_call = "" then
log(instance, ID_DATA, proc_name & ": instance " & to_string(instance) & ", fetching tag by " & to_string(identifier_option) & " " &
to_string(identifier) & ". " & add_msg_delimiter(msg), vr_scope);
else
log(instance, ID_DATA, ext_proc_call & add_msg_delimiter(msg), vr_scope);
end if;
return to_string(fetch_entry(instance, identifier_option, identifier).tag);
end function fetch_tag;
impure function fetch_tag(
constant identifier_option : t_identifier_option;
constant identifier : positive;
constant msg : string := ""
) return string is
begin
return fetch_tag(1, identifier_option, identifier, msg, "fetch_tag: fetching tag by " &
to_string(identifier_option) & " " & to_string(identifier) & ". ");
end function fetch_tag;
impure function fetch_tag(
constant instance : integer;
constant msg : string := ""
) return string is
begin
return fetch_tag(instance, POSITION, 1, msg);
end function fetch_tag;
impure function fetch_tag(
constant msg : string
) return string is
begin
return fetch_tag(POSITION, 1, msg);
end function fetch_tag;
impure function fetch_tag(
constant void : t_void
) return string is
begin
return fetch_tag(POSITION, 1);
end function fetch_tag;
----------------------------------------------------------------------------------------------------
--
-- exists
--
-- Returns true if entry exists, false if not.
--
----------------------------------------------------------------------------------------------------
impure function exists(
constant instance : integer;
constant expected_element : t_expected_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := ""
) return boolean is
begin
return (find_expected_position(instance, expected_element, tag_usage, tag) /= C_NO_MATCH);
end function exists;
impure function exists(
constant expected_element : t_expected_element;
constant tag_usage : t_tag_usage := NO_TAG;
constant tag : string := ""
) return boolean is
begin
return exists(1, expected_element, tag_usage, tag);
end function exists;
impure function exists(
constant instance : integer;
constant tag_usage : t_tag_usage;
constant tag : string
) return boolean is
begin
return (find_expected_position(instance, tag_usage, tag) /= C_NO_MATCH);
end function exists;
impure function exists(
constant tag_usage : t_tag_usage;
constant tag : string
) return boolean is
begin
return exists(1, tag_usage, tag);
end function exists;
end protected body;
end package body generic_sb_pkg; | mit | 74d4140bc46e30fff1b00a299865878d | 0.552619 | 4.391302 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/Shadow_Register_tb.vhd | 2 | 2,850 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:12:55 04/13/2016
-- Design Name:
-- Module Name: /home/tj/Desktop/UMD_RISC-16G5/ProjectLab2/Shadow_Register/Lab04/Shadow_Register_tb.vhd
-- Project Name: Lab04
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Shadow_Reg
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Shadow_Register_tb IS
END Shadow_Register_tb;
ARCHITECTURE behavior OF Shadow_Register_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Shadow_Reg
PORT(
RAddr : IN std_logic_vector(1 downto 0);
CLK : IN std_logic;
RST : IN std_logic;
R : IN std_logic;
W : IN std_logic;
RAout : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal RAddr : std_logic_vector(1 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal R : std_logic := '0';
signal W : std_logic := '0';
--Outputs
signal RAout : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 1 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Shadow_Reg PORT MAP (
RAddr => RAddr,
CLK => CLK,
RST => RST,
R => R,
W => W,
RAout => RAout
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*2;
wait for CLK_period/2;
RST <= '0';
-- insert stimulus here
wait for CLK_period/2;
R <= '1';
--wait for CLK_period;
RAddr <= "00";
wait for CLK_period;
RAddr <= "01";
wait for CLK_period;
RAddr <= "10";
wait for CLK_period;
RAddr <= "11";
wait for CLK_period*10;
wait;
end process;
END;
| gpl-3.0 | 087b2ba89c232b0a0279e5380d80e9b4 | 0.570877 | 3.677419 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_log/flt_log_rnd.vhd | 3 | 10,757 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6224)
`protect data_block
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`protect end_protected
| gpl-2.0 | 175368085e60996df8e94dc7b03ea9dd | 0.926559 | 1.886531 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd | 11 | 20,893 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
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`protect end_protected
| gpl-2.0 | 8d577b630ba16ab952aca190151f1d1a | 0.941272 | 1.84128 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/fp_shift_ram_clr_op.vhd | 2 | 10,347 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| gpl-2.0 | 275b55e2907f487870661c8251f79d2e | 0.925389 | 1.896097 | false | false | false | false |
amerryfellow/dlx | alu/testbench.vhd | 1 | 1,351 | library IEEE;
use std.textio.all;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
use WORK.alu_types.all;
entity TBALU is
end TBALU;
architecture ALU_TEST of TBALU is
constant NBIT: integer := NSUMG;
signal FUNC_CODE: TYPE_OP:=ADD;
signal CLK: std_logic:='0';
signal RESET: std_logic;
signal OP1: STD_LOGIC_VECTOR(NBIT-1 downto 0);
signal OP2: STD_LOGIC_VECTOR(NBIT-1 downto 0);
signal RESULT: STD_LOGIC_VECTOR(NBIT-1 downto 0);
component ALU
generic (
N : integer := NSUMG
);
port (
FUNC: in TYPE_OP;
A, B: in std_logic_vector(N-1 downto 0);
CLK: in std_logic;
RESET: in std_logic;
OUTALU: out std_logic_vector(N-1 downto 0)
);
end component;
begin
p_clock: process (CLK)
begin -- process p_clock
CLK <= not(CLK) after 2 ns;
end process p_clock;
RESET <= '1', '0' after 1 ns;
U1 : ALU
generic map (NBIT)
port map (FUNC_CODE, OP1, OP2,CLK, RESET, RESULT);
OP1 <= "00000000000000000000000000110101";
OP2 <= "00000000000000000000000000010110";
FUNC_CODE <=
ADD after 8 ns,
SUBT after 16 ns,
--MULT after 24 ns,
BITAND after 32 ns,
BITOR after 40 ns,
BITXOR after 48 ns,
FUNCSLL after 56 ns,
FUNCSRL after 64 ns,
FUNCSRA after 72 ns,
COMP after 80 ns;
end ALU_TEST;
| gpl-3.0 | 3f63771512389826a2ba6e2cbf4d49bb | 0.629904 | 2.762781 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_2/part_5/ip/clk_video/clk_video_funcsim.vhdl | 1 | 7,960 | -- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Thu Mar 20 14:12:08 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/clk_video/clk_video_funcsim.vhdl
-- Design : clk_video
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_videoclk_video_clk_wiz is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_videoclk_video_clk_wiz;
architecture STRUCTURE of clk_videoclk_video_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_video : STD_LOGIC;
signal clk_193MHz_clk_video : STD_LOGIC;
signal clkfbout_buf_clk_video : STD_LOGIC;
signal clkfbout_clk_video : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute box_type of clkin1_bufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_video,
O => clkfbout_buf_clk_video
);
clkin1_bufg: unisim.vcomponents.BUFG
port map (
I => clk_100MHz,
O => clk_100MHz_clk_video
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_193MHz_clk_video,
O => clk_193MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 45.875000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 4.750000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_video,
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_video : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_video : entity is "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_video;
architecture STRUCTURE of clk_video is
begin
U0: entity work.clk_videoclk_video_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_193MHz => clk_193MHz,
locked => locked
);
end STRUCTURE;
| gpl-2.0 | 9c1e6ac1f181174c7f839667503305c6 | 0.623618 | 3.285184 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/fir_lp_54kHz/fir_compiler_v7_1/hdl/transpose_decimation.vhd | 8 | 151,985 | `protect begin_protected
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| gpl-2.0 | 13c495112d9c487fdd6a7b1d1704f0e9 | 0.954864 | 1.812798 | false | false | false | false |
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| mit | dd1f99429549901a2b1c11edb427b917 | 0.922348 | 1.90042 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/ipcore_dir/DEBUG_RAM/simulation/DEBUG_RAM_tb.vhd | 3 | 4,523 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: DEBUG_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY DEBUG_RAM_tb IS
END ENTITY;
ARCHITECTURE DEBUG_RAM_tb_ARCH OF DEBUG_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
DEBUG_RAM_synth_inst:ENTITY work.DEBUG_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | 972d37f037bda76e02585566311238dc | 0.615742 | 4.587221 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/r2_datapath.vhd | 2 | 50,615 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | c4183113b781dac15b567de4c95f6088 | 0.949323 | 1.823964 | false | false | false | false |
UVVM/uvvm_vvc_framework | bitvis_vip_uart/src/vvc_context.vhd | 1 | 1,440 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_uart;
use bitvis_vip_uart.uart_bfm_pkg.all;
use bitvis_vip_uart.vvc_cmd_pkg.all;
use bitvis_vip_uart.vvc_methods_pkg.all;
use bitvis_vip_uart.td_vvc_framework_common_methods_pkg.all;
end context; | mit | e6c70a6530fb2725f6be45a90d3ecf16 | 0.532639 | 5.333333 | false | false | false | false |
UVVM/UVVM_All | uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd | 1 | 40,949 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_protected_types_pkg.all;
package ti_vvc_framework_support_pkg is
--constant C_VVC_NAME_MAX_LENGTH : natural := 20;
constant C_VVC_NAME_MAX_LENGTH : natural := C_MAX_VVC_NAME_LENGTH;
------------------------------------------------------------------------
-- Common support types for UVVM
------------------------------------------------------------------------
type t_immediate_or_queued is (NO_command_type, IMMEDIATE, QUEUED);
type t_flag_record is record
set : std_logic;
reset : std_logic;
is_active : std_logic;
end record;
type t_uvvm_state is (IDLE, PHASE_A, PHASE_B, INIT_COMPLETED);
type t_lastness is (LAST, NOT_LAST);
type t_broadcastable_cmd is (NO_CMD, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, INSERT_DELAY, AWAIT_COMPLETION, TERMINATE_CURRENT_COMMAND);
constant C_BROADCAST_CMD_STRING_MAX_LENGTH : natural := 300;
type t_vvc_broadcast_cmd_record is record
operation : t_broadcastable_cmd;
msg_id : t_msg_id;
msg : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
proc_call : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
quietness : t_quietness;
delay : time;
timeout : time;
gen_integer : integer;
end record;
constant C_VVC_BROADCAST_CMD_DEFAULT : t_vvc_broadcast_cmd_record := (
operation => NO_CMD,
msg_id => NO_ID,
msg => (others => NUL),
proc_call => (others => NUL),
quietness => NON_QUIET,
delay => 0 ns,
timeout => 0 ns,
gen_integer => -1
);
------------------------------------------------------------------------
-- Common signals for acknowledging a pending command
------------------------------------------------------------------------
shared variable shared_vvc_broadcast_cmd : t_vvc_broadcast_cmd_record := C_VVC_BROADCAST_CMD_DEFAULT;
signal VVC_BROADCAST : std_logic := 'L';
------------------------------------------------------------------------
-- Common signals for triggering VVC activity in central VVC register
------------------------------------------------------------------------
signal global_trigger_vvc_activity_register : std_logic := 'L';
------------------------------------------------------------------------
-- Common signal for signalling between VVCs, used during await_any_completion()
-- Default (when not active): Z
-- Awaiting: 1:
-- Completed: 0
-- This signal is a vector to support multiple sequencers calling await_any_completion simultaneously:
-- - When calling await_any_completion, each sequencer specifies which bit in this global signal the VVCs shall use.
------------------------------------------------------------------------
signal global_awaiting_completion : std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0); -- ACK on global triggers
------------------------------------------------------------------------
-- Shared variables for UVVM framework
------------------------------------------------------------------------
shared variable shared_cmd_idx : integer := 0;
shared variable shared_uvvm_state : t_uvvm_state := IDLE;
-------------------------------------------
-- flag_handler
-------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
);
-------------------------------------------
-- set_flag
-------------------------------------------
-- Sets reset and is_active to 'Z' and pulses set_flag
procedure set_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- reset_flag
-------------------------------------------
-- Sets set and is_active to 'Z' and pulses reset_flag
procedure reset_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- await_uvvm_initialization
-------------------------------------------
-- Waits until uvvm has been initialized
procedure await_uvvm_initialization(
constant dummy : in t_void
);
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Converts the command index to string, enclused by
-- C_CMD_IDX_PREFIX and C_CMD_IDX_SUFFIX
impure function format_command_idx(
command_idx : integer
) return string;
--***********************************************
-- BROADCAST COMMANDS
--***********************************************
-------------------------------------------
-- enable_log_msg (Broadcast)
-------------------------------------------
-- Enables a log message for all VVCs
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- disable_log_msg (Broadcast)
-------------------------------------------
-- Disables a log message for all VVCs
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- flush_command_queue (Broadcast)
-------------------------------------------
-- Flushes the command queue for all VVCs
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as number of clock cycles)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as time)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- await_completion (Broadcast)
-------------------------------------------
-- Wait for all VVCs to finish (specified as time)
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- terminate_current_command (Broadcast)
-------------------------------------------
-- terminates all current tasks
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- terminate_all_commands (Broadcast)
-------------------------------------------
-- terminates all tasks
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- transmit_broadcast
-------------------------------------------
-- Common broadcast transmission routine
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Inputs vvc_name and channel are truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH
-- are to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string;
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Input vvc_name is truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH
-- is to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string;
-------------------------------------------
-- await_completion
-------------------------------------------
-- Awaits completion of any VVC in the list or until timeout.
procedure await_completion(
constant vvc_select : in t_vvc_select;
variable vvc_info_list : inout t_vvc_info_list;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-- Awaits completion of all the VVCs in the activity register or until timeout.
procedure await_completion(
constant vvc_select : in t_vvc_select;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-- ============================================================================
-- Activity Watchdog
-- ============================================================================
procedure activity_watchdog(
constant num_exp_vvc : natural;
constant timeout : time;
constant alert_level : t_alert_level := TB_ERROR;
constant msg : string := "Activity_Watchdog"
);
-- ============================================================================
-- VVC Activity Register
-- ============================================================================
shared variable shared_vvc_activity_register : t_vvc_activity;
-- ============================================================================
-- Hierarchical VVC (HVVC)
-- ============================================================================
type t_vvc_operation is (TRANSMIT, RECEIVE); -- Type of operation to be executed by the VVC
type t_direction is (TRANSMIT, RECEIVE); -- Direction of the interface (used by the IF field config)
type t_field_position is (FIRST, MIDDLE, LAST, FIRST_AND_LAST); -- Position of a field within a packet
type t_hvvc_to_bridge is record
trigger : boolean; -- Trigger signal
operation : t_vvc_operation; -- Operation of the VVC
num_data_words : positive; -- Number of data words transferred
data_words : t_slv_array; -- Data sent to the VVC
dut_if_field_idx : natural; -- Index of the interface field
dut_if_field_pos : t_field_position; -- Position of the interface field within the packet
msg_id_panel : t_msg_id_panel; -- Message ID panel of the HVVC
end record;
type t_bridge_to_hvvc is record
trigger : boolean; -- Trigger signal
data_words : t_slv_array; -- Data received from the VVC
end record;
type t_dut_if_field_config is record
dut_address : unsigned; -- Address of the DUT IF field
dut_address_increment : integer; -- Incrementation of the address on each access
data_width : positive; -- Width of the data per transfer
use_field : boolean; -- Used by the HVVC to send/request fields to/from the bridge or ignore them when not applicable
field_description : string; -- Description of the DUT IF field
end record;
constant C_DUT_IF_FIELD_CONFIG_DEFAULT : t_dut_if_field_config(dut_address(0 downto 0)) := (
dut_address => (others => '0'),
dut_address_increment => 0,
data_width => 8,
use_field => true,
field_description => "default");
type t_dut_if_field_config_array is array (natural range <>) of t_dut_if_field_config;
type t_dut_if_field_config_direction_array is array (t_direction range <>) of t_dut_if_field_config_array;
constant C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY_DEFAULT :
t_dut_if_field_config_direction_array(t_direction'low to t_direction'high)(0 to 0)(dut_address(0 downto 0), field_description(1 to 7))
:= (others => (others => C_DUT_IF_FIELD_CONFIG_DEFAULT));
end package ti_vvc_framework_support_pkg;
package body ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
--
------------------------------------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.set <= 'Z';
flag.is_active <= '0';
wait until flag.set = '1';
flag.is_active <= '1';
wait until flag.reset = '1';
flag.is_active <= '0';
end procedure;
procedure set_flag(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.set, 0 ns, "set flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
procedure reset_flag(
signal flag : inout t_flag_record
) is
begin
flag.set <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.reset, 0 ns, "reset flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
-- This procedure checks the shared_uvvm_state on each delta cycle
procedure await_uvvm_initialization(
constant dummy : in t_void) is
begin
while (shared_uvvm_state /= INIT_COMPLETED) loop
wait for 0 ns;
end loop;
end procedure;
impure function format_command_idx(
command_idx : integer
) return string is
begin
return C_CMD_IDX_PREFIX & to_string(command_idx) & C_CMD_IDX_SUFFIX;
end;
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, ENABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, DISABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, NON_QUIET, 0 ns, delay, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, INSERT_DELAY, proc_call, NO_ID, msg, NON_QUIET, delay, scope => scope);
end procedure;
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
log(ID_OLD_AWAIT_COMPLETION, "Procedure is not supporting the VVC activity register.", scope);
transmit_broadcast(VVC_BROADCAST, AWAIT_COMPLETION, proc_call, NO_ID, msg, NON_QUIET, 0 ns, -1, timeout, scope);
end procedure;
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, TERMINATE_CURRENT_COMMAND, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "terminate_all_commands";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
flush_command_queue(VVC_BROADCAST, msg);
terminate_current_command(VVC_BROADCAST, msg, scope => scope);
end procedure;
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
begin
await_semaphore_in_delta_cycles(protected_semaphore);
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(proc_call) & ": " & add_msg_delimiter(to_string(msg))
& format_command_idx(shared_cmd_idx), scope);
else
log(ID_UVVM_SEND_CMD, to_string(proc_call)
& format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd.operation := operation;
shared_vvc_broadcast_cmd.msg_id := msg_id;
shared_vvc_broadcast_cmd.msg := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.msg(1 to msg'length) := msg;
shared_vvc_broadcast_cmd.quietness := quietness;
shared_vvc_broadcast_cmd.timeout := timeout;
shared_vvc_broadcast_cmd.delay := delay;
shared_vvc_broadcast_cmd.gen_integer := delay_int;
shared_vvc_broadcast_cmd.proc_call := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.proc_call(1 to proc_call'length) := proc_call;
if VVC_BROADCAST /= 'L' then
-- a VVC is waiting for example in await_completion
wait until VVC_BROADCAST = 'L';
end if;
-- Trigger the broadcast
VVC_BROADCAST <= '1';
wait for 0 ns;
-- set back to 'L' and wait until all VVCs have set it back
VVC_BROADCAST <= 'L';
wait until VVC_BROADCAST = 'L' for timeout; -- Wait for executor
if not (VVC_BROADCAST'event) and VVC_BROADCAST /= 'L' then -- Indicates timeout
tb_error("Timeout while waiting for the broadcast command to be ACK'ed", scope);
else
log(ID_UVVM_CMD_ACK, "ACK received for broadcast command" & format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd := C_VVC_BROADCAST_CMD_DEFAULT;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
release_semaphore(protected_semaphore);
end procedure;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_CHANNEL_STR : string := to_upper(to_string(channel));
constant C_SCOPE_LENGTH : natural := vvc_name'length + C_INSTANCE_IDX_STR'length + C_CHANNEL_STR'length + 2; -- +2 because of the two added commas
variable v_vvc_name_truncation_value : integer;
variable v_channel_truncation_value : integer;
variable v_vvc_name_truncation_idx : integer;
variable v_channel_truncation_idx : integer;
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_MINIMUM_CHANNEL_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 2) > C_LOG_SCOPE_WIDTH then -- +2 because of the two added commas
alert(TB_WARNING, "The combined width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 2.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If C_SCOPE_LENGTH is greater than allowed width
-- Check if vvc_name is greater than minimum width to truncate
elsif vvc_name'length <= C_MINIMUM_VVC_NAME_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to (C_CHANNEL_STR'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)));
-- Check if channel is greater than minimum width to truncate
elsif C_CHANNEL_STR'length <= C_MINIMUM_CHANNEL_SCOPE_WIDTH then
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If both vvc_name and channel is to be truncated
else
-- Calculate linear scaling of truncation between vvc_name and channel: (a*x)/(a+b), (b*x)/(a+b)
v_vvc_name_truncation_idx := integer(round(real(vvc_name'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
v_channel_truncation_value := integer(round(real(C_CHANNEL_STR'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
-- In case division ended with .5 and both rounded up
if (v_vvc_name_truncation_idx + v_channel_truncation_value) > (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH) then
v_channel_truncation_value := v_channel_truncation_value - 1;
end if;
-- Character index to truncate
v_vvc_name_truncation_idx := vvc_name'length - v_vvc_name_truncation_idx;
v_channel_truncation_idx := C_CHANNEL_STR'length - v_channel_truncation_value;
-- If bellow minimum name width
while v_vvc_name_truncation_idx < C_MINIMUM_VVC_NAME_SCOPE_WIDTH loop
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx + 1;
v_channel_truncation_idx := v_channel_truncation_idx - 1;
end loop;
-- If bellow minimum channel width
while v_channel_truncation_idx < C_MINIMUM_CHANNEL_SCOPE_WIDTH loop
v_channel_truncation_idx := v_channel_truncation_idx + 1;
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx - 1;
end loop;
return vvc_name(1 to v_vvc_name_truncation_idx) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to v_channel_truncation_idx);
end if;
end function;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_SCOPE_LENGTH : integer := vvc_name'length + C_INSTANCE_IDX_STR'length + 1; -- +1 because of the added comma
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 1) > C_LOG_SCOPE_WIDTH then -- +1 because of the added comma
alert(TB_WARNING, "The width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 1.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR;
-- If C_SCOPE_LENGTH is greater than allowed width truncate vvc_name
else
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR;
end if;
end function;
procedure await_completion(
constant vvc_select : in t_vvc_select;
variable vvc_info_list : inout t_vvc_info_list;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_select) & "," & vvc_info_list.priv_get_vvc_info_list & "," & to_string(timeout, ns) & ")";
constant proc_call_short : string := proc_name & "(" & to_string(vvc_select) & "," & to_string(timeout, ns) & ")";
constant c_index_not_found : integer := -1;
constant c_vvc_info_list_length : natural := vvc_info_list.priv_get_num_vvc_in_list;
variable v_vvc_idx_in_activity_register : t_integer_array(0 to C_MAX_TB_VVC_NUM) := (others => -1);
variable v_num_vvc_instances : natural := 0;
variable v_tot_vvc_instances : natural range 0 to C_MAX_TB_VVC_NUM:= 0;
variable v_vvc_logged : std_logic_vector(0 to C_MAX_TB_VVC_NUM-1) := (others => '0');
variable v_vvcs_completed : natural := 0;
variable v_local_cmd_idx : integer;
variable v_timestamp : time;
variable v_done : boolean := false;
variable v_first_wait : boolean := true;
variable v_list_idx : natural := 0;
variable v_proc_call : line;
begin
if vvc_select = ALL_VVCS and shared_vvc_activity_register.priv_get_num_registered_vvcs = c_vvc_info_list_length then
v_proc_call := new string'(proc_call_short);
else
v_proc_call := new string'(proc_call);
end if;
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
-- Store it in a local variable since new commands might be executed from another sequencer.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_cmd_idx := shared_cmd_idx + 1;
v_local_cmd_idx := shared_cmd_idx;
release_semaphore(protected_semaphore);
log(ID_AWAIT_COMPLETION, v_proc_call.all & ": " & add_msg_delimiter(msg) & "." & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
-- Give a warning for incorrect use of ALL_VVCS
if vvc_select = ALL_VVCS and shared_vvc_activity_register.priv_get_num_registered_vvcs /= c_vvc_info_list_length then
alert(TB_WARNING, v_proc_call.all & add_msg_delimiter(msg) & "=> When using ALL_VVCS with a VVC list, only the VVCs from the list will be checked."
& format_command_idx(v_local_cmd_idx), scope);
end if;
-- Check that list is not empty
if c_vvc_info_list_length = 0 then
v_done := true;
end if;
-- Loop through the VVC list and get the corresponding index from the vvc activity register
for i in 0 to c_vvc_info_list_length-1 loop
if vvc_info_list.priv_get_instance(i) = ALL_INSTANCES or vvc_info_list.priv_get_channel(i) = ALL_CHANNELS then
-- Check how many instances or channels of this VVC are registered in the vvc activity register
v_num_vvc_instances := shared_vvc_activity_register.priv_get_num_registered_vvc_matches(vvc_info_list.priv_get_name(i),
vvc_info_list.priv_get_instance(i), vvc_info_list.priv_get_channel(i));
-- Get the index for every instance or channel of this VVC
for j in 0 to v_num_vvc_instances-1 loop
v_vvc_idx_in_activity_register(v_tot_vvc_instances+j) := shared_vvc_activity_register.priv_get_vvc_idx(j, vvc_info_list.priv_get_name(i),
vvc_info_list.priv_get_instance(i), vvc_info_list.priv_get_channel(i));
end loop;
else
-- Get the index for a specific VVC
v_vvc_idx_in_activity_register(v_tot_vvc_instances) := shared_vvc_activity_register.priv_get_vvc_idx(vvc_info_list.priv_get_name(i),
vvc_info_list.priv_get_instance(i), vvc_info_list.priv_get_channel(i));
v_num_vvc_instances := 0 when v_vvc_idx_in_activity_register(v_tot_vvc_instances) = c_index_not_found else 1;
end if;
-- Update the total number of VVCs in the group
v_tot_vvc_instances := v_tot_vvc_instances + v_num_vvc_instances;
-- Check if the VVC from the list is registered in the vvc activity register, otherwise clean the list and exit procedure
if v_vvc_idx_in_activity_register(v_tot_vvc_instances-v_num_vvc_instances) = c_index_not_found then
alert(TB_ERROR, v_proc_call.all & add_msg_delimiter(msg) & "=> " & vvc_info_list.priv_get_vvc_info(i) &
" does not support this procedure." & format_command_idx(v_local_cmd_idx), scope);
v_done := true;
exit;
end if;
end loop;
v_timestamp := now;
while not(v_done) loop
v_list_idx := 0;
for i in 0 to v_tot_vvc_instances-1 loop
-- Wait for the VVCs in the group to complete (INACTIVE status)
if vvc_info_list.priv_get_cmd_idx(v_list_idx) = -1 then
if shared_vvc_activity_register.priv_get_vvc_activity(v_vvc_idx_in_activity_register(i)) = INACTIVE then
if not(v_vvc_logged(i)) then
log(ID_AWAIT_COMPLETION_END, v_proc_call.all & "=> " & shared_vvc_activity_register.priv_get_vvc_info(v_vvc_idx_in_activity_register(i)) &
" finished. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
v_vvc_logged(i) := '1';
v_vvcs_completed := v_vvcs_completed + 1;
end if;
if vvc_select = ANY_OF or v_vvcs_completed = v_tot_vvc_instances then
v_done := true;
end if;
end if;
-- Wait for the VVCs in the group to complete (cmd_idx completed)
else
if shared_vvc_activity_register.priv_get_vvc_last_cmd_idx_executed(v_vvc_idx_in_activity_register(i)) >= vvc_info_list.priv_get_cmd_idx(v_list_idx) then
if not(v_vvc_logged(i)) then
log(ID_AWAIT_COMPLETION_END, v_proc_call.all & "=> " & shared_vvc_activity_register.priv_get_vvc_info(v_vvc_idx_in_activity_register(i)) &
" finished. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
v_vvc_logged(i) := '1';
v_vvcs_completed := v_vvcs_completed + 1;
end if;
if vvc_select = ANY_OF or v_vvcs_completed = v_tot_vvc_instances then
v_done := true;
end if;
end if;
end if;
-- Increment the vvc_info_list index (different from the v_vvc_idx_in_activity_register)
if not(vvc_info_list.priv_get_instance(v_list_idx) = ALL_INSTANCES or vvc_info_list.priv_get_channel(v_list_idx) = ALL_CHANNELS) then
v_list_idx := v_list_idx + 1;
end if;
end loop;
if not(v_done) then
if v_first_wait then
log(ID_AWAIT_COMPLETION_WAIT, v_proc_call.all & " - Pending completion. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
v_first_wait := false;
end if;
-- Wait for vvc activity trigger pulse
wait on global_trigger_vvc_activity_register for timeout;
-- Check if there was a timeout
if now >= v_timestamp + timeout then
alert(TB_ERROR, v_proc_call.all & "=> Timeout. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope);
v_done := true;
end if;
end if;
end loop;
if list_action = CLEAR_LIST then
vvc_info_list.priv_clear_list;
log(ID_AWAIT_COMPLETION_LIST, v_proc_call.all & "=> All VVCs removed from the list. " & add_msg_delimiter(msg) &
format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
elsif list_action = KEEP_LIST then
log(ID_AWAIT_COMPLETION_LIST, v_proc_call.all & "=> Keeping all VVCs in the list. " & add_msg_delimiter(msg) &
format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
end if;
end procedure;
procedure await_completion(
constant vvc_select : in t_vvc_select;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_select) & "," & to_string(timeout, ns) & ")";
variable v_vvc_info_list : t_vvc_info_list;
begin
if vvc_select = ALL_VVCS then
-- Get all the VVCs from the vvc activity register and put them in the vvc_info_list
for i in 0 to shared_vvc_activity_register.priv_get_num_registered_vvcs-1 loop
v_vvc_info_list.add(shared_vvc_activity_register.priv_get_vvc_name(i),
shared_vvc_activity_register.priv_get_vvc_instance(i),
shared_vvc_activity_register.priv_get_vvc_channel(i));
end loop;
await_completion(vvc_select, v_vvc_info_list, timeout, list_action, msg, scope);
else
alert(TB_ERROR, proc_call & add_msg_delimiter(msg) & "=> A VVC list is required when using " & to_string(vvc_select) & ".", scope);
end if;
end procedure;
-- ============================================================================
-- Activity Watchdog
-- ============================================================================
-------------------------------------------------------------------------------
-- Activity watchdog:
-- Include this as a concurrent procedure from your testbench.
-------------------------------------------------------------------------------
procedure activity_watchdog(
constant num_exp_vvc : natural;
constant timeout : time;
constant alert_level : t_alert_level := TB_ERROR;
constant msg : string := "Activity_Watchdog"
) is
variable v_timeout : time;
begin
wait for 0 ns;
log(ID_WATCHDOG, "Starting activity watchdog , timeout=" & to_string(timeout, C_LOG_TIME_BASE) & ". " & msg);
wait for 0 ns;
-- Check if all expected VVCs are registered
if (num_exp_vvc /= shared_vvc_activity_register.priv_get_num_registered_vvcs) and (num_exp_vvc > 0) then
shared_vvc_activity_register.priv_list_registered_vvc(msg);
alert(TB_WARNING, "Number of VVCs in activity watchdog is not expected, actual=" &
to_string(shared_vvc_activity_register.priv_get_num_registered_vvcs) & ", exp=" & to_string(num_exp_vvc) & ".\n" &
"Note that leaf VVCs (e.g. channels) are counted individually. " & msg);
end if;
loop
wait on global_trigger_vvc_activity_register for timeout;
if not(global_trigger_vvc_activity_register'event) and shared_vvc_activity_register.priv_are_all_vvc_inactive then
alert(alert_level, "Activity watchdog timer ended after " & to_string(timeout, C_LOG_TIME_BASE) & "! " & msg);
end if;
end loop;
wait;
end procedure activity_watchdog;
end package body ti_vvc_framework_support_pkg;
| mit | 114a0eb56a7eb37bde5275b3ca7039e9 | 0.568072 | 4.023681 | false | false | false | false |
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 88816)
`protect data_block
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`protect end_protected
| gpl-2.0 | a230bd9c9319aa08d6c05df0599e14c8 | 0.952931 | 1.809175 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_addsub_v12_0/hdl/c_addsub_v12_0_viv.vhd | 3 | 41,084 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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| gpl-2.0 | 1765d786cbf0ebd85b0a9efe969fff7b | 0.947376 | 1.831491 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_gmii/src/gmii_bfm_pkg.vhd | 1 | 19,781 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library std;
use std.textio.all;
--================================================================================================================================
--================================================================================================================================
package gmii_bfm_pkg is
--==========================================================================================
-- Types and constants for GMII BFM
--==========================================================================================
constant C_SCOPE : string := "GMII BFM";
-- Interface record for BFM signals to DUT
type t_gmii_tx_if is record
gtxclk : std_logic;
txd : std_logic_vector(7 downto 0);
txen : std_logic;
end record;
-- Interface record for BFM signals from DUT
type t_gmii_rx_if is record
rxclk : std_logic;
rxd : std_logic_vector(7 downto 0);
rxdv : std_logic;
end record;
-- Configuration record to be assigned in the test harness.
type t_gmii_bfm_config is record
max_wait_cycles : integer; -- Used for setting the maximum cycles to wait before an alert is issued when
-- waiting for signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- Severity if max_wait_cycles expires.
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
bfm_sync : t_bfm_sync; -- Synchronisation of the BFM procedures, i.e. using clock signals, using setup_time and hold_time.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the BFM
end record;
-- Define the default value for the BFM config
constant C_GMII_BFM_CONFIG_DEFAULT : t_gmii_bfm_config := (
max_wait_cycles => 12, -- Standard minimum interpacket gap (Gigabith Ethernet)
max_wait_cycles_severity => ERROR,
clock_period => -1 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => -1 ns,
hold_time => -1 ns,
bfm_sync => SYNC_ON_CLOCK_ONLY,
match_strictness => MATCH_EXACT,
id_for_bfm => ID_BFM
);
--==========================================================================================
-- BFM procedures
--==========================================================================================
-- This function returns a GMII interface with initialized signals.
-- All input signals are initialized to 0
-- All output signals are initialized to Z
function init_gmii_if_signals
return t_gmii_tx_if;
function init_gmii_if_signals
return t_gmii_rx_if;
---------------------------------------------------------------------------------------------
-- GMII Write
-- BFM -> DUT
---------------------------------------------------------------------------------------------
procedure gmii_write (
constant data_array : in t_slv_array;
constant msg : in string := "";
signal gmii_tx_if : inout t_gmii_tx_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT
);
---------------------------------------------------------------------------------------------
-- GMII Read
-- DUT -> BFM
---------------------------------------------------------------------------------------------
procedure gmii_read (
variable data_array : out t_slv_array;
variable data_len : out natural;
constant msg : in string := "";
signal gmii_rx_if : inout t_gmii_rx_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
---------------------------------------------------------------------------------------------
-- GMII Expect
---------------------------------------------------------------------------------------------
procedure gmii_expect (
constant data_exp : in t_slv_array;
constant msg : in string := "";
signal gmii_rx_if : inout t_gmii_rx_if;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT
);
end package gmii_bfm_pkg;
--================================================================================================================================
--================================================================================================================================
package body gmii_bfm_pkg is
function init_gmii_if_signals
return t_gmii_tx_if is
variable init_if : t_gmii_tx_if;
begin
init_if.gtxclk := 'Z';
init_if.txd := (init_if.txd'range => '0');
init_if.txen := '0';
return init_if;
end function;
function init_gmii_if_signals
return t_gmii_rx_if is
variable init_if : t_gmii_rx_if;
begin
init_if.rxclk := 'Z';
init_if.rxd := (init_if.rxd'range => 'Z');
init_if.rxdv := 'Z';
return init_if;
end function;
---------------------------------------------------------------------------------------------
-- GMII Write
-- BFM -> DUT
---------------------------------------------------------------------------------------------
procedure gmii_write(
constant data_array : in t_slv_array;
constant msg : in string := "";
signal gmii_tx_if : inout t_gmii_tx_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "gmii_write";
constant proc_call : string := proc_name & "(" & to_string(data_array'length) & " bytes)";
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
check_value(data_array'ascending, TB_FAILURE, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity.", scope, ID_NEVER, msg_id_panel, proc_call);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
end if;
gmii_tx_if <= init_gmii_if_signals;
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(gmii_tx_if.gtxclk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
log(config.id_for_bfm, proc_call & "=> " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Write all the bytes in the data_array
for i in data_array'range loop
gmii_tx_if.txd <= data_array(i);
gmii_tx_if.txen <= '1';
-- Check the clock margin
wait until rising_edge(gmii_tx_if.gtxclk);
if v_time_of_rising_edge < 0 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(gmii_tx_if.gtxclk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(gmii_tx_if.gtxclk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
gmii_tx_if <= init_gmii_if_signals;
log(config.id_for_bfm, proc_call & " DONE. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------------------
-- GMII Read
-- DUT -> BFM
---------------------------------------------------------------------------------------------
procedure gmii_read(
variable data_array : out t_slv_array;
variable data_len : out natural;
constant msg : in string := "";
signal gmii_rx_if : inout t_gmii_rx_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant local_proc_name : string := "gmii_read"; -- Internal proc_name; Used if called from sequencer or VVC
constant local_proc_call : string := local_proc_name & "(" & to_string(data_array'length) & " bytes)";
variable v_proc_call : line; -- Current proc_call, external or local
variable v_normalized_data : t_slv_array(0 to data_array'length-1)(7 downto 0);
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_byte_cnt : natural := 0;
variable v_done : boolean := false;
variable v_timeout : boolean := false;
variable v_wait_cycles : natural := 0;
begin
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'gmii_read...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing gmii_read...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
check_value(data_array'ascending, TB_FAILURE, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
gmii_rx_if <= init_gmii_if_signals;
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(gmii_rx_if.rxclk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
log(config.id_for_bfm, v_proc_call.all & "=> " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Wait for the first rising edge to sample the data and check the clock margin
wait until rising_edge(gmii_rx_if.rxclk);
v_time_of_rising_edge := now;
check_clock_period_margin(gmii_rx_if.rxclk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Wait for data valid to be active
while gmii_rx_if.rxdv /= '1' and v_wait_cycles < config.max_wait_cycles loop
wait_on_bfm_sync_start(gmii_rx_if.rxclk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
wait until rising_edge(gmii_rx_if.rxclk);
v_wait_cycles := v_wait_cycles + 1;
end loop;
if gmii_rx_if.rxdv /= '1' then
v_timeout := true;
v_done := true;
end if;
-- Sample the data
while not(v_done) loop
if gmii_rx_if.rxdv = '1' then
v_normalized_data(v_byte_cnt) := gmii_rx_if.rxd;
if v_byte_cnt = v_normalized_data'length-1 then
v_done := true;
else
wait_on_bfm_exit(gmii_rx_if.rxclk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
wait until rising_edge(gmii_rx_if.rxclk);
end if;
v_byte_cnt := v_byte_cnt + 1;
else
-- Data valid went low
v_done := true;
end if;
end loop;
data_array := v_normalized_data;
data_len := v_byte_cnt;
-- Wait according to bfm_sync config
if not(v_timeout) then
wait_on_bfm_exit(gmii_rx_if.rxclk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
-- Done. Check if there was a timeout or it was successful
if v_timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout while waiting for valid data. " &
add_msg_delimiter(msg), scope);
else
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & " DONE. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. gmii_expect)
end if;
end if;
DEALLOCATE(v_proc_call);
end procedure;
---------------------------------------------------------------------------------------------
-- GMII Expect
---------------------------------------------------------------------------------------------
procedure gmii_expect (
constant data_exp : in t_slv_array;
constant msg : in string := "";
signal gmii_rx_if : inout t_gmii_rx_if;
constant alert_level : in t_alert_level := ERROR;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_gmii_bfm_config := C_GMII_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "gmii_expect";
constant proc_call : string := proc_name & "(" & to_string(data_exp'length) & " bytes)";
variable v_normalized_data : t_slv_array(0 to data_exp'length-1)(7 downto 0) := data_exp;
variable v_rx_data_array : t_slv_array(v_normalized_data'range)(7 downto 0);
variable v_rx_data_len : natural;
variable v_length_error : boolean := false;
variable v_data_error_cnt : natural := 0;
variable v_first_wrong_byte : natural;
variable v_alert_radix : t_radix;
begin
check_value(data_exp'ascending, TB_FAILURE, "Sanity check: Check that data_exp is ascending (defined with 'to'), for byte order clarity.", scope, ID_NEVER, msg_id_panel, proc_call);
-- Read data
gmii_read(v_rx_data_array, v_rx_data_len, msg, gmii_rx_if, scope, msg_id_panel, config, proc_call);
-- Check the length of the received data
if v_rx_data_len /= v_normalized_data'length then
v_length_error := true;
end if;
-- Check if each received bit matches the expected.
-- Report the first wrong byte (iterate from the last to the first)
for byte in v_rx_data_array'high downto 0 loop
for i in v_rx_data_array(byte)'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if v_normalized_data(byte)(i) = '-' or check_value(v_rx_data_array(byte)(i), v_normalized_data(byte)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
-- Received byte doesn't match
v_data_error_cnt := v_data_error_cnt + 1;
v_first_wrong_byte := byte;
end if;
end loop;
end loop;
-- Done. Report result
if v_length_error then
alert(alert_level, proc_call & "=> Failed. Mismatch in received data length. Was " & to_string(v_rx_data_len) &
". Expected " & to_string(v_normalized_data'length) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_data_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data_array(v_first_wrong_byte), v_normalized_data(v_first_wrong_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in "& to_string(v_data_error_cnt) & " data bits. First mismatch in byte# " &
to_string(v_first_wrong_byte) & ". Was " & to_string(v_rx_data_array(v_first_wrong_byte), v_alert_radix, AS_IS, INCL_RADIX) &
". Expected " & to_string(v_normalized_data(v_first_wrong_byte), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received " & to_string(v_rx_data_array'length) & " bytes. " &
add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
end package body gmii_bfm_pkg;
| mit | 662e7aacf5f3bfafdb63c7cd870ba10b | 0.541985 | 3.920912 | false | true | false | false |
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`protect end_protected
| gpl-2.0 | 7239654afc587a720753ee2e78259cc1 | 0.948487 | 1.843125 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_fma/flt_fma_round_bit.vhd | 3 | 30,968 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21184)
`protect data_block
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| gpl-2.0 | 8254f190fcc96a4f2b40165ea45e7347 | 0.944717 | 1.838627 | false | false | false | false |
keith-epidev/VHDL-lib | src/components/debounce/debounce.vhd | 1 | 1,753 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity debounce is
generic(
delay:integer := 50000
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end debounce;
architecture Behavioral of debounce is
signal press : std_logic;
signal debounce_enable : std_logic;
signal debounce_pulse : std_logic;
signal hold_check : std_logic;
signal hold_pulse: std_logic;
-- signal rapid_pulse: std_logic;
-- signal rapid_enable: std_logic;
type states is (idle,wait_noise,check,debounced,holding,held);
signal state : states := idle;
begin
output <= press;
pulser1: pulser generic map(delay=>delay) port map(clk,debounce_enable,debounce_pulse);
pulser2: pulser generic map(delay=>delay*2) port map(clk,hold_check,hold_pulse);
debounce_signal: process(clk)
begin
if(clk'event and clk = '1')then
case state is
when idle =>
debounce_enable <= '0';
hold_check <= '0';
press <= '0';
if(input = '1')then
state <= wait_noise;
end if;
when wait_noise =>
debounce_enable <= '1';
if(debounce_pulse = '1')then
state <= check;
end if;
when check =>
if(input = '1')then
state <= debounced;
else
state <= idle;
end if;
when debounced =>
press <= '1';
state <= holding;
when holding =>
press <= '0';
hold_check <= '1';
if(hold_pulse = '1')then
state <= held;
end if;
when held =>
if(input = '1')then
state <= debounced;
else
state <= idle;
end if;
end case;
end if;
end process;
end Behavioral;
| gpl-2.0 | 727728b0ca86aa0d9affe8ec442841ec | 0.593269 | 3.135957 | false | false | false | false |
notti/dis_se | testbench/tb_filter.vhd | 1 | 6,011 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_filter is
end tb_filter;
architecture behav of tb_filter is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal clk2x : std_logic := '0';
signal ena : std_logic := '0';
signal addra : t_data2 := (others => '0');
signal doa : t_data2 := (others => '0');
signal enb : std_logic := '0';
signal addrb : t_data2 := (others => '0');
signal dob : t_data2 := (others => '0');
signal web : std_logic_vector(1 downto 0) := (others => '0');
signal dib : t_data2 := (others => '0');
signal bbusy : std_logic := '0';
signal mem : t_data2_array(4095 downto 0) := (others => (others => '0'));
signal serial : t_data_array(1023 downto 0) :=
(32 => X"3F",
33 => X"3F",
34 => X"3F",
35 => X"3F",
36 => X"3F",
37 => X"3F",
38 => X"3F",
39 => X"3F",
40 => X"3F",
41 => X"3F",
42 => X"3F",
43 => X"3F",
44 => X"3F",
45 => X"3F",
46 => X"3F",
47 => X"3F",
48 => X"3F",
49 => X"3F",
50 => X"3F",
51 => X"3F",
52 => X"3F",
53 => X"3F",
54 => X"3F",
55 => X"3F",
56 => X"3F",
57 => X"3F",
58 => X"3F",
59 => X"3F",
60 => X"3F",
61 => X"3F",
62 => X"3F",
63 => X"3F",
64 => X"3F",
others => X"00");
procedure hex2slv(c : character; slv : out std_logic_vector(3 downto 0); good : out boolean) is
begin
good := true;
case c is
when 'A' to 'F' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('A') + 10, 4)); return;
when 'a' to 'f' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('a') + 10, 4)); return;
when '0' to '9' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('0'), 4)); return;
when others => good := false; return;
end case;
end procedure;
signal init : boolean := false;
begin
process
begin
clk <= '1';
clk2x <= '1';
wait for 5 ns;
clk2x <= '0';
wait for 5 ns;
clk <= '0';
clk2x <= '1';
wait for 5 ns;
clk2x <= '0';
wait for 5 ns;
end process;
process(clk)
file memfile : text;
variable fname : string(1 to 63) := "/home/notti/uni/master/dis_vertiefung/se/project/src/filter.mem";
variable buf_in, buf_out : line;
variable f_status : FILE_OPEN_STATUS;
variable good: boolean := true;
variable o: character;
variable i: integer := 1;
variable val: std_logic_vector(15 downto 0);
variable ser_out : integer;
begin
if rising_edge(clk) then
if rst = '1' and init = false then
file_open(f_status, memfile, fname, read_mode);
readline(memfile, buf_in);
for j in 0 to 4 loop
read(buf_in, o, good);
assert good report "memfile error" severity failure;
end loop;
i := 0;
loop
read(buf_in, o, good);
exit when not good;
assert o = ' ' report "memfile error: " & o severity failure;
for j in 0 to 3 loop
read(buf_in, o, good);
assert good report "memfile error" severity failure;
hex2slv(o, val((j+1)*4-1 downto j*4), good);
assert good report "memfile error" severity failure;
end loop;
mem(i) <= val;
i := i + 1;
end loop;
assert false report "read " & integer'image(i) & " tokens" severity note;
init <= true;
i := 0;
elsif rst = '0' then
if ena = '1' then
doa <= mem(to_integer(unsigned(addra)));
end if;
if enb = '1' then
if addrb = X"FFFF" then
if web = "00" then
if i = 64 then
assert false report "stop" severity failure;
end if;
dob <= serial(i) & serial(i);
i := i + 1;
else
if web(0) = '1' then
ser_out := to_integer(signed(dib(7 downto 0)));
write(buf_out, ser_out);
writeline(output, buf_out);
end if;
end if;
else
dob <= mem(to_integer(unsigned(addrb)));
if web(1) = '1' then
mem(to_integer(unsigned(addrb)))(15 downto 8) <= dib(15 downto 8);
end if;
if web(0) = '1' then
mem(to_integer(unsigned(addrb)))(7 downto 0) <= dib(7 downto 0);
end if;
end if;
end if;
end if;
end if;
end process;
process
begin
wait for 61 ns;
rst <= '0';
wait for 20 ns;
end process;
asoc: entity work.cpu
port map(
rst => rst,
clk => clk,
clk2x => clk2x,
ena => ena,
addra => addra,
doa => doa,
enb => enb,
addrb => addrb,
dob => dob,
web => web,
dib => dib,
bbusy => bbusy
);
end behav;
| bsd-2-clause | 237967947fc05b83c792a37ba022c8c8 | 0.417734 | 3.865595 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/r2_datapath.vhd | 3 | 50,052 | `protect begin_protected
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| gpl-2.0 | ade1077896fc7a185553486bd048ee3b | 0.950851 | 1.824385 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/NewCombined/RegisterBank.vhd | 1 | 4,293 | ----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Revision 0.02 - Reset line added
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
RST : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk,RST) -- Synchronous register bank
begin
if (RST = '0') then
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
else
R0dat <= (OTHERS => '0');
R1dat <= (OTHERS => '0');
R2dat <= (OTHERS => '0');
R3dat <= (OTHERS => '0');
R4dat <= (OTHERS => '0');
R5dat <= (OTHERS => '0');
R6dat <= (OTHERS => '0');
R7dat <= (OTHERS => '0');
R8dat <= (OTHERS => '0');
R9dat <= (OTHERS => '0');
R10dat <= (OTHERS => '0');
R11dat <= (OTHERS => '0');
R12dat <= (OTHERS => '0');
R13dat <= (OTHERS => '0');
R14dat <= (OTHERS => '0');
R15dat <= (OTHERS => '0');
end if;
end process;
end Behavioral;
| gpl-3.0 | 5c2e44a64e0d997a20694e63e0aa8352 | 0.528535 | 2.805882 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | b735f0042d70bae502308c57d3598be4 | 0.924351 | 1.901692 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Combined[old]/ipcore_dir/EX_MEM/example_design/EX_MEM_exdes.vhd | 1 | 4,601 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: EX_MEM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EX_MEM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END EX_MEM_exdes;
ARCHITECTURE xilinx OF EX_MEM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT EX_MEM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : EX_MEM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | c3fcfe0103bf36e553ccc5d5c7dad2c7 | 0.565964 | 4.718974 | false | false | false | false |
UVVM/UVVM_All | uvvm_util/src/data_fifo_pkg.vhd | 1 | 9,470 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
use work.data_queue_pkg.all;
package data_fifo_pkg is
shared variable shared_data_fifo : t_data_queue;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the FIFO.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
-- - Returns: The index of the initiated FIFO (natural).
-- Returns 0 on error.
--
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_fifo_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the FIFO
--
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_fifo_put
------------------------------------------
-- This procedure puts data into a FIFO with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the FIFO size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_fifo_get
------------------------------------------
-- This function returns the data from the FIFO
-- and removes the returned data from the FIFO.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to get() from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to get() a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_flush
------------------------------------------
-- This procedure empties the FIFO given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be flushed.
--
procedure uvvm_fifo_flush(
buffer_idx : natural
);
------------------------------------------
-- uvvm_fifo_peek
------------------------------------------
-- This function returns the data from the FIFO
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the FIFO. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty FIFO is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the FIFO size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_fifo_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The number of elements occupying the FIFO (natural).
--
--
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_fifo_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the FIFO given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the FIFO (natural).
--
--
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_fifo_is_full
------------------------------------------
-- This function returns a boolean indicating if
-- the FIFO is full or not.
--
-- - Parameters:
-- - buffer_idx - The index of the FIFO (natural)
--
-- - Returns: TRUE if FIFO is full, else FALSE.
--
--
impure function uvvm_fifo_is_full(
buffer_idx : natural
) return boolean;
------------------------------------------
-- uvvm_fifo_deallocate
------------------------------------------
-- This procedure deallocates all the FIFOs
-- in the buffer.
--
procedure uvvm_fifo_deallocate(
dummy : t_void
);
end package data_fifo_pkg;
package body data_fifo_pkg is
impure function uvvm_fifo_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_fifo.init_queue(buffer_size_in_bits, "UVVM_FIFO");
end function;
procedure uvvm_fifo_init(
buffer_idx : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_fifo.init_queue(buffer_idx, buffer_size_in_bits, "UVVM_FIFO");
end procedure;
procedure uvvm_fifo_put(
buffer_idx : natural;
data : std_logic_vector
) is
begin
shared_data_fifo.push_back(buffer_idx, data);
end procedure;
impure function uvvm_fifo_get(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.pop_front(buffer_idx, entry_size_in_bits);
end function;
procedure uvvm_fifo_flush(
buffer_idx : natural
) is
begin
shared_data_fifo.flush(buffer_idx);
end procedure;
impure function uvvm_fifo_peek(
buffer_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_fifo.peek_front(buffer_idx, entry_size_in_bits);
end function;
impure function uvvm_fifo_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_count(buffer_idx);
end function;
impure function uvvm_fifo_get_max_count(
buffer_idx : natural
) return natural is
begin
return shared_data_fifo.get_queue_count_max(buffer_idx);
end function;
impure function uvvm_fifo_is_full(
buffer_idx : natural
) return boolean is
begin
return shared_data_fifo.get_queue_is_full(buffer_idx);
end function;
procedure uvvm_fifo_deallocate(
dummy : t_void
) is
begin
shared_data_fifo.deallocate_buffer(VOID);
end procedure;
end package body data_fifo_pkg;
| mit | f377799e4cb0933c76478b83aa23e2a4 | 0.529461 | 4.477541 | false | false | false | false |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_spdif_tx/axi_spdif_tx.vhd | 1 | 10,647 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011-2013(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- [email protected] (c) Analog Devices Inc.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tx_package.all;
use work.axi_ctrlif;
use work.axi_streaming_dma_tx_fifo;
use work.pl330_dma_fifo;
entity axi_spdif_tx is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_FAMILY : string := "virtex6";
C_DMA_TYPE : integer := 0
);
port (
--SPDIF ports
spdif_data_clk : in std_logic;
spdif_tx_o : out std_logic;
--AXI Lite interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
--AXI streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
--PL330 DMA interface
DMA_REQ_ACLK : in std_logic;
DMA_REQ_RSTN : in std_logic;
DMA_REQ_DAVALID : in std_logic;
DMA_REQ_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_DAREADY : out std_logic;
DMA_REQ_DRVALID : out std_logic;
DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_DRLAST : out std_logic;
DMA_REQ_DRREADY : in std_logic
);
end entity axi_spdif_tx;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_spdif_tx is
------------------------------------------
-- SPDIF signals
------------------------------------------
signal config_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal chstat_freq : std_logic_vector(1 downto 0);
signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
signal sample_data_ack : std_logic;
signal sample_data: std_logic_vector(15 downto 0);
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_ratio : std_logic_vector(7 downto 0);
signal conf_tinten, conf_txdata, conf_txen : std_logic;
signal channel : std_logic;
signal enable : boolean;
signal fifo_data_out : std_logic_vector(31 downto 0);
signal fifo_data_ack : std_logic;
signal fifo_reset : std_logic;
signal tx_fifo_stb : std_logic;
-- Register access
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 3;
signal rd_addr : integer range 0 to 3;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
begin
fifo_reset <= not conf_txdata;
enable <= conf_txdata = '1';
fifo_data_ack <= channel and sample_data_ack;
streaming_dma_gen: if C_DMA_TYPE = 0 generate
fifo: entity axi_streaming_dma_tx_fifo
generic map (
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => fifo_reset,
enable => enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TLAST,
S_AXIS_TLAST => S_AXIS_TVALID,
out_ack => fifo_data_ack,
out_data => fifo_data_out
);
end generate;
no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate
S_AXIS_TREADY <= '0';
end generate;
pl330_dma_gen: if C_DMA_TYPE = 1 generate
tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32,
FIFO_DIRECTION => 0
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => fifo_reset,
enable => enable,
in_data => wr_data,
in_stb => tx_fifo_stb,
out_ack => fifo_data_ack,
out_data => fifo_data_out,
dclk => DMA_REQ_ACLK,
dresetn => DMA_REQ_RSTN,
davalid => DMA_REQ_DAVALID,
daready => DMA_REQ_DAREADY,
datype => DMA_REQ_DATYPE,
drvalid => DMA_REQ_DRVALID,
drready => DMA_REQ_DRREADY,
drtype => DMA_REQ_DRTYPE,
drlast => DMA_REQ_DRLAST
);
end generate;
no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate
DMA_REQ_DAREADY <= '0';
DMA_REQ_DRVALID <= '0';
DMA_REQ_DRTYPE <= (others => '0');
DMA_REQ_DRLAST <= '0';
end generate;
sample_data_mux: process (fifo_data_out, channel) is
begin
if channel = '0' then
sample_data <= fifo_data_out(15 downto 0);
else
sample_data <= fifo_data_out(31 downto 16);
end if;
end process;
-- Configuration signals update
conf_mode(3 downto 0) <= config_reg(23 downto 20);
conf_ratio(7 downto 0) <= config_reg(15 downto 8);
conf_tinten <= config_reg(2);
conf_txdata <= config_reg(1);
conf_txen <= config_reg(0);
-- Channel status signals update
chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
chstat_gstat <= chstatus_reg(3);
chstat_preem <= chstatus_reg(2);
chstat_copy <= chstatus_reg(1);
chstat_audio <= chstatus_reg(0);
-- Transmit encoder
TENC: tx_encoder
generic map (
DATA_WIDTH => 16
)
port map (
up_clk => S_AXI_ACLK,
data_clk => spdif_data_clk, -- data clock
resetn => S_AXI_ARESETN, -- resetn
conf_mode => conf_mode, -- sample format
conf_ratio => conf_ratio, -- clock divider
conf_txdata => conf_txdata, -- sample data enable
conf_txen => conf_txen, -- spdif signal enable
chstat_freq => chstat_freq, -- sample freq.
chstat_gstat => chstat_gstat, -- generation status
chstat_preem => chstat_preem, -- preemphasis status
chstat_copy => chstat_copy, -- copyright bit
chstat_audio => chstat_audio, -- data format
sample_data => sample_data, -- audio data
sample_data_ack => sample_data_ack, -- sample buffer read
channel => channel, -- which channel should be read
spdif_tx_o => spdif_tx_o -- SPDIF output signal
);
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_REG => 4
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
rd_stb => '1',
wr_addr => wr_addr,
wr_data => wr_data,
wr_ack => '1',
wr_stb => wr_stb
);
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
config_reg <= (others => '0');
chstatus_reg <= (others => '0');
else
if wr_stb = '1' then
case wr_addr is
when 0 => config_reg <= wr_data;
when 1 => chstatus_reg <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
process (rd_addr, config_reg, chstatus_reg)
begin
case rd_addr is
when 0 => rd_data <= config_reg;
when 1 => rd_data <= chstatus_reg;
when others => rd_data <= (others => '0');
end case;
end process;
end IMP;
| gpl-3.0 | 1b555b7861f473ae672f0c856a395132 | 0.609092 | 3.011029 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/clk_108MHz/clk_108MHz_funcsim.vhdl | 1 | 7,474 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:12:25 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_108MHz/clk_108MHz_funcsim.vhdl
-- Design : clk_108MHz
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_108MHzclk_108MHz_clk_wiz is
port (
clk_100MHz : in STD_LOGIC;
clk_108MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_108MHzclk_108MHz_clk_wiz : entity is "clk_108MHz_clk_wiz";
end clk_108MHzclk_108MHz_clk_wiz;
architecture STRUCTURE of clk_108MHzclk_108MHz_clk_wiz is
signal clk_100MHz_clk_108MHz : STD_LOGIC;
signal clk_108MHz_clk_108MHz : STD_LOGIC;
signal clkfbout_buf_clk_108MHz : STD_LOGIC;
signal clkfbout_clk_108MHz : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute box_type of clkin1_ibufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_108MHz,
O => clkfbout_buf_clk_108MHz
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_100MHz,
O => clk_100MHz_clk_108MHz
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_108MHz_clk_108MHz,
O => clk_108MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 9.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_108MHz,
CLKFBOUT => clkfbout_clk_108MHz,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_100MHz_clk_108MHz,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_108MHz_clk_108MHz,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_108MHz is
port (
clk_100MHz : in STD_LOGIC;
clk_108MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_108MHz;
architecture STRUCTURE of clk_108MHz is
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of STRUCTURE : architecture is true;
begin
U0: entity work.clk_108MHzclk_108MHz_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_108MHz => clk_108MHz,
locked => locked
);
end STRUCTURE;
| gpl-2.0 | ce6e1274516c7af001c6a8d778cc4847 | 0.61841 | 3.318828 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 39c9c78cd624bb4ce5924301ee951574 | 0.948631 | 1.824265 | false | false | false | false |
UVVM/uvvm_vvc_framework | bitvis_vip_gpio/src/vvc_context.vhd | 1 | 1,440 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_gpio;
use bitvis_vip_gpio.gpio_bfm_pkg.all;
use bitvis_vip_gpio.vvc_cmd_pkg.all;
use bitvis_vip_gpio.vvc_methods_pkg.all;
use bitvis_vip_gpio.td_vvc_framework_common_methods_pkg.all;
end context; | mit | 495f85115ff5b0b2e71aa9351e92d9e9 | 0.532639 | 5.333333 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/max2_2.vhd | 3 | 6,651 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3184)
`protect data_block
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`protect end_protected
| gpl-2.0 | f6d42977c1f581a58c4588d060d9dbc9 | 0.913547 | 1.977111 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/logic_gate.vhd | 2 | 18,733 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12128)
`protect data_block
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`protect end_protected
| gpl-2.0 | 574f5f82312e3ab08979c618659e35fa | 0.9408 | 1.856407 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_clock_generator/src/vvc_cmd_pkg.vhd | 1 | 7,596 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
START_CLOCK,
STOP_CLOCK,
SET_CLOCK_PERIOD,
SET_CLOCK_HIGH_TIME
);
--<USER_INPUT> Create constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- For example, given a VVC with parallel data bus and address bus, constraints should be added for maximum data length
-- and address length
-- Example:
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 8;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
-- VVC dedicated fields
clock_period : time;
clock_high_time : time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL,
-- VVC dedicated fields
clock_period => 10 ns,
clock_high_time => 5 ns
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--========================================================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--========================================================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--========================================================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--========================================================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--========================================================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--========================================================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | 308c28d4a8bee07bf3230306183142a2 | 0.43049 | 5.520349 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_ethernet/tb/ethernet_mac.vhd | 1 | 9,079 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_ethernet;
use bitvis_vip_ethernet.support_pkg.all;
use work.ethernet_mac_pkg.all;
entity ethernet_mac is
port(
-- SBI interface
clk : in std_logic;
sbi_cs : in std_logic;
sbi_addr : in unsigned(7 downto 0);
sbi_rena : in std_logic;
sbi_wena : in std_logic;
sbi_wdata : in std_logic_vector(7 downto 0);
sbi_ready : out std_logic;
sbi_rdata : out std_logic_vector(7 downto 0);
-- GMII interface (only TX)
gtxclk : out std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic
);
end entity ethernet_mac;
architecture behave of ethernet_mac is
signal mac_dest_addr : std_logic_vector(47 downto 0) := (others => '0');
signal mac_src_addr : std_logic_vector(47 downto 0) := (others => '0');
signal payload_len : std_logic_vector(15 downto 0) := (others => '0');
signal payload_len_int : integer;
signal payload : t_byte_array(0 to C_MAX_PAYLOAD_LENGTH-1);
signal dummy_reg : std_logic_vector(7 downto 0) := (others => '0');
signal frame_ready : std_logic := '0';
signal frame_sent : std_logic := '0';
signal read_ready : std_logic := '0';
type t_state is (s_idle, s_send_pkt);
signal fsm_tx : t_state := s_idle;
begin
------------------------------------------------------------------------------------
-- SBI interface
------------------------------------------------------------------------------------
-- Write SBI data to the Ethernet MAC registers (can only hold one frame at a time).
-- Data is transmitted with the LSB first.
p_sbi_write_regs : process(clk)
variable v_mac_dest_byte : integer range 0 to 6 := 0;
variable v_mac_src_byte : integer range 0 to 6 := 0;
variable v_pay_len_byte : integer range 0 to 2 := 0;
variable v_payload_byte : integer range 0 to C_MAX_PAYLOAD_LENGTH := 0;
begin
if rising_edge(clk) then
if sbi_cs = '1' and sbi_wena = '1' and sbi_ready = '1' then
-- Registers are expected to be written in order (payload being the last).
case sbi_addr is
when C_ETH_ADDR_MAC_DEST =>
if v_mac_dest_byte < 6 then
mac_dest_addr <= mac_dest_addr(39 downto 0) & sbi_wdata;
v_mac_dest_byte := v_mac_dest_byte + 1;
else
alert(WARNING, "Ethernet MAC: Overwriting register C_ETH_ADDR_MAC_DEST!");
end if;
when C_ETH_ADDR_MAC_SRC =>
if v_mac_src_byte < 6 then
mac_src_addr <= mac_src_addr(39 downto 0) & sbi_wdata;
v_mac_src_byte := v_mac_src_byte + 1;
else
alert(WARNING, "Ethernet MAC: Overwriting register C_ETH_ADDR_MAC_SRC!");
end if;
when C_ETH_ADDR_PAY_LEN =>
if v_pay_len_byte < 2 then
payload_len <= payload_len(7 downto 0) & sbi_wdata;
v_pay_len_byte := v_pay_len_byte + 1;
else
alert(WARNING, "Ethernet MAC: Overwriting register C_ETH_ADDR_PAY_LEN!");
end if;
when C_ETH_ADDR_PAYLOAD =>
if v_payload_byte < payload_len_int then
payload(v_payload_byte) <= sbi_wdata;
v_payload_byte := v_payload_byte + 1;
else
alert(WARNING, "Ethernet MAC: Overwriting register C_ETH_ADDR_PAYLOAD!");
end if;
-- Once a complete frame is written, it will be sent via the GMII interface.
if v_payload_byte = payload_len_int then
v_mac_dest_byte := 0;
v_mac_src_byte := 0;
v_pay_len_byte := 0;
v_payload_byte := 0;
frame_ready <= '1';
end if;
when C_ETH_ADDR_DUMMY =>
dummy_reg <= sbi_wdata;
when others =>
alert(ERROR, "Ethernet MAC: SBI write address " & to_hstring(sbi_addr) & " not supported!");
end case;
end if;
if frame_sent = '1' then
frame_ready <= '0';
end if;
end if;
end process p_sbi_write_regs;
-- Read the Ethernet MAC dummy register
p_sbi_read_regs : process(sbi_cs, sbi_rena, sbi_addr)
begin
sbi_rdata <= (others => '0');
read_ready <= '0';
if sbi_cs = '1' and sbi_rena = '1' then
-- Decode read address
case sbi_addr is
when C_ETH_ADDR_DUMMY =>
sbi_rdata <= dummy_reg;
read_ready <= '1';
when others =>
alert(ERROR, "Ethernet MAC: SBI read address " & to_hstring(sbi_addr) & " not supported!");
end case;
end if;
end process p_sbi_read_regs;
-- Make sure to receive and send the padding bytes
payload_len_int <= to_integer(unsigned(payload_len)) when to_integer(unsigned(payload_len)) > C_MIN_PAYLOAD_LENGTH
else C_MIN_PAYLOAD_LENGTH;
-- Only accept new SBI writes after the frame is transmitted
sbi_ready <= not frame_ready or read_ready;
------------------------------------------------------------------------------------
-- GMII interface
------------------------------------------------------------------------------------
-- Send Ethernet frames once they have been completely stored in the internal registers.
p_gmii_send_frame : process(clk)
variable v_byte_idx : integer range 0 to C_MAX_PACKET_LENGTH := 0;
variable v_packet : t_byte_array(0 to C_MAX_PACKET_LENGTH-1);
variable v_crc_32 : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(clk) then
txd <= (others => '0');
txen <= '0';
frame_sent <= '0';
case fsm_tx is
when s_idle =>
if frame_ready = '1' and frame_sent = '0' then
-- Preamble (LSb first)
v_packet(0 to 6) := convert_slv_to_byte_array(C_PREAMBLE, LOWER_BYTE_LEFT);
-- SFD (LSb first)
v_packet(7) := C_SFD;
-- MAC destination (LSb first)
v_packet(8 to 13) := convert_slv_to_byte_array(mac_dest_addr, LOWER_BYTE_LEFT);
-- MAC source (LSb first)
v_packet(14 to 19) := convert_slv_to_byte_array(mac_src_addr, LOWER_BYTE_LEFT);
-- Payload length (LSb first)
v_packet(20 to 21) := convert_slv_to_byte_array(payload_len, LOWER_BYTE_LEFT);
-- Payload (LSb first)
v_packet(22 to 22+payload_len_int-1) := payload(0 to payload_len_int-1);
-- Calculate the FCS with the MAC addresses, payload length and payload data
v_crc_32 := generate_crc_32(v_packet(8 to 22+payload_len_int-1));
-- Post complement the CRC according to Ethernet standard
v_crc_32 := not(v_crc_32);
-- FCS (MSb first). Convert slv to byte_array with MSB first and then reverse the bits in each byte so MSb is transmitted first
v_packet(22+payload_len_int to 22+payload_len_int+4-1) := reverse_vectors_in_array(convert_slv_to_byte_array(v_crc_32, LOWER_BYTE_LEFT));
v_byte_idx := 0;
fsm_tx <= s_send_pkt;
end if;
when s_send_pkt =>
txd <= v_packet(v_byte_idx);
txen <= '1';
if v_byte_idx = 22+payload_len_int+4-1 then
frame_sent <= '1';
fsm_tx <= s_idle;
else
v_byte_idx := v_byte_idx + 1;
end if;
end case;
end if;
end process p_gmii_send_frame;
-- Use the same clock for both interfaces
gtxclk <= clk;
end architecture behave; | mit | 22cbed63089ddcafca660aadea28ff0d | 0.52649 | 3.908308 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_3/part_1/top.vhd | 1 | 9,496 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (4 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant vga_width : integer := 1280;
constant vga_height : integer := 1024;
constant xwidth : integer := log2(vga_width);
constant ywidth : integer := log2(vga_height);
signal dbtn : std_logic_vector(4 downto 0);
signal clk_100MHz: std_logic;
signal clk_250MHz: std_logic;
signal ch1_x: std_logic_vector(xwidth-1 downto 0);
signal ch1_y: std_logic_vector(ywidth-1 downto 0);
signal ch1_trigger: std_logic_vector(ywidth-1 downto 0);
signal ch1_update: std_logic;
signal ch2_x: std_logic_vector(xwidth-1 downto 0);
signal ch2_y: std_logic_vector(ywidth-1 downto 0);
signal ch2_trigger: std_logic_vector(ywidth-1 downto 0);
signal ch2_update: std_logic;
signal vline: std_logic_vector(ywidth-1 downto 0);
signal vline_clear: std_logic;
signal vline_enb: std_logic;
signal sine_out: std_logic_vector(ywidth-1 downto 0);
signal cosine_out: std_logic_vector(ywidth-1 downto 0);
signal sw_buffer : std_logic_vector(7 downto 0);
signal valid: std_logic;
signal m_axis_data_tdata : std_logic_vector(15 downto 0) ;
signal m_axis_data_tdata_cosine : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_sine : std_logic_vector(ywidth-1 downto 0) := (others => '0');
-- Alias signals for each separate TDM channel (these are 1 cycle delayed relative to the above alias signals)
signal m_axis_data_channel : integer := 0; -- indicates TDM channel number of data master channel outputs
signal m_axis_data_tdata_cosine_c0 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c0 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c1 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c1 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c2 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c2 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c3 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c3 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c4 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c4 : std_logic_vector(ywidth-1 downto 0) := (others => '0');
signal time_val: std_logic_vector(6 downto 0);
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
component trigger is
generic(
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port ( clk_100MHz : in STD_LOGIC;
input: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
value: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
valid: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
time_val: in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
component cro is
generic(
width:integer := 16;
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port ( clk_100MHz : in STD_LOGIC;
ch1_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch1_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch1_update: in STD_LOGIC;
ch2_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch2_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch2_update: in STD_LOGIC;
vline: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end component;
COMPONENT dds
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, open);
cro1: cro port map(clk_100MHz,ch1_x,ch1_y,ch1_update,ch2_x,ch2_y,ch2_update,vline,VGA_DATA,VGA_HSYNC,VGA_VSYNC);
trigger1: trigger port map(clk_100MHz,ch1_y,ch1_trigger,ch1_update,ch1_x,time_val);
trigger2: trigger port map(clk_100MHz,ch2_y,ch2_trigger,ch2_update,ch2_x,time_val);
dbounce1: debounce port map(clk_100MHz, btn(0), dbtn(0));
dbounce2: debounce port map(clk_100MHz, btn(4), dbtn(4));
dbounce3: debounce port map(clk_100MHz, btn(1), dbtn(1));
dbounce4: debounce port map(clk_100MHz, btn(3), dbtn(3));
pulser1: pulser generic map(delay=>100000000) port map(clk_100MHz,vline_enb,vline_clear);
sig_gen: dds
PORT MAP (
aclk => clk_100MHz,
m_axis_data_tvalid => valid,
m_axis_data_tdata => m_axis_data_tdata
);
ch1_y <= std_logic_vector(resize(signed(sine_out(7 downto 0)),ywidth));
ch2_y <= std_logic_vector(resize(signed(cosine_out(7 downto 0)),ywidth));
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
if(dbtn(0) = '1')then
ch1_trigger <= std_logic_vector(signed(ch1_trigger) + 1);
vline <= ch1_trigger;
vline_enb <= '1';
elsif(dbtn(4) = '1')then
ch1_trigger <= std_logic_vector(signed(ch1_trigger) - 1);
vline <= ch1_trigger;
vline_enb <= '1';
elsif(vline_enb = '1' and vline_clear = '1') then
vline <= std_logic_vector(to_signed(vga_height/2,ywidth));
vline_enb <= '0';
end if;
if(dbtn(1) = '1')then
time_val <= time_val+1;
elsif(dbtn(3) = '1')then
time_val <= time_val -1;
end if;
sw_buffer <= sw;
led <= sw_buffer;
if(sw_buffer(6 downto 4) = 0)then
sine_out <= m_axis_data_tdata_sine_c0;
cosine_out <= m_axis_data_tdata_cosine_c0;
elsif(sw_buffer(6 downto 4) = 1)then
sine_out <= m_axis_data_tdata_sine_c1;
cosine_out <= m_axis_data_tdata_cosine_c1;
elsif(sw_buffer(6 downto 4) = 2)then
sine_out <= m_axis_data_tdata_sine_c2;
cosine_out <= m_axis_data_tdata_cosine_c2;
elsif(sw_buffer(6 downto 4) = 3)then
sine_out <= m_axis_data_tdata_sine_c3;
cosine_out <= m_axis_data_tdata_cosine_c3;
else
sine_out <= m_axis_data_tdata_sine_c4;
cosine_out <= m_axis_data_tdata_cosine_c4;
end if;
if valid = '1' then
if m_axis_data_channel = 4 then
m_axis_data_channel <= 0;
else
m_axis_data_channel <= m_axis_data_channel + 1;
end if;
if m_axis_data_channel = 0 then
m_axis_data_tdata_cosine_c0(7 downto 0) <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c0(7 downto 0) <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 1 then
m_axis_data_tdata_cosine_c1(7 downto 0) <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c1(7 downto 0) <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 2 then
m_axis_data_tdata_cosine_c2(7 downto 0) <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c2(7 downto 0) <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 3 then
m_axis_data_tdata_cosine_c3(7 downto 0) <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c3(7 downto 0) <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 4 then
m_axis_data_tdata_cosine_c4(7 downto 0) <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c4(7 downto 0) <= m_axis_data_tdata(15 downto 8);
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 348e42657200fb8d503da5c3a704dbf5 | 0.589195 | 3.079118 | false | false | false | false |
UVVM/UVVM_All | uvvm_util/src/data_stack_pkg.vhd | 1 | 8,653 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
use work.data_queue_pkg.all;
package data_stack_pkg is
shared variable shared_data_stack : t_data_queue;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the stack.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the stack
--
-- - Returns: The index of the initiated stack (natural).
-- Returns 0 on error.
--
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the stack
--
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_stack_push
------------------------------------------
-- This procedure puts data into a stack with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the stack size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_stack_pop
------------------------------------------
-- This function returns the data from the stack
-- and removes the returned data from the stack.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the stack size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_flush
------------------------------------------
-- This procedure empties the stack given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be flushed.
--
procedure uvvm_stack_flush(
buffer_index : natural
);
------------------------------------------
-- uvvm_stack_peek
------------------------------------------
-- This function returns the data from the stack
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the stack size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The number of elements occupying the stack (natural).
--
--
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_stack_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the stack (natural).
--
--
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural;
end package data_stack_pkg;
package body data_stack_pkg is
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_stack.init_queue(buffer_size_in_bits, "UVVM_STACK");
end function;
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_stack.init_queue(buffer_index, buffer_size_in_bits, "UVVM_STACK");
end procedure;
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
) is
begin
shared_data_stack.push_back(buffer_index,data);
end procedure;
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.pop_back(buffer_index, entry_size_in_bits);
end function;
procedure uvvm_stack_flush(
buffer_index : natural
) is
begin
shared_data_stack.flush(buffer_index);
end procedure;
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.peek_back(buffer_index, entry_size_in_bits);
end function;
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_stack.get_count(buffer_idx);
end function;
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural is
begin
return shared_data_stack.get_queue_count_max(buffer_index);
end function;
end package body data_stack_pkg;
| mit | b3de2ae33cfbc884d1fddc46c5a44189 | 0.532185 | 4.592887 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_3/part_1/ip/dds/dds_funcsim.vhdl | 1 | 218,390 | -- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 24 21:51:05 2014
-- Host : macbook running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_3/part_1/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 44 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 44 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 2 downto 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 44 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "dds_compiler_v6_0_viv";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 45;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 5;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 8;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 8;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "100000000000000000000000000000000000,1000000000000000000000000000000000000,10000000000000000000000000000000000000,100000000000000000000000000000000000000,1000000000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0_viv__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal A : STD_LOGIC_VECTOR ( 2 downto 0 );
signal chan_addr_del1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/first_q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\ : STD_LOGIC_VECTOR ( 45 downto 0 );
signal \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\ : STD_LOGIC_VECTOR ( 45 downto 0 );
signal \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \i_dds/Q1_out\ : STD_LOGIC;
signal \i_dds/Q2_out\ : STD_LOGIC;
signal \i_dds/chan_addr\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \i_dds/i_rdy.rdy_logic/i_multi_channel.i_non_trivial_lat.i_rdy/first_q\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \i_dds/i_rdy.rdy_logic/i_multi_channel.i_non_trivial_lat.i_rdy/first_q\ : signal is "true";
signal \i_dds/i_rdy.rdy_logic/pre_rdy\ : STD_LOGIC;
signal \i_dds/next_chan\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \i_has_nd_rdy_pipe.channel_pipe/first_q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \i_has_nd_rdy_pipe.valid_phase_read_del/first_q\ : STD_LOGIC;
attribute RTL_KEEP of \i_has_nd_rdy_pipe.valid_phase_read_del/first_q\ : signal is "true";
signal master_count : STD_LOGIC_VECTOR ( 2 downto 0 );
signal mutant_x_op : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[45]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_3\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_4\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_5\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/i_rdy.rdy_logic/mutant_x_op[0]_i_1\ : STD_LOGIC;
signal \n_0_i_dds/i_rdy.rdy_logic/mutant_x_op[1]_i_1\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\ : STD_LOGIC;
signal \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\ : STD_LOGIC;
signal \n_0_master_channel_count.master_count[0]_i_1\ : STD_LOGIC;
signal \n_0_master_channel_count.master_count[1]_i_1\ : STD_LOGIC;
signal \n_0_master_channel_count.master_count[2]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\ : STD_LOGIC;
signal \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\ : STD_LOGIC;
signal \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\ : STD_LOGIC;
signal \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\ : STD_LOGIC;
signal \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1\ : STD_LOGIC;
signal \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\ : STD_LOGIC;
signal \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\ : STD_LOGIC;
signal \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\ : STD_LOGIC;
signal \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 45 downto 0 );
signal \pipe[2]\ : STD_LOGIC;
signal ram_op : STD_LOGIC_VECTOR ( 45 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_42_45_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_42_45_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute keep : string;
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[10]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[11]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[12]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[13]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[14]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[15]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[16]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[17]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[18]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[19]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[20]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[21]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[22]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[23]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[24]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[25]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[26]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[27]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[28]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[29]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[30]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[31]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[32]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[33]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[34]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[35]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[36]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[37]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[38]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[39]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[40]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[41]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[42]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[43]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[44]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[45]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[9]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[10]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[11]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[12]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[13]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[14]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[15]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[16]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[17]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[18]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[19]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[20]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[21]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[22]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[23]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[24]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[25]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[26]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[27]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[28]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[29]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[30]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[31]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[32]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[33]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[34]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[35]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[36]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[37]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[38]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[39]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[40]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[41]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[42]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[43]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[44]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[45]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[9]\ : label is "yes";
attribute box_type : string;
attribute box_type of \i_dds/I_PHASEGEN.i_multichan.i_chan_addr_reg_ext.i_char_addr_reg[1].i_reg\ : label is "PRIMITIVE";
attribute box_type of \i_dds/I_PHASEGEN.i_multichan.i_chan_addr_reg_ext.i_char_addr_reg[2].i_reg\ : label is "PRIMITIVE";
attribute box_type of \i_dds/I_PHASEGEN.i_multichan.i_low_reg\ : label is "PRIMITIVE";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : label is "{SYNTH-6 {cell inst1}}{SYNTH-6 {cell inst1}}";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : label is 35;
attribute keep of \i_dds/i_rdy.rdy_logic/i_multi_channel.i_non_trivial_lat.i_rdy/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \i_dds/i_rdy.rdy_logic/mutant_x_op[1]_i_1\ : label is "soft_lutpair1";
attribute keep of \i_has_nd_rdy_pipe.channel_pipe/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \i_has_nd_rdy_pipe.channel_pipe/opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \i_has_nd_rdy_pipe.channel_pipe/opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute SOFT_HLUTNM of \master_channel_count.master_count[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \master_channel_count.master_count[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1\ : label is "soft_lutpair1";
begin
debug_axi_chan_in(2) <= \<const0>\;
debug_axi_chan_in(1) <= \<const0>\;
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(44) <= \<const0>\;
debug_axi_pinc_in(43) <= \<const0>\;
debug_axi_pinc_in(42) <= \<const0>\;
debug_axi_pinc_in(41) <= \<const0>\;
debug_axi_pinc_in(40) <= \<const0>\;
debug_axi_pinc_in(39) <= \<const0>\;
debug_axi_pinc_in(38) <= \<const0>\;
debug_axi_pinc_in(37) <= \<const0>\;
debug_axi_pinc_in(36) <= \<const0>\;
debug_axi_pinc_in(35) <= \<const0>\;
debug_axi_pinc_in(34) <= \<const0>\;
debug_axi_pinc_in(33) <= \<const0>\;
debug_axi_pinc_in(32) <= \<const0>\;
debug_axi_pinc_in(31) <= \<const0>\;
debug_axi_pinc_in(30) <= \<const0>\;
debug_axi_pinc_in(29) <= \<const0>\;
debug_axi_pinc_in(28) <= \<const0>\;
debug_axi_pinc_in(27) <= \<const0>\;
debug_axi_pinc_in(26) <= \<const0>\;
debug_axi_pinc_in(25) <= \<const0>\;
debug_axi_pinc_in(24) <= \<const0>\;
debug_axi_pinc_in(23) <= \<const0>\;
debug_axi_pinc_in(22) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(44) <= \<const0>\;
debug_axi_poff_in(43) <= \<const0>\;
debug_axi_poff_in(42) <= \<const0>\;
debug_axi_poff_in(41) <= \<const0>\;
debug_axi_poff_in(40) <= \<const0>\;
debug_axi_poff_in(39) <= \<const0>\;
debug_axi_poff_in(38) <= \<const0>\;
debug_axi_poff_in(37) <= \<const0>\;
debug_axi_poff_in(36) <= \<const0>\;
debug_axi_poff_in(35) <= \<const0>\;
debug_axi_poff_in(34) <= \<const0>\;
debug_axi_poff_in(33) <= \<const0>\;
debug_axi_poff_in(32) <= \<const0>\;
debug_axi_poff_in(31) <= \<const0>\;
debug_axi_poff_in(30) <= \<const0>\;
debug_axi_poff_in(29) <= \<const0>\;
debug_axi_poff_in(28) <= \<const0>\;
debug_axi_poff_in(27) <= \<const0>\;
debug_axi_poff_in(26) <= \<const0>\;
debug_axi_poff_in(25) <= \<const0>\;
debug_axi_poff_in(24) <= \<const0>\;
debug_axi_poff_in(23) <= \<const0>\;
debug_axi_poff_in(22) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(44) <= \<const0>\;
debug_phase(43) <= \<const0>\;
debug_phase(42) <= \<const0>\;
debug_phase(41) <= \<const0>\;
debug_phase(40) <= \<const0>\;
debug_phase(39) <= \<const0>\;
debug_phase(38) <= \<const0>\;
debug_phase(37) <= \<const0>\;
debug_phase(36) <= \<const0>\;
debug_phase(35) <= \<const0>\;
debug_phase(34) <= \<const0>\;
debug_phase(33) <= \<const0>\;
debug_phase(32) <= \<const0>\;
debug_phase(31) <= \<const0>\;
debug_phase(30) <= \<const0>\;
debug_phase(29) <= \<const0>\;
debug_phase(28) <= \<const0>\;
debug_phase(27) <= \<const0>\;
debug_phase(26) <= \<const0>\;
debug_phase(25) <= \<const0>\;
debug_phase(24) <= \<const0>\;
debug_phase(23) <= \<const0>\;
debug_phase(22) <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_missing <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const1>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/Q2_out\,
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/first_q\(0),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/Q1_out\,
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/first_q\(1),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/chan_addr\(2),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_phase_adj_multi.i_prog_freq/first_q\(2),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(0),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(0),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(10),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(10),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(11),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(11),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(12),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(12),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(13),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(13),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(14),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(14),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(15),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(15),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(16),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(16),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(17),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(17),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(18),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(18),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(19),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(19),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(1),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(1),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(20),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(20),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(21),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(21),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(22),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(22),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(23),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(23),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(24),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(24),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(25),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(25),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(26),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(26),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(27),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(27),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(28),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(28),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(29),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(29),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(2),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(2),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(30),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(30),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(31),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(31),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(32),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(32),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(33),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(33),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(34),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(34),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(35),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(35),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(36),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(36),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(37),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(37),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(38),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(38),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(39),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(39),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(3),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(3),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(40),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(40),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(41),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(41),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(42),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(42),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(43),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(43),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(44),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(44),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(45),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(45),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(4),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(4),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(5),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(5),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(6),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(6),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(7),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(7),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(8),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(8),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => p_0_in(9),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(9),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(0),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(0),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(10),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(10),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(11),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(11),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(12),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(12),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(13),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(13),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(14),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(14),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(15),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(15),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(16),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(16),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(17),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(17),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(18),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(18),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(19),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(19),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(1),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(1),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(20),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(20),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(21),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(21),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(22),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(22),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(23),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(23),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(24),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(24),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(25),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(25),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(26),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(26),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(27),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(27),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(28),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(28),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(29),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(29),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(2),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(2),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(30),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(30),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(31),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(31),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(32),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(32),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(33),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(33),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(34),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(34),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(35),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(35),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(36),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(36),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(37),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(37),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(38),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(38),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(39),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(39),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(3),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(3),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(40),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(40),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(41),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(41),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(42),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(42),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(43),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(43),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(44),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(44),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(45),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(45),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(4),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(4),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(5),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(5),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(6),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(6),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(7),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(7),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(8),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(8),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => ram_op(9),
Q => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(9),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_0_5\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(1 downto 0),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(3 downto 2),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(5 downto 4),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(1 downto 0),
DOB(1 downto 0) => ram_op(3 downto 2),
DOC(1 downto 0) => ram_op(5 downto 4),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_0_5_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_12_17\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(13 downto 12),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(15 downto 14),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(17 downto 16),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(13 downto 12),
DOB(1 downto 0) => ram_op(15 downto 14),
DOC(1 downto 0) => ram_op(17 downto 16),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_12_17_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_18_23\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(19 downto 18),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(21 downto 20),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(23 downto 22),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(19 downto 18),
DOB(1 downto 0) => ram_op(21 downto 20),
DOC(1 downto 0) => ram_op(23 downto 22),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_18_23_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_24_29\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(25 downto 24),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(27 downto 26),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(29 downto 28),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(25 downto 24),
DOB(1 downto 0) => ram_op(27 downto 26),
DOC(1 downto 0) => ram_op(29 downto 28),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_24_29_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_30_35\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(31 downto 30),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(33 downto 32),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(35 downto 34),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(31 downto 30),
DOB(1 downto 0) => ram_op(33 downto 32),
DOC(1 downto 0) => ram_op(35 downto 34),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_30_35_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_36_41\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(37 downto 36),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(39 downto 38),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(41 downto 40),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(37 downto 36),
DOB(1 downto 0) => ram_op(39 downto 38),
DOC(1 downto 0) => ram_op(41 downto 40),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_36_41_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_42_45\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(43 downto 42),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(45 downto 44),
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(43 downto 42),
DOB(1 downto 0) => ram_op(45 downto 44),
DOC(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_42_45_DOC_UNCONNECTED\(1 downto 0),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_42_45_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_6_11\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2) => \i_dds/chan_addr\(2),
ADDRA(1) => \i_dds/Q1_out\,
ADDRA(0) => \i_dds/Q2_out\,
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2) => \i_dds/chan_addr\(2),
ADDRB(1) => \i_dds/Q1_out\,
ADDRB(0) => \i_dds/Q2_out\,
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2) => \i_dds/chan_addr\(2),
ADDRC(1) => \i_dds/Q1_out\,
ADDRC(0) => \i_dds/Q2_out\,
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2 downto 0) => A(2 downto 0),
DIA(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(7 downto 6),
DIB(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(9 downto 8),
DIC(1 downto 0) => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(11 downto 10),
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1 downto 0) => ram_op(7 downto 6),
DOB(1 downto 0) => ram_op(9 downto 8),
DOC(1 downto 0) => ram_op(11 downto 10),
DOD(1 downto 0) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/the_ram_reg_0_7_6_11_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const1>\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(11),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(10),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(9),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(8),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(15),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(14),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(13),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(12),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(19),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(18),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(17),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(16),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(23),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(22),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(21),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(20),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(27),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(26),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(25),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(24),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(31),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(30),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(29),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(28),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(35),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(34),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(33),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(32),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(39),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(38),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(37),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(36),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(3),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(2),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(1),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(0),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(43),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(42),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(41),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(40),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[45]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(44),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[45]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(7),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(6),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_3\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(5),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_4\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
I1 => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_acc_ram/i_ram_reg/first_q\(4),
O => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DI(2) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DI(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DI(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
O(3 downto 0) => p_0_in(11 downto 8),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[11]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[11]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DI(2) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DI(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DI(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
O(3 downto 0) => p_0_in(15 downto 12),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[15]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[15]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DI(2) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DI(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DI(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
O(3 downto 0) => p_0_in(19 downto 16),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[19]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[19]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DI(2) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DI(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DI(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
O(3 downto 0) => p_0_in(23 downto 20),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[23]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[23]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DI(2) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DI(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DI(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
O(3 downto 0) => p_0_in(27 downto 24),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[27]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[27]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DI(2) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DI(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DI(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
O(3 downto 0) => p_0_in(31 downto 28),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[31]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[31]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DI(2) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DI(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DI(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
O(3 downto 0) => p_0_in(35 downto 32),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[35]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[35]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DI(2) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DI(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DI(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
O(3 downto 0) => p_0_in(39 downto 36),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[39]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \<const0>\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DI(2) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DI(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DI(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
O(3 downto 0) => p_0_in(3 downto 0),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[3]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[39]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
DI(2) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
DI(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DI(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
O(3 downto 0) => p_0_in(43 downto 40),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[43]_i_5\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[43]_i_1\,
CO(3 downto 1) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1\,
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
O(3 downto 2) => \NLW_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[45]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_0_in(45 downto 44),
S(3) => \<const0>\,
S(2) => \<const0>\,
S(1) => \<const0>\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[45]_i_2\
);
\i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[3]_i_1\,
CO(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\,
CO(2) => \n_1_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\,
CO(1) => \n_2_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\,
CO(0) => \n_3_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q_reg[7]_i_1\,
CYINIT => \<const0>\,
DI(3) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DI(2) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DI(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DI(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
O(3 downto 0) => p_0_in(7 downto 4),
S(3) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_2\,
S(2) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_3\,
S(1) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_4\,
S(0) => \n_0_i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_multi_channel.i_accum/opt_has_pipe.first_q[7]_i_5\
);
\i_dds/I_PHASEGEN.i_multichan.chan_addr_del1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/Q2_out\,
Q => chan_addr_del1(0),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.chan_addr_del1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/Q1_out\,
Q => chan_addr_del1(1),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.chan_addr_del1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/chan_addr\(2),
Q => chan_addr_del1(2),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.chan_addr_del2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => chan_addr_del1(0),
Q => A(0),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.chan_addr_del2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => chan_addr_del1(1),
Q => A(1),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.chan_addr_del2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => chan_addr_del1(2),
Q => A(2),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.i_chan_addr_reg_ext.i_char_addr_reg[1].i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/next_chan\(1),
Q => \i_dds/Q1_out\,
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.i_chan_addr_reg_ext.i_char_addr_reg[2].i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/next_chan\(2),
Q => \i_dds/chan_addr\(2),
R => \<const0>\
);
\i_dds/I_PHASEGEN.i_multichan.i_low_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_S_INVERTED => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/next_chan\(0),
Q => \i_dds/Q2_out\,
S => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(37),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(0),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(38),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(1),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(39),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(2),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(40),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(3),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(41),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(4),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(42),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(5),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(43),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(6),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(44),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(7),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const0>\,
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(8),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(37),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(0),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(38),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(1),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(39),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(2),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(40),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(3),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(41),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(4),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(42),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(5),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(43),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(6),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_fabric.i_common.i_phase_acc/first_q\(44),
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(7),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(8),
R => \<const0>\
);
\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"002F002C0029002600230020001D001A001700140011000E000B000800050002",
INIT_01 => X"0058005600530051004F004C004A004700450042003F003D003A003700340032",
INIT_02 => X"0074007300710070006E006D006B006A00680066006400620060005E005C005A",
INIT_03 => X"007E007E007E007E007D007D007C007C007B007B007A00790078007700760075",
INIT_04 => X"00750076007700780079007A007B007B007C007C007D007D007E007E007E007E",
INIT_05 => X"005A005C005E00600062006400660068006A006B006D006E0070007100730074",
INIT_06 => X"003200340037003A003D003F004200450047004A004C004F0051005300560058",
INIT_07 => X"000200050008000B000E001100140017001A001D0020002300260029002C002F",
INIT_08 => X"00D100D400D700DA00DD00E000E300E600E900EC00EF00F200F500F800FB00FE",
INIT_09 => X"00A800AA00AD00AF00B100B400B600B900BB00BE00C100C300C600C900CC00CE",
INIT_0A => X"008C008D008F009000920093009500960098009A009C009E00A000A200A400A6",
INIT_0B => X"00820082008200820083008300840084008500850086008700880089008A008B",
INIT_0C => X"008B008A00890088008700860085008500840084008300830082008200820082",
INIT_0D => X"00A600A400A200A0009E009C009A009800960095009300920090008F008D008C",
INIT_0E => X"00CE00CC00C900C600C300C100BE00BB00B900B600B400B100AF00AD00AA00A8",
INIT_0F => X"00FE00FB00F800F500F200EF00EC00E900E600E300E000DD00DA00D700D400D1",
INIT_10 => X"00750076007700780079007A007B007B007C007C007D007D007E007E007E007E",
INIT_11 => X"005A005C005E00600062006400660068006A006B006D006E0070007100730074",
INIT_12 => X"003200340037003A003D003F004200450047004A004C004F0051005300560058",
INIT_13 => X"000200050008000B000E001100140017001A001D0020002300260029002C002F",
INIT_14 => X"00D100D400D700DA00DD00E000E300E600E900EC00EF00F200F500F800FB00FE",
INIT_15 => X"00A800AA00AD00AF00B100B400B600B900BB00BE00C100C300C600C900CC00CE",
INIT_16 => X"008C008D008F009000920093009500960098009A009C009E00A000A200A400A6",
INIT_17 => X"00820082008200820083008300840084008500850086008700880089008A008B",
INIT_18 => X"008B008A00890088008700860085008500840084008300830082008200820082",
INIT_19 => X"00A600A400A200A0009E009C009A009800960095009300920090008F008D008C",
INIT_1A => X"00CE00CC00C900C600C300C100BE00BB00B900B600B400B100AF00AD00AA00A8",
INIT_1B => X"00FE00FB00F800F500F200EF00EC00E900E600E300E000DD00DA00D700D400D1",
INIT_1C => X"002F002C0029002600230020001D001A001700140011000E000B000800050002",
INIT_1D => X"0058005600530051004F004C004A004700450042003F003D003A003700340032",
INIT_1E => X"0074007300710070006E006D006B006A00680066006400620060005E005C005A",
INIT_1F => X"007E007E007E007E007D007D007C007C007B007B007A00790078007700760075",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13) => \<const0>\,
ADDRARDADDR(12 downto 4) => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_b/first_q\(8 downto 0),
ADDRARDADDR(3) => \<const0>\,
ADDRARDADDR(2) => \<const0>\,
ADDRARDADDR(1) => \<const0>\,
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(13) => \<const0>\,
ADDRBWRADDR(12 downto 4) => \i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_addr_reg_a/first_q\(8 downto 0),
ADDRBWRADDR(3) => \<const0>\,
ADDRBWRADDR(2) => \<const0>\,
ADDRBWRADDR(1) => \<const0>\,
ADDRBWRADDR(0) => \<const0>\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const1>\,
DIADI(6) => \<const1>\,
DIADI(5) => \<const1>\,
DIADI(4) => \<const1>\,
DIADI(3) => \<const1>\,
DIADI(2) => \<const1>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(15 downto 8) => \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => m_axis_data_tdata(7 downto 0),
DOBDO(15 downto 8) => \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => m_axis_data_tdata(15 downto 8),
DOPADOP(1 downto 0) => \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \<const1>\,
ENBWREN => \<const1>\,
REGCEAREGCE => \<const0>\,
REGCEB => \<const0>\,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_dds/i_rdy.rdy_logic/i_multi_channel.i_non_trivial_lat.i_rdy/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_dds/i_rdy.rdy_logic/pre_rdy\,
Q => \i_dds/i_rdy.rdy_logic/i_multi_channel.i_non_trivial_lat.i_rdy/first_q\,
R => \<const0>\
);
\i_dds/i_rdy.rdy_logic/mutant_x_op[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
O => \n_0_i_dds/i_rdy.rdy_logic/mutant_x_op[0]_i_1\
);
\i_dds/i_rdy.rdy_logic/mutant_x_op[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
O => \n_0_i_dds/i_rdy.rdy_logic/mutant_x_op[1]_i_1\
);
\i_dds/i_rdy.rdy_logic/mutant_x_op_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_i_dds/i_rdy.rdy_logic/mutant_x_op[0]_i_1\,
Q => mutant_x_op(0),
R => \<const0>\
);
\i_dds/i_rdy.rdy_logic/mutant_x_op_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_i_dds/i_rdy.rdy_logic/mutant_x_op[1]_i_1\,
Q => mutant_x_op(1),
R => \<const0>\
);
\i_dds/next_chan_inferred_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \i_dds/Q1_out\,
I1 => \i_dds/chan_addr\(2),
I2 => \i_dds/Q2_out\,
O => \i_dds/next_chan\(3)
);
\i_dds/next_chan_inferred_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"68"
)
port map (
I0 => \i_dds/chan_addr\(2),
I1 => \i_dds/Q2_out\,
I2 => \i_dds/Q1_out\,
O => \i_dds/next_chan\(2)
);
\i_dds/next_chan_inferred_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \i_dds/Q1_out\,
I1 => \i_dds/Q2_out\,
O => \i_dds/next_chan\(1)
);
\i_has_nd_rdy_pipe.channel_pipe/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => master_count(0),
Q => \i_has_nd_rdy_pipe.channel_pipe/first_q\(0),
R => \<const0>\
);
\i_has_nd_rdy_pipe.channel_pipe/opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => master_count(1),
Q => \i_has_nd_rdy_pipe.channel_pipe/first_q\(1),
R => \<const0>\
);
\i_has_nd_rdy_pipe.channel_pipe/opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => master_count(2),
Q => \i_has_nd_rdy_pipe.channel_pipe/first_q\(2),
R => \<const0>\
);
\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => \i_has_nd_rdy_pipe.valid_phase_read_del/first_q\,
R => \<const0>\
);
\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[2].pipe_reg[2][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \i_has_nd_rdy_pipe.valid_phase_read_del/first_q\,
Q => \pipe[2]\,
R => \<const0>\
);
\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[3].pipe_reg[3][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \pipe[2]\,
Q => m_axis_data_tvalid,
R => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_0_5_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_12_17_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_18_23_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_24_29_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000002",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_30_35_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000024",
INIT_B => X"0000000000000240",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_36_41_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
DOB(1) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44_DOB_UNCONNECTED\(1),
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44\,
DOC(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44_DOC_UNCONNECTED\(1 downto 0),
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_42_44_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4) => \<const0>\,
ADDRA(3) => \<const0>\,
ADDRA(2 downto 0) => master_count(2 downto 0),
ADDRB(4) => \<const0>\,
ADDRB(3) => \<const0>\,
ADDRB(2 downto 0) => master_count(2 downto 0),
ADDRC(4) => \<const0>\,
ADDRC(3) => \<const0>\,
ADDRC(2 downto 0) => master_count(2 downto 0),
ADDRD(4) => \<const0>\,
ADDRD(3) => \<const0>\,
ADDRD(2) => \<const0>\,
ADDRD(1) => \<const0>\,
ADDRD(0) => \<const0>\,
DIA(1) => \<const0>\,
DIA(0) => \<const0>\,
DIB(1) => \<const0>\,
DIB(0) => \<const0>\,
DIC(1) => \<const0>\,
DIC(0) => \<const0>\,
DID(1) => \<const0>\,
DID(0) => \<const0>\,
DOA(1) => \n_0_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DOA(0) => \n_1_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DOB(1) => \n_2_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DOB(0) => \n_3_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DOC(1) => \n_4_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DOC(0) => \n_5_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11\,
DOD(1 downto 0) => \NLW_i_pinc_poff_in.i_mult_channel_fixed_pinc.i_inc_ram/the_ram_reg_0_7_6_11_DOD_UNCONNECTED\(1 downto 0),
WCLK => aclk,
WE => \<const0>\
);
\master_channel_count.master_count[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => master_count(1),
I1 => master_count(2),
I2 => master_count(0),
O => \n_0_master_channel_count.master_count[0]_i_1\
);
\master_channel_count.master_count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => master_count(1),
I1 => master_count(0),
O => \n_0_master_channel_count.master_count[1]_i_1\
);
\master_channel_count.master_count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"68"
)
port map (
I0 => master_count(1),
I1 => master_count(0),
I2 => master_count(2),
O => \n_0_master_channel_count.master_count[2]_i_1\
);
\master_channel_count.master_count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_master_channel_count.master_count[0]_i_1\,
Q => master_count(0),
R => \<const0>\
);
\master_channel_count.master_count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_master_channel_count.master_count[1]_i_1\,
Q => master_count(1),
R => \<const0>\
);
\master_channel_count.master_count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_master_channel_count.master_count[2]_i_1\,
Q => master_count(2),
R => \<const0>\
);
next_chan_inferred_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => \i_dds/Q1_out\,
I1 => \i_dds/chan_addr\(2),
I2 => \i_dds/Q2_out\,
O => \i_dds/next_chan\(0)
);
\opt_has_pipe.first_q[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => mutant_x_op(0),
I1 => mutant_x_op(1),
O => \i_dds/i_rdy.rdy_logic/pre_rdy\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 44 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 44 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 2 downto 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 44 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 45;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 5;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0__parameterized0\ : entity is 3;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 8;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 8;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0__parameterized0\ : entity is 2;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0__parameterized0\ : entity is "100000000000000000000000000000000000,1000000000000000000000000000000000000,10000000000000000000000000000000000000,100000000000000000000000000000000000000,1000000000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 16;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 3;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 45;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS of i_synth : label is 5;
attribute C_CHAN_WIDTH of i_synth : label is 3;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 0;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 3;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 2;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 8;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 8;
attribute C_PHASE_INCREMENT of i_synth : label is 2;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "100000000000000000000000000000000000,1000000000000000000000000000000000000,10000000000000000000000000000000000000,100000000000000000000000000000000000000,1000000000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
debug_axi_resync_in <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
debug_axi_chan_in(2 downto 0) => debug_axi_chan_in(2 downto 0),
debug_axi_pinc_in(44 downto 0) => debug_axi_pinc_in(44 downto 0),
debug_axi_poff_in(44 downto 0) => debug_axi_poff_in(44 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => debug_core_nd,
debug_phase(44 downto 0) => debug_phase(44 downto 0),
debug_phase_nd => debug_phase_nd,
event_phase_in_invalid => event_phase_in_invalid,
event_pinc_invalid => event_pinc_invalid,
event_poff_invalid => event_poff_invalid,
event_s_config_tlast_missing => event_s_config_tlast_missing,
event_s_config_tlast_unexpected => event_s_config_tlast_unexpected,
event_s_phase_chanid_incorrect => event_s_phase_chanid_incorrect,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => event_s_phase_tlast_unexpected,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tuser(0) => m_axis_data_tuser(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => m_axis_phase_tdata(0),
m_axis_phase_tlast => m_axis_phase_tlast,
m_axis_phase_tready => m_axis_phase_tready,
m_axis_phase_tuser(0) => m_axis_phase_tuser(0),
m_axis_phase_tvalid => m_axis_phase_tvalid,
s_axis_config_tdata(0) => s_axis_config_tdata(0),
s_axis_config_tlast => s_axis_config_tlast,
s_axis_config_tready => s_axis_config_tready,
s_axis_config_tvalid => s_axis_config_tvalid,
s_axis_phase_tdata(0) => s_axis_phase_tdata(0),
s_axis_phase_tlast => s_axis_phase_tlast,
s_axis_phase_tready => s_axis_phase_tready,
s_axis_phase_tuser(0) => s_axis_phase_tuser(0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2013.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=45,C_CHANNELS=5,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=3,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=8,C_PHASE_ANGLE_WIDTH=8,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=100000000000000000000000000000000000_1000000000000000000000000000000000000_10000000000000000000000000000000000000_100000000000000000000000000000000000000_1000000000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=16,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=3}";
end dds;
architecture STRUCTURE of dds is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 44 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 44 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 44 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 45;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 5;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 3;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 8;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 8;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 2;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "100000000000000000000000000000000000,1000000000000000000000000000000000000,10000000000000000000000000000000000000,100000000000000000000000000000000000000,1000000000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
aclken => \<const1>\,
aresetn => \<const1>\,
debug_axi_chan_in(2 downto 0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(2 downto 0),
debug_axi_pinc_in(44 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(44 downto 0),
debug_axi_poff_in(44 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(44 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(44 downto 0) => NLW_U0_debug_phase_UNCONNECTED(44 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => \<const0>\,
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => \<const0>\,
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => \<const0>\,
s_axis_config_tlast => \<const0>\,
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => \<const0>\,
s_axis_phase_tdata(0) => \<const0>\,
s_axis_phase_tlast => \<const0>\,
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => \<const0>\,
s_axis_phase_tvalid => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| gpl-2.0 | 3f3461aa74de67b3a653bc3c07cbb3e7 | 0.642813 | 2.535144 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 1a46692b6267dcfa4414b9ee1a88839a | 0.924483 | 1.907506 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/mux_bus8.vhd | 3 | 14,388 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8912)
`protect data_block
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`protect end_protected
| gpl-2.0 | e7c0588cf4d0a9e201312fb62776b133 | 0.934598 | 1.87417 | false | false | false | false |
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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 44832)
`protect data_block
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`protect end_protected
| gpl-2.0 | 15fdf55b8419d311e97851980302b42b | 0.950931 | 1.818079 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_addsub_v12_0/hdl/c_addsub_v12_0_lut6_legacy.vhd | 3 | 78,757 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect end_protected
| gpl-2.0 | 51f903475eeb96cb94557225f59ddce8 | 0.952652 | 1.818742 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/c_addsub_v12_0/hdl/c_addsub_v12_0_viv_comp.vhd | 2 | 9,654 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5408)
`protect data_block
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`protect end_protected
| gpl-2.0 | a32f90a3b23adeb7feacf56e611d751e | 0.924384 | 1.913957 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/butterfly_dsp48e.vhd | 2 | 35,787 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24752)
`protect data_block
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`protect end_protected
| gpl-2.0 | 75eaf7a632f627abb2ee0a85f7d451eb | 0.947635 | 1.831005 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/r22_ovflo.vhd | 3 | 8,402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4480)
`protect data_block
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`protect end_protected
| gpl-2.0 | 1724c9ac03b51b87ebf8ed705a3ca92b | 0.918234 | 1.924857 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_fma/flt_fma_mul.vhd | 3 | 12,896 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7808)
`protect data_block
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`protect end_protected
| gpl-2.0 | 79f4cb80b4c6fafe05e44c8cc34daaec | 0.929203 | 1.862238 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/bfly_byp.vhd | 3 | 9,934 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
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| gpl-2.0 | f5ef22064fe36f057a877587344d3497 | 0.926918 | 1.911487 | false | false | false | false |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi/solution1/syn/vhdl/contact_discoverydEe.vhd | 3 | 3,101 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverydEe_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 1;
awidth : integer := 9;
mem_size : integer := 300
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverydEe_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverydEe is
generic (
DataWidth : INTEGER := 1;
AddressRange : INTEGER := 300;
AddressWidth : INTEGER := 9);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverydEe is
component contact_discoverydEe_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverydEe_ram_U : component contact_discoverydEe_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 | ca62b0c78136555b7659b3b580e105b5 | 0.550145 | 3.622664 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_accum/flt_accum_bit_encode.vhd | 3 | 37,537 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | ae0669e8e813d280d038ebde076b0b4d | 0.948184 | 1.839238 | false | false | false | false |
UVVM/UVVM_All | uvvm_vvc_framework/src/ti_generic_queue_pkg.vhd | 1 | 50,724 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
-- WARNING! This package will be deprecated and no longer receive updates or bug fixes!
-- The generic_queue_pkg in uvvm_util/src/generic_queue_pkg.vhd has replaced ti_generic_queue_pkg
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_generic_queue_pkg is
generic (type t_generic_element;
scope : string := C_SCOPE;
GC_QUEUE_COUNT_MAX : natural := 1000;
GC_QUEUE_COUNT_THRESHOLD : natural := 950);
-- When find_* doesn't find a match, they return C_NO_MATCH.
constant C_NO_MATCH : integer := -1;
-- A generic queue for verification
type t_generic_queue is protected
procedure add(
constant instance : in integer;
constant element : in t_generic_element);
procedure add(
constant element : in t_generic_element);
procedure put(
constant instance : in integer;
constant element : in t_generic_element);
procedure put(
constant element : in t_generic_element);
impure function get(
constant instance : in integer)
return t_generic_element;
impure function get(
constant dummy : in t_void)
return t_generic_element;
impure function is_empty(
constant instance : in integer)
return boolean;
impure function is_empty(
constant dummy : in t_void)
return boolean;
procedure set_scope(
constant instance : in integer;
constant scope : in string);
procedure set_scope(
constant scope : in string);
procedure set_name(
constant name : in string);
impure function get_scope(
constant instance : in integer)
return string;
impure function get_scope(
constant dummy : in t_void)
return string;
impure function get_count(
constant instance : in integer)
return natural;
impure function get_count(
constant dummy : in t_void)
return natural;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural);
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural);
impure function get_queue_count_threshold(
constant instance : in integer) return natural;
impure function get_queue_count_threshold(
constant dummy : in t_void) return natural;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void) return t_alert_level;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level);
impure function get_queue_count_max(
constant instance : in integer) return natural;
impure function get_queue_count_max(
constant dummy : in t_void) return natural;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural);
procedure set_queue_count_max(
constant queue_count_max : in natural);
procedure flush(
constant instance : in integer);
procedure flush(
constant dummy : in t_void);
procedure reset(
constant instance : in integer);
procedure reset(
constant dummy : in t_void);
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
);
procedure delete(
constant element : in t_generic_element
);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant instance : in integer
) return t_generic_element;
impure function peek(
constant dummy : in t_void
) return t_generic_element;
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant instance : in integer
) return t_generic_element;
impure function fetch(
constant dummy : in t_void
) return t_generic_element;
impure function find_position(
constant element : in t_generic_element) return integer;
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean;
impure function exists(
constant element : in t_generic_element
) return boolean;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive) return integer;
impure function get_entry_num(
constant position_val : in positive) return integer;
procedure print_queue(
constant instance : in integer);
procedure print_queue(
constant dummy : in t_void);
end protected;
end package ti_generic_queue_pkg;
package body ti_generic_queue_pkg is
type t_generic_queue is protected body
-- Types and control variables for the linked list implementation
type t_element;
type t_element_ptr is access t_element;
type t_element is record
entry_num : natural;
next_element : t_element_ptr;
element_data : t_generic_element;
end record;
type t_element_ptr_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr;
type t_string_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH);
variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry
variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry
variable vr_num_elements_in_queue : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0);
-- Scope variables
variable vr_scope : t_string_array := (others => (others => NUL));
variable vr_scope_is_defined : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
-- Name variables
variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL);
variable vr_name_is_defined : boolean := false;
variable vr_queue_count_max : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX);
variable vr_queue_count_threshold : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD);
variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING;
variable vr_entry_num : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert
-- Fill level alert
type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY);
constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY;
variable vr_queue_count_threshold_triggered : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
------------------------------------------------------------------------------------------------------
--
-- Helper methods (not visible from outside)
--
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
-- Helper method: Check if an Alert shall be triggered (to be called before adding another entry)
------------------------------------------------------------------------------------------------------
procedure perform_pre_add_checks (
constant instance : in integer
) is
begin
if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then
if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then
alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance));
vr_queue_count_threshold_triggered(instance) := true;
end if;
end if;
end procedure;
------------------------------------------------------------------------------------------------------
-- Helper method: Iterate through all entries, and match the one with element_data = element
-- This also works if the element is a record or array, whereas all entries/indexes must match
------------------------------------------------------------------------------------------------------
procedure match_element_data (
instance : in integer; -- Queue instance
element : in t_generic_element; -- Element to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr -- valid if found_match=true
) is
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
if vr_num_elements_in_queue(instance) > 0 then
-- Search from front to back element
v_element_ptr := vr_first_element(instance);
loop
if v_element_ptr.element_data = element then -- Element matched entry
found_match := true;
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else -- No match.
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop;
end if;
end procedure;
-- Find and return entry that matches the identifier
procedure match_identifier (
instance : in integer; -- Queue instance
identifier_option : in t_identifier_option; -- Determines what 'identifier' means
identifier : in positive; -- Identifier value to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr; -- valid if found_match=true
preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr
) is
-- Search from front to back element. Init pointers/counters to the first entry:
variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
preceding_element_ptr := null;
-- If queue is not empty and indentifier in valid range
if (vr_num_elements_in_queue(instance) > 0) and
((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or
(identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then
loop
-- For each element in queue:
-- Check if POSITION or ENTRY_NUM matches v_element_ptr
if (identifier_option = POSITION) and (v_position_ctr = identifier) then
found_match := true;
end if;
if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then
found_match := true;
end if;
if found_match then
-- This element matched. Done searching.
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else
-- No match.
if v_element_ptr.next_element = null then
-- report "last v_position_ctr = " & to_string(v_position_ctr);
exit; -- Last entry. All queue entries have been searched through.
end if;
preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop; -- for each element in queue
end if; -- Not empty
end procedure;
------------------------------------------------------------------------------------------------------
--
-- Public methods, visible from outside
--
------------------------------------------------------------------------------------------------------
-- add : Insert element in the back of queue, i.e. at the highest position
procedure add(
constant instance : in integer;
constant element : in t_generic_element
) is
constant proc_name : string := "add";
variable v_previous_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
-- Increment vr_entry_num
vr_entry_num(instance) := vr_entry_num(instance)+1;
-- Set read and write pointers when appending element to existing list
if vr_num_elements_in_queue(instance) > 0 then
v_previous_ptr := vr_last_element(instance);
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list
else -- List is empty
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list.
end if;
-- Increment number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1;
end procedure;
procedure add(
constant element : in t_generic_element
) is
begin
add(1, element);
end procedure;
procedure put(
constant instance : in integer;
constant element : in t_generic_element
) is
begin
add(instance, element);
end procedure;
procedure put(
constant element : in t_generic_element
) is
begin
put(1, element);
end procedure;
impure function get(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance);
end function;
impure function get(
constant dummy : in t_void
) return t_generic_element is
begin
return get(1);
end function;
procedure flush(
constant instance : in integer
) is
variable v_to_be_deallocated_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue " &to_string(instance), "???", ID_NEVER);
-- Deallocate all entries in the list
-- Setting the last element to null and iterating over the queue until finding the null element
vr_last_element(instance) := null;
while vr_first_element(instance) /= null loop
v_to_be_deallocated_ptr := vr_first_element(instance);
vr_first_element(instance) := vr_first_element(instance).next_element;
DEALLOCATE(v_to_be_deallocated_ptr);
end loop;
-- Reset the queue counter
vr_num_elements_in_queue(instance) := 0;
vr_queue_count_threshold_triggered(instance) := false;
end procedure;
procedure flush(
constant dummy : in t_void
) is
begin
flush(1);
end procedure;
procedure reset(
constant instance : in integer) is
begin
flush(instance);
vr_entry_num(instance) := 0; -- Incremented before first insert
end procedure;
procedure reset(
constant dummy : in t_void) is
begin
reset(1);
end procedure;
impure function is_empty(
constant instance : in integer
) return boolean is
begin
if vr_num_elements_in_queue(instance) = 0 then
return true;
else
return false;
end if;
end function;
impure function is_empty(
constant dummy : in t_void
) return boolean is
begin
return is_empty(1);
end function;
procedure set_scope(
constant instance : in integer;
constant scope : in string) is
begin
if instance = ALL_INSTANCES then
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH));
else
for idx in vr_scope'range loop
vr_scope(idx) := (others => NUL);
vr_scope(idx)(1 to scope'length) := scope;
end loop;
end if;
vr_scope_is_defined := (others => true);
else
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH);
else
vr_scope(instance) := (others => NUL);
vr_scope(instance)(1 to scope'length) := scope;
end if;
vr_scope_is_defined(instance) := true;
end if;
end procedure;
procedure set_scope(
constant scope : in string) is
begin
set_scope(1, scope);
end procedure;
procedure set_name(
constant name : in string) is
begin
vr_name(1 to name'length) := name;
vr_name_is_defined := true;
end procedure;
impure function get_scope(
constant instance : in integer
) return string is
begin
return to_string(vr_scope(instance));
end function;
impure function get_scope(
constant dummy : in t_void
) return string is
begin
return get_scope(1);
end function;
impure function get_count(
constant instance : in integer
) return natural is
begin
return vr_num_elements_in_queue(instance);
end function;
impure function get_count(
constant dummy : in t_void
) return natural is
begin
return get_count(1);
end function;
impure function get_queue_count_max(
constant instance : in integer
) return natural is
begin
return vr_queue_count_max(instance);
end function;
impure function get_queue_count_max(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_max(1);
end function;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural
) is
begin
vr_queue_count_max(instance) := queue_count_max;
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER);
end procedure;
procedure set_queue_count_max(
constant queue_count_max : in natural
) is
begin
set_queue_count_max(1, queue_count_max);
end procedure;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural
) is
begin
vr_queue_count_threshold(instance) := queue_count_alert_level;
end procedure;
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural
) is
begin
set_queue_count_threshold(1, queue_count_alert_level);
end procedure;
impure function get_queue_count_threshold(
constant instance : in integer
) return natural is
begin
return vr_queue_count_threshold(instance);
end function;
impure function get_queue_count_threshold(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_threshold(1);
end function;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void
) return t_alert_level is
begin
return vr_queue_count_threshold_severity;
end function;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level) is
begin
vr_queue_count_threshold_severity := alert_level;
end procedure;
----------------------------------------------------
-- Insert:
----------------------------------------------------
-- Inserts element into the queue after the matching entry with specified identifier:
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element)
is
constant proc_name : string := "insert";
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_found_match : boolean;
variable v_matched_position : integer;
begin
-- pre insert checks
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER);
if identifier_option = POSITION then
check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER);
end if;
-- Search from front to back element.
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Make new element
vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num
-- POSITION: insert at matched position
if identifier_option = POSITION then
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr,
element_data => element);
-- if match is first element
if v_preceding_element_ptr = null then
vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list
else
v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
--ENTRY_NUM: insert at position after match
else
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr.next_element,
element_data => element);
v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements
elsif identifier_option = ENTRY_NUM then
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier) &
", element...", scope);
end if;
end if;
end procedure;
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element) is
begin
insert(1, identifier_option, identifier, element);
end procedure;
----------------------------------------------------
-- delete:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
constant proc_name : string := "delete";
variable v_matched_element_ptr : t_element_ptr; -- The element being deleted
variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
variable v_deletes_remaining : integer;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
-- delete based on POSITION :
-- Note that when deleting the first position, all above positions are decremented by one.
-- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- Find min position
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier_min,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first
while v_deletes_remaining > 0 loop
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_element_to_delete_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
v_deletes_remaining := v_deletes_remaining - 1;
-- Prepare next iteration:
-- Next element to delete:
if v_deletes_remaining > 0 then
if (v_preceding_element_ptr = null) then
-- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry.
v_element_to_delete_ptr := vr_first_element(instance);
else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element
v_element_to_delete_ptr := v_preceding_element_ptr.next_element;
end if;
end if;
end loop;
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier_min), scope);
end if;
end if; -- v_found_match
-- delete based on ENTRY_NUM :
-- Unlike position, an entry's Entry_num is stable when deleting other entries
-- Entry_num is not necessarily increasing as we follow next_element pointers.
-- This means that we must do a complete search for each entry we want to delete
elsif (identifier_option = ENTRY_NUM) then
check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- For each entry to delete, find it based on entry_num , then delete it
for identifier in identifier_min to identifier_max loop
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_element_to_delete_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier), scope);
end if;
end if; -- v_found_match
end loop;
end if; -- identifier_option
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
begin
delete(1, identifier_option, identifier_min, identifier_max);
end procedure;
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
) is
variable v_entry_num : integer:= find_entry_num(element);
begin
delete(instance, ENTRY_NUM, v_entry_num, v_entry_num);
end procedure;
procedure delete(
constant element : in t_generic_element
) is
begin
delete(1, element);
end procedure;
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
case range_option is
when SINGLE =>
delete(instance, identifier_option, identifier, identifier);
when AND_LOWER =>
delete(instance, identifier_option, 1, identifier);
when AND_HIGHER =>
if identifier_option = POSITION then
delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance));
elsif identifier_option = ENTRY_NUM then
delete(instance, identifier_option, identifier, vr_entry_num(instance));
end if;
end case;
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
delete(1, identifier_option, identifier, range_option);
end procedure;
----------------------------------------------------
-- peek:
----------------------------------------------------
-- Read the entry matching the identifier, but don't remove it.
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "peek";
variable v_matched_element_data : t_generic_element; -- Return value
variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_matched_element_data := v_matched_element_ptr.element_data;
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return peek(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function peek(
constant instance : in integer
) return t_generic_element is
begin
return peek(instance, POSITION, 1);
end function;
impure function peek(
constant dummy : in t_void
) return t_generic_element is
begin
return peek(1);
end function;
----------------------------------------------------
-- Fetch:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "fetch";
variable v_matched_element_ptr : t_element_ptr; -- The element being fetched
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Keep info about element before removing it from queue
v_matched_element_data := v_matched_element_ptr.element_data;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element;
-- If the element is the last entry, update vr_last_element
if v_matched_element_ptr.next_element = null then
vr_last_element(instance) := v_preceding_element_ptr;
end if;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_matched_element_ptr);
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return fetch(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function fetch(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance, POSITION, 1);
end function;
impure function fetch(
constant dummy : in t_void
) return t_generic_element is
begin
return fetch(1);
end function;
-- Returns position of entry if found, else C_NO_MATCH.
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element --
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
-- Don't include this check, because we may want to use exists() on an empty queue.
-- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_matched_position;
else
return C_NO_MATCH;
end if;
end function;
impure function find_position(
constant element : in t_generic_element
) return integer is
begin
return find_position(1, element);
end function;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean is
begin
return (find_position(instance, element) /= C_NO_MATCH);
end function;
impure function exists(
constant element : in t_generic_element
) return boolean is
begin
return exists(1, element);
end function;
-- Returns entry number or position to entry if found, else C_NO_MATCH.
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_element_ptr.entry_num;
else
return C_NO_MATCH;
end if;
end function;
impure function find_entry_num(
constant element : in t_generic_element
) return integer is
begin
return find_entry_num(1, element);
end function;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive
) return integer is
variable v_found_match : boolean;
variable v_matched_position : integer;
variable v_matched_element_ptr : t_element_ptr;
variable v_preceding_element_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => POSITION ,
identifier => position_val,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
return v_matched_element_ptr.entry_num;
else
return -1;
end if;
end function get_entry_num;
impure function get_entry_num(
constant position_val : in positive
) return integer is
begin
return get_entry_num(1, position_val);
end function get_entry_num;
-- for debugging:
-- print each entry's position and entry_num
procedure print_queue(
constant instance : in integer
)
is
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
-- Search from front to back element. Initalise pointers/counters to the first entry:
v_element_ptr := vr_first_element(instance);
if v_element_ptr = NULL then
return; -- Return if queue is empty
end if;
loop
log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope);
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end loop;
end procedure;
procedure print_queue(
constant dummy : in t_void) is
begin
print_queue(1);
end procedure;
end protected body;
end package body ti_generic_queue_pkg;
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`protect end_protected
| gpl-2.0 | 127f33596fdf2e704bdedd8d55babd42 | 0.946039 | 1.840687 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_fma/flt_fma_addsub_dsp1.vhd | 2 | 32,999 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22688)
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rog=
`protect end_protected
| gpl-2.0 | 5db1adcbb44b6cc2d005dbc80b33fa0a | 0.945332 | 1.839307 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/vm2/vm2Comps.vhd | 2 | 21,996 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14544)
`protect data_block
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`protect end_protected
| gpl-2.0 | 2506419e0e9439c65f7fff572c7892a3 | 0.939989 | 1.847317 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/fir_lp_54kHz/fir_compiler_v7_1/hdl/cntrl_delay.vhd | 8 | 9,460 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5264)
`protect data_block
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`protect end_protected
| gpl-2.0 | 67e9380ee8755736f05ca86e02d9e041 | 0.92241 | 1.903804 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/out_addr_gen_b.vhd | 3 | 13,111 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7968)
`protect data_block
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`protect end_protected
| gpl-2.0 | 8cc2ea41713d0ae19fde94b134c86c64 | 0.933262 | 1.880522 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/cmpy_v6_0/hdl/delay_line.vhd | 3 | 18,150 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11696)
`protect data_block
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| gpl-2.0 | 8f5ca52e280d3d420d00f3110ddd5a3b | 0.941102 | 1.856398 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ALU/ALU/arith_unit.vhd | 1 | 1,885 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:02 03/28/2016
-- Design Name:
-- Module Name: arith_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity arith_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
AR_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end arith_unit;
architecture Combinational of arith_unit is
signal a,b : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
signal RESULT : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
signal SREG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
a <= '0' & RA;
b <= '0' & RB;
with OP select
RESULT <=
a + b when "000", -- ADD
a - b when "001", -- SUB
a + b when "101", -- ADDI
'0' & X"0000" when OTHERS;
SREG(3) <= RESULT(15); -- Negative with signed logic
SREG(2) <= '1' when RESULT(15 downto 0) = x"00000000" else '1'; -- Zero
SREG(1) <= RESULT(16) xor RESULT(15); -- Overflow with signed logic
SREG(0) <= RESULT(16); -- Carry
SREG_OUT <= SREG;
AR_OUT <= RESULT(15 downto 0);
end Combinational;
| gpl-3.0 | 6d5e5581803788f1c46cf5cec0783d90 | 0.586207 | 3.244406 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/so_run_addr_gen_rotator.vhd | 3 | 225,106 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 164896)
`protect data_block
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| gpl-2.0 | 234ab0da6524106ab6d86ec24c5f85b9 | 0.954084 | 1.808996 | false | false | false | false |
UVVM/UVVM_All | bitvis_irqc/src/irqc_pif.vhd | 1 | 4,367 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end irqc_pif;
architecture rtl of irqc_pif is
signal p2c_i : t_p2c; -- internal version of output
signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
dout_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_IRR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
when C_ADDR_IER =>
dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
when C_ADDR_IPR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
when C_ADDR_IRQ2CPU_ALLOWED =>
dout_i(0) <= c2p.aro_irq2cpu_allowed;
when others =>
null;
end case;
end if;
end process p_read_reg;
dout <= dout_i;
-- Writing to registers that are not functionally manipulated
p_write_reg : process(clk, arst)
begin
if arst = '1' then
p2c_i.rw_ier <= (others => '0');
elsif rising_edge(clk) then
if cs = '1' and wr = '1' then
case to_integer(addr) is
when C_ADDR_IER =>
p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
-- Auxiliary write (below)
when others =>
null;
end case;
end if;
end if;
end process p_write_reg;
-- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
p_aux : process(wr, addr, din)
begin
-- Note that arst is not considered here, but must be considered in any clocked process in the core
-- Default - always to return to these values
p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_irq2cpu_ena <= '0';
p2c_i.awt_irq2cpu_disable <= '0';
if (cs = '1' and wr = '1') then
case to_integer(addr) is
when C_ADDR_ITR =>
p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_ICR =>
p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_IRQ2CPU_ENA =>
p2c_i.awt_irq2cpu_ena <= din(0);
when C_ADDR_IRQ2CPU_DISABLE =>
p2c_i.awt_irq2cpu_disable <= din(0);
when others =>
null;
end case;
end if;
end process p_aux;
end rtl;
| mit | e8dd76bfc141b0198156e015f8129015 | 0.517747 | 3.735672 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_pkg.vhd | 7 | 24,914 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | a9db03b4980b2df3271c9ae4b446794a | 0.944569 | 1.842615 | false | false | false | false |
Unrelentless/FPGAProject2011 | LCD_controller/LCD_controller.vhd | 1 | 17,829 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- This code displays time in the DE2's LCD Display
-- Key2 resets time
ENTITY LCD_controller IS
PORT(clock_50Mhz, reset : IN STD_LOGIC;
LCD_EN, LCD_RS, LCD_ON : OUT STD_LOGIC;
LCD_RW : BUFFER STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
address_in : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
data_bus : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END LCD_controller;
ARCHITECTURE operation OF LCD_controller IS
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, MODE_SET2, WRITE_ADD1,
WRITE_ADD2,WRITE_ADD3,WRITE_ADD4,WRITE_ADD5,WRITE_ADD6,WRITE_ADD7,
WRITE_ADD8, WRITE_ADD9, WRITE_ADD10,WRITE_ADD11,WRITE_ADD12,
WRITE_ADD13, WRITE_ADD14, WRITE_ADD15, WRITE_ADD16, WRITE_DATA1,
WRITE_DATA2,WRITE_DATA3,WRITE_DATA4,WRITE_DATA5,WRITE_DATA6,WRITE_DATA7,
WRITE_DATA8, WRITE_DATA9, WRITE_DATA10,WRITE_DATA11,WRITE_DATA12,
WRITE_DATA13, WRITE_DATA14, WRITE_DATA15, WRITE_DATA16, RETURN_HOME,
TOGGLE_E, RESET1, RESET2, RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL data_1, data_2, data_3, data_4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL add_1, add_2, add_3, add_4, add_5 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_bus_value : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL clock_count_400Hz : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL clock_400Hz : STD_LOGIC;
BEGIN
LCD_ON <= '1';
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
data_bus <= data_bus_value WHEN LCD_RW = '0' ELSE "ZZZZZZZZ";
add_1 <= X"1" WHEN address_in(3 downto 0) = X"1" OR address_in(3 downto 0) = X"A" ELSE
X"2" WHEN address_in(3 downto 0) = X"2" OR address_in(3 downto 0) = X"B" ELSE
X"3" WHEN address_in(3 downto 0) = X"3" OR address_in(3 downto 0) = X"C" ELSE
X"4" WHEN address_in(3 downto 0) = X"4" OR address_in(3 downto 0) = X"D" ELSE
X"5" WHEN address_in(3 downto 0) = X"5" OR address_in(3 downto 0) = X"E" ELSE
X"6" WHEN address_in(3 downto 0) = X"6" OR address_in(3 downto 0) = X"F" ELSE
X"7" WHEN address_in(3 downto 0) = X"7" ELSE
X"8" WHEN address_in(3 downto 0) = X"8" ELSE
X"9" WHEN address_in(3 downto 0) = X"9" ELSE
X"0";
add_2 <= X"1" WHEN address_in(7 downto 4) = X"1" OR address_in(7 downto 4) = X"A" ELSE
X"2" WHEN address_in(7 downto 4) = X"2" OR address_in(7 downto 4) = X"B" ELSE
X"3" WHEN address_in(7 downto 4) = X"3" OR address_in(7 downto 4) = X"C" ELSE
X"4" WHEN address_in(7 downto 4) = X"4" OR address_in(7 downto 4) = X"D" ELSE
X"5" WHEN address_in(7 downto 4) = X"5" OR address_in(7 downto 4) = X"E" ELSE
X"6" WHEN address_in(7 downto 4) = X"6" OR address_in(7 downto 4) = X"F" ELSE
X"7" WHEN address_in(7 downto 4) = X"7" ELSE
X"8" WHEN address_in(7 downto 4) = X"8" ELSE
X"9" WHEN address_in(7 downto 4) = X"9" ELSE
X"0";
add_3 <= X"1" WHEN address_in(11 downto 8) = X"1" OR address_in(11 downto 8) = X"A" ELSE
X"2" WHEN address_in(11 downto 8) = X"2" OR address_in(11 downto 8) = X"B" ELSE
X"3" WHEN address_in(11 downto 8) = X"3" OR address_in(11 downto 8) = X"C" ELSE
X"4" WHEN address_in(11 downto 8) = X"4" OR address_in(11 downto 8) = X"D" ELSE
X"5" WHEN address_in(11 downto 8) = X"5" OR address_in(11 downto 8) = X"E" ELSE
X"6" WHEN address_in(11 downto 8) = X"6" OR address_in(11 downto 8) = X"F" ELSE
X"7" WHEN address_in(11 downto 8) = X"7" ELSE
X"8" WHEN address_in(11 downto 8) = X"8" ELSE
X"9" WHEN address_in(11 downto 8) = X"9" ELSE
X"0";
add_4 <= X"1" WHEN address_in(15 downto 12) = X"1" OR address_in(15 downto 12) = X"A" ELSE
X"2" WHEN address_in(15 downto 12) = X"2" OR address_in(15 downto 12) = X"B" ELSE
X"3" WHEN address_in(15 downto 12) = X"3" OR address_in(15 downto 12) = X"C" ELSE
X"4" WHEN address_in(15 downto 12) = X"4" OR address_in(15 downto 12) = X"D" ELSE
X"5" WHEN address_in(15 downto 12) = X"5" OR address_in(15 downto 12) = X"E" ELSE
X"6" WHEN address_in(15 downto 12) = X"6" OR address_in(15 downto 12) = X"F" ELSE
X"7" WHEN address_in(15 downto 12) = X"7" ELSE
X"8" WHEN address_in(15 downto 12) = X"8" ELSE
X"9" WHEN address_in(15 downto 12) = X"9" ELSE
X"0";
add_5 <= "00" & address_in(17 downto 16);
data_1 <= X"1" WHEN data_in(3 downto 0) = X"1" OR data_in(3 downto 0) = X"A" ELSE
X"2" WHEN data_in(3 downto 0) = X"2" OR data_in(3 downto 0) = X"B" ELSE
X"3" WHEN data_in(3 downto 0) = X"3" OR data_in(3 downto 0) = X"C" ELSE
X"4" WHEN data_in(3 downto 0) = X"4" OR data_in(3 downto 0) = X"D" ELSE
X"5" WHEN data_in(3 downto 0) = X"5" OR data_in(3 downto 0) = X"E" ELSE
X"6" WHEN data_in(3 downto 0) = X"6" OR data_in(3 downto 0) = X"F" ELSE
X"7" WHEN data_in(3 downto 0) = X"7" ELSE
X"8" WHEN data_in(3 downto 0) = X"8" ELSE
X"9" WHEN data_in(3 downto 0) = X"9" ELSE
X"0";
data_2 <= X"1" WHEN data_in(7 downto 4) = X"1" OR data_in(7 downto 4) = X"A" ELSE
X"2" WHEN data_in(7 downto 4) = X"2" OR data_in(7 downto 4) = X"B" ELSE
X"3" WHEN data_in(7 downto 4) = X"3" OR data_in(7 downto 4) = X"C" ELSE
X"4" WHEN data_in(7 downto 4) = X"4" OR data_in(7 downto 4) = X"D" ELSE
X"5" WHEN data_in(7 downto 4) = X"5" OR data_in(7 downto 4) = X"E" ELSE
X"6" WHEN data_in(7 downto 4) = X"6" OR data_in(7 downto 4) = X"F" ELSE
X"7" WHEN data_in(7 downto 4) = X"7" ELSE
X"8" WHEN data_in(7 downto 4) = X"8" ELSE
X"9" WHEN data_in(7 downto 4) = X"9" ELSE
X"0";
data_3 <= X"1" WHEN data_in(11 downto 8) = X"1" OR data_in(11 downto 8) = X"A" ELSE
X"2" WHEN data_in(11 downto 8) = X"2" OR data_in(11 downto 8) = X"B" ELSE
X"3" WHEN data_in(11 downto 8) = X"3" OR data_in(11 downto 8) = X"C" ELSE
X"4" WHEN data_in(11 downto 8) = X"4" OR data_in(11 downto 8) = X"D" ELSE
X"5" WHEN data_in(11 downto 8) = X"5" OR data_in(11 downto 8) = X"E" ELSE
X"6" WHEN data_in(11 downto 8) = X"6" OR data_in(11 downto 8) = X"F" ELSE
X"7" WHEN data_in(11 downto 8) = X"7" ELSE
X"8" WHEN data_in(11 downto 8) = X"8" ELSE
X"9" WHEN data_in(11 downto 8) = X"9" ELSE
X"0";
data_4 <= X"1" WHEN data_in(15 downto 12) = X"1" OR data_in(15 downto 12) = X"A" ELSE
X"2" WHEN data_in(15 downto 12) = X"2" OR data_in(15 downto 12) = X"B" ELSE
X"3" WHEN data_in(15 downto 12) = X"3" OR data_in(15 downto 12) = X"C" ELSE
X"4" WHEN data_in(15 downto 12) = X"4" OR data_in(15 downto 12) = X"D" ELSE
X"5" WHEN data_in(15 downto 12) = X"5" OR data_in(15 downto 12) = X"E" ELSE
X"6" WHEN data_in(15 downto 12) = X"6" OR data_in(15 downto 12) = X"F" ELSE
X"7" WHEN data_in(15 downto 12) = X"7" ELSE
X"8" WHEN data_in(15 downto 12) = X"8" ELSE
X"9" WHEN data_in(15 downto 12) = X"9" ELSE
X"0";
PROCESS
BEGIN
WAIT UNTIL clock_50Mhz'EVENT AND clock_50Mhz = '1';
IF reset = '0' THEN
clock_count_400Hz <= X"00000";
clock_400Hz <= '0';
ELSE
IF clock_count_400Hz < X"0F424" THEN
clock_count_400Hz <= clock_count_400Hz + 1;
ELSE
clock_count_400Hz <= X"00000";
clock_400Hz <= NOT clock_400Hz;
END IF;
END IF;
END PROCESS;
PROCESS (clock_400Hz, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
data_bus_value <= X"38";
next_command <= RESET2;
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
ELSIF clock_400Hz'EVENT AND clock_400Hz = '1' THEN
-- SEND DATA AND ADDRESS TO LCD
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"38";
state <= TOGGLE_E;
next_command <= RESET2;
WHEN RESET2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"38";
state <= TOGGLE_E;
next_command <= RESET3;
WHEN RESET3 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"38";
state <= TOGGLE_E;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"38";
state <= TOGGLE_E;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"08";
state <= TOGGLE_E;
next_command <= DISPLAY_CLEAR;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"01";
state <= TOGGLE_E;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"0C";
state <= TOGGLE_E;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"06";
state <= TOGGLE_E;
next_command <= WRITE_ADD1;
-- Write ASCII hex character in first LCD character location
WHEN WRITE_ADD1 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"41";
state <= TOGGLE_E;
next_command <= WRITE_ADD2;
-- Write ASCII hex character in second LCD character location
WHEN WRITE_ADD2 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"64";
state <= TOGGLE_E;
next_command <= WRITE_ADD3;
-- Write ASCII hex character in third LCD character location
WHEN WRITE_ADD3 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"64";
state <= TOGGLE_E;
next_command <= WRITE_ADD4;
-- Write ASCII hex character in fourth LCD character location
WHEN WRITE_ADD4 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"72";
state <= TOGGLE_E;
next_command <= WRITE_ADD5;
-- Write ASCII hex character in fifth LCD character location
WHEN WRITE_ADD5 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"65";
state <= TOGGLE_E;
next_command <= WRITE_ADD6;
-- Write ASCII hex character in sixth LCD character location
WHEN WRITE_ADD6 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"73" ;
state <= TOGGLE_E;
next_command <= WRITE_ADD7;
-- Write ASCII hex character in seventh LCD character location
WHEN WRITE_ADD7 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"73";
state <= TOGGLE_E;
next_command <= WRITE_ADD8;
-- Write ASCII hex character in eighth LCD character location
WHEN WRITE_ADD8 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_ADD9;
WHEN WRITE_ADD9 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"3D";
state <= TOGGLE_E;
next_command <= WRITE_ADD10;
WHEN WRITE_ADD10 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_ADD11;
WHEN WRITE_ADD11 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(address_in(17 downto 16) < X"A") THEN
data_bus_value <= X"3" & add_5;
ELSE
data_bus_value <= X"4" & add_5;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_ADD12;
WHEN WRITE_ADD12 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(address_in(15 downto 12) < X"A") THEN
data_bus_value <= X"3" & add_4;
ELSE
data_bus_value <= X"4" & add_4;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_ADD13;
WHEN WRITE_ADD13 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(address_in(11 downto 8) < X"A") THEN
data_bus_value <= X"3" & add_3;
ELSE
data_bus_value <= X"4" & add_3;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_ADD14;
WHEN WRITE_ADD14 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(address_in(7 downto 4) < X"A") THEN
data_bus_value <= X"3" & add_2;
ELSE
data_bus_value <= X"4" & add_2;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_ADD15;
WHEN WRITE_ADD15 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(address_in(3 downto 0) < X"A") THEN
data_bus_value <= X"3" & add_1;
ELSE
data_bus_value <= X"4" & add_1;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_ADD16;
WHEN WRITE_ADD16 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= MODE_SET2;
-- Set write mode to auto increment address and move cursor to the right on second line
WHEN MODE_SET2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"C0";
state <= TOGGLE_E;
next_command <= WRITE_DATA1;
-- Write ASCII hex character in first LCD character location
WHEN WRITE_DATA1 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"44";
state <= TOGGLE_E;
next_command <= WRITE_DATA2;
-- Write ASCII hex character in second LCD character location
WHEN WRITE_DATA2 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"61";
state <= TOGGLE_E;
next_command <= WRITE_DATA3;
-- Write ASCII hex character in third LCD character location
WHEN WRITE_DATA3 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"74";
state <= TOGGLE_E;
next_command <= WRITE_DATA4;
-- Write ASCII hex character in fourth LCD character location
WHEN WRITE_DATA4 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"61";
state <= TOGGLE_E;
next_command <= WRITE_DATA5;
-- Write ASCII hex character in fifth LCD character location
WHEN WRITE_DATA5 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_DATA6;
-- Write ASCII hex character in sixth LCD character location
WHEN WRITE_DATA6 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20" ;
state <= TOGGLE_E;
next_command <= WRITE_DATA7;
-- Write ASCII hex character in seventh LCD character location
WHEN WRITE_DATA7 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_DATA8;
-- Write ASCII hex character in eighth LCD character location
WHEN WRITE_DATA8 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_DATA9;
WHEN WRITE_DATA9 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"3D";
state <= TOGGLE_E;
next_command <= WRITE_DATA10;
WHEN WRITE_DATA10 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_DATA11;
WHEN WRITE_DATA11 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= WRITE_DATA12;
WHEN WRITE_DATA12 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(data_in(15 downto 12) < X"A") THEN
data_bus_value <= X"3" & data_4;
ELSE
data_bus_value <= X"4" & data_4;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_DATA13;
WHEN WRITE_DATA13 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(data_in(11 downto 8) < X"A") THEN
data_bus_value <= X"3" & data_3;
ELSE
data_bus_value <= X"4" & data_3;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_DATA14;
WHEN WRITE_DATA14 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(data_in(7 downto 4) < X"A") THEN
data_bus_value <= X"3" & data_2;
ELSE
data_bus_value <= X"4" & data_2;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_DATA15;
WHEN WRITE_DATA15 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
IF(data_in(3 downto 0) < X"A") THEN
data_bus_value <= X"3" & data_1;
ELSE
data_bus_value <= X"4" & data_1;
END IF;
state <= TOGGLE_E;
next_command <= WRITE_DATA16;
WHEN WRITE_DATA16 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus_value <= X"20";
state <= TOGGLE_E;
next_command <= RETURN_HOME;
-- Return write address to first character postion
WHEN RETURN_HOME =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus_value <= X"80";
state <= TOGGLE_E;
next_command <= WRITE_ADD1;
-- The next two states occur at the end of each command to the LCD
-- Toggle E line - falling edge loads inst/data to LCD controller
WHEN TOGGLE_E =>
LCD_EN <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END PROCESS;
END operation;
| gpl-2.0 | 6b1db176bcae84f9c05b689729112018 | 0.553761 | 2.650758 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 68698b0fcdcc363e736047227ce950f0 | 0.942585 | 1.847035 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/axi_utils_v2_0/hdl/glb_srl_fifo.vhd | 15 | 35,288 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24384)
`protect data_block
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`protect end_protected
| gpl-2.0 | 1f118646c56911bb52708ac8d97c0e33 | 0.945477 | 1.827068 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_avalon_mm/src/vvc_cmd_pkg.vhd | 1 | 7,204 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
-- VVC dedicated fields
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
max_polls : integer;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
operation => NO_OPERATION, -- Default unless overwritten by a common operation
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '1'), -- All bytes enabled by default
max_polls => 1,
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit | 63c1cba29ebcd882f5a443b673d81d16 | 0.436008 | 5.293167 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_mult/flt_mult.vhd | 3 | 21,866 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | a952767d4bdb1d38b4405eabf0cf8fe9 | 0.940227 | 1.846011 | false | false | false | false |
amerryfellow/dlx | cu/bht.vhd | 1 | 1,548 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.myTypes.all;
use work.cu.all;
--use work.all;
entity BHT is
generic (
LSBITS : integer := 8; -- How many bits is the BHT addressed by?
LINES : integer := 2 ** LSBITS
);
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset:Active-Low
PC : out std_logic;
NPC : out std_logic;
LAST : in std_logic;
ADDR : in std_logic_vector(31 downto 0);
);
end BHT;
architecture CORRELATING_PREDICTOR of BHT is
type LOCAL_HISTORY is array (1 downto 0) of std_logic := '0';
type ARRAY_LOCAL is array (0 to LINES-1) of LOCAL_HISTORY;
variable HISTORY : ARRAY_LOCAL;
variable INDEX0 : integer;
variable INDEX1 : integer;
variable GLOBAL_HISTORY : std_logic_vector(1 downto 0) := (others => '0');
variable PRED : std_logic;
variable LAST_PREDICTION : std_logic;
variable RIGHT_PREDICTION : std_logic;
signal IPC : integer;
signal INPC : integer;
begin
-- 0 : Not Taken ; 1 : Taken
PREDICTOR: process(Clk, Rst)
begin
INDEX0 := to_integer(signed(ADDR));
INDEX1 := to_integer(signed(GLOBAL_HISTORY));
if Rst = '0' then
PRED <= '0';
GLOBAL_HISTORY <= (others => '0');
elsif Clk'event and Clk = '1' then
PRED <= HISTORY( INDEX0 )( INDEX1 )(1);
GLOBAL_HISTORY := GLOBAL_HISTORY(0) & LAST;
RIGHT_PREDICTION := not ( LAST xor LAST_PREDICTION );
-- Wrong prediction, must stall and update PC
if RIGHT_PREDICTION = '0' then
end if;
end process;
end
| gpl-3.0 | a8336a51673f208aa72f30a75f198c65 | 0.652455 | 2.819672 | false | false | false | false |
Subsets and Splits