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{
list-style-image: url("chrome://charting/skin/toolbar-button.png");
-moz-image-region: rect(0px 24px 24px 0px);
}
#charting-note-toolbar-button
{
list-style-image: url("chrome://charting/skin/note-button.png");
-moz-image-region: rect(0px 24px 24px 0px);
}
.charting-toolbar-button:hover
{
-moz-image-region: rect(24px 24px 48px 0px);
}
[iconsize="small"] .charting-toolbar-button
{
-moz-image-region: rect( 0px 40px 16px 24px);
}
[iconsize="small"] .charting-toolbar-button:hover
{
-moz-image-region: rect(24px 40px 40px 24px);
}
.goal-button
{
}
| {'content_hash': 'a3bf2f956b6a65918e341045911da41a', 'timestamp': '', 'source': 'github', 'line_count': 29, 'max_line_length': 69, 'avg_line_length': 19.655172413793103, 'alnum_prop': 0.6964912280701754, 'repo_name': 'johnturner/charting', 'id': '78204ddaf52a374531ff7a7f12198fb7bf5fa331', 'size': '603', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'extension/firefox/chrome/skin/overlay.css', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'C#', 'bytes': '18106'}, {'name': 'CSS', 'bytes': '25959'}, {'name': 'JavaScript', 'bytes': '11681'}, {'name': 'Ruby', 'bytes': '107756'}, {'name': 'Shell', 'bytes': '130'}]} |
package org.apache.hadoop.hdfs.protocol;
import org.apache.hadoop.classification.InterfaceAudience;
import org.apache.hadoop.classification.InterfaceStability;
import org.apache.hadoop.hdfs.security.token.block.BlockTokenIdentifier;
import org.apache.hadoop.security.token.Token;
/**
* Associates a block with the Datanodes that contain its replicas
* and other block metadata (E.g. the file offset associated with this
* block, whether it is corrupt, security token, etc).
*/
@InterfaceAudience.Private
@InterfaceStability.Evolving
public class LocatedBlock {
private ExtendedBlock b;
private long offset; // offset of the first byte of the block in the file
private DatanodeInfo[] locs;
// corrupt flag is true if all of the replicas of a block are corrupt.
// else false. If block has few corrupt replicas, they are filtered and
// their locations are not part of this object
private boolean corrupt;
private Token<BlockTokenIdentifier> blockToken = new Token<BlockTokenIdentifier>();
public LocatedBlock(ExtendedBlock b, DatanodeInfo[] locs) {
this(b, locs, -1, false); // startOffset is unknown
}
public LocatedBlock(ExtendedBlock b, DatanodeInfo[] locs, long startOffset) {
this(b, locs, startOffset, false);
}
public LocatedBlock(ExtendedBlock b, DatanodeInfo[] locs, long startOffset,
boolean corrupt) {
this.b = b;
this.offset = startOffset;
this.corrupt = corrupt;
if (locs==null) {
this.locs = new DatanodeInfo[0];
} else {
this.locs = locs;
}
}
public Token<BlockTokenIdentifier> getBlockToken() {
return blockToken;
}
public void setBlockToken(Token<BlockTokenIdentifier> token) {
this.blockToken = token;
}
public ExtendedBlock getBlock() {
return b;
}
public DatanodeInfo[] getLocations() {
return locs;
}
public long getStartOffset() {
return offset;
}
public long getBlockSize() {
return b.getNumBytes();
}
void setStartOffset(long value) {
this.offset = value;
}
void setCorrupt(boolean corrupt) {
this.corrupt = corrupt;
}
public boolean isCorrupt() {
return this.corrupt;
}
@Override
public String toString() {
return getClass().getSimpleName() + "{" + b
+ "; getBlockSize()=" + getBlockSize()
+ "; corrupt=" + corrupt
+ "; offset=" + offset
+ "; locs=" + java.util.Arrays.asList(locs)
+ "}";
}
}
| {'content_hash': '9dc1ddb6027b133efda8ffa8ab3e970d', 'timestamp': '', 'source': 'github', 'line_count': 92, 'max_line_length': 85, 'avg_line_length': 26.77173913043478, 'alnum_prop': 0.682907023954527, 'repo_name': 'shirdrn/hadoop-2.2.0', 'id': 'd9da5b845b79b482594a4ac7ad1165f72007ddac', 'size': '3269', 'binary': False, 'copies': '8', 'ref': 'refs/heads/master', 'path': 'hadoop-hdfs-project/hadoop-hdfs/src/main/java/org/apache/hadoop/hdfs/protocol/LocatedBlock.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'C', 'bytes': '986657'}, {'name': 'C++', 'bytes': '86543'}, {'name': 'CSS', 'bytes': '41761'}, {'name': 'Erlang', 'bytes': '232'}, {'name': 'Java', 'bytes': '34526149'}, {'name': 'JavaScript', 'bytes': '4688'}, {'name': 'Perl', 'bytes': '18992'}, {'name': 'Python', 'bytes': '11309'}, {'name': 'Shell', 'bytes': '199330'}, {'name': 'TeX', 'bytes': '19322'}, {'name': 'XSLT', 'bytes': '34239'}]} |
function showLoginDialog() {
dijit.byId('loginDialog').show();
}
function hideLoginDialog() {
dijit.byId('loginDialog').hide();
}
function showLoginWaitDialog() {
dijit.byId('loginWaitDialog').show();
}
function hideLoginWaitDialog() {
dijit.byId('loginWaitDialog').hide();
}
function updateLoggedInUserWelcome() {
var loggedinuser = dojo.cookie("loggedinuser");
if (loggedinuser == null) {
dojo.byId("loggedinwelcome").innerHTML = '';
}
else {
dojo.byId("loggedinwelcome").innerHTML = 'Welcome Back ' + loggedinuser;
}
}
function login() {
hideLoginDialog();
showLoginWaitDialog();
var userString = document.getElementById('userId').value;
dojo.xhrPost({
content : {
login: userString,
password: document.getElementById('password').value
},
url: 'rest/api/login',
load: function(response, ioArgs) {
hideLoginWaitDialog();
if (response != 'logged in') {
// TODO: why isn't error function being called in this case
alert('error logging in, response: ' + response);
return;
}
dojo.cookie("loggedinuser", userString, {expires: 5});
updateLoggedInUserWelcome();
},
error: function(response, ioArgs) {
hideLoginWaitDialog();
alert('error logging in, response: ' + response);
}
});
}
function logout() {
updateLoggedInUserWelcome();
var loggedinuser = dojo.cookie("loggedinuser");
if (loggedinuser == null) {
return;
}
dojo.xhrGet({
content : {
login: loggedinuser
},
url: 'rest/api/login/logout',
load: function(response, ioArgs) {
if (response != 'logged out') {
// TODO: why isn't error function being called in this case
alert('error logging out, response: ' + response);
return;
}
dojo.cookie("loggedinuser", null, {expires: -1});
updateLoggedInUserWelcome();
window.location='index.html';
},
error: function(response, ioArgs) {
alert('error logging out, response: ' + response);
}
});
}
function dateFormatter(data) {
var d = new Date(data);
return dojo.date.locale.format(d, {selector: 'date', datePattern: 'MMMM d, yyyy - hh:mm a'});
}
function currencyFormatter(data) {
return dojo.currency.format(data, {currency: "USD"});
}
// genned from mongo by: db.airportcodes.find({}, {airportCode:1, airportName:1}).forEach(function(f){print(tojson(f, '', true));});
// switch airportCode to id
var airportCodes = [
{ airportName : "Brussels", id : "BRU" },
{ airportName : "Cairo", id : "CAI" },
{ airportName : "Dubai", id : "DXB" },
{ airportName : "Geneva", id : "GVA" },
{ airportName : "Istanbul", id : "IST" },
{ airportName : "Karachi", id : "KHI" },
{ airportName : "Kuwait", id : "KWI" },
{ airportName : "Lagos", id : "LOS" },
{ airportName : "Manila", id : "MNL" },
{ airportName : "Mexico City", id : "MEX" },
{ airportName : "Nairobi", id : "NBO" },
{ airportName : "Prague", id : "PRG" },
{ airportName : "Rio de Janeir", id : "GIG" },
{ airportName : "Stockholm", id : "ARN" },
{ airportName : "Mumbai", id : "BOM" },
{ airportName : "Delhi", id : "DEL" },
{ airportName : "Frankfurt", id : "FRA" },
{ airportName : "Hong Kong", id : "HKG" },
{ airportName : "London", id : "LHR" },
{ airportName : "Montreal", id : "YUL" },
{ airportName : "Moscow", id : "SVO" },
{ airportName : "New York", id : "JFK" },
{ airportName : "Paris", id : "CDG" },
{ airportName : "Rome", id : "FCO" },
{ airportName : "Singapore", id : "SIN" },
{ airportName : "Sydney", id : "SYD" },
{ airportName : "Tehran", id : "IKA" },
{ airportName : "Tokyo", id : "NRT" },
{ airportName : "Amsterdam", id : "AMS" },
{ airportName : "Aukland", id : "AKL" },
{ airportName : "Bangkok", id : "BKK" }
];
function airportCodeToAirportName(airportCode) {
var airports = dojo.filter(airportCodes, function (item) { return item.id == airportCode; } );
if (airports.length > 0) {
return airports[0].airportName;
}
return airportCode;
} | {'content_hash': '300e7cbc6b93ab13081c39c364a6668a', 'timestamp': '', 'source': 'github', 'line_count': 135, 'max_line_length': 133, 'avg_line_length': 28.992592592592594, 'alnum_prop': 0.631578947368421, 'repo_name': 'WASdev/sample.acmeair', 'id': 'e15b4f3bcd878fb14ddd88514f530ed9213bd57e', 'size': '4651', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'acmeair-webapp/src/main/webapp/js/acmeair-common.js', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'CSS', 'bytes': '3463'}, {'name': 'HTML', 'bytes': '42553'}, {'name': 'Java', 'bytes': '99145'}, {'name': 'JavaScript', 'bytes': '4651'}]} |
/**
* Created by rafal on 25.05.2017.
*/
function editButtonOnClick() {
$("#emailInput").prop('disabled', false);
$("#nameInput").prop('disabled', false);
$("#surnameInput").prop('disabled', false);
$("#imageInput").prop('disabled', false);
$("#phoneInput").prop('disabled', false);
$("#button-edit").hide();
$("#button-save").show();
} | {'content_hash': '8405a9b2472c1e0ec0f10fc56e71b516', 'timestamp': '', 'source': 'github', 'line_count': 15, 'max_line_length': 47, 'avg_line_length': 24.6, 'alnum_prop': 0.5772357723577236, 'repo_name': 'maciejole/fBot', 'id': '74d9beea1791dfb916000dc63dd602503c22c331', 'size': '984', 'binary': False, 'copies': '1', 'ref': 'refs/heads/developer', 'path': 'src/main/resources/static/js/account.js', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '5006'}, {'name': 'CSS', 'bytes': '4647'}, {'name': 'HTML', 'bytes': '68193'}, {'name': 'Java', 'bytes': '265265'}, {'name': 'JavaScript', 'bytes': '14859'}, {'name': 'Shell', 'bytes': '7058'}]} |
class ScopedHandle {
public:
ScopedHandle() : handle_(NULL) {
}
explicit ScopedHandle(HANDLE h) : handle_(NULL) {
Set(h);
}
~ScopedHandle() {
Close();
}
// Use this instead of comparing to INVALID_HANDLE_VALUE to pick up our NULL
// usage for errors.
bool IsValid() const {
return handle_ != NULL;
}
void Set(HANDLE new_handle) {
Close();
// Windows is inconsistent about invalid handles, so we always use NULL
if (new_handle != INVALID_HANDLE_VALUE)
handle_ = new_handle;
}
HANDLE Get() {
return handle_;
}
operator HANDLE() { return handle_; }
HANDLE Take() {
// transfers ownership away from this object
HANDLE h = handle_;
handle_ = NULL;
return h;
}
void Close() {
if (handle_) {
if (!::CloseHandle(handle_)) {
NOTREACHED();
}
handle_ = NULL;
}
}
private:
HANDLE handle_;
DISALLOW_EVIL_CONSTRUCTORS(ScopedHandle);
};
// Like ScopedHandle, but for HANDLEs returned from FindFile().
class ScopedFindFileHandle {
public:
explicit ScopedFindFileHandle(HANDLE handle) : handle_(handle) {
// Windows is inconsistent about invalid handles, so we always use NULL
if (handle_ == INVALID_HANDLE_VALUE)
handle_ = NULL;
}
~ScopedFindFileHandle() {
if (handle_)
FindClose(handle_);
}
// Use this instead of comparing to INVALID_HANDLE_VALUE to pick up our NULL
// usage for errors.
bool IsValid() const { return handle_ != NULL; }
operator HANDLE() { return handle_; }
private:
HANDLE handle_;
DISALLOW_EVIL_CONSTRUCTORS(ScopedFindFileHandle);
};
// Like ScopedHandle but for HDC. Only use this on HDCs returned from
// CreateCompatibleDC. For an HDC returned by GetDC, use ReleaseDC instead.
class ScopedHDC {
public:
ScopedHDC() : hdc_(NULL) { }
explicit ScopedHDC(HDC h) : hdc_(h) { }
~ScopedHDC() {
Close();
}
HDC Get() {
return hdc_;
}
void Set(HDC h) {
Close();
hdc_ = h;
}
operator HDC() { return hdc_; }
private:
void Close() {
#ifdef NOGDI
assert(false);
#else
if (hdc_)
DeleteDC(hdc_);
#endif // NOGDI
}
HDC hdc_;
DISALLOW_EVIL_CONSTRUCTORS(ScopedHDC);
};
// Like ScopedHandle but for GDI objects.
template<class T>
class ScopedGDIObject {
public:
ScopedGDIObject() : object_(NULL) {}
explicit ScopedGDIObject(T object) : object_(object) {}
~ScopedGDIObject() {
Close();
}
T Get() {
return object_;
}
void Set(T object) {
if (object_ && object != object_)
Close();
object_ = object;
}
ScopedGDIObject& operator=(T object) {
Set(object);
return *this;
}
operator T() { return object_; }
private:
void Close() {
if (object_)
DeleteObject(object_);
}
T object_;
DISALLOW_COPY_AND_ASSIGN(ScopedGDIObject);
};
// Typedefs for some common use cases.
typedef ScopedGDIObject<HBITMAP> ScopedBitmap;
typedef ScopedGDIObject<HRGN> ScopedHRGN;
typedef ScopedGDIObject<HFONT> ScopedHFONT;
// Like ScopedHandle except for HGLOBAL.
template<class T>
class ScopedHGlobal {
public:
explicit ScopedHGlobal(HGLOBAL glob) : glob_(glob) {
data_ = static_cast<T*>(GlobalLock(glob_));
}
~ScopedHGlobal() {
GlobalUnlock(glob_);
}
T* get() { return data_; }
size_t Size() const { return GlobalSize(glob_); }
T* operator->() const {
assert(data_ != 0);
return data_;
}
private:
HGLOBAL glob_;
T* data_;
DISALLOW_EVIL_CONSTRUCTORS(ScopedHGlobal);
};
#endif // BASE_SCOPED_HANDLE_WIN_H_
| {'content_hash': '8730e2e87d16c36be4f2aa7e64f1d64a', 'timestamp': '', 'source': 'github', 'line_count': 189, 'max_line_length': 78, 'avg_line_length': 18.788359788359788, 'alnum_prop': 0.6322162771050408, 'repo_name': 'amyvmiwei/chromium', 'id': 'dbd0627d52f63a2e7881f96a8868da31bc5c6ae5', 'size': '4385', 'binary': False, 'copies': '5', 'ref': 'refs/heads/trunk', 'path': 'base/scoped_handle_win.h', 'mode': '33188', 'license': 'bsd-3-clause', 'language': []} |
namespace Kephas.Data.Client.Queries.Conversion.ExpressionConverters
{
using System;
using System.Linq.Expressions;
/// <summary>
/// Expression converter for the greater-than operator.
/// </summary>
[Operator("$gt")]
public class GtExpressionConverter : BinaryExpressionConverterBase
{
/// <summary>
/// Initializes a new instance of the <see cref="GtExpressionConverter"/> class.
/// </summary>
public GtExpressionConverter()
: base((Func<Expression, Expression, BinaryExpression>)Expression.GreaterThan)
{
}
}
} | {'content_hash': 'b274bd2f544bdfd031d9fe3212e6cadd', 'timestamp': '', 'source': 'github', 'line_count': 20, 'max_line_length': 90, 'avg_line_length': 30.6, 'alnum_prop': 0.6454248366013072, 'repo_name': 'quartz-software/kephas', 'id': 'ffe4740c58ebfeccc82610aeabd645b1b1a8551a', 'size': '1189', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'src/Kephas.Data.Client/Queries/Conversion/ExpressionConverters/GtExpressionConverter.cs', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Batchfile', 'bytes': '1940'}, {'name': 'C#', 'bytes': '3855441'}, {'name': 'PowerShell', 'bytes': '3685'}, {'name': 'TypeScript', 'bytes': '9590'}]} |
// Copyright 2011, 2012 Anaplan Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
package com.anaplan.client;
import com.anaplan.client.auth.Authenticator;
import com.anaplan.client.auth.AuthenticatorFactory;
import com.anaplan.client.dto.WorkspaceData;
import com.anaplan.client.transport.AnaplanApiProvider;
import com.anaplan.client.transport.ConnectionProperties;
import com.google.common.base.Preconditions;
import java.io.Closeable;
import java.lang.ref.Reference;
import java.net.URI;
import java.net.URISyntaxException;
import java.util.Map;
import java.util.WeakHashMap;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
/**
* An authenticated connection to the Anaplan API service.
*/
public class Service implements Closeable {
private static final Logger LOG = LoggerFactory.getLogger(Service.class);
private static final URI PRODUCTION_API_ROOT;
private static final URI PRODUCTION_AUTH_API_ROOT;
private String userId;
static {
try {
PRODUCTION_API_ROOT = new URI("https://api.anaplan.com/");
PRODUCTION_AUTH_API_ROOT = new URI("https://auth.anaplan.com/");
} catch (URISyntaxException uriSyntaxException) {
throw new ExceptionInInitializerError(uriSyntaxException);
}
}
private ConnectionProperties props;
private AnaplanApiProvider apiProvider;
private Authenticator authProvider;
public AnaplanApiProvider getApiProvider() {
return apiProvider;
}
public void setApiProvider(AnaplanApiProvider apiProvider) {
this.apiProvider = apiProvider;
}
public Authenticator getAuthProvider() {
return authProvider;
}
public void setAuthProvider(Authenticator authProvider) {
this.authProvider = authProvider;
}
// Cached Workspace instances
private Map<WorkspaceData, Reference<Workspace>> workspaceCache = new WeakHashMap<>();
public Service(ConnectionProperties properties) {
if (properties.getApiServicesUri() == null) {
properties.setApiServicesUri(PRODUCTION_API_ROOT);
}
if (properties.getAuthServiceUri() == null) {
properties.setAuthServiceUri(PRODUCTION_AUTH_API_ROOT);
}
LOG.info("Initializing Service...");
this.props = properties;
this.authProvider = AuthenticatorFactory.getAuthenticator(properties);
this.apiProvider = new AnaplanApiProvider(properties, authProvider);
}
/**
* Authenticates using provided credentials
*/
public void authenticate() {
Preconditions.checkNotNull(props.getApiCredentials(), "No service credentials present to authenticate with.");
authProvider.getAuthToken();
}
/**
* Retrieve a reference to a workspace from its workspaceId.
*
* @param workspaceId The workspace ID or name of the workspace.
* @return The workspace; null if no such workspace exists or the user is
* not permitted to access the workspace.
* @throws com.anaplan.client.ex.AnaplanAPIException an error occurred.
*/
public Workspace getWorkspace(String workspaceId) {
return new Workspace(this, new WorkspaceData(workspaceId));
}
/**
* Release any system resources associated with this instance.
*/
@Override
public void close() {
if (apiProvider != null) {
apiProvider = null;
authProvider = null;
}
}
}
| {'content_hash': '2467523c3da22832a1c5ed8074abac15', 'timestamp': '', 'source': 'github', 'line_count': 121, 'max_line_length': 118, 'avg_line_length': 33.082644628099175, 'alnum_prop': 0.6997252060954284, 'repo_name': 'data-integrations/anaplan', 'id': '639adddd845b6cc72a75aed634b57f0a040bd2ea', 'size': '4003', 'binary': False, 'copies': '1', 'ref': 'refs/heads/develop', 'path': 'src/main/java/com/anaplan/client/Service.java', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
import React from 'react';
import classnames from 'classnames';
const Checkbox = ({ name, label, topLabel, ...props }) => (
<label
className={classnames('checkbox', {
'top-label': topLabel
})}
htmlFor={name}
>
{topLabel && label}
<input type="checkbox" id={name} name={name} {...props} />
<span />
{!topLabel && label}
</label>
);
export default Checkbox;
| {'content_hash': '2d20ec29232954f7f9d5952f65344944', 'timestamp': '', 'source': 'github', 'line_count': 18, 'max_line_length': 62, 'avg_line_length': 22.11111111111111, 'alnum_prop': 0.592964824120603, 'repo_name': 'khlieng/name_pending', 'id': 'b975e4afe420feb1bbd04784ba108454cd00ede6', 'size': '398', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'client/js/components/ui/Checkbox.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '10729'}, {'name': 'Go', 'bytes': '102676'}, {'name': 'HTML', 'bytes': '354'}, {'name': 'JavaScript', 'bytes': '69316'}, {'name': 'Shell', 'bytes': '932'}]} |
/**
* VirtualBlink1 -- on-screen representation of what's going on with blink(1) device
* - represents current colors (from Blink1Service) on-screen
* - runs multi-channel fading algorithm, similar to real blink(1)
* - updates Blink1ColorPicker with fade updates
*
*/
"use strict";
var React = require('react');
var log = require('../../logger');
var Blink1Service = require('../../server/blink1Service');
var tinycolor = require('tinycolor2');
var d3 = require('d3-timer');
// var blackc = tinycolor('#000000');
var VirtualBlink1 = React.createClass({
getInitialState: function() {
return {
// colors: ['#ff00ff', '#00ffff', 0,0, 0,0,0,0, 0,0,0,0 ], // FIXME: should be blink1service.getCurrentColors()
// colors: [ tinycolor('#ff00ff'), tinycolor('#00ffff') ],
// nextColors: [ tinycolor('#ff00ff'), tinycolor('#00ffff') ],
// lastColors:[ tinycolor('#ff00ff'), tinycolor('#00ffff')],
colors: new Array(2).fill(tinycolor('#000033')),
// millis: []
};
},
componentDidMount: function() {
Blink1Service.addChangeListener( this.fetchBlink1Color, "virtualBlink1" );
},
// callback to Blink1Service
fetchBlink1Color: function() {
// log.msg("virtualBlink1.fetchBlink1Color");
this.lastColors = this.state.colors;
// this.ledn = Blink1Service.getCurrentLedN(); // FIXME: need this??
this.blink1Id = Blink1Service.getCurrentBlink1Id();
this.nextColors = Blink1Service.getCurrentColors( this.blink1Id );
this._colorFaderStart();
},
handleBlink1IdChange: function(id) {
Blink1Service.setCurrentBlink1Id(id);
},
handleClick: function() {
Blink1Service.reloadConfig();
},
blink1Id: 0,
nextColors: new Array(2).fill(tinycolor('#ff00ff')), // ledn colors
lastColors: new Array(2).fill(tinycolor('#ff00ff')), // last ledn colors
timer: null,
faderMillis: 0,
currentMillis: 0,
stepMillis: 25,
//
// FIXME FIXME FIXME: this whole file is confused in its thinking
//
_colorFaderStart: function() {
// if( this.timer ) { clearTimeout(this.timer); }
// if( this.timer ) { this.timer.stop(); }
// if( !this.timer ) {
// this.timer = d3.interval( this._colorFaderInterval, this.stepMillis );
// }
this.faderMillis = 0; // shouldb be 0; // goes from 0 to currentMillis
this.currentMillis = Blink1Service.getCurrentMillis() || this.stepMillis; // FIXME: HACK
this.currentMillis = this.currentMillis / 2; // FIXME: to match what blink1service does
var now = d3.now();
var nowDelta = now - this.lastNow;
if( nowDelta <= 100 || this.currentMillis <= 100 ) {
this.faderMillis = this.currentMillis; // no fading, go to color immediately
}
this.lastNow = now;
// log.msg("--- START:",nowDelta, "currentMillis:", this.currentMillis, "stepMillis:",this.stepMillis, "next:",this.nextColors );
this._colorFader();
},
_colorFader: function() {
var self = this;
var p = (this.faderMillis / this.currentMillis); // "percentage done", ranges from 0.0 to 1.0 -ish
if( p > 1.0 ) { p = 1.0; } // guard against going over 100%
// log.msg("--- fader:", "faderMillis:", this.faderMillis, "p:",p, "colors:", this.state.colors);
self.faderMillis += self.stepMillis;
var colors = self.state.colors;
colors.slice().map( function(c,i) { // copy and modify in place? FIXME:????
var oldc = self.lastColors[i].toRgb();
var newc = self.nextColors[i].toRgb();
var r = (1-p) * (oldc.r) + (p * newc.r);
var g = (1-p) * (oldc.g) + (p * newc.g);
var b = (1-p) * (oldc.b) + (p * newc.b);
var tmpc = tinycolor( {r:r,g:g,b:b} );
colors[i] = tmpc;
});
self.setState({colors: colors});
this.timer = (p<1) ? d3.timeout( self._colorFader, self.stepMillis ) : null;
},
render: function() {
var topLum = this.state.colors[0].toHsl().l; //was .getLuminance();
var botLum = this.state.colors[1].toHsl().l;
var topColor = tinycolor(this.state.colors[0]).setAlpha(topLum);
var botColor = tinycolor(this.state.colors[1]).setAlpha(botLum); // was (Math.pow(botLum,0.5));
// var topColor = tinycolor(this.state.colors[0]).setAlpha(Math.pow(topLum,0.5));
// var botColor = tinycolor(this.state.colors[1]).setAlpha(Math.pow(botLum,0.5));
var colorDesc = "Click for device rescan\nLED A:" +
this.state.colors[0].toHexString() + "\nLED B:"+ this.state.colors[1].toHexString();
// console.log("VirtualBlink1: color0:",topColor.toRgbString());
var topgradient = // (this.state.colors[0].toHexString() === '#000000') ?
"radial-gradient(160px 90px at 150px 50px," + topColor.toRgbString() + " 20%, rgba(255,255,255,0.2) 55% )";
var botgradient = //(this.state.colors[1].toHexString() === '#000000') ? 'url()' :
"radial-gradient(160px 90px at 150px 110px," + botColor.toRgbString() + " 20%, rgba(255,255,255,0.2) 55% )";
// "radial-gradient(160px 90px at 150px 110px," + this.state.colors[1].toRgbString() + " 0%, rgba(255,255,255,0.2) 55% )";
// linear-gradient(to bottom, rgba(30,87,153,1) 0%,rgba(66,124,183,0) 38%,rgba(125,185,232,0) 100%);
var virtBlink1style = { width: 240, height: 150,
margin: 0, padding: 0, marginTop:-15, // FIXME why do I need marginTop-15?
border: '0px solid grey',
//background: this.props.blink1Color
backgroundImage: [
topgradient,
"url(images/device-light-bg.png)",
// topgradient,
"url(images/device-light-mask.png)",
// "url(images/device-preview.png)",
"url(images/device-light-bg-bottom.png)",
"url(images/device-light-bg-top.png)",
botgradient,
]
};
// <img style={img2style} src="images/device-light-bg.png" />
// <img style={img3style} src="images/device-light-mask.png" />
// var img1style = { width: 240, height: 192 };
// var img2style = { width: 240, height: 192, position: "relative", top: 0 };
// var img3style = { width: 240, height: 192, position: "relative", top: 0 };
var makeMiniBlink1 = function(serial,idx) {
var colrs = Blink1Service.getCurrentColors(serial);
var colrA = colrs[0];
var colrB = colrs[1];
// log.msg(idx+":"+serial+": ", colrA.toHexString(),colrB.toHexString());
if( colrA.getBrightness() === 0 ) { colrA = tinycolor('#888'); }
if( colrB.getBrightness() === 0 ) { colrB = tinycolor('#888'); }
var titlestr = 'serial:'+serial +' A/B:'+colrs[0].toHexString().toUpperCase()+'/'+colrs[1].toHexString().toUpperCase();
colrA = colrA.toHexString();
colrB = colrB.toHexString();
var borderStyle = (serial===this.blink1Id) ? '2px solid #aaa' : '2px solid #eee';
return (<div key={idx} onClick={this.handleBlink1IdChange.bind(null,serial)} value={serial}
style={{border:borderStyle, borderRadius:5, padding:0, margin:3 }}>
<div style={{width:20, height:7, margin:0,padding:0,background:colrA, borderRadius:'3px 3px 0 0'}}
title={titlestr} ></div>
<div style={{width:20, height:7, margin:0,padding:0,background:colrB, borderRadius:'0 0 3px 3px'}}
title={titlestr} ></div>
</div>
);
};
var serials = Blink1Service.getAllSerials();
var miniBlink1s = (serials.length > 1 ) ? serials.map(makeMiniBlink1, this) : null;
return (
<div style={{position:'relative', border:'0px solid green'}}>
<div style={virtBlink1style} title={colorDesc} onClick={this.handleClick}></div>
<div style={{position:'absolute', top:5, left:0, padding:0, marginLeft:0}}>
{miniBlink1s}
</div>
</div>
);
}
});
module.exports = VirtualBlink1;
| {'content_hash': '08e1a538489c056bfe364cb0974eb2c3', 'timestamp': '', 'source': 'github', 'line_count': 180, 'max_line_length': 137, 'avg_line_length': 46.61666666666667, 'alnum_prop': 0.5737099273030628, 'repo_name': 'todbot/Blink1Control2', 'id': 'a87c3c5a6bd341d888ead7c40cb52218b576ddd3', 'size': '8391', 'binary': False, 'copies': '1', 'ref': 'refs/heads/main-es5', 'path': 'app/components/gui/virtualBlink1.js', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'CSS', 'bytes': '13571'}, {'name': 'HTML', 'bytes': '34676'}, {'name': 'JavaScript', 'bytes': '324241'}]} |
package com.facebook.buck.util.config;
import com.google.common.base.Joiner;
import java.io.IOException;
import java.io.Reader;
import java.io.StringReader;
public class ConfigBuilder {
// Utility class, do not instantiate.
private ConfigBuilder() {}
public static Config createFromText(String... lines) {
return new Config(rawFromLines(lines));
}
public static RawConfig rawFromLines(String... lines) {
try {
return rawFromReader(new StringReader(Joiner.on('\n').join(lines)));
} catch (IOException e) {
throw new AssertionError("Ini read from StringReader should not throw", e);
}
}
public static RawConfig rawFromReader(Reader reader) throws IOException {
return RawConfig.of(Inis.read(reader));
}
}
| {'content_hash': '326b32906b1f824e0cbbf620ce0db129', 'timestamp': '', 'source': 'github', 'line_count': 29, 'max_line_length': 81, 'avg_line_length': 26.137931034482758, 'alnum_prop': 0.7189973614775725, 'repo_name': 'Addepar/buck', 'id': '75fabb5e8508a797797061811565c306ba9389f2', 'size': '1374', 'binary': False, 'copies': '6', 'ref': 'refs/heads/master', 'path': 'test/com/facebook/buck/util/config/ConfigBuilder.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Assembly', 'bytes': '1585'}, {'name': 'Batchfile', 'bytes': '3875'}, {'name': 'C', 'bytes': '281239'}, {'name': 'C#', 'bytes': '237'}, {'name': 'C++', 'bytes': '18966'}, {'name': 'CSS', 'bytes': '56106'}, {'name': 'D', 'bytes': '1017'}, {'name': 'Dockerfile', 'bytes': '2081'}, {'name': 'Go', 'bytes': '10020'}, {'name': 'Groovy', 'bytes': '3362'}, {'name': 'HTML', 'bytes': '11252'}, {'name': 'Haskell', 'bytes': '1008'}, {'name': 'IDL', 'bytes': '480'}, {'name': 'Java', 'bytes': '29247474'}, {'name': 'JavaScript', 'bytes': '938678'}, {'name': 'Kotlin', 'bytes': '25755'}, {'name': 'Lex', 'bytes': '12772'}, {'name': 'MATLAB', 'bytes': '47'}, {'name': 'Makefile', 'bytes': '1916'}, {'name': 'OCaml', 'bytes': '4935'}, {'name': 'Objective-C', 'bytes': '176958'}, {'name': 'Objective-C++', 'bytes': '34'}, {'name': 'PowerShell', 'bytes': '2244'}, {'name': 'Prolog', 'bytes': '1486'}, {'name': 'Python', 'bytes': '2076151'}, {'name': 'Roff', 'bytes': '1207'}, {'name': 'Rust', 'bytes': '5716'}, {'name': 'Scala', 'bytes': '5082'}, {'name': 'Shell', 'bytes': '77999'}, {'name': 'Smalltalk', 'bytes': '194'}, {'name': 'Swift', 'bytes': '11393'}, {'name': 'Thrift', 'bytes': '48595'}, {'name': 'Yacc', 'bytes': '323'}]} |
<?xml version="1.0" encoding="utf-8"?>
<manifest xmlns:android="http://schemas.android.com/apk/res/android"
package="ar.edu.unc.famaf.redditreader">
<uses-permission android:name="android.permission.INTERNET" />
<uses-permission android:name="android.permission.ACCESS_NETWORK_STATE" />
<application
android:allowBackup="true"
android:icon="@mipmap/ic_launcher"
android:label="@string/app_name"
android:supportsRtl="true"
android:theme="@style/AppTheme">
<activity
android:name=".ui.LoginActivity"
android:label="@string/app_name" />
<activity
android:name=".ui.NewsActivity"
android:label="@string/app_name"
android:theme="@style/AppTheme.NoActionBar">
<intent-filter>
<action android:name="android.intent.action.MAIN" />
<category android:name="android.intent.category.LAUNCHER" />
</intent-filter>
</activity>
<activity android:name=".ui.NewsDetailActivity" />
<activity android:name=".ui.WebViewActivity"></activity>
</application>
</manifest> | {'content_hash': '89e58d8ba7b79c62de01f254787b145f', 'timestamp': '', 'source': 'github', 'line_count': 31, 'max_line_length': 78, 'avg_line_length': 37.645161290322584, 'alnum_prop': 0.6229648671808055, 'repo_name': 'agustinhurquiza/RedditRead_new', 'id': '0c5c4cd2d55001229386ccc7ac8453f0d0b897c3', 'size': '1167', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'app/src/main/AndroidManifest.xml', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Java', 'bytes': '55001'}]} |
@class NSEntityDescription;
@class NSPersistentStore;
@class NSURL;
COREDATA_EXPORT_CLASS
@interface NSManagedObjectID : NSObject <NSCopying>
@property (readonly, strong) NSEntityDescription* entity STUB_PROPERTY;
@property (readonly, getter=isTemporaryID) BOOL temporaryID STUB_PROPERTY;
@property (readonly, assign) NSPersistentStore* persistentStore STUB_PROPERTY;
- (NSURL*)URIRepresentation STUB_METHOD;
@end
| {'content_hash': '4e20ed99ce56795365e40e2b208cfe44', 'timestamp': '', 'source': 'github', 'line_count': 11, 'max_line_length': 78, 'avg_line_length': 37.72727272727273, 'alnum_prop': 0.8192771084337349, 'repo_name': 'autodesk-forks/WinObjC', 'id': '25ed153a8d346be7427d73ecb4ffe769b9471a6f', 'size': '1275', 'binary': False, 'copies': '17', 'ref': 'refs/heads/adsk-develop', 'path': 'include/CoreData/NSManagedObjectID.h', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Assembly', 'bytes': '13134'}, {'name': 'C', 'bytes': '6326273'}, {'name': 'C#', 'bytes': '132853'}, {'name': 'C++', 'bytes': '3539189'}, {'name': 'Lex', 'bytes': '4667'}, {'name': 'M', 'bytes': '77709'}, {'name': 'Makefile', 'bytes': '3446'}, {'name': 'Objective-C', 'bytes': '8138600'}, {'name': 'Objective-C++', 'bytes': '10326175'}, {'name': 'PowerShell', 'bytes': '15625'}, {'name': 'Python', 'bytes': '7658'}, {'name': 'Yacc', 'bytes': '9740'}]} |
/* TEMPLATE GENERATED TESTCASE FILE
Filename: CWE122_Heap_Based_Buffer_Overflow__cpp_CWE193_char_loop_52b.cpp
Label Definition File: CWE122_Heap_Based_Buffer_Overflow__cpp_CWE193.label.xml
Template File: sources-sink-52b.tmpl.cpp
*/
/*
* @description
* CWE: 122 Heap Based Buffer Overflow
* BadSource: Allocate memory for a string, but do not allocate space for NULL terminator
* GoodSource: Allocate enough memory for a string and the NULL terminator
* Sink: loop
* BadSink : Copy array to data using a loop
* Flow Variant: 52 Data flow: data passed as an argument from one function to another to another in three different source files
*
* */
#include "std_testcase.h"
#ifndef _WIN32
#include <wchar.h>
#endif
/* MAINTENANCE NOTE: The length of this string should equal the 10 */
#define SRC_STRING "AAAAAAAAAA"
namespace CWE122_Heap_Based_Buffer_Overflow__cpp_CWE193_char_loop_52
{
/* all the sinks are the same, we just want to know where the hit originated if a tool flags one */
#ifndef OMITBAD
/* bad function declaration */
void badSink_c(char * data);
void badSink_b(char * data)
{
badSink_c(data);
}
#endif /* OMITBAD */
#ifndef OMITGOOD
/* goodG2B uses the GoodSource with the BadSink */
void goodG2BSink_c(char * data);
void goodG2BSink_b(char * data)
{
goodG2BSink_c(data);
}
#endif /* OMITGOOD */
} /* close namespace */
| {'content_hash': 'b8db0b7bc68a5fd21809556185be4673', 'timestamp': '', 'source': 'github', 'line_count': 55, 'max_line_length': 129, 'avg_line_length': 25.90909090909091, 'alnum_prop': 0.7003508771929825, 'repo_name': 'maurer/tiamat', 'id': 'f9b942ff513059d38aa2a49016f50ca2b0e33547', 'size': '1425', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'samples/Juliet/testcases/CWE122_Heap_Based_Buffer_Overflow/s01/CWE122_Heap_Based_Buffer_Overflow__cpp_CWE193_char_loop_52b.cpp', 'mode': '33188', 'license': 'mit', 'language': []} |
#ifndef PC_VIDEOTRACKSOURCE_H_
#define PC_VIDEOTRACKSOURCE_H_
#include "api/mediastreaminterface.h"
#include "api/notifier.h"
#include "media/base/mediachannel.h"
#include "media/base/videosinkinterface.h"
#include "rtc_base/thread_checker.h"
// VideoTrackSource implements VideoTrackSourceInterface.
namespace webrtc {
class VideoTrackSource : public Notifier<VideoTrackSourceInterface> {
public:
VideoTrackSource(rtc::VideoSourceInterface<VideoFrame>* source, bool remote);
void SetState(SourceState new_state);
// OnSourceDestroyed clears this instance pointer to |source_|. It is useful
// when the underlying rtc::VideoSourceInterface is destroyed before the
// reference counted VideoTrackSource.
void OnSourceDestroyed();
SourceState state() const override { return state_; }
bool remote() const override { return remote_; }
bool is_screencast() const override { return false; }
rtc::Optional<bool> needs_denoising() const override { return rtc::nullopt; }
bool GetStats(Stats* stats) override { return false; }
void AddOrUpdateSink(rtc::VideoSinkInterface<VideoFrame>* sink,
const rtc::VideoSinkWants& wants) override;
void RemoveSink(rtc::VideoSinkInterface<VideoFrame>* sink) override;
private:
rtc::ThreadChecker worker_thread_checker_;
rtc::VideoSourceInterface<VideoFrame>* source_;
cricket::VideoOptions options_;
SourceState state_;
const bool remote_;
};
} // namespace webrtc
#endif // PC_VIDEOTRACKSOURCE_H_
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<!-- NewPage -->
<html lang="zh">
<head>
<!-- Generated by javadoc (1.8.0_45) on Tue Jun 30 20:58:17 CST 2015 -->
<title>LibGoogleCalendarConnector</title>
<meta name="date" content="2015-06-30">
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var methods = {"i0":9,"i1":9,"i2":9};
var tabs = {65535:["t0","All Methods"],1:["t1","Static Methods"],8:["t4","Concrete Methods"]};
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<li>Nested | </li>
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<li><a href="#method.summary">Method</a></li>
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<h2 title="Class LibGoogleCalendarConnector" class="title">Class LibGoogleCalendarConnector</h2>
</div>
<div class="contentContainer">
<ul class="inheritance">
<li>java.lang.Object</li>
<li>
<ul class="inheritance">
<li>LibGoogleCalendarConnector</li>
</ul>
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<pre>public final class <span class="typeNameLabel">LibGoogleCalendarConnector</span>
extends java.lang.Object</pre>
<div class="block">The connector library for Google Calendar accounts.</div>
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<h3>Field Summary</h3>
<table class="memberSummary" border="0" cellpadding="3" cellspacing="0" summary="Field Summary table, listing fields, and an explanation">
<caption><span>Fields</span><span class="tabEnd"> </span></caption>
<tr>
<th class="colFirst" scope="col">Modifier and Type</th>
<th class="colLast" scope="col">Field and Description</th>
</tr>
<tr class="altColor">
<td class="colFirst"><code>private static java.lang.String</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#APPLICATION_NAME">APPLICATION_NAME</a></span></code>
<div class="block">The name of the application.</div>
</td>
</tr>
<tr class="rowColor">
<td class="colFirst"><code>private static java.lang.String</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#DATA_STORE_DIR">DATA_STORE_DIR</a></span></code>
<div class="block">A String representing the credential directory path.</div>
</td>
</tr>
<tr class="altColor">
<td class="colFirst"><code>private static com.google.api.client.util.store.FileDataStoreFactory</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#DATA_STORE_FACTORY">DATA_STORE_FACTORY</a></span></code>
<div class="block">A FileDataStoreFactory object built from the credential directory reference.</div>
</td>
</tr>
<tr class="rowColor">
<td class="colFirst"><code>private static java.io.File</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#DATA_STORE_REF">DATA_STORE_REF</a></span></code>
<div class="block">A File object referencing to the credential directory.</div>
</td>
</tr>
<tr class="altColor">
<td class="colFirst"><code>private static com.google.api.client.http.HttpTransport</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#HTTP_TRANSPORT">HTTP_TRANSPORT</a></span></code>
<div class="block">A HttpTransport object.</div>
</td>
</tr>
<tr class="rowColor">
<td class="colFirst"><code>private static com.google.api.client.json.JsonFactory</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#JSON_FACTORY">JSON_FACTORY</a></span></code>
<div class="block">A JsonFactory object.</div>
</td>
</tr>
<tr class="altColor">
<td class="colFirst"><code>private static java.util.List<java.lang.String></code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#SCOPES">SCOPES</a></span></code>
<div class="block">The scopes of the Google Calendar.</div>
</td>
</tr>
</table>
</li>
</ul>
<!-- ======== CONSTRUCTOR SUMMARY ======== -->
<ul class="blockList">
<li class="blockList"><a name="constructor.summary">
<!-- -->
</a>
<h3>Constructor Summary</h3>
<table class="memberSummary" border="0" cellpadding="3" cellspacing="0" summary="Constructor Summary table, listing constructors, and an explanation">
<caption><span>Constructors</span><span class="tabEnd"> </span></caption>
<tr>
<th class="colOne" scope="col">Constructor and Description</th>
</tr>
<tr class="altColor">
<td class="colOne"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#LibGoogleCalendarConnector--">LibGoogleCalendarConnector</a></span>()</code> </td>
</tr>
</table>
</li>
</ul>
<!-- ========== METHOD SUMMARY =========== -->
<ul class="blockList">
<li class="blockList"><a name="method.summary">
<!-- -->
</a>
<h3>Method Summary</h3>
<table class="memberSummary" border="0" cellpadding="3" cellspacing="0" summary="Method Summary table, listing methods, and an explanation">
<caption><span id="t0" class="activeTableTab"><span>All Methods</span><span class="tabEnd"> </span></span><span id="t1" class="tableTab"><span><a href="javascript:show(1);">Static Methods</a></span><span class="tabEnd"> </span></span><span id="t4" class="tableTab"><span><a href="javascript:show(8);">Concrete Methods</a></span><span class="tabEnd"> </span></span></caption>
<tr>
<th class="colFirst" scope="col">Modifier and Type</th>
<th class="colLast" scope="col">Method and Description</th>
</tr>
<tr id="i0" class="altColor">
<td class="colFirst"><code>static com.google.api.client.auth.oauth2.Credential</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#authorize--">authorize</a></span>()</code>
<div class="block">Creates an authorized Credential object.</div>
</td>
</tr>
<tr id="i1" class="rowColor">
<td class="colFirst"><code>static com.google.api.services.calendar.Calendar</code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#getCalendarService--">getCalendarService</a></span>()</code>
<div class="block">Build and return an authorized Calendar client service.</div>
</td>
</tr>
<tr id="i2" class="altColor">
<td class="colFirst"><code>static java.util.List<com.google.api.services.calendar.model.Event></code></td>
<td class="colLast"><code><span class="memberNameLink"><a href="LibGoogleCalendarConnector.html#getConnection--">getConnection</a></span>()</code>
<div class="block">Build a new authorized API client service and receive the event list.</div>
</td>
</tr>
</table>
<ul class="blockList">
<li class="blockList"><a name="methods.inherited.from.class.java.lang.Object">
<!-- -->
</a>
<h3>Methods inherited from class java.lang.Object</h3>
<code>clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait</code></li>
</ul>
</li>
</ul>
</li>
</ul>
</div>
<div class="details">
<ul class="blockList">
<li class="blockList">
<!-- ============ FIELD DETAIL =========== -->
<ul class="blockList">
<li class="blockList"><a name="field.detail">
<!-- -->
</a>
<h3>Field Detail</h3>
<a name="APPLICATION_NAME">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>APPLICATION_NAME</h4>
<pre>private static final java.lang.String APPLICATION_NAME</pre>
<div class="block">The name of the application.</div>
<dl>
<dt><span class="seeLabel">See Also:</span></dt>
<dd><a href="constant-values.html#LibGoogleCalendarConnector.APPLICATION_NAME">Constant Field Values</a></dd>
</dl>
</li>
</ul>
<a name="DATA_STORE_DIR">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>DATA_STORE_DIR</h4>
<pre>private static final java.lang.String DATA_STORE_DIR</pre>
<div class="block">A String representing the credential directory path.</div>
</li>
</ul>
<a name="DATA_STORE_REF">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>DATA_STORE_REF</h4>
<pre>private static final java.io.File DATA_STORE_REF</pre>
<div class="block">A File object referencing to the credential directory.</div>
</li>
</ul>
<a name="DATA_STORE_FACTORY">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>DATA_STORE_FACTORY</h4>
<pre>private static com.google.api.client.util.store.FileDataStoreFactory DATA_STORE_FACTORY</pre>
<div class="block">A FileDataStoreFactory object built from the credential directory reference.</div>
</li>
</ul>
<a name="JSON_FACTORY">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>JSON_FACTORY</h4>
<pre>private static final com.google.api.client.json.JsonFactory JSON_FACTORY</pre>
<div class="block">A JsonFactory object.</div>
</li>
</ul>
<a name="HTTP_TRANSPORT">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>HTTP_TRANSPORT</h4>
<pre>private static com.google.api.client.http.HttpTransport HTTP_TRANSPORT</pre>
<div class="block">A HttpTransport object.</div>
</li>
</ul>
<a name="SCOPES">
<!-- -->
</a>
<ul class="blockListLast">
<li class="blockList">
<h4>SCOPES</h4>
<pre>private static final java.util.List<java.lang.String> SCOPES</pre>
<div class="block">The scopes of the Google Calendar.</div>
</li>
</ul>
</li>
</ul>
<!-- ========= CONSTRUCTOR DETAIL ======== -->
<ul class="blockList">
<li class="blockList"><a name="constructor.detail">
<!-- -->
</a>
<h3>Constructor Detail</h3>
<a name="LibGoogleCalendarConnector--">
<!-- -->
</a>
<ul class="blockListLast">
<li class="blockList">
<h4>LibGoogleCalendarConnector</h4>
<pre>public LibGoogleCalendarConnector()</pre>
</li>
</ul>
</li>
</ul>
<!-- ============ METHOD DETAIL ========== -->
<ul class="blockList">
<li class="blockList"><a name="method.detail">
<!-- -->
</a>
<h3>Method Detail</h3>
<a name="authorize--">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>authorize</h4>
<pre>public static com.google.api.client.auth.oauth2.Credential authorize()
throws java.io.IOException</pre>
<div class="block">Creates an authorized Credential object.</div>
<dl>
<dt><span class="returnLabel">Returns:</span></dt>
<dd>a Credential object</dd>
<dt><span class="throwsLabel">Throws:</span></dt>
<dd><code>java.io.IOException</code> - an IOException object</dd>
</dl>
</li>
</ul>
<a name="getCalendarService--">
<!-- -->
</a>
<ul class="blockList">
<li class="blockList">
<h4>getCalendarService</h4>
<pre>public static com.google.api.services.calendar.Calendar getCalendarService()
throws java.io.IOException</pre>
<div class="block">Build and return an authorized Calendar client service.</div>
<dl>
<dt><span class="returnLabel">Returns:</span></dt>
<dd>a Calendar object</dd>
<dt><span class="throwsLabel">Throws:</span></dt>
<dd><code>java.io.IOException</code> - an IOException object</dd>
</dl>
</li>
</ul>
<a name="getConnection--">
<!-- -->
</a>
<ul class="blockListLast">
<li class="blockList">
<h4>getConnection</h4>
<pre>public static java.util.List<com.google.api.services.calendar.model.Event> getConnection()
throws java.io.IOException</pre>
<div class="block">Build a new authorized API client service and receive the event list.</div>
<dl>
<dt><span class="returnLabel">Returns:</span></dt>
<dd>a List of Event objects</dd>
<dt><span class="throwsLabel">Throws:</span></dt>
<dd><code>java.io.IOException</code> - an IOException object</dd>
</dl>
</li>
</ul>
</li>
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| {'content_hash': 'b1afe7894c86eba8d62bcc14d5791df2', 'timestamp': '', 'source': 'github', 'line_count': 464, 'max_line_length': 389, 'avg_line_length': 35.6551724137931, 'alnum_prop': 0.6681576402321083, 'repo_name': 'yuwen41200/personal-calendar', 'id': '0300ab7f1e3a20a678ecad7d4ad865b5153b00e5', 'size': '16544', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'docs/LibGoogleCalendarConnector.html', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Batchfile', 'bytes': '3087'}, {'name': 'Java', 'bytes': '37839'}, {'name': 'Shell', 'bytes': '5799'}]} |
The MIT License (MIT)
Copyright (c) 2016 Stephen Royle
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
| {'content_hash': '224eba40270d2f301f89234d264c252e', 'timestamp': '', 'source': 'github', 'line_count': 21, 'max_line_length': 78, 'avg_line_length': 51.42857142857143, 'alnum_prop': 0.8037037037037037, 'repo_name': 'quantixed/blog-standard', 'id': '5e31b40b8265afe9da1d4a23b852a347c921a5ec', 'size': '1080', 'binary': False, 'copies': '5', 'ref': 'refs/heads/master', 'path': 'LICENSE.md', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'IGOR Pro', 'bytes': '27210'}, {'name': 'Ruby', 'bytes': '467'}]} |
<?php
/* vim: set expandtab sw=4 ts=4 sts=4: */
/**
* hold PMA_Theme class
*
* @package PhpMyAdmin
*/
if (! defined('PHPMYADMIN')) {
exit;
}
/**
* handles theme
*
* @todo add the possibility to make a theme depend on another theme
* and by default on original
* @todo make all components optional - get missing components from 'parent' theme
*
* @package PhpMyAdmin
*/
class PMA_Theme
{
/**
* @var string theme version
* @access protected
*/
var $version = '0.0.0.0';
/**
* @var string theme name
* @access protected
*/
var $name = '';
/**
* @var string theme id
* @access protected
*/
var $id = '';
/**
* @var string theme path
* @access protected
*/
var $path = '';
/**
* @var string image path
* @access protected
*/
var $img_path = '';
/**
* @var integer last modification time for info file
* @access protected
*/
var $mtime_info = 0;
/**
* needed because sometimes, the mtime for different themes
* is identical
* @var integer filesize for info file
* @access protected
*/
var $filesize_info = 0;
/**
* @var array List of css files to load
* @access private
*/
private $_cssFiles = array(
'common',
'enum_editor',
'gis',
'navigation',
'pmd',
'rte',
'codemirror',
'jqplot',
'resizable-menu'
);
/**
* Loads theme information
*
* @return boolean whether loading them info was successful or not
* @access public
*/
function loadInfo()
{
if (! file_exists($this->getPath() . '/info.inc.php')) {
return false;
}
if ($this->mtime_info === filemtime($this->getPath() . '/info.inc.php')) {
return true;
}
@include $this->getPath() . '/info.inc.php';
// was it set correctly?
if (! isset($theme_name)) {
return false;
}
$this->mtime_info = filemtime($this->getPath() . '/info.inc.php');
$this->filesize_info = filesize($this->getPath() . '/info.inc.php');
if (isset($theme_full_version)) {
$this->setVersion($theme_full_version);
} elseif (isset($theme_generation, $theme_version)) {
$this->setVersion($theme_generation . '.' . $theme_version);
}
$this->setName($theme_name);
return true;
}
/**
* returns theme object loaded from given folder
* or false if theme is invalid
*
* @param string $folder path to theme
*
* @return PMA_Theme|false
* @static
* @access public
*/
static public function load($folder)
{
$theme = new PMA_Theme();
$theme->setPath($folder);
if (! $theme->loadInfo()) {
return false;
}
$theme->checkImgPath();
return $theme;
}
/**
* checks image path for existance - if not found use img from fallback theme
*
* @access public
* @return bool
*/
public function checkImgPath()
{
// try current theme first
if (is_dir($this->getPath() . '/img/')) {
$this->setImgPath($this->getPath() . '/img/');
return true;
}
// try fallback theme
$fallback = $GLOBALS['cfg']['ThemePath'] . '/'
. PMA_Theme_Manager::FALLBACK_THEME
. '/img/';
if (is_dir($fallback)) {
$this->setImgPath($fallback);
return true;
}
// we failed
trigger_error(
sprintf(
__('No valid image path for theme %s found!'),
$this->getName()
),
E_USER_ERROR
);
return false;
}
/**
* returns path to theme
*
* @access public
* @return string path to theme
*/
public function getPath()
{
return $this->path;
}
/**
* returns layout file
*
* @access public
* @return string layout file
*/
public function getLayoutFile()
{
return $this->getPath() . '/layout.inc.php';
}
/**
* set path to theme
*
* @param string $path path to theme
*
* @return void
* @access public
*/
public function setPath($path)
{
$this->path = trim($path);
}
/**
* sets version
*
* @param string $version version to set
*
* @return void
* @access public
*/
public function setVersion($version)
{
$this->version = trim($version);
}
/**
* returns version
*
* @return string version
* @access public
*/
public function getVersion()
{
return $this->version;
}
/**
* checks theme version agaisnt $version
* returns true if theme version is equal or higher to $version
*
* @param string $version version to compare to
*
* @return boolean true if theme version is equal or higher to $version
* @access public
*/
public function checkVersion($version)
{
return version_compare($this->getVersion(), $version, 'lt');
}
/**
* sets name
*
* @param string $name name to set
*
* @return void
* @access public
*/
public function setName($name)
{
$this->name = trim($name);
}
/**
* returns name
*
* @access public
* @return string name
*/
public function getName()
{
return $this->name;
}
/**
* sets id
*
* @param string $id new id
*
* @return void
* @access public
*/
public function setId($id)
{
$this->id = trim($id);
}
/**
* returns id
*
* @return string id
* @access public
*/
public function getId()
{
return $this->id;
}
/**
* Sets path to images for the theme
*
* @param string $path path to images for this theme
*
* @return void
* @access public
*/
public function setImgPath($path)
{
$this->img_path = $path;
}
/**
* Returns the path to image for the theme.
* If filename is given, it possibly fallbacks to fallback
* theme for it if image does not exist.
*
* @param string $file file name for image
*
* @access public
* @return string image path for this theme
*/
public function getImgPath($file = null)
{
if (is_null($file)) {
return $this->img_path;
} else {
if (is_readable($this->img_path . $file)) {
return $this->img_path . $file;
} else {
return $GLOBALS['cfg']['ThemePath'] . '/'
. PMA_Theme_Manager::FALLBACK_THEME . '/img/' . $file;
}
}
}
/**
* load css (send to stdout, normally the browser)
*
* @return bool
* @access public
*/
public function loadCss()
{
$success = true;
if ($GLOBALS['text_dir'] === 'ltr') {
$right = 'right';
$left = 'left';
} else {
$right = 'left';
$left = 'right';
}
foreach ($this->_cssFiles as $file) {
$path = $this->getPath() . "/css/$file.css.php";
$fallback = "./themes/"
. PMA_Theme_Manager::FALLBACK_THEME . "/css/$file.css.php";
if (is_readable($path)) {
echo "\n/* FILE: $file.css.php */\n";
include $path;
} else if (is_readable($fallback)) {
echo "\n/* FILE: $file.css.php */\n";
include $fallback;
} else {
$success = false;
}
}
include './themes/sprites.css.php';
return $success;
}
/**
* Renders the preview for this theme
*
* @return string
* @access public
*/
public function getPrintPreview()
{
$url_params = array('set_theme' => $this->getId());
$url = 'index.php'. PMA_URL_getCommon($url_params);
$retval = '<div class="theme_preview">';
$retval .= '<h2>';
$retval .= htmlspecialchars($this->getName());
$retval .= ' (' . htmlspecialchars($this->getVersion()) . ') ';
$retval .= '</h2>';
$retval .= '<p>';
$retval .= '<a class="take_theme" ';
$retval .= 'name="' . htmlspecialchars($this->getId()) . '" ';
$retval .= 'href="' . $url . '">';
if (@file_exists($this->getPath() . '/screen.png')) {
// if screen exists then output
$retval .= '<img src="' . $this->getPath() . '/screen.png" border="1"';
$retval .= ' alt="' . htmlspecialchars($this->getName()) . '"';
$retval .= ' title="' . htmlspecialchars($this->getName()) . '" />';
$retval .= '<br />';
} else {
$retval .= __('No preview available.');
}
$retval .= '[ <strong>' . __('take it') . '</strong> ]';
$retval .= '</a>';
$retval .= '</p>';
$retval .= '</div>';
return $retval;
}
/**
* Remove filter for IE.
*
* @return string CSS code.
*/
function getCssIEClearFilter()
{
return PMA_USR_BROWSER_AGENT == 'IE'
&& PMA_USR_BROWSER_VER >= 6
&& PMA_USR_BROWSER_VER <= 8
? 'filter: none'
: '';
}
/**
* Gets currently configured font size.
*
* @return String with font size.
*/
function getFontSize()
{
$fs = $GLOBALS['PMA_Config']->get('fontsize');
if (!is_null($fs)) {
return $fs;
}
if (isset($_COOKIE['pma_fontsize'])) {
return $_COOKIE['pma_fontsize'];
}
return '82%';
}
/**
* Generates code for CSS gradient using various browser extensions.
*
* @param string $start_color Color of gradient start, hex value without #
* @param string $end_color Color of gradient end, hex value without #
*
* @return string CSS code.
*/
function getCssGradient($start_color, $end_color)
{
$result = array();
// Opera 9.5+, IE 9
$result[] = 'background-image: url(./themes/svg_gradient.php?from='
. $start_color . '&to=' . $end_color . ');';
$result[] = 'background-size: 100% 100%;';
// Safari 4-5, Chrome 1-9
$result[] = 'background: '
. '-webkit-gradient(linear, left top, left bottom, from(#'
. $start_color . '), to(#' . $end_color . '));';
// Safari 5.1, Chrome 10+
$result[] = 'background: -webkit-linear-gradient(top, #'
. $start_color . ', #' . $end_color . ');';
// Firefox 3.6+
$result[] = 'background: -moz-linear-gradient(top, #'
. $start_color . ', #' . $end_color . ');';
// IE 10
$result[] = 'background: -ms-linear-gradient(top, #'
. $start_color . ', #' . $end_color . ');';
// Opera 11.10
$result[] = 'background: -o-linear-gradient(top, #'
. $start_color . ', #' . $end_color . ');';
// IE 6-8
if (PMA_USR_BROWSER_AGENT == 'IE'
&& PMA_USR_BROWSER_VER >= 6
&& PMA_USR_BROWSER_VER <= 8
) {
$result[] = 'filter: '
. 'progid:DXImageTransform.Microsoft.gradient(startColorstr="#'
. $start_color . '", endColorstr="#' . $end_color . '");';
}
return implode("\n", $result);
}
}
?>
| {'content_hash': 'b7fbe18b63f1e6d35f77301f614e8bbc', 'timestamp': '', 'source': 'github', 'line_count': 485, 'max_line_length': 83, 'avg_line_length': 24.35463917525773, 'alnum_prop': 0.4828140873687775, 'repo_name': 'littlebearz/kitty.go', 'id': 'a6c8a5f6e7bb31e0b79150c4786865cf2ef67873', 'size': '11812', 'binary': False, 'copies': '34', 'ref': 'refs/heads/master', 'path': 'pma/libraries/Theme.class.php', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Batchfile', 'bytes': '5104'}, {'name': 'CSS', 'bytes': '61747'}, {'name': 'Groff', 'bytes': '29'}, {'name': 'HTML', 'bytes': '803848'}, {'name': 'JavaScript', 'bytes': '1967308'}, {'name': 'Makefile', 'bytes': '5575'}, {'name': 'PHP', 'bytes': '6557149'}, {'name': 'Python', 'bytes': '16042'}, {'name': 'Shell', 'bytes': '2292'}]} |
<?php
defined('JPATH_PLATFORM') or die;
/**
* GitHub API Orgs Members class for the Joomla Platform.
*
* @documentation http://developer.github.com/v3/orgs/members/
*
* @since 12.3
*/
class JGithubPackageOrgsMembers extends JGithubPackage
{
/**
* Members list.
*
* List all users who are members of an organization.
* A member is a user that belongs to at least 1 team in the organization.
* If the authenticated user is also a member of this organization then
* both concealed and public members will be returned.
* If the requester is not a member of the organization the query will be
* redirected to the public members list.
*
* @param string $org The name of the organization.
*
* @throws UnexpectedValueException
* @since 3.3 (CMS)
*
* @return boolean|mixed
*/
public function getList($org)
{
// Build the request path.
$path = '/orgs/' . $org . '/members';
$response = $this->client->get($this->fetchUrl($path));
switch ($response->code)
{
case 302 :
// Requester is not an organization member.
return false;
break;
case 200 :
return json_decode($response->body);
break;
default :
throw new UnexpectedValueException('Unexpected response code: ' . $response->code);
break;
}
}
/**
* Check membership.
*
* Check if a user is, publicly or privately, a member of the organization.
*
* @param string $org The name of the organization.
* @param string $user The name of the user.
*
* @throws UnexpectedValueException
* @since 3.3 (CMS)
*
* @return boolean
*/
public function check($org, $user)
{
// Build the request path.
$path = '/orgs/' . $org . '/members/' . $user;
$response = $this->client->get($this->fetchUrl($path));
switch ($response->code)
{
case 204 :
// Requester is an organization member and user is a member.
return true;
break;
case 404 :
// Requester is an organization member and user is not a member.
// Requester is not an organization member and is inquiring about themselves.
return false;
break;
case 302 :
// Requester is not an organization member.
return false;
break;
default :
throw new UnexpectedValueException('Unexpected response code: ' . $response->code);
break;
}
}
/**
* Add a member.
*
* To add someone as a member to an org, you must add them to a team.
*/
/**
* Remove a member.
*
* Removing a user from this list will remove them from all teams and they will no longer have
* any access to the organization’s repositories.
*
* @param string $org The name of the organization.
* @param string $user The name of the user.
*
* @since 3.3 (CMS)
*
* @return object
*/
public function remove($org, $user)
{
// Build the request path.
$path = '/orgs/' . $org . '/members/' . $user;
return $this->processResponse(
$this->client->delete($this->fetchUrl($path)),
204
);
}
/**
* Public members list.
*
* Members of an organization can choose to have their membership publicized or not.
*
* @param string $org The name of the organization.
*
* @since 3.3 (CMS)
*
* @return object
*/
public function getListPublic($org)
{
// Build the request path.
$path = '/orgs/' . $org . '/public_members';
return $this->processResponse(
$this->client->get($this->fetchUrl($path))
);
}
/**
* Check public membership.
*
* @param string $org The name of the organization.
* @param string $user The name of the user.
*
* @throws UnexpectedValueException
* @since 3.3 (CMS)
*
* @return object
*/
public function checkPublic($org, $user)
{
// Build the request path.
$path = '/orgs/' . $org . '/public_members/' . $user;
$response = $this->client->get($this->fetchUrl($path));
switch ($response->code)
{
case 204 :
// Response if user is a public member.
return true;
break;
case 404 :
// Response if user is not a public member.
return false;
break;
default :
throw new UnexpectedValueException('Unexpected response code: ' . $response->code);
break;
}
}
/**
* Publicize a user’s membership.
*
* @param string $org The name of the organization.
* @param string $user The name of the user.
*
* @since 3.3 (CMS)
*
* @return object
*/
public function publicize($org, $user)
{
// Build the request path.
$path = '/orgs/' . $org . '/public_members/' . $user;
return $this->processResponse(
$this->client->put($this->fetchUrl($path), ''),
204
);
}
/**
* Conceal a user’s membership.
*
* @param string $org The name of the organization.
* @param string $user The name of the user.
*
* @since 3.3 (CMS)
*
* @return object
*/
public function conceal($org, $user)
{
// Build the request path.
$path = '/orgs/' . $org . '/public_members/' . $user;
return $this->processResponse(
$this->client->delete($this->fetchUrl($path)),
204
);
}
}
| {'content_hash': '86e70138c1beaa5ab1e1cc929d642980', 'timestamp': '', 'source': 'github', 'line_count': 228, 'max_line_length': 95, 'avg_line_length': 22.214912280701753, 'alnum_prop': 0.6229022704837117, 'repo_name': 'prabirmsp/prabirmsp.github.io', 'id': '3a30658368b5c12e9c177fd3b4bd68046e5e1fd2', 'size': '5300', 'binary': False, 'copies': '333', 'ref': 'refs/heads/cached_mas', 'path': 'ws/joomla/libraries/joomla/github/package/orgs/members.php', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '1553905'}, {'name': 'HTML', 'bytes': '40776'}, {'name': 'JavaScript', 'bytes': '1592025'}, {'name': 'PHP', 'bytes': '11122154'}, {'name': 'PLpgSQL', 'bytes': '1088252'}]} |
<?php
use Illuminate\Database\Schema\Blueprint;
use Illuminate\Database\Migrations\Migration;
class CreateTiposIdentificationTable extends Migration
{
/**
* Run the migrations.
*
* @return void
*/
public function up()
{
Schema::create('tipos_identificacion', function (Blueprint $table) {
$table->increments('id_tipo_identificacion');
$table->string('nombre', 200);
$table->string('descripcion', 400);
$table->timestamps();
});
}
/**
* Reverse the migrations.
*
* @return void
*/
public function down()
{
Schema::drop('tipos_identificacion');
}
}
| {'content_hash': '83b73fbd903b836e08cbfff2f427536f', 'timestamp': '', 'source': 'github', 'line_count': 32, 'max_line_length': 76, 'avg_line_length': 21.125, 'alnum_prop': 0.5872781065088757, 'repo_name': 'mementosoftwareco/siup', 'id': 'a27fbeda057e05fd585874e75a09dd8af6c22812', 'size': '676', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'database/migrations/2017_05_31_015711_create_tipos_identification_table.php', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '72'}, {'name': 'HTML', 'bytes': '234348'}, {'name': 'JavaScript', 'bytes': '503'}, {'name': 'PHP', 'bytes': '202338'}]} |
require 'carrierwave/processing/mini_magick'
class PhotoUploader < CarrierWave::Uploader::Base
include CarrierWave::MiniMagick
storage :file
# Override the directory where uploaded files will be stored.
# This is a sensible default for uploaders that are meant to be mounted:
def store_dir
"uploads/#{model.class.to_s.underscore}/#{mounted_as}/#{model.id}"
end
process resize_to_limit: [800, 800]
version :small do
process resize_to_limit: [70, 70]
end
version :index do
process resize_to_fill: [170, 118]
end
version :medium do
process resize_to_limit: [170, 118]
end
version :large do
process resize_to_limit: [270, 270]
end
# Add a white list of extensions which are allowed to be uploaded.
def extension_white_list
%w(jpg jpeg gif png)
end
end | {'content_hash': '90aebe8709a86d65cff19327cb2b6b60', 'timestamp': '', 'source': 'github', 'line_count': 35, 'max_line_length': 74, 'avg_line_length': 23.37142857142857, 'alnum_prop': 0.7017114914425427, 'repo_name': 'TxSSC/SayWhat', 'id': '3cd489bc5ece074b45ca36721786d97eeee58363', 'size': '818', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'app/uploaders/photo_uploader.rb', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '33198'}, {'name': 'HTML', 'bytes': '158280'}, {'name': 'JavaScript', 'bytes': '10319'}, {'name': 'Ruby', 'bytes': '360508'}]} |
#ifndef __NRF52_BITS_H
#define __NRF52_BITS_H
/*lint ++flb "Enter library region" */
/* Peripheral: AAR */
/* Description: Accelerated Address Resolver */
/* Register: AAR_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_NOTRESOLVED event */
#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_RESOLVED event */
#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_END event */
#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
/* Register: AAR_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_NOTRESOLVED event */
#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_RESOLVED event */
#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_END event */
#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Register: AAR_STATUS */
/* Description: Resolution status */
/* Bits 3..0 : The IRK that was used last time an address was resolved */
#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
/* Register: AAR_ENABLE */
/* Description: Enable AAR */
/* Bits 1..0 : Enable or disable AAR */
#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
/* Register: AAR_NIRK */
/* Description: Number of IRKs */
/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
/* Register: AAR_IRKPTR */
/* Description: Pointer to IRK data structure */
/* Bits 31..0 : Pointer to the IRK data structure */
#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
/* Register: AAR_ADDRPTR */
/* Description: Pointer to the resolvable address */
/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
/* Register: AAR_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
/* Bits 31..0 : Pointer to a "scratch" data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* Peripheral: BPROT */
/* Description: Block Protect */
/* Register: BPROT_CONFIG0 */
/* Description: Block protect configuration register 0 */
/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
/* Register: BPROT_CONFIG1 */
/* Description: Block protect configuration register 1 */
/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
/* Register: BPROT_DISABLEINDEBUG */
/* Description: Disable protection mechanism in debug mode */
/* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
/* Register: BPROT_CONFIG2 */
/* Description: Block protect configuration register 2 */
/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
/* Register: BPROT_CONFIG3 */
/* Description: Block protect configuration register 3 */
/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
/* Peripheral: CCM */
/* Description: AES CCM Mode Encryption */
/* Register: CCM_SHORTS */
/* Description: Shortcut register */
/* Bit 0 : Shortcut between EVENTS_ENDKSGEN event and TASKS_CRYPT task */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
/* Register: CCM_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_ENDCRYPT event */
#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_ENDKSGEN event */
#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
/* Register: CCM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_ENDCRYPT event */
#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_ENDKSGEN event */
#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
/* Register: CCM_MICSTATUS */
/* Description: MIC check result */
/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
/* Register: CCM_ENABLE */
/* Description: Enable */
/* Bits 1..0 : Enable or disable CCM */
#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
/* Register: CCM_MODE */
/* Description: Operation mode */
/* Bit 24 : Packet length configuration */
#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
/* Bit 16 : Data rate that the CCM shall run in synch with */
#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
/* Bit 0 : The mode of operation to be used */
#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
/* Register: CCM_CNFPTR */
/* Description: Pointer to data structure holding AES key and NONCE vector */
/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
/* Register: CCM_INPTR */
/* Description: Input pointer */
/* Bits 31..0 : Input pointer */
#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
/* Register: CCM_OUTPTR */
/* Description: Output pointer */
/* Bits 31..0 : Output pointer */
#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
/* Register: CCM_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
/* Bits 31..0 : Pointer to a "scratch" data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.The scratch area is used for temporary storage of data during key-stream generation and encryption. A space of minimum 43 bytes must be reserved. */
#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* Peripheral: CLOCK */
/* Description: Clock control */
/* Register: CLOCK_INTENSET */
/* Description: Enable interrupt */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_CTTO event */
#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_DONE event */
#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_LFCLKSTARTED event */
#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_HFCLKSTARTED event */
#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
/* Register: CLOCK_INTENCLR */
/* Description: Disable interrupt */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_CTTO event */
#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_DONE event */
#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_LFCLKSTARTED event */
#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_HFCLKSTARTED event */
#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
/* Register: CLOCK_HFCLKRUN */
/* Description: Status indicating that HFCLKSTART task has been triggered */
/* Bit 0 : HFCLKSTART task triggered or not */
#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
/* Register: CLOCK_HFCLKSTAT */
/* Description: Which HFCLK source is running */
/* Bit 16 : HFCLK state */
#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
/* Bit 0 : Active clock source */
#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal oscillator (HFINT) */
#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 32 MHz crystal oscillator (HFXO) */
/* Register: CLOCK_LFCLKRUN */
/* Description: Status indicating that LFCLKSTART task has been triggered */
/* Bit 0 : LFCLKSTART task triggered or not */
#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
/* Register: CLOCK_LFCLKSTAT */
/* Description: Which LFCLK source is running */
/* Bit 16 : LFCLK state */
#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
/* Bits 1..0 : Active clock source */
#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
/* Register: CLOCK_LFCLKSRCCOPY */
/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
/* Bits 1..0 : Clock source */
#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
/* Register: CLOCK_LFCLKSRC */
/* Description: Clock source for the LFCLK */
/* Bits 1..0 : Clock source */
#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
/* Register: CLOCK_CTIV */
/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
/* Register: CLOCK_TRACECONFIG */
/* Description: Clocking options for the Trace Port debug interface */
/* Bits 17..16 : Pin multiplexing of trace signals. */
#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
/* Peripheral: COMP */
/* Description: Comparator */
/* Register: COMP_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between EVENTS_CROSS event and TASKS_STOP task */
#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_UP event and TASKS_STOP task */
#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between EVENTS_DOWN event and TASKS_STOP task */
#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between EVENTS_READY event and TASKS_STOP task */
#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_READY event and TASKS_SAMPLE task */
#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
/* Register: COMP_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 3 : Enable or disable interrupt on EVENTS_CROSS event */
#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_UP event */
#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_DOWN event */
#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_READY event */
#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
/* Register: COMP_INTENSET */
/* Description: Enable interrupt */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_CROSS event */
#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_UP event */
#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_DOWN event */
#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_READY event */
#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: COMP_INTENCLR */
/* Description: Disable interrupt */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_CROSS event */
#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_UP event */
#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_DOWN event */
#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_READY event */
#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: COMP_RESULT */
/* Description: Compare result */
/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */
#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */
/* Register: COMP_ENABLE */
/* Description: COMP enable */
/* Bits 1..0 : Enable or disable COMP */
#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
/* Register: COMP_PSEL */
/* Description: Pin select */
/* Bits 2..0 : Analog pin select */
#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
/* Register: COMP_REFSEL */
/* Description: Reference source select */
/* Bits 2..0 : Reference select */
#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */
#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */
#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */
#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */
/* Register: COMP_EXTREFSEL */
/* Description: External reference select */
/* Bit 0 : External analog reference select */
#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
/* Register: COMP_TH */
/* Description: Threshold configuration for hysteresis unit */
/* Bits 13..8 : VDOWN = (THDOWN+1)/64*VREF */
#define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */
#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
/* Bits 5..0 : VUP = (THUP+1)/64*VREF */
#define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */
#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
/* Register: COMP_MODE */
/* Description: Mode configuration */
/* Bit 8 : Main operation mode */
#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
/* Bits 1..0 : Speed and power mode */
#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
/* Register: COMP_HYST */
/* Description: Comparator hysteresis enable */
/* Bit 0 : Comparator hysteresis */
#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
/* Register: COMP_ISOURCE */
/* Description: Current source select on analog input */
/* Bits 1..0 : Comparator hysteresis */
#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
/* Peripheral: ECB */
/* Description: AES ECB Mode Encryption */
/* Register: ECB_INTENSET */
/* Description: Enable interrupt */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_ERRORECB event */
#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_ENDECB event */
#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
/* Register: ECB_INTENCLR */
/* Description: Disable interrupt */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_ERRORECB event */
#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_ENDECB event */
#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
/* Register: ECB_ECBDATAPTR */
/* Description: ECB block encrypt memory pointers */
/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
/* Peripheral: EGU */
/* Description: Event Generator Unit 0 */
/* Register: EGU_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 15 : Enable or disable interrupt on EVENTS_TRIGGERED[15] event */
#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
/* Bit 14 : Enable or disable interrupt on EVENTS_TRIGGERED[14] event */
#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
/* Bit 13 : Enable or disable interrupt on EVENTS_TRIGGERED[13] event */
#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
/* Bit 12 : Enable or disable interrupt on EVENTS_TRIGGERED[12] event */
#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
/* Bit 11 : Enable or disable interrupt on EVENTS_TRIGGERED[11] event */
#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
/* Bit 10 : Enable or disable interrupt on EVENTS_TRIGGERED[10] event */
#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt on EVENTS_TRIGGERED[9] event */
#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
/* Bit 8 : Enable or disable interrupt on EVENTS_TRIGGERED[8] event */
#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt on EVENTS_TRIGGERED[7] event */
#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt on EVENTS_TRIGGERED[6] event */
#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt on EVENTS_TRIGGERED[5] event */
#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt on EVENTS_TRIGGERED[4] event */
#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt on EVENTS_TRIGGERED[3] event */
#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_TRIGGERED[2] event */
#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_TRIGGERED[1] event */
#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_TRIGGERED[0] event */
#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
/* Register: EGU_INTENSET */
/* Description: Enable interrupt */
/* Bit 15 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[15] event */
#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[14] event */
#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
/* Bit 13 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[13] event */
#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[12] event */
#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
/* Bit 11 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[11] event */
#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[10] event */
#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[9] event */
#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[8] event */
#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[7] event */
#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[6] event */
#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[5] event */
#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[4] event */
#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[3] event */
#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[2] event */
#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[1] event */
#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_TRIGGERED[0] event */
#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
/* Register: EGU_INTENCLR */
/* Description: Disable interrupt */
/* Bit 15 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[15] event */
#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[14] event */
#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
/* Bit 13 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[13] event */
#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[12] event */
#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
/* Bit 11 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[11] event */
#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[10] event */
#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[9] event */
#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[8] event */
#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[7] event */
#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[6] event */
#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[5] event */
#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[4] event */
#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[3] event */
#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[2] event */
#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[1] event */
#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_TRIGGERED[0] event */
#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
/* Peripheral: FICR */
/* Description: Factory Information Configuration Registers */
/* Register: FICR_CODEPAGESIZE */
/* Description: Code memory page size */
/* Bits 31..0 : Code memory page size */
#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
/* Register: FICR_CODESIZE */
/* Description: Code memory size */
/* Bits 31..0 : Code memory size in number of pages */
#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
/* Register: FICR_CONFIGID */
/* Description: Configuration identifier */
/* Bits 31..16 : Deprecated field - Identification number for the FW that is pre-loaded into the chip */
#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
/* Bits 15..0 : Identification number for the HW */
#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
/* Register: FICR_DEVICEID */
/* Description: Description collection[0]: Device identifier */
/* Bits 31..0 : 64 bit unique device identifier */
#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
/* Register: FICR_ER */
/* Description: Description collection[0]: Encryption Root, word 0 */
/* Bits 31..0 : Encryption Root, word n */
#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
/* Register: FICR_IR */
/* Description: Description collection[0]: Identity Root, word 0 */
/* Bits 31..0 : Identity Root, word n */
#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
/* Register: FICR_DEVICEADDRTYPE */
/* Description: Device address type */
/* Bit 0 : Device address type */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
/* Register: FICR_DEVICEADDR */
/* Description: Description collection[0]: Device address 0 */
/* Bits 31..0 : 48 bit device address */
#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
/* Register: FICR_INFO_PART */
/* Description: Part code */
/* Bits 31..0 : Part code */
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
#define FICR_INFO_PART_PART_N52000 (0x52000UL) /*!< nRF52000 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_VARIANT */
/* Description: Part variant */
/* Bits 31..0 : Part variant */
#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C */
#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D */
#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_PACKAGE */
/* Description: Package option */
/* Bits 31..0 : Package option */
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
/* Description: RAM variant */
/* Bits 31..0 : RAM variant */
#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM */
#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM */
#define FICR_INFO_RAM_RAM_K64 (64UL) /*!< 64 kByte RAM */
#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_FLASH */
/* Description: Flash variant */
/* Bits 31..0 : Flash variant */
#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K512 (512UL) /*!< 512 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_NFC_TAGHEADER0 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 3 */
#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
/* Bits 23..16 : Unique identifier byte 2 */
#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
/* Bits 15..8 : Unique identifier byte 1 */
#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
/* Register: FICR_NFC_TAGHEADER1 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 7 */
#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
/* Bits 23..16 : Unique identifier byte 6 */
#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
/* Bits 15..8 : Unique identifier byte 5 */
#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
/* Bits 7..0 : Unique identifier byte 4 */
#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
/* Register: FICR_NFC_TAGHEADER2 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 11 */
#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
/* Bits 23..16 : Unique identifier byte 10 */
#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
/* Bits 15..8 : Unique identifier byte 9 */
#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
/* Bits 7..0 : Unique identifier byte 8 */
#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
/* Register: FICR_NFC_TAGHEADER3 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 15 */
#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
/* Bits 23..16 : Unique identifier byte 14 */
#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
/* Bits 15..8 : Unique identifier byte 13 */
#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
/* Bits 7..0 : Unique identifier byte 12 */
#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
/* Peripheral: GPIOTE */
/* Description: GPIO Tasks and Events */
/* Register: GPIOTE_INTENSET */
/* Description: Enable interrupt */
/* Bit 31 : Write '1' to Enable interrupt on EVENTS_PORT event */
#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_IN[7] event */
#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_IN[6] event */
#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_IN[5] event */
#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_IN[4] event */
#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_IN[3] event */
#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_IN[2] event */
#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_IN[1] event */
#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_IN[0] event */
#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
/* Register: GPIOTE_INTENCLR */
/* Description: Disable interrupt */
/* Bit 31 : Write '1' to Clear interrupt on EVENTS_PORT event */
#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_IN[7] event */
#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_IN[6] event */
#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_IN[5] event */
#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_IN[4] event */
#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_IN[3] event */
#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_IN[2] event */
#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_IN[1] event */
#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_IN[0] event */
#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
/* Register: GPIOTE_CONFIG */
/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
/* Bits 1..0 : Mode */
#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
/* Peripheral: I2S */
/* Description: Inter-IC Sound */
/* Register: I2S_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 5 : Enable or disable interrupt on EVENTS_TXPTRUPD event */
#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_STOPPED event */
#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_RXPTRUPD event */
#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
/* Register: I2S_INTENSET */
/* Description: Enable interrupt */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_TXPTRUPD event */
#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_RXPTRUPD event */
#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
/* Register: I2S_INTENCLR */
/* Description: Disable interrupt */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_TXPTRUPD event */
#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_RXPTRUPD event */
#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
/* Register: I2S_ENABLE */
/* Description: Enable I<sup>2</sup>S module. */
/* Bit 0 : Enable I<sup>2</sup>S module. */
#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define I2S_ENABLE_ENABLE_DISABLE (0UL) /*!< Disabl */
#define I2S_ENABLE_ENABLE_ENABLE (1UL) /*!< Enable */
/* Register: I2S_CONFIG_MODE */
/* Description: I<sup>2</sup>S mode. */
/* Bit 0 : I<sup>2</sup>S mode. */
#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define I2S_CONFIG_MODE_MODE_MASTER (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
#define I2S_CONFIG_MODE_MODE_SLAVE (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
/* Register: I2S_CONFIG_RXEN */
/* Description: Reception (RX) enable. */
/* Bit 0 : Reception (RX) enable. */
#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
#define I2S_CONFIG_RXEN_RXEN_DISABLE (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
#define I2S_CONFIG_RXEN_RXEN_ENABLE (1UL) /*!< Reception enabled. */
/* Register: I2S_CONFIG_TXEN */
/* Description: Transmission (TX) enable. */
/* Bit 0 : Transmission (TX) enable. */
#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
#define I2S_CONFIG_TXEN_TXEN_DISABLE (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
#define I2S_CONFIG_TXEN_TXEN_ENABLE (1UL) /*!< Transmission enabled. */
/* Register: I2S_CONFIG_MCKEN */
/* Description: Master clock generator enable. */
/* Bit 0 : Master clock generator enable. */
#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
/* Register: I2S_CONFIG_MCKFREQ */
/* Description: Master clock generator frequency. */
/* Bits 31..0 : Master clock generator frequency. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08200000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
/* Register: I2S_CONFIG_RATIO */
/* Description: MCK / LRCK ratio. */
/* Bits 3..0 : MCK / LRCK ratio. */
#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96x */
#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
/* Register: I2S_CONFIG_SWIDTH */
/* Description: Sample width. */
/* Bits 1..0 : Sample width. */
#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT (0UL) /*!< 8 bit. */
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT (1UL) /*!< 16 bit. */
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT (2UL) /*!< 24 bit. */
/* Register: I2S_CONFIG_ALIGN */
/* Description: Alignment of sample within a frame. */
/* Bit 0 : Alignment of sample within a frame. */
#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
#define I2S_CONFIG_ALIGN_ALIGN_LEFT (0UL) /*!< Left-aligned. */
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT (1UL) /*!< Right-aligned. */
/* Register: I2S_CONFIG_FORMAT */
/* Description: Frame format. */
/* Bit 0 : Frame format. */
#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I<sup>2</sup>S format. */
#define I2S_CONFIG_FORMAT_FORMAT_DSP (1UL) /*!< Alternate (DSP) format. */
/* Register: I2S_CONFIG_CHANNELS */
/* Description: Enable channels. */
/* Bits 1..0 : Enable channels. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO (0UL) /*!< Stereo. */
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT (1UL) /*!< Left only. */
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT (2UL) /*!< Right only. */
/* Register: I2S_RXD_PTR */
/* Description: Receive buffer RAM start address. */
/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: I2S_TXD_PTR */
/* Description: Transmit buffer RAM start address. */
/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: I2S_RXTXD_MAXCNT */
/* Description: Size of RXD and TXD buffers. */
/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: I2S_PSEL_MCK */
/* Description: Pin select for MCK signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_SCK */
/* Description: Pin select for SCK signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_LRCK */
/* Description: Pin select for LRCK signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_SDIN */
/* Description: Pin select for SDIN signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: I2S_PSEL_SDOUT */
/* Description: Pin select for SDOUT signal. */
/* Bit 31 : Connection */
#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
/* Peripheral: LPCOMP */
/* Description: Low Power Comparator */
/* Register: LPCOMP_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between EVENTS_CROSS event and TASKS_STOP task */
#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_UP event and TASKS_STOP task */
#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between EVENTS_DOWN event and TASKS_STOP task */
#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between EVENTS_READY event and TASKS_STOP task */
#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_READY event and TASKS_SAMPLE task */
#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
/* Register: LPCOMP_INTENSET */
/* Description: Enable interrupt */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_CROSS event */
#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_UP event */
#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_DOWN event */
#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_READY event */
#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: LPCOMP_INTENCLR */
/* Description: Disable interrupt */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_CROSS event */
#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_UP event */
#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_DOWN event */
#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_READY event */
#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: LPCOMP_RESULT */
/* Description: Compare result */
/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */
#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */
/* Register: LPCOMP_ENABLE */
/* Description: Enable LPCOMP */
/* Bits 1..0 : Enable or disable LPCOMP */
#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: LPCOMP_PSEL */
/* Description: Input pin select */
/* Bits 2..0 : Analog pin select */
#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
/* Register: LPCOMP_REFSEL */
/* Description: Reference select */
/* Bits 3..0 : Reference select */
#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
/* Register: LPCOMP_EXTREFSEL */
/* Description: External reference select */
/* Bit 0 : External analog reference select */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
/* Register: LPCOMP_ANADETECT */
/* Description: Analog detect configuration */
/* Bits 1..0 : Analog detect configuration */
#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
/* Register: LPCOMP_HYST */
/* Description: Comparator hysteresis enable */
/* Bit 0 : Comparator hysteresis enable */
#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
/* Peripheral: MWU */
/* Description: Memory Watch Unit */
/* Register: MWU_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 27 : Enable or disable interrupt on EVENTS_PREGION[1].RA event */
#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 26 : Enable or disable interrupt on EVENTS_PREGION[1].WA event */
#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 25 : Enable or disable interrupt on EVENTS_PREGION[0].RA event */
#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 24 : Enable or disable interrupt on EVENTS_PREGION[0].WA event */
#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt on EVENTS_REGION[3].RA event */
#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt on EVENTS_REGION[3].WA event */
#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt on EVENTS_REGION[2].RA event */
#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt on EVENTS_REGION[2].WA event */
#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt on EVENTS_REGION[1].RA event */
#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_REGION[1].WA event */
#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_REGION[0].RA event */
#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_REGION[0].WA event */
#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
/* Register: MWU_INTENSET */
/* Description: Enable interrupt */
/* Bit 27 : Write '1' to Enable interrupt on EVENTS_PREGION[1].RA event */
#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
/* Bit 26 : Write '1' to Enable interrupt on EVENTS_PREGION[1].WA event */
#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
/* Bit 25 : Write '1' to Enable interrupt on EVENTS_PREGION[0].RA event */
#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
/* Bit 24 : Write '1' to Enable interrupt on EVENTS_PREGION[0].WA event */
#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_REGION[3].RA event */
#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_REGION[3].WA event */
#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_REGION[2].RA event */
#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_REGION[2].WA event */
#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_REGION[1].RA event */
#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_REGION[1].WA event */
#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_REGION[0].RA event */
#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_REGION[0].WA event */
#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
/* Register: MWU_INTENCLR */
/* Description: Disable interrupt */
/* Bit 27 : Write '1' to Clear interrupt on EVENTS_PREGION[1].RA event */
#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
/* Bit 26 : Write '1' to Clear interrupt on EVENTS_PREGION[1].WA event */
#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
/* Bit 25 : Write '1' to Clear interrupt on EVENTS_PREGION[0].RA event */
#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
/* Bit 24 : Write '1' to Clear interrupt on EVENTS_PREGION[0].WA event */
#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_REGION[3].RA event */
#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_REGION[3].WA event */
#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_REGION[2].RA event */
#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_REGION[2].WA event */
#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_REGION[1].RA event */
#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_REGION[1].WA event */
#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_REGION[0].RA event */
#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_REGION[0].WA event */
#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
/* Register: MWU_NMIEN */
/* Description: Enable or disable non-maskable interrupt */
/* Bit 27 : Enable or disable non-maskable interrupt on EVENTS_PREGION[1].RA event */
#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 26 : Enable or disable non-maskable interrupt on EVENTS_PREGION[1].WA event */
#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 25 : Enable or disable non-maskable interrupt on EVENTS_PREGION[0].RA event */
#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 24 : Enable or disable non-maskable interrupt on EVENTS_PREGION[0].WA event */
#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable non-maskable interrupt on EVENTS_REGION[3].RA event */
#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable non-maskable interrupt on EVENTS_REGION[3].WA event */
#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable non-maskable interrupt on EVENTS_REGION[2].RA event */
#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable non-maskable interrupt on EVENTS_REGION[2].WA event */
#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable non-maskable interrupt on EVENTS_REGION[1].RA event */
#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable non-maskable interrupt on EVENTS_REGION[1].WA event */
#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable non-maskable interrupt on EVENTS_REGION[0].RA event */
#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable non-maskable interrupt on EVENTS_REGION[0].WA event */
#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
/* Register: MWU_NMIENSET */
/* Description: Enable non-maskable interrupt */
/* Bit 27 : Write '1' to Enable non-maskable interrupt on EVENTS_PREGION[1].RA event */
#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
/* Bit 26 : Write '1' to Enable non-maskable interrupt on EVENTS_PREGION[1].WA event */
#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
/* Bit 25 : Write '1' to Enable non-maskable interrupt on EVENTS_PREGION[0].RA event */
#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
/* Bit 24 : Write '1' to Enable non-maskable interrupt on EVENTS_PREGION[0].WA event */
#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[3].RA event */
#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[3].WA event */
#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[2].RA event */
#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[2].WA event */
#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[1].RA event */
#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[1].WA event */
#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[0].RA event */
#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable non-maskable interrupt on EVENTS_REGION[0].WA event */
#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
/* Register: MWU_NMIENCLR */
/* Description: Disable non-maskable interrupt */
/* Bit 27 : Write '1' to Clear non-maskable interrupt on EVENTS_PREGION[1].RA event */
#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
/* Bit 26 : Write '1' to Clear non-maskable interrupt on EVENTS_PREGION[1].WA event */
#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
/* Bit 25 : Write '1' to Clear non-maskable interrupt on EVENTS_PREGION[0].RA event */
#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
/* Bit 24 : Write '1' to Clear non-maskable interrupt on EVENTS_PREGION[0].WA event */
#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[3].RA event */
#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[3].WA event */
#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[2].RA event */
#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[2].WA event */
#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[1].RA event */
#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[1].WA event */
#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[0].RA event */
#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear non-maskable interrupt on EVENTS_REGION[0].WA event */
#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
/* Register: MWU_PERREGION_SUBSTATWA */
/* Description: Description cluster[0]: Source of interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
/* Bit 31 : Sub region 31 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 30 : Sub region 30 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 29 : Sub region 29 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 28 : Sub region 28 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 27 : Sub region 27 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 26 : Sub region 26 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 25 : Sub region 25 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 24 : Sub region 24 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 23 : Sub region 23 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 22 : Sub region 22 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 21 : Sub region 21 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 20 : Sub region 20 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 19 : Sub region 19 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 18 : Sub region 18 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 17 : Sub region 17 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 16 : Sub region 16 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 15 : Sub region 15 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 14 : Sub region 14 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 13 : Sub region 13 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 12 : Sub region 12 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 11 : Sub region 11 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 10 : Sub region 10 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 9 : Sub region 9 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 8 : Sub region 8 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 7 : Sub region 7 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 6 : Sub region 6 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 5 : Sub region 5 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 4 : Sub region 4 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 3 : Sub region 3 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 2 : Sub region 2 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 1 : Sub region 1 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Bit 0 : Sub region 0 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Register: MWU_PERREGION_SUBSTATRA */
/* Description: Description cluster[0]: Source of interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
/* Bit 31 : Sub region 31 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 30 : Sub region 30 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 29 : Sub region 29 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 28 : Sub region 28 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 27 : Sub region 27 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 26 : Sub region 26 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 25 : Sub region 25 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 24 : Sub region 24 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 23 : Sub region 23 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 22 : Sub region 22 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 21 : Sub region 21 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 20 : Sub region 20 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 19 : Sub region 19 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 18 : Sub region 18 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 17 : Sub region 17 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 16 : Sub region 16 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 15 : Sub region 15 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 14 : Sub region 14 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 13 : Sub region 13 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 12 : Sub region 12 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 11 : Sub region 11 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 10 : Sub region 10 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 9 : Sub region 9 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 8 : Sub region 8 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 7 : Sub region 7 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 6 : Sub region 6 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 5 : Sub region 5 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 4 : Sub region 4 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 3 : Sub region 3 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 2 : Sub region 2 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 1 : Sub region 1 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Bit 0 : Sub region 0 in region 0 (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
/* Register: MWU_REGIONEN */
/* Description: Enable/disable regions watch */
/* Bit 27 : Enable/disable read access watch in PREGION[1] */
#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 26 : Enable/disable write access watch in PREGION[1] */
#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 25 : Enable/disable read access watch in PREGION[0] */
#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 24 : Enable/disable write access watch in PREGION[0] */
#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 7 : Enable/disable read access watch in region[3] */
#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 6 : Enable/disable write access watch in region[3] */
#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Bit 5 : Enable/disable read access watch in region[2] */
#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 4 : Enable/disable write access watch in region[2] */
#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Bit 3 : Enable/disable read access watch in region[1] */
#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 2 : Enable/disable write access watch in region[1] */
#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Bit 1 : Enable/disable read access watch in region[0] */
#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
/* Bit 0 : Enable/disable write access watch in region[0] */
#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
/* Register: MWU_REGIONENSET */
/* Description: Enable regions watch */
/* Bit 27 : Enable read access watch in PREGION[1] */
#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 26 : Enable write access watch in PREGION[1] */
#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 25 : Enable read access watch in PREGION[0] */
#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
/* Bit 24 : Enable write access watch in PREGION[0] */
#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
/* Bit 7 : Enable read access watch in region[3] */
#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 6 : Enable write access watch in region[3] */
#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
/* Bit 5 : Enable read access watch in region[2] */
#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 4 : Enable write access watch in region[2] */
#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
/* Bit 3 : Enable read access watch in region[1] */
#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 2 : Enable write access watch in region[1] */
#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
/* Bit 1 : Enable read access watch in region[0] */
#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
/* Bit 0 : Enable write access watch in region[0] */
#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
/* Register: MWU_REGIONENCLR */
/* Description: Disable regions watch */
/* Bit 27 : Disable read access watch in PREGION[1] */
#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
/* Bit 26 : Disable write access watch in PREGION[1] */
#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
/* Bit 25 : Disable read access watch in PREGION[0] */
#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
/* Bit 24 : Disable write access watch in PREGION[0] */
#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
/* Bit 7 : Disable read access watch in region[3] */
#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 6 : Disable write access watch in region[3] */
#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Bit 5 : Disable read access watch in region[2] */
#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 4 : Disable write access watch in region[2] */
#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Bit 3 : Disable read access watch in region[1] */
#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 2 : Disable write access watch in region[1] */
#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Bit 1 : Disable read access watch in region[0] */
#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
/* Bit 0 : Disable write access watch in region[0] */
#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Register: MWU_REGION_START */
/* Description: Description cluster[0]: Start address for region 0 */
/* Bits 31..0 : Start address for region */
#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
/* Register: MWU_REGION_END */
/* Description: Description cluster[0]: End address of region 0 */
/* Bits 31..0 : End address of region. Value 0 has a special meaning, see below. */
#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
#define MWU_REGION_END_END_OneByte (0UL) /*!< Region is 1 byte long (End address = Start address) */
/* Register: MWU_PREGION_START */
/* Description: Description cluster[0]: Reserved for future use */
/* Bits 31..0 : Reserved for future use */
#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
/* Register: MWU_PREGION_END */
/* Description: Description cluster[0]: Reserved for future use */
/* Bits 31..0 : Reserved for future use */
#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
/* Register: MWU_PREGION_SUBS */
/* Description: Description cluster[0]: Sub regions of region 0 */
/* Bit 31 : Include or exclude subregion 31 in region */
#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
/* Bit 30 : Include or exclude subregion 30 in region */
#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
/* Bit 29 : Include or exclude subregion 29 in region */
#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
/* Bit 28 : Include or exclude subregion 28 in region */
#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
/* Bit 27 : Include or exclude subregion 27 in region */
#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
/* Bit 26 : Include or exclude subregion 26 in region */
#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
/* Bit 25 : Include or exclude subregion 25 in region */
#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
/* Bit 24 : Include or exclude subregion 24 in region */
#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
/* Bit 23 : Include or exclude subregion 23 in region */
#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
/* Bit 22 : Include or exclude subregion 22 in region */
#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
/* Bit 21 : Include or exclude subregion 21 in region */
#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
/* Bit 20 : Include or exclude subregion 20 in region */
#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
/* Bit 19 : Include or exclude subregion 19 in region */
#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
/* Bit 18 : Include or exclude subregion 18 in region */
#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
/* Bit 17 : Include or exclude subregion 17 in region */
#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
/* Bit 16 : Include or exclude subregion 16 in region */
#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
/* Bit 15 : Include or exclude subregion 15 in region */
#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
/* Bit 14 : Include or exclude subregion 14 in region */
#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
/* Bit 13 : Include or exclude subregion 13 in region */
#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
/* Bit 12 : Include or exclude subregion 12 in region */
#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
/* Bit 11 : Include or exclude subregion 11 in region */
#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
/* Bit 10 : Include or exclude subregion 10 in region */
#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
/* Bit 9 : Include or exclude subregion 9 in region */
#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
/* Bit 8 : Include or exclude subregion 8 in region */
#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
/* Bit 7 : Include or exclude subregion 7 in region */
#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
/* Bit 6 : Include or exclude subregion 6 in region */
#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
/* Bit 5 : Include or exclude subregion 5 in region */
#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
/* Bit 4 : Include or exclude subregion 4 in region */
#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
/* Bit 3 : Include or exclude subregion 3 in region */
#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
/* Bit 2 : Include or exclude subregion 2 in region */
#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
/* Bit 1 : Include or exclude subregion 1 in region */
#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
/* Bit 0 : Include or exclude subregion 0 in region */
#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
/* Peripheral: NFCT */
/* Description: NFC-A compatible radio */
/* Register: NFCT_SHORTS */
/* Description: Shortcut register */
/* Bit 1 : Shortcut between EVENTS_FIELDLOST event and TASKS_SENSE task */
#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_FIELDDETECTED event and TASKS_ACTIVATE task */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
/* Register: NFCT_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 20 : Enable or disable interrupt on EVENTS_STARTED event */
#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt on EVENTS_SELECTED event */
#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable interrupt on EVENTS_COLLISION event */
#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
/* Bit 14 : Enable or disable interrupt on EVENTS_AUTOCOLRESSTARTED event */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 12 : Enable or disable interrupt on EVENTS_ENDTX event */
#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
/* Bit 11 : Enable or disable interrupt on EVENTS_ENDRX event */
#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
/* Bit 10 : Enable or disable interrupt on EVENTS_RXERROR event */
#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt on EVENTS_ERROR event */
#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt on EVENTS_RXFRAMEEND event */
#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt on EVENTS_RXFRAMESTART event */
#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt on EVENTS_TXFRAMEEND event */
#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt on EVENTS_TXFRAMESTART event */
#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_FIELDLOST event */
#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_FIELDDETECTED event */
#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_READY event */
#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
/* Register: NFCT_INTENSET */
/* Description: Enable interrupt */
/* Bit 20 : Write '1' to Enable interrupt on EVENTS_STARTED event */
#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_SELECTED event */
#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt on EVENTS_COLLISION event */
#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt on EVENTS_AUTOCOLRESSTARTED event */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt on EVENTS_ENDTX event */
#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
/* Bit 11 : Write '1' to Enable interrupt on EVENTS_ENDRX event */
#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt on EVENTS_RXERROR event */
#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_RXFRAMEEND event */
#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_RXFRAMESTART event */
#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_TXFRAMEEND event */
#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_TXFRAMESTART event */
#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_FIELDLOST event */
#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_FIELDDETECTED event */
#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_READY event */
#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: NFCT_INTENCLR */
/* Description: Disable interrupt */
/* Bit 20 : Write '1' to Clear interrupt on EVENTS_STARTED event */
#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_SELECTED event */
#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Clear interrupt on EVENTS_COLLISION event */
#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Clear interrupt on EVENTS_AUTOCOLRESSTARTED event */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Clear interrupt on EVENTS_ENDTX event */
#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
/* Bit 11 : Write '1' to Clear interrupt on EVENTS_ENDRX event */
#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Clear interrupt on EVENTS_RXERROR event */
#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_RXFRAMEEND event */
#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_RXFRAMESTART event */
#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_TXFRAMEEND event */
#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_TXFRAMESTART event */
#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_FIELDLOST event */
#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_FIELDDETECTED event */
#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_READY event */
#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: NFCT_ERRORSTATUS */
/* Description: NFC Error Status register */
/* Bit 6 : No valid End of Frame detected */
#define NFCT_ERRORSTATUS_EOFERROR_Pos (6UL) /*!< Position of EOFERROR field. */
#define NFCT_ERRORSTATUS_EOFERROR_Msk (0x1UL << NFCT_ERRORSTATUS_EOFERROR_Pos) /*!< Bit mask of EOFERROR field. */
/* Bit 3 : Field level is too low at min load resistance */
#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
/* Bit 2 : Field level is too high at max load resistance */
#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
/* Bit 1 : The received pulse does not match a valid NFC-A symbol */
#define NFCT_ERRORSTATUS_INVALIDNFCSYMBOL_Pos (1UL) /*!< Position of INVALIDNFCSYMBOL field. */
#define NFCT_ERRORSTATUS_INVALIDNFCSYMBOL_Msk (0x1UL << NFCT_ERRORSTATUS_INVALIDNFCSYMBOL_Pos) /*!< Bit mask of INVALIDNFCSYMBOL field. */
/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
/* Register: NFCT_FRAMESTATUS_RX */
/* Description: Result of last incoming frames */
/* Bit 3 : Overrun detected */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
/* Bit 2 : Parity status of received frame */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
/* Bit 0 : No valid End of Frame detected */
#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
/* Register: NFCT_CURRENTLOADCTRL */
/* Description: Current value driven to the NFC Load Control */
/* Bits 5..0 : Current value driven to the NFC Load Control */
#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
/* Register: NFCT_FIELDPRESENT */
/* Description: Indicates the presence or not of a valid field */
/* Bit 1 : Indicates if the low level has locked to the field */
#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
/* Bit 0 : Indicates the presence or not of a valid field. Linked to the FIELDDETECTED and FIELDLOST events. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
/* Register: NFCT_FRAMEDELAYMIN */
/* Description: Minimum frame delay */
/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
/* Register: NFCT_FRAMEDELAYMAX */
/* Description: Maximum frame delay */
/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
/* Register: NFCT_FRAMEDELAYMODE */
/* Description: Configuration register for the Frame Delay Timer */
/* Bits 1..0 : Configuration register for the Frame Delay Timer */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
/* Register: NFCT_PACKETPTR */
/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: NFCT_MAXLEN */
/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
/* Register: NFCT_TXD_FRAMECONFIG */
/* Description: Configuration of outgoing frames */
/* Bit 4 : CRC mode for outgoing frames */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
/* Bit 2 : Adding SoF or not in TX frames */
#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
/* Bit 1 : Discarding unused bits in start or at end of a Frame */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
/* Bit 0 : Adding parity or not in the frame */
#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
/* Register: NFCT_TXD_AMOUNT */
/* Description: Size of outgoing frame */
/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). The DISCARDMODE field in FRAMECONFIG.TX selects if unused bits is discarded at the start or at the end of a frame. A value of 0 bytes and 0 bits is invalid. */
#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
/* Register: NFCT_RXD_FRAMECONFIG */
/* Description: Configuration of incoming frames */
/* Bit 4 : CRC mode for incoming frames */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
/* Bit 2 : SoF expected or not in RX frames */
#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
/* Bit 0 : Parity expected or not in RX frame */
#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
/* Register: NFCT_RXD_AMOUNT */
/* Description: Size of last incoming frame */
/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing) */
#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
/* Register: NFCT_NFCID1_LAST */
/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
/* Bits 31..24 : NFCID1 byte W */
#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
/* Bits 23..16 : NFCID1 byte X */
#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
/* Bits 15..8 : NFCID1 byte Y */
#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
/* Register: NFCT_NFCID1_2ND_LAST */
/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
/* Bits 23..16 : NFCID1 byte T */
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
/* Bits 15..8 : NFCID1 byte U */
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
/* Bits 7..0 : NFCID1 byte V */
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
/* Register: NFCT_NFCID1_3RD_LAST */
/* Description: Third last NFCID1 part (10 bytes ID) */
/* Bits 23..16 : NFCID1 byte Q */
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
/* Bits 15..8 : NFCID1 byte R */
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
/* Bits 7..0 : NFCID1 byte S */
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
/* Register: NFCT_AUTOCOLRESCONFIG */
/* Description: Controls the Auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */
/* Bit 1 : Enables/disables Auto collision resolution short frame (any frames less than 7 bits) noise filter */
#define NFCT_AUTOCOLRESCONFIG_FILTER_Pos (1UL) /*!< Position of FILTER field. */
#define NFCT_AUTOCOLRESCONFIG_FILTER_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_FILTER_Pos) /*!< Bit mask of FILTER field. */
#define NFCT_AUTOCOLRESCONFIG_FILTER_Off (0UL) /*!< Auto collision resolution short frame noise filter disabled */
#define NFCT_AUTOCOLRESCONFIG_FILTER_On (1UL) /*!< Auto collision resolution ignores any frames less than 7 bits */
/* Bit 0 : Enables/disables Auto collision resolution */
#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
/* Register: NFCT_SENSRES */
/* Description: NFC-A SENS_RES auto-response settings */
/* Bits 15..12 : Reserved for future use. Shall be 0. */
#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
/* Bit 5 : Reserved for future use. Shall be 0. */
#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
/* Register: NFCT_SELRES */
/* Description: NFC-A SEL_RES auto-response settings */
/* Bit 7 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
/* Bits 4..3 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
/* Bits 1..0 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
/* Peripheral: NVMC */
/* Description: Non Volatile Memory Controller */
/* Register: NVMC_READY */
/* Description: Ready flag */
/* Bit 0 : NVMC is ready or busy */
#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
/* Register: NVMC_CONFIG */
/* Description: Configuration register */
/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
/* Register: NVMC_ERASEPAGE */
/* Description: Register for erasing a page in Code area */
/* Bits 31..0 : Register for starting erase of a page in Code area */
#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
/* Register: NVMC_ERASEPCR1 */
/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
/* Register: NVMC_ERASEALL */
/* Description: Register for erasing all non-volatile user memory */
/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
/* Register: NVMC_ERASEPCR0 */
/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
/* Register: NVMC_ERASEUICR */
/* Description: Register for erasing User Information Configuration Registers */
/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
/* Register: NVMC_ICACHECNF */
/* Description: I-Code cache configuration register. */
/* Bit 8 : Cache profiling enable */
#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
/* Bit 0 : Cache enable */
#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
/* Register: NVMC_IHIT */
/* Description: I-Code cache hit counter. */
/* Bits 31..0 : Number of cache hits */
#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
/* Register: NVMC_IMISS */
/* Description: I-Code cache miss counter. */
/* Bits 31..0 : Number of cache misses */
#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
/* Peripheral: GPIO */
/* Description: GPIO Port 1 */
/* Register: GPIO_OUT */
/* Description: Write GPIO port */
/* Bit 31 : P0.31 pin */
#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
/* Bit 30 : P0.30 pin */
#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
/* Bit 29 : P0.29 pin */
#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
/* Bit 28 : P0.28 pin */
#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
/* Bit 27 : P0.27 pin */
#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
/* Bit 26 : P0.26 pin */
#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
/* Bit 25 : P0.25 pin */
#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
/* Bit 24 : P0.24 pin */
#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
/* Bit 23 : P0.23 pin */
#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
/* Bit 22 : P0.22 pin */
#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
/* Bit 21 : P0.21 pin */
#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
/* Bit 20 : P0.20 pin */
#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
/* Bit 19 : P0.19 pin */
#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
/* Bit 18 : P0.18 pin */
#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
/* Bit 17 : P0.17 pin */
#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
/* Bit 16 : P0.16 pin */
#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
/* Bit 15 : P0.15 pin */
#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
/* Bit 14 : P0.14 pin */
#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
/* Bit 13 : P0.13 pin */
#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
/* Bit 12 : P0.12 pin */
#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
/* Bit 11 : P0.11 pin */
#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
/* Bit 10 : P0.10 pin */
#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
/* Bit 9 : P0.9 pin */
#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
/* Bit 8 : P0.8 pin */
#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
/* Bit 7 : P0.7 pin */
#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
/* Bit 6 : P0.6 pin */
#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
/* Bit 5 : P0.5 pin */
#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
/* Bit 4 : P0.4 pin */
#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
/* Bit 3 : P0.3 pin */
#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
/* Bit 2 : P0.2 pin */
#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
/* Bit 1 : P0.1 pin */
#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
/* Bit 0 : P0.0 pin */
#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
/* Register: GPIO_OUTSET */
/* Description: Set individual bits in GPIO port */
/* Bit 31 : P0.31 pin */
#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 30 : P0.30 pin */
#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 29 : P0.29 pin */
#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 28 : P0.28 pin */
#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 27 : P0.27 pin */
#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 26 : P0.26 pin */
#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 25 : P0.25 pin */
#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 24 : P0.24 pin */
#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 23 : P0.23 pin */
#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 22 : P0.22 pin */
#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 21 : P0.21 pin */
#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 20 : P0.20 pin */
#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 19 : P0.19 pin */
#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 18 : P0.18 pin */
#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 17 : P0.17 pin */
#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 16 : P0.16 pin */
#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 15 : P0.15 pin */
#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 14 : P0.14 pin */
#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 13 : P0.13 pin */
#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 12 : P0.12 pin */
#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 11 : P0.11 pin */
#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 10 : P0.10 pin */
#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 9 : P0.9 pin */
#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 8 : P0.8 pin */
#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 7 : P0.7 pin */
#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 6 : P0.6 pin */
#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 5 : P0.5 pin */
#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 4 : P0.4 pin */
#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 3 : P0.3 pin */
#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 2 : P0.2 pin */
#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 1 : P0.1 pin */
#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Bit 0 : P0.0 pin */
#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
/* Register: GPIO_OUTCLR */
/* Description: Clear individual bits in GPIO port */
/* Bit 31 : P0.31 pin */
#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 30 : P0.30 pin */
#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 29 : P0.29 pin */
#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 28 : P0.28 pin */
#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 27 : P0.27 pin */
#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 26 : P0.26 pin */
#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 25 : P0.25 pin */
#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 24 : P0.24 pin */
#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 23 : P0.23 pin */
#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 22 : P0.22 pin */
#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 21 : P0.21 pin */
#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 20 : P0.20 pin */
#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 19 : P0.19 pin */
#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 18 : P0.18 pin */
#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 17 : P0.17 pin */
#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 16 : P0.16 pin */
#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 15 : P0.15 pin */
#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 14 : P0.14 pin */
#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 13 : P0.13 pin */
#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 12 : P0.12 pin */
#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 11 : P0.11 pin */
#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 10 : P0.10 pin */
#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 9 : P0.9 pin */
#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 8 : P0.8 pin */
#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 7 : P0.7 pin */
#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 6 : P0.6 pin */
#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 5 : P0.5 pin */
#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 4 : P0.4 pin */
#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 3 : P0.3 pin */
#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 2 : P0.2 pin */
#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 1 : P0.1 pin */
#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Bit 0 : P0.0 pin */
#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
/* Register: GPIO_IN */
/* Description: Read GPIO port */
/* Bit 31 : P0.31 pin */
#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
/* Bit 30 : P0.30 pin */
#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
/* Bit 29 : P0.29 pin */
#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
/* Bit 28 : P0.28 pin */
#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
/* Bit 27 : P0.27 pin */
#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
/* Bit 26 : P0.26 pin */
#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
/* Bit 25 : P0.25 pin */
#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
/* Bit 24 : P0.24 pin */
#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
/* Bit 23 : P0.23 pin */
#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
/* Bit 22 : P0.22 pin */
#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
/* Bit 21 : P0.21 pin */
#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
/* Bit 20 : P0.20 pin */
#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
/* Bit 19 : P0.19 pin */
#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
/* Bit 18 : P0.18 pin */
#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
/* Bit 17 : P0.17 pin */
#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
/* Bit 16 : P0.16 pin */
#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
/* Bit 15 : P0.15 pin */
#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
/* Bit 14 : P0.14 pin */
#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
/* Bit 13 : P0.13 pin */
#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
/* Bit 12 : P0.12 pin */
#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
/* Bit 11 : P0.11 pin */
#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
/* Bit 10 : P0.10 pin */
#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
/* Bit 9 : P0.9 pin */
#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
/* Bit 8 : P0.8 pin */
#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
/* Bit 7 : P0.7 pin */
#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
/* Bit 6 : P0.6 pin */
#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
/* Bit 5 : P0.5 pin */
#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
/* Bit 4 : P0.4 pin */
#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
/* Bit 3 : P0.3 pin */
#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
/* Bit 2 : P0.2 pin */
#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
/* Bit 1 : P0.1 pin */
#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
/* Bit 0 : P0.0 pin */
#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
/* Register: GPIO_DIR */
/* Description: Direction of GPIO pins */
/* Bit 31 : P0.31 pin */
#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
/* Bit 30 : P0.30 pin */
#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
/* Bit 29 : P0.29 pin */
#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
/* Bit 28 : P0.28 pin */
#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
/* Bit 27 : P0.27 pin */
#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
/* Bit 26 : P0.26 pin */
#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
/* Bit 25 : P0.25 pin */
#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
/* Bit 24 : P0.24 pin */
#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
/* Bit 23 : P0.23 pin */
#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
/* Bit 22 : P0.22 pin */
#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
/* Bit 21 : P0.21 pin */
#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
/* Bit 20 : P0.20 pin */
#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
/* Bit 19 : P0.19 pin */
#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
/* Bit 18 : P0.18 pin */
#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
/* Bit 17 : P0.17 pin */
#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
/* Bit 16 : P0.16 pin */
#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
/* Bit 15 : P0.15 pin */
#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
/* Bit 14 : P0.14 pin */
#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
/* Bit 13 : P0.13 pin */
#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
/* Bit 12 : P0.12 pin */
#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
/* Bit 11 : P0.11 pin */
#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
/* Bit 10 : P0.10 pin */
#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
/* Bit 9 : P0.9 pin */
#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
/* Bit 8 : P0.8 pin */
#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
/* Bit 7 : P0.7 pin */
#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
/* Bit 6 : P0.6 pin */
#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
/* Bit 5 : P0.5 pin */
#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
/* Bit 4 : P0.4 pin */
#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
/* Bit 3 : P0.3 pin */
#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
/* Bit 2 : P0.2 pin */
#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
/* Bit 1 : P0.1 pin */
#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
/* Bit 0 : P0.0 pin */
#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
/* Register: GPIO_DIRSET */
/* Description: DIR set register */
/* Bit 31 : Set as output pin 31 */
#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 30 : Set as output pin 30 */
#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 29 : Set as output pin 29 */
#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 28 : Set as output pin 28 */
#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 27 : Set as output pin 27 */
#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 26 : Set as output pin 26 */
#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 25 : Set as output pin 25 */
#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 24 : Set as output pin 24 */
#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 23 : Set as output pin 23 */
#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 22 : Set as output pin 22 */
#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 21 : Set as output pin 21 */
#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 20 : Set as output pin 20 */
#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 19 : Set as output pin 19 */
#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 18 : Set as output pin 18 */
#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 17 : Set as output pin 17 */
#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 16 : Set as output pin 16 */
#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 15 : Set as output pin 15 */
#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 14 : Set as output pin 14 */
#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 13 : Set as output pin 13 */
#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 12 : Set as output pin 12 */
#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 11 : Set as output pin 11 */
#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 10 : Set as output pin 10 */
#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 9 : Set as output pin 9 */
#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 8 : Set as output pin 8 */
#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 7 : Set as output pin 7 */
#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 6 : Set as output pin 6 */
#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 5 : Set as output pin 5 */
#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 4 : Set as output pin 4 */
#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 3 : Set as output pin 3 */
#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 2 : Set as output pin 2 */
#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 1 : Set as output pin 1 */
#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Bit 0 : Set as output pin 0 */
#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
/* Register: GPIO_DIRCLR */
/* Description: DIR clear register */
/* Bit 31 : Set as input pin 31 */
#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 30 : Set as input pin 30 */
#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 29 : Set as input pin 29 */
#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 28 : Set as input pin 28 */
#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 27 : Set as input pin 27 */
#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 26 : Set as input pin 26 */
#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 25 : Set as input pin 25 */
#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 24 : Set as input pin 24 */
#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 23 : Set as input pin 23 */
#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 22 : Set as input pin 22 */
#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 21 : Set as input pin 21 */
#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 20 : Set as input pin 20 */
#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 19 : Set as input pin 19 */
#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 18 : Set as input pin 18 */
#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 17 : Set as input pin 17 */
#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 16 : Set as input pin 16 */
#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 15 : Set as input pin 15 */
#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 14 : Set as input pin 14 */
#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 13 : Set as input pin 13 */
#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 12 : Set as input pin 12 */
#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 11 : Set as input pin 11 */
#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 10 : Set as input pin 10 */
#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 9 : Set as input pin 9 */
#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 8 : Set as input pin 8 */
#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 7 : Set as input pin 7 */
#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 6 : Set as input pin 6 */
#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 5 : Set as input pin 5 */
#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 4 : Set as input pin 4 */
#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 3 : Set as input pin 3 */
#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 2 : Set as input pin 2 */
#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 1 : Set as input pin 1 */
#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Bit 0 : Set as input pin 0 */
#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
/* Register: GPIO_LATCH */
/* Description: Latch indicating which GPIO pins have met the criteria set in PIN_CNF[n].SENSE register */
/* Bits 31..0 : Register holding a '1' for each GPIO pins which has met the criteria set in PIN_CNF[n].SENSE */
#define GPIO_LATCH_LATCH_Pos (0UL) /*!< Position of LATCH field. */
#define GPIO_LATCH_LATCH_Msk (0xFFFFFFFFUL << GPIO_LATCH_LATCH_Pos) /*!< Bit mask of LATCH field. */
/* Register: GPIO_DETECTMODE */
/* Description: Select between default DETECT signal behaviour and LDETECT mode */
/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< Use default behaviour */
#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use LDETECT behaviour */
/* Register: GPIO_PIN_CNF */
/* Description: Description collection[0]: Configuration of GPIO pins */
/* Bits 17..16 : Pin sensing mechanism */
#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
/* Bits 10..8 : Drive configuration */
#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' */
#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' */
#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' */
#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' */
/* Bits 3..2 : Pull configuration */
#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
/* Bit 1 : Connect or disconnect input buffer */
#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
/* Bit 0 : Pin direction */
#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
/* Peripheral: PDM */
/* Description: Pulse Density Modulation (Digital Microphone) Interface */
/* Register: PDM_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 2 : Enable or disable interrupt on EVENTS_END event */
#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_STOPPED event */
#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_STARTED event */
#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
/* Register: PDM_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_END event */
#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_STARTED event */
#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Register: PDM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_END event */
#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_STARTED event */
#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Register: PDM_ENABLE */
/* Description: PDM module enable register */
/* Bit 0 : Enable or disable PDM reception */
#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: PDM_PDMCLKCTRL */
/* Description: PDM clock generator control */
/* Bits 31..0 : PDM_CLK frequency */
#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 1.000 MHz */
#define PDM_PDMCLKCTRL_FREQ_1024K (0x08400000UL) /*!< PDM_CLK = 1.024 MHz */
#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 1.067 MHz */
/* Register: PDM_MODE */
/* Description: Defines the routing of the connected PDM microphones' signals */
/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
/* Bit 0 : Mono or stereo operation */
#define PDM_MODE_MONO_Pos (0UL) /*!< Position of MONO field. */
#define PDM_MODE_MONO_Msk (0x1UL << PDM_MODE_MONO_Pos) /*!< Bit mask of MONO field. */
#define PDM_MODE_MONO_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
#define PDM_MODE_MONO_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
/* Register: PDM_GAINL */
/* Description: Left output gain adjustment */
/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the requirement that 0dB gain adjustment corresponds to 2500 RMS output samples (16-bit) with 1 kHz 90dBA signal into a -26dBFS sensitivity PDM microphone. 0x00 -20 dB gain 0x01 -19.5 dB gain (...) 0x27 -0.5 dB gain 0x28 0 dB gain 0x29 +0.5 dB gain (...) 0x4F +19.5 dB gain 0x50 +20 dB gain */
#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
/* Register: PDM_GAINR */
/* Description: Right output gain adjustment */
/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the requirement that 0dB gain adjustment corresponds to 2500 RMS output samples (16-bit) with 1 kHz 90dBA signal into a -26dBFS sensitivity PDM microphone. (same encoding as GAINL) */
#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
/* Register: PDM_PSEL_CLK */
/* Description: Pin number configuration for PDM CLK signal */
/* Bit 31 : Connection */
#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: PDM_PSEL_DIN */
/* Description: Pin number configuration for PDM DIN signal */
/* Bit 31 : Connection */
#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: PDM_SAMPLE_PTR */
/* Description: RAM address pointer to write samples to with EasyDMA */
/* Bits 31..0 : Address to write PDM samples to over DMA */
#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
/* Register: PDM_SAMPLE_MAXCNT */
/* Description: Number of samples to allocate memory for in EasyDMA mode */
/* Bits 14..0 : Length of DMA RAM allocation in number of samples. Number of RAM word allocated depends on MODE.CHANNELS. */
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
/* Peripheral: POWER */
/* Description: Power control */
/* Register: POWER_INTENSET */
/* Description: Enable interrupt */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_SLEEPEXIT event */
#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_SLEEPENTER event */
#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_POFWARN event */
#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
/* Register: POWER_INTENCLR */
/* Description: Disable interrupt */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_SLEEPEXIT event */
#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_SLEEPENTER event */
#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_POFWARN event */
#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
/* Register: POWER_RESETREAS */
/* Description: Reset reason */
/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
/* Bit 3 : Reset from CPU lock-up detected */
#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected */
#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
/* Bit 1 : Reset from watchdog detected */
#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
/* Bit 0 : Reset from pin-reset detected */
#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
/* Register: POWER_RAMSTATUS */
/* Description: Deprecated register - RAM status register */
/* Bit 3 : RAM block 3 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
/* Bit 2 : RAM block 2 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
/* Bit 1 : RAM block 1 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
/* Bit 0 : RAM block 0 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
/* Register: POWER_SYSTEMOFF */
/* Description: System OFF register */
/* Bit 0 : Enable System OFF mode */
#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
/* Register: POWER_POFCON */
/* Description: Power failure comparator configuration */
/* Bits 4..1 : Power failure comparator threshold setting */
#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
/* Bit 0 : Enable or disable power failure comparator */
#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
/* Register: POWER_GPREGRET */
/* Description: General purpose retention register */
/* Bits 7..0 : General purpose retention register */
#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
/* Register: POWER_GPREGRET2 */
/* Description: General purpose retention register */
/* Bits 7..0 : General purpose retention register */
#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
/* Register: POWER_RAMON */
/* Description: Deprecated register - RAM on/off register (this register is retained) */
/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
/* Register: POWER_RAMONB */
/* Description: Deprecated register - RAM on/off register (this register is retained) */
/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
/* Register: POWER_DCDCEN */
/* Description: DC/DC enable register */
/* Bit 0 : Enable or disable DC/DC converter */
#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
/* Register: POWER_RAM_POWER */
/* Description: Description cluster[0]: RAM0 power control register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
/* Bit 1 : Keep RAM section S1 of RAMm on or off in System ON mode */
#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
/* Bit 0 : Keep RAM section S0 of RAMm on or off in System ON mode */
#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
/* Register: POWER_RAM_POWERSET */
/* Description: Description cluster[0]: RAM0 power control set register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
/* Bit 1 : Keep RAM section S1 of RAMm on or off in System ON mode */
#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
/* Bit 0 : Keep RAM section S0 of RAMm on or off in System ON mode */
#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
/* Register: POWER_RAM_POWERCLR */
/* Description: Description cluster[0]: RAM0 power control clear register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
/* Bit 1 : Keep RAM section S1 of RAMm on or off in System ON mode */
#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
/* Bit 0 : Keep RAM section S0 of RAMm on or off in System ON mode */
#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
/* Peripheral: PPI */
/* Description: Programmable Peripheral Interconnect */
/* Register: PPI_CHEN */
/* Description: Channel enable register */
/* Bit 31 : Enable or disable channel 31 */
#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
/* Bit 30 : Enable or disable channel 30 */
#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
/* Bit 29 : Enable or disable channel 29 */
#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
/* Bit 28 : Enable or disable channel 28 */
#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
/* Bit 27 : Enable or disable channel 27 */
#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
/* Bit 26 : Enable or disable channel 26 */
#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
/* Bit 25 : Enable or disable channel 25 */
#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
/* Bit 24 : Enable or disable channel 24 */
#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
/* Bit 23 : Enable or disable channel 23 */
#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
/* Bit 22 : Enable or disable channel 22 */
#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
/* Bit 21 : Enable or disable channel 21 */
#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
/* Bit 20 : Enable or disable channel 20 */
#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
/* Bit 19 : Enable or disable channel 19 */
#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
/* Bit 18 : Enable or disable channel 18 */
#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
/* Bit 17 : Enable or disable channel 17 */
#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
/* Bit 16 : Enable or disable channel 16 */
#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
/* Bit 15 : Enable or disable channel 15 */
#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
/* Bit 14 : Enable or disable channel 14 */
#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
/* Bit 13 : Enable or disable channel 13 */
#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
/* Bit 12 : Enable or disable channel 12 */
#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
/* Bit 11 : Enable or disable channel 11 */
#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
/* Bit 10 : Enable or disable channel 10 */
#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
/* Bit 9 : Enable or disable channel 9 */
#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
/* Bit 8 : Enable or disable channel 8 */
#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
/* Bit 7 : Enable or disable channel 7 */
#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
/* Bit 6 : Enable or disable channel 6 */
#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
/* Bit 5 : Enable or disable channel 5 */
#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
/* Bit 4 : Enable or disable channel 4 */
#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
/* Bit 3 : Enable or disable channel 3 */
#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
/* Bit 2 : Enable or disable channel 2 */
#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
/* Bit 1 : Enable or disable channel 1 */
#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
/* Bit 0 : Enable or disable channel 0 */
#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
/* Register: PPI_CHENSET */
/* Description: Channel enable set register */
/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
/* Register: PPI_CHENCLR */
/* Description: Channel enable clear register */
/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
/* Register: PPI_CH_EEP */
/* Description: Description cluster[0]: Channel 0 event end-point */
/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
/* Register: PPI_CH_TEP */
/* Description: Description cluster[0]: Channel 0 task end-point */
/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
/* Register: PPI_CHG */
/* Description: Description collection[0]: Channel group 0 */
/* Bit 31 : Include or exclude channel 31 */
#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH31_Included (1UL) /*!< Include */
/* Bit 30 : Include or exclude channel 30 */
#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH30_Included (1UL) /*!< Include */
/* Bit 29 : Include or exclude channel 29 */
#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH29_Included (1UL) /*!< Include */
/* Bit 28 : Include or exclude channel 28 */
#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH28_Included (1UL) /*!< Include */
/* Bit 27 : Include or exclude channel 27 */
#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH27_Included (1UL) /*!< Include */
/* Bit 26 : Include or exclude channel 26 */
#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH26_Included (1UL) /*!< Include */
/* Bit 25 : Include or exclude channel 25 */
#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH25_Included (1UL) /*!< Include */
/* Bit 24 : Include or exclude channel 24 */
#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH24_Included (1UL) /*!< Include */
/* Bit 23 : Include or exclude channel 23 */
#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH23_Included (1UL) /*!< Include */
/* Bit 22 : Include or exclude channel 22 */
#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH22_Included (1UL) /*!< Include */
/* Bit 21 : Include or exclude channel 21 */
#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH21_Included (1UL) /*!< Include */
/* Bit 20 : Include or exclude channel 20 */
#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH20_Included (1UL) /*!< Include */
/* Bit 19 : Include or exclude channel 19 */
#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH19_Included (1UL) /*!< Include */
/* Bit 18 : Include or exclude channel 18 */
#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH18_Included (1UL) /*!< Include */
/* Bit 17 : Include or exclude channel 17 */
#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH17_Included (1UL) /*!< Include */
/* Bit 16 : Include or exclude channel 16 */
#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH16_Included (1UL) /*!< Include */
/* Bit 15 : Include or exclude channel 15 */
#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH15_Included (1UL) /*!< Include */
/* Bit 14 : Include or exclude channel 14 */
#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH14_Included (1UL) /*!< Include */
/* Bit 13 : Include or exclude channel 13 */
#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH13_Included (1UL) /*!< Include */
/* Bit 12 : Include or exclude channel 12 */
#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH12_Included (1UL) /*!< Include */
/* Bit 11 : Include or exclude channel 11 */
#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH11_Included (1UL) /*!< Include */
/* Bit 10 : Include or exclude channel 10 */
#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH10_Included (1UL) /*!< Include */
/* Bit 9 : Include or exclude channel 9 */
#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH9_Included (1UL) /*!< Include */
/* Bit 8 : Include or exclude channel 8 */
#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH8_Included (1UL) /*!< Include */
/* Bit 7 : Include or exclude channel 7 */
#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH7_Included (1UL) /*!< Include */
/* Bit 6 : Include or exclude channel 6 */
#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH6_Included (1UL) /*!< Include */
/* Bit 5 : Include or exclude channel 5 */
#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH5_Included (1UL) /*!< Include */
/* Bit 4 : Include or exclude channel 4 */
#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH4_Included (1UL) /*!< Include */
/* Bit 3 : Include or exclude channel 3 */
#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH3_Included (1UL) /*!< Include */
/* Bit 2 : Include or exclude channel 2 */
#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH2_Included (1UL) /*!< Include */
/* Bit 1 : Include or exclude channel 1 */
#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH1_Included (1UL) /*!< Include */
/* Bit 0 : Include or exclude channel 0 */
#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
#define PPI_CHG_CH0_Included (1UL) /*!< Include */
/* Register: PPI_FORK_TEP */
/* Description: Description cluster[0]: Channel 0 task end-point */
/* Bits 31..0 : Pointer to task register */
#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
/* Peripheral: PWM */
/* Description: Pulse Width Modulation Unit 0 */
/* Register: PWM_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between EVENTS_LOOPSDONE event and TASKS_STOP task */
#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_LOOPSDONE event and TASKS_SEQSTART[1] task */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between EVENTS_LOOPSDONE event and TASKS_SEQSTART[0] task */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between EVENTS_SEQEND[1] event and TASKS_STOP task */
#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_SEQEND[0] event and TASKS_STOP task */
#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Register: PWM_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 7 : Enable or disable interrupt on EVENTS_LOOPSDONE event */
#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt on EVENTS_PWMPERIODEND event */
#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt on EVENTS_SEQEND[1] event */
#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt on EVENTS_SEQEND[0] event */
#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt on EVENTS_SEQSTARTED[1] event */
#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_SEQSTARTED[0] event */
#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_STOPPED event */
#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Register: PWM_INTENSET */
/* Description: Enable interrupt */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_LOOPSDONE event */
#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_PWMPERIODEND event */
#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_SEQEND[1] event */
#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_SEQEND[0] event */
#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_SEQSTARTED[1] event */
#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_SEQSTARTED[0] event */
#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: PWM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_LOOPSDONE event */
#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_PWMPERIODEND event */
#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_SEQEND[1] event */
#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_SEQEND[0] event */
#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_SEQSTARTED[1] event */
#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_SEQSTARTED[0] event */
#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: PWM_ENABLE */
/* Description: PWM module enable register */
/* Bit 0 : Enable or disable PWM module */
#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: PWM_MODE */
/* Description: Selects operating mode of the wave counter */
/* Bit 0 : Selects up or up and down as wave counter mode */
#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
/* Register: PWM_COUNTERTOP */
/* Description: Value up to which the pulse generator counter counts */
/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
/* Register: PWM_PRESCALER */
/* Description: Configuration for PWM_CLK */
/* Bits 2..0 : Pre-scaler of PWM_CLK */
#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */
#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */
#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
/* Register: PWM_DECODER */
/* Description: Configuration of the decoder */
/* Bit 8 : Selects source for advancing the active sequence */
#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
/* Register: PWM_LOOP */
/* Description: Amount of playback of a loop */
/* Bits 15..0 : Amount of playback of pattern cycles */
#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
/* Register: PWM_SEQ_PTR */
/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */
/* Bits 31..0 : Beginning address in Data RAM of sequence A */
#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: PWM_SEQ_CNT */
/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */
/* Bits 14..0 : Amount of values (duty cycles) in sequence A */
#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled */
/* Register: PWM_SEQ_REFRESH */
/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
/* Register: PWM_SEQ_ENDDELAY */
/* Description: Description cluster[0]: Time added after the sequence */
/* Bits 23..0 : Time added after the sequence in PWM periods */
#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
/* Register: PWM_PSEL_OUT */
/* Description: Description collection[0]: Output pin select for PWM channel 0 */
/* Bit 31 : Connection */
#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
/* Peripheral: QDEC */
/* Description: Quadrature Decoder */
/* Register: QDEC_SHORTS */
/* Description: Shortcut register */
/* Bit 6 : Shortcut between EVENTS_SAMPLERDY event and TASKS_READCLRACC task */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between EVENTS_DBLRDY event and TASKS_STOP task */
#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 4 : Shortcut between EVENTS_DBLRDY event and TASKS_RDCLRDBL task */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_REPORTRDY event and TASKS_STOP task */
#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between EVENTS_REPORTRDY event and TASKS_RDCLRACC task */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between EVENTS_SAMPLERDY event and TASKS_STOP task */
#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_REPORTRDY event and TASKS_READCLRACC task */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
/* Register: QDEC_INTENSET */
/* Description: Enable interrupt */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_DBLRDY event */
#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_ACCOF event */
#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_REPORTRDY event */
#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_SAMPLERDY event */
#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
/* Register: QDEC_INTENCLR */
/* Description: Disable interrupt */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_DBLRDY event */
#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_ACCOF event */
#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_REPORTRDY event */
#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_SAMPLERDY event */
#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
/* Register: QDEC_ENABLE */
/* Description: Enable the quadrature decoder */
/* Bit 0 : Enable or disable the quadrature decoder */
#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
/* Register: QDEC_LEDPOL */
/* Description: LED output pin polarity */
/* Bit 0 : LED output pin polarity */
#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
/* Register: QDEC_SAMPLEPER */
/* Description: Sample period */
/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
/* Register: QDEC_SAMPLE */
/* Description: Motion sample value */
/* Bits 31..0 : Last motion sample */
#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
/* Register: QDEC_REPORTPER */
/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
/* Register: QDEC_ACC */
/* Description: Register accumulating the valid transitions */
/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
/* Register: QDEC_ACCREAD */
/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
/* Bits 31..0 : Snapshot of the ACC register. */
#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
/* Register: QDEC_PSEL_LED */
/* Description: Pin select for LED signal */
/* Bit 31 : Connection */
#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: QDEC_PSEL_A */
/* Description: Pin select for A signal */
/* Bit 31 : Connection */
#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: QDEC_PSEL_B */
/* Description: Pin select for B signal */
/* Bit 31 : Connection */
#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: QDEC_DBFEN */
/* Description: Enable input debounce filters */
/* Bit 0 : Enable input debounce filters */
#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
/* Register: QDEC_LEDPRE */
/* Description: Time period the LED is switched ON prior to sampling */
/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
/* Register: QDEC_ACCDBL */
/* Description: Register accumulating the number of detected double transitions */
/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
/* Register: QDEC_ACCDBLREAD */
/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
/* Peripheral: RADIO */
/* Description: 2.4 GHz Radio */
/* Register: RADIO_SHORTS */
/* Description: Shortcut register */
/* Bit 8 : Shortcut between EVENTS_DISABLED event and TASKS_RSSISTOP task */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 6 : Shortcut between EVENTS_ADDRESS event and TASKS_BCSTART task */
#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between EVENTS_END event and TASKS_START task */
#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
/* Bit 4 : Shortcut between EVENTS_ADDRESS event and TASKS_RSSISTART task */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_DISABLED event and TASKS_RXEN task */
#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between EVENTS_DISABLED event and TASKS_TXEN task */
#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between EVENTS_END event and TASKS_DISABLE task */
#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_READY event and TASKS_START task */
#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
/* Register: RADIO_INTENSET */
/* Description: Enable interrupt */
/* Bit 13 : Write '1' to Enable interrupt on EVENTS_CRCERROR event */
#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt on EVENTS_CRCOK event */
#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt on EVENTS_BCMATCH event */
#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_RSSIEND event */
#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_DEVMISS event */
#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_DEVMATCH event */
#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_DISABLED event */
#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_END event */
#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_PAYLOAD event */
#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_ADDRESS event */
#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_READY event */
#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: RADIO_INTENCLR */
/* Description: Disable interrupt */
/* Bit 13 : Write '1' to Clear interrupt on EVENTS_CRCERROR event */
#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Clear interrupt on EVENTS_CRCOK event */
#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Clear interrupt on EVENTS_BCMATCH event */
#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_RSSIEND event */
#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_DEVMISS event */
#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_DEVMATCH event */
#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_DISABLED event */
#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_END event */
#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_PAYLOAD event */
#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_ADDRESS event */
#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_READY event */
#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: RADIO_CRCSTATUS */
/* Description: CRC status */
/* Bit 0 : CRC status of packet received */
#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
/* Register: RADIO_RXMATCH */
/* Description: Received address */
/* Bits 2..0 : Received address */
#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
/* Register: RADIO_RXCRC */
/* Description: CRC field of previously received packet */
/* Bits 23..0 : CRC field of previously received packet */
#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
/* Register: RADIO_DAI */
/* Description: Device address match index */
/* Bits 2..0 : Device address match index */
#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
/* Register: RADIO_PACKETPTR */
/* Description: Packet pointer */
/* Bits 31..0 : Packet pointer */
#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
/* Register: RADIO_FREQUENCY */
/* Description: Frequency */
/* Bits 6..0 : Radio channel frequency */
#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
/* Register: RADIO_TXPOWER */
/* Description: Output power */
/* Bits 7..0 : RADIO output power. */
#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
/* Register: RADIO_MODE */
/* Description: Data rate and modulation */
/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
/* Register: RADIO_PCNF0 */
/* Description: Packet configuration register 0 */
/* Bit 24 : Length of preamble on air. Decision point: "RADIO.TASKS_START" task */
#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
/* Bit 20 : Include or exclude S1 field in RAM */
#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */
#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
/* Bits 19..16 : Length on air of S1 field in number of bits. */
#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
/* Bit 8 : Length on air of S0 field in number of bytes. */
#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
/* Register: RADIO_PCNF1 */
/* Description: Packet configuration register 1 */
/* Bit 25 : Enable or disable packet whitening */
#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
/* Bits 18..16 : Base address length in number of bytes */
#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
/* Bits 15..8 : Static length in number of bytes */
#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
/* Register: RADIO_BASE0 */
/* Description: Base address 0 */
/* Bits 31..0 : Base address 0 */
#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
/* Register: RADIO_BASE1 */
/* Description: Base address 1 */
/* Bits 31..0 : Base address 1 */
#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
/* Register: RADIO_PREFIX0 */
/* Description: Prefixes bytes for logical addresses 0-3 */
/* Bits 31..24 : Address prefix 3. */
#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
/* Bits 23..16 : Address prefix 2. */
#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
/* Bits 15..8 : Address prefix 1. */
#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
/* Bits 7..0 : Address prefix 0. */
#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
/* Register: RADIO_PREFIX1 */
/* Description: Prefixes bytes for logical addresses 4-7 */
/* Bits 31..24 : Address prefix 7. */
#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
/* Bits 23..16 : Address prefix 6. */
#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
/* Bits 15..8 : Address prefix 5. */
#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
/* Bits 7..0 : Address prefix 4. */
#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
/* Register: RADIO_TXADDRESS */
/* Description: Transmit address select */
/* Bits 2..0 : Transmit address select */
#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
/* Register: RADIO_RXADDRESSES */
/* Description: Receive address select */
/* Bit 7 : Enable or disable reception on logical address 7. */
#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable reception on logical address 6. */
#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable reception on logical address 5. */
#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable reception on logical address 4. */
#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable reception on logical address 3. */
#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable reception on logical address 2. */
#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable reception on logical address 1. */
#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable reception on logical address 0. */
#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
/* Register: RADIO_CRCCNF */
/* Description: CRC configuration */
/* Bit 8 : Include or exclude packet address field out of CRC calculation. */
#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
/* Bits 1..0 : CRC length in number of bytes. */
#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
/* Register: RADIO_CRCPOLY */
/* Description: CRC polynomial */
/* Bits 23..0 : CRC polynomial */
#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
/* Register: RADIO_CRCINIT */
/* Description: CRC initial value */
/* Bits 23..0 : CRC initial value */
#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
/* Register: RADIO_TIFS */
/* Description: Inter Frame Spacing in us */
/* Bits 7..0 : Inter Frame Spacing in us */
#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
/* Register: RADIO_RSSISAMPLE */
/* Description: RSSI sample */
/* Bits 6..0 : RSSI sample */
#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
/* Register: RADIO_STATE */
/* Description: Current radio state */
/* Bits 3..0 : Current radio state */
#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
/* Register: RADIO_DATAWHITEIV */
/* Description: Data whitening initial value */
/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
/* Register: RADIO_BCC */
/* Description: Bit counter compare */
/* Bits 31..0 : Bit counter compare */
#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
/* Register: RADIO_DAB */
/* Description: Description collection[0]: Device address base segment 0 */
/* Bits 31..0 : Device address base segment 0 */
#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
/* Register: RADIO_DAP */
/* Description: Description collection[0]: Device address prefix 0 */
/* Bits 15..0 : Device address prefix 0 */
#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
/* Register: RADIO_DACNF */
/* Description: Device address match configuration */
/* Bit 15 : TxAdd for device address 7 */
#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
/* Bit 14 : TxAdd for device address 6 */
#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
/* Bit 13 : TxAdd for device address 5 */
#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
/* Bit 12 : TxAdd for device address 4 */
#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
/* Bit 11 : TxAdd for device address 3 */
#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
/* Bit 10 : TxAdd for device address 2 */
#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
/* Bit 9 : TxAdd for device address 1 */
#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
/* Bit 8 : TxAdd for device address 0 */
#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
/* Bit 7 : Enable or disable device address matching using device address 7 */
#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
/* Bit 6 : Enable or disable device address matching using device address 6 */
#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
/* Bit 5 : Enable or disable device address matching using device address 5 */
#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
/* Bit 4 : Enable or disable device address matching using device address 4 */
#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
/* Bit 3 : Enable or disable device address matching using device address 3 */
#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
/* Bit 2 : Enable or disable device address matching using device address 2 */
#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
/* Bit 1 : Enable or disable device address matching using device address 1 */
#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
/* Bit 0 : Enable or disable device address matching using device address 0 */
#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
/* Register: RADIO_MODECNF0 */
/* Description: Radio mode configuration register 0 */
/* Bits 9..8 : Default TX value */
#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
/* Bit 0 : Radio ramp-up time */
#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time, compatible with nRF51 */
#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up, see product specification for more information */
/* Register: RADIO_POWER */
/* Description: Peripheral power control */
/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
/* Peripheral: RNG */
/* Description: Random Number Generator */
/* Register: RNG_SHORTS */
/* Description: Shortcut register */
/* Bit 0 : Shortcut between EVENTS_VALRDY event and TASKS_STOP task */
#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Register: RNG_INTENSET */
/* Description: Enable interrupt */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_VALRDY event */
#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
/* Register: RNG_INTENCLR */
/* Description: Disable interrupt */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_VALRDY event */
#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
/* Register: RNG_CONFIG */
/* Description: Configuration register */
/* Bit 0 : Bias correction */
#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
/* Register: RNG_VALUE */
/* Description: Output random number */
/* Bits 7..0 : Generated random number */
#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
/* Peripheral: RTC */
/* Description: Real time counter 0 */
/* Register: RTC_INTENSET */
/* Description: Enable interrupt */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_COMPARE[3] event */
#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt on EVENTS_COMPARE[2] event */
#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt on EVENTS_COMPARE[1] event */
#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable interrupt on EVENTS_COMPARE[0] event */
#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_OVRFLW event */
#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_TICK event */
#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
/* Register: RTC_INTENCLR */
/* Description: Disable interrupt */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_COMPARE[3] event */
#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Clear interrupt on EVENTS_COMPARE[2] event */
#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Clear interrupt on EVENTS_COMPARE[1] event */
#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Clear interrupt on EVENTS_COMPARE[0] event */
#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_OVRFLW event */
#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_TICK event */
#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
/* Register: RTC_EVTEN */
/* Description: Enable or disable event routing */
/* Bit 19 : Enable or disable event routing on EVENTS_COMPARE[3] event */
#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable event routing on EVENTS_COMPARE[2] event */
#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable event routing on EVENTS_COMPARE[1] event */
#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
/* Bit 16 : Enable or disable event routing on EVENTS_COMPARE[0] event */
#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable event routing on EVENTS_OVRFLW event */
#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable event routing on EVENTS_TICK event */
#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
/* Register: RTC_EVTENSET */
/* Description: Enable event routing */
/* Bit 19 : Write '1' to Enable event routing on EVENTS_COMPARE[3] event */
#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable event routing on EVENTS_COMPARE[2] event */
#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable event routing on EVENTS_COMPARE[1] event */
#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable event routing on EVENTS_COMPARE[0] event */
#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable event routing on EVENTS_OVRFLW event */
#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable event routing on EVENTS_TICK event */
#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
/* Register: RTC_EVTENCLR */
/* Description: Disable event routing */
/* Bit 19 : Write '1' to Clear event routing on EVENTS_COMPARE[3] event */
#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Clear event routing on EVENTS_COMPARE[2] event */
#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Clear event routing on EVENTS_COMPARE[1] event */
#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Clear event routing on EVENTS_COMPARE[0] event */
#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear event routing on EVENTS_OVRFLW event */
#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear event routing on EVENTS_TICK event */
#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
/* Register: RTC_COUNTER */
/* Description: Current COUNTER value */
/* Bits 23..0 : Counter value */
#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
/* Register: RTC_PRESCALER */
/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
/* Bits 11..0 : Prescaler value */
#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
/* Register: RTC_CC */
/* Description: Description collection[0]: Compare register 0 */
/* Bits 23..0 : Compare value */
#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
/* Peripheral: SAADC */
/* Description: Analog to Digital Converter */
/* Register: SAADC_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 21 : Enable or disable interrupt on EVENTS_CH[7].LIMITL event */
#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt on EVENTS_CH[7].LIMITH event */
#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt on EVENTS_CH[6].LIMITL event */
#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable interrupt on EVENTS_CH[6].LIMITH event */
#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable interrupt on EVENTS_CH[5].LIMITL event */
#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 16 : Enable or disable interrupt on EVENTS_CH[5].LIMITH event */
#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 15 : Enable or disable interrupt on EVENTS_CH[4].LIMITL event */
#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 14 : Enable or disable interrupt on EVENTS_CH[4].LIMITH event */
#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 13 : Enable or disable interrupt on EVENTS_CH[3].LIMITL event */
#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 12 : Enable or disable interrupt on EVENTS_CH[3].LIMITH event */
#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 11 : Enable or disable interrupt on EVENTS_CH[2].LIMITL event */
#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 10 : Enable or disable interrupt on EVENTS_CH[2].LIMITH event */
#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt on EVENTS_CH[1].LIMITL event */
#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 8 : Enable or disable interrupt on EVENTS_CH[1].LIMITH event */
#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 7 : Enable or disable interrupt on EVENTS_CH[0].LIMITL event */
#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
/* Bit 6 : Enable or disable interrupt on EVENTS_CH[0].LIMITH event */
#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
/* Bit 5 : Enable or disable interrupt on EVENTS_STOPPED event */
#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt on EVENTS_CALIBRATEDONE event */
#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
/* Bit 3 : Enable or disable interrupt on EVENTS_RESULTDONE event */
#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
/* Bit 2 : Enable or disable interrupt on EVENTS_DONE event */
#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_END event */
#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_STARTED event */
#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
/* Register: SAADC_INTENSET */
/* Description: Enable interrupt */
/* Bit 21 : Write '1' to Enable interrupt on EVENTS_CH[7].LIMITL event */
#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt on EVENTS_CH[7].LIMITH event */
#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_CH[6].LIMITL event */
#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt on EVENTS_CH[6].LIMITH event */
#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt on EVENTS_CH[5].LIMITL event */
#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable interrupt on EVENTS_CH[5].LIMITH event */
#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
/* Bit 15 : Write '1' to Enable interrupt on EVENTS_CH[4].LIMITL event */
#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt on EVENTS_CH[4].LIMITH event */
#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
/* Bit 13 : Write '1' to Enable interrupt on EVENTS_CH[3].LIMITL event */
#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
/* Bit 12 : Write '1' to Enable interrupt on EVENTS_CH[3].LIMITH event */
#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
/* Bit 11 : Write '1' to Enable interrupt on EVENTS_CH[2].LIMITL event */
#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt on EVENTS_CH[2].LIMITH event */
#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_CH[1].LIMITL event */
#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt on EVENTS_CH[1].LIMITH event */
#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_CH[0].LIMITL event */
#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_CH[0].LIMITH event */
#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
/* Bit 5 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_CALIBRATEDONE event */
#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
/* Bit 3 : Write '1' to Enable interrupt on EVENTS_RESULTDONE event */
#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_DONE event */
#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_END event */
#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_STARTED event */
#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Register: SAADC_INTENCLR */
/* Description: Disable interrupt */
/* Bit 21 : Write '1' to Clear interrupt on EVENTS_CH[7].LIMITL event */
#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Clear interrupt on EVENTS_CH[7].LIMITH event */
#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_CH[6].LIMITL event */
#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Clear interrupt on EVENTS_CH[6].LIMITH event */
#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Clear interrupt on EVENTS_CH[5].LIMITL event */
#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Clear interrupt on EVENTS_CH[5].LIMITH event */
#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
/* Bit 15 : Write '1' to Clear interrupt on EVENTS_CH[4].LIMITL event */
#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Clear interrupt on EVENTS_CH[4].LIMITH event */
#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
/* Bit 13 : Write '1' to Clear interrupt on EVENTS_CH[3].LIMITL event */
#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
/* Bit 12 : Write '1' to Clear interrupt on EVENTS_CH[3].LIMITH event */
#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
/* Bit 11 : Write '1' to Clear interrupt on EVENTS_CH[2].LIMITL event */
#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Clear interrupt on EVENTS_CH[2].LIMITH event */
#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_CH[1].LIMITL event */
#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Clear interrupt on EVENTS_CH[1].LIMITH event */
#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_CH[0].LIMITL event */
#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_CH[0].LIMITH event */
#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
/* Bit 5 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_CALIBRATEDONE event */
#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
/* Bit 3 : Write '1' to Clear interrupt on EVENTS_RESULTDONE event */
#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_DONE event */
#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_END event */
#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_STARTED event */
#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Register: SAADC_STATUS */
/* Description: Status */
/* Bit 0 : Status */
#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
/* Register: SAADC_ENABLE */
/* Description: Enable or disable ADC */
/* Bit 0 : Enable or disable ADC */
#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
/* Register: SAADC_CH_PSELP */
/* Description: Description cluster[0]: Input positive pin selection for CH[0] */
/* Bits 4..0 : Analog positive input channel */
#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
/* Register: SAADC_CH_PSELN */
/* Description: Description cluster[0]: Input negative pin selection for CH[0] */
/* Bits 4..0 : Analog negative input, enables differential channel */
#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
/* Register: SAADC_CH_CONFIG */
/* Description: Description cluster[0]: Input configuration for CH[0] */
/* Bit 20 : Enable differential mode */
#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
/* Bit 12 : Reference control */
#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
/* Bits 10..8 : Gain control */
#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
/* Bits 5..4 : Negative channel resistor control */
#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
/* Bits 1..0 : Positive channel resistor control */
#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
/* Register: SAADC_CH_LIMIT */
/* Description: Description cluster[0]: High/low limits for event monitoring a channel */
/* Bits 31..16 : High level limit */
#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
/* Bits 15..0 : Low level limit */
#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
/* Register: SAADC_RESOLUTION */
/* Description: Resolution configuration */
/* Bits 2..0 : Set the resolution */
#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
/* Register: SAADC_OVERSAMPLE */
/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
/* Bits 3..0 : Oversample control */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
/* Register: SAADC_SAMPLERATE */
/* Description: Controls normal or continuous sample rate */
/* Bit 12 : Select mode for sample rate control */
#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
/* Register: SAADC_RESULT_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SAADC_RESULT_MAXCNT */
/* Description: Maximum number of buffer words to transfer */
/* Bits 15..0 : Maximum number of buffer words to transfer */
#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0xFFFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SAADC_RESULT_AMOUNT */
/* Description: Number of buffer words transferred since last START */
/* Bits 15..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0xFFFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Peripheral: SPI */
/* Description: Serial Peripheral Interface 0 */
/* Register: SPI_INTENSET */
/* Description: Enable interrupt */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_READY event */
#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
/* Register: SPI_INTENCLR */
/* Description: Disable interrupt */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_READY event */
#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
/* Register: SPI_ENABLE */
/* Description: Enable SPI */
/* Bits 3..0 : Enable or disable SPI */
#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
/* Register: SPI_PSEL_SCK */
/* Description: Pin select for SCK */
/* Bits 31..0 : Pin number configuration for SPI SCK signal */
#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: SPI_PSEL_MOSI */
/* Description: Pin select for MOSI */
/* Bits 31..0 : Pin number configuration for SPI MOSI signal */
#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: SPI_PSEL_MISO */
/* Description: Pin select for MISO */
/* Bits 31..0 : Pin number configuration for SPI MISO signal */
#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: SPI_RXD */
/* Description: RXD register */
/* Bits 7..0 : RX data received. Double buffered */
#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: SPI_TXD */
/* Description: TXD register */
/* Bits 7..0 : TX data to send. Double buffered */
#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: SPI_FREQUENCY */
/* Description: SPI frequency */
/* Bits 31..0 : SPI master data rate */
#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
/* Register: SPI_CONFIG */
/* Description: Configuration register */
/* Bit 2 : Serial clock (SCK) polarity */
#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
/* Bit 1 : Serial clock (SCK) phase */
#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
/* Bit 0 : Bit order */
#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Peripheral: SPIM */
/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
/* Register: SPIM_SHORTS */
/* Description: Shortcut register */
/* Bit 17 : Shortcut between EVENTS_END event and TASKS_START task */
#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
/* Register: SPIM_INTENSET */
/* Description: Enable interrupt */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_STARTED event */
#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt on EVENTS_ENDTX event */
#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
/* Bit 6 : Write '1' to Enable interrupt on EVENTS_END event */
#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_ENDRX event */
#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: SPIM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_STARTED event */
#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Clear interrupt on EVENTS_ENDTX event */
#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
/* Bit 6 : Write '1' to Clear interrupt on EVENTS_END event */
#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_ENDRX event */
#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: SPIM_ENABLE */
/* Description: Enable SPIM */
/* Bits 3..0 : Enable or disable SPIM */
#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
/* Register: SPIM_PSEL_SCK */
/* Description: Pin select for SCK */
/* Bit 31 : Connection */
#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_PSEL_MOSI */
/* Description: Pin select for MOSI signal */
/* Bit 31 : Connection */
#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_PSEL_MISO */
/* Description: Pin select for MISO signal */
/* Bit 31 : Connection */
#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_FREQUENCY */
/* Description: SPI frequency */
/* Bits 31..0 : SPI master data rate */
#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
/* Register: SPIM_RXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIM_RXD_MAXCNT */
/* Description: Maximum number of buffer words to transfer */
/* Bits 7..0 : Maximum number of buffer words to transfer */
#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIM_RXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: SPIM_TXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIM_TXD_MAXCNT */
/* Description: Maximum number of buffer words to transfer */
/* Bits 7..0 : Maximum number of buffer words to transfer */
#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIM_TXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: SPIM_CONFIG */
/* Description: Configuration register */
/* Bit 2 : Serial clock (SCK) polarity */
#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
/* Bit 1 : Serial clock (SCK) phase */
#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
/* Bit 0 : Bit order */
#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Register: SPIM_ORC */
/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Peripheral: SPIS */
/* Description: SPI Slave 0 */
/* Register: SPIS_SHORTS */
/* Description: Shortcut register */
/* Bit 2 : Shortcut between EVENTS_END event and TASKS_ACQUIRE task */
#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
/* Register: SPIS_INTENSET */
/* Description: Enable interrupt */
/* Bit 10 : Write '1' to Enable interrupt on EVENTS_ACQUIRED event */
#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_END event */
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
/* Register: SPIS_INTENCLR */
/* Description: Disable interrupt */
/* Bit 10 : Write '1' to Clear interrupt on EVENTS_ACQUIRED event */
#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_END event */
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
/* Register: SPIS_SEMSTAT */
/* Description: Semaphore status register */
/* Bits 1..0 : Semaphore status */
#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
/* Register: SPIS_STATUS */
/* Description: Status from last transaction */
/* Bit 1 : RX buffer overflow detected, and prevented */
#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
/* Bit 0 : TX buffer over-read detected, and prevented */
#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
/* Register: SPIS_ENABLE */
/* Description: Enable SPI slave */
/* Bits 3..0 : Enable or disable SPI slave */
#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
/* Register: SPIS_PSEL_SCK */
/* Description: Pin select for SCK */
/* Bit 31 : Connection */
#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_PSEL_MISO */
/* Description: Pin select for MISO signal */
/* Bit 31 : Connection */
#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_PSEL_MOSI */
/* Description: Pin select for MOSI signal */
/* Bit 31 : Connection */
#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_PSEL_CSN */
/* Description: Pin select for CSN signal */
/* Bit 31 : Connection */
#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIS_RXD_PTR */
/* Description: RXD data pointer */
/* Bits 31..0 : RXD data pointer */
#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIS_RXD_AMOUNT */
/* Description: Number of bytes received in last granted transaction */
/* Bits 7..0 : Number of bytes received in the last granted transaction */
#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIS_TXD_PTR */
/* Description: TXD data pointer */
/* Bits 31..0 : TXD data pointer */
#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: SPIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIS_TXD_AMOUNT */
/* Description: Number of bytes transmitted in last granted transaction */
/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIS_CONFIG */
/* Description: Configuration register */
/* Bit 2 : Serial clock (SCK) polarity */
#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
/* Bit 1 : Serial clock (SCK) phase */
#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
/* Bit 0 : Bit order */
#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Register: SPIS_DEF */
/* Description: Default character. Character clocked out in case of an ignored transaction. */
/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
/* Register: SPIS_ORC */
/* Description: Over-read character */
/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Peripheral: TEMP */
/* Description: Temperature Sensor */
/* Register: TEMP_INTENSET */
/* Description: Enable interrupt */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_DATARDY event */
#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
/* Register: TEMP_INTENCLR */
/* Description: Disable interrupt */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_DATARDY event */
#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
/* Register: TEMP_TEMP */
/* Description: Temperature in degC */
/* Bits 31..0 : Temperature in degC */
#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
/* Peripheral: TIMER */
/* Description: Timer/Counter 0 */
/* Register: TIMER_SHORTS */
/* Description: Shortcut register */
/* Bit 13 : Shortcut between EVENTS_COMPARE[5] event and TASKS_STOP task */
#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 12 : Shortcut between EVENTS_COMPARE[4] event and TASKS_STOP task */
#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 11 : Shortcut between EVENTS_COMPARE[3] event and TASKS_STOP task */
#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 10 : Shortcut between EVENTS_COMPARE[2] event and TASKS_STOP task */
#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 9 : Shortcut between EVENTS_COMPARE[1] event and TASKS_STOP task */
#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 8 : Shortcut between EVENTS_COMPARE[0] event and TASKS_STOP task */
#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between EVENTS_COMPARE[5] event and TASKS_CLEAR task */
#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 4 : Shortcut between EVENTS_COMPARE[4] event and TASKS_CLEAR task */
#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_COMPARE[3] event and TASKS_CLEAR task */
#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 2 : Shortcut between EVENTS_COMPARE[2] event and TASKS_CLEAR task */
#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 1 : Shortcut between EVENTS_COMPARE[1] event and TASKS_CLEAR task */
#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_COMPARE[0] event and TASKS_CLEAR task */
#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
/* Register: TIMER_INTENSET */
/* Description: Enable interrupt */
/* Bit 21 : Write '1' to Enable interrupt on EVENTS_COMPARE[5] event */
#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt on EVENTS_COMPARE[4] event */
#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_COMPARE[3] event */
#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
/* Bit 18 : Write '1' to Enable interrupt on EVENTS_COMPARE[2] event */
#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt on EVENTS_COMPARE[1] event */
#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
/* Bit 16 : Write '1' to Enable interrupt on EVENTS_COMPARE[0] event */
#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
/* Register: TIMER_INTENCLR */
/* Description: Disable interrupt */
/* Bit 21 : Write '1' to Clear interrupt on EVENTS_COMPARE[5] event */
#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Clear interrupt on EVENTS_COMPARE[4] event */
#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_COMPARE[3] event */
#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
/* Bit 18 : Write '1' to Clear interrupt on EVENTS_COMPARE[2] event */
#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Clear interrupt on EVENTS_COMPARE[1] event */
#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
/* Bit 16 : Write '1' to Clear interrupt on EVENTS_COMPARE[0] event */
#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Register: TIMER_MODE */
/* Description: Timer mode selection */
/* Bits 1..0 : Timer mode */
#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
#define TIMER_MODE_MODE_Counter (1UL) /*!< Select Counter mode */
#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
/* Register: TIMER_BITMODE */
/* Description: Configure the number of bits used by the TIMER */
/* Bits 1..0 : Timer bit width */
#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
/* Register: TIMER_PRESCALER */
/* Description: Timer prescaler register */
/* Bits 3..0 : Prescaler value */
#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
/* Register: TIMER_CC */
/* Description: Description collection[0]: Capture/Compare register 0 */
/* Bits 31..0 : Capture/Compare value */
#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
/* Peripheral: TWI */
/* Description: I2C compatible Two-Wire Interface 0 */
/* Register: TWI_SHORTS */
/* Description: Shortcut register */
/* Bit 1 : Shortcut between EVENTS_BB event and TASKS_STOP task */
#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 0 : Shortcut between EVENTS_BB event and TASKS_SUSPEND task */
#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Register: TWI_INTENSET */
/* Description: Enable interrupt */
/* Bit 18 : Write '1' to Enable interrupt on EVENTS_SUSPENDED event */
#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
/* Bit 14 : Write '1' to Enable interrupt on EVENTS_BB event */
#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_TXDSENT event */
#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_RXDREADY event */
#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: TWI_INTENCLR */
/* Description: Disable interrupt */
/* Bit 18 : Write '1' to Clear interrupt on EVENTS_SUSPENDED event */
#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
/* Bit 14 : Write '1' to Clear interrupt on EVENTS_BB event */
#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_TXDSENT event */
#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_RXDREADY event */
#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: TWI_ERRORSRC */
/* Description: Error source */
/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
/* Bit 1 : NACK received after sending the address (write '1' to clear) */
#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
/* Bit 0 : Overrun error */
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
/* Register: TWI_ENABLE */
/* Description: Enable TWI */
/* Bits 3..0 : Enable or disable TWI */
#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
/* Register: TWI_PSELSCL */
/* Description: Pin select for SCL */
/* Bits 31..0 : Pin number configuration for TWI SCL signal */
#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: TWI_PSELSDA */
/* Description: Pin select for SDA */
/* Bits 31..0 : Pin number configuration for TWI SDA signal */
#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: TWI_RXD */
/* Description: RXD register */
/* Bits 7..0 : RXD register */
#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: TWI_TXD */
/* Description: TXD register */
/* Bits 7..0 : TXD register */
#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: TWI_FREQUENCY */
/* Description: TWI frequency */
/* Bits 31..0 : TWI master clock frequency */
#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
/* Register: TWI_ADDRESS */
/* Description: Address used in the TWI transfer */
/* Bits 6..0 : Address used in the TWI transfer */
#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
/* Peripheral: TWIM */
/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
/* Register: TWIM_SHORTS */
/* Description: Shortcut register */
/* Bit 12 : Shortcut between EVENTS_LASTRX event and TASKS_STOP task */
#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 10 : Shortcut between EVENTS_LASTRX event and TASKS_STARTTX task */
#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
/* Bit 9 : Shortcut between EVENTS_LASTTX event and TASKS_STOP task */
#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
/* Bit 8 : Shortcut between EVENTS_LASTTX event and TASKS_SUSPEND task */
#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Bit 7 : Shortcut between EVENTS_LASTTX event and TASKS_STARTRX task */
#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
/* Register: TWIM_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 24 : Enable or disable interrupt on EVENTS_LASTTX event */
#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
/* Bit 23 : Enable or disable interrupt on EVENTS_LASTRX event */
#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt on EVENTS_TXSTARTED event */
#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt on EVENTS_RXSTARTED event */
#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt on EVENTS_ERROR event */
#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_STOPPED event */
#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Register: TWIM_INTENSET */
/* Description: Enable interrupt */
/* Bit 24 : Write '1' to Enable interrupt on EVENTS_LASTTX event */
#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
/* Bit 23 : Write '1' to Enable interrupt on EVENTS_LASTRX event */
#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt on EVENTS_TXSTARTED event */
#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_RXSTARTED event */
#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: TWIM_INTENCLR */
/* Description: Disable interrupt */
/* Bit 24 : Write '1' to Clear interrupt on EVENTS_LASTTX event */
#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
/* Bit 23 : Write '1' to Clear interrupt on EVENTS_LASTRX event */
#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Clear interrupt on EVENTS_TXSTARTED event */
#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_RXSTARTED event */
#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: TWIM_ERRORSRC */
/* Description: Error source */
/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
/* Bit 1 : NACK received after sending the address (write '1' to clear) */
#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
/* Register: TWIM_ENABLE */
/* Description: Enable TWIM */
/* Bits 3..0 : Enable or disable TWIM */
#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
/* Register: TWIM_PSEL_SCL */
/* Description: Pin select for SCL signal */
/* Bit 31 : Connection */
#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIM_PSEL_SDA */
/* Description: Pin select for SDA signal */
/* Bit 31 : Connection */
#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIM_FREQUENCY */
/* Description: TWI frequency */
/* Bits 31..0 : TWI master clock frequency */
#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
/* Register: TWIM_RXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIM_RXD_MAXCNT */
/* Description: Maximum number of buffer words to transfer */
/* Bits 7..0 : Maximum number of buffer words to transfer */
#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIM_RXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: TWIM_TXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIM_TXD_MAXCNT */
/* Description: Maximum number of buffer words to transfer */
/* Bits 7..0 : Maximum number of buffer words to transfer */
#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIM_TXD_LIST */
/* Description: EasyDMA list type */
/* Bits 2..0 : List type */
#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
/* Register: TWIM_ADDRESS */
/* Description: Address used in the TWI transfer */
/* Bits 6..0 : Address used in the TWI transfer */
#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
/* Peripheral: TWIS */
/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
/* Register: TWIS_SHORTS */
/* Description: Shortcut register */
/* Bit 14 : Shortcut between EVENTS_READ event and TASKS_SUSPEND task */
#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Bit 13 : Shortcut between EVENTS_WRITE event and TASKS_SUSPEND task */
#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
/* Register: TWIS_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 26 : Enable or disable interrupt on EVENTS_READ event */
#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
/* Bit 25 : Enable or disable interrupt on EVENTS_WRITE event */
#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt on EVENTS_TXSTARTED event */
#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt on EVENTS_RXSTARTED event */
#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt on EVENTS_ERROR event */
#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_STOPPED event */
#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
/* Register: TWIS_INTENSET */
/* Description: Enable interrupt */
/* Bit 26 : Write '1' to Enable interrupt on EVENTS_READ event */
#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
/* Bit 25 : Write '1' to Enable interrupt on EVENTS_WRITE event */
#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt on EVENTS_TXSTARTED event */
#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_RXSTARTED event */
#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_STOPPED event */
#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
/* Register: TWIS_INTENCLR */
/* Description: Disable interrupt */
/* Bit 26 : Write '1' to Clear interrupt on EVENTS_READ event */
#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
/* Bit 25 : Write '1' to Clear interrupt on EVENTS_WRITE event */
#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Clear interrupt on EVENTS_TXSTARTED event */
#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_RXSTARTED event */
#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_STOPPED event */
#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
/* Register: TWIS_ERRORSRC */
/* Description: Error source */
/* Bit 3 : TX buffer over-read detected, and prevented */
#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
/* Bit 2 : NACK sent after receiving a data byte */
#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
/* Bit 0 : RX buffer overflow detected, and prevented */
#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
/* Register: TWIS_MATCH */
/* Description: Status register indicating which address had a match */
/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
/* Register: TWIS_ENABLE */
/* Description: Enable TWIS */
/* Bits 3..0 : Enable or disable TWIS */
#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
/* Register: TWIS_PSEL_SCL */
/* Description: Pin select for SCL signal */
/* Bit 31 : Connection */
#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIS_PSEL_SDA */
/* Description: Pin select for SDA signal */
/* Bit 31 : Connection */
#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: TWIS_RXD_PTR */
/* Description: RXD Data pointer */
/* Bits 31..0 : RXD Data pointer */
#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in RXD buffer */
/* Bits 7..0 : Maximum number of bytes in RXD buffer */
#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIS_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last RXD transaction */
/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_TXD_PTR */
/* Description: TXD Data pointer */
/* Bits 31..0 : TXD Data pointer */
#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: TWIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in TXD buffer */
/* Bits 7..0 : Maximum number of bytes in TXD buffer */
#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIS_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last TXD transaction */
/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_ADDRESS */
/* Description: Description collection[0]: TWI slave address 0 */
/* Bits 6..0 : TWI slave address */
#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
/* Register: TWIS_CONFIG */
/* Description: Configuration register for the address match mechanism */
/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
/* Register: TWIS_ORC */
/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Peripheral: UART */
/* Description: Universal Asynchronous Receiver/Transmitter */
/* Register: UART_SHORTS */
/* Description: Shortcut register */
/* Bit 4 : Shortcut between EVENTS_NCTS event and TASKS_STOPRX task */
#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
/* Bit 3 : Shortcut between EVENTS_CTS event and TASKS_STARTRX task */
#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
/* Register: UART_INTENSET */
/* Description: Enable interrupt */
/* Bit 17 : Write '1' to Enable interrupt on EVENTS_RXTO event */
#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 7 : Write '1' to Enable interrupt on EVENTS_TXDRDY event */
#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
/* Bit 2 : Write '1' to Enable interrupt on EVENTS_RXDRDY event */
#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_NCTS event */
#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_CTS event */
#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
/* Register: UART_INTENCLR */
/* Description: Disable interrupt */
/* Bit 17 : Write '1' to Clear interrupt on EVENTS_RXTO event */
#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 7 : Write '1' to Clear interrupt on EVENTS_TXDRDY event */
#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
/* Bit 2 : Write '1' to Clear interrupt on EVENTS_RXDRDY event */
#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_NCTS event */
#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_CTS event */
#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
/* Register: UART_ERRORSRC */
/* Description: Error source */
/* Bit 3 : Break condition */
#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
/* Bit 2 : Framing error occurred */
#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
/* Bit 1 : Parity error */
#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
/* Bit 0 : Overrun error */
#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
/* Register: UART_ENABLE */
/* Description: Enable UART */
/* Bits 3..0 : Enable or disable UART */
#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
/* Register: UART_PSELRTS */
/* Description: Pin select for RTS */
/* Bits 31..0 : Pin number configuration for UART RTS signal */
#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_PSELTXD */
/* Description: Pin select for TXD */
/* Bits 31..0 : Pin number configuration for UART TXD signal */
#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_PSELCTS */
/* Description: Pin select for CTS */
/* Bits 31..0 : Pin number configuration for UART CTS signal */
#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_PSELRXD */
/* Description: Pin select for RXD */
/* Bits 31..0 : Pin number configuration for UART RXD signal */
#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
/* Register: UART_RXD */
/* Description: RXD register */
/* Bits 7..0 : RX data received in previous transfers, double buffered */
#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: UART_TXD */
/* Description: TXD register */
/* Bits 7..0 : TX data to be transferred */
#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: UART_BAUDRATE */
/* Description: Baud rate */
/* Bits 31..0 : Baud-rate */
#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
/* Register: UART_CONFIG */
/* Description: Configuration of parity and hardware flow control */
/* Bits 3..1 : Parity */
#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
/* Bit 0 : Hardware flow control */
#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
/* Peripheral: UARTE */
/* Description: UART with EasyDMA */
/* Register: UARTE_SHORTS */
/* Description: Shortcut register */
/* Bit 6 : Shortcut between EVENTS_ENDRX event and TASKS_STOPRX task */
#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
/* Bit 5 : Shortcut between EVENTS_ENDRX event and TASKS_STARTRX task */
#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
/* Register: UARTE_INTEN */
/* Description: Enable or disable interrupt */
/* Bit 22 : Enable or disable interrupt on EVENTS_TXSTOPPED event */
#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
/* Bit 20 : Enable or disable interrupt on EVENTS_TXSTARTED event */
#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 19 : Enable or disable interrupt on EVENTS_RXSTARTED event */
#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable interrupt on EVENTS_RXTO event */
#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
/* Bit 9 : Enable or disable interrupt on EVENTS_ERROR event */
#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
/* Bit 8 : Enable or disable interrupt on EVENTS_ENDTX event */
#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
/* Bit 4 : Enable or disable interrupt on EVENTS_ENDRX event */
#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable interrupt on EVENTS_NCTS event */
#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable interrupt on EVENTS_CTS event */
#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
/* Register: UARTE_INTENSET */
/* Description: Enable interrupt */
/* Bit 22 : Write '1' to Enable interrupt on EVENTS_TXSTOPPED event */
#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
/* Bit 20 : Write '1' to Enable interrupt on EVENTS_TXSTARTED event */
#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
/* Bit 19 : Write '1' to Enable interrupt on EVENTS_RXSTARTED event */
#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
/* Bit 17 : Write '1' to Enable interrupt on EVENTS_RXTO event */
#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
/* Bit 9 : Write '1' to Enable interrupt on EVENTS_ERROR event */
#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
/* Bit 8 : Write '1' to Enable interrupt on EVENTS_ENDTX event */
#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt on EVENTS_ENDRX event */
#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
/* Bit 1 : Write '1' to Enable interrupt on EVENTS_NCTS event */
#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_CTS event */
#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
/* Register: UARTE_INTENCLR */
/* Description: Disable interrupt */
/* Bit 22 : Write '1' to Clear interrupt on EVENTS_TXSTOPPED event */
#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
/* Bit 20 : Write '1' to Clear interrupt on EVENTS_TXSTARTED event */
#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 19 : Write '1' to Clear interrupt on EVENTS_RXSTARTED event */
#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
/* Bit 17 : Write '1' to Clear interrupt on EVENTS_RXTO event */
#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
/* Bit 9 : Write '1' to Clear interrupt on EVENTS_ERROR event */
#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
/* Bit 8 : Write '1' to Clear interrupt on EVENTS_ENDTX event */
#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Clear interrupt on EVENTS_ENDRX event */
#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
/* Bit 1 : Write '1' to Clear interrupt on EVENTS_NCTS event */
#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_CTS event */
#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
/* Register: UARTE_ERRORSRC */
/* Description: Error source */
/* Bit 3 : Break condition */
#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
/* Bit 2 : Framing error occurred */
#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
/* Bit 1 : Parity error */
#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
/* Bit 0 : Overrun error */
#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
/* Register: UARTE_ENABLE */
/* Description: Enable UART */
/* Bits 3..0 : Enable or disable UARTE */
#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
/* Register: UARTE_PSEL_RTS */
/* Description: Pin select for RTS signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_PSEL_TXD */
/* Description: Pin select for TXD signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_PSEL_CTS */
/* Description: Pin select for CTS signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_PSEL_RXD */
/* Description: Pin select for RXD signal */
/* Bit 31 : Connection */
#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : Pin number */
#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UARTE_BAUDRATE */
/* Description: Baud rate */
/* Bits 31..0 : Baud-rate */
#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
/* Register: UARTE_RXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: UARTE_RXD_MAXCNT */
/* Description: Maximum number of bytes in buffer */
/* Bits 7..0 : Maximum number of bytes in buffer */
#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: UARTE_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: UARTE_TXD_PTR */
/* Description: Data pointer */
/* Bits 31..0 : Data pointer */
#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: UARTE_TXD_MAXCNT */
/* Description: Maximum number of bytes in buffer */
/* Bits 7..0 : Maximum number of bytes in buffer */
#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: UARTE_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction */
#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: UARTE_CONFIG */
/* Description: Configuration of parity and hardware flow control */
/* Bits 3..1 : Parity */
#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
/* Bit 0 : Hardware flow control */
#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
/* Peripheral: UICR */
/* Description: User Information Configuration Registers */
/* Register: UICR_NRFFW */
/* Description: Description collection[0]: Reserved for Nordic firmware design */
/* Bits 31..0 : Reserved for Nordic firmware design */
#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
/* Register: UICR_NRFHW */
/* Description: Description collection[0]: Reserved for Nordic hardware design */
/* Bits 31..0 : Reserved for Nordic hardware design */
#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
/* Register: UICR_CUSTOMER */
/* Description: Description collection[0]: Reserved for customer */
/* Bits 31..0 : Reserved for customer */
#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
/* Register: UICR_PSELRESET */
/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
/* Bit 31 : Connection */
#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: UICR_APPROTECT */
/* Description: Access port protection */
/* Bits 7..0 : Blocks debugger read/write access to all CPU registers and memory mapped addresses except for the Control Access Port registers. */
#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
/* Register: UICR_NFCPINS */
/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
/* Bit 0 : Setting of pins dedicated to NFC functionality */
#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
/* Peripheral: WDT */
/* Description: Watchdog Timer */
/* Register: WDT_INTENSET */
/* Description: Enable interrupt */
/* Bit 0 : Write '1' to Enable interrupt on EVENTS_TIMEOUT event */
#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
/* Register: WDT_INTENCLR */
/* Description: Disable interrupt */
/* Bit 0 : Write '1' to Clear interrupt on EVENTS_TIMEOUT event */
#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
/* Register: WDT_RUNSTATUS */
/* Description: Run status */
/* Bit 0 : Indicates whether or not the watchdog is running */
#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
/* Register: WDT_REQSTATUS */
/* Description: Request status */
/* Bit 7 : Request status for RR[7] register */
#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
/* Bit 6 : Request status for RR[6] register */
#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
/* Bit 5 : Request status for RR[5] register */
#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
/* Bit 4 : Request status for RR[4] register */
#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
/* Bit 3 : Request status for RR[3] register */
#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
/* Bit 2 : Request status for RR[2] register */
#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
/* Bit 1 : Request status for RR[1] register */
#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
/* Bit 0 : Request status for RR[0] register */
#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
/* Register: WDT_CRV */
/* Description: Counter reload value */
/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
/* Register: WDT_RREN */
/* Description: Enable register for reload request registers */
/* Bit 7 : Enable or disable RR[7] register */
#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
/* Bit 6 : Enable or disable RR[6] register */
#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
/* Bit 5 : Enable or disable RR[5] register */
#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
/* Bit 4 : Enable or disable RR[4] register */
#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
/* Bit 3 : Enable or disable RR[3] register */
#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
/* Bit 2 : Enable or disable RR[2] register */
#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
/* Bit 1 : Enable or disable RR[1] register */
#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
/* Bit 0 : Enable or disable RR[0] register */
#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
/* Register: WDT_CONFIG */
/* Description: Configuration register */
/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
/* Register: WDT_RR */
/* Description: Description collection[0]: Reload request 0 */
/* Bits 31..0 : Reload request register */
#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
/*lint --flb "Leave library region" */
#endif
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using System;
namespace Codecov.Services.ContinuousIntegrationServers
{
internal class Jenkins : ContinuousIntegrationServer
{
private readonly Lazy<string> _branch;
private readonly Lazy<string> _build;
private readonly Lazy<string> _buildUrl;
private readonly Lazy<string> _commit;
private readonly Lazy<bool> _detecter;
private readonly Lazy<string> _pr;
public Jenkins(IEnviornmentVariables environmentVariables)
: base(environmentVariables)
{
_branch = new Lazy<string>(() => GetFirstExistingEnvironmentVariable("ghprbSourceBranch", "GIT_BRANCH", "BRANCH_NAME"));
_build = new Lazy<string>(() => GetEnvironmentVariable("BUILD_NUMBER"));
_buildUrl = new Lazy<string>(() => GetEnvironmentVariable("BUILD_URL"));
_commit = new Lazy<string>(() => GetFirstExistingEnvironmentVariable("ghprbActualCommit", "GIT_COMMIT"));
_detecter = new Lazy<bool>(() => !string.IsNullOrWhiteSpace(GetEnvironmentVariable("JENKINS_URL")));
_pr = new Lazy<string>(() => GetFirstExistingEnvironmentVariable("ghprbPullId", "CHANGE_ID"));
}
public override string Branch => _branch.Value;
public override string Build => _build.Value;
public override string BuildUrl => _buildUrl.Value;
public override string Commit => _commit.Value;
public override bool Detecter => _detecter.Value;
public override string Pr => _pr.Value;
public override string Service => "jenkins";
}
}
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import { html, LitElement } from 'lit';
import { customElement, property, query } from 'lit/decorators.js';
import { styleMap } from 'lit/directives/style-map.js';
import '../../components/icon/icon';
import { drag } from '../../internal/drag';
import { emit } from '../../internal/event';
import { clamp } from '../../internal/math';
import { watch } from '../../internal/watch';
import styles from './image-comparer.styles';
/**
* @since 2.0
* @status stable
*
* @dependency sl-icon
*
* @slot before - The before image, an `<img>` or `<svg>` element.
* @slot after - The after image, an `<img>` or `<svg>` element.
* @slot handle-icon - The icon used inside the handle.
*
* @event sl-change - Emitted when the position changes.
*
* @csspart base - The component's internal wrapper.
* @csspart before - The container that holds the "before" image.
* @csspart after - The container that holds the "after" image.
* @csspart divider - The divider that separates the images.
* @csspart handle - The handle that the user drags to expose the after image.
*
* @cssproperty --divider-width - The width of the dividing line.
* @cssproperty --handle-size - The size of the compare handle.
*/
@customElement('sl-image-comparer')
export default class SlImageComparer extends LitElement {
static styles = styles;
@query('.image-comparer') base: HTMLElement;
@query('.image-comparer__handle') handle: HTMLElement;
/** The position of the divider as a percentage. */
@property({ type: Number, reflect: true }) position = 50;
handleDrag(event: Event) {
const { width } = this.base.getBoundingClientRect();
event.preventDefault();
drag(this.base, x => {
this.position = parseFloat(clamp((x / width) * 100, 0, 100).toFixed(2));
});
}
handleKeyDown(event: KeyboardEvent) {
if (['ArrowLeft', 'ArrowRight', 'Home', 'End'].includes(event.key)) {
const incr = event.shiftKey ? 10 : 1;
let newPosition = this.position;
event.preventDefault();
if (event.key === 'ArrowLeft') {
newPosition -= incr;
}
if (event.key === 'ArrowRight') {
newPosition += incr;
}
if (event.key === 'Home') {
newPosition = 0;
}
if (event.key === 'End') {
newPosition = 100;
}
newPosition = clamp(newPosition, 0, 100);
this.position = newPosition;
}
}
@watch('position', { waitUntilFirstUpdate: true })
handlePositionChange() {
emit(this, 'sl-change');
}
render() {
return html`
<div part="base" id="image-comparer" class="image-comparer" @keydown=${this.handleKeyDown}>
<div class="image-comparer__image">
<div part="before" class="image-comparer__before">
<slot name="before"></slot>
</div>
<div
part="after"
class="image-comparer__after"
style=${styleMap({ clipPath: `inset(0 ${100 - this.position}% 0 0)` })}
>
<slot name="after"></slot>
</div>
</div>
<div
part="divider"
class="image-comparer__divider"
style=${styleMap({ left: `${this.position}%` })}
@mousedown=${this.handleDrag}
@touchstart=${this.handleDrag}
>
<div
part="handle"
class="image-comparer__handle"
role="scrollbar"
aria-valuenow=${this.position}
aria-valuemin="0"
aria-valuemax="100"
aria-controls="image-comparer"
tabindex="0"
>
<slot name="handle-icon">
<sl-icon class="image-comparer__handle-icon" name="grip-vertical" library="system"></sl-icon>
</slot>
</div>
</div>
</div>
`;
}
}
declare global {
interface HTMLElementTagNameMap {
'sl-image-comparer': SlImageComparer;
}
}
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package org.elasticsearch.discovery;
import org.apache.logging.log4j.message.ParameterizedMessage;
import org.elasticsearch.cluster.ClusterState;
import org.elasticsearch.cluster.ClusterStateUpdateTask;
import org.elasticsearch.cluster.metadata.IndexMetaData;
import org.elasticsearch.cluster.node.DiscoveryNode;
import org.elasticsearch.cluster.service.ClusterService;
import org.elasticsearch.common.Priority;
import org.elasticsearch.common.Strings;
import org.elasticsearch.common.collect.Tuple;
import org.elasticsearch.common.settings.Settings;
import org.elasticsearch.common.unit.TimeValue;
import org.elasticsearch.discovery.zen.ElectMasterService;
import org.elasticsearch.discovery.zen.ZenDiscovery;
import org.elasticsearch.monitor.jvm.HotThreads;
import org.elasticsearch.test.ESIntegTestCase;
import org.elasticsearch.test.disruption.IntermittentLongGCDisruption;
import org.elasticsearch.test.disruption.LongGCDisruption;
import org.elasticsearch.test.disruption.NetworkDisruption;
import org.elasticsearch.test.disruption.NetworkDisruption.TwoPartitions;
import org.elasticsearch.test.disruption.SingleNodeDisruption;
import org.elasticsearch.test.junit.annotations.TestLogging;
import java.util.ArrayList;
import java.util.Collections;
import java.util.HashMap;
import java.util.HashSet;
import java.util.List;
import java.util.Map;
import java.util.Objects;
import java.util.Set;
import java.util.concurrent.CountDownLatch;
import java.util.concurrent.TimeUnit;
import static org.elasticsearch.test.hamcrest.ElasticsearchAssertions.assertAcked;
import static org.hamcrest.Matchers.equalTo;
import static org.hamcrest.Matchers.not;
import static org.hamcrest.Matchers.nullValue;
/**
* Tests relating to the loss of the master.
*/
@ESIntegTestCase.ClusterScope(scope = ESIntegTestCase.Scope.TEST, numDataNodes = 0, transportClientRatio = 0, autoMinMasterNodes = false)
@TestLogging("_root:DEBUG,org.elasticsearch.cluster.service:TRACE")
public class MasterDisruptionIT extends AbstractDisruptionTestCase {
/**
* Test that no split brain occurs under partial network partition. See https://github.com/elastic/elasticsearch/issues/2488
*/
public void testFailWithMinimumMasterNodesConfigured() throws Exception {
List<String> nodes = startCluster(3);
// Figure out what is the elected master node
final String masterNode = internalCluster().getMasterName();
logger.info("---> legit elected master node={}", masterNode);
// Pick a node that isn't the elected master.
Set<String> nonMasters = new HashSet<>(nodes);
nonMasters.remove(masterNode);
final String unluckyNode = randomFrom(nonMasters.toArray(Strings.EMPTY_ARRAY));
// Simulate a network issue between the unlucky node and elected master node in both directions.
NetworkDisruption networkDisconnect = new NetworkDisruption(
new NetworkDisruption.TwoPartitions(masterNode, unluckyNode),
new NetworkDisruption.NetworkDisconnect());
setDisruptionScheme(networkDisconnect);
networkDisconnect.startDisrupting();
// Wait until elected master has removed that the unlucky node...
ensureStableCluster(2, masterNode);
// The unlucky node must report *no* master node, since it can't connect to master and in fact it should
// continuously ping until network failures have been resolved. However
// It may a take a bit before the node detects it has been cut off from the elected master
assertNoMaster(unluckyNode);
networkDisconnect.stopDisrupting();
// Wait until the master node sees all 3 nodes again.
ensureStableCluster(3);
// The elected master shouldn't have changed, since the unlucky node never could have elected himself as
// master since m_m_n of 2 could never be satisfied.
assertMaster(masterNode, nodes);
}
/**
* Verify that nodes fault detection works after master (re) election
*/
public void testNodesFDAfterMasterReelection() throws Exception {
startCluster(4);
logger.info("--> stopping current master");
internalCluster().stopCurrentMasterNode();
ensureStableCluster(3);
logger.info("--> reducing min master nodes to 2");
assertAcked(client().admin().cluster().prepareUpdateSettings()
.setTransientSettings(Settings.builder().put(ElectMasterService.DISCOVERY_ZEN_MINIMUM_MASTER_NODES_SETTING.getKey(), 2))
.get());
String master = internalCluster().getMasterName();
String nonMaster = null;
for (String node : internalCluster().getNodeNames()) {
if (!node.equals(master)) {
nonMaster = node;
}
}
logger.info("--> isolating [{}]", nonMaster);
NetworkDisruption.TwoPartitions partitions = isolateNode(nonMaster);
NetworkDisruption networkDisruption = addRandomDisruptionType(partitions);
networkDisruption.startDisrupting();
logger.info("--> waiting for master to remove it");
ensureStableCluster(2, master);
}
/**
* Tests that emulates a frozen elected master node that unfreezes and pushes his cluster state to other nodes
* that already are following another elected master node. These nodes should reject this cluster state and prevent
* them from following the stale master.
*/
@TestLogging("_root:DEBUG,org.elasticsearch.cluster.service:TRACE,org.elasticsearch.test.disruption:TRACE")
public void testStaleMasterNotHijackingMajority() throws Exception {
// 3 node cluster with unicast discovery and minimum_master_nodes set to 2:
final List<String> nodes = startCluster(3, 2);
// Save the current master node as old master node, because that node will get frozen
final String oldMasterNode = internalCluster().getMasterName();
for (String node : nodes) {
ensureStableCluster(3, node);
}
assertMaster(oldMasterNode, nodes);
// Simulating a painful gc by suspending all threads for a long time on the current elected master node.
SingleNodeDisruption masterNodeDisruption = new LongGCDisruption(random(), oldMasterNode);
// Save the majority side
final List<String> majoritySide = new ArrayList<>(nodes);
majoritySide.remove(oldMasterNode);
// Keeps track of the previous and current master when a master node transition took place on each node on the majority side:
final Map<String, List<Tuple<String, String>>> masters = Collections.synchronizedMap(new HashMap<String, List<Tuple<String,
String>>>());
for (final String node : majoritySide) {
masters.put(node, new ArrayList<Tuple<String, String>>());
internalCluster().getInstance(ClusterService.class, node).addListener(event -> {
DiscoveryNode previousMaster = event.previousState().nodes().getMasterNode();
DiscoveryNode currentMaster = event.state().nodes().getMasterNode();
if (!Objects.equals(previousMaster, currentMaster)) {
logger.info("node {} received new cluster state: {} \n and had previous cluster state: {}", node, event.state(),
event.previousState());
String previousMasterNodeName = previousMaster != null ? previousMaster.getName() : null;
String currentMasterNodeName = currentMaster != null ? currentMaster.getName() : null;
masters.get(node).add(new Tuple<>(previousMasterNodeName, currentMasterNodeName));
}
});
}
final CountDownLatch oldMasterNodeSteppedDown = new CountDownLatch(1);
internalCluster().getInstance(ClusterService.class, oldMasterNode).addListener(event -> {
if (event.state().nodes().getMasterNodeId() == null) {
oldMasterNodeSteppedDown.countDown();
}
});
internalCluster().setDisruptionScheme(masterNodeDisruption);
logger.info("freezing node [{}]", oldMasterNode);
masterNodeDisruption.startDisrupting();
// Wait for the majority side to get stable
assertDifferentMaster(majoritySide.get(0), oldMasterNode);
assertDifferentMaster(majoritySide.get(1), oldMasterNode);
// the test is periodically tripping on the following assertion. To find out which threads are blocking the nodes from making
// progress we print a stack dump
boolean failed = true;
try {
assertDiscoveryCompleted(majoritySide);
failed = false;
} finally {
if (failed) {
logger.error("discovery failed to complete, probably caused by a blocked thread: {}",
new HotThreads().busiestThreads(Integer.MAX_VALUE).ignoreIdleThreads(false).detect());
}
}
// The old master node is frozen, but here we submit a cluster state update task that doesn't get executed,
// but will be queued and once the old master node un-freezes it gets executed.
// The old master node will send this update + the cluster state where he is flagged as master to the other
// nodes that follow the new master. These nodes should ignore this update.
internalCluster().getInstance(ClusterService.class, oldMasterNode).submitStateUpdateTask("sneaky-update", new
ClusterStateUpdateTask(Priority.IMMEDIATE) {
@Override
public ClusterState execute(ClusterState currentState) throws Exception {
return ClusterState.builder(currentState).build();
}
@Override
public void onFailure(String source, Exception e) {
logger.warn(() -> new ParameterizedMessage("failure [{}]", source), e);
}
});
// Save the new elected master node
final String newMasterNode = internalCluster().getMasterName(majoritySide.get(0));
logger.info("new detected master node [{}]", newMasterNode);
// Stop disruption
logger.info("Unfreeze node [{}]", oldMasterNode);
masterNodeDisruption.stopDisrupting();
oldMasterNodeSteppedDown.await(30, TimeUnit.SECONDS);
// Make sure that the end state is consistent on all nodes:
assertDiscoveryCompleted(nodes);
assertMaster(newMasterNode, nodes);
assertThat(masters.size(), equalTo(2));
for (Map.Entry<String, List<Tuple<String, String>>> entry : masters.entrySet()) {
String nodeName = entry.getKey();
List<Tuple<String, String>> recordedMasterTransition = entry.getValue();
assertThat("[" + nodeName + "] Each node should only record two master node transitions", recordedMasterTransition.size(),
equalTo(2));
assertThat("[" + nodeName + "] First transition's previous master should be [null]", recordedMasterTransition.get(0).v1(),
equalTo(oldMasterNode));
assertThat("[" + nodeName + "] First transition's current master should be [" + newMasterNode + "]", recordedMasterTransition
.get(0).v2(), nullValue());
assertThat("[" + nodeName + "] Second transition's previous master should be [null]", recordedMasterTransition.get(1).v1(),
nullValue());
assertThat("[" + nodeName + "] Second transition's current master should be [" + newMasterNode + "]",
recordedMasterTransition.get(1).v2(), equalTo(newMasterNode));
}
}
/**
* Test that cluster recovers from a long GC on master that causes other nodes to elect a new one
*/
public void testMasterNodeGCs() throws Exception {
List<String> nodes = startCluster(3, -1);
String oldMasterNode = internalCluster().getMasterName();
// a very long GC, but it's OK as we remove the disruption when it has had an effect
SingleNodeDisruption masterNodeDisruption = new IntermittentLongGCDisruption(random(), oldMasterNode, 100, 200, 30000, 60000);
internalCluster().setDisruptionScheme(masterNodeDisruption);
masterNodeDisruption.startDisrupting();
Set<String> oldNonMasterNodesSet = new HashSet<>(nodes);
oldNonMasterNodesSet.remove(oldMasterNode);
List<String> oldNonMasterNodes = new ArrayList<>(oldNonMasterNodesSet);
logger.info("waiting for nodes to de-elect master [{}]", oldMasterNode);
for (String node : oldNonMasterNodesSet) {
assertDifferentMaster(node, oldMasterNode);
}
logger.info("waiting for nodes to elect a new master");
ensureStableCluster(2, oldNonMasterNodes.get(0));
logger.info("waiting for any pinging to stop");
assertDiscoveryCompleted(oldNonMasterNodes);
// restore GC
masterNodeDisruption.stopDisrupting();
final TimeValue waitTime = new TimeValue(DISRUPTION_HEALING_OVERHEAD.millis() + masterNodeDisruption.expectedTimeToHeal().millis());
ensureStableCluster(3, waitTime, false, oldNonMasterNodes.get(0));
// make sure all nodes agree on master
String newMaster = internalCluster().getMasterName();
assertThat(newMaster, not(equalTo(oldMasterNode)));
assertMaster(newMaster, nodes);
}
/**
* This test isolates the master from rest of the cluster, waits for a new master to be elected, restores the partition
* and verifies that all node agree on the new cluster state
*/
@TestLogging(
"_root:DEBUG,"
+ "org.elasticsearch.cluster.service:TRACE,"
+ "org.elasticsearch.gateway:TRACE,"
+ "org.elasticsearch.indices.store:TRACE")
public void testIsolateMasterAndVerifyClusterStateConsensus() throws Exception {
final List<String> nodes = startCluster(3);
assertAcked(prepareCreate("test")
.setSettings(Settings.builder()
.put(IndexMetaData.SETTING_NUMBER_OF_SHARDS, 1 + randomInt(2))
.put(IndexMetaData.SETTING_NUMBER_OF_REPLICAS, randomInt(2))
));
ensureGreen();
String isolatedNode = internalCluster().getMasterName();
TwoPartitions partitions = isolateNode(isolatedNode);
NetworkDisruption networkDisruption = addRandomDisruptionType(partitions);
networkDisruption.startDisrupting();
String nonIsolatedNode = partitions.getMajoritySide().iterator().next();
// make sure cluster reforms
ensureStableCluster(2, nonIsolatedNode);
// make sure isolated need picks up on things.
assertNoMaster(isolatedNode, TimeValue.timeValueSeconds(40));
// restore isolation
networkDisruption.stopDisrupting();
for (String node : nodes) {
ensureStableCluster(3, new TimeValue(DISRUPTION_HEALING_OVERHEAD.millis() + networkDisruption.expectedTimeToHeal().millis()),
true, node);
}
logger.info("issue a reroute");
// trigger a reroute now, instead of waiting for the background reroute of RerouteService
assertAcked(client().admin().cluster().prepareReroute());
// and wait for it to finish and for the cluster to stabilize
ensureGreen("test");
// verify all cluster states are the same
// use assert busy to wait for cluster states to be applied (as publish_timeout has low value)
assertBusy(() -> {
ClusterState state = null;
for (String node : nodes) {
ClusterState nodeState = getNodeClusterState(node);
if (state == null) {
state = nodeState;
continue;
}
// assert nodes are identical
try {
assertEquals("unequal versions", state.version(), nodeState.version());
assertEquals("unequal node count", state.nodes().getSize(), nodeState.nodes().getSize());
assertEquals("different masters ", state.nodes().getMasterNodeId(), nodeState.nodes().getMasterNodeId());
assertEquals("different meta data version", state.metaData().version(), nodeState.metaData().version());
assertEquals("different routing", state.routingTable().toString(), nodeState.routingTable().toString());
} catch (AssertionError t) {
fail("failed comparing cluster state: " + t.getMessage() + "\n" +
"--- cluster state of node [" + nodes.get(0) + "]: ---\n" + state +
"\n--- cluster state [" + node + "]: ---\n" + nodeState);
}
}
});
}
/**
* Verify that the proper block is applied when nodes loose their master
*/
public void testVerifyApiBlocksDuringPartition() throws Exception {
startCluster(3);
// Makes sure that the get request can be executed on each node locally:
assertAcked(prepareCreate("test").setSettings(Settings.builder()
.put(IndexMetaData.SETTING_NUMBER_OF_SHARDS, 1)
.put(IndexMetaData.SETTING_NUMBER_OF_REPLICAS, 2)
));
// Everything is stable now, it is now time to simulate evil...
// but first make sure we have no initializing shards and all is green
// (waiting for green here, because indexing / search in a yellow index is fine as long as no other nodes go down)
ensureGreen("test");
TwoPartitions partitions = TwoPartitions.random(random(), internalCluster().getNodeNames());
NetworkDisruption networkDisruption = addRandomDisruptionType(partitions);
assertEquals(1, partitions.getMinoritySide().size());
final String isolatedNode = partitions.getMinoritySide().iterator().next();
assertEquals(2, partitions.getMajoritySide().size());
final String nonIsolatedNode = partitions.getMajoritySide().iterator().next();
// Simulate a network issue between the unlucky node and the rest of the cluster.
networkDisruption.startDisrupting();
// The unlucky node must report *no* master node, since it can't connect to master and in fact it should
// continuously ping until network failures have been resolved. However
// It may a take a bit before the node detects it has been cut off from the elected master
logger.info("waiting for isolated node [{}] to have no master", isolatedNode);
assertNoMaster(isolatedNode, DiscoverySettings.NO_MASTER_BLOCK_WRITES, TimeValue.timeValueSeconds(10));
logger.info("wait until elected master has been removed and a new 2 node cluster was from (via [{}])", isolatedNode);
ensureStableCluster(2, nonIsolatedNode);
for (String node : partitions.getMajoritySide()) {
ClusterState nodeState = getNodeClusterState(node);
boolean success = true;
if (nodeState.nodes().getMasterNode() == null) {
success = false;
}
if (!nodeState.blocks().global().isEmpty()) {
success = false;
}
if (!success) {
fail("node [" + node + "] has no master or has blocks, despite of being on the right side of the partition. State dump:\n"
+ nodeState);
}
}
networkDisruption.stopDisrupting();
// Wait until the master node sees al 3 nodes again.
ensureStableCluster(3, new TimeValue(DISRUPTION_HEALING_OVERHEAD.millis() + networkDisruption.expectedTimeToHeal().millis()));
logger.info("Verify no master block with {} set to {}", DiscoverySettings.NO_MASTER_BLOCK_SETTING.getKey(), "all");
client().admin().cluster().prepareUpdateSettings()
.setTransientSettings(Settings.builder().put(DiscoverySettings.NO_MASTER_BLOCK_SETTING.getKey(), "all"))
.get();
networkDisruption.startDisrupting();
// The unlucky node must report *no* master node, since it can't connect to master and in fact it should
// continuously ping until network failures have been resolved. However
// It may a take a bit before the node detects it has been cut off from the elected master
logger.info("waiting for isolated node [{}] to have no master", isolatedNode);
assertNoMaster(isolatedNode, DiscoverySettings.NO_MASTER_BLOCK_ALL, TimeValue.timeValueSeconds(10));
// make sure we have stable cluster & cross partition recoveries are canceled by the removal of the missing node
// the unresponsive partition causes recoveries to only time out after 15m (default) and these will cause
// the test to fail due to unfreed resources
ensureStableCluster(2, nonIsolatedNode);
}
void assertDiscoveryCompleted(List<String> nodes) throws InterruptedException {
for (final String node : nodes) {
assertTrue(
"node [" + node + "] is still joining master",
awaitBusy(
() -> !((ZenDiscovery) internalCluster().getInstance(Discovery.class, node)).joiningCluster(),
30,
TimeUnit.SECONDS
)
);
}
}
}
| {'content_hash': '001c84d19074596e87ef56b29c532341', 'timestamp': '', 'source': 'github', 'line_count': 448, 'max_line_length': 140, 'avg_line_length': 48.520089285714285, 'alnum_prop': 0.6572204075999448, 'repo_name': 'rajanm/elasticsearch', 'id': '43e3b2ef01b676d3ec07f1980e360efc19a63cbe', 'size': '22525', 'binary': False, 'copies': '4', 'ref': 'refs/heads/master', 'path': 'server/src/test/java/org/elasticsearch/discovery/MasterDisruptionIT.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '10152'}, {'name': 'Groovy', 'bytes': '451'}, {'name': 'HTML', 'bytes': '1212'}, {'name': 'Java', 'bytes': '27475929'}, {'name': 'Perl', 'bytes': '7087'}, {'name': 'Python', 'bytes': '79977'}, {'name': 'Ruby', 'bytes': '17776'}, {'name': 'Shell', 'bytes': '84636'}]} |
SYNONYM
#### According to
The Catalogue of Life, 3rd January 2011
#### Published in
null
#### Original name
null
### Remarks
null | {'content_hash': '1a8e9f4cae404aef1f5ca6037f3af4ee', 'timestamp': '', 'source': 'github', 'line_count': 13, 'max_line_length': 39, 'avg_line_length': 10.23076923076923, 'alnum_prop': 0.6917293233082706, 'repo_name': 'mdoering/backbone', 'id': '909e659a94d198e2b7a8d533f8537af28b7a5937', 'size': '200', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'life/Plantae/Magnoliophyta/Magnoliopsida/Brassicales/Brassicaceae/Eutrema/Eutrema yungshunensis/ Syn. Eutrema xingshanensis/README.md', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
package org.optaplanner.quarkus.testdata.normal.domain;
import java.util.List;
import org.optaplanner.core.api.domain.solution.PlanningEntityCollectionProperty;
import org.optaplanner.core.api.domain.solution.PlanningScore;
import org.optaplanner.core.api.domain.solution.PlanningSolution;
import org.optaplanner.core.api.domain.solution.ProblemFactCollectionProperty;
import org.optaplanner.core.api.domain.valuerange.ValueRangeProvider;
import org.optaplanner.core.api.score.buildin.simple.SimpleScore;
@PlanningSolution
public class TestdataQuarkusSolution {
private List<String> valueList;
private List<TestdataQuarkusEntity> entityList;
private SimpleScore score;
@ValueRangeProvider(id = "valueRange")
@ProblemFactCollectionProperty
public List<String> getValueList() {
return valueList;
}
public void setValueList(List<String> valueList) {
this.valueList = valueList;
}
@PlanningEntityCollectionProperty
public List<TestdataQuarkusEntity> getEntityList() {
return entityList;
}
public void setEntityList(List<TestdataQuarkusEntity> entityList) {
this.entityList = entityList;
}
@PlanningScore
public SimpleScore getScore() {
return score;
}
public void setScore(SimpleScore score) {
this.score = score;
}
}
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_LIBCPP_PUSH_MACROS
#include <__undef_macros>
_LIBCPP_BEGIN_NAMESPACE_STD
#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_RANGES)
namespace ranges
{
// [range.range], ranges
template <class>
inline constexpr bool enable_borrowed_range = false;
} // namespace ranges
#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_RANGES)
_LIBCPP_END_NAMESPACE_STD
_LIBCPP_POP_MACROS
#endif // _LIBCPP___RANGES_ENABLE_BORROWED_RANGE_H
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/*
* // TODO
* possible optimizations:
* - calculate f as soon as g or h are set, so it will not have to be
* calculated each time it is retrieved
* - store nodes in openList sorted by their f value.
*/
package com.seventh_root.ld33.common.pathfinding;
import java.util.LinkedList;
import java.util.List;
/**
* This class represents a simple map.
* <p>
* It's width as well as hight can be set up on construction.
* The map can represent nodes that are walkable or not, it can be printed
* to sto, and it can calculate the shortest path between two nodes avoiding
* walkable nodes.
* <p>
* <p>
* Usage of this package:
* Create a node class which extends AbstractNode and implements the setHCosts
* method.
* Create a NodeFactory that implements the NodeFactory interface.
* Create Map instance with those created classes.
* <p>
*
* @see AbstractNode
* @see NodeFactory
* @version 1.0
* @param <T>
*/
public class Map<T extends AbstractNode> {
/** weather or not it is possible to walk diagonally on the map in general. */
protected static boolean CANMOVEDIAGONALY = true;
/** holds nodes. first dim represents x-, second y-axis. */
private T[][] nodes;
/** width + 1 is size of first dimension of nodes. */
protected int width;
/** height + 1 is size of second dimension of nodes. */
protected int height;
/** a Factory to create instances of specified nodes. */
private NodeFactory nodeFactory;
/**
* constructs a squared map with given width and hight.
* <p>
* The nodes will be instanciated througth the given nodeFactory.
*
* @param width
* @param height
* @param nodeFactory
*/
public Map(int width, int height, NodeFactory nodeFactory) {
// TODO check parameters. width and height should be > 0.
this.nodeFactory = nodeFactory;
nodes = (T[][]) new AbstractNode[width][height];
this.width = width - 1;
this.height = height - 1;
initEmptyNodes();
}
/**
* initializes all nodes. Their coordinates will be set correctly.
*/
private void initEmptyNodes() {
for (int i = 0; i <= width; i++) {
for (int j = 0; j <= height; j++) {
nodes[i][j] = (T) nodeFactory.createNode(i, j);
}
}
}
public boolean isWalkable(int x, int y) {
return nodes[x][y].isWalkable();
}
/**
* sets nodes walkable field at given coordinates to given value.
* <p>
* x/y must be bigger or equal to 0 and smaller or equal to width/hight.
*
* @param x
* @param y
* @param bool
*/
public void setWalkable(int x, int y, boolean bool) {
// TODO check parameter.
nodes[x][y].setWalkable(bool);
}
/**
* returns node at given coordinates.
* <p>
* x/y must be bigger or equal to 0 and smaller or equal to width/hight.
*
* @param x
* @param y
* @return node
*/
public final T getNode(int x, int y) {
// TODO check parameter.
return nodes[x][y];
}
/**
* prints map to sto. Feel free to override this method.
* <p>
* a player will be represented as "o", an unwakable terrain as "#".
* Movement penalty will not be displayed.
*/
public void drawMap() {
for (int i = 0; i <= width; i++) {
print(" _"); // boarder of map
}
print("\n");
for (int j = height; j >= 0; j--) {
print("|"); // boarder of map
for (int i = 0; i <= width; i++) {
if (nodes[i][j].isWalkable()) {
print(" ");
} else {
print(" #"); // draw unwakable
}
}
print("|\n"); // boarder of map
}
for (int i = 0; i <= width; i++) {
print(" _"); // boarder of map
}
}
/**
* prints something to sto.
*/
private void print(String s) {
System.out.print(s);
}
/* Variables and methodes for path finding */
// variables needed for path finding
/** list containing nodes not visited but adjacent to visited nodes. */
private List<T> openList;
/** list containing nodes already visited/taken care of. */
private List<T> closedList;
/** done finding path? */
private boolean done = false;
/**
* finds an allowed path from start to goal coordinates on this map.
* <p>
* This method uses the A* algorithm. The hCosts value is calculated in
* the given Node implementation.
* <p>
* This method will return a LinkedList containing the start node at the
* beginning followed by the calculated shortest allowed path ending
* with the end node.
* <p>
* If no allowed path exists, an empty list will be returned.
* <p>
* <p>
* x/y must be bigger or equal to 0 and smaller or equal to width/hight.
*
* @param oldX
* @param oldY
* @param newX
* @param newY
* @return
*/
public final List<T> findPath(int oldX, int oldY, int newX, int newY) {
// TODO check input
openList = new LinkedList<T>();
closedList = new LinkedList<T>();
openList.add(nodes[oldX][oldY]); // add starting node to open list
done = false;
T current;
while (!done) {
current = lowestFInOpen(); // get node with lowest fCosts from openList
closedList.add(current); // add current node to closed list
openList.remove(current); // delete current node from open list
if ((current.getX() == newX)
&& (current.getY() == newY)) { // found goal
return calcPath(nodes[oldX][oldY], current);
}
// for all adjacent nodes:
List<T> adjacentNodes = getAdjacent(current);
for (T currentAdj : adjacentNodes) {
if (!openList.contains(currentAdj)) { // node is not in openList
currentAdj.setPrevious(current); // set current node as previous for this node
currentAdj.setHCosts(nodes[newX][newY]); // set h costs of this node (estimated costs to goal)
currentAdj.setGCosts(current); // set g costs of this node (costs from start to this node)
openList.add(currentAdj); // add node to openList
} else { // node is in openList
if (currentAdj.getGCosts() > currentAdj.calculateGCosts(current)) { // costs from current node are cheaper than previous costs
currentAdj.setPrevious(current); // set current node as previous for this node
currentAdj.setGCosts(current); // set g costs of this node (costs from start to this node)
}
}
}
if (openList.isEmpty()) { // no path exists
return new LinkedList<T>(); // return empty list
}
}
return null; // unreachable
}
/**
* calculates the found path between two points according to
* their given <code>previousNode</code> field.
*
* @param start
* @param goal
* @return
*/
private List<T> calcPath(T start, T goal) {
// TODO if invalid nodes are given (eg cannot find from
// goal to start, this method will result in an infinite loop!)
LinkedList<T> path = new LinkedList<T>();
T curr = goal;
boolean done = false;
while (!done) {
path.addFirst(curr);
curr = (T) curr.getPrevious();
if (curr.equals(start)) {
done = true;
}
}
return path;
}
/**
* returns the node with the lowest fCosts.
*
* @return
*/
private T lowestFInOpen() {
// TODO currently, this is done by going through the whole openList!
T cheapest = openList.get(0);
for (T node : openList) {
if (node.getFCosts() < cheapest.getFCosts()) {
cheapest = node;
}
}
return cheapest;
}
/**
* returns a LinkedList with nodes adjacent to the given node.
* if those exist, are walkable and are not already in the closedList!
*/
private List<T> getAdjacent(T node) {
int x = node.getX();
int y = node.getY();
List<T> adj = new LinkedList<T>();
T temp;
if (x > 0) {
temp = this.getNode((x - 1), y);
if (temp.isWalkable() && !closedList.contains(temp)) {
adj.add(temp);
}
}
if (x < width) {
temp = this.getNode((x + 1), y);
if (temp.isWalkable() && !closedList.contains(temp)) {
adj.add(temp);
}
}
if (y > 0) {
temp = this.getNode(x, (y - 1));
if (temp.isWalkable() && !closedList.contains(temp)) {
adj.add(temp);
}
}
if (y < height) {
temp = this.getNode(x, (y + 1));
if (temp.isWalkable() && !closedList.contains(temp)) {
adj.add(temp);
}
}
return adj;
}
}
| {'content_hash': '5f279c4f0f1d6ed00b1eaa74145b4a76', 'timestamp': '', 'source': 'github', 'line_count': 304, 'max_line_length': 146, 'avg_line_length': 30.825657894736842, 'alnum_prop': 0.5461530252907907, 'repo_name': 'alyphen/ld33', 'id': 'ae47923bcaaf3fdc4327d093e4294f3de6db46a9', 'size': '9965', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'ld33-common/src/main/java/com/seventh_root/ld33/common/pathfinding/Map.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Java', 'bytes': '200477'}]} |
typename _VertexEvaluator,\
typename _vertex_id_type\
>
#define CGameLocationSelector CBaseLocationSelector<CGameGraph,_VertexEvaluator,_vertex_id_type>
TEMPLATE_SPECIALIZATION
IC CGameLocationSelector::CBaseLocationSelector (CRestrictedObject *object, CLocationManager *location_manager) :
inherited (object)
{
m_location_manager = location_manager;
VERIFY (location_manager);
}
TEMPLATE_SPECIALIZATION
IC CGameLocationSelector::~CBaseLocationSelector ()
{
}
TEMPLATE_SPECIALIZATION
IC void CGameLocationSelector::set_selection_type (const ESelectionType selection_type)
{
m_selection_type = selection_type;
}
TEMPLATE_SPECIALIZATION
IC void CGameLocationSelector::reinit (const CGameGraph *graph)
{
inherited::reinit (graph);
m_selection_type = eSelectionTypeRandomBranching;
if (graph)
graph->set_invalid_vertex (m_previous_vertex_id);
else
m_previous_vertex_id = GameGraph::_GRAPH_ID(-1);
}
TEMPLATE_SPECIALIZATION
IC void CGameLocationSelector::select_location (const _vertex_id_type start_vertex_id, _vertex_id_type &dest_vertex_id)
{
switch (m_selection_type) {
case eSelectionTypeMask : {
if (used())
perform_search (start_vertex_id);
else
m_failed = false;
break;
}
case eSelectionTypeRandomBranching : {
if (m_graph)
select_random_location(start_vertex_id,dest_vertex_id);
m_failed = m_failed && (start_vertex_id == dest_vertex_id);
break;
}
default : NODEFAULT;
}
}
TEMPLATE_SPECIALIZATION
IC void CGameLocationSelector::select_random_location(const _vertex_id_type start_vertex_id, _vertex_id_type &dest_vertex_id)
{
VERIFY (m_graph);
VERIFY (m_graph->valid_vertex_id(start_vertex_id));
if (!m_graph->valid_vertex_id(m_previous_vertex_id))
m_previous_vertex_id = GameGraph::_GRAPH_ID(start_vertex_id);
u32 branch_factor = 0;
const GameGraph::TERRAIN_VECTOR &vertex_types = m_location_manager->vertex_types();
GameGraph::TERRAIN_VECTOR::const_iterator B = vertex_types.begin(), I;
GameGraph::TERRAIN_VECTOR::const_iterator E = vertex_types.end();
_Graph::const_iterator i,e;
m_graph->begin (start_vertex_id,i,e);
for ( ; i != e; ++i) {
// * íå ñîîòâåòñòâóåò ïðåäûäåùåé âåðøèíå
if ((*i).vertex_id() == m_previous_vertex_id)
continue;
// * âåðøèíà íà òåêóùåì óðîâíå?
if ((m_graph->vertex((*i).vertex_id())->level_id() != ai().level_graph().level_id()))
continue;
// * accessible
if (!accessible((*i).vertex_id()))
continue;
const u8 *curr_types = m_graph->vertex((*i).vertex_id())->vertex_type();
// * ïîäõîäèò ïî ìàñêå
for (I = B; I != E; ++I)
if (m_graph->mask((*I).tMask,curr_types))
++branch_factor;
}
if (!branch_factor) {
if ((start_vertex_id != m_previous_vertex_id) && accessible(m_previous_vertex_id))
dest_vertex_id = m_previous_vertex_id;
else
dest_vertex_id = start_vertex_id;
}
else {
u32 choice = ::Random.randI(0,branch_factor);
branch_factor = 0;
bool found = false;
m_graph->begin (start_vertex_id,i,e);
for ( ; i != e; ++i) {
// * íå ñîîòâåòñòâóåò ïðåäûäåùåé âåðøèíå
if ((*i).vertex_id() == m_previous_vertex_id)
continue;
// * âåðøèíà íà òåêóùåì óðîâíå?
if ((m_graph->vertex((*i).vertex_id())->level_id() != ai().level_graph().level_id()))
continue;
// * accessible
if (!accessible((*i).vertex_id()))
continue;
const u8 *curr_types = m_graph->vertex((*i).vertex_id())->vertex_type();
// * ïîäõîäèò ïî ìàñêå
for (I = B; I != E; ++I)
if (m_graph->mask((*I).tMask,curr_types)) {
if (choice != branch_factor) {
++branch_factor;
continue;
}
dest_vertex_id = (*i).vertex_id();
found = true;
break;
}
if (found)
break;
}
}
m_previous_vertex_id = GameGraph::_GRAPH_ID(start_vertex_id);
}
TEMPLATE_SPECIALIZATION
IC void CGameLocationSelector::selection_type () const
{
return (m_selection_type);
}
TEMPLATE_SPECIALIZATION
IC bool CGameLocationSelector::actual (const _vertex_id_type start_vertex_id, bool path_completed)
{
if (m_selection_type != eSelectionTypeRandomBranching)
return (inherited::actual(start_vertex_id,path_completed));
return (!path_completed);
}
TEMPLATE_SPECIALIZATION
IC bool CGameLocationSelector::accessible (const _vertex_id_type vertex_id) const
{
return (m_restricted_object ? m_restricted_object->accessible(m_graph->vertex(vertex_id)->level_vertex_id()) : true);
}
#undef TEMPLATE_SPECIALIZATION
#undef CGameLocationSelector | {'content_hash': '063ca434eecef376233fcd83d757992c', 'timestamp': '', 'source': 'github', 'line_count': 163, 'max_line_length': 125, 'avg_line_length': 27.70552147239264, 'alnum_prop': 0.6740478299379983, 'repo_name': 'OLR-xray/XRay-NEW', 'id': '454024516b4e3c2bb3784c70baed14f9fd37b127', 'size': '4914', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'XRay/xr_3da/xrGame/game_location_selector_inline.h', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Assembly', 'bytes': '62738'}, {'name': 'Batchfile', 'bytes': '7939'}, {'name': 'C', 'bytes': '24706439'}, {'name': 'C++', 'bytes': '42161717'}, {'name': 'Groff', 'bytes': '287360'}, {'name': 'HTML', 'bytes': '67830'}, {'name': 'Lua', 'bytes': '96997'}, {'name': 'Makefile', 'bytes': '16534'}, {'name': 'Objective-C', 'bytes': '175957'}, {'name': 'Pascal', 'bytes': '1259032'}, {'name': 'Perl', 'bytes': '9355'}, {'name': 'PostScript', 'bytes': '115918'}, {'name': 'Shell', 'bytes': '962'}, {'name': 'TeX', 'bytes': '2421274'}, {'name': 'xBase', 'bytes': '99233'}]} |
<!--
~ Copyright 2013-2014 must-be.org
~
~ Licensed under the Apache License, Version 2.0 (the "License");
~ you may not use this file except in compliance with the License.
~ You may obtain a copy of the License at
~
~ http://www.apache.org/licenses/LICENSE-2.0
~
~ Unless required by applicable law or agreed to in writing, software
~ distributed under the License is distributed on an "AS IS" BASIS,
~ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
~ See the License for the specific language governing permissions and
~ limitations under the License.
-->
<assembly>
<version>\d.\d.\d.\d</version>
<class name="System.Xml.XmlNode">
<method name="SelectNodes">
<parameter type="System.String">
<attribute name="MustBe.Consulo.Attributes.InjectLanguageAttribute">
<argument type="System.String">XPath</argument>
</attribute>
</parameter>
</method>
<method name="SelectNodes">
<parameter type="System.String">
<attribute name="MustBe.Consulo.Attributes.InjectLanguageAttribute">
<argument type="System.String">XPath</argument>
</attribute>
</parameter>
<parameter type="System.Xml.XmlNamespaceManager" />
</method>
<method name="SelectSingleNode">
<parameter type="System.String">
<attribute name="MustBe.Consulo.Attributes.InjectLanguageAttribute">
<argument type="System.String">XPath</argument>
</attribute>
</parameter>
</method>
<method name="SelectSingleNode">
<parameter type="System.String">
<attribute name="MustBe.Consulo.Attributes.InjectLanguageAttribute">
<argument type="System.String">XPath</argument>
</attribute>
</parameter>
<parameter type="System.Xml.XmlNamespaceManager" />
</method>
</class>
</assembly> | {'content_hash': '4c0465496a3033df4de3e14654fdd907', 'timestamp': '', 'source': 'github', 'line_count': 52, 'max_line_length': 76, 'avg_line_length': 34.26923076923077, 'alnum_prop': 0.7081930415263749, 'repo_name': 'minhdu/consulo-unity3d', 'id': 'ffc86a3effa9833b529b66fa6c49807fb4ebc15f', 'size': '1782', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'dist/externalAttributes/any/System.Xml.xml', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Java', 'bytes': '416895'}, {'name': 'Lex', 'bytes': '2388'}]} |
<?xml version="1.0" encoding="utf-8"?>
<manifest xmlns:android="http://schemas.android.com/apk/res/android" android:versionCode="1" android:versionName="1.0" package="com.companyname.userauth">
<uses-sdk android:minSdkVersion="15" />
<application android:label="userAuth">
</application>
</manifest>
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import json
import logging
from os import environ, path
#------------------------------------------------------------------------------
# App logger
log = logging.getLogger(__name__)
#------------------------------------------------------------------------------
def _read_env():
""" Read environment variables from .env file and put the values in
``os.environ``. This won't overwrite existing ``os.environ`` values.
"""
envfile = path.join(path.dirname(__file__), '.env')
log.info('Reading %s ...', envfile)
with open(envfile) as fenv:
for line in fenv.readlines():
keyval = [ x.strip() for x in line.split('=') ]
if keyval and len(keyval) == 2:
key, val = keyval
val = environ.get(key) or val # Don't overwrite existing values
log.info('ENV: %s = %s', key, val)
environ[key] = val
_read_env()
#------------------------------------------------------------------------------
# Google App Engine disallows dynamically built responses because
# it wants to know the response content length upfront :(
ALLOW_STREAMING = environ['ALLOW_STREAMING']
# Readability API token (mandatory)
READABILITY_API_KEY = environ.get('READABILITY_API_KEY')
# Google Analytics tracking ID (optional)
GOOG_ANALYTICS_ID = environ.get('GOOG_ANALYTICS_ID')
#------------------------------------------------------------------------------
ERROR_UNDEFINED_READABILITY_KEY = '''
Readability API key is undefined. Please get your key at
https://www.readability.com/developers/api and set it either
as an environment variable (e.g., with ``export READABILITY_API_KEY=<Key>``)
or in ``app/.env`` file.
'''
WARN_UNDEFINED_GOOG_ANALYTICS_ID = '''
Google Tracking ID is undefined. If you want your site to be tracked by Google \
Analytics, please register and get a tracking ID at \
http://www.google.com/analytics. Then set it either as an environment variable \
(e.g., with ``export GOOG_ANALYTICS_ID=<ID>``) or in ``app/.env`` file.
'''
#------------------------------------------------------------------------------
class Settings(object):
"""Global app settings stored in a JSON file and in env vars.
"""
def __init__(self, filename='settings.json'):
self._settings = Settings._read_json_settings(filename)
allow_streaming = ALLOW_STREAMING.lower() not in ['false', '0']
current_version = self._settings['current_version']
# Current app version is preset by App Engine
GAE_CURRENT_VERSION_ID = environ.get('CURRENT_VERSION_ID')
if GAE_CURRENT_VERSION_ID is not None:
gae_version_norm = GAE_CURRENT_VERSION_ID.replace('-', '.')
current_version_norm = current_version.replace('-', '.')
if not gae_version_norm.startswith(current_version_norm):
raise ValueError(
"App version {} doesn't match GAE version {}".format(
current_version, GAE_CURRENT_VERSION_ID))
self._settings['current_version'] = GAE_CURRENT_VERSION_ID
self._settings['allow_streaming'] = allow_streaming
if not GOOG_ANALYTICS_ID:
log.warn(WARN_UNDEFINED_GOOG_ANALYTICS_ID.strip())
self._settings['goog_analytics_id'] = GOOG_ANALYTICS_ID
if not READABILITY_API_KEY:
raise ValueError(ERROR_UNDEFINED_READABILITY_KEY.strip())
self._settings['parsers']['Readability']['token'] = READABILITY_API_KEY
log.info('App settings: %r', self._settings)
@property
def app_version(self):
return self._settings['current_version']
def get(self, key, default=None):
return self.get(key, default)
def __getitem__(self, key):
return self._settings[key]
def __getattr__(self, name):
return self._settings[name]
@staticmethod
def _read_json_settings(filename):
fullpath = path.join(path.dirname(__file__), filename)
with open(fullpath) as fileobj:
settings = json.load(fileobj, 'utf-8')
return settings
# Global settings object
settings = Settings()
| {'content_hash': '3af384b2836127ef82f395fcecaf463f', 'timestamp': '', 'source': 'github', 'line_count': 129, 'max_line_length': 80, 'avg_line_length': 32.248062015503876, 'alnum_prop': 0.575, 'repo_name': 'the-happy-hippo/sprits-it', 'id': 'b96975b68fe7b07500ba1c640ecab80563b91405', 'size': '4184', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'app/settings.py', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '8471'}, {'name': 'JavaScript', 'bytes': '48917'}, {'name': 'Python', 'bytes': '31827'}]} |
package org.scalatestexamples
import org.scalatest.WordSpec
import org.scalatest.matchers.ShouldMatchers
import org.scalatestexamples.helpers.Stack
class StackShouldWordSpec extends WordSpec with StackFixtureCreationMethods with WordStackBehaviors with ShouldMatchers {
def it = afterWord("it")
"A Stack" when it {
"is empty" should {
"be empty" in {
assert(emptyStack.empty)
}
"complain on peek" in {
intercept[IllegalStateException] {
emptyStack.peek
}
}
"complain on pop" in {
intercept[IllegalStateException] {
emptyStack.pop
}
}
}
"has one item" should {
behave like nonEmptyStack(lastValuePushed)(stackWithOneItem)
behave like nonFullStack(stackWithOneItem)
}
"has one item less than capacity" should {
behave like nonEmptyStack(lastValuePushed)(stackWithOneItemLessThanCapacity)
behave like nonFullStack(stackWithOneItemLessThanCapacity)
}
"is full" should {
"be full" in {
assert(fullStack.full)
}
"go to sleep soon" in (pending)
behave like nonEmptyStack(lastValuePushed)(fullStack)
"complain on a push" in {
intercept[IllegalStateException] {
fullStack.push(10)
}
}
}
}
}
| {'content_hash': '3451a37755ca2e7ea9a18ac32df29f11', 'timestamp': '', 'source': 'github', 'line_count': 62, 'max_line_length': 121, 'avg_line_length': 21.548387096774192, 'alnum_prop': 0.6467065868263473, 'repo_name': 'kevinwright/scalatest', 'id': 'b724e358562462078ec152a41733daef14b78a89', 'size': '1936', 'binary': False, 'copies': '6', 'ref': 'refs/heads/master', 'path': 'src/examples/scala/org/scalatestexamples/StackShouldWordSpec.scala', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Java', 'bytes': '14653'}, {'name': 'Scala', 'bytes': '4074315'}, {'name': 'Shell', 'bytes': '100'}]} |
<html>
<body>
Reports classes that are directly or indirectly dependent on too many other classes.
<p>Modifications to any dependency of such a class may require changing the class thus making it prone to instability.</p>
<p>Only top-level classes are reported.</p>
<!-- tooltip end -->
<p>Use the <b>Maximum number of transitive dependencies</b> field to specify the maximum allowed number of direct or indirect dependencies
for a class.</p>
<p>Available only from <b>Code | Inspect Code</b> or
<b>Code | Analyze Code | Run Inspection by Name</b> and isn't reported in the editor.</p>
</body>
</html> | {'content_hash': 'a0f7d8b465ef36187ea7faae5920bfe6', 'timestamp': '', 'source': 'github', 'line_count': 12, 'max_line_length': 138, 'avg_line_length': 50.416666666666664, 'alnum_prop': 0.743801652892562, 'repo_name': 'GunoH/intellij-community', 'id': '753a988290d56d4d24ec23b8c852425dbbcf5f64', 'size': '605', 'binary': False, 'copies': '9', 'ref': 'refs/heads/master', 'path': 'plugins/InspectionGadgets/src/inspectionDescriptions/ClassWithTooManyTransitiveDependencies.html', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
#ifdef USE_TI_UISCROLLABLEVIEW
#import "TiUIView.h"
@interface TiUIScrollableView : TiUIView<UIScrollViewDelegate> {
@private
UIScrollView *scrollview;
UIPageControl *pageControl;
int currentPage; // Duplicate some info, just in case we're not showing the page control
BOOL showPageControl;
UIColor *pageControlBackgroundColor;
CGFloat pageControlHeight;
CGFloat pagingControlAlpha;
BOOL handlingPageControlEvent;
BOOL scrollingEnabled;
BOOL pagingControlOnTop;
BOOL overlayEnabled;
// Have to correct for an apple goof; rotation stops scrolling, AND doesn't move to the next page.
BOOL rotatedWhileScrolling;
// See the code for why we need this...
int lastPage;
BOOL enforceCacheRecalculation;
int cacheSize;
BOOL pageChanged;
}
#pragma mark - SimpleCalculator Internal Use Only
-(void)manageRotation;
-(UIScrollView*)scrollview;
-(void)refreshScrollView:(CGRect)visibleBounds readd:(BOOL)readd;
-(void)setCurrentPage:(id)page animated:(NSNumber*)animate;
-(void)addView:(id)viewproxy;
-(void)removeView:(id)args;
@end
#endif | {'content_hash': 'ae8227a6736e9ab85125f47d010ee47f', 'timestamp': '', 'source': 'github', 'line_count': 38, 'max_line_length': 102, 'avg_line_length': 28.526315789473685, 'alnum_prop': 0.7675276752767528, 'repo_name': 'felicitia/SimpleCalculator-Prism-JS', 'id': 'cc6f7eb2b3d097117ac9dc973927570c40872f98', 'size': '1406', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'build/iphone/Classes/TiUIScrollableView.h', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'C', 'bytes': '145776'}, {'name': 'C++', 'bytes': '58724'}, {'name': 'CSS', 'bytes': '1276'}, {'name': 'D', 'bytes': '868851'}, {'name': 'Java', 'bytes': '536720'}, {'name': 'JavaScript', 'bytes': '45783'}, {'name': 'Objective-C', 'bytes': '3314359'}, {'name': 'Objective-C++', 'bytes': '18015'}, {'name': 'Shell', 'bytes': '1272'}]} |
namespace swift {
class ClassDecl;
class DeclContext;
class DeclName;
class DeclNameRef;
class DestructorDecl;
class GenericContext;
class GenericParamList;
class LookupResult;
enum class NLKind;
class SourceLoc;
class TypeAliasDecl;
class TypeDecl;
enum class UnqualifiedLookupFlags;
namespace ast_scope {
class ASTScopeImpl;
class ScopeCreator;
} // namespace ast_scope
namespace namelookup {
enum class ResolutionKind;
} // namespace namelookup
/// Display a nominal type or extension thereof.
void simple_display(
llvm::raw_ostream &out,
const llvm::PointerUnion<const TypeDecl *, const ExtensionDecl *> &value);
/// Describes a set of type declarations that are "direct" referenced by
/// a particular type in the AST.
using DirectlyReferencedTypeDecls = llvm::TinyPtrVector<TypeDecl *>;
/// Request the set of declarations directly referenced by the an "inherited"
/// type of a type or extension declaration.
///
/// This request retrieves the set of declarations that are directly referenced
/// by a particular type in the "inherited" clause of a type or extension
/// declaration. For example:
///
/// \code
/// protocol P { }
/// protocol Q { }
/// typealias Alias = P & Q
/// class C { }
///
/// class D: C, Alias { }
/// \endcode
///
/// The inherited declaration of \c D at index 0 is the class declaration C.
/// The inherited declaration of \c D at index 1 is the typealias Alias.
class InheritedDeclsReferencedRequest
: public SimpleRequest<
InheritedDeclsReferencedRequest,
DirectlyReferencedTypeDecls(
llvm::PointerUnion<const TypeDecl *, const ExtensionDecl *>,
unsigned),
RequestFlags::Uncached> // FIXME: Cache these
{
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
DirectlyReferencedTypeDecls
evaluate(Evaluator &evaluator,
llvm::PointerUnion<const TypeDecl *, const ExtensionDecl *> decl,
unsigned index) const;
public:
// Caching
bool isCached() const { return true; }
// Source location information.
SourceLoc getNearestLoc() const;
};
/// Request the set of declarations directly referenced by the underlying
/// type of a typealias.
///
/// This request retrieves the set of type declarations that directly referenced
/// by the underlying type of a typealias. For example:
///
/// \code
/// protocol P { }
/// protocol Q { }
/// class C { }
/// typealias PQ = P & Q
/// typealias Alias = C & PQ
/// \endcode
///
/// The set of declarations referenced by the underlying type of \c PQ
/// contains both \c P and \c Q.
/// The set of declarations referenced by the underlying type of \c Alias
/// contains \c C and \c PQ. Clients can choose to look further into \c PQ
/// using another instance of this request.
class UnderlyingTypeDeclsReferencedRequest :
public SimpleRequest<UnderlyingTypeDeclsReferencedRequest,
DirectlyReferencedTypeDecls(TypeAliasDecl *),
RequestFlags::Uncached> // FIXME: Cache these
{
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
DirectlyReferencedTypeDecls evaluate(
Evaluator &evaluator,
TypeAliasDecl *typealias) const;
public:
// Caching
bool isCached() const { return true; }
};
/// Request the superclass declaration for the given class.
class SuperclassDeclRequest :
public SimpleRequest<SuperclassDeclRequest,
ClassDecl *(NominalTypeDecl *),
RequestFlags::SeparatelyCached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
ClassDecl *
evaluate(Evaluator &evaluator, NominalTypeDecl *subject) const;
public:
// Caching
bool isCached() const { return true; }
Optional<ClassDecl *> getCachedResult() const;
void cacheResult(ClassDecl *value) const;
};
class InheritedProtocolsRequest
: public SimpleRequest<
InheritedProtocolsRequest, ArrayRef<ProtocolDecl *>(ProtocolDecl *),
RequestFlags::SeparatelyCached | RequestFlags::DependencySink |
RequestFlags::DependencySource> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
ArrayRef<ProtocolDecl *>
evaluate(Evaluator &evaluator, ProtocolDecl *PD) const;
public:
// Caching
bool isCached() const { return true; }
Optional<ArrayRef<ProtocolDecl *>> getCachedResult() const;
void cacheResult(ArrayRef<ProtocolDecl *> value) const;
public:
// Incremental dependencies
evaluator::DependencySource
readDependencySource(const evaluator::DependencyRecorder &e) const;
void writeDependencySink(evaluator::DependencyCollector &tracker,
ArrayRef<ProtocolDecl *> result) const;
};
/// Requests whether or not this class has designated initializers that are
/// not public or @usableFromInline.
class HasMissingDesignatedInitializersRequest :
public SimpleRequest<HasMissingDesignatedInitializersRequest,
bool(ClassDecl *),
RequestFlags::SeparatelyCached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
bool
evaluate(Evaluator &evaluator, ClassDecl *subject) const;
public:
// Caching
bool isCached() const { return true; }
Optional<bool> getCachedResult() const;
void cacheResult(bool) const;
};
/// Request the nominal declaration extended by a given extension declaration.
class ExtendedNominalRequest
: public SimpleRequest<
ExtendedNominalRequest, NominalTypeDecl *(ExtensionDecl *),
RequestFlags::SeparatelyCached | RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
NominalTypeDecl *
evaluate(Evaluator &evaluator, ExtensionDecl *ext) const;
public:
// Separate caching.
bool isCached() const { return true; }
Optional<NominalTypeDecl *> getCachedResult() const;
void cacheResult(NominalTypeDecl *value) const;
public:
// Incremental dependencies
void writeDependencySink(evaluator::DependencyCollector &tracker,
NominalTypeDecl *result) const;
};
struct SelfBounds {
llvm::TinyPtrVector<NominalTypeDecl *> decls;
bool anyObject = false;
};
/// Request the nominal types that occur as the right-hand side of "Self: Foo"
/// constraints in the "where" clause of a protocol extension.
class SelfBoundsFromWhereClauseRequest
: public SimpleRequest<SelfBoundsFromWhereClauseRequest,
SelfBounds(llvm::PointerUnion<
const TypeDecl *, const ExtensionDecl *>),
RequestFlags::Uncached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
SelfBounds
evaluate(Evaluator &evaluator,
llvm::PointerUnion<const TypeDecl *, const ExtensionDecl *>) const;
};
/// Request all type aliases and nominal types that appear in the "where"
/// clause of an extension.
class TypeDeclsFromWhereClauseRequest :
public SimpleRequest<TypeDeclsFromWhereClauseRequest,
DirectlyReferencedTypeDecls(ExtensionDecl *),
RequestFlags::Uncached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
DirectlyReferencedTypeDecls evaluate(Evaluator &evaluator,
ExtensionDecl *ext) const;
};
/// Request the nominal type declaration to which the given custom attribute
/// refers.
class CustomAttrNominalRequest :
public SimpleRequest<CustomAttrNominalRequest,
NominalTypeDecl *(CustomAttr *, DeclContext *),
RequestFlags::Cached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
NominalTypeDecl *
evaluate(Evaluator &evaluator, CustomAttr *attr, DeclContext *dc) const;
public:
// Caching
bool isCached() const { return true; }
};
/// Finds or synthesizes a destructor for the given class.
class GetDestructorRequest
: public SimpleRequest<GetDestructorRequest, DestructorDecl *(ClassDecl *),
RequestFlags::SeparatelyCached |
RequestFlags::DependencySource> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
DestructorDecl *
evaluate(Evaluator &evaluator, ClassDecl *classDecl) const;
public:
// Caching
bool isCached() const { return true; }
Optional<DestructorDecl *> getCachedResult() const;
void cacheResult(DestructorDecl *value) const;
public:
// Incremental dependencies.
evaluator::DependencySource
readDependencySource(const evaluator::DependencyRecorder &) const;
};
class GenericParamListRequest :
public SimpleRequest<GenericParamListRequest,
GenericParamList *(GenericContext *),
RequestFlags::SeparatelyCached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
GenericParamList *
evaluate(Evaluator &evaluator, GenericContext *value) const;
public:
// Separate caching.
bool isCached() const { return true; }
Optional<GenericParamList *> getCachedResult() const;
void cacheResult(GenericParamList *value) const;
};
/// Expand the given ASTScope. Requestified to detect recursion.
class ExpandASTScopeRequest
: public SimpleRequest<ExpandASTScopeRequest,
ast_scope::ASTScopeImpl *(ast_scope::ASTScopeImpl *,
ast_scope::ScopeCreator *),
RequestFlags::SeparatelyCached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
ast_scope::ASTScopeImpl *
evaluate(Evaluator &evaluator, ast_scope::ASTScopeImpl *,
ast_scope::ScopeCreator *) const;
public:
// Separate caching.
bool isCached() const;
Optional<ast_scope::ASTScopeImpl *> getCachedResult() const;
void cacheResult(ast_scope::ASTScopeImpl *) const {}
};
/// The input type for an unqualified lookup request.
class UnqualifiedLookupDescriptor {
using LookupOptions = OptionSet<UnqualifiedLookupFlags>;
public:
DeclNameRef Name;
DeclContext *DC;
SourceLoc Loc;
LookupOptions Options;
UnqualifiedLookupDescriptor(DeclNameRef name, DeclContext *dc,
SourceLoc loc = SourceLoc(),
LookupOptions options = {})
: Name(name), DC(dc), Loc(loc), Options(options) { }
friend llvm::hash_code hash_value(const UnqualifiedLookupDescriptor &desc) {
return llvm::hash_combine(desc.Name, desc.DC, desc.Loc,
desc.Options.toRaw());
}
friend bool operator==(const UnqualifiedLookupDescriptor &lhs,
const UnqualifiedLookupDescriptor &rhs) {
return lhs.Name == rhs.Name && lhs.DC == rhs.DC && lhs.Loc == rhs.Loc &&
lhs.Options.toRaw() == rhs.Options.toRaw();
}
friend bool operator!=(const UnqualifiedLookupDescriptor &lhs,
const UnqualifiedLookupDescriptor &rhs) {
return !(lhs == rhs);
}
};
void simple_display(llvm::raw_ostream &out,
const UnqualifiedLookupDescriptor &desc);
SourceLoc extractNearestSourceLoc(const UnqualifiedLookupDescriptor &desc);
/// Performs unqualified lookup for a DeclName from a given context.
class UnqualifiedLookupRequest
: public SimpleRequest<UnqualifiedLookupRequest,
LookupResult(UnqualifiedLookupDescriptor),
RequestFlags::Uncached | RequestFlags::DependencySource |
RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
LookupResult evaluate(Evaluator &evaluator,
UnqualifiedLookupDescriptor desc) const;
public:
// Incremental dependencies
evaluator::DependencySource
readDependencySource(const evaluator::DependencyRecorder &) const;
void writeDependencySink(evaluator::DependencyCollector &tracker,
LookupResult res) const;
};
using QualifiedLookupResult = SmallVector<ValueDecl *, 4>;
/// Performs a lookup into a given module and its imports.
class LookupInModuleRequest
: public SimpleRequest<LookupInModuleRequest,
QualifiedLookupResult(
const DeclContext *, DeclName, NLKind,
namelookup::ResolutionKind, const DeclContext *),
RequestFlags::Uncached | RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
QualifiedLookupResult
evaluate(Evaluator &evaluator, const DeclContext *moduleOrFile, DeclName name,
NLKind lookupKind, namelookup::ResolutionKind resolutionKind,
const DeclContext *moduleScopeContext) const;
public:
// Incremental dependencies
void writeDependencySink(evaluator::DependencyCollector &tracker,
QualifiedLookupResult l) const;
};
/// Perform \c AnyObject lookup for a given member.
class AnyObjectLookupRequest
: public SimpleRequest<AnyObjectLookupRequest,
QualifiedLookupResult(const DeclContext *,
DeclNameRef, NLOptions),
RequestFlags::Uncached | RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
QualifiedLookupResult evaluate(Evaluator &evaluator,
const DeclContext *dc,
DeclNameRef name,
NLOptions options) const;
public:
// Incremental dependencies
void writeDependencySink(evaluator::DependencyCollector &tracker,
QualifiedLookupResult l) const;
};
class ModuleQualifiedLookupRequest
: public SimpleRequest<ModuleQualifiedLookupRequest,
QualifiedLookupResult(const DeclContext *,
ModuleDecl *, DeclNameRef,
NLOptions),
RequestFlags::Uncached | RequestFlags::DependencySource |
RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
QualifiedLookupResult evaluate(Evaluator &evaluator,
const DeclContext *DC,
ModuleDecl *mod, DeclNameRef name,
NLOptions opts) const;
public:
// Incremental dependencies
evaluator::DependencySource
readDependencySource(const evaluator::DependencyRecorder &) const;
void writeDependencySink(evaluator::DependencyCollector &tracker,
QualifiedLookupResult lookupResult) const;
};
class QualifiedLookupRequest
: public SimpleRequest<QualifiedLookupRequest,
QualifiedLookupResult(const DeclContext *,
SmallVector<NominalTypeDecl *, 4>,
DeclNameRef, NLOptions),
RequestFlags::Uncached | RequestFlags::DependencySource> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
QualifiedLookupResult
evaluate(Evaluator &evaluator, const DeclContext *DC,
SmallVector<NominalTypeDecl *, 4> decls,
DeclNameRef name,
NLOptions opts) const;
public:
// Incremental dependencies.
evaluator::DependencySource
readDependencySource(const evaluator::DependencyRecorder &) const;
};
/// The input type for a direct lookup request.
class DirectLookupDescriptor final {
using LookupOptions = OptionSet<NominalTypeDecl::LookupDirectFlags>;
public:
NominalTypeDecl *DC;
DeclName Name;
LookupOptions Options;
DirectLookupDescriptor(NominalTypeDecl *dc, DeclName name,
LookupOptions options = {})
: DC(dc), Name(name), Options(options) {}
friend llvm::hash_code hash_value(const DirectLookupDescriptor &desc) {
return llvm::hash_combine(desc.Name, desc.DC, desc.Options.toRaw());
}
friend bool operator==(const DirectLookupDescriptor &lhs,
const DirectLookupDescriptor &rhs) {
return lhs.Name == rhs.Name && lhs.DC == rhs.DC &&
lhs.Options.toRaw() == rhs.Options.toRaw();
}
friend bool operator!=(const DirectLookupDescriptor &lhs,
const DirectLookupDescriptor &rhs) {
return !(lhs == rhs);
}
};
void simple_display(llvm::raw_ostream &out, const DirectLookupDescriptor &desc);
SourceLoc extractNearestSourceLoc(const DirectLookupDescriptor &desc);
class DirectLookupRequest
: public SimpleRequest<DirectLookupRequest,
TinyPtrVector<ValueDecl *>(DirectLookupDescriptor),
RequestFlags::Uncached|RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
TinyPtrVector<ValueDecl *>
evaluate(Evaluator &evaluator, DirectLookupDescriptor desc) const;
public:
// Incremental dependencies
void writeDependencySink(evaluator::DependencyCollector &tracker,
TinyPtrVector<ValueDecl *> result) const;
};
class OperatorLookupDescriptor final {
public:
using Storage = llvm::PointerUnion<FileUnit *, ModuleDecl *>;
Storage fileOrModule;
Identifier name;
private:
OperatorLookupDescriptor(Storage fileOrModule, Identifier name)
: fileOrModule(fileOrModule), name(name) {}
public:
/// Retrieves the files to perform lookup in.
ArrayRef<FileUnit *> getFiles() const;
/// If this is for a module lookup, returns the module. Otherwise returns
/// \c nullptr.
ModuleDecl *getModule() const {
return fileOrModule.dyn_cast<ModuleDecl *>();
}
/// Retrieve the file or module for the lookup, as a DeclContext.
DeclContext *getDC() const {
if (auto *module = getModule())
return module;
return fileOrModule.get<FileUnit *>();
}
friend llvm::hash_code hash_value(const OperatorLookupDescriptor &desc) {
return llvm::hash_combine(desc.fileOrModule, desc.name);
}
friend bool operator==(const OperatorLookupDescriptor &lhs,
const OperatorLookupDescriptor &rhs) {
return lhs.fileOrModule == rhs.fileOrModule && lhs.name == rhs.name;
}
friend bool operator!=(const OperatorLookupDescriptor &lhs,
const OperatorLookupDescriptor &rhs) {
return !(lhs == rhs);
}
static OperatorLookupDescriptor forFile(FileUnit *file, Identifier name) {
return OperatorLookupDescriptor(file, name);
}
static OperatorLookupDescriptor forModule(ModuleDecl *mod, Identifier name) {
return OperatorLookupDescriptor(mod, name);
}
static OperatorLookupDescriptor forDC(const DeclContext *DC, Identifier name);
};
void simple_display(llvm::raw_ostream &out,
const OperatorLookupDescriptor &desc);
SourceLoc extractNearestSourceLoc(const OperatorLookupDescriptor &desc);
/// Looks up an operator in a given file or module without looking through
/// imports.
class DirectOperatorLookupRequest
: public SimpleRequest<DirectOperatorLookupRequest,
TinyPtrVector<OperatorDecl *>(
OperatorLookupDescriptor, OperatorFixity),
RequestFlags::Uncached |
RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
TinyPtrVector<OperatorDecl *>
evaluate(Evaluator &evaluator, OperatorLookupDescriptor descriptor,
OperatorFixity fixity) const;
public:
// Incremental dependencies.
void writeDependencySink(evaluator::DependencyCollector &tracker,
TinyPtrVector<OperatorDecl *> ops) const;
};
/// Looks up an precedencegroup in a given file or module without looking
/// through imports.
class DirectPrecedenceGroupLookupRequest
: public SimpleRequest<DirectPrecedenceGroupLookupRequest,
TinyPtrVector<PrecedenceGroupDecl *>(
OperatorLookupDescriptor),
RequestFlags::Uncached |
RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
TinyPtrVector<PrecedenceGroupDecl *>
evaluate(Evaluator &evaluator, OperatorLookupDescriptor descriptor) const;
public:
// Incremental dependencies.
void writeDependencySink(evaluator::DependencyCollector &tracker,
TinyPtrVector<PrecedenceGroupDecl *> groups) const;
};
class LookupConformanceDescriptor final {
public:
ModuleDecl *Mod;
Type Ty;
ProtocolDecl *PD;
LookupConformanceDescriptor(ModuleDecl *Mod, Type Ty, ProtocolDecl *PD)
: Mod(Mod), Ty(Ty), PD(PD) {}
friend llvm::hash_code hash_value(const LookupConformanceDescriptor &desc) {
return llvm::hash_combine(desc.Mod, desc.Ty.getPointer(), desc.PD);
}
friend bool operator==(const LookupConformanceDescriptor &lhs,
const LookupConformanceDescriptor &rhs) {
return lhs.Mod == rhs.Mod && lhs.Ty.getPointer() == rhs.Ty.getPointer() &&
lhs.PD == rhs.PD;
}
friend bool operator!=(const LookupConformanceDescriptor &lhs,
const LookupConformanceDescriptor &rhs) {
return !(lhs == rhs);
}
};
void simple_display(llvm::raw_ostream &out,
const LookupConformanceDescriptor &desc);
SourceLoc extractNearestSourceLoc(const LookupConformanceDescriptor &desc);
class LookupConformanceInModuleRequest
: public SimpleRequest<LookupConformanceInModuleRequest,
ProtocolConformanceRef(LookupConformanceDescriptor),
RequestFlags::Uncached|RequestFlags::DependencySink> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
// Evaluation.
ProtocolConformanceRef evaluate(
Evaluator &evaluator, LookupConformanceDescriptor desc) const;
public:
// Incremental dependencies
void writeDependencySink(evaluator::DependencyCollector &tracker,
ProtocolConformanceRef result) const;
};
/// Look up an 'infix operator' decl by name.
class LookupInfixOperatorRequest
: public SimpleRequest<LookupInfixOperatorRequest,
TinyPtrVector<InfixOperatorDecl *>(
OperatorLookupDescriptor),
RequestFlags::Cached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
TinyPtrVector<InfixOperatorDecl *>
evaluate(Evaluator &evaluator, OperatorLookupDescriptor desc) const;
public:
// Cached.
bool isCached() const { return true; }
};
/// Look up an 'prefix operator' decl by name.
class LookupPrefixOperatorRequest
: public SimpleRequest<LookupPrefixOperatorRequest,
PrefixOperatorDecl *(OperatorLookupDescriptor),
RequestFlags::Cached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
PrefixOperatorDecl *evaluate(Evaluator &evaluator,
OperatorLookupDescriptor desc) const;
public:
// Cached.
bool isCached() const { return true; }
};
/// Look up an 'postfix operator' decl by name.
class LookupPostfixOperatorRequest
: public SimpleRequest<LookupPostfixOperatorRequest,
PostfixOperatorDecl *(OperatorLookupDescriptor),
RequestFlags::Cached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
PostfixOperatorDecl *evaluate(Evaluator &evaluator,
OperatorLookupDescriptor desc) const;
public:
// Cached.
bool isCached() const { return true; }
};
/// Look up a precedencegroup decl by name.
class LookupPrecedenceGroupRequest
: public SimpleRequest<LookupPrecedenceGroupRequest,
TinyPtrVector<PrecedenceGroupDecl *>(
OperatorLookupDescriptor),
RequestFlags::Cached> {
public:
using SimpleRequest::SimpleRequest;
private:
friend SimpleRequest;
TinyPtrVector<PrecedenceGroupDecl *>
evaluate(Evaluator &evaluator, OperatorLookupDescriptor descriptor) const;
public:
// Cached.
bool isCached() const { return true; }
};
#define SWIFT_TYPEID_ZONE NameLookup
#define SWIFT_TYPEID_HEADER "swift/AST/NameLookupTypeIDZone.def"
#include "swift/Basic/DefineTypeIDZone.h"
#undef SWIFT_TYPEID_ZONE
#undef SWIFT_TYPEID_HEADER
// Set up reporting of evaluated requests.
template<typename Request>
void reportEvaluatedRequest(UnifiedStatsReporter &stats,
const Request &request);
#define SWIFT_REQUEST(Zone, RequestType, Sig, Caching, LocOptions) \
template <> \
inline void reportEvaluatedRequest(UnifiedStatsReporter &stats, \
const RequestType &request) { \
++stats.getFrontendCounters().RequestType; \
}
#include "swift/AST/NameLookupTypeIDZone.def"
#undef SWIFT_REQUEST
} // end namespace swift
#endif // SWIFT_NAME_LOOKUP_REQUESTS
| {'content_hash': '95774257026e57b6bdbf708f7b1a8114', 'timestamp': '', 'source': 'github', 'line_count': 824, 'max_line_length': 85, 'avg_line_length': 31.557038834951456, 'alnum_prop': 0.6740760681459832, 'repo_name': 'allevato/swift', 'id': 'b1433f82767dc9ae601a069e91148138f97e9d7d', 'size': '27046', 'binary': False, 'copies': '4', 'ref': 'refs/heads/master', 'path': 'include/swift/AST/NameLookupRequests.h', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '13584'}, {'name': 'C', 'bytes': '272029'}, {'name': 'C++', 'bytes': '38686827'}, {'name': 'CMake', 'bytes': '556052'}, {'name': 'D', 'bytes': '1107'}, {'name': 'DTrace', 'bytes': '2593'}, {'name': 'Emacs Lisp', 'bytes': '57338'}, {'name': 'LLVM', 'bytes': '70652'}, {'name': 'MATLAB', 'bytes': '2576'}, {'name': 'Makefile', 'bytes': '1841'}, {'name': 'Objective-C', 'bytes': '427480'}, {'name': 'Objective-C++', 'bytes': '243545'}, {'name': 'Python', 'bytes': '1788396'}, {'name': 'Roff', 'bytes': '3495'}, {'name': 'Ruby', 'bytes': '2117'}, {'name': 'Shell', 'bytes': '179656'}, {'name': 'Swift', 'bytes': '33700469'}, {'name': 'Vim Script', 'bytes': '19900'}, {'name': 'sed', 'bytes': '1050'}]} |
require 'json'
def getCreds
begin
return JSON.parse(File.read('.creds'))
rescue StandardError=>e
return e
end
end
| {'content_hash': '61dc5ece55a8b989b11788bbc8a8c9fb', 'timestamp': '', 'source': 'github', 'line_count': 8, 'max_line_length': 40, 'avg_line_length': 15.125, 'alnum_prop': 0.7272727272727273, 'repo_name': 'rubrik-devops/ruby-bits', 'id': 'bbc959c8baee0c9e258c43796d26aa5fdda8c4c9', 'size': '416', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'lib/getCreds.rb', 'mode': '33261', 'license': 'mit', 'language': [{'name': 'Ruby', 'bytes': '63351'}]} |
package org.apache.hadoop.hbase.client;
import java.io.IOException;
import java.io.InterruptedIOException;
import java.net.SocketTimeoutException;
import java.util.ArrayList;
import java.util.Arrays;
import java.util.HashMap;
import java.util.LinkedList;
import java.util.List;
import java.util.Map;
import java.util.Map.Entry;
import java.util.concurrent.atomic.AtomicInteger;
import java.util.concurrent.atomic.AtomicReference;
import java.util.regex.Pattern;
import org.apache.commons.logging.Log;
import org.apache.commons.logging.LogFactory;
import org.apache.hadoop.conf.Configuration;
import org.apache.hadoop.hbase.Abortable;
import org.apache.hadoop.hbase.ClusterStatus;
import org.apache.hadoop.hbase.DoNotRetryIOException;
import org.apache.hadoop.hbase.HBaseConfiguration;
import org.apache.hadoop.hbase.HColumnDescriptor;
import org.apache.hadoop.hbase.HConstants;
import org.apache.hadoop.hbase.HRegionInfo;
import org.apache.hadoop.hbase.HRegionLocation;
import org.apache.hadoop.hbase.HTableDescriptor;
import org.apache.hadoop.hbase.MasterNotRunningException;
import org.apache.hadoop.hbase.MetaTableAccessor;
import org.apache.hadoop.hbase.NamespaceDescriptor;
import org.apache.hadoop.hbase.NotServingRegionException;
import org.apache.hadoop.hbase.RegionException;
import org.apache.hadoop.hbase.RegionLocations;
import org.apache.hadoop.hbase.ServerName;
import org.apache.hadoop.hbase.TableExistsException;
import org.apache.hadoop.hbase.TableName;
import org.apache.hadoop.hbase.TableNotDisabledException;
import org.apache.hadoop.hbase.TableNotEnabledException;
import org.apache.hadoop.hbase.TableNotFoundException;
import org.apache.hadoop.hbase.UnknownRegionException;
import org.apache.hadoop.hbase.ZooKeeperConnectionException;
import org.apache.hadoop.hbase.classification.InterfaceAudience;
import org.apache.hadoop.hbase.classification.InterfaceStability;
import org.apache.hadoop.hbase.client.MetaScanner.MetaScannerVisitor;
import org.apache.hadoop.hbase.client.MetaScanner.MetaScannerVisitorBase;
import org.apache.hadoop.hbase.exceptions.DeserializationException;
import org.apache.hadoop.hbase.ipc.CoprocessorRpcChannel;
import org.apache.hadoop.hbase.ipc.MasterCoprocessorRpcChannel;
import org.apache.hadoop.hbase.ipc.RegionServerCoprocessorRpcChannel;
import org.apache.hadoop.hbase.protobuf.ProtobufUtil;
import org.apache.hadoop.hbase.protobuf.RequestConverter;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.AdminService;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.CloseRegionRequest;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.CloseRegionResponse;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.CompactRegionRequest;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.FlushRegionRequest;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.GetRegionInfoRequest;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.GetRegionInfoResponse;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.GetRegionInfoResponse.CompactionState;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.RollWALWriterRequest;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.RollWALWriterResponse;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.StopServerRequest;
import org.apache.hadoop.hbase.protobuf.generated.AdminProtos.UpdateConfigurationRequest;
import org.apache.hadoop.hbase.protobuf.generated.HBaseProtos;
import org.apache.hadoop.hbase.protobuf.generated.HBaseProtos.NameStringPair;
import org.apache.hadoop.hbase.protobuf.generated.HBaseProtos.ProcedureDescription;
import org.apache.hadoop.hbase.protobuf.generated.HBaseProtos.SnapshotDescription;
import org.apache.hadoop.hbase.protobuf.generated.HBaseProtos.TableSchema;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.AddColumnRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.AssignRegionRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.CreateNamespaceRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.CreateTableRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.DeleteColumnRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.DeleteNamespaceRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.DeleteSnapshotRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.DeleteTableRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.DisableTableRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.DispatchMergingRegionsRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.EnableTableRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ExecProcedureRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ExecProcedureResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetClusterStatusRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetCompletedSnapshotsRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetNamespaceDescriptorRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetSchemaAlterStatusRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetSchemaAlterStatusResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetTableDescriptorsRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetTableDescriptorsResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.GetTableNamesRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.IsProcedureDoneRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.IsProcedureDoneResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.IsRestoreSnapshotDoneRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.IsRestoreSnapshotDoneResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.IsSnapshotDoneRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.IsSnapshotDoneResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ListNamespaceDescriptorsRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ListTableDescriptorsByNamespaceRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ListTableNamesByNamespaceRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ModifyColumnRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ModifyNamespaceRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ModifyTableRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.MoveRegionRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.RestoreSnapshotRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.RestoreSnapshotResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.SetBalancerRunningRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.ShutdownRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.SnapshotRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.SnapshotResponse;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.StopMasterRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.TruncateTableRequest;
import org.apache.hadoop.hbase.protobuf.generated.MasterProtos.UnassignRegionRequest;
import org.apache.hadoop.hbase.quotas.QuotaFilter;
import org.apache.hadoop.hbase.quotas.QuotaRetriever;
import org.apache.hadoop.hbase.quotas.QuotaSettings;
import org.apache.hadoop.hbase.regionserver.wal.FailedLogCloseException;
import org.apache.hadoop.hbase.snapshot.ClientSnapshotDescriptionUtils;
import org.apache.hadoop.hbase.snapshot.HBaseSnapshotException;
import org.apache.hadoop.hbase.snapshot.RestoreSnapshotException;
import org.apache.hadoop.hbase.snapshot.SnapshotCreationException;
import org.apache.hadoop.hbase.snapshot.UnknownSnapshotException;
import org.apache.hadoop.hbase.util.Addressing;
import org.apache.hadoop.hbase.util.Bytes;
import org.apache.hadoop.hbase.util.EnvironmentEdgeManager;
import org.apache.hadoop.hbase.util.Pair;
import org.apache.hadoop.hbase.zookeeper.MasterAddressTracker;
import org.apache.hadoop.hbase.zookeeper.MetaTableLocator;
import org.apache.hadoop.hbase.zookeeper.ZooKeeperWatcher;
import org.apache.hadoop.ipc.RemoteException;
import org.apache.hadoop.util.StringUtils;
import org.apache.zookeeper.KeeperException;
import com.google.common.annotations.VisibleForTesting;
import com.google.protobuf.ByteString;
import com.google.protobuf.ServiceException;
/**
* HBaseAdmin is no longer a client API. It is marked InterfaceAudience.Private indicating that
* this is an HBase-internal class as defined in
* https://hadoop.apache.org/docs/current/hadoop-project-dist/hadoop-common/InterfaceClassification.html
* There are no guarantees for backwards source / binary compatibility and methods or class can
* change or go away without deprecation.
* Use {@link Connection#getAdmin()} to obtain an instance of {@link Admin} instead of constructing
* an HBaseAdmin directly.
*
* <p>Connection should be an <i>unmanaged</i> connection obtained via
* {@link ConnectionFactory#createConnection(Configuration)}
*
* @see ConnectionFactory
* @see Connection
* @see Admin
*/
@InterfaceAudience.Private
@InterfaceStability.Evolving
public class HBaseAdmin implements Admin {
private static final Log LOG = LogFactory.getLog(HBaseAdmin.class);
private static final String ZK_IDENTIFIER_PREFIX = "hbase-admin-on-";
private ClusterConnection connection;
private volatile Configuration conf;
private final long pause;
private final int numRetries;
// Some operations can take a long time such as disable of big table.
// numRetries is for 'normal' stuff... Multiply by this factor when
// want to wait a long time.
private final int retryLongerMultiplier;
private boolean aborted;
private boolean cleanupConnectionOnClose = false; // close the connection in close()
private boolean closed = false;
private int operationTimeout;
private RpcRetryingCallerFactory rpcCallerFactory;
/**
* Constructor.
* See {@link #HBaseAdmin(Connection connection)}
*
* @param c Configuration object. Copied internally.
* @deprecated Constructing HBaseAdmin objects manually has been deprecated.
* Use {@link Connection#getAdmin()} to obtain an instance of {@link Admin} instead.
*/
@Deprecated
public HBaseAdmin(Configuration c)
throws MasterNotRunningException, ZooKeeperConnectionException, IOException {
// Will not leak connections, as the new implementation of the constructor
// does not throw exceptions anymore.
this(ConnectionManager.getConnectionInternal(new Configuration(c)));
this.cleanupConnectionOnClose = true;
}
@Override
public int getOperationTimeout() {
return operationTimeout;
}
/**
* Constructor for externally managed Connections.
* The connection to master will be created when required by admin functions.
*
* @param connection The Connection instance to use
* @throws MasterNotRunningException, ZooKeeperConnectionException are not
* thrown anymore but kept into the interface for backward api compatibility
* @deprecated Constructing HBaseAdmin objects manually has been deprecated.
* Use {@link Connection#getAdmin()} to obtain an instance of {@link Admin} instead.
*/
@Deprecated
public HBaseAdmin(Connection connection)
throws MasterNotRunningException, ZooKeeperConnectionException {
this((ClusterConnection)connection);
}
HBaseAdmin(ClusterConnection connection) {
this.conf = connection.getConfiguration();
this.connection = connection;
this.pause = this.conf.getLong(HConstants.HBASE_CLIENT_PAUSE,
HConstants.DEFAULT_HBASE_CLIENT_PAUSE);
this.numRetries = this.conf.getInt(HConstants.HBASE_CLIENT_RETRIES_NUMBER,
HConstants.DEFAULT_HBASE_CLIENT_RETRIES_NUMBER);
this.retryLongerMultiplier = this.conf.getInt(
"hbase.client.retries.longer.multiplier", 10);
this.operationTimeout = this.conf.getInt(HConstants.HBASE_CLIENT_OPERATION_TIMEOUT,
HConstants.DEFAULT_HBASE_CLIENT_OPERATION_TIMEOUT);
this.rpcCallerFactory = RpcRetryingCallerFactory.instantiate(this.conf);
}
@Override
public void abort(String why, Throwable e) {
// Currently does nothing but throw the passed message and exception
this.aborted = true;
throw new RuntimeException(why, e);
}
@Override
public boolean isAborted(){
return this.aborted;
}
/** @return HConnection used by this object. */
@Override
public HConnection getConnection() {
return connection;
}
/** @return - true if the master server is running. Throws an exception
* otherwise.
* @throws ZooKeeperConnectionException
* @throws MasterNotRunningException
* @deprecated this has been deprecated without a replacement
*/
@Deprecated
public boolean isMasterRunning()
throws MasterNotRunningException, ZooKeeperConnectionException {
return connection.isMasterRunning();
}
/**
* @param tableName Table to check.
* @return True if table exists already.
* @throws IOException
*/
@Override
public boolean tableExists(final TableName tableName) throws IOException {
return MetaTableAccessor.tableExists(connection, tableName);
}
public boolean tableExists(final byte[] tableName)
throws IOException {
return tableExists(TableName.valueOf(tableName));
}
public boolean tableExists(final String tableName)
throws IOException {
return tableExists(TableName.valueOf(tableName));
}
@Override
public HTableDescriptor[] listTables() throws IOException {
return listTables((Pattern)null, false);
}
@Override
public HTableDescriptor[] listTables(Pattern pattern) throws IOException {
return listTables(pattern, false);
}
@Override
public HTableDescriptor[] listTables(String regex) throws IOException {
return listTables(Pattern.compile(regex), false);
}
@Override
public HTableDescriptor[] listTables(final Pattern pattern, final boolean includeSysTables)
throws IOException {
return executeCallable(new MasterCallable<HTableDescriptor[]>(getConnection()) {
@Override
public HTableDescriptor[] call(int callTimeout) throws ServiceException {
GetTableDescriptorsRequest req =
RequestConverter.buildGetTableDescriptorsRequest(pattern, includeSysTables);
return ProtobufUtil.getHTableDescriptorArray(master.getTableDescriptors(null, req));
}
});
}
@Override
public HTableDescriptor[] listTables(String regex, boolean includeSysTables)
throws IOException {
return listTables(Pattern.compile(regex), includeSysTables);
}
/**
* List all of the names of userspace tables.
* @return String[] table names
* @throws IOException if a remote or network exception occurs
* @deprecated Use {@link Admin#listTableNames()} instead
*/
@Deprecated
public String[] getTableNames() throws IOException {
TableName[] tableNames = listTableNames();
String result[] = new String[tableNames.length];
for (int i = 0; i < tableNames.length; i++) {
result[i] = tableNames[i].getNameAsString();
}
return result;
}
/**
* List all of the names of userspace tables matching the given regular expression.
* @param pattern The regular expression to match against
* @return String[] table names
* @throws IOException if a remote or network exception occurs
* @deprecated Use {@link Admin#listTableNames(Pattern)} instead.
*/
@Deprecated
public String[] getTableNames(Pattern pattern) throws IOException {
TableName[] tableNames = listTableNames(pattern);
String result[] = new String[tableNames.length];
for (int i = 0; i < tableNames.length; i++) {
result[i] = tableNames[i].getNameAsString();
}
return result;
}
/**
* List all of the names of userspace tables matching the given regular expression.
* @param regex The regular expression to match against
* @return String[] table names
* @throws IOException if a remote or network exception occurs
* @deprecated Use {@link Admin#listTableNames(Pattern)} instead.
*/
@Deprecated
public String[] getTableNames(String regex) throws IOException {
return getTableNames(Pattern.compile(regex));
}
@Override
public TableName[] listTableNames() throws IOException {
return listTableNames((Pattern)null, false);
}
@Override
public TableName[] listTableNames(Pattern pattern) throws IOException {
return listTableNames(pattern, false);
}
@Override
public TableName[] listTableNames(String regex) throws IOException {
return listTableNames(Pattern.compile(regex), false);
}
@Override
public TableName[] listTableNames(final Pattern pattern, final boolean includeSysTables)
throws IOException {
return executeCallable(new MasterCallable<TableName[]>(getConnection()) {
@Override
public TableName[] call(int callTimeout) throws ServiceException {
GetTableNamesRequest req =
RequestConverter.buildGetTableNamesRequest(pattern, includeSysTables);
return ProtobufUtil.getTableNameArray(master.getTableNames(null, req)
.getTableNamesList());
}
});
}
@Override
public TableName[] listTableNames(final String regex, final boolean includeSysTables)
throws IOException {
return listTableNames(Pattern.compile(regex), includeSysTables);
}
/**
* Method for getting the tableDescriptor
* @param tableName as a byte []
* @return the tableDescriptor
* @throws TableNotFoundException
* @throws IOException if a remote or network exception occurs
*/
@Override
public HTableDescriptor getTableDescriptor(final TableName tableName)
throws TableNotFoundException, IOException {
if (tableName == null) return null;
if (tableName.equals(TableName.META_TABLE_NAME)) {
return HTableDescriptor.META_TABLEDESC;
}
HTableDescriptor htd = executeCallable(new MasterCallable<HTableDescriptor>(getConnection()) {
@Override
public HTableDescriptor call(int callTimeout) throws ServiceException {
GetTableDescriptorsResponse htds;
GetTableDescriptorsRequest req =
RequestConverter.buildGetTableDescriptorsRequest(tableName);
htds = master.getTableDescriptors(null, req);
if (!htds.getTableSchemaList().isEmpty()) {
return HTableDescriptor.convert(htds.getTableSchemaList().get(0));
}
return null;
}
});
if (htd != null) {
return htd;
}
throw new TableNotFoundException(tableName.getNameAsString());
}
public HTableDescriptor getTableDescriptor(final byte[] tableName)
throws TableNotFoundException, IOException {
return getTableDescriptor(TableName.valueOf(tableName));
}
private long getPauseTime(int tries) {
int triesCount = tries;
if (triesCount >= HConstants.RETRY_BACKOFF.length) {
triesCount = HConstants.RETRY_BACKOFF.length - 1;
}
return this.pause * HConstants.RETRY_BACKOFF[triesCount];
}
/**
* Creates a new table.
* Synchronous operation.
*
* @param desc table descriptor for table
*
* @throws IllegalArgumentException if the table name is reserved
* @throws MasterNotRunningException if master is not running
* @throws TableExistsException if table already exists (If concurrent
* threads, the table may have been created between test-for-existence
* and attempt-at-creation).
* @throws IOException if a remote or network exception occurs
*/
@Override
public void createTable(HTableDescriptor desc)
throws IOException {
createTable(desc, null);
}
/**
* Creates a new table with the specified number of regions. The start key
* specified will become the end key of the first region of the table, and
* the end key specified will become the start key of the last region of the
* table (the first region has a null start key and the last region has a
* null end key).
*
* BigInteger math will be used to divide the key range specified into
* enough segments to make the required number of total regions.
*
* Synchronous operation.
*
* @param desc table descriptor for table
* @param startKey beginning of key range
* @param endKey end of key range
* @param numRegions the total number of regions to create
*
* @throws IllegalArgumentException if the table name is reserved
* @throws MasterNotRunningException if master is not running
* @throws org.apache.hadoop.hbase.TableExistsException if table already exists (If concurrent
* threads, the table may have been created between test-for-existence
* and attempt-at-creation).
* @throws IOException
*/
@Override
public void createTable(HTableDescriptor desc, byte [] startKey,
byte [] endKey, int numRegions)
throws IOException {
if(numRegions < 3) {
throw new IllegalArgumentException("Must create at least three regions");
} else if(Bytes.compareTo(startKey, endKey) >= 0) {
throw new IllegalArgumentException("Start key must be smaller than end key");
}
if (numRegions == 3) {
createTable(desc, new byte[][]{startKey, endKey});
return;
}
byte [][] splitKeys = Bytes.split(startKey, endKey, numRegions - 3);
if(splitKeys == null || splitKeys.length != numRegions - 1) {
throw new IllegalArgumentException("Unable to split key range into enough regions");
}
createTable(desc, splitKeys);
}
/**
* Creates a new table with an initial set of empty regions defined by the
* specified split keys. The total number of regions created will be the
* number of split keys plus one. Synchronous operation.
* Note : Avoid passing empty split key.
*
* @param desc table descriptor for table
* @param splitKeys array of split keys for the initial regions of the table
*
* @throws IllegalArgumentException if the table name is reserved, if the split keys
* are repeated and if the split key has empty byte array.
* @throws MasterNotRunningException if master is not running
* @throws org.apache.hadoop.hbase.TableExistsException if table already exists (If concurrent
* threads, the table may have been created between test-for-existence
* and attempt-at-creation).
* @throws IOException
*/
@Override
public void createTable(final HTableDescriptor desc, byte [][] splitKeys)
throws IOException {
try {
createTableAsync(desc, splitKeys);
} catch (SocketTimeoutException ste) {
LOG.warn("Creating " + desc.getTableName() + " took too long", ste);
}
int numRegs = (splitKeys == null ? 1 : splitKeys.length + 1) * desc.getRegionReplication();
int prevRegCount = 0;
boolean doneWithMetaScan = false;
for (int tries = 0; tries < this.numRetries * this.retryLongerMultiplier;
++tries) {
if (!doneWithMetaScan) {
// Wait for new table to come on-line
final AtomicInteger actualRegCount = new AtomicInteger(0);
MetaScannerVisitor visitor = new MetaScannerVisitorBase() {
@Override
public boolean processRow(Result rowResult) throws IOException {
RegionLocations list = MetaTableAccessor.getRegionLocations(rowResult);
if (list == null) {
LOG.warn("No serialized HRegionInfo in " + rowResult);
return true;
}
HRegionLocation l = list.getRegionLocation();
if (l == null) {
return true;
}
if (!l.getRegionInfo().getTable().equals(desc.getTableName())) {
return false;
}
if (l.getRegionInfo().isOffline() || l.getRegionInfo().isSplit()) return true;
HRegionLocation[] locations = list.getRegionLocations();
for (HRegionLocation location : locations) {
if (location == null) continue;
ServerName serverName = location.getServerName();
// Make sure that regions are assigned to server
if (serverName != null && serverName.getHostAndPort() != null) {
actualRegCount.incrementAndGet();
}
}
return true;
}
};
MetaScanner.metaScan(connection, visitor, desc.getTableName());
if (actualRegCount.get() < numRegs) {
if (tries == this.numRetries * this.retryLongerMultiplier - 1) {
throw new RegionOfflineException("Only " + actualRegCount.get() +
" of " + numRegs + " regions are online; retries exhausted.");
}
try { // Sleep
Thread.sleep(getPauseTime(tries));
} catch (InterruptedException e) {
throw new InterruptedIOException("Interrupted when opening" +
" regions; " + actualRegCount.get() + " of " + numRegs +
" regions processed so far");
}
if (actualRegCount.get() > prevRegCount) { // Making progress
prevRegCount = actualRegCount.get();
tries = -1;
}
} else {
doneWithMetaScan = true;
tries = -1;
}
} else if (isTableEnabled(desc.getTableName())) {
return;
} else {
try { // Sleep
Thread.sleep(getPauseTime(tries));
} catch (InterruptedException e) {
throw new InterruptedIOException("Interrupted when waiting" +
" for table to be enabled; meta scan was done");
}
}
}
throw new TableNotEnabledException(
"Retries exhausted while still waiting for table: "
+ desc.getTableName() + " to be enabled");
}
/**
* Creates a new table but does not block and wait for it to come online.
* Asynchronous operation. To check if the table exists, use
* {@link #isTableAvailable} -- it is not safe to create an HTable
* instance to this table before it is available.
* Note : Avoid passing empty split key.
* @param desc table descriptor for table
*
* @throws IllegalArgumentException Bad table name, if the split keys
* are repeated and if the split key has empty byte array.
* @throws MasterNotRunningException if master is not running
* @throws org.apache.hadoop.hbase.TableExistsException if table already exists (If concurrent
* threads, the table may have been created between test-for-existence
* and attempt-at-creation).
* @throws IOException
*/
@Override
public void createTableAsync(
final HTableDescriptor desc, final byte [][] splitKeys)
throws IOException {
if(desc.getTableName() == null) {
throw new IllegalArgumentException("TableName cannot be null");
}
if(splitKeys != null && splitKeys.length > 0) {
Arrays.sort(splitKeys, Bytes.BYTES_COMPARATOR);
// Verify there are no duplicate split keys
byte [] lastKey = null;
for(byte [] splitKey : splitKeys) {
if (Bytes.compareTo(splitKey, HConstants.EMPTY_BYTE_ARRAY) == 0) {
throw new IllegalArgumentException(
"Empty split key must not be passed in the split keys.");
}
if(lastKey != null && Bytes.equals(splitKey, lastKey)) {
throw new IllegalArgumentException("All split keys must be unique, " +
"found duplicate: " + Bytes.toStringBinary(splitKey) +
", " + Bytes.toStringBinary(lastKey));
}
lastKey = splitKey;
}
}
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
CreateTableRequest request = RequestConverter.buildCreateTableRequest(desc, splitKeys);
master.createTable(null, request);
return null;
}
});
}
public void deleteTable(final String tableName) throws IOException {
deleteTable(TableName.valueOf(tableName));
}
public void deleteTable(final byte[] tableName) throws IOException {
deleteTable(TableName.valueOf(tableName));
}
/**
* Deletes a table.
* Synchronous operation.
*
* @param tableName name of table to delete
* @throws IOException if a remote or network exception occurs
*/
@Override
public void deleteTable(final TableName tableName) throws IOException {
boolean tableExists = true;
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
DeleteTableRequest req = RequestConverter.buildDeleteTableRequest(tableName);
master.deleteTable(null,req);
return null;
}
});
int failures = 0;
// Wait until all regions deleted
for (int tries = 0; tries < (this.numRetries * this.retryLongerMultiplier); tries++) {
try {
// Find whether all regions are deleted.
List<RegionLocations> regionLations =
MetaScanner.listTableRegionLocations(conf, connection, tableName);
// let us wait until hbase:meta table is updated and
// HMaster removes the table from its HTableDescriptors
if (regionLations == null || regionLations.size() == 0) {
HTableDescriptor htd = getTableDescriptorByTableName(tableName);
if (htd == null) {
// table could not be found in master - we are done.
tableExists = false;
break;
}
}
} catch (IOException ex) {
failures++;
if(failures >= numRetries - 1) { // no more tries left
if (ex instanceof RemoteException) {
throw ((RemoteException) ex).unwrapRemoteException();
} else {
throw ex;
}
}
}
try {
Thread.sleep(getPauseTime(tries));
} catch (InterruptedException e) {
throw new InterruptedIOException("Interrupted when waiting" +
" for table to be deleted");
}
}
if (tableExists) {
throw new IOException("Retries exhausted, it took too long to wait"+
" for the table " + tableName + " to be deleted.");
}
// Delete cached information to prevent clients from using old locations
this.connection.clearRegionCache(tableName);
LOG.info("Deleted " + tableName);
}
/**
* Deletes tables matching the passed in pattern and wait on completion.
*
* Warning: Use this method carefully, there is no prompting and the effect is
* immediate. Consider using {@link #listTables(java.lang.String)} and
* {@link #deleteTable(byte[])}
*
* @param regex The regular expression to match table names against
* @return Table descriptors for tables that couldn't be deleted
* @throws IOException
* @see #deleteTables(java.util.regex.Pattern)
* @see #deleteTable(java.lang.String)
*/
@Override
public HTableDescriptor[] deleteTables(String regex) throws IOException {
return deleteTables(Pattern.compile(regex));
}
/**
* Delete tables matching the passed in pattern and wait on completion.
*
* Warning: Use this method carefully, there is no prompting and the effect is
* immediate. Consider using {@link #listTables(java.util.regex.Pattern) } and
* {@link #deleteTable(byte[])}
*
* @param pattern The pattern to match table names against
* @return Table descriptors for tables that couldn't be deleted
* @throws IOException
*/
@Override
public HTableDescriptor[] deleteTables(Pattern pattern) throws IOException {
List<HTableDescriptor> failed = new LinkedList<HTableDescriptor>();
for (HTableDescriptor table : listTables(pattern)) {
try {
deleteTable(table.getTableName());
} catch (IOException ex) {
LOG.info("Failed to delete table " + table.getTableName(), ex);
failed.add(table);
}
}
return failed.toArray(new HTableDescriptor[failed.size()]);
}
/**
* Truncate a table.
* Synchronous operation.
*
* @param tableName name of table to truncate
* @param preserveSplits True if the splits should be preserved
* @throws IOException if a remote or network exception occurs
*/
@Override
public void truncateTable(final TableName tableName, final boolean preserveSplits)
throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
TruncateTableRequest req = RequestConverter.buildTruncateTableRequest(
tableName, preserveSplits);
master.truncateTable(null, req);
return null;
}
});
}
/**
* Enable a table. May timeout. Use {@link #enableTableAsync(byte[])}
* and {@link #isTableEnabled(byte[])} instead.
* The table has to be in disabled state for it to be enabled.
* @param tableName name of the table
* @throws IOException if a remote or network exception occurs
* There could be couple types of IOException
* TableNotFoundException means the table doesn't exist.
* TableNotDisabledException means the table isn't in disabled state.
* @see #isTableEnabled(byte[])
* @see #disableTable(byte[])
* @see #enableTableAsync(byte[])
*/
@Override
public void enableTable(final TableName tableName)
throws IOException {
enableTableAsync(tableName);
// Wait until all regions are enabled
waitUntilTableIsEnabled(tableName);
LOG.info("Enabled table " + tableName);
}
public void enableTable(final byte[] tableName)
throws IOException {
enableTable(TableName.valueOf(tableName));
}
public void enableTable(final String tableName)
throws IOException {
enableTable(TableName.valueOf(tableName));
}
/**
* Wait for the table to be enabled and available
* If enabling the table exceeds the retry period, an exception is thrown.
* @param tableName name of the table
* @throws IOException if a remote or network exception occurs or
* table is not enabled after the retries period.
*/
private void waitUntilTableIsEnabled(final TableName tableName) throws IOException {
boolean enabled = false;
long start = EnvironmentEdgeManager.currentTime();
for (int tries = 0; tries < (this.numRetries * this.retryLongerMultiplier); tries++) {
try {
enabled = isTableEnabled(tableName);
} catch (TableNotFoundException tnfe) {
// wait for table to be created
enabled = false;
}
enabled = enabled && isTableAvailable(tableName);
if (enabled) {
break;
}
long sleep = getPauseTime(tries);
if (LOG.isDebugEnabled()) {
LOG.debug("Sleeping= " + sleep + "ms, waiting for all regions to be " +
"enabled in " + tableName);
}
try {
Thread.sleep(sleep);
} catch (InterruptedException e) {
// Do this conversion rather than let it out because do not want to
// change the method signature.
throw (InterruptedIOException)new InterruptedIOException("Interrupted").initCause(e);
}
}
if (!enabled) {
long msec = EnvironmentEdgeManager.currentTime() - start;
throw new IOException("Table '" + tableName +
"' not yet enabled, after " + msec + "ms.");
}
}
/**
* Brings a table on-line (enables it). Method returns immediately though
* enable of table may take some time to complete, especially if the table
* is large (All regions are opened as part of enabling process). Check
* {@link #isTableEnabled(byte[])} to learn when table is fully online. If
* table is taking too long to online, check server logs.
* @param tableName
* @throws IOException
* @since 0.90.0
*/
@Override
public void enableTableAsync(final TableName tableName)
throws IOException {
TableName.isLegalFullyQualifiedTableName(tableName.getName());
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
LOG.info("Started enable of " + tableName);
EnableTableRequest req = RequestConverter.buildEnableTableRequest(tableName);
master.enableTable(null,req);
return null;
}
});
}
public void enableTableAsync(final byte[] tableName)
throws IOException {
enableTable(TableName.valueOf(tableName));
}
public void enableTableAsync(final String tableName)
throws IOException {
enableTableAsync(TableName.valueOf(tableName));
}
/**
* Enable tables matching the passed in pattern and wait on completion.
*
* Warning: Use this method carefully, there is no prompting and the effect is
* immediate. Consider using {@link #listTables(java.lang.String)} and
* {@link #enableTable(byte[])}
*
* @param regex The regular expression to match table names against
* @throws IOException
* @see #enableTables(java.util.regex.Pattern)
* @see #enableTable(java.lang.String)
*/
@Override
public HTableDescriptor[] enableTables(String regex) throws IOException {
return enableTables(Pattern.compile(regex));
}
/**
* Enable tables matching the passed in pattern and wait on completion.
*
* Warning: Use this method carefully, there is no prompting and the effect is
* immediate. Consider using {@link #listTables(java.util.regex.Pattern) } and
* {@link #enableTable(byte[])}
*
* @param pattern The pattern to match table names against
* @throws IOException
*/
@Override
public HTableDescriptor[] enableTables(Pattern pattern) throws IOException {
List<HTableDescriptor> failed = new LinkedList<HTableDescriptor>();
for (HTableDescriptor table : listTables(pattern)) {
if (isTableDisabled(table.getTableName())) {
try {
enableTable(table.getTableName());
} catch (IOException ex) {
LOG.info("Failed to enable table " + table.getTableName(), ex);
failed.add(table);
}
}
}
return failed.toArray(new HTableDescriptor[failed.size()]);
}
/**
* Starts the disable of a table. If it is being served, the master
* will tell the servers to stop serving it. This method returns immediately.
* The disable of a table can take some time if the table is large (all
* regions are closed as part of table disable operation).
* Call {@link #isTableDisabled(byte[])} to check for when disable completes.
* If table is taking too long to online, check server logs.
* @param tableName name of table
* @throws IOException if a remote or network exception occurs
* @see #isTableDisabled(byte[])
* @see #isTableEnabled(byte[])
* @since 0.90.0
*/
@Override
public void disableTableAsync(final TableName tableName) throws IOException {
TableName.isLegalFullyQualifiedTableName(tableName.getName());
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
LOG.info("Started disable of " + tableName);
DisableTableRequest req = RequestConverter.buildDisableTableRequest(tableName);
master.disableTable(null,req);
return null;
}
});
}
public void disableTableAsync(final byte[] tableName) throws IOException {
disableTableAsync(TableName.valueOf(tableName));
}
public void disableTableAsync(final String tableName) throws IOException {
disableTableAsync(TableName.valueOf(tableName));
}
/**
* Disable table and wait on completion. May timeout eventually. Use
* {@link #disableTableAsync(byte[])} and {@link #isTableDisabled(String)}
* instead.
* The table has to be in enabled state for it to be disabled.
* @param tableName
* @throws IOException
* There could be couple types of IOException
* TableNotFoundException means the table doesn't exist.
* TableNotEnabledException means the table isn't in enabled state.
*/
@Override
public void disableTable(final TableName tableName)
throws IOException {
disableTableAsync(tableName);
// Wait until table is disabled
boolean disabled = false;
for (int tries = 0; tries < (this.numRetries * this.retryLongerMultiplier); tries++) {
disabled = isTableDisabled(tableName);
if (disabled) {
break;
}
long sleep = getPauseTime(tries);
if (LOG.isDebugEnabled()) {
LOG.debug("Sleeping= " + sleep + "ms, waiting for all regions to be " +
"disabled in " + tableName);
}
try {
Thread.sleep(sleep);
} catch (InterruptedException e) {
// Do this conversion rather than let it out because do not want to
// change the method signature.
throw (InterruptedIOException)new InterruptedIOException("Interrupted").initCause(e);
}
}
if (!disabled) {
throw new RegionException("Retries exhausted, it took too long to wait"+
" for the table " + tableName + " to be disabled.");
}
LOG.info("Disabled " + tableName);
}
public void disableTable(final byte[] tableName)
throws IOException {
disableTable(TableName.valueOf(tableName));
}
public void disableTable(final String tableName)
throws IOException {
disableTable(TableName.valueOf(tableName));
}
/**
* Disable tables matching the passed in pattern and wait on completion.
*
* Warning: Use this method carefully, there is no prompting and the effect is
* immediate. Consider using {@link #listTables(java.lang.String)} and
* {@link #disableTable(byte[])}
*
* @param regex The regular expression to match table names against
* @return Table descriptors for tables that couldn't be disabled
* @throws IOException
* @see #disableTables(java.util.regex.Pattern)
* @see #disableTable(java.lang.String)
*/
@Override
public HTableDescriptor[] disableTables(String regex) throws IOException {
return disableTables(Pattern.compile(regex));
}
/**
* Disable tables matching the passed in pattern and wait on completion.
*
* Warning: Use this method carefully, there is no prompting and the effect is
* immediate. Consider using {@link #listTables(java.util.regex.Pattern) } and
* {@link #disableTable(byte[])}
*
* @param pattern The pattern to match table names against
* @return Table descriptors for tables that couldn't be disabled
* @throws IOException
*/
@Override
public HTableDescriptor[] disableTables(Pattern pattern) throws IOException {
List<HTableDescriptor> failed = new LinkedList<HTableDescriptor>();
for (HTableDescriptor table : listTables(pattern)) {
if (isTableEnabled(table.getTableName())) {
try {
disableTable(table.getTableName());
} catch (IOException ex) {
LOG.info("Failed to disable table " + table.getTableName(), ex);
failed.add(table);
}
}
}
return failed.toArray(new HTableDescriptor[failed.size()]);
}
/*
* Checks whether table exists. If not, throws TableNotFoundException
* @param tableName
*/
private void checkTableExistence(TableName tableName) throws IOException {
if (!tableExists(tableName)) {
throw new TableNotFoundException(tableName);
}
}
/**
* @param tableName name of table to check
* @return true if table is on-line
* @throws IOException if a remote or network exception occurs
*/
@Override
public boolean isTableEnabled(TableName tableName) throws IOException {
checkTableExistence(tableName);
return connection.isTableEnabled(tableName);
}
public boolean isTableEnabled(byte[] tableName) throws IOException {
return isTableEnabled(TableName.valueOf(tableName));
}
public boolean isTableEnabled(String tableName) throws IOException {
return isTableEnabled(TableName.valueOf(tableName));
}
/**
* @param tableName name of table to check
* @return true if table is off-line
* @throws IOException if a remote or network exception occurs
*/
@Override
public boolean isTableDisabled(TableName tableName) throws IOException {
checkTableExistence(tableName);
return connection.isTableDisabled(tableName);
}
public boolean isTableDisabled(byte[] tableName) throws IOException {
return isTableDisabled(TableName.valueOf(tableName));
}
public boolean isTableDisabled(String tableName) throws IOException {
return isTableDisabled(TableName.valueOf(tableName));
}
/**
* @param tableName name of table to check
* @return true if all regions of the table are available
* @throws IOException if a remote or network exception occurs
*/
@Override
public boolean isTableAvailable(TableName tableName) throws IOException {
return connection.isTableAvailable(tableName);
}
public boolean isTableAvailable(byte[] tableName) throws IOException {
return isTableAvailable(TableName.valueOf(tableName));
}
public boolean isTableAvailable(String tableName) throws IOException {
return isTableAvailable(TableName.valueOf(tableName));
}
/**
* Use this api to check if the table has been created with the specified number of
* splitkeys which was used while creating the given table.
* Note : If this api is used after a table's region gets splitted, the api may return
* false.
* @param tableName
* name of table to check
* @param splitKeys
* keys to check if the table has been created with all split keys
* @throws IOException
* if a remote or network excpetion occurs
*/
@Override
public boolean isTableAvailable(TableName tableName,
byte[][] splitKeys) throws IOException {
return connection.isTableAvailable(tableName, splitKeys);
}
public boolean isTableAvailable(byte[] tableName,
byte[][] splitKeys) throws IOException {
return isTableAvailable(TableName.valueOf(tableName), splitKeys);
}
public boolean isTableAvailable(String tableName,
byte[][] splitKeys) throws IOException {
return isTableAvailable(TableName.valueOf(tableName), splitKeys);
}
/**
* Get the status of alter command - indicates how many regions have received
* the updated schema Asynchronous operation.
*
* @param tableName TableName instance
* @return Pair indicating the number of regions updated Pair.getFirst() is the
* regions that are yet to be updated Pair.getSecond() is the total number
* of regions of the table
* @throws IOException
* if a remote or network exception occurs
*/
@Override
public Pair<Integer, Integer> getAlterStatus(final TableName tableName)
throws IOException {
return executeCallable(new MasterCallable<Pair<Integer, Integer>>(getConnection()) {
@Override
public Pair<Integer, Integer> call(int callTimeout) throws ServiceException {
GetSchemaAlterStatusRequest req = RequestConverter
.buildGetSchemaAlterStatusRequest(tableName);
GetSchemaAlterStatusResponse ret = master.getSchemaAlterStatus(null, req);
Pair<Integer, Integer> pair = new Pair<Integer, Integer>(Integer.valueOf(ret
.getYetToUpdateRegions()), Integer.valueOf(ret.getTotalRegions()));
return pair;
}
});
}
/**
* Get the status of alter command - indicates how many regions have received
* the updated schema Asynchronous operation.
*
* @param tableName
* name of the table to get the status of
* @return Pair indicating the number of regions updated Pair.getFirst() is the
* regions that are yet to be updated Pair.getSecond() is the total number
* of regions of the table
* @throws IOException
* if a remote or network exception occurs
*/
@Override
public Pair<Integer, Integer> getAlterStatus(final byte[] tableName)
throws IOException {
return getAlterStatus(TableName.valueOf(tableName));
}
/**
* Add a column to an existing table.
* Asynchronous operation.
*
* @param tableName name of the table to add column to
* @param column column descriptor of column to be added
* @throws IOException if a remote or network exception occurs
*/
public void addColumn(final byte[] tableName, HColumnDescriptor column)
throws IOException {
addColumn(TableName.valueOf(tableName), column);
}
/**
* Add a column to an existing table.
* Asynchronous operation.
*
* @param tableName name of the table to add column to
* @param column column descriptor of column to be added
* @throws IOException if a remote or network exception occurs
*/
public void addColumn(final String tableName, HColumnDescriptor column)
throws IOException {
addColumn(TableName.valueOf(tableName), column);
}
/**
* Add a column to an existing table.
* Asynchronous operation.
*
* @param tableName name of the table to add column to
* @param column column descriptor of column to be added
* @throws IOException if a remote or network exception occurs
*/
@Override
public void addColumn(final TableName tableName, final HColumnDescriptor column)
throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
AddColumnRequest req = RequestConverter.buildAddColumnRequest(tableName, column);
master.addColumn(null,req);
return null;
}
});
}
/**
* Delete a column from a table.
* Asynchronous operation.
*
* @param tableName name of table
* @param columnName name of column to be deleted
* @throws IOException if a remote or network exception occurs
*/
public void deleteColumn(final byte[] tableName, final String columnName)
throws IOException {
deleteColumn(TableName.valueOf(tableName), Bytes.toBytes(columnName));
}
/**
* Delete a column from a table.
* Asynchronous operation.
*
* @param tableName name of table
* @param columnName name of column to be deleted
* @throws IOException if a remote or network exception occurs
*/
public void deleteColumn(final String tableName, final String columnName)
throws IOException {
deleteColumn(TableName.valueOf(tableName), Bytes.toBytes(columnName));
}
/**
* Delete a column from a table.
* Asynchronous operation.
*
* @param tableName name of table
* @param columnName name of column to be deleted
* @throws IOException if a remote or network exception occurs
*/
@Override
public void deleteColumn(final TableName tableName, final byte [] columnName)
throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
DeleteColumnRequest req = RequestConverter.buildDeleteColumnRequest(tableName, columnName);
master.deleteColumn(null,req);
return null;
}
});
}
/**
* Modify an existing column family on a table.
* Asynchronous operation.
*
* @param tableName name of table
* @param descriptor new column descriptor to use
* @throws IOException if a remote or network exception occurs
*/
public void modifyColumn(final String tableName, HColumnDescriptor descriptor)
throws IOException {
modifyColumn(TableName.valueOf(tableName), descriptor);
}
/**
* Modify an existing column family on a table.
* Asynchronous operation.
*
* @param tableName name of table
* @param descriptor new column descriptor to use
* @throws IOException if a remote or network exception occurs
*/
public void modifyColumn(final byte[] tableName, HColumnDescriptor descriptor)
throws IOException {
modifyColumn(TableName.valueOf(tableName), descriptor);
}
/**
* Modify an existing column family on a table.
* Asynchronous operation.
*
* @param tableName name of table
* @param descriptor new column descriptor to use
* @throws IOException if a remote or network exception occurs
*/
@Override
public void modifyColumn(final TableName tableName, final HColumnDescriptor descriptor)
throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
ModifyColumnRequest req = RequestConverter.buildModifyColumnRequest(tableName, descriptor);
master.modifyColumn(null,req);
return null;
}
});
}
/**
* Close a region. For expert-admins. Runs close on the regionserver. The
* master will not be informed of the close.
* @param regionname region name to close
* @param serverName If supplied, we'll use this location rather than
* the one currently in <code>hbase:meta</code>
* @throws IOException if a remote or network exception occurs
*/
@Override
public void closeRegion(final String regionname, final String serverName)
throws IOException {
closeRegion(Bytes.toBytes(regionname), serverName);
}
/**
* Close a region. For expert-admins Runs close on the regionserver. The
* master will not be informed of the close.
* @param regionname region name to close
* @param serverName The servername of the regionserver. If passed null we
* will use servername found in the hbase:meta table. A server name
* is made of host, port and startcode. Here is an example:
* <code> host187.example.com,60020,1289493121758</code>
* @throws IOException if a remote or network exception occurs
*/
@Override
public void closeRegion(final byte [] regionname, final String serverName)
throws IOException {
if (serverName != null) {
Pair<HRegionInfo, ServerName> pair = MetaTableAccessor.getRegion(connection, regionname);
if (pair == null || pair.getFirst() == null) {
throw new UnknownRegionException(Bytes.toStringBinary(regionname));
} else {
closeRegion(ServerName.valueOf(serverName), pair.getFirst());
}
} else {
Pair<HRegionInfo, ServerName> pair = MetaTableAccessor.getRegion(connection, regionname);
if (pair == null) {
throw new UnknownRegionException(Bytes.toStringBinary(regionname));
} else if (pair.getSecond() == null) {
throw new NoServerForRegionException(Bytes.toStringBinary(regionname));
} else {
closeRegion(pair.getSecond(), pair.getFirst());
}
}
}
/**
* For expert-admins. Runs close on the regionserver. Closes a region based on
* the encoded region name. The region server name is mandatory. If the
* servername is provided then based on the online regions in the specified
* regionserver the specified region will be closed. The master will not be
* informed of the close. Note that the regionname is the encoded regionname.
*
* @param encodedRegionName
* The encoded region name; i.e. the hash that makes up the region
* name suffix: e.g. if regionname is
* <code>TestTable,0094429456,1289497600452.527db22f95c8a9e0116f0cc13c680396.</code>
* , then the encoded region name is:
* <code>527db22f95c8a9e0116f0cc13c680396</code>.
* @param serverName
* The servername of the regionserver. A server name is made of host,
* port and startcode. This is mandatory. Here is an example:
* <code> host187.example.com,60020,1289493121758</code>
* @return true if the region was closed, false if not.
* @throws IOException
* if a remote or network exception occurs
*/
@Override
public boolean closeRegionWithEncodedRegionName(final String encodedRegionName,
final String serverName) throws IOException {
if (null == serverName || ("").equals(serverName.trim())) {
throw new IllegalArgumentException(
"The servername cannot be null or empty.");
}
ServerName sn = ServerName.valueOf(serverName);
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
// Close the region without updating zk state.
CloseRegionRequest request =
RequestConverter.buildCloseRegionRequest(sn, encodedRegionName);
try {
CloseRegionResponse response = admin.closeRegion(null, request);
boolean isRegionClosed = response.getClosed();
if (false == isRegionClosed) {
LOG.error("Not able to close the region " + encodedRegionName + ".");
}
return isRegionClosed;
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
}
}
/**
* Close a region. For expert-admins Runs close on the regionserver. The
* master will not be informed of the close.
* @param sn
* @param hri
* @throws IOException
*/
@Override
public void closeRegion(final ServerName sn, final HRegionInfo hri)
throws IOException {
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
// Close the region without updating zk state.
ProtobufUtil.closeRegion(admin, sn, hri.getRegionName());
}
/**
* Get all the online regions on a region server.
*/
@Override
public List<HRegionInfo> getOnlineRegions(final ServerName sn) throws IOException {
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
return ProtobufUtil.getOnlineRegions(admin);
}
/**
* {@inheritDoc}
*/
@Override
public void flush(final TableName tableName) throws IOException {
checkTableExists(tableName);
if (isTableDisabled(tableName)) {
LOG.info("Table is disabled: " + tableName.getNameAsString());
return;
}
execProcedure("flush-table-proc", tableName.getNameAsString(),
new HashMap<String, String>());
}
/**
* {@inheritDoc}
*/
@Override
public void flushRegion(final byte[] regionName) throws IOException {
Pair<HRegionInfo, ServerName> regionServerPair = getRegion(regionName);
if (regionServerPair == null) {
throw new IllegalArgumentException("Unknown regionname: " + Bytes.toStringBinary(regionName));
}
if (regionServerPair.getSecond() == null) {
throw new NoServerForRegionException(Bytes.toStringBinary(regionName));
}
flush(regionServerPair.getSecond(), regionServerPair.getFirst());
}
/**
* @deprecated Use {@link #flush(org.apache.hadoop.hbase.TableName)} or {@link #flushRegion
* (byte[])} instead.
*/
@Deprecated
public void flush(final String tableNameOrRegionName)
throws IOException, InterruptedException {
flush(Bytes.toBytes(tableNameOrRegionName));
}
/**
* @deprecated Use {@link #flush(org.apache.hadoop.hbase.TableName)} or {@link #flushRegion
* (byte[])} instead.
*/
@Deprecated
public void flush(final byte[] tableNameOrRegionName)
throws IOException, InterruptedException {
try {
flushRegion(tableNameOrRegionName);
} catch (IllegalArgumentException e) {
// Unknown region. Try table.
flush(TableName.valueOf(tableNameOrRegionName));
}
}
private void flush(final ServerName sn, final HRegionInfo hri)
throws IOException {
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
FlushRegionRequest request =
RequestConverter.buildFlushRegionRequest(hri.getRegionName());
try {
admin.flushRegion(null, request);
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
}
}
/**
* {@inheritDoc}
*/
@Override
public void compact(final TableName tableName)
throws IOException {
compact(tableName, null, false);
}
/**
* {@inheritDoc}
*/
@Override
public void compactRegion(final byte[] regionName)
throws IOException {
compactRegion(regionName, null, false);
}
/**
* @deprecated Use {@link #compact(org.apache.hadoop.hbase.TableName)} or {@link #compactRegion
* (byte[])} instead.
*/
@Deprecated
public void compact(final String tableNameOrRegionName)
throws IOException {
compact(Bytes.toBytes(tableNameOrRegionName));
}
/**
* @deprecated Use {@link #compact(org.apache.hadoop.hbase.TableName)} or {@link #compactRegion
* (byte[])} instead.
*/
@Deprecated
public void compact(final byte[] tableNameOrRegionName)
throws IOException {
try {
compactRegion(tableNameOrRegionName, null, false);
} catch (IllegalArgumentException e) {
compact(TableName.valueOf(tableNameOrRegionName), null, false);
}
}
/**
* {@inheritDoc}
*/
@Override
public void compact(final TableName tableName, final byte[] columnFamily)
throws IOException {
compact(tableName, columnFamily, false);
}
/**
* {@inheritDoc}
*/
@Override
public void compactRegion(final byte[] regionName, final byte[] columnFamily)
throws IOException {
compactRegion(regionName, columnFamily, false);
}
/**
* @deprecated Use {@link #compact(org.apache.hadoop.hbase.TableName)} or {@link #compactRegion
* (byte[], byte[])} instead.
*/
@Deprecated
public void compact(String tableOrRegionName, String columnFamily)
throws IOException {
compact(Bytes.toBytes(tableOrRegionName), Bytes.toBytes(columnFamily));
}
/**
* @deprecated Use {@link #compact(org.apache.hadoop.hbase.TableName)} or {@link #compactRegion
* (byte[], byte[])} instead.
*/
@Deprecated
public void compact(final byte[] tableNameOrRegionName, final byte[] columnFamily)
throws IOException {
try {
compactRegion(tableNameOrRegionName, columnFamily, false);
} catch (IllegalArgumentException e) {
// Bad region, try table
compact(TableName.valueOf(tableNameOrRegionName), columnFamily, false);
}
}
/**
* {@inheritDoc}
*/
@Override
public void compactRegionServer(final ServerName sn, boolean major)
throws IOException, InterruptedException {
for (HRegionInfo region : getOnlineRegions(sn)) {
compact(sn, region, major, null);
}
}
/**
* {@inheritDoc}
*/
@Override
public void majorCompact(final TableName tableName)
throws IOException {
compact(tableName, null, true);
}
/**
* {@inheritDoc}
*/
@Override
public void majorCompactRegion(final byte[] regionName)
throws IOException {
compactRegion(regionName, null, true);
}
/**
* @deprecated Use {@link #majorCompact(org.apache.hadoop.hbase.TableName)} or {@link
* #majorCompactRegion(byte[])} instead.
*/
@Deprecated
public void majorCompact(final String tableNameOrRegionName)
throws IOException {
majorCompact(Bytes.toBytes(tableNameOrRegionName));
}
/**
* @deprecated Use {@link #majorCompact(org.apache.hadoop.hbase.TableName)} or {@link
* #majorCompactRegion(byte[])} instead.
*/
@Deprecated
public void majorCompact(final byte[] tableNameOrRegionName)
throws IOException {
try {
compactRegion(tableNameOrRegionName, null, true);
} catch (IllegalArgumentException e) {
// Invalid region, try table
compact(TableName.valueOf(tableNameOrRegionName), null, true);
}
}
/**
* {@inheritDoc}
*/
@Override
public void majorCompact(final TableName tableName, final byte[] columnFamily)
throws IOException {
compact(tableName, columnFamily, true);
}
/**
* {@inheritDoc}
*/
@Override
public void majorCompactRegion(final byte[] regionName, final byte[] columnFamily)
throws IOException {
compactRegion(regionName, columnFamily, true);
}
/**
* @deprecated Use {@link #majorCompact(org.apache.hadoop.hbase.TableName,
* byte[])} or {@link #majorCompactRegion(byte[], byte[])} instead.
*/
@Deprecated
public void majorCompact(final String tableNameOrRegionName, final String columnFamily)
throws IOException {
majorCompact(Bytes.toBytes(tableNameOrRegionName), Bytes.toBytes(columnFamily));
}
/**
* @deprecated Use {@link #majorCompact(org.apache.hadoop.hbase.TableName,
* byte[])} or {@link #majorCompactRegion(byte[], byte[])} instead.
*/
@Deprecated
public void majorCompact(final byte[] tableNameOrRegionName, final byte[] columnFamily)
throws IOException {
try {
compactRegion(tableNameOrRegionName, columnFamily, true);
} catch (IllegalArgumentException e) {
// Invalid region, try table
compact(TableName.valueOf(tableNameOrRegionName), columnFamily, true);
}
}
/**
* Compact a table.
* Asynchronous operation.
*
* @param tableName table or region to compact
* @param columnFamily column family within a table or region
* @param major True if we are to do a major compaction.
* @throws IOException if a remote or network exception occurs
* @throws InterruptedException
*/
private void compact(final TableName tableName, final byte[] columnFamily,final boolean major)
throws IOException {
ZooKeeperWatcher zookeeper = null;
try {
checkTableExists(tableName);
zookeeper = new ZooKeeperWatcher(conf, ZK_IDENTIFIER_PREFIX + connection.toString(),
new ThrowableAbortable());
List<Pair<HRegionInfo, ServerName>> pairs;
if (TableName.META_TABLE_NAME.equals(tableName)) {
pairs = new MetaTableLocator().getMetaRegionsAndLocations(zookeeper);
} else {
pairs = MetaTableAccessor.getTableRegionsAndLocations(connection, tableName);
}
for (Pair<HRegionInfo, ServerName> pair: pairs) {
if (pair.getFirst().isOffline()) continue;
if (pair.getSecond() == null) continue;
try {
compact(pair.getSecond(), pair.getFirst(), major, columnFamily);
} catch (NotServingRegionException e) {
if (LOG.isDebugEnabled()) {
LOG.debug("Trying to" + (major ? " major" : "") + " compact " +
pair.getFirst() + ": " +
StringUtils.stringifyException(e));
}
}
}
} finally {
if (zookeeper != null) {
zookeeper.close();
}
}
}
/**
* Compact an individual region.
* Asynchronous operation.
*
* @param regionName region to compact
* @param columnFamily column family within a table or region
* @param major True if we are to do a major compaction.
* @throws IOException if a remote or network exception occurs
* @throws InterruptedException
*/
private void compactRegion(final byte[] regionName, final byte[] columnFamily,final boolean major)
throws IOException {
Pair<HRegionInfo, ServerName> regionServerPair = getRegion(regionName);
if (regionServerPair == null) {
throw new IllegalArgumentException("Invalid region: " + Bytes.toStringBinary(regionName));
}
if (regionServerPair.getSecond() == null) {
throw new NoServerForRegionException(Bytes.toStringBinary(regionName));
}
compact(regionServerPair.getSecond(), regionServerPair.getFirst(), major, columnFamily);
}
private void compact(final ServerName sn, final HRegionInfo hri,
final boolean major, final byte [] family)
throws IOException {
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
CompactRegionRequest request =
RequestConverter.buildCompactRegionRequest(hri.getRegionName(), major, family);
try {
admin.compactRegion(null, request);
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
}
}
/**
* Move the region <code>r</code> to <code>dest</code>.
* @param encodedRegionName The encoded region name; i.e. the hash that makes
* up the region name suffix: e.g. if regionname is
* <code>TestTable,0094429456,1289497600452.527db22f95c8a9e0116f0cc13c680396.</code>,
* then the encoded region name is: <code>527db22f95c8a9e0116f0cc13c680396</code>.
* @param destServerName The servername of the destination regionserver. If
* passed the empty byte array we'll assign to a random server. A server name
* is made of host, port and startcode. Here is an example:
* <code> host187.example.com,60020,1289493121758</code>
* @throws UnknownRegionException Thrown if we can't find a region named
* <code>encodedRegionName</code>
*/
@Override
public void move(final byte [] encodedRegionName, final byte [] destServerName)
throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
try {
MoveRegionRequest request =
RequestConverter.buildMoveRegionRequest(encodedRegionName, destServerName);
master.moveRegion(null, request);
} catch (DeserializationException de) {
LOG.error("Could not parse destination server name: " + de);
throw new ServiceException(new DoNotRetryIOException(de));
}
return null;
}
});
}
/**
* @param regionName
* Region name to assign.
* @throws MasterNotRunningException
* @throws ZooKeeperConnectionException
* @throws IOException
*/
@Override
public void assign(final byte[] regionName) throws MasterNotRunningException,
ZooKeeperConnectionException, IOException {
final byte[] toBeAssigned = getRegionName(regionName);
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
AssignRegionRequest request =
RequestConverter.buildAssignRegionRequest(toBeAssigned);
master.assignRegion(null,request);
return null;
}
});
}
/**
* Unassign a region from current hosting regionserver. Region will then be
* assigned to a regionserver chosen at random. Region could be reassigned
* back to the same server. Use {@link #move(byte[], byte[])} if you want
* to control the region movement.
* @param regionName Region to unassign. Will clear any existing RegionPlan
* if one found.
* @param force If true, force unassign (Will remove region from
* regions-in-transition too if present. If results in double assignment
* use hbck -fix to resolve. To be used by experts).
* @throws MasterNotRunningException
* @throws ZooKeeperConnectionException
* @throws IOException
*/
@Override
public void unassign(final byte [] regionName, final boolean force)
throws MasterNotRunningException, ZooKeeperConnectionException, IOException {
final byte[] toBeUnassigned = getRegionName(regionName);
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
UnassignRegionRequest request =
RequestConverter.buildUnassignRegionRequest(toBeUnassigned, force);
master.unassignRegion(null, request);
return null;
}
});
}
/**
* Offline specified region from master's in-memory state. It will not attempt to reassign the
* region as in unassign. This API can be used when a region not served by any region server and
* still online as per Master's in memory state. If this API is incorrectly used on active region
* then master will loose track of that region.
*
* This is a special method that should be used by experts or hbck.
*
* @param regionName
* Region to offline.
* @throws IOException
*/
@Override
public void offline(final byte [] regionName)
throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
master.offlineRegion(null,RequestConverter.buildOfflineRegionRequest(regionName));
return null;
}
});
}
/**
* Turn the load balancer on or off.
* @param on If true, enable balancer. If false, disable balancer.
* @param synchronous If true, it waits until current balance() call, if outstanding, to return.
* @return Previous balancer value
*/
@Override
public boolean setBalancerRunning(final boolean on, final boolean synchronous)
throws IOException {
return executeCallable(new MasterCallable<Boolean>(getConnection()) {
@Override
public Boolean call(int callTimeout) throws ServiceException {
SetBalancerRunningRequest req =
RequestConverter.buildSetBalancerRunningRequest(on, synchronous);
return master.setBalancerRunning(null, req).getPrevBalanceValue();
}
});
}
/**
* Invoke the balancer. Will run the balancer and if regions to move, it will
* go ahead and do the reassignments. Can NOT run for various reasons. Check
* logs.
* @return True if balancer ran, false otherwise.
*/
@Override
public boolean balancer() throws IOException {
return executeCallable(new MasterCallable<Boolean>(getConnection()) {
@Override
public Boolean call(int callTimeout) throws ServiceException {
return master.balance(null, RequestConverter.buildBalanceRequest()).getBalancerRan();
}
});
}
/**
* Enable/Disable the catalog janitor
* @param enable if true enables the catalog janitor
* @return the previous state
* @throws MasterNotRunningException
*/
@Override
public boolean enableCatalogJanitor(final boolean enable)
throws IOException {
return executeCallable(new MasterCallable<Boolean>(getConnection()) {
@Override
public Boolean call(int callTimeout) throws ServiceException {
return master.enableCatalogJanitor(null,
RequestConverter.buildEnableCatalogJanitorRequest(enable)).getPrevValue();
}
});
}
/**
* Ask for a scan of the catalog table
* @return the number of entries cleaned
* @throws MasterNotRunningException
*/
@Override
public int runCatalogScan() throws IOException {
return executeCallable(new MasterCallable<Integer>(getConnection()) {
@Override
public Integer call(int callTimeout) throws ServiceException {
return master.runCatalogScan(null,
RequestConverter.buildCatalogScanRequest()).getScanResult();
}
});
}
/**
* Query on the catalog janitor state (Enabled/Disabled?)
* @throws org.apache.hadoop.hbase.MasterNotRunningException
*/
@Override
public boolean isCatalogJanitorEnabled() throws IOException {
return executeCallable(new MasterCallable<Boolean>(getConnection()) {
@Override
public Boolean call(int callTimeout) throws ServiceException {
return master.isCatalogJanitorEnabled(null,
RequestConverter.buildIsCatalogJanitorEnabledRequest()).getValue();
}
});
}
/**
* Merge two regions. Asynchronous operation.
* @param encodedNameOfRegionA encoded name of region a
* @param encodedNameOfRegionB encoded name of region b
* @param forcible true if do a compulsory merge, otherwise we will only merge
* two adjacent regions
* @throws IOException
*/
@Override
public void mergeRegions(final byte[] encodedNameOfRegionA,
final byte[] encodedNameOfRegionB, final boolean forcible)
throws IOException {
Pair<HRegionInfo, ServerName> pair = getRegion(encodedNameOfRegionA);
if (pair != null && pair.getFirst().getReplicaId() != HRegionInfo.DEFAULT_REPLICA_ID)
throw new IllegalArgumentException("Can't invoke merge on non-default regions directly");
pair = getRegion(encodedNameOfRegionB);
if (pair != null && pair.getFirst().getReplicaId() != HRegionInfo.DEFAULT_REPLICA_ID)
throw new IllegalArgumentException("Can't invoke merge on non-default regions directly");
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
try {
DispatchMergingRegionsRequest request = RequestConverter
.buildDispatchMergingRegionsRequest(encodedNameOfRegionA,
encodedNameOfRegionB, forcible);
master.dispatchMergingRegions(null, request);
} catch (DeserializationException de) {
LOG.error("Could not parse destination server name: " + de);
}
return null;
}
});
}
/**
* {@inheritDoc}
*/
@Override
public void split(final TableName tableName)
throws IOException {
split(tableName, null);
}
/**
* {@inheritDoc}
*/
@Override
public void splitRegion(final byte[] regionName)
throws IOException {
splitRegion(regionName, null);
}
/**
* @deprecated Use {@link #split(org.apache.hadoop.hbase.TableName)} or {@link #splitRegion
* (byte[])} instead.
*/
@Deprecated
public void split(final String tableNameOrRegionName)
throws IOException, InterruptedException {
split(Bytes.toBytes(tableNameOrRegionName));
}
/**
* @deprecated Use {@link #split(org.apache.hadoop.hbase.TableName)} or {@link #splitRegion
* (byte[])} instead.
*/
@Deprecated
public void split(final byte[] tableNameOrRegionName)
throws IOException, InterruptedException {
split(tableNameOrRegionName, null);
}
/**
* {@inheritDoc}
*/
@Override
public void split(final TableName tableName, final byte [] splitPoint)
throws IOException {
ZooKeeperWatcher zookeeper = null;
try {
checkTableExists(tableName);
zookeeper = new ZooKeeperWatcher(conf, ZK_IDENTIFIER_PREFIX + connection.toString(),
new ThrowableAbortable());
List<Pair<HRegionInfo, ServerName>> pairs;
if (TableName.META_TABLE_NAME.equals(tableName)) {
pairs = new MetaTableLocator().getMetaRegionsAndLocations(zookeeper);
} else {
pairs = MetaTableAccessor.getTableRegionsAndLocations(connection, tableName);
}
for (Pair<HRegionInfo, ServerName> pair: pairs) {
// May not be a server for a particular row
if (pair.getSecond() == null) continue;
HRegionInfo r = pair.getFirst();
// check for parents
if (r.isSplitParent()) continue;
// if a split point given, only split that particular region
if (r.getReplicaId() != HRegionInfo.DEFAULT_REPLICA_ID ||
(splitPoint != null && !r.containsRow(splitPoint))) continue;
// call out to region server to do split now
split(pair.getSecond(), pair.getFirst(), splitPoint);
}
} finally {
if (zookeeper != null) {
zookeeper.close();
}
}
}
/**
* {@inheritDoc}
*/
@Override
public void splitRegion(final byte[] regionName, final byte [] splitPoint)
throws IOException {
Pair<HRegionInfo, ServerName> regionServerPair = getRegion(regionName);
if (regionServerPair == null) {
throw new IllegalArgumentException("Invalid region: " + Bytes.toStringBinary(regionName));
}
if (regionServerPair.getFirst() != null &&
regionServerPair.getFirst().getReplicaId() != HRegionInfo.DEFAULT_REPLICA_ID) {
throw new IllegalArgumentException("Can't split replicas directly. "
+ "Replicas are auto-split when their primary is split.");
}
if (regionServerPair.getSecond() == null) {
throw new NoServerForRegionException(Bytes.toStringBinary(regionName));
}
split(regionServerPair.getSecond(), regionServerPair.getFirst(), splitPoint);
}
/**
* @deprecated Use {@link #split(org.apache.hadoop.hbase.TableName,
* byte[])} or {@link #splitRegion(byte[], byte[])} instead.
*/
@Deprecated
public void split(final String tableNameOrRegionName,
final String splitPoint) throws IOException {
split(Bytes.toBytes(tableNameOrRegionName), Bytes.toBytes(splitPoint));
}
/**
* @deprecated Use {@link #split(org.apache.hadoop.hbase.TableName,
* byte[])} or {@link #splitRegion(byte[], byte[])} instead.
*/
@Deprecated
public void split(final byte[] tableNameOrRegionName,
final byte [] splitPoint) throws IOException {
try {
splitRegion(tableNameOrRegionName, splitPoint);
} catch (IllegalArgumentException e) {
// Bad region, try table
split(TableName.valueOf(tableNameOrRegionName), splitPoint);
}
}
@VisibleForTesting
public void split(final ServerName sn, final HRegionInfo hri,
byte[] splitPoint) throws IOException {
if (hri.getStartKey() != null && splitPoint != null &&
Bytes.compareTo(hri.getStartKey(), splitPoint) == 0) {
throw new IOException("should not give a splitkey which equals to startkey!");
}
// TODO: This is not executed via retries
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
ProtobufUtil.split(admin, hri, splitPoint);
}
/**
* Modify an existing table, more IRB friendly version.
* Asynchronous operation. This means that it may be a while before your
* schema change is updated across all of the table.
*
* @param tableName name of table.
* @param htd modified description of the table
* @throws IOException if a remote or network exception occurs
*/
@Override
public void modifyTable(final TableName tableName, final HTableDescriptor htd)
throws IOException {
if (!tableName.equals(htd.getTableName())) {
throw new IllegalArgumentException("the specified table name '" + tableName +
"' doesn't match with the HTD one: " + htd.getTableName());
}
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
ModifyTableRequest request = RequestConverter.buildModifyTableRequest(tableName, htd);
master.modifyTable(null, request);
return null;
}
});
}
public void modifyTable(final byte[] tableName, final HTableDescriptor htd)
throws IOException {
modifyTable(TableName.valueOf(tableName), htd);
}
public void modifyTable(final String tableName, final HTableDescriptor htd)
throws IOException {
modifyTable(TableName.valueOf(tableName), htd);
}
/**
* @param regionName Name of a region.
* @return a pair of HRegionInfo and ServerName if <code>regionName</code> is
* a verified region name (we call {@link
* MetaTableAccessor#getRegion(HConnection, byte[])}
* else null.
* Throw IllegalArgumentException if <code>regionName</code> is null.
* @throws IOException
*/
Pair<HRegionInfo, ServerName> getRegion(final byte[] regionName) throws IOException {
if (regionName == null) {
throw new IllegalArgumentException("Pass a table name or region name");
}
Pair<HRegionInfo, ServerName> pair =
MetaTableAccessor.getRegion(connection, regionName);
if (pair == null) {
final AtomicReference<Pair<HRegionInfo, ServerName>> result =
new AtomicReference<Pair<HRegionInfo, ServerName>>(null);
final String encodedName = Bytes.toString(regionName);
MetaScannerVisitor visitor = new MetaScannerVisitorBase() {
@Override
public boolean processRow(Result data) throws IOException {
HRegionInfo info = HRegionInfo.getHRegionInfo(data);
if (info == null) {
LOG.warn("No serialized HRegionInfo in " + data);
return true;
}
RegionLocations rl = MetaTableAccessor.getRegionLocations(data);
boolean matched = false;
ServerName sn = null;
for (HRegionLocation h : rl.getRegionLocations()) {
if (h != null && encodedName.equals(h.getRegionInfo().getEncodedName())) {
sn = h.getServerName();
info = h.getRegionInfo();
matched = true;
}
}
if (!matched) return true;
result.set(new Pair<HRegionInfo, ServerName>(info, sn));
return false; // found the region, stop
}
};
MetaScanner.metaScan(connection, visitor, null);
pair = result.get();
}
return pair;
}
/**
* If the input is a region name, it is returned as is. If it's an
* encoded region name, the corresponding region is found from meta
* and its region name is returned. If we can't find any region in
* meta matching the input as either region name or encoded region
* name, the input is returned as is. We don't throw unknown
* region exception.
*/
private byte[] getRegionName(
final byte[] regionNameOrEncodedRegionName) throws IOException {
if (Bytes.equals(regionNameOrEncodedRegionName,
HRegionInfo.FIRST_META_REGIONINFO.getRegionName())
|| Bytes.equals(regionNameOrEncodedRegionName,
HRegionInfo.FIRST_META_REGIONINFO.getEncodedNameAsBytes())) {
return HRegionInfo.FIRST_META_REGIONINFO.getRegionName();
}
byte[] tmp = regionNameOrEncodedRegionName;
Pair<HRegionInfo, ServerName> regionServerPair = getRegion(regionNameOrEncodedRegionName);
if (regionServerPair != null && regionServerPair.getFirst() != null) {
tmp = regionServerPair.getFirst().getRegionName();
}
return tmp;
}
/**
* Check if table exists or not
* @param tableName Name of a table.
* @return tableName instance
* @throws IOException if a remote or network exception occurs.
* @throws TableNotFoundException if table does not exist.
*/
private TableName checkTableExists(final TableName tableName)
throws IOException {
if (!MetaTableAccessor.tableExists(connection, tableName)) {
throw new TableNotFoundException(tableName);
}
return tableName;
}
/**
* Shuts down the HBase cluster
* @throws IOException if a remote or network exception occurs
*/
@Override
public synchronized void shutdown() throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
master.shutdown(null,ShutdownRequest.newBuilder().build());
return null;
}
});
}
/**
* Shuts down the current HBase master only.
* Does not shutdown the cluster.
* @see #shutdown()
* @throws IOException if a remote or network exception occurs
*/
@Override
public synchronized void stopMaster() throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
master.stopMaster(null, StopMasterRequest.newBuilder().build());
return null;
}
});
}
/**
* Stop the designated regionserver
* @param hostnamePort Hostname and port delimited by a <code>:</code> as in
* <code>example.org:1234</code>
* @throws IOException if a remote or network exception occurs
*/
@Override
public synchronized void stopRegionServer(final String hostnamePort)
throws IOException {
String hostname = Addressing.parseHostname(hostnamePort);
int port = Addressing.parsePort(hostnamePort);
AdminService.BlockingInterface admin =
this.connection.getAdmin(ServerName.valueOf(hostname, port, 0));
StopServerRequest request = RequestConverter.buildStopServerRequest(
"Called by admin client " + this.connection.toString());
try {
admin.stopServer(null, request);
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
}
}
/**
* @return cluster status
* @throws IOException if a remote or network exception occurs
*/
@Override
public ClusterStatus getClusterStatus() throws IOException {
return executeCallable(new MasterCallable<ClusterStatus>(getConnection()) {
@Override
public ClusterStatus call(int callTimeout) throws ServiceException {
GetClusterStatusRequest req = RequestConverter.buildGetClusterStatusRequest();
return ClusterStatus.convert(master.getClusterStatus(null, req).getClusterStatus());
}
});
}
/**
* @return Configuration used by the instance.
*/
@Override
public Configuration getConfiguration() {
return this.conf;
}
/**
* Create a new namespace
* @param descriptor descriptor which describes the new namespace
* @throws IOException
*/
@Override
public void createNamespace(final NamespaceDescriptor descriptor) throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws Exception {
master.createNamespace(null,
CreateNamespaceRequest.newBuilder()
.setNamespaceDescriptor(ProtobufUtil
.toProtoNamespaceDescriptor(descriptor)).build()
);
return null;
}
});
}
/**
* Modify an existing namespace
* @param descriptor descriptor which describes the new namespace
* @throws IOException
*/
@Override
public void modifyNamespace(final NamespaceDescriptor descriptor) throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws Exception {
master.modifyNamespace(null, ModifyNamespaceRequest.newBuilder().
setNamespaceDescriptor(ProtobufUtil.toProtoNamespaceDescriptor(descriptor)).build());
return null;
}
});
}
/**
* Delete an existing namespace. Only empty namespaces (no tables) can be removed.
* @param name namespace name
* @throws IOException
*/
@Override
public void deleteNamespace(final String name) throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws Exception {
master.deleteNamespace(null, DeleteNamespaceRequest.newBuilder().
setNamespaceName(name).build());
return null;
}
});
}
/**
* Get a namespace descriptor by name
* @param name name of namespace descriptor
* @return A descriptor
* @throws IOException
*/
@Override
public NamespaceDescriptor getNamespaceDescriptor(final String name) throws IOException {
return
executeCallable(new MasterCallable<NamespaceDescriptor>(getConnection()) {
@Override
public NamespaceDescriptor call(int callTimeout) throws Exception {
return ProtobufUtil.toNamespaceDescriptor(
master.getNamespaceDescriptor(null, GetNamespaceDescriptorRequest.newBuilder().
setNamespaceName(name).build()).getNamespaceDescriptor());
}
});
}
/**
* List available namespace descriptors
* @return List of descriptors
* @throws IOException
*/
@Override
public NamespaceDescriptor[] listNamespaceDescriptors() throws IOException {
return
executeCallable(new MasterCallable<NamespaceDescriptor[]>(getConnection()) {
@Override
public NamespaceDescriptor[] call(int callTimeout) throws Exception {
List<HBaseProtos.NamespaceDescriptor> list =
master.listNamespaceDescriptors(null, ListNamespaceDescriptorsRequest.newBuilder().
build()).getNamespaceDescriptorList();
NamespaceDescriptor[] res = new NamespaceDescriptor[list.size()];
for(int i = 0; i < list.size(); i++) {
res[i] = ProtobufUtil.toNamespaceDescriptor(list.get(i));
}
return res;
}
});
}
/**
* Get list of table descriptors by namespace
* @param name namespace name
* @return A descriptor
* @throws IOException
*/
@Override
public HTableDescriptor[] listTableDescriptorsByNamespace(final String name) throws IOException {
return
executeCallable(new MasterCallable<HTableDescriptor[]>(getConnection()) {
@Override
public HTableDescriptor[] call(int callTimeout) throws Exception {
List<TableSchema> list =
master.listTableDescriptorsByNamespace(null, ListTableDescriptorsByNamespaceRequest.
newBuilder().setNamespaceName(name).build()).getTableSchemaList();
HTableDescriptor[] res = new HTableDescriptor[list.size()];
for(int i=0; i < list.size(); i++) {
res[i] = HTableDescriptor.convert(list.get(i));
}
return res;
}
});
}
/**
* Get list of table names by namespace
* @param name namespace name
* @return The list of table names in the namespace
* @throws IOException
*/
@Override
public TableName[] listTableNamesByNamespace(final String name) throws IOException {
return
executeCallable(new MasterCallable<TableName[]>(getConnection()) {
@Override
public TableName[] call(int callTimeout) throws Exception {
List<HBaseProtos.TableName> tableNames =
master.listTableNamesByNamespace(null, ListTableNamesByNamespaceRequest.
newBuilder().setNamespaceName(name).build())
.getTableNameList();
TableName[] result = new TableName[tableNames.size()];
for (int i = 0; i < tableNames.size(); i++) {
result[i] = ProtobufUtil.toTableName(tableNames.get(i));
}
return result;
}
});
}
/**
* Check to see if HBase is running. Throw an exception if not.
* @param conf system configuration
* @throws MasterNotRunningException if the master is not running
* @throws ZooKeeperConnectionException if unable to connect to zookeeper
*/
// Used by tests and by the Merge tool. Merge tool uses it to figure if HBase is up or not.
public static void checkHBaseAvailable(Configuration conf)
throws MasterNotRunningException, ZooKeeperConnectionException, ServiceException, IOException {
Configuration copyOfConf = HBaseConfiguration.create(conf);
// We set it to make it fail as soon as possible if HBase is not available
copyOfConf.setInt(HConstants.HBASE_CLIENT_RETRIES_NUMBER, 1);
copyOfConf.setInt("zookeeper.recovery.retry", 0);
try (ClusterConnection connection =
(ClusterConnection)ConnectionFactory.createConnection(copyOfConf)) {
// Check ZK first.
// If the connection exists, we may have a connection to ZK that does not work anymore
ZooKeeperKeepAliveConnection zkw = null;
try {
// This is NASTY. FIX!!!! Dependent on internal implementation! TODO
zkw = ((ConnectionManager.HConnectionImplementation)connection).
getKeepAliveZooKeeperWatcher();
zkw.getRecoverableZooKeeper().getZooKeeper().exists(zkw.baseZNode, false);
} catch (IOException e) {
throw new ZooKeeperConnectionException("Can't connect to ZooKeeper", e);
} catch (InterruptedException e) {
throw (InterruptedIOException)
new InterruptedIOException("Can't connect to ZooKeeper").initCause(e);
} catch (KeeperException e) {
throw new ZooKeeperConnectionException("Can't connect to ZooKeeper", e);
} finally {
if (zkw != null) {
zkw.close();
}
}
connection.isMasterRunning();
}
}
/**
* get the regions of a given table.
*
* @param tableName the name of the table
* @return Ordered list of {@link HRegionInfo}.
* @throws IOException
*/
@Override
public List<HRegionInfo> getTableRegions(final TableName tableName)
throws IOException {
ZooKeeperWatcher zookeeper =
new ZooKeeperWatcher(conf, ZK_IDENTIFIER_PREFIX + connection.toString(),
new ThrowableAbortable());
List<HRegionInfo> regions = null;
try {
if (TableName.META_TABLE_NAME.equals(tableName)) {
regions = new MetaTableLocator().getMetaRegions(zookeeper);
} else {
regions = MetaTableAccessor.getTableRegions(connection, tableName, true);
}
} finally {
zookeeper.close();
}
return regions;
}
public List<HRegionInfo> getTableRegions(final byte[] tableName)
throws IOException {
return getTableRegions(TableName.valueOf(tableName));
}
@Override
public synchronized void close() throws IOException {
if (cleanupConnectionOnClose && this.connection != null && !this.closed) {
this.connection.close();
this.closed = true;
}
}
/**
* Get tableDescriptors
* @param tableNames List of table names
* @return HTD[] the tableDescriptor
* @throws IOException if a remote or network exception occurs
*/
@Override
public HTableDescriptor[] getTableDescriptorsByTableName(final List<TableName> tableNames)
throws IOException {
return executeCallable(new MasterCallable<HTableDescriptor[]>(getConnection()) {
@Override
public HTableDescriptor[] call(int callTimeout) throws Exception {
GetTableDescriptorsRequest req =
RequestConverter.buildGetTableDescriptorsRequest(tableNames);
return ProtobufUtil.getHTableDescriptorArray(master.getTableDescriptors(null, req));
}
});
}
/**
* Get tableDescriptor
* @param tableName one table name
* @return HTD the HTableDescriptor or null if the table not exists
* @throws IOException if a remote or network exception occurs
*/
private HTableDescriptor getTableDescriptorByTableName(TableName tableName)
throws IOException {
List<TableName> tableNames = new ArrayList<TableName>(1);
tableNames.add(tableName);
HTableDescriptor[] htdl = getTableDescriptorsByTableName(tableNames);
if (htdl == null || htdl.length == 0) {
return null;
}
else {
return htdl[0];
}
}
/**
* Get tableDescriptors
* @param names List of table names
* @return HTD[] the tableDescriptor
* @throws IOException if a remote or network exception occurs
*/
@Override
public HTableDescriptor[] getTableDescriptors(List<String> names)
throws IOException {
List<TableName> tableNames = new ArrayList<TableName>(names.size());
for(String name : names) {
tableNames.add(TableName.valueOf(name));
}
return getTableDescriptorsByTableName(tableNames);
}
private RollWALWriterResponse rollWALWriterImpl(final ServerName sn) throws IOException,
FailedLogCloseException {
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
RollWALWriterRequest request = RequestConverter.buildRollWALWriterRequest();
try {
return admin.rollWALWriter(null, request);
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
}
}
/**
* Roll the log writer. I.e. when using a file system based write ahead log,
* start writing log messages to a new file.
*
* Note that when talking to a version 1.0+ HBase deployment, the rolling is asynchronous.
* This method will return as soon as the roll is requested and the return value will
* always be null. Additionally, the named region server may schedule store flushes at the
* request of the wal handling the roll request.
*
* When talking to a 0.98 or older HBase deployment, the rolling is synchronous and the
* return value may be either null or a list of encoded region names.
*
* @param serverName
* The servername of the regionserver. A server name is made of host,
* port and startcode. This is mandatory. Here is an example:
* <code> host187.example.com,60020,1289493121758</code>
* @return a set of {@link HRegionInfo#getEncodedName()} that would allow the wal to
* clean up some underlying files. null if there's nothing to flush.
* @throws IOException if a remote or network exception occurs
* @throws FailedLogCloseException
* @deprecated use {@link #rollWALWriter(ServerName)}
*/
@Deprecated
public synchronized byte[][] rollHLogWriter(String serverName)
throws IOException, FailedLogCloseException {
ServerName sn = ServerName.valueOf(serverName);
final RollWALWriterResponse response = rollWALWriterImpl(sn);
int regionCount = response.getRegionToFlushCount();
if (0 == regionCount) {
return null;
}
byte[][] regionsToFlush = new byte[regionCount][];
for (int i = 0; i < regionCount; i++) {
ByteString region = response.getRegionToFlush(i);
regionsToFlush[i] = region.toByteArray();
}
return regionsToFlush;
}
@Override
public synchronized void rollWALWriter(ServerName serverName)
throws IOException, FailedLogCloseException {
rollWALWriterImpl(serverName);
}
@Override
public String[] getMasterCoprocessors() {
try {
return getClusterStatus().getMasterCoprocessors();
} catch (IOException e) {
LOG.error("Could not getClusterStatus()",e);
return null;
}
}
/**
* {@inheritDoc}
*/
@Override
public CompactionState getCompactionState(final TableName tableName)
throws IOException {
CompactionState state = CompactionState.NONE;
ZooKeeperWatcher zookeeper =
new ZooKeeperWatcher(conf, ZK_IDENTIFIER_PREFIX + connection.toString(),
new ThrowableAbortable());
try {
checkTableExists(tableName);
List<Pair<HRegionInfo, ServerName>> pairs;
if (TableName.META_TABLE_NAME.equals(tableName)) {
pairs = new MetaTableLocator().getMetaRegionsAndLocations(zookeeper);
} else {
pairs = MetaTableAccessor.getTableRegionsAndLocations(connection, tableName);
}
for (Pair<HRegionInfo, ServerName> pair: pairs) {
if (pair.getFirst().isOffline()) continue;
if (pair.getSecond() == null) continue;
try {
ServerName sn = pair.getSecond();
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
GetRegionInfoRequest request = RequestConverter.buildGetRegionInfoRequest(
pair.getFirst().getRegionName(), true);
GetRegionInfoResponse response = admin.getRegionInfo(null, request);
switch (response.getCompactionState()) {
case MAJOR_AND_MINOR:
return CompactionState.MAJOR_AND_MINOR;
case MAJOR:
if (state == CompactionState.MINOR) {
return CompactionState.MAJOR_AND_MINOR;
}
state = CompactionState.MAJOR;
break;
case MINOR:
if (state == CompactionState.MAJOR) {
return CompactionState.MAJOR_AND_MINOR;
}
state = CompactionState.MINOR;
break;
case NONE:
default: // nothing, continue
}
} catch (NotServingRegionException e) {
if (LOG.isDebugEnabled()) {
LOG.debug("Trying to get compaction state of " +
pair.getFirst() + ": " +
StringUtils.stringifyException(e));
}
} catch (RemoteException e) {
if (e.getMessage().indexOf(NotServingRegionException.class.getName()) >= 0) {
if (LOG.isDebugEnabled()) {
LOG.debug("Trying to get compaction state of " + pair.getFirst() + ": "
+ StringUtils.stringifyException(e));
}
} else {
throw e;
}
}
}
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
} finally {
zookeeper.close();
}
return state;
}
/**
* {@inheritDoc}
*/
@Override
public CompactionState getCompactionStateForRegion(final byte[] regionName)
throws IOException {
try {
Pair<HRegionInfo, ServerName> regionServerPair = getRegion(regionName);
if (regionServerPair == null) {
throw new IllegalArgumentException("Invalid region: " + Bytes.toStringBinary(regionName));
}
if (regionServerPair.getSecond() == null) {
throw new NoServerForRegionException(Bytes.toStringBinary(regionName));
}
ServerName sn = regionServerPair.getSecond();
AdminService.BlockingInterface admin = this.connection.getAdmin(sn);
GetRegionInfoRequest request = RequestConverter.buildGetRegionInfoRequest(
regionServerPair.getFirst().getRegionName(), true);
GetRegionInfoResponse response = admin.getRegionInfo(null, request);
return response.getCompactionState();
} catch (ServiceException se) {
throw ProtobufUtil.getRemoteException(se);
}
}
/**
* @deprecated Use {@link #getCompactionState(org.apache.hadoop.hbase.TableName)} or {@link
* #getCompactionStateForRegion(byte[])} instead.
*/
@Deprecated
public CompactionState getCompactionState(final String tableNameOrRegionName)
throws IOException, InterruptedException {
return getCompactionState(Bytes.toBytes(tableNameOrRegionName));
}
/**
* @deprecated Use {@link #getCompactionState(org.apache.hadoop.hbase.TableName)} or {@link
* #getCompactionStateForRegion(byte[])} instead.
*/
@Deprecated
public CompactionState getCompactionState(final byte[] tableNameOrRegionName)
throws IOException, InterruptedException {
try {
return getCompactionStateForRegion(tableNameOrRegionName);
} catch (IllegalArgumentException e) {
// Invalid region, try table
return getCompactionState(TableName.valueOf(tableNameOrRegionName));
}
}
/**
* Take a snapshot for the given table. If the table is enabled, a FLUSH-type snapshot will be
* taken. If the table is disabled, an offline snapshot is taken.
* <p>
* Snapshots are considered unique based on <b>the name of the snapshot</b>. Attempts to take a
* snapshot with the same name (even a different type or with different parameters) will fail with
* a {@link SnapshotCreationException} indicating the duplicate naming.
* <p>
* Snapshot names follow the same naming constraints as tables in HBase. See
* {@link org.apache.hadoop.hbase.TableName#isLegalFullyQualifiedTableName(byte[])}.
* @param snapshotName name of the snapshot to be created
* @param tableName name of the table for which snapshot is created
* @throws IOException if a remote or network exception occurs
* @throws SnapshotCreationException if snapshot creation failed
* @throws IllegalArgumentException if the snapshot request is formatted incorrectly
*/
@Override
public void snapshot(final String snapshotName,
final TableName tableName) throws IOException,
SnapshotCreationException, IllegalArgumentException {
snapshot(snapshotName, tableName, SnapshotDescription.Type.FLUSH);
}
public void snapshot(final String snapshotName,
final String tableName) throws IOException,
SnapshotCreationException, IllegalArgumentException {
snapshot(snapshotName, TableName.valueOf(tableName),
SnapshotDescription.Type.FLUSH);
}
/**
* Create snapshot for the given table of given flush type.
* <p>
* Snapshots are considered unique based on <b>the name of the snapshot</b>. Attempts to take a
* snapshot with the same name (even a different type or with different parameters) will fail with
* a {@link SnapshotCreationException} indicating the duplicate naming.
* <p>
* Snapshot names follow the same naming constraints as tables in HBase.
* @param snapshotName name of the snapshot to be created
* @param tableName name of the table for which snapshot is created
* @param flushType if the snapshot should be taken without flush memstore first
* @throws IOException if a remote or network exception occurs
* @throws SnapshotCreationException if snapshot creation failed
* @throws IllegalArgumentException if the snapshot request is formatted incorrectly
*/
public void snapshot(final byte[] snapshotName, final byte[] tableName,
final SnapshotDescription.Type flushType) throws
IOException, SnapshotCreationException, IllegalArgumentException {
snapshot(Bytes.toString(snapshotName), Bytes.toString(tableName), flushType);
}
/**
public void snapshot(final String snapshotName,
* Create a timestamp consistent snapshot for the given table.
final byte[] tableName) throws IOException,
* <p>
* Snapshots are considered unique based on <b>the name of the snapshot</b>. Attempts to take a
* snapshot with the same name (even a different type or with different parameters) will fail with
* a {@link SnapshotCreationException} indicating the duplicate naming.
* <p>
* Snapshot names follow the same naming constraints as tables in HBase.
* @param snapshotName name of the snapshot to be created
* @param tableName name of the table for which snapshot is created
* @throws IOException if a remote or network exception occurs
* @throws SnapshotCreationException if snapshot creation failed
* @throws IllegalArgumentException if the snapshot request is formatted incorrectly
*/
@Override
public void snapshot(final byte[] snapshotName,
final TableName tableName) throws IOException,
SnapshotCreationException, IllegalArgumentException {
snapshot(Bytes.toString(snapshotName), tableName, SnapshotDescription.Type.FLUSH);
}
public void snapshot(final byte[] snapshotName,
final byte[] tableName) throws IOException,
SnapshotCreationException, IllegalArgumentException {
snapshot(Bytes.toString(snapshotName), TableName.valueOf(tableName),
SnapshotDescription.Type.FLUSH);
}
/**
* Create typed snapshot of the table.
* <p>
* Snapshots are considered unique based on <b>the name of the snapshot</b>. Attempts to take a
* snapshot with the same name (even a different type or with different parameters) will fail with
* a {@link SnapshotCreationException} indicating the duplicate naming.
* <p>
* Snapshot names follow the same naming constraints as tables in HBase. See
* {@link org.apache.hadoop.hbase.TableName#isLegalFullyQualifiedTableName(byte[])}.
* <p>
* @param snapshotName name to give the snapshot on the filesystem. Must be unique from all other
* snapshots stored on the cluster
* @param tableName name of the table to snapshot
* @param type type of snapshot to take
* @throws IOException we fail to reach the master
* @throws SnapshotCreationException if snapshot creation failed
* @throws IllegalArgumentException if the snapshot request is formatted incorrectly
*/
@Override
public void snapshot(final String snapshotName,
final TableName tableName,
SnapshotDescription.Type type) throws IOException, SnapshotCreationException,
IllegalArgumentException {
SnapshotDescription.Builder builder = SnapshotDescription.newBuilder();
builder.setTable(tableName.getNameAsString());
builder.setName(snapshotName);
builder.setType(type);
snapshot(builder.build());
}
public void snapshot(final String snapshotName,
final String tableName,
SnapshotDescription.Type type) throws IOException, SnapshotCreationException,
IllegalArgumentException {
snapshot(snapshotName, TableName.valueOf(tableName), type);
}
public void snapshot(final String snapshotName,
final byte[] tableName,
SnapshotDescription.Type type) throws IOException, SnapshotCreationException,
IllegalArgumentException {
snapshot(snapshotName, TableName.valueOf(tableName), type);
}
/**
* Take a snapshot and wait for the server to complete that snapshot (blocking).
* <p>
* Only a single snapshot should be taken at a time for an instance of HBase, or results may be
* undefined (you can tell multiple HBase clusters to snapshot at the same time, but only one at a
* time for a single cluster).
* <p>
* Snapshots are considered unique based on <b>the name of the snapshot</b>. Attempts to take a
* snapshot with the same name (even a different type or with different parameters) will fail with
* a {@link SnapshotCreationException} indicating the duplicate naming.
* <p>
* Snapshot names follow the same naming constraints as tables in HBase. See
* {@link org.apache.hadoop.hbase.TableName#isLegalFullyQualifiedTableName(byte[])}.
* <p>
* You should probably use {@link #snapshot(String, String)} or {@link #snapshot(byte[], byte[])}
* unless you are sure about the type of snapshot that you want to take.
* @param snapshot snapshot to take
* @throws IOException or we lose contact with the master.
* @throws SnapshotCreationException if snapshot failed to be taken
* @throws IllegalArgumentException if the snapshot request is formatted incorrectly
*/
@Override
public void snapshot(SnapshotDescription snapshot) throws IOException, SnapshotCreationException,
IllegalArgumentException {
// actually take the snapshot
SnapshotResponse response = takeSnapshotAsync(snapshot);
final IsSnapshotDoneRequest request = IsSnapshotDoneRequest.newBuilder().setSnapshot(snapshot)
.build();
IsSnapshotDoneResponse done = null;
long start = EnvironmentEdgeManager.currentTime();
long max = response.getExpectedTimeout();
long maxPauseTime = max / this.numRetries;
int tries = 0;
LOG.debug("Waiting a max of " + max + " ms for snapshot '" +
ClientSnapshotDescriptionUtils.toString(snapshot) + "'' to complete. (max " +
maxPauseTime + " ms per retry)");
while (tries == 0
|| ((EnvironmentEdgeManager.currentTime() - start) < max && !done.getDone())) {
try {
// sleep a backoff <= pauseTime amount
long sleep = getPauseTime(tries++);
sleep = sleep > maxPauseTime ? maxPauseTime : sleep;
LOG.debug("(#" + tries + ") Sleeping: " + sleep +
"ms while waiting for snapshot completion.");
Thread.sleep(sleep);
} catch (InterruptedException e) {
throw (InterruptedIOException)new InterruptedIOException("Interrupted").initCause(e);
}
LOG.debug("Getting current status of snapshot from master...");
done = executeCallable(new MasterCallable<IsSnapshotDoneResponse>(getConnection()) {
@Override
public IsSnapshotDoneResponse call(int callTimeout) throws ServiceException {
return master.isSnapshotDone(null, request);
}
});
}
if (!done.getDone()) {
throw new SnapshotCreationException("Snapshot '" + snapshot.getName()
+ "' wasn't completed in expectedTime:" + max + " ms", snapshot);
}
}
/**
* Take a snapshot without waiting for the server to complete that snapshot (asynchronous)
* <p>
* Only a single snapshot should be taken at a time, or results may be undefined.
* @param snapshot snapshot to take
* @return response from the server indicating the max time to wait for the snapshot
* @throws IOException if the snapshot did not succeed or we lose contact with the master.
* @throws SnapshotCreationException if snapshot creation failed
* @throws IllegalArgumentException if the snapshot request is formatted incorrectly
*/
@Override
public SnapshotResponse takeSnapshotAsync(SnapshotDescription snapshot) throws IOException,
SnapshotCreationException {
ClientSnapshotDescriptionUtils.assertSnapshotRequestIsValid(snapshot);
final SnapshotRequest request = SnapshotRequest.newBuilder().setSnapshot(snapshot)
.build();
// run the snapshot on the master
return executeCallable(new MasterCallable<SnapshotResponse>(getConnection()) {
@Override
public SnapshotResponse call(int callTimeout) throws ServiceException {
return master.snapshot(null, request);
}
});
}
/**
* Check the current state of the passed snapshot.
* <p>
* There are three possible states:
* <ol>
* <li>running - returns <tt>false</tt></li>
* <li>finished - returns <tt>true</tt></li>
* <li>finished with error - throws the exception that caused the snapshot to fail</li>
* </ol>
* <p>
* The cluster only knows about the most recent snapshot. Therefore, if another snapshot has been
* run/started since the snapshot your are checking, you will recieve an
* {@link UnknownSnapshotException}.
* @param snapshot description of the snapshot to check
* @return <tt>true</tt> if the snapshot is completed, <tt>false</tt> if the snapshot is still
* running
* @throws IOException if we have a network issue
* @throws HBaseSnapshotException if the snapshot failed
* @throws UnknownSnapshotException if the requested snapshot is unknown
*/
@Override
public boolean isSnapshotFinished(final SnapshotDescription snapshot)
throws IOException, HBaseSnapshotException, UnknownSnapshotException {
return executeCallable(new MasterCallable<IsSnapshotDoneResponse>(getConnection()) {
@Override
public IsSnapshotDoneResponse call(int callTimeout) throws ServiceException {
return master.isSnapshotDone(null,
IsSnapshotDoneRequest.newBuilder().setSnapshot(snapshot).build());
}
}).getDone();
}
/**
* Restore the specified snapshot on the original table. (The table must be disabled)
* If the "hbase.snapshot.restore.take.failsafe.snapshot" configuration property
* is set to true, a snapshot of the current table is taken
* before executing the restore operation.
* In case of restore failure, the failsafe snapshot will be restored.
* If the restore completes without problem the failsafe snapshot is deleted.
*
* @param snapshotName name of the snapshot to restore
* @throws IOException if a remote or network exception occurs
* @throws RestoreSnapshotException if snapshot failed to be restored
* @throws IllegalArgumentException if the restore request is formatted incorrectly
*/
@Override
public void restoreSnapshot(final byte[] snapshotName)
throws IOException, RestoreSnapshotException {
restoreSnapshot(Bytes.toString(snapshotName));
}
/**
* Restore the specified snapshot on the original table. (The table must be disabled)
* If the "hbase.snapshot.restore.take.failsafe.snapshot" configuration property
* is set to true, a snapshot of the current table is taken
* before executing the restore operation.
* In case of restore failure, the failsafe snapshot will be restored.
* If the restore completes without problem the failsafe snapshot is deleted.
*
* @param snapshotName name of the snapshot to restore
* @throws IOException if a remote or network exception occurs
* @throws RestoreSnapshotException if snapshot failed to be restored
* @throws IllegalArgumentException if the restore request is formatted incorrectly
*/
@Override
public void restoreSnapshot(final String snapshotName)
throws IOException, RestoreSnapshotException {
boolean takeFailSafeSnapshot =
conf.getBoolean("hbase.snapshot.restore.take.failsafe.snapshot", false);
restoreSnapshot(snapshotName, takeFailSafeSnapshot);
}
/**
* Restore the specified snapshot on the original table. (The table must be disabled)
* If 'takeFailSafeSnapshot' is set to true, a snapshot of the current table is taken
* before executing the restore operation.
* In case of restore failure, the failsafe snapshot will be restored.
* If the restore completes without problem the failsafe snapshot is deleted.
*
* The failsafe snapshot name is configurable by using the property
* "hbase.snapshot.restore.failsafe.name".
*
* @param snapshotName name of the snapshot to restore
* @param takeFailSafeSnapshot true if the failsafe snapshot should be taken
* @throws IOException if a remote or network exception occurs
* @throws RestoreSnapshotException if snapshot failed to be restored
* @throws IllegalArgumentException if the restore request is formatted incorrectly
*/
@Override
public void restoreSnapshot(final byte[] snapshotName, final boolean takeFailSafeSnapshot)
throws IOException, RestoreSnapshotException {
restoreSnapshot(Bytes.toString(snapshotName), takeFailSafeSnapshot);
}
/**
* Restore the specified snapshot on the original table. (The table must be disabled)
* If 'takeFailSafeSnapshot' is set to true, a snapshot of the current table is taken
* before executing the restore operation.
* In case of restore failure, the failsafe snapshot will be restored.
* If the restore completes without problem the failsafe snapshot is deleted.
*
* The failsafe snapshot name is configurable by using the property
* "hbase.snapshot.restore.failsafe.name".
*
* @param snapshotName name of the snapshot to restore
* @param takeFailSafeSnapshot true if the failsafe snapshot should be taken
* @throws IOException if a remote or network exception occurs
* @throws RestoreSnapshotException if snapshot failed to be restored
* @throws IllegalArgumentException if the restore request is formatted incorrectly
*/
@Override
public void restoreSnapshot(final String snapshotName, boolean takeFailSafeSnapshot)
throws IOException, RestoreSnapshotException {
TableName tableName = null;
for (SnapshotDescription snapshotInfo: listSnapshots()) {
if (snapshotInfo.getName().equals(snapshotName)) {
tableName = TableName.valueOf(snapshotInfo.getTable());
break;
}
}
if (tableName == null) {
throw new RestoreSnapshotException(
"Unable to find the table name for snapshot=" + snapshotName);
}
// The table does not exists, switch to clone.
if (!tableExists(tableName)) {
cloneSnapshot(snapshotName, tableName);
return;
}
// Check if the table is disabled
if (!isTableDisabled(tableName)) {
throw new TableNotDisabledException(tableName);
}
// Take a snapshot of the current state
String failSafeSnapshotSnapshotName = null;
if (takeFailSafeSnapshot) {
failSafeSnapshotSnapshotName = conf.get("hbase.snapshot.restore.failsafe.name",
"hbase-failsafe-{snapshot.name}-{restore.timestamp}");
failSafeSnapshotSnapshotName = failSafeSnapshotSnapshotName
.replace("{snapshot.name}", snapshotName)
.replace("{table.name}", tableName.toString().replace(TableName.NAMESPACE_DELIM, '.'))
.replace("{restore.timestamp}", String.valueOf(EnvironmentEdgeManager.currentTime()));
LOG.info("Taking restore-failsafe snapshot: " + failSafeSnapshotSnapshotName);
snapshot(failSafeSnapshotSnapshotName, tableName);
}
try {
// Restore snapshot
internalRestoreSnapshot(snapshotName, tableName);
} catch (IOException e) {
// Somthing went wrong during the restore...
// if the pre-restore snapshot is available try to rollback
if (takeFailSafeSnapshot) {
try {
internalRestoreSnapshot(failSafeSnapshotSnapshotName, tableName);
String msg = "Restore snapshot=" + snapshotName +
" failed. Rollback to snapshot=" + failSafeSnapshotSnapshotName + " succeeded.";
LOG.error(msg, e);
throw new RestoreSnapshotException(msg, e);
} catch (IOException ex) {
String msg = "Failed to restore and rollback to snapshot=" + failSafeSnapshotSnapshotName;
LOG.error(msg, ex);
throw new RestoreSnapshotException(msg, e);
}
} else {
throw new RestoreSnapshotException("Failed to restore snapshot=" + snapshotName, e);
}
}
// If the restore is succeeded, delete the pre-restore snapshot
if (takeFailSafeSnapshot) {
try {
LOG.info("Deleting restore-failsafe snapshot: " + failSafeSnapshotSnapshotName);
deleteSnapshot(failSafeSnapshotSnapshotName);
} catch (IOException e) {
LOG.error("Unable to remove the failsafe snapshot: " + failSafeSnapshotSnapshotName, e);
}
}
}
/**
* Create a new table by cloning the snapshot content.
*
* @param snapshotName name of the snapshot to be cloned
* @param tableName name of the table where the snapshot will be restored
* @throws IOException if a remote or network exception occurs
* @throws TableExistsException if table to be created already exists
* @throws RestoreSnapshotException if snapshot failed to be cloned
* @throws IllegalArgumentException if the specified table has not a valid name
*/
public void cloneSnapshot(final byte[] snapshotName, final byte[] tableName)
throws IOException, TableExistsException, RestoreSnapshotException {
cloneSnapshot(Bytes.toString(snapshotName), TableName.valueOf(tableName));
}
/**
* Create a new table by cloning the snapshot content.
*
* @param snapshotName name of the snapshot to be cloned
* @param tableName name of the table where the snapshot will be restored
* @throws IOException if a remote or network exception occurs
* @throws TableExistsException if table to be created already exists
* @throws RestoreSnapshotException if snapshot failed to be cloned
* @throws IllegalArgumentException if the specified table has not a valid name
*/
@Override
public void cloneSnapshot(final byte[] snapshotName, final TableName tableName)
throws IOException, TableExistsException, RestoreSnapshotException {
cloneSnapshot(Bytes.toString(snapshotName), tableName);
}
/**
* Create a new table by cloning the snapshot content.
*
* @param snapshotName name of the snapshot to be cloned
* @param tableName name of the table where the snapshot will be restored
* @throws IOException if a remote or network exception occurs
* @throws TableExistsException if table to be created already exists
* @throws RestoreSnapshotException if snapshot failed to be cloned
* @throws IllegalArgumentException if the specified table has not a valid name
*/
public void cloneSnapshot(final String snapshotName, final String tableName)
throws IOException, TableExistsException, RestoreSnapshotException, InterruptedException {
cloneSnapshot(snapshotName, TableName.valueOf(tableName));
}
/**
* Create a new table by cloning the snapshot content.
*
* @param snapshotName name of the snapshot to be cloned
* @param tableName name of the table where the snapshot will be restored
* @throws IOException if a remote or network exception occurs
* @throws TableExistsException if table to be created already exists
* @throws RestoreSnapshotException if snapshot failed to be cloned
* @throws IllegalArgumentException if the specified table has not a valid name
*/
@Override
public void cloneSnapshot(final String snapshotName, final TableName tableName)
throws IOException, TableExistsException, RestoreSnapshotException {
if (tableExists(tableName)) {
throw new TableExistsException(tableName);
}
internalRestoreSnapshot(snapshotName, tableName);
waitUntilTableIsEnabled(tableName);
}
/**
* Execute a distributed procedure on a cluster synchronously with return data
*
* @param signature A distributed procedure is uniquely identified
* by its signature (default the root ZK node name of the procedure).
* @param instance The instance name of the procedure. For some procedures, this parameter is
* optional.
* @param props Property/Value pairs of properties passing to the procedure
* @return data returned after procedure execution. null if no return data.
* @throws IOException
*/
@Override
public byte[] execProcedureWithRet(String signature, String instance,
Map<String, String> props) throws IOException {
ProcedureDescription.Builder builder = ProcedureDescription.newBuilder();
builder.setSignature(signature).setInstance(instance);
for (Entry<String, String> entry : props.entrySet()) {
NameStringPair pair = NameStringPair.newBuilder().setName(entry.getKey())
.setValue(entry.getValue()).build();
builder.addConfiguration(pair);
}
final ExecProcedureRequest request = ExecProcedureRequest.newBuilder()
.setProcedure(builder.build()).build();
// run the procedure on the master
ExecProcedureResponse response = executeCallable(new MasterCallable<ExecProcedureResponse>(
getConnection()) {
@Override
public ExecProcedureResponse call(int callTimeout) throws ServiceException {
return master.execProcedureWithRet(null, request);
}
});
return response.hasReturnData() ? response.getReturnData().toByteArray() : null;
}
/**
* Execute a distributed procedure on a cluster.
*
* @param signature A distributed procedure is uniquely identified
* by its signature (default the root ZK node name of the procedure).
* @param instance The instance name of the procedure. For some procedures, this parameter is
* optional.
* @param props Property/Value pairs of properties passing to the procedure
* @throws IOException
*/
@Override
public void execProcedure(String signature, String instance,
Map<String, String> props) throws IOException {
ProcedureDescription.Builder builder = ProcedureDescription.newBuilder();
builder.setSignature(signature).setInstance(instance);
for (Entry<String, String> entry : props.entrySet()) {
NameStringPair pair = NameStringPair.newBuilder().setName(entry.getKey())
.setValue(entry.getValue()).build();
builder.addConfiguration(pair);
}
final ExecProcedureRequest request = ExecProcedureRequest.newBuilder()
.setProcedure(builder.build()).build();
// run the procedure on the master
ExecProcedureResponse response = executeCallable(new MasterCallable<ExecProcedureResponse>(
getConnection()) {
@Override
public ExecProcedureResponse call(int callTimeout) throws ServiceException {
return master.execProcedure(null, request);
}
});
long start = EnvironmentEdgeManager.currentTime();
long max = response.getExpectedTimeout();
long maxPauseTime = max / this.numRetries;
int tries = 0;
LOG.debug("Waiting a max of " + max + " ms for procedure '" +
signature + " : " + instance + "'' to complete. (max " + maxPauseTime + " ms per retry)");
boolean done = false;
while (tries == 0
|| ((EnvironmentEdgeManager.currentTime() - start) < max && !done)) {
try {
// sleep a backoff <= pauseTime amount
long sleep = getPauseTime(tries++);
sleep = sleep > maxPauseTime ? maxPauseTime : sleep;
LOG.debug("(#" + tries + ") Sleeping: " + sleep +
"ms while waiting for procedure completion.");
Thread.sleep(sleep);
} catch (InterruptedException e) {
throw (InterruptedIOException)new InterruptedIOException("Interrupted").initCause(e);
}
LOG.debug("Getting current status of procedure from master...");
done = isProcedureFinished(signature, instance, props);
}
if (!done) {
throw new IOException("Procedure '" + signature + " : " + instance
+ "' wasn't completed in expectedTime:" + max + " ms");
}
}
/**
* Check the current state of the specified procedure.
* <p>
* There are three possible states:
* <ol>
* <li>running - returns <tt>false</tt></li>
* <li>finished - returns <tt>true</tt></li>
* <li>finished with error - throws the exception that caused the procedure to fail</li>
* </ol>
* <p>
*
* @param signature The signature that uniquely identifies a procedure
* @param instance The instance name of the procedure
* @param props Property/Value pairs of properties passing to the procedure
* @return true if the specified procedure is finished successfully, false if it is still running
* @throws IOException if the specified procedure finished with error
*/
@Override
public boolean isProcedureFinished(String signature, String instance, Map<String, String> props)
throws IOException {
final ProcedureDescription.Builder builder = ProcedureDescription.newBuilder();
builder.setSignature(signature).setInstance(instance);
for (Entry<String, String> entry : props.entrySet()) {
NameStringPair pair = NameStringPair.newBuilder().setName(entry.getKey())
.setValue(entry.getValue()).build();
builder.addConfiguration(pair);
}
final ProcedureDescription desc = builder.build();
return executeCallable(
new MasterCallable<IsProcedureDoneResponse>(getConnection()) {
@Override
public IsProcedureDoneResponse call(int callTimeout) throws ServiceException {
return master.isProcedureDone(null, IsProcedureDoneRequest
.newBuilder().setProcedure(desc).build());
}
}).getDone();
}
/**
* Execute Restore/Clone snapshot and wait for the server to complete (blocking).
* To check if the cloned table exists, use {@link #isTableAvailable} -- it is not safe to
* create an HTable instance to this table before it is available.
* @param snapshotName snapshot to restore
* @param tableName table name to restore the snapshot on
* @throws IOException if a remote or network exception occurs
* @throws RestoreSnapshotException if snapshot failed to be restored
* @throws IllegalArgumentException if the restore request is formatted incorrectly
*/
private void internalRestoreSnapshot(final String snapshotName, final TableName
tableName)
throws IOException, RestoreSnapshotException {
SnapshotDescription snapshot = SnapshotDescription.newBuilder()
.setName(snapshotName).setTable(tableName.getNameAsString()).build();
// actually restore the snapshot
internalRestoreSnapshotAsync(snapshot);
final IsRestoreSnapshotDoneRequest request = IsRestoreSnapshotDoneRequest.newBuilder()
.setSnapshot(snapshot).build();
IsRestoreSnapshotDoneResponse done = IsRestoreSnapshotDoneResponse.newBuilder()
.setDone(false).buildPartial();
final long maxPauseTime = 5000;
int tries = 0;
while (!done.getDone()) {
try {
// sleep a backoff <= pauseTime amount
long sleep = getPauseTime(tries++);
sleep = sleep > maxPauseTime ? maxPauseTime : sleep;
LOG.debug(tries + ") Sleeping: " + sleep + " ms while we wait for snapshot restore to complete.");
Thread.sleep(sleep);
} catch (InterruptedException e) {
throw (InterruptedIOException)new InterruptedIOException("Interrupted").initCause(e);
}
LOG.debug("Getting current status of snapshot restore from master...");
done = executeCallable(new MasterCallable<IsRestoreSnapshotDoneResponse>(
getConnection()) {
@Override
public IsRestoreSnapshotDoneResponse call(int callTimeout) throws ServiceException {
return master.isRestoreSnapshotDone(null, request);
}
});
}
if (!done.getDone()) {
throw new RestoreSnapshotException("Snapshot '" + snapshot.getName() + "' wasn't restored.");
}
}
/**
* Execute Restore/Clone snapshot and wait for the server to complete (asynchronous)
* <p>
* Only a single snapshot should be restored at a time, or results may be undefined.
* @param snapshot snapshot to restore
* @return response from the server indicating the max time to wait for the snapshot
* @throws IOException if a remote or network exception occurs
* @throws RestoreSnapshotException if snapshot failed to be restored
* @throws IllegalArgumentException if the restore request is formatted incorrectly
*/
private RestoreSnapshotResponse internalRestoreSnapshotAsync(final SnapshotDescription snapshot)
throws IOException, RestoreSnapshotException {
ClientSnapshotDescriptionUtils.assertSnapshotRequestIsValid(snapshot);
final RestoreSnapshotRequest request = RestoreSnapshotRequest.newBuilder().setSnapshot(snapshot)
.build();
// run the snapshot restore on the master
return executeCallable(new MasterCallable<RestoreSnapshotResponse>(getConnection()) {
@Override
public RestoreSnapshotResponse call(int callTimeout) throws ServiceException {
return master.restoreSnapshot(null, request);
}
});
}
/**
* List completed snapshots.
* @return a list of snapshot descriptors for completed snapshots
* @throws IOException if a network error occurs
*/
@Override
public List<SnapshotDescription> listSnapshots() throws IOException {
return executeCallable(new MasterCallable<List<SnapshotDescription>>(getConnection()) {
@Override
public List<SnapshotDescription> call(int callTimeout) throws ServiceException {
return master.getCompletedSnapshots(null, GetCompletedSnapshotsRequest.newBuilder().build())
.getSnapshotsList();
}
});
}
/**
* List all the completed snapshots matching the given regular expression.
*
* @param regex The regular expression to match against
* @return - returns a List of SnapshotDescription
* @throws IOException if a remote or network exception occurs
*/
@Override
public List<SnapshotDescription> listSnapshots(String regex) throws IOException {
return listSnapshots(Pattern.compile(regex));
}
/**
* List all the completed snapshots matching the given pattern.
*
* @param pattern The compiled regular expression to match against
* @return - returns a List of SnapshotDescription
* @throws IOException if a remote or network exception occurs
*/
@Override
public List<SnapshotDescription> listSnapshots(Pattern pattern) throws IOException {
List<SnapshotDescription> matched = new LinkedList<SnapshotDescription>();
List<SnapshotDescription> snapshots = listSnapshots();
for (SnapshotDescription snapshot : snapshots) {
if (pattern.matcher(snapshot.getName()).matches()) {
matched.add(snapshot);
}
}
return matched;
}
/**
* Delete an existing snapshot.
* @param snapshotName name of the snapshot
* @throws IOException if a remote or network exception occurs
*/
@Override
public void deleteSnapshot(final byte[] snapshotName) throws IOException {
deleteSnapshot(Bytes.toString(snapshotName));
}
/**
* Delete an existing snapshot.
* @param snapshotName name of the snapshot
* @throws IOException if a remote or network exception occurs
*/
@Override
public void deleteSnapshot(final String snapshotName) throws IOException {
// make sure the snapshot is possibly valid
TableName.isLegalFullyQualifiedTableName(Bytes.toBytes(snapshotName));
// do the delete
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
master.deleteSnapshot(null,
DeleteSnapshotRequest.newBuilder().
setSnapshot(SnapshotDescription.newBuilder().setName(snapshotName).build()).build()
);
return null;
}
});
}
/**
* Delete existing snapshots whose names match the pattern passed.
* @param regex The regular expression to match against
* @throws IOException if a remote or network exception occurs
*/
@Override
public void deleteSnapshots(final String regex) throws IOException {
deleteSnapshots(Pattern.compile(regex));
}
/**
* Delete existing snapshots whose names match the pattern passed.
* @param pattern pattern for names of the snapshot to match
* @throws IOException if a remote or network exception occurs
*/
@Override
public void deleteSnapshots(final Pattern pattern) throws IOException {
List<SnapshotDescription> snapshots = listSnapshots(pattern);
for (final SnapshotDescription snapshot : snapshots) {
try {
internalDeleteSnapshot(snapshot);
} catch (IOException ex) {
LOG.info(
"Failed to delete snapshot " + snapshot.getName() + " for table " + snapshot.getTable(),
ex);
}
}
}
private void internalDeleteSnapshot(final SnapshotDescription snapshot) throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
this.master.deleteSnapshot(null, DeleteSnapshotRequest.newBuilder().setSnapshot(snapshot)
.build());
return null;
}
});
}
/**
* Apply the new quota settings.
*
* @param quota the quota settings
* @throws IOException if a remote or network exception occurs
*/
@Override
public void setQuota(final QuotaSettings quota) throws IOException {
executeCallable(new MasterCallable<Void>(getConnection()) {
@Override
public Void call(int callTimeout) throws ServiceException {
this.master.setQuota(null, QuotaSettings.buildSetQuotaRequestProto(quota));
return null;
}
});
}
/**
* Return a Quota Scanner to list the quotas based on the filter.
*
* @param filter the quota settings filter
* @return the quota scanner
* @throws IOException if a remote or network exception occurs
*/
@Override
public QuotaRetriever getQuotaRetriever(final QuotaFilter filter) throws IOException {
return QuotaRetriever.open(conf, filter);
}
private <V> V executeCallable(MasterCallable<V> callable) throws IOException {
RpcRetryingCaller<V> caller = rpcCallerFactory.newCaller();
try {
return caller.callWithRetries(callable, operationTimeout);
} finally {
callable.close();
}
}
/**
* Creates and returns a {@link com.google.protobuf.RpcChannel} instance
* connected to the active master.
*
* <p>
* The obtained {@link com.google.protobuf.RpcChannel} instance can be used to access a published
* coprocessor {@link com.google.protobuf.Service} using standard protobuf service invocations:
* </p>
*
* <div style="background-color: #cccccc; padding: 2px">
* <blockquote><pre>
* CoprocessorRpcChannel channel = myAdmin.coprocessorService();
* MyService.BlockingInterface service = MyService.newBlockingStub(channel);
* MyCallRequest request = MyCallRequest.newBuilder()
* ...
* .build();
* MyCallResponse response = service.myCall(null, request);
* </pre></blockquote></div>
*
* @return A MasterCoprocessorRpcChannel instance
*/
@Override
public CoprocessorRpcChannel coprocessorService() {
return new MasterCoprocessorRpcChannel(connection);
}
/**
* Simple {@link Abortable}, throwing RuntimeException on abort.
*/
private static class ThrowableAbortable implements Abortable {
@Override
public void abort(String why, Throwable e) {
throw new RuntimeException(why, e);
}
@Override
public boolean isAborted() {
return true;
}
}
/**
* Creates and returns a {@link com.google.protobuf.RpcChannel} instance
* connected to the passed region server.
*
* <p>
* The obtained {@link com.google.protobuf.RpcChannel} instance can be used to access a published
* coprocessor {@link com.google.protobuf.Service} using standard protobuf service invocations:
* </p>
*
* <div style="background-color: #cccccc; padding: 2px">
* <blockquote><pre>
* CoprocessorRpcChannel channel = myAdmin.coprocessorService(serverName);
* MyService.BlockingInterface service = MyService.newBlockingStub(channel);
* MyCallRequest request = MyCallRequest.newBuilder()
* ...
* .build();
* MyCallResponse response = service.myCall(null, request);
* </pre></blockquote></div>
*
* @param sn the server name to which the endpoint call is made
* @return A RegionServerCoprocessorRpcChannel instance
*/
@Override
public CoprocessorRpcChannel coprocessorService(ServerName sn) {
return new RegionServerCoprocessorRpcChannel(connection, sn);
}
@Override
public void updateConfiguration(ServerName server) throws IOException {
try {
this.connection.getAdmin(server).updateConfiguration(null,
UpdateConfigurationRequest.getDefaultInstance());
} catch (ServiceException e) {
throw ProtobufUtil.getRemoteException(e);
}
}
@Override
public void updateConfiguration() throws IOException {
for (ServerName server : this.getClusterStatus().getServers()) {
updateConfiguration(server);
}
}
@Override
public int getMasterInfoPort() throws IOException {
// TODO: Fix! Reaching into internal implementation!!!!
ConnectionManager.HConnectionImplementation connection =
(ConnectionManager.HConnectionImplementation)this.connection;
ZooKeeperKeepAliveConnection zkw = connection.getKeepAliveZooKeeperWatcher();
try {
return MasterAddressTracker.getMasterInfoPort(zkw);
} catch (KeeperException e) {
throw new IOException("Failed to get master info port from MasterAddressTracker", e);
}
}
}
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#include "config.h"
#include "AccessibilityObject.h"
#include "AXObjectCache.h"
#include "AccessibilityRenderObject.h"
#include "AccessibilityTable.h"
#include "FloatRect.h"
#include "FocusController.h"
#include "Frame.h"
#include "FrameLoader.h"
#include "FrameSelection.h"
#include "HTMLNames.h"
#include "LocalizedStrings.h"
#include "NodeList.h"
#include "NotImplemented.h"
#include "Page.h"
#include "RenderImage.h"
#include "RenderListItem.h"
#include "RenderListMarker.h"
#include "RenderMenuList.h"
#include "RenderTextControl.h"
#include "RenderTheme.h"
#include "RenderView.h"
#include "RenderWidget.h"
#include "RenderedPosition.h"
#include "Settings.h"
#include "TextCheckerClient.h"
#include "TextCheckingHelper.h"
#include "TextIterator.h"
#include "htmlediting.h"
#include "visible_units.h"
#include <wtf/StdLibExtras.h>
#include <wtf/text/StringBuilder.h>
#include <wtf/text/WTFString.h>
#include <wtf/unicode/CharacterNames.h>
using namespace std;
namespace WebCore {
using namespace HTMLNames;
AccessibilityObject::AccessibilityObject()
: m_id(0)
, m_haveChildren(false)
, m_role(UnknownRole)
, m_cachedIsIgnoredValue(DefaultBehavior)
#if PLATFORM(GTK) || PLATFORM(EFL)
, m_wrapper(0)
#elif PLATFORM(CHROMIUM)
, m_detached(false)
#endif
{
}
AccessibilityObject::~AccessibilityObject()
{
ASSERT(isDetached());
}
void AccessibilityObject::detach()
{
#if HAVE(ACCESSIBILITY) && PLATFORM(CHROMIUM)
m_detached = true;
#elif HAVE(ACCESSIBILITY)
setWrapper(0);
#endif
}
bool AccessibilityObject::isDetached() const
{
#if HAVE(ACCESSIBILITY) && PLATFORM(CHROMIUM)
return m_detached;
#elif HAVE(ACCESSIBILITY)
return !wrapper();
#else
return true;
#endif
}
bool AccessibilityObject::isAccessibilityObjectSearchMatch(AccessibilityObject* axObject, AccessibilitySearchCriteria* criteria)
{
if (!axObject || !criteria)
return false;
switch (criteria->searchKey) {
// The AnyTypeSearchKey matches any non-null AccessibilityObject.
case AnyTypeSearchKey:
return true;
case BlockquoteSameLevelSearchKey:
return criteria->startObject
&& axObject->isBlockquote()
&& axObject->blockquoteLevel() == criteria->startObject->blockquoteLevel();
case BlockquoteSearchKey:
return axObject->isBlockquote();
case BoldFontSearchKey:
return axObject->hasBoldFont();
case ButtonSearchKey:
return axObject->isButton();
case CheckBoxSearchKey:
return axObject->isCheckbox();
case ControlSearchKey:
return axObject->isControl();
case DifferentTypeSearchKey:
return criteria->startObject
&& axObject->roleValue() != criteria->startObject->roleValue();
case FontChangeSearchKey:
return criteria->startObject
&& !axObject->hasSameFont(criteria->startObject->renderer());
case FontColorChangeSearchKey:
return criteria->startObject
&& !axObject->hasSameFontColor(criteria->startObject->renderer());
case FrameSearchKey:
return axObject->isWebArea();
case GraphicSearchKey:
return axObject->isImage();
case HeadingLevel1SearchKey:
return axObject->headingLevel() == 1;
case HeadingLevel2SearchKey:
return axObject->headingLevel() == 2;
case HeadingLevel3SearchKey:
return axObject->headingLevel() == 3;
case HeadingLevel4SearchKey:
return axObject->headingLevel() == 4;
case HeadingLevel5SearchKey:
return axObject->headingLevel() == 5;
case HeadingLevel6SearchKey:
return axObject->headingLevel() == 6;
case HeadingSameLevelSearchKey:
return criteria->startObject
&& axObject->isHeading()
&& axObject->headingLevel() == criteria->startObject->headingLevel();
case HeadingSearchKey:
return axObject->isHeading();
case HighlightedSearchKey:
return axObject->hasHighlighting();
case ItalicFontSearchKey:
return axObject->hasItalicFont();
case LandmarkSearchKey:
return axObject->isLandmark();
case LinkSearchKey:
return axObject->isLink();
case ListSearchKey:
return axObject->isList();
case LiveRegionSearchKey:
return axObject->supportsARIALiveRegion();
case MisspelledWordSearchKey:
return axObject->hasMisspelling();
case PlainTextSearchKey:
return axObject->hasPlainText();
case RadioGroupSearchKey:
return axObject->isRadioGroup();
case SameTypeSearchKey:
return criteria->startObject
&& axObject->roleValue() == criteria->startObject->roleValue();
case StaticTextSearchKey:
return axObject->hasStaticText();
case StyleChangeSearchKey:
return criteria->startObject
&& !axObject->hasSameStyle(criteria->startObject->renderer());
case TableSameLevelSearchKey:
return criteria->startObject
&& axObject->isAccessibilityTable()
&& axObject->tableLevel() == criteria->startObject->tableLevel();
case TableSearchKey:
return axObject->isAccessibilityTable();
case TextFieldSearchKey:
return axObject->isTextControl();
case UnderlineSearchKey:
return axObject->hasUnderline();
case UnvisitedLinkSearchKey:
return axObject->isUnvisited();
case VisitedLinkSearchKey:
return axObject->isVisited();
default:
return false;
}
}
bool AccessibilityObject::isAccessibilityTextSearchMatch(AccessibilityObject* axObject, AccessibilitySearchCriteria* criteria)
{
if (!axObject || !criteria)
return false;
return axObject->accessibilityObjectContainsText(criteria->searchText);
}
bool AccessibilityObject::accessibilityObjectContainsText(String* text) const
{
// If text is null or empty we return true.
return !text
|| text->isEmpty()
|| title().contains(*text, false)
|| accessibilityDescription().contains(*text, false)
|| stringValue().contains(*text, false);
}
bool AccessibilityObject::isBlockquote() const
{
return node() && node()->hasTagName(blockquoteTag);
}
bool AccessibilityObject::isARIATextControl() const
{
return ariaRoleAttribute() == TextAreaRole || ariaRoleAttribute() == TextFieldRole;
}
bool AccessibilityObject::isLandmark() const
{
AccessibilityRole role = roleValue();
return role == LandmarkApplicationRole
|| role == LandmarkBannerRole
|| role == LandmarkComplementaryRole
|| role == LandmarkContentInfoRole
|| role == LandmarkMainRole
|| role == LandmarkNavigationRole
|| role == LandmarkSearchRole;
}
bool AccessibilityObject::hasMisspelling() const
{
if (!node())
return false;
Document* document = node()->document();
if (!document)
return false;
Frame* frame = document->frame();
if (!frame)
return false;
Editor* editor = frame->editor();
if (!editor)
return false;
TextCheckerClient* textChecker = editor->textChecker();
if (!textChecker)
return false;
const UChar* chars = stringValue().characters();
int charsLength = stringValue().length();
bool isMisspelled = false;
if (unifiedTextCheckerEnabled(frame)) {
Vector<TextCheckingResult> results;
checkTextOfParagraph(textChecker, chars, charsLength, TextCheckingTypeSpelling, results);
if (!results.isEmpty())
isMisspelled = true;
return isMisspelled;
}
int misspellingLength = 0;
int misspellingLocation = -1;
textChecker->checkSpellingOfString(chars, charsLength, &misspellingLocation, &misspellingLength);
if (misspellingLength || misspellingLocation != -1)
isMisspelled = true;
return isMisspelled;
}
int AccessibilityObject::blockquoteLevel() const
{
int level = 0;
for (Node* elementNode = node(); elementNode; elementNode = elementNode->parentNode()) {
if (elementNode->hasTagName(blockquoteTag))
++level;
}
return level;
}
AccessibilityObject* AccessibilityObject::parentObjectUnignored() const
{
AccessibilityObject* parent;
for (parent = parentObject(); parent && parent->accessibilityIsIgnored(); parent = parent->parentObject()) {
}
return parent;
}
AccessibilityObject* AccessibilityObject::firstAccessibleObjectFromNode(const Node* node)
{
if (!node)
return 0;
Document* document = node->document();
if (!document)
return 0;
AXObjectCache* cache = document->axObjectCache();
AccessibilityObject* accessibleObject = cache->getOrCreate(node->renderer());
while (accessibleObject && accessibleObject->accessibilityIsIgnored()) {
node = node->traverseNextNode();
while (node && !node->renderer())
node = node->traverseNextSibling();
if (!node)
return 0;
accessibleObject = cache->getOrCreate(node->renderer());
}
return accessibleObject;
}
static void appendAccessibilityObject(AccessibilityObject* object, AccessibilityObject::AccessibilityChildrenVector& results)
{
// Find the next descendant of this attachment object so search can continue through frames.
if (object->isAttachment()) {
Widget* widget = object->widgetForAttachmentView();
if (!widget || !widget->isFrameView())
return;
Document* doc = static_cast<FrameView*>(widget)->frame()->document();
if (!doc || !doc->renderer())
return;
object = object->axObjectCache()->getOrCreate(doc);
}
if (object)
results.append(object);
}
static void appendChildrenToArray(AccessibilityObject* object, bool isForward, AccessibilityObject* startObject, AccessibilityObject::AccessibilityChildrenVector& results)
{
AccessibilityObject::AccessibilityChildrenVector searchChildren;
// A table's children includes elements whose own children are also the table's children (due to the way the Mac exposes tables).
// The rows from the table should be queried, since those are direct descendants of the table, and they contain content.
if (object->isAccessibilityTable())
searchChildren = toAccessibilityTable(object)->rows();
else
searchChildren = object->children();
size_t childrenSize = searchChildren.size();
size_t startIndex = isForward ? childrenSize : 0;
size_t endIndex = isForward ? 0 : childrenSize;
size_t searchPosition = startObject ? searchChildren.find(startObject) : WTF::notFound;
if (searchPosition != WTF::notFound) {
if (isForward)
endIndex = searchPosition + 1;
else
endIndex = searchPosition;
}
// This is broken into two statements so that it's easier read.
if (isForward) {
for (size_t i = startIndex; i > endIndex; i--)
appendAccessibilityObject(searchChildren.at(i - 1).get(), results);
} else {
for (size_t i = startIndex; i < endIndex; i++)
appendAccessibilityObject(searchChildren.at(i).get(), results);
}
}
// Returns true if the number of results is now >= the number of results desired.
bool AccessibilityObject::objectMatchesSearchCriteriaWithResultLimit(AccessibilityObject* object, AccessibilitySearchCriteria* criteria, AccessibilityChildrenVector& results)
{
if (isAccessibilityObjectSearchMatch(object, criteria) && isAccessibilityTextSearchMatch(object, criteria)) {
results.append(object);
// Enough results were found to stop searching.
if (results.size() >= criteria->resultsLimit)
return true;
}
return false;
}
void AccessibilityObject::findMatchingObjects(AccessibilitySearchCriteria* criteria, AccessibilityChildrenVector& results)
{
ASSERT(criteria);
if (!criteria)
return;
// This search mechanism only searches the elements before/after the starting object.
// It does this by stepping up the parent chain and at each level doing a DFS.
// If there's no start object, it means we want to search everything.
AccessibilityObject* startObject = criteria->startObject;
if (!startObject)
startObject = this;
bool isForward = criteria->searchDirection == SearchDirectionNext;
// In the first iteration of the loop, it will examine the children of the start object for matches.
// However, when going backwards, those children should not be considered, so the loop is skipped ahead.
AccessibilityObject* previousObject = 0;
if (!isForward) {
previousObject = startObject;
startObject = startObject->parentObjectUnignored();
}
// The outer loop steps up the parent chain each time (unignored is important here because otherwise elements would be searched twice)
for (AccessibilityObject* stopSearchElement = parentObjectUnignored(); startObject != stopSearchElement; startObject = startObject->parentObjectUnignored()) {
// Only append the children after/before the previous element, so that the search does not check elements that are
// already behind/ahead of start element.
AccessibilityChildrenVector searchStack;
appendChildrenToArray(startObject, isForward, previousObject, searchStack);
// This now does a DFS at the current level of the parent.
while (!searchStack.isEmpty()) {
AccessibilityObject* searchObject = searchStack.last().get();
searchStack.removeLast();
if (objectMatchesSearchCriteriaWithResultLimit(searchObject, criteria, results))
break;
appendChildrenToArray(searchObject, isForward, 0, searchStack);
}
if (results.size() >= criteria->resultsLimit)
break;
// When moving backwards, the parent object needs to be checked, because technically it's "before" the starting element.
if (!isForward && objectMatchesSearchCriteriaWithResultLimit(startObject, criteria, results))
break;
previousObject = startObject;
}
}
bool AccessibilityObject::isARIAInput(AccessibilityRole ariaRole)
{
return ariaRole == RadioButtonRole || ariaRole == CheckBoxRole || ariaRole == TextFieldRole;
}
bool AccessibilityObject::isARIAControl(AccessibilityRole ariaRole)
{
return isARIAInput(ariaRole) || ariaRole == TextAreaRole || ariaRole == ButtonRole
|| ariaRole == ComboBoxRole || ariaRole == SliderRole;
}
IntPoint AccessibilityObject::clickPoint()
{
LayoutRect rect = elementRect();
return roundedIntPoint(LayoutPoint(rect.x() + rect.width() / 2, rect.y() + rect.height() / 2));
}
IntRect AccessibilityObject::boundingBoxForQuads(RenderObject* obj, const Vector<FloatQuad>& quads)
{
ASSERT(obj);
if (!obj)
return IntRect();
size_t count = quads.size();
if (!count)
return IntRect();
IntRect result;
for (size_t i = 0; i < count; ++i) {
IntRect r = quads[i].enclosingBoundingBox();
if (!r.isEmpty()) {
if (obj->style()->hasAppearance())
obj->theme()->adjustRepaintRect(obj, r);
result.unite(r);
}
}
return result;
}
bool AccessibilityObject::press() const
{
Element* actionElem = actionElement();
if (!actionElem)
return false;
if (Frame* f = actionElem->document()->frame())
f->loader()->resetMultipleFormSubmissionProtection();
actionElem->accessKeyAction(true);
return true;
}
String AccessibilityObject::language() const
{
const AtomicString& lang = getAttribute(langAttr);
if (!lang.isEmpty())
return lang;
AccessibilityObject* parent = parentObject();
// as a last resort, fall back to the content language specified in the meta tag
if (!parent) {
Document* doc = document();
if (doc)
return doc->contentLanguage();
return nullAtom;
}
return parent->language();
}
VisiblePositionRange AccessibilityObject::visiblePositionRangeForUnorderedPositions(const VisiblePosition& visiblePos1, const VisiblePosition& visiblePos2) const
{
if (visiblePos1.isNull() || visiblePos2.isNull())
return VisiblePositionRange();
VisiblePosition startPos;
VisiblePosition endPos;
bool alreadyInOrder;
// upstream is ordered before downstream for the same position
if (visiblePos1 == visiblePos2 && visiblePos2.affinity() == UPSTREAM)
alreadyInOrder = false;
// use selection order to see if the positions are in order
else
alreadyInOrder = VisibleSelection(visiblePos1, visiblePos2).isBaseFirst();
if (alreadyInOrder) {
startPos = visiblePos1;
endPos = visiblePos2;
} else {
startPos = visiblePos2;
endPos = visiblePos1;
}
return VisiblePositionRange(startPos, endPos);
}
VisiblePositionRange AccessibilityObject::positionOfLeftWord(const VisiblePosition& visiblePos) const
{
VisiblePosition startPosition = startOfWord(visiblePos, LeftWordIfOnBoundary);
VisiblePosition endPosition = endOfWord(startPosition);
return VisiblePositionRange(startPosition, endPosition);
}
VisiblePositionRange AccessibilityObject::positionOfRightWord(const VisiblePosition& visiblePos) const
{
VisiblePosition startPosition = startOfWord(visiblePos, RightWordIfOnBoundary);
VisiblePosition endPosition = endOfWord(startPosition);
return VisiblePositionRange(startPosition, endPosition);
}
static VisiblePosition updateAXLineStartForVisiblePosition(const VisiblePosition& visiblePosition)
{
// A line in the accessibility sense should include floating objects, such as aligned image, as part of a line.
// So let's update the position to include that.
VisiblePosition tempPosition;
VisiblePosition startPosition = visiblePosition;
while (true) {
tempPosition = startPosition.previous();
if (tempPosition.isNull())
break;
Position p = tempPosition.deepEquivalent();
RenderObject* renderer = p.deprecatedNode()->renderer();
if (!renderer || (renderer->isRenderBlock() && !p.deprecatedEditingOffset()))
break;
if (!RenderedPosition(tempPosition).isNull())
break;
startPosition = tempPosition;
}
return startPosition;
}
VisiblePositionRange AccessibilityObject::leftLineVisiblePositionRange(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePositionRange();
// make a caret selection for the position before marker position (to make sure
// we move off of a line start)
VisiblePosition prevVisiblePos = visiblePos.previous();
if (prevVisiblePos.isNull())
return VisiblePositionRange();
VisiblePosition startPosition = startOfLine(prevVisiblePos);
// keep searching for a valid line start position. Unless the VisiblePosition is at the very beginning, there should
// always be a valid line range. However, startOfLine will return null for position next to a floating object,
// since floating object doesn't really belong to any line.
// This check will reposition the marker before the floating object, to ensure we get a line start.
if (startPosition.isNull()) {
while (startPosition.isNull() && prevVisiblePos.isNotNull()) {
prevVisiblePos = prevVisiblePos.previous();
startPosition = startOfLine(prevVisiblePos);
}
} else
startPosition = updateAXLineStartForVisiblePosition(startPosition);
VisiblePosition endPosition = endOfLine(prevVisiblePos);
return VisiblePositionRange(startPosition, endPosition);
}
VisiblePositionRange AccessibilityObject::rightLineVisiblePositionRange(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePositionRange();
// make sure we move off of a line end
VisiblePosition nextVisiblePos = visiblePos.next();
if (nextVisiblePos.isNull())
return VisiblePositionRange();
VisiblePosition startPosition = startOfLine(nextVisiblePos);
// fetch for a valid line start position
if (startPosition.isNull()) {
startPosition = visiblePos;
nextVisiblePos = nextVisiblePos.next();
} else
startPosition = updateAXLineStartForVisiblePosition(startPosition);
VisiblePosition endPosition = endOfLine(nextVisiblePos);
// as long as the position hasn't reached the end of the doc, keep searching for a valid line end position
// Unless the VisiblePosition is at the very end, there should always be a valid line range. However, endOfLine will
// return null for position by a floating object, since floating object doesn't really belong to any line.
// This check will reposition the marker after the floating object, to ensure we get a line end.
while (endPosition.isNull() && nextVisiblePos.isNotNull()) {
nextVisiblePos = nextVisiblePos.next();
endPosition = endOfLine(nextVisiblePos);
}
return VisiblePositionRange(startPosition, endPosition);
}
VisiblePositionRange AccessibilityObject::sentenceForPosition(const VisiblePosition& visiblePos) const
{
// FIXME: FO 2 IMPLEMENT (currently returns incorrect answer)
// Related? <rdar://problem/3927736> Text selection broken in 8A336
VisiblePosition startPosition = startOfSentence(visiblePos);
VisiblePosition endPosition = endOfSentence(startPosition);
return VisiblePositionRange(startPosition, endPosition);
}
VisiblePositionRange AccessibilityObject::paragraphForPosition(const VisiblePosition& visiblePos) const
{
VisiblePosition startPosition = startOfParagraph(visiblePos);
VisiblePosition endPosition = endOfParagraph(startPosition);
return VisiblePositionRange(startPosition, endPosition);
}
static VisiblePosition startOfStyleRange(const VisiblePosition visiblePos)
{
RenderObject* renderer = visiblePos.deepEquivalent().deprecatedNode()->renderer();
RenderObject* startRenderer = renderer;
RenderStyle* style = renderer->style();
// traverse backward by renderer to look for style change
for (RenderObject* r = renderer->previousInPreOrder(); r; r = r->previousInPreOrder()) {
// skip non-leaf nodes
if (r->firstChild())
continue;
// stop at style change
if (r->style() != style)
break;
// remember match
startRenderer = r;
}
return firstPositionInOrBeforeNode(startRenderer->node());
}
static VisiblePosition endOfStyleRange(const VisiblePosition& visiblePos)
{
RenderObject* renderer = visiblePos.deepEquivalent().deprecatedNode()->renderer();
RenderObject* endRenderer = renderer;
RenderStyle* style = renderer->style();
// traverse forward by renderer to look for style change
for (RenderObject* r = renderer->nextInPreOrder(); r; r = r->nextInPreOrder()) {
// skip non-leaf nodes
if (r->firstChild())
continue;
// stop at style change
if (r->style() != style)
break;
// remember match
endRenderer = r;
}
return lastPositionInOrAfterNode(endRenderer->node());
}
VisiblePositionRange AccessibilityObject::styleRangeForPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePositionRange();
return VisiblePositionRange(startOfStyleRange(visiblePos), endOfStyleRange(visiblePos));
}
// NOTE: Consider providing this utility method as AX API
VisiblePositionRange AccessibilityObject::visiblePositionRangeForRange(const PlainTextRange& range) const
{
unsigned textLength = getLengthForTextRange();
if (range.start + range.length > textLength)
return VisiblePositionRange();
VisiblePosition startPosition = visiblePositionForIndex(range.start);
startPosition.setAffinity(DOWNSTREAM);
VisiblePosition endPosition = visiblePositionForIndex(range.start + range.length);
return VisiblePositionRange(startPosition, endPosition);
}
static bool replacedNodeNeedsCharacter(Node* replacedNode)
{
// we should always be given a rendered node and a replaced node, but be safe
// replaced nodes are either attachments (widgets) or images
if (!replacedNode || !replacedNode->renderer() || !replacedNode->renderer()->isReplaced() || replacedNode->isTextNode())
return false;
// create an AX object, but skip it if it is not supposed to be seen
AccessibilityObject* object = replacedNode->renderer()->document()->axObjectCache()->getOrCreate(replacedNode);
if (object->accessibilityIsIgnored())
return false;
return true;
}
// Finds a RenderListItem parent give a node.
static RenderListItem* renderListItemContainerForNode(Node* node)
{
for (; node; node = node->parentNode()) {
RenderBoxModelObject* renderer = node->renderBoxModelObject();
if (renderer && renderer->isListItem())
return toRenderListItem(renderer);
}
return 0;
}
// Returns the text associated with a list marker if this node is contained within a list item.
String AccessibilityObject::listMarkerTextForNodeAndPosition(Node* node, const VisiblePosition& visiblePositionStart) const
{
// If the range does not contain the start of the line, the list marker text should not be included.
if (!isStartOfLine(visiblePositionStart))
return String();
RenderListItem* listItem = renderListItemContainerForNode(node);
if (!listItem)
return String();
// If this is in a list item, we need to manually add the text for the list marker
// because a RenderListMarker does not have a Node equivalent and thus does not appear
// when iterating text.
const String& markerText = listItem->markerText();
if (markerText.isEmpty())
return String();
// Append text, plus the period that follows the text.
// FIXME: Not all list marker styles are followed by a period, but this
// sounds much better when there is a synthesized pause because of a period.
return markerText + ". ";
}
String AccessibilityObject::stringForVisiblePositionRange(const VisiblePositionRange& visiblePositionRange) const
{
if (visiblePositionRange.isNull())
return String();
StringBuilder builder;
RefPtr<Range> range = makeRange(visiblePositionRange.start, visiblePositionRange.end);
for (TextIterator it(range.get()); !it.atEnd(); it.advance()) {
// non-zero length means textual node, zero length means replaced node (AKA "attachments" in AX)
if (it.length()) {
// Add a textual representation for list marker text
String listMarkerText = listMarkerTextForNodeAndPosition(it.node(), visiblePositionRange.start);
if (!listMarkerText.isEmpty())
builder.append(listMarkerText);
builder.append(it.characters(), it.length());
} else {
// locate the node and starting offset for this replaced range
int exception = 0;
Node* node = it.range()->startContainer(exception);
ASSERT(node == it.range()->endContainer(exception));
int offset = it.range()->startOffset(exception);
if (replacedNodeNeedsCharacter(node->childNode(offset)))
builder.append(objectReplacementCharacter);
}
}
return builder.toString();
}
int AccessibilityObject::lengthForVisiblePositionRange(const VisiblePositionRange& visiblePositionRange) const
{
// FIXME: Multi-byte support
if (visiblePositionRange.isNull())
return -1;
int length = 0;
RefPtr<Range> range = makeRange(visiblePositionRange.start, visiblePositionRange.end);
for (TextIterator it(range.get()); !it.atEnd(); it.advance()) {
// non-zero length means textual node, zero length means replaced node (AKA "attachments" in AX)
if (it.length())
length += it.length();
else {
// locate the node and starting offset for this replaced range
int exception = 0;
Node* node = it.range()->startContainer(exception);
ASSERT(node == it.range()->endContainer(exception));
int offset = it.range()->startOffset(exception);
if (replacedNodeNeedsCharacter(node->childNode(offset)))
length++;
}
}
return length;
}
VisiblePosition AccessibilityObject::nextWordEnd(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a word end
VisiblePosition nextVisiblePos = visiblePos.next();
if (nextVisiblePos.isNull())
return VisiblePosition();
return endOfWord(nextVisiblePos, LeftWordIfOnBoundary);
}
VisiblePosition AccessibilityObject::previousWordStart(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a word start
VisiblePosition prevVisiblePos = visiblePos.previous();
if (prevVisiblePos.isNull())
return VisiblePosition();
return startOfWord(prevVisiblePos, RightWordIfOnBoundary);
}
VisiblePosition AccessibilityObject::nextLineEndPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePosition();
// to make sure we move off of a line end
VisiblePosition nextVisiblePos = visiblePos.next();
if (nextVisiblePos.isNull())
return VisiblePosition();
VisiblePosition endPosition = endOfLine(nextVisiblePos);
// as long as the position hasn't reached the end of the doc, keep searching for a valid line end position
// There are cases like when the position is next to a floating object that'll return null for end of line. This code will avoid returning null.
while (endPosition.isNull() && nextVisiblePos.isNotNull()) {
nextVisiblePos = nextVisiblePos.next();
endPosition = endOfLine(nextVisiblePos);
}
return endPosition;
}
VisiblePosition AccessibilityObject::previousLineStartPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a line start
VisiblePosition prevVisiblePos = visiblePos.previous();
if (prevVisiblePos.isNull())
return VisiblePosition();
VisiblePosition startPosition = startOfLine(prevVisiblePos);
// as long as the position hasn't reached the beginning of the doc, keep searching for a valid line start position
// There are cases like when the position is next to a floating object that'll return null for start of line. This code will avoid returning null.
if (startPosition.isNull()) {
while (startPosition.isNull() && prevVisiblePos.isNotNull()) {
prevVisiblePos = prevVisiblePos.previous();
startPosition = startOfLine(prevVisiblePos);
}
} else
startPosition = updateAXLineStartForVisiblePosition(startPosition);
return startPosition;
}
VisiblePosition AccessibilityObject::nextSentenceEndPosition(const VisiblePosition& visiblePos) const
{
// FIXME: FO 2 IMPLEMENT (currently returns incorrect answer)
// Related? <rdar://problem/3927736> Text selection broken in 8A336
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a sentence end
VisiblePosition nextVisiblePos = visiblePos.next();
if (nextVisiblePos.isNull())
return VisiblePosition();
// an empty line is considered a sentence. If it's skipped, then the sentence parser will not
// see this empty line. Instead, return the end position of the empty line.
VisiblePosition endPosition;
String lineString = plainText(makeRange(startOfLine(nextVisiblePos), endOfLine(nextVisiblePos)).get());
if (lineString.isEmpty())
endPosition = nextVisiblePos;
else
endPosition = endOfSentence(nextVisiblePos);
return endPosition;
}
VisiblePosition AccessibilityObject::previousSentenceStartPosition(const VisiblePosition& visiblePos) const
{
// FIXME: FO 2 IMPLEMENT (currently returns incorrect answer)
// Related? <rdar://problem/3927736> Text selection broken in 8A336
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a sentence start
VisiblePosition previousVisiblePos = visiblePos.previous();
if (previousVisiblePos.isNull())
return VisiblePosition();
// treat empty line as a separate sentence.
VisiblePosition startPosition;
String lineString = plainText(makeRange(startOfLine(previousVisiblePos), endOfLine(previousVisiblePos)).get());
if (lineString.isEmpty())
startPosition = previousVisiblePos;
else
startPosition = startOfSentence(previousVisiblePos);
return startPosition;
}
VisiblePosition AccessibilityObject::nextParagraphEndPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a paragraph end
VisiblePosition nextPos = visiblePos.next();
if (nextPos.isNull())
return VisiblePosition();
return endOfParagraph(nextPos);
}
VisiblePosition AccessibilityObject::previousParagraphStartPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return VisiblePosition();
// make sure we move off of a paragraph start
VisiblePosition previousPos = visiblePos.previous();
if (previousPos.isNull())
return VisiblePosition();
return startOfParagraph(previousPos);
}
AccessibilityObject* AccessibilityObject::accessibilityObjectForPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull())
return 0;
RenderObject* obj = visiblePos.deepEquivalent().deprecatedNode()->renderer();
if (!obj)
return 0;
return obj->document()->axObjectCache()->getOrCreate(obj);
}
#if HAVE(ACCESSIBILITY)
int AccessibilityObject::lineForPosition(const VisiblePosition& visiblePos) const
{
if (visiblePos.isNull() || !node())
return -1;
// If the position is not in the same editable region as this AX object, return -1.
Node* containerNode = visiblePos.deepEquivalent().containerNode();
if (!containerNode->containsIncludingShadowDOM(node()) && !node()->containsIncludingShadowDOM(containerNode))
return -1;
int lineCount = -1;
VisiblePosition currentVisiblePos = visiblePos;
VisiblePosition savedVisiblePos;
// move up until we get to the top
// FIXME: This only takes us to the top of the rootEditableElement, not the top of the
// top document.
do {
savedVisiblePos = currentVisiblePos;
VisiblePosition prevVisiblePos = previousLinePosition(currentVisiblePos, 0, HasEditableAXRole);
currentVisiblePos = prevVisiblePos;
++lineCount;
} while (currentVisiblePos.isNotNull() && !(inSameLine(currentVisiblePos, savedVisiblePos)));
return lineCount;
}
#endif
// NOTE: Consider providing this utility method as AX API
PlainTextRange AccessibilityObject::plainTextRangeForVisiblePositionRange(const VisiblePositionRange& positionRange) const
{
int index1 = index(positionRange.start);
int index2 = index(positionRange.end);
if (index1 < 0 || index2 < 0 || index1 > index2)
return PlainTextRange();
return PlainTextRange(index1, index2 - index1);
}
// The composed character range in the text associated with this accessibility object that
// is specified by the given screen coordinates. This parameterized attribute returns the
// complete range of characters (including surrogate pairs of multi-byte glyphs) at the given
// screen coordinates.
// NOTE: This varies from AppKit when the point is below the last line. AppKit returns an
// an error in that case. We return textControl->text().length(), 1. Does this matter?
PlainTextRange AccessibilityObject::doAXRangeForPosition(const IntPoint& point) const
{
int i = index(visiblePositionForPoint(point));
if (i < 0)
return PlainTextRange();
return PlainTextRange(i, 1);
}
// Given a character index, the range of text associated with this accessibility object
// over which the style in effect at that character index applies.
PlainTextRange AccessibilityObject::doAXStyleRangeForIndex(unsigned index) const
{
VisiblePositionRange range = styleRangeForPosition(visiblePositionForIndex(index, false));
return plainTextRangeForVisiblePositionRange(range);
}
// Given an indexed character, the line number of the text associated with this accessibility
// object that contains the character.
unsigned AccessibilityObject::doAXLineForIndex(unsigned index)
{
return lineForPosition(visiblePositionForIndex(index, false));
}
#if HAVE(ACCESSIBILITY)
void AccessibilityObject::updateBackingStore()
{
// Updating the layout may delete this object.
if (Document* document = this->document())
document->updateLayoutIgnorePendingStylesheets();
}
#endif
Document* AccessibilityObject::document() const
{
FrameView* frameView = documentFrameView();
if (!frameView)
return 0;
return frameView->frame()->document();
}
Page* AccessibilityObject::page() const
{
Document* document = this->document();
if (!document)
return 0;
return document->page();
}
FrameView* AccessibilityObject::documentFrameView() const
{
const AccessibilityObject* object = this;
while (object && !object->isAccessibilityRenderObject())
object = object->parentObject();
if (!object)
return 0;
return object->documentFrameView();
}
#if HAVE(ACCESSIBILITY)
const AccessibilityObject::AccessibilityChildrenVector& AccessibilityObject::children()
{
updateChildrenIfNecessary();
return m_children;
}
#endif
void AccessibilityObject::updateChildrenIfNecessary()
{
if (!hasChildren())
addChildren();
}
void AccessibilityObject::clearChildren()
{
// Some objects have weak pointers to their parents and those associations need to be detached.
size_t length = m_children.size();
for (size_t i = 0; i < length; i++)
m_children[i]->detachFromParent();
m_children.clear();
m_haveChildren = false;
}
AccessibilityObject* AccessibilityObject::anchorElementForNode(Node* node)
{
RenderObject* obj = node->renderer();
if (!obj)
return 0;
RefPtr<AccessibilityObject> axObj = obj->document()->axObjectCache()->getOrCreate(obj);
Element* anchor = axObj->anchorElement();
if (!anchor)
return 0;
RenderObject* anchorRenderer = anchor->renderer();
if (!anchorRenderer)
return 0;
return anchorRenderer->document()->axObjectCache()->getOrCreate(anchorRenderer);
}
void AccessibilityObject::ariaTreeRows(AccessibilityChildrenVector& result)
{
AccessibilityChildrenVector axChildren = children();
unsigned count = axChildren.size();
for (unsigned k = 0; k < count; ++k) {
AccessibilityObject* obj = axChildren[k].get();
// Add tree items as the rows.
if (obj->roleValue() == TreeItemRole)
result.append(obj);
// Now see if this item also has rows hiding inside of it.
obj->ariaTreeRows(result);
}
}
void AccessibilityObject::ariaTreeItemContent(AccessibilityChildrenVector& result)
{
// The ARIA tree item content are the item that are not other tree items or their containing groups.
AccessibilityChildrenVector axChildren = children();
unsigned count = axChildren.size();
for (unsigned k = 0; k < count; ++k) {
AccessibilityObject* obj = axChildren[k].get();
AccessibilityRole role = obj->roleValue();
if (role == TreeItemRole || role == GroupRole)
continue;
result.append(obj);
}
}
void AccessibilityObject::ariaTreeItemDisclosedRows(AccessibilityChildrenVector& result)
{
AccessibilityChildrenVector axChildren = children();
unsigned count = axChildren.size();
for (unsigned k = 0; k < count; ++k) {
AccessibilityObject* obj = axChildren[k].get();
// Add tree items as the rows.
if (obj->roleValue() == TreeItemRole)
result.append(obj);
// If it's not a tree item, then descend into the group to find more tree items.
else
obj->ariaTreeRows(result);
}
}
#if HAVE(ACCESSIBILITY)
const String& AccessibilityObject::actionVerb() const
{
// FIXME: Need to add verbs for select elements.
DEFINE_STATIC_LOCAL(const String, buttonAction, (AXButtonActionVerb()));
DEFINE_STATIC_LOCAL(const String, textFieldAction, (AXTextFieldActionVerb()));
DEFINE_STATIC_LOCAL(const String, radioButtonAction, (AXRadioButtonActionVerb()));
DEFINE_STATIC_LOCAL(const String, checkedCheckBoxAction, (AXCheckedCheckBoxActionVerb()));
DEFINE_STATIC_LOCAL(const String, uncheckedCheckBoxAction, (AXUncheckedCheckBoxActionVerb()));
DEFINE_STATIC_LOCAL(const String, linkAction, (AXLinkActionVerb()));
DEFINE_STATIC_LOCAL(const String, menuListAction, (AXMenuListActionVerb()));
DEFINE_STATIC_LOCAL(const String, menuListPopupAction, (AXMenuListPopupActionVerb()));
DEFINE_STATIC_LOCAL(const String, noAction, ());
switch (roleValue()) {
case ButtonRole:
case ToggleButtonRole:
return buttonAction;
case TextFieldRole:
case TextAreaRole:
return textFieldAction;
case RadioButtonRole:
return radioButtonAction;
case CheckBoxRole:
return isChecked() ? checkedCheckBoxAction : uncheckedCheckBoxAction;
case LinkRole:
case WebCoreLinkRole:
return linkAction;
case PopUpButtonRole:
return menuListAction;
case MenuListPopupRole:
return menuListPopupAction;
default:
return noAction;
}
}
#endif
bool AccessibilityObject::ariaIsMultiline() const
{
return equalIgnoringCase(getAttribute(aria_multilineAttr), "true");
}
const AtomicString& AccessibilityObject::invalidStatus() const
{
DEFINE_STATIC_LOCAL(const AtomicString, invalidStatusFalse, ("false", AtomicString::ConstructFromLiteral));
// aria-invalid can return false (default), grammer, spelling, or true.
const AtomicString& ariaInvalid = getAttribute(aria_invalidAttr);
// If empty or not present, it should return false.
if (ariaInvalid.isEmpty())
return invalidStatusFalse;
return ariaInvalid;
}
bool AccessibilityObject::hasAttribute(const QualifiedName& attribute) const
{
Node* elementNode = node();
if (!elementNode)
return false;
if (!elementNode->isElementNode())
return false;
Element* element = static_cast<Element*>(elementNode);
return element->fastHasAttribute(attribute);
}
const AtomicString& AccessibilityObject::getAttribute(const QualifiedName& attribute) const
{
Node* elementNode = node();
if (!elementNode)
return nullAtom;
if (!elementNode->isElementNode())
return nullAtom;
Element* element = static_cast<Element*>(elementNode);
return element->fastGetAttribute(attribute);
}
// Lacking concrete evidence of orientation, horizontal means width > height. vertical is height > width;
AccessibilityOrientation AccessibilityObject::orientation() const
{
LayoutRect bounds = elementRect();
if (bounds.size().width() > bounds.size().height())
return AccessibilityOrientationHorizontal;
if (bounds.size().height() > bounds.size().width())
return AccessibilityOrientationVertical;
// A tie goes to horizontal.
return AccessibilityOrientationHorizontal;
}
bool AccessibilityObject::isDescendantOfObject(const AccessibilityObject* axObject) const
{
if (!axObject || !axObject->hasChildren())
return false;
for (const AccessibilityObject* parent = parentObject(); parent; parent = parent->parentObject()) {
if (parent == axObject)
return true;
}
return false;
}
bool AccessibilityObject::isAncestorOfObject(const AccessibilityObject* axObject) const
{
if (!axObject)
return false;
return this == axObject || axObject->isDescendantOfObject(this);
}
AccessibilityObject* AccessibilityObject::firstAnonymousBlockChild() const
{
for (AccessibilityObject* child = firstChild(); child; child = child->nextSibling()) {
if (child->renderer() && child->renderer()->isAnonymousBlock())
return child;
}
return 0;
}
typedef HashMap<String, AccessibilityRole, CaseFoldingHash> ARIARoleMap;
struct RoleEntry {
String ariaRole;
AccessibilityRole webcoreRole;
};
static ARIARoleMap* createARIARoleMap()
{
const RoleEntry roles[] = {
{ "alert", ApplicationAlertRole },
{ "alertdialog", ApplicationAlertDialogRole },
{ "application", LandmarkApplicationRole },
{ "article", DocumentArticleRole },
{ "banner", LandmarkBannerRole },
{ "button", ButtonRole },
{ "checkbox", CheckBoxRole },
{ "complementary", LandmarkComplementaryRole },
{ "contentinfo", LandmarkContentInfoRole },
{ "dialog", ApplicationDialogRole },
{ "directory", DirectoryRole },
{ "grid", TableRole },
{ "gridcell", CellRole },
{ "columnheader", ColumnHeaderRole },
{ "combobox", ComboBoxRole },
{ "definition", DefinitionListDefinitionRole },
{ "document", DocumentRole },
{ "rowheader", RowHeaderRole },
{ "group", GroupRole },
{ "heading", HeadingRole },
{ "img", ImageRole },
{ "link", WebCoreLinkRole },
{ "list", ListRole },
{ "listitem", ListItemRole },
{ "listbox", ListBoxRole },
{ "log", ApplicationLogRole },
// "option" isn't here because it may map to different roles depending on the parent element's role
{ "main", LandmarkMainRole },
{ "marquee", ApplicationMarqueeRole },
{ "math", DocumentMathRole },
{ "menu", MenuRole },
{ "menubar", MenuBarRole },
{ "menuitem", MenuItemRole },
{ "menuitemcheckbox", MenuItemRole },
{ "menuitemradio", MenuItemRole },
{ "note", DocumentNoteRole },
{ "navigation", LandmarkNavigationRole },
{ "option", ListBoxOptionRole },
{ "presentation", PresentationalRole },
{ "progressbar", ProgressIndicatorRole },
{ "radio", RadioButtonRole },
{ "radiogroup", RadioGroupRole },
{ "region", DocumentRegionRole },
{ "row", RowRole },
{ "scrollbar", ScrollBarRole },
{ "search", LandmarkSearchRole },
{ "separator", SplitterRole },
{ "slider", SliderRole },
{ "spinbutton", SpinButtonRole },
{ "status", ApplicationStatusRole },
{ "tab", TabRole },
{ "tablist", TabListRole },
{ "tabpanel", TabPanelRole },
{ "text", StaticTextRole },
{ "textbox", TextAreaRole },
{ "timer", ApplicationTimerRole },
{ "toolbar", ToolbarRole },
{ "tooltip", UserInterfaceTooltipRole },
{ "tree", TreeRole },
{ "treegrid", TreeGridRole },
{ "treeitem", TreeItemRole }
};
ARIARoleMap* roleMap = new ARIARoleMap;
for (size_t i = 0; i < WTF_ARRAY_LENGTH(roles); ++i)
roleMap->set(roles[i].ariaRole, roles[i].webcoreRole);
return roleMap;
}
AccessibilityRole AccessibilityObject::ariaRoleToWebCoreRole(const String& value)
{
ASSERT(!value.isEmpty());
static const ARIARoleMap* roleMap = createARIARoleMap();
Vector<String> roleVector;
value.split(' ', roleVector);
AccessibilityRole role = UnknownRole;
unsigned size = roleVector.size();
for (unsigned i = 0; i < size; ++i) {
String roleName = roleVector[i];
role = roleMap->get(roleName);
if (role)
return role;
}
return role;
}
bool AccessibilityObject::hasHighlighting() const
{
for (Node* node = this->node(); node; node = node->parentNode()) {
if (node->hasTagName(markTag))
return true;
}
return false;
}
const AtomicString& AccessibilityObject::placeholderValue() const
{
const AtomicString& placeholder = getAttribute(placeholderAttr);
if (!placeholder.isEmpty())
return placeholder;
return nullAtom;
}
bool AccessibilityObject::isInsideARIALiveRegion() const
{
if (supportsARIALiveRegion())
return true;
for (AccessibilityObject* axParent = parentObject(); axParent; axParent = axParent->parentObject()) {
if (axParent->supportsARIALiveRegion())
return true;
}
return false;
}
bool AccessibilityObject::supportsARIAAttributes() const
{
return supportsARIALiveRegion()
|| supportsARIADragging()
|| supportsARIADropping()
|| supportsARIAFlowTo()
|| supportsARIAOwns()
|| hasAttribute(aria_labelAttr);
}
bool AccessibilityObject::supportsARIALiveRegion() const
{
const AtomicString& liveRegion = ariaLiveRegionStatus();
return equalIgnoringCase(liveRegion, "polite") || equalIgnoringCase(liveRegion, "assertive");
}
AccessibilityObject* AccessibilityObject::elementAccessibilityHitTest(const IntPoint& point) const
{
// Send the hit test back into the sub-frame if necessary.
if (isAttachment()) {
Widget* widget = widgetForAttachmentView();
// Normalize the point for the widget's bounds.
if (widget && widget->isFrameView())
return axObjectCache()->getOrCreate(widget)->accessibilityHitTest(toPoint(point - widget->frameRect().location()));
}
// Check if there are any mock elements that need to be handled.
size_t count = m_children.size();
for (size_t k = 0; k < count; k++) {
if (m_children[k]->isMockObject() && m_children[k]->elementRect().contains(point))
return m_children[k]->elementAccessibilityHitTest(point);
}
return const_cast<AccessibilityObject*>(this);
}
AXObjectCache* AccessibilityObject::axObjectCache() const
{
Document* doc = document();
if (doc)
return doc->axObjectCache();
return 0;
}
AccessibilityObject* AccessibilityObject::focusedUIElement() const
{
Document* doc = document();
if (!doc)
return 0;
Page* page = doc->page();
if (!page)
return 0;
return AXObjectCache::focusedUIElementForPage(page);
}
AccessibilitySortDirection AccessibilityObject::sortDirection() const
{
const AtomicString& sortAttribute = getAttribute(aria_sortAttr);
if (equalIgnoringCase(sortAttribute, "ascending"))
return SortDirectionAscending;
if (equalIgnoringCase(sortAttribute, "descending"))
return SortDirectionDescending;
return SortDirectionNone;
}
bool AccessibilityObject::supportsRangeValue() const
{
return isProgressIndicator()
|| isSlider()
|| isScrollbar()
|| isSpinButton();
}
bool AccessibilityObject::supportsARIAExpanded() const
{
return !getAttribute(aria_expandedAttr).isEmpty();
}
bool AccessibilityObject::isExpanded() const
{
if (equalIgnoringCase(getAttribute(aria_expandedAttr), "true"))
return true;
return false;
}
AccessibilityButtonState AccessibilityObject::checkboxOrRadioValue() const
{
// If this is a real checkbox or radio button, AccessibilityRenderObject will handle.
// If it's an ARIA checkbox or radio, the aria-checked attribute should be used.
const AtomicString& result = getAttribute(aria_checkedAttr);
if (equalIgnoringCase(result, "true"))
return ButtonStateOn;
if (equalIgnoringCase(result, "mixed"))
return ButtonStateMixed;
return ButtonStateOff;
}
// This is a 1-dimensional scroll offset helper function that's applied
// separately in the horizontal and vertical directions, because the
// logic is the same. The goal is to compute the best scroll offset
// in order to make an object visible within a viewport.
//
// In case the whole object cannot fit, you can specify a
// subfocus - a smaller region within the object that should
// be prioritized. If the whole object can fit, the subfocus is
// ignored.
//
// Example: the viewport is scrolled to the right just enough
// that the object is in view.
// Before:
// +----------Viewport---------+
// +---Object---+
// +--SubFocus--+
//
// After:
// +----------Viewport---------+
// +---Object---+
// +--SubFocus--+
//
// When constraints cannot be fully satisfied, the min
// (left/top) position takes precedence over the max (right/bottom).
//
// Note that the return value represents the ideal new scroll offset.
// This may be out of range - the calling function should clip this
// to the available range.
static int computeBestScrollOffset(int currentScrollOffset,
int subfocusMin, int subfocusMax,
int objectMin, int objectMax,
int viewportMin, int viewportMax) {
int viewportSize = viewportMax - viewportMin;
// If the focus size is larger than the viewport size, shrink it in the
// direction of subfocus.
if (objectMax - objectMin > viewportSize) {
// Subfocus must be within focus:
subfocusMin = std::max(subfocusMin, objectMin);
subfocusMax = std::min(subfocusMax, objectMax);
// Subfocus must be no larger than the viewport size; favor top/left.
if (subfocusMax - subfocusMin > viewportSize)
subfocusMax = subfocusMin + viewportSize;
if (subfocusMin + viewportSize > objectMax)
objectMin = objectMax - viewportSize;
else {
objectMin = subfocusMin;
objectMax = subfocusMin + viewportSize;
}
}
// Exit now if the focus is already within the viewport.
if (objectMin - currentScrollOffset >= viewportMin
&& objectMax - currentScrollOffset <= viewportMax)
return currentScrollOffset;
// Scroll left if we're too far to the right.
if (objectMax - currentScrollOffset > viewportMax)
return objectMax - viewportMax;
// Scroll right if we're too far to the left.
if (objectMin - currentScrollOffset < viewportMin)
return objectMin - viewportMin;
ASSERT_NOT_REACHED();
// This shouldn't happen.
return currentScrollOffset;
}
void AccessibilityObject::scrollToMakeVisible() const
{
IntRect objectRect = pixelSnappedIntRect(boundingBoxRect());
objectRect.setLocation(IntPoint());
scrollToMakeVisibleWithSubFocus(objectRect);
}
void AccessibilityObject::scrollToMakeVisibleWithSubFocus(const IntRect& subfocus) const
{
// Search up the parent chain until we find the first one that's scrollable.
AccessibilityObject* scrollParent = parentObject();
ScrollableArea* scrollableArea;
for (scrollableArea = 0;
scrollParent && !(scrollableArea = scrollParent->getScrollableAreaIfScrollable());
scrollParent = scrollParent->parentObject()) { }
if (!scrollableArea)
return;
LayoutRect objectRect = boundingBoxRect();
IntPoint scrollPosition = scrollableArea->scrollPosition();
IntRect scrollVisibleRect = scrollableArea->visibleContentRect();
int desiredX = computeBestScrollOffset(
scrollPosition.x(),
objectRect.x() + subfocus.x(), objectRect.x() + subfocus.maxX(),
objectRect.x(), objectRect.maxX(),
0, scrollVisibleRect.width());
int desiredY = computeBestScrollOffset(
scrollPosition.y(),
objectRect.y() + subfocus.y(), objectRect.y() + subfocus.maxY(),
objectRect.y(), objectRect.maxY(),
0, scrollVisibleRect.height());
scrollParent->scrollTo(IntPoint(desiredX, desiredY));
// Recursively make sure the scroll parent itself is visible.
if (scrollParent->parentObject())
scrollParent->scrollToMakeVisible();
}
void AccessibilityObject::scrollToGlobalPoint(const IntPoint& globalPoint) const
{
// Search up the parent chain and create a vector of all scrollable parent objects
// and ending with this object itself.
Vector<const AccessibilityObject*> objects;
AccessibilityObject* parentObject;
for (parentObject = this->parentObject(); parentObject; parentObject = parentObject->parentObject()) {
if (parentObject->getScrollableAreaIfScrollable())
objects.prepend(parentObject);
}
objects.append(this);
// Start with the outermost scrollable (the main window) and try to scroll the
// next innermost object to the given point.
int offsetX = 0, offsetY = 0;
IntPoint point = globalPoint;
size_t levels = objects.size() - 1;
for (size_t i = 0; i < levels; i++) {
const AccessibilityObject* outer = objects[i];
const AccessibilityObject* inner = objects[i + 1];
ScrollableArea* scrollableArea = outer->getScrollableAreaIfScrollable();
LayoutRect innerRect = inner->isAccessibilityScrollView() ? inner->parentObject()->boundingBoxRect() : inner->boundingBoxRect();
LayoutRect objectRect = innerRect;
IntPoint scrollPosition = scrollableArea->scrollPosition();
// Convert the object rect into local coordinates.
objectRect.move(offsetX, offsetY);
if (!outer->isAccessibilityScrollView())
objectRect.move(scrollPosition.x(), scrollPosition.y());
int desiredX = computeBestScrollOffset(
0,
objectRect.x(), objectRect.maxX(),
objectRect.x(), objectRect.maxX(),
point.x(), point.x());
int desiredY = computeBestScrollOffset(
0,
objectRect.y(), objectRect.maxY(),
objectRect.y(), objectRect.maxY(),
point.y(), point.y());
outer->scrollTo(IntPoint(desiredX, desiredY));
if (outer->isAccessibilityScrollView() && !inner->isAccessibilityScrollView()) {
// If outer object we just scrolled is a scroll view (main window or iframe) but the
// inner object is not, keep track of the coordinate transformation to apply to
// future nested calculations.
scrollPosition = scrollableArea->scrollPosition();
offsetX -= (scrollPosition.x() + point.x());
offsetY -= (scrollPosition.y() + point.y());
point.move(scrollPosition.x() - innerRect.x(),
scrollPosition.y() - innerRect.y());
} else if (inner->isAccessibilityScrollView()) {
// Otherwise, if the inner object is a scroll view, reset the coordinate transformation.
offsetX = 0;
offsetY = 0;
}
}
}
bool AccessibilityObject::cachedIsIgnoredValue()
{
if (m_cachedIsIgnoredValue == DefaultBehavior)
m_cachedIsIgnoredValue = accessibilityIsIgnored() ? IgnoreObject : IncludeObject;
return m_cachedIsIgnoredValue == IgnoreObject;
}
void AccessibilityObject::setCachedIsIgnoredValue(bool isIgnored)
{
m_cachedIsIgnoredValue = isIgnored ? IgnoreObject : IncludeObject;
}
void AccessibilityObject::notifyIfIgnoredValueChanged()
{
bool isIgnored = accessibilityIsIgnored();
if (cachedIsIgnoredValue() != isIgnored) {
axObjectCache()->childrenChanged(parentObject());
setCachedIsIgnoredValue(isIgnored);
}
}
bool AccessibilityObject::ariaPressedIsPresent() const
{
return !getAttribute(aria_pressedAttr).isEmpty();
}
TextIteratorBehavior AccessibilityObject::textIteratorBehaviorForTextRange() const
{
TextIteratorBehavior behavior = TextIteratorIgnoresStyleVisibility;
#if PLATFORM(GTK)
// We need to emit replaced elements for GTK, and present
// them with the 'object replacement character' (0xFFFC).
behavior = static_cast<TextIteratorBehavior>(behavior | TextIteratorEmitsObjectReplacementCharacters);
#endif
return behavior;
}
AccessibilityRole AccessibilityObject::buttonRoleType() const
{
// If aria-pressed is present, then it should be exposed as a toggle button.
// http://www.w3.org/TR/wai-aria/states_and_properties#aria-pressed
if (ariaPressedIsPresent())
return ToggleButtonRole;
if (ariaHasPopup())
return PopUpButtonRole;
// We don't contemplate RadioButtonRole, as it depends on the input
// type.
return ButtonRole;
}
bool AccessibilityObject::isButton() const
{
AccessibilityRole role = roleValue();
return role == ButtonRole || role == PopUpButtonRole || role == ToggleButtonRole;
}
} // namespace WebCore
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.class public abstract Lcom/android/internal/view/IInputMethodClient$Stub;
.super Landroid/os/Binder;
.source "IInputMethodClient.java"
# interfaces
.implements Lcom/android/internal/view/IInputMethodClient;
# annotations
.annotation system Ldalvik/annotation/EnclosingClass;
value = Lcom/android/internal/view/IInputMethodClient;
.end annotation
.annotation system Ldalvik/annotation/InnerClass;
accessFlags = 0x409
name = "Stub"
.end annotation
.annotation system Ldalvik/annotation/MemberClasses;
value = {
Lcom/android/internal/view/IInputMethodClient$Stub$Proxy;
}
.end annotation
# static fields
.field private static final DESCRIPTOR:Ljava/lang/String; = "com.android.internal.view.IInputMethodClient"
.field static final TRANSACTION_onBindMethod:I = 0x2
.field static final TRANSACTION_onUnbindMethod:I = 0x3
.field static final TRANSACTION_setActive:I = 0x4
.field static final TRANSACTION_setUsingInputMethod:I = 0x1
# direct methods
.method public constructor <init>()V
.locals 1
.prologue
.line 18
invoke-direct {p0}, Landroid/os/Binder;-><init>()V
.line 19
const-string v0, "com.android.internal.view.IInputMethodClient"
invoke-virtual {p0, p0, v0}, Lcom/android/internal/view/IInputMethodClient$Stub;->attachInterface(Landroid/os/IInterface;Ljava/lang/String;)V
.line 20
return-void
.end method
.method public static asInterface(Landroid/os/IBinder;)Lcom/android/internal/view/IInputMethodClient;
.locals 2
.parameter "obj"
.prologue
.line 27
if-nez p0, :cond_0
.line 28
const/4 v0, 0x0
.line 34
:goto_0
return-object v0
.line 30
:cond_0
const-string v1, "com.android.internal.view.IInputMethodClient"
invoke-interface {p0, v1}, Landroid/os/IBinder;->queryLocalInterface(Ljava/lang/String;)Landroid/os/IInterface;
move-result-object v0
.line 31
.local v0, iin:Landroid/os/IInterface;
if-eqz v0, :cond_1
instance-of v1, v0, Lcom/android/internal/view/IInputMethodClient;
if-eqz v1, :cond_1
.line 32
check-cast v0, Lcom/android/internal/view/IInputMethodClient;
goto :goto_0
.line 34
:cond_1
new-instance v0, Lcom/android/internal/view/IInputMethodClient$Stub$Proxy;
.end local v0 #iin:Landroid/os/IInterface;
invoke-direct {v0, p0}, Lcom/android/internal/view/IInputMethodClient$Stub$Proxy;-><init>(Landroid/os/IBinder;)V
goto :goto_0
.end method
# virtual methods
.method public asBinder()Landroid/os/IBinder;
.locals 0
.prologue
.line 38
return-object p0
.end method
.method public onTransact(ILandroid/os/Parcel;Landroid/os/Parcel;I)Z
.locals 3
.parameter "code"
.parameter "data"
.parameter "reply"
.parameter "flags"
.annotation system Ldalvik/annotation/Throws;
value = {
Landroid/os/RemoteException;
}
.end annotation
.prologue
const/4 v0, 0x0
const/4 v1, 0x1
.line 42
sparse-switch p1, :sswitch_data_0
.line 87
invoke-super {p0, p1, p2, p3, p4}, Landroid/os/Binder;->onTransact(ILandroid/os/Parcel;Landroid/os/Parcel;I)Z
move-result v1
:goto_0
return v1
.line 46
:sswitch_0
const-string v2, "com.android.internal.view.IInputMethodClient"
invoke-virtual {p3, v2}, Landroid/os/Parcel;->writeString(Ljava/lang/String;)V
goto :goto_0
.line 51
:sswitch_1
const-string v2, "com.android.internal.view.IInputMethodClient"
invoke-virtual {p2, v2}, Landroid/os/Parcel;->enforceInterface(Ljava/lang/String;)V
.line 53
invoke-virtual {p2}, Landroid/os/Parcel;->readInt()I
move-result v2
if-eqz v2, :cond_0
move v0, v1
.line 54
.local v0, _arg0:Z
:cond_0
invoke-virtual {p0, v0}, Lcom/android/internal/view/IInputMethodClient$Stub;->setUsingInputMethod(Z)V
goto :goto_0
.line 59
.end local v0 #_arg0:Z
:sswitch_2
const-string v2, "com.android.internal.view.IInputMethodClient"
invoke-virtual {p2, v2}, Landroid/os/Parcel;->enforceInterface(Ljava/lang/String;)V
.line 61
invoke-virtual {p2}, Landroid/os/Parcel;->readInt()I
move-result v2
if-eqz v2, :cond_1
.line 62
sget-object v2, Lcom/android/internal/view/InputBindResult;->CREATOR:Landroid/os/Parcelable$Creator;
invoke-interface {v2, p2}, Landroid/os/Parcelable$Creator;->createFromParcel(Landroid/os/Parcel;)Ljava/lang/Object;
move-result-object v0
check-cast v0, Lcom/android/internal/view/InputBindResult;
.line 67
.local v0, _arg0:Lcom/android/internal/view/InputBindResult;
:goto_1
invoke-virtual {p0, v0}, Lcom/android/internal/view/IInputMethodClient$Stub;->onBindMethod(Lcom/android/internal/view/InputBindResult;)V
goto :goto_0
.line 65
.end local v0 #_arg0:Lcom/android/internal/view/InputBindResult;
:cond_1
const/4 v0, 0x0
.restart local v0 #_arg0:Lcom/android/internal/view/InputBindResult;
goto :goto_1
.line 72
.end local v0 #_arg0:Lcom/android/internal/view/InputBindResult;
:sswitch_3
const-string v2, "com.android.internal.view.IInputMethodClient"
invoke-virtual {p2, v2}, Landroid/os/Parcel;->enforceInterface(Ljava/lang/String;)V
.line 74
invoke-virtual {p2}, Landroid/os/Parcel;->readInt()I
move-result v0
.line 75
.local v0, _arg0:I
invoke-virtual {p0, v0}, Lcom/android/internal/view/IInputMethodClient$Stub;->onUnbindMethod(I)V
goto :goto_0
.line 80
.end local v0 #_arg0:I
:sswitch_4
const-string v2, "com.android.internal.view.IInputMethodClient"
invoke-virtual {p2, v2}, Landroid/os/Parcel;->enforceInterface(Ljava/lang/String;)V
.line 82
invoke-virtual {p2}, Landroid/os/Parcel;->readInt()I
move-result v2
if-eqz v2, :cond_2
move v0, v1
.line 83
.local v0, _arg0:Z
:cond_2
invoke-virtual {p0, v0}, Lcom/android/internal/view/IInputMethodClient$Stub;->setActive(Z)V
goto :goto_0
.line 42
:sswitch_data_0
.sparse-switch
0x1 -> :sswitch_1
0x2 -> :sswitch_2
0x3 -> :sswitch_3
0x4 -> :sswitch_4
0x5f4e5446 -> :sswitch_0
.end sparse-switch
.end method
| {'content_hash': 'bc6d202772f46cd5a1b93e5fbd0084d1', 'timestamp': '', 'source': 'github', 'line_count': 257, 'max_line_length': 145, 'avg_line_length': 24.53307392996109, 'alnum_prop': 0.6832672482157018, 'repo_name': 'baidurom/reference', 'id': '446c8ecfe2571cc9ee3899c7e2a4c13be6b4900a', 'size': '6305', 'binary': False, 'copies': '11', 'ref': 'refs/heads/coron-4.2', 'path': 'aosp/framework.jar.out/smali/com/android/internal/view/IInputMethodClient$Stub.smali', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
<?php
namespace PiggyBox\OrderBundle\Form\Type;
use Symfony\Component\Form\AbstractType;
use Symfony\Component\Form\FormInterface;
use Symfony\Component\Form\FormBuilderInterface;
use Symfony\Component\Form\FormView;
use Symfony\Component\Form\Extension\Core\DataTransformer\DateTimeToLocalizedStringTransformer;
use PiggyBox\OrderBundle\Form\DataTransformer\DateTimeToArrayTransformer;
use Symfony\Component\Form\Extension\Core\DataTransformer\DateTimeToStringTransformer;
use Symfony\Component\Form\Extension\Core\DataTransformer\DateTimeToTimestampTransformer;
use Symfony\Component\Form\ReversedTransformer;
use Symfony\Component\OptionsResolver\Options;
use Symfony\Component\OptionsResolver\OptionsResolverInterface;
use Symfony\Component\OptionsResolver\Exception\InvalidOptionsException;
class DateUniqueSelectorType extends AbstractType
{
const DEFAULT_FORMAT = \IntlDateFormatter::FULL;
const HTML5_FORMAT = 'yyyy-MM-dd';
private static $acceptedFormats = array(
\IntlDateFormatter::FULL,
\IntlDateFormatter::LONG,
\IntlDateFormatter::MEDIUM,
\IntlDateFormatter::SHORT,
);
/**
* {@inheritdoc}
*/
public function buildForm(FormBuilderInterface $builder, array $options)
{
$dateFormat = is_int($options['format']) ? $options['format'] : self::DEFAULT_FORMAT;
$timeFormat = \IntlDateFormatter::NONE;
$calendar = \IntlDateFormatter::GREGORIAN;
$pattern = is_string($options['format']) ? $options['format'] : null;
if (!in_array($dateFormat, self::$acceptedFormats, true)) {
throw new InvalidOptionsException('The "format" option must be one of the IntlDateFormatter constants (FULL, LONG, MEDIUM, SHORT) or a string representing a custom format.');
}
if (null !== $pattern && (false === strpos($pattern, 'y') || false === strpos($pattern, 'M') || false === strpos($pattern, 'd'))) {
throw new InvalidOptionsException(sprintf('The "format" option should contain the letters "y", "M" and "d". Its current value is "%s".', $pattern));
}
if ('single_text' === $options['widget']) {
$builder->addViewTransformer(new DateTimeToLocalizedStringTransformer(
$options['model_timezone'],
$options['view_timezone'],
$dateFormat,
$timeFormat,
$calendar,
$pattern
));
} else {
$dateOption = $yearOptions = $monthOptions = $dayOptions = array(
'error_bubbling' => true,
);
$formatter = new \IntlDateFormatter(
\Locale::getDefault(),
$dateFormat,
$timeFormat,
'UTC',
$calendar,
$pattern
);
$formatter->setLenient(false);
if ('choice' === $options['widget']) {
// Only pass a subset of the options to children
$dateOption['choices'] = $this->listUniqueDate($options['number_of_days'], $options['closed_days'], $options['start_today']);
//$dayOptions['choices'] = $this->formatTimestamps($formatter, '/d+/', $this->listDays($options['days']));
//$dayOptions['empty_value'] = $options['empty_value']['day'];
}
// Append generic carry-along options
foreach (array('required', 'translation_domain') as $passOpt) {
$yearOptions[$passOpt] = $monthOptions[$passOpt] = $dayOptions[$passOpt] = $options[$passOpt];
}
$builder
->add('date', $options['widget'], $dateOption)
->addViewTransformer(new DateTimeToArrayTransformer(
$options['model_timezone'], $options['view_timezone'], array('date')
))
->setAttribute('formatter', $formatter)
;
}
if ('string' === $options['input']) {
$builder->addModelTransformer(new ReversedTransformer(
new DateTimeToStringTransformer($options['model_timezone'], $options['model_timezone'], 'Y-m-d')
));
} elseif ('timestamp' === $options['input']) {
$builder->addModelTransformer(new ReversedTransformer(
new DateTimeToTimestampTransformer($options['model_timezone'], $options['model_timezone'])
));
} elseif ('array' === $options['input']) {
$builder->addModelTransformer(new ReversedTransformer(
new DateTimeToArrayTransformer($options['model_timezone'], $options['model_timezone'], array('year', 'month', 'day'))
));
}
}
/**
* {@inheritdoc}
*/
public function finishView(FormView $view, FormInterface $form, array $options)
{
$view->vars['widget'] = $options['widget'];
// Change the input to a HTML5 date input if
// * the widget is set to "single_text"
// * the format matches the one expected by HTML5
if ('single_text' === $options['widget'] && self::HTML5_FORMAT === $options['format']) {
$view->vars['type'] = 'date';
}
if ($form->getConfig()->hasAttribute('formatter')) {
$pattern = $form->getConfig()->getAttribute('formatter')->getPattern();
// set right order with respect to locale (e.g.: de_DE=dd.MM.yy; en_US=M/d/yy)
// lookup various formats at http://userguide.icu-project.org/formatparse/datetime
if (preg_match('/^([yMd]+).+([yMd]+).+([yMd]+)$/', $pattern)) {
$pattern = preg_replace(array('/y+/', '/M+/', '/d+/'), array('{{ year }}', '{{ month }}', '{{ day }}'), $pattern);
} else {
// default fallback
$pattern = '{{ year }}-{{ month }}-{{ day }}';
}
$view->vars['date_pattern'] = $pattern;
}
}
/**
* {@inheritdoc}
*/
public function setDefaultOptions(OptionsResolverInterface $resolver)
{
$compound = function (Options $options) {
return $options['widget'] !== 'single_text';
};
$emptyValue = $emptyValueDefault = function (Options $options) {
return $options['required'] ? null : '';
};
$emptyValueNormalizer = function (Options $options, $emptyValue) use ($emptyValueDefault) {
if (is_array($emptyValue)) {
$default = $emptyValueDefault($options);
return array_merge(
array('year' => $default, 'month' => $default, 'day' => $default),
$emptyValue
);
}
return array(
'year' => $emptyValue,
'month' => $emptyValue,
'day' => $emptyValue
);
};
// BC until Symfony 2.3
$modelTimezone = function (Options $options) {
return $options['data_timezone'];
};
// BC until Symfony 2.3
$viewTimezone = function (Options $options) {
return $options['user_timezone'];
};
$resolver->setDefaults(array(
'years' => range(date('Y') - 5, date('Y') + 5),
'months' => range(1, 12),
'days' => range(1, 31),
'widget' => 'choice',
'input' => 'datetime',
'format' => self::HTML5_FORMAT,
'model_timezone' => $modelTimezone,
'view_timezone' => $viewTimezone,
// Deprecated timezone options
'data_timezone' => null,
'user_timezone' => null,
'empty_value' => $emptyValue,
// Don't modify \DateTime classes by reference, we treat
// them like immutable value objects
'by_reference' => false,
'error_bubbling' => false,
// If initialized with a \DateTime object, FormType initializes
// this option to "\DateTime". Since the internal, normalized
// representation is not \DateTime, but an array, we need to unset
// this option.
'data_class' => null,
'compound' => $compound,
'number_of_days' => 8,
'closed_days' => array(),
'start_today' => true,
));
$resolver->setNormalizers(array(
'empty_value' => $emptyValueNormalizer,
));
$resolver->setAllowedValues(array(
'input' => array(
'datetime',
'string',
'timestamp',
'array',
),
'widget' => array(
'single_text',
'text',
'choice',
),
));
$resolver->setAllowedTypes(array(
'format' => array('int', 'string'),
));
}
/**
* {@inheritdoc}
*/
public function getParent()
{
return 'form';
}
/**
* {@inheritdoc}
*/
public function getName()
{
return 'date_unique_selector';
}
private function formatTimestamps(\IntlDateFormatter $formatter, $regex, array $timestamps)
{
$pattern = $formatter->getPattern();
$timezone = $formatter->getTimezoneId();
$formatter->setTimezoneId(\DateTimeZone::UTC);
if (preg_match($regex, $pattern, $matches)) {
$formatter->setPattern($matches[0]);
foreach ($timestamps as $key => $timestamp) {
$timestamps[$key] = $formatter->format($timestamp);
}
// I'd like to clone the formatter above, but then we get a
// segmentation fault, so let's restore the old state instead
$formatter->setPattern($pattern);
}
$formatter->setTimezoneId($timezone);
return $timestamps;
}
private function listUniqueDate($number_of_days, $closed_days, $start_today)
{
$result = array();
$weekBuffer = array();
$today = new \DateTime('now');
if ($start_today == false) {
$today->modify('+1 day');
}
for ($i=0; $i < $number_of_days; $i++) {
if (!in_array($today->format('N'), $closed_days)) {
$weekBuffer[$this->twig_localized_date_filter($today,'full','none','en_EN')] = $this->twig_localized_date_filter($today,'full','none','fr_FR');
}
if ($today->format('N') == 7) {
(empty($result)) ? ($result['Cette semaine'] = $weekBuffer): ($result['Semaine Num. '.$today->format('W')] = $weekBuffer);
$weekBuffer = array();
}
$today->modify('+1 day');
}
return $result;
}
private function twig_localized_date_filter($date, $dateFormat = 'medium', $timeFormat = 'medium', $locale = null)
{
$formatValues = array(
'none' => \IntlDateFormatter::NONE,
'short' => \IntlDateFormatter::SHORT,
'medium' => \IntlDateFormatter::MEDIUM,
'long' => \IntlDateFormatter::LONG,
'full' => \IntlDateFormatter::FULL,
);
$formatter = \IntlDateFormatter::create(
$locale !== null ? $locale : \Locale::getDefault(),
$formatValues[$dateFormat],
$formatValues[$timeFormat],
date_default_timezone_get()
);
if (!$date instanceof \DateTime) {
if (ctype_digit((string) $date)) {
$date = new \DateTime('@'.$date);
$date->setTimezone(new DateTimeZone(date_default_timezone_get()));
} else {
$date = new \DateTime($date);
}
}
return $formatter->format($date->getTimestamp());
}
}
| {'content_hash': '09393dbc6dfe3dec429b56d0eccfbce9', 'timestamp': '', 'source': 'github', 'line_count': 322, 'max_line_length': 186, 'avg_line_length': 37.04347826086956, 'alnum_prop': 0.5352951039570758, 'repo_name': 'julienbourdeau/PiggyBox', 'id': '6b9a2d204f50a8266c11d41c3b28c737a4ddfc35', 'size': '11928', 'binary': False, 'copies': '1', 'ref': 'refs/heads/develop', 'path': 'src/PiggyBox/OrderBundle/Form/Type/DateUniqueSelectorType.php', 'mode': '33261', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '463975'}, {'name': 'JavaScript', 'bytes': '7118'}, {'name': 'PHP', 'bytes': '323581'}, {'name': 'Puppet', 'bytes': '5708'}, {'name': 'Ruby', 'bytes': '1506'}]} |
/***********************************************************************
created: 30/10/2010
author: Lukas E Meindl
purpose: Interface to base class for ColourPicker Widget
*************************************************************************/
/***************************************************************************
* Copyright (C) 2004 - 2011 Paul D Turner & The CEGUI Development Team
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
***************************************************************************/
#ifndef _CEGUIColourPicker_h_
#define _CEGUIColourPicker_h_
#include "CEGUI/CommonDialogs/Module.h"
#include "CEGUI/CommonDialogs/ColourPicker/Controls.h"
#include "CEGUI/Window.h"
#if defined(_MSC_VER)
# pragma warning(push)
# pragma warning(disable : 4251)
#endif
// Start of CEGUI namespace section
namespace CEGUI
{
//!Base class for the ColourPicker widget
class CEGUI_COMMONDIALOGS_API ColourPicker : public Window
{
public:
//! Constructor for ColourPicker class.
ColourPicker(const String& type, const String& name);
//! Destructor for ColourPicker class.
~ColourPicker(void);
//! Namespace for global events
static const String EventNamespace;
//! Window factory name
static const String WidgetTypeName;
// generated internally by Window
/** Event fired when the ColourPickerControls window is opened.
* Handlers are passed a const WindowEventArgs reference with
* WindowEventArgs::window set to the Window that triggered this event.
*/
static const String EventOpenedPicker;
// generated internally by Window
/** Event fired when the ColourPickerControls window is closed.
* Handlers are passed a const WindowEventArgs reference with
* WindowEventArgs::window set to the Window that triggered this event.
*/
static const String EventClosedPicker;
// generated internally by Window
/** Event fired when a new colour is set and accepted by the colour picker.
* Handlers are passed a const WindowEventArgs reference with
* WindowEventArgs::window set to the Window that triggered this event.
*/
static const String EventAcceptedColour;
/*!
\brief
Set the current colour of the colour picker manually and refresh the
ColourPicker elements accordingly.
\param setting
newColour the selected Colour for the ColourPicker
*/
void setColour(const Colour& newColour);
/*!
\brief
Return the current colour of the colour picker.
*/
Colour getColour();
// overridden from Window base class
void initialiseComponents(void) override;
protected:
//! Widget name for the open button (colour rect) component.
static const String ColourRectName;
/*!\brief
Initialises the properties for the creation of the ColourPickerControls
window and decides if a new window of this type is necessary.
\note
This will be called once during the initialisation of the components.
*/
void initialiseColourPickerControlsWindow();
/*!\brief
Creates the ColourPickerControls window.
\param colourPickerControlsStyle
The window type of the window that will be created.
\note
This will be called once during the initialisation of the components.
*/
void createColourPickerControlsWindow(const String& colourPickerControlsStyle);
/*!
\brief
Return a Window pointer to the ColourRect component widget for this
ColourPicker.
\return
Pointer to a Window object.
\exception UnknownObjectException
Thrown if the colour rectangle component does not exist.
*/
Window* getColourRect(void);
bool colourRect_ColourRectClickedHandler(const EventArgs& e);
virtual void onColourRectClicked(WindowEventArgs& e);
static std::map<Window*, int> s_colourPickerWindows;
bool d_shareColourPickerControlsWindow;
ColourPickerControls* d_colourPickerControlsWindow;
//! selected colour of the ColourPickerControls
Colour d_selectedColour;
};
}
#if defined(_MSC_VER)
# pragma warning(pop)
#endif
#endif
| {'content_hash': '3ab43160d16c71979187da2f27696279', 'timestamp': '', 'source': 'github', 'line_count': 156, 'max_line_length': 83, 'avg_line_length': 33.39102564102564, 'alnum_prop': 0.6817047417930505, 'repo_name': 'cbeck88/cegui-mirror-two', 'id': '9435074dc837dc1ad56c479fc5ba31dd6f9ab2b8', 'size': '5209', 'binary': False, 'copies': '1', 'ref': 'refs/heads/def', 'path': 'cegui/include/CEGUI/CommonDialogs/ColourPicker/ColourPicker.h', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Batchfile', 'bytes': '141'}, {'name': 'C', 'bytes': '422585'}, {'name': 'C++', 'bytes': '20764850'}, {'name': 'CMake', 'bytes': '332760'}, {'name': 'Java', 'bytes': '6178'}, {'name': 'Lua', 'bytes': '131055'}, {'name': 'Makefile', 'bytes': '6808'}, {'name': 'Objective-C', 'bytes': '15620'}, {'name': 'Python', 'bytes': '92177'}, {'name': 'Shell', 'bytes': '32217'}]} |
'use strict';
describe('Subkeys', function () {
var input;
beforeEach(function () {
angular.mock.module('formsAngular');
});
describe('simple subkey', function () {
var $httpBackend, scope, ctrl, elm,
subkeySchema = {
'surname': {'path': 'surname', 'instance': 'String', 'options': {'index': true, 'list': {}}, '_index': true, '$conditionalHandlers': {}},
'forename': {'path': 'forename', 'instance': 'String', 'options': {'index': true, 'list': true}, '_index': true, '$conditionalHandlers': {}},
'exams': {
'schema': {
'subject': {'path': 'subject', 'instance': 'String', 'options': {}, '_index': null, '$conditionalHandlers': {}},
'score': {'path': 'score', 'instance': 'Number', 'options': {}, '_index': null, '$conditionalHandlers': {}}
},
'options': {
'form': {
'formStyle': 'inline',
'subkey': {
'keyList': {'subject': 'English'},
'container': 'fieldset',
'title': 'English Exam'
}
}
}
}
};
afterEach(function () {
$httpBackend.verifyNoOutstandingExpectation();
$httpBackend.verifyNoOutstandingRequest();
});
describe('existing data with selected data present in first position', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$httpBackend.whenGET('/api/f_nested_schema/51c583d5b5c51226db418f16').respond({
'_id': '51c583d5b5c51226db418f16',
'surname': 'Smith',
'forename': 'Anne',
'exams': [
{
'subject': 'English',
'score': 83
},
{
'subject': 'French',
'score': 34
},
{
'subject': 'Maths',
'score': 97
}
]
});
$location.$$path = '/f_nested_schema/English/51c583d5b5c51226db418f16/edit';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
$compile(elm)(scope);
scope.$digest();
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
}));
it('generates correct fields', function () {
// correct number of fields - excluding subkey
input = elm.find('input');
expect(input.length).toBe(3);
var label = angular.element(elm.find('label')[0]);
expect(label.text()).toBe('Surname');
label = angular.element(elm.find('label')[1]);
expect(label.text()).toBe('Forename');
label = angular.element(elm.find('label')[2]);
expect(label.text()).toBe('Score');
input = angular.element(elm.find('input')[2]);
expect(input.val()).toBe('83');
});
});
describe('existing data with selected data present in different position', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$httpBackend.whenGET('/api/f_nested_schema/51c583d5b5c51226db418f16').respond({
'_id': '51c583d5b5c51226db418f16',
'surname': 'Smith',
'forename': 'Anne',
'exams': [
{
'subject': 'French',
'examDate': '2013-03-11T23:00:00.000Z',
'score': 34,
'result': 'fail'
},
{
'subject': 'English',
'examDate': '2013-05-12T23:00:00.000Z',
'score': 83,
'result': 'pass'
},
{
'subject': 'Maths',
'examDate': '2013-05-11T23:00:00.000Z',
'score': 97,
'result': 'distinction'
}
]
});
$location.$$path = '/f_nested_schema/English/51c583d5b5c51226db418f16/edit';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
$compile(elm)(scope);
scope.$digest();
}));
it('gets correct array element', function () {
input = angular.element(elm.find('input')[2]);
expect(input.val()).toBe('83');
});
});
describe('existing data without required subschema', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$httpBackend.whenGET('/api/f_nested_schema/51c583d5b5c51226db418f16').respond({
'_id': '51c583d5b5c51226db418f16',
'surname': 'Smith',
'forename': 'Anne',
'exams': [
{
'subject': 'French',
'examDate': '2013-03-11T23:00:00.000Z',
'score': 34,
'result': 'fail'
},
{
'subject': 'Maths',
'examDate': '2013-05-11T23:00:00.000Z',
'score': 97,
'result': 'distinction'
}
]
});
$location.$$path = '/f_nested_schema/English/51c583d5b5c51226db418f16/edit';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
$compile(elm)(scope);
scope.$digest();
}));
it('creates a new array element', function () {
expect(scope.record.exams.length).toBe(3);
expect(scope.record.exams[2].subject).toBe('English');
});
});
describe('existing data without any subschema', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$httpBackend.whenGET('/api/f_nested_schema/51c583d5b5c51226db418f16').respond({
'_id': '51c583d5b5c51226db418f16',
'surname': 'Smith',
'forename': 'Anne'
});
$location.$$path = '/f_nested_schema/English/51c583d5b5c51226db418f16/edit';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
$compile(elm)(scope);
scope.$digest();
}));
it('creates a new array element', function () {
expect(scope.record.exams.length).toBe(1);
expect(scope.record.exams[0].subject).toBe('English');
});
});
describe('new data', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$location.$$path = '/f_nested_schema/English/new';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
$compile(elm)(scope);
scope.$digest();
}));
it('creates a new array element', function () {
expect(scope.record.exams.length).toBe(1);
expect(scope.record.exams[0].subject).toBe('English');
});
});
});
describe('two subkeys', function () {
var $httpBackend, scope, ctrl, elm,
subkeySchema = {
'surname': {'path': 'surname', 'instance': 'String', 'options': {'index': true, 'list': {}}, '_index': true, '$conditionalHandlers': {}},
'forename': {'path': 'forename', 'instance': 'String', 'options': {'index': true, 'list': true}, '_index': true, '$conditionalHandlers': {}},
'exams': {
'schema': {
'subject': {'path': 'subject', 'instance': 'String', 'options': {}, '_index': null, '$conditionalHandlers': {}},
'score': {'path': 'score', 'instance': 'Number', 'options': {}, '_index': null, '$conditionalHandlers': {}}
},
'options': {
'form': {
'formStyle': 'inline',
'subkey': [
{
'keyList': {'subject': 'English'},
'container': 'fieldset',
'title': 'English Exam'
},
{
'keyList': {'subject': 'Maths'},
'container': 'fieldset',
'title': 'Maths Exam'
}
]
}
}
}
};
afterEach(function () {
$httpBackend.verifyNoOutstandingExpectation();
$httpBackend.verifyNoOutstandingRequest();
});
describe('existing data with selected data', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$httpBackend.whenGET('/api/f_nested_schema/51c583d5b5c51226db418f16').respond({
'_id': '51c583d5b5c51226db418f16',
'surname': 'Smith',
'forename': 'Anne',
'exams': [
{
'subject': 'English',
'score': 83
},
{
'subject': 'French',
'score': 34
},
{
'subject': 'Maths',
'score': 97
}
]
});
$location.$$path = '/f_nested_schema/English/51c583d5b5c51226db418f16/edit';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
$compile(elm)(scope);
scope.$digest();
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
}));
it('generates correct fields', function () {
// correct number of fields - excluding subkey
var input = elm.find('input');
expect(input.length).toBe(4);
var label = angular.element(elm.find('label')[0]);
expect(label.text()).toBe('Surname');
label = angular.element(elm.find('label')[1]);
expect(label.text()).toBe('Forename');
label = angular.element(elm.find('label')[2]);
expect(label.text()).toBe('Score');
label = angular.element(elm.find('label')[3]);
expect(label.text()).toBe('Score');
input = angular.element(elm.find('input')[2]);
expect(input.val()).toBe('83');
input = angular.element(elm.find('input')[3]);
expect(input.val()).toBe('97');
});
});
});
describe('subkey selected by function', function () {
var $httpBackend, scope, ctrl, elm,
subkeySchema = {
'surname': {'path': 'surname', 'instance': 'String', 'options': {'index': true, 'list': {}}, '_index': true, '$conditionalHandlers': {}},
'forename': {'path': 'forename', 'instance': 'String', 'options': {'index': true, 'list': true}, '_index': true, '$conditionalHandlers': {}},
'exams': {
'schema': {
'subject': {'path': 'subject', 'instance': 'String', 'options': {}, '_index': null, '$conditionalHandlers': {}},
'score': {'path': 'score', 'instance': 'Number', 'options': {}, '_index': null, '$conditionalHandlers': {}}
},
'options': {
'form': {
'formStyle': 'inline',
'subkey': {
'selectFunc':'bestResult',
'container': 'fieldset',
'title': 'Best Result'
}
}
}
}
};
afterEach(function () {
$httpBackend.verifyNoOutstandingExpectation();
$httpBackend.verifyNoOutstandingRequest();
});
describe('existing data', function () {
beforeEach(inject(function (_$httpBackend_, $rootScope, $location, $controller, $compile) {
$httpBackend = _$httpBackend_;
$httpBackend.whenGET('/api/schema/f_nested_schema/English').respond(subkeySchema);
$httpBackend.whenGET('/api/f_nested_schema/51c583d5b5c51226db418f16').respond({
'_id': '51c583d5b5c51226db418f16',
'surname': 'Smith',
'forename': 'Anne',
'exams': [
{
'subject': 'English',
'score': 83
},
{
'subject': 'French',
'score': 34
},
{
'subject': 'Maths',
'score': 97
}
]
});
$location.$$path = '/f_nested_schema/English/51c583d5b5c51226db418f16/edit';
elm = angular.element(
'<form name="myForm" class="form-horizontal compact">' +
'<form-input schema="formSchema"></form-input>' +
'</form>');
scope = $rootScope.$new();
$compile(elm)(scope);
scope.$digest();
scope.bestResult = function() { return 2;};
ctrl = $controller('BaseCtrl', {$scope: scope});
$httpBackend.flush();
}));
it('generates correct fields', function () {
// correct number of fields - excluding subkey
input = elm.find('input');
expect(input.length).toBe(4);
var label = angular.element(elm.find('label')[0]);
expect(label.text()).toBe('Surname');
label = angular.element(elm.find('label')[1]);
expect(label.text()).toBe('Forename');
label = angular.element(elm.find('label')[2]);
expect(label.text()).toBe('Subject');
input = angular.element(elm.find('input')[2]);
expect(input.val()).toBe('Maths');
label = angular.element(elm.find('label')[3]);
expect(label.text()).toBe('Score');
input = angular.element(elm.find('input')[3]);
expect(input.val()).toBe('97');
});
});
});
});
| {'content_hash': 'd17b6c93b8c3a4a9ab16b9061913b0ad', 'timestamp': '', 'source': 'github', 'line_count': 430, 'max_line_length': 149, 'avg_line_length': 35.23255813953488, 'alnum_prop': 0.5142574257425743, 'repo_name': 'behzad88/forms-angular', 'id': '3e951b0f0dbd55e50dad83c0feae4cd4fe249969', 'size': '15150', 'binary': False, 'copies': '4', 'ref': 'refs/heads/master', 'path': 'test/unit/subkeySpec.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '563261'}, {'name': 'JavaScript', 'bytes': '619738'}, {'name': 'Shell', 'bytes': '321'}]} |
package org.dcm4chex.archive.web.maverick;
import org.dcm4chex.archive.web.maverick.model.PatientModel;
/**
* @author [email protected]
* @author [email protected]
* @version $Revision: 3150 $ $Date: 2007-02-23 22:35:01 +0800 (周五, 23 2月 2007) $
*/
public class PatientEditCtrl extends Dcm4cheeFormController
{
private long pk = -1;
public final void setPk(long pk)
{
this.pk = pk;
}
public PatientModel getPatient() {
PatientModel pat = FolderForm.getFolderForm(getCtx()).getPatientByPk(pk);
return pat != null ? pat : newPatient();
}
private PatientModel newPatient() {
PatientModel pat = new PatientModel();
pat.setSpecificCharacterSet("ISO_IR 100");
return pat;
}
public String getPopupMsg() {
return FolderForm.getFolderForm(getCtx()).getPopupMsg();
}
}
| {'content_hash': '12ee4260888cd98b625645a22998731e', 'timestamp': '', 'source': 'github', 'line_count': 37, 'max_line_length': 81, 'avg_line_length': 23.10810810810811, 'alnum_prop': 0.6865497076023391, 'repo_name': 'medicayun/medicayundicom', 'id': '51c8c53f3fa9d21b42479b6a0b26924efbef90f2', 'size': '2737', 'binary': False, 'copies': '25', 'ref': 'refs/heads/master', 'path': 'dcm4jboss-all/tags/BRANCHA_TAG1/dcm4jboss-web/src/java/org/dcm4chex/archive/web/maverick/PatientEditCtrl.java', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
using System;
using System.Collections.Generic;
using Exceptionless.Core.Dependency;
using SimpleInjector;
namespace Exceptionless.Core.Utility {
public class SimpleInjectorDependencyResolver : IDependencyResolver {
private readonly Container _container;
public SimpleInjectorDependencyResolver(Container container) {
_container = container;
}
public object GetService(Type serviceType) {
return _container.GetInstance(serviceType);
}
public IEnumerable<object> GetServices(Type serviceType) {
return _container.GetAllInstances(serviceType);
}
}
}
| {'content_hash': '293dcd713e0d9ac53f0c8368c66e20d3', 'timestamp': '', 'source': 'github', 'line_count': 22, 'max_line_length': 73, 'avg_line_length': 29.681818181818183, 'alnum_prop': 0.6998468606431854, 'repo_name': 'adamzolotarev/Exceptionless', 'id': '74a100b26a71c7225b405820379785b2ca3232a2', 'size': '655', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'Source/Core/Utility/SimpleInjectorDependencyResolver.cs', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '47'}, {'name': 'C#', 'bytes': '1558806'}, {'name': 'CSS', 'bytes': '6495'}, {'name': 'HTML', 'bytes': '5533'}, {'name': 'JavaScript', 'bytes': '146'}, {'name': 'PowerShell', 'bytes': '12084'}]} |
/**
* Let's say we want to build an API to make coffee.
* We have a function, `makeCoffee( ... )` with the following signature:
*
* function makeCoffee(sugars, flavor, size, callback);
*
* 1. sugars - number of sugars. optional. non-negative decimal number.
* defaults to 1.
* 2. flavor - flavor of the coffee. optional. string. defaults to 'bitter'.
* 3. size - size of cup. 'small', 'medium', 'large' or any positive integer.
* defaults to 'large'.
* 4. callback - called when coffee is ready.
*/
var decree = require('../');
// Step 1 - Specify the properties of the function's arguments:
// ------------------------------------------------------------
var decs = [{
name: 'sugars',
type: 'nn-number', // non-negative
optional: true,
default: 1
}, {
name: 'flavor',
type: 'string',
optional: true,
default: 'bitter'
}, {
name: 'size',
types: ['string', 'p-int'], // string or positive integer
optional: true,
default: 'large'
}, {
name: 'callback',
type: 'function'
}];
// Step 2 - Create a function which receives an array of arguments and decrees
// if the arguments are valid:
// ---------------------------------------------------------------------------
var judge = decree(decs); // `judge` is a function.
// Step 3 - Use it to handle arguments disambiguation inside your API function.
// Supply a callback which will be called with the disambiguated
// arguments.
// Supply a second callback to handle arguments problems. This
// guarantees no exceptions will be thrown.
// ----------------------------------------------------------------------------
function makeCoffee() {
judge(arguments, function(sugars, flavor, size, callback) {
var msg = size + " cup of " + flavor + " coffe with " + sugars + " sugars.";
// you can be sure that callback is indeed a function:
callback(msg);
}, function(err) {
console.log("Invalid arguments: " + err);
});
}
// Step 4 - Use your function:
// ---------------------------
makeCoffee('sweet', 'small', function(msg) {
console.log(msg); // small cup of sweet coffee with 1 sugars.
});
makeCoffee('sweet', 'small'); // Invalid arguments: Error: Unknown arguments configuration,sweet,small
makeCoffee('foo', function() {}); // Invalid arguments: Error: Arguments ambiguity,Argument 0 matches both flavor (string) and size (string)
| {'content_hash': '4c1df6378ae96002b5dfa0531e253a49', 'timestamp': '', 'source': 'github', 'line_count': 70, 'max_line_length': 140, 'avg_line_length': 35.05714285714286, 'alnum_prop': 0.5745721271393643, 'repo_name': 'coderReview/NTL-ISS-Food-Intake-Tracker', 'id': 'f1bd7bcabfd77d9114c81a7041ae4ab9b6bfca65', 'size': '2454', 'binary': False, 'copies': '12', 'ref': 'refs/heads/master', 'path': 'Backend Services/issfit-api/node_modules/decree/examples/decree_3.js', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'C', 'bytes': '7674'}, {'name': 'CSS', 'bytes': '70936'}, {'name': 'HTML', 'bytes': '1081112'}, {'name': 'JavaScript', 'bytes': '622475'}, {'name': 'Objective-C', 'bytes': '2337557'}, {'name': 'Objective-C++', 'bytes': '10637'}, {'name': 'PLpgSQL', 'bytes': '30687'}, {'name': 'Python', 'bytes': '40699'}, {'name': 'Ruby', 'bytes': '1374'}, {'name': 'Shell', 'bytes': '6454'}]} |
import willie.module
import willie.web
import json
from willie.formatting import bold
@willie.module.commands('munweather')
def munweather(bot, trigger):
"""
munweather - gets the bot to tell you the current weather at the nearest weather station to the
MUN Engineering building coordinates. weather data is retrieved from the Open Weather API.
"""
url = "http://api.openweathermap.org/data/2.5/weather?lat=47.574037&lon=-52.734607"
# parse json into a python dict
data = json.loads(willie.web.get(url))
# get string description and current temperature in Celsius
description = data['weather'][0]['description']
temp = data['main']['temp'] - 273.15
# get humidity and wind speed in km/h
humidity = data['main']['humidity']
windspeed = data['wind']['speed'] * 3.6
answer = "The current weather is {}! It is {:.1f}\N{DEGREE SIGN}C ".format(description,
temp)
if(temp < -5):
answer += "cold! Brrr!"
elif(temp >= -5 and temp < 5):
answer += "chilly!"
elif(temp >= 5 and temp < 20):
answer += "! Rather pleasant!"
elif(temp >= 20 and temp < 25):
answer += " warm!"
else:
answer += " hot!"
answer2 = "The humidity is {}% and the wind speed is {:.1f} km/h.".format(humidity, windspeed)
bot.say(answer)
bot.say(answer2)
bot.say(bold("Woof!"))
| {'content_hash': '8609d793fe46a421fe262949a3d56967', 'timestamp': '', 'source': 'github', 'line_count': 41, 'max_line_length': 99, 'avg_line_length': 33.853658536585364, 'alnum_prop': 0.6282420749279539, 'repo_name': 'MUNComputerScienceSociety/Frisket', 'id': '305827194c255d574590402a7cb1a3bb1f4f94b4', 'size': '1412', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'modules/munweather.py', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Python', 'bytes': '3508'}]} |
@interface FPMultipartUploader : FPUploader
@end
| {'content_hash': '4ed93b221117c9913fdc088be85499f4', 'timestamp': '', 'source': 'github', 'line_count': 3, 'max_line_length': 43, 'avg_line_length': 16.666666666666668, 'alnum_prop': 0.82, 'repo_name': 'MobileXLabs/ios-picker', 'id': '847e1414df90f71672e285bcbb8e16cb69c01a38', 'size': '219', 'binary': False, 'copies': '5', 'ref': 'refs/heads/develop', 'path': 'FPPicker/Shared/FPMultipartUploader.h', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'C', 'bytes': '709'}, {'name': 'Objective-C', 'bytes': '500652'}, {'name': 'Ruby', 'bytes': '3196'}]} |
define(["require", "exports", "../geom/Size"], function (require, exports, Size) {
var ArrayUtils = (function () {
function ArrayUtils() {
}
ArrayUtils.getMaxSize = function (arr) {
var size = new Size(0, 0);
for (var i = 0; i < arr.length; i++) {
size.width = Math.max(arr[i].width, size.width);
size.height = Math.max(arr[i].height, size.height);
}
return size;
};
ArrayUtils.getSize = function (arr) {
var size = new Size(0, 0);
for (var i = 0; i < arr.length; i++) {
size.width += arr[i].width;
size.height += arr[i].height;
}
return size;
};
return ArrayUtils;
})();
return ArrayUtils;
});
| {'content_hash': '3b1ecdd2b18279baead3a2c4135ea474', 'timestamp': '', 'source': 'github', 'line_count': 24, 'max_line_length': 82, 'avg_line_length': 34.291666666666664, 'alnum_prop': 0.46537059538274606, 'repo_name': 'markknol/EaselTS', 'id': 'ba7bbec6c109b0f4b92db0df87b6e116bce391b2', 'size': '823', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'src/easelts/util/ArrayUtils.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '454'}, {'name': 'HTML', 'bytes': '7444'}, {'name': 'JavaScript', 'bytes': '711813'}, {'name': 'TypeScript', 'bytes': '847364'}]} |
import * as React from 'react';
import PropTypes from 'prop-types';
import { TreeList } from '@extjs/ext-react';
declare var Ext:any;
Ext.require('Ext.data.TreeStore');
interface NavMenuProps {
onItemClick: Function,
selection: string
}
/**
* The main navigation menu
*/
const NavMenu: React.SFC<NavMenuProps & any> = ({
onItemClick,
selection,
...props
}) => (
<TreeList
{...props}
ui="nav"
expanderFirst={false}
onItemClick={(tree, item) => onItemClick(item.node.getId())}
selection={selection}
store={{
root: {
children: [
{ id: '/', text: 'Home', iconCls: 'x-fa fa-home', leaf: true },
{ id: '/about', text: 'About', iconCls: 'x-fa fa-info', leaf: true },
]
}
}}
/>
)
export default NavMenu; | {'content_hash': '69980bbf9914a3c7856431afff4a6711', 'timestamp': '', 'source': 'github', 'line_count': 39, 'max_line_length': 89, 'avg_line_length': 22.94871794871795, 'alnum_prop': 0.5217877094972067, 'repo_name': 'dbuhrman/extjs-reactor', 'id': 'fb0605cb0a5ffb2a07d4b0c7122db7bf1fad3676', 'size': '895', 'binary': False, 'copies': '3', 'ref': 'refs/heads/master', 'path': 'packages/reactor-typescript-boilerplate/src/NavMenu.tsx', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '52553'}, {'name': 'HTML', 'bytes': '3188'}, {'name': 'JavaScript', 'bytes': '4057721'}, {'name': 'Ruby', 'bytes': '280'}, {'name': 'TypeScript', 'bytes': '21568'}]} |
package expression
import (
"bytes"
"encoding/binary"
"fmt"
"math"
"net"
"strconv"
"strings"
"time"
"unicode/utf8"
"github.com/google/uuid"
"github.com/pingcap/errors"
"github.com/pingcap/tidb/parser/mysql"
"github.com/pingcap/tidb/parser/terror"
"github.com/pingcap/tidb/sessionctx"
"github.com/pingcap/tidb/sessionctx/variable"
"github.com/pingcap/tidb/types"
"github.com/pingcap/tidb/util/chunk"
"github.com/pingcap/tidb/util/vitess"
"github.com/pingcap/tipb/go-tipb"
)
var (
_ functionClass = &sleepFunctionClass{}
_ functionClass = &lockFunctionClass{}
_ functionClass = &releaseLockFunctionClass{}
_ functionClass = &anyValueFunctionClass{}
_ functionClass = &defaultFunctionClass{}
_ functionClass = &inetAtonFunctionClass{}
_ functionClass = &inetNtoaFunctionClass{}
_ functionClass = &inet6AtonFunctionClass{}
_ functionClass = &inet6NtoaFunctionClass{}
_ functionClass = &isFreeLockFunctionClass{}
_ functionClass = &isIPv4FunctionClass{}
_ functionClass = &isIPv4CompatFunctionClass{}
_ functionClass = &isIPv4MappedFunctionClass{}
_ functionClass = &isIPv6FunctionClass{}
_ functionClass = &isUsedLockFunctionClass{}
_ functionClass = &masterPosWaitFunctionClass{}
_ functionClass = &nameConstFunctionClass{}
_ functionClass = &releaseAllLocksFunctionClass{}
_ functionClass = &uuidFunctionClass{}
_ functionClass = &uuidShortFunctionClass{}
_ functionClass = &vitessHashFunctionClass{}
_ functionClass = &uuidToBinFunctionClass{}
_ functionClass = &binToUUIDFunctionClass{}
_ functionClass = &isUUIDFunctionClass{}
_ functionClass = &tidbShardFunctionClass{}
)
var (
_ builtinFunc = &builtinSleepSig{}
_ builtinFunc = &builtinLockSig{}
_ builtinFunc = &builtinReleaseLockSig{}
_ builtinFunc = &builtinReleaseAllLocksSig{}
_ builtinFunc = &builtinDecimalAnyValueSig{}
_ builtinFunc = &builtinDurationAnyValueSig{}
_ builtinFunc = &builtinIntAnyValueSig{}
_ builtinFunc = &builtinJSONAnyValueSig{}
_ builtinFunc = &builtinRealAnyValueSig{}
_ builtinFunc = &builtinStringAnyValueSig{}
_ builtinFunc = &builtinTimeAnyValueSig{}
_ builtinFunc = &builtinInetAtonSig{}
_ builtinFunc = &builtinInetNtoaSig{}
_ builtinFunc = &builtinInet6AtonSig{}
_ builtinFunc = &builtinInet6NtoaSig{}
_ builtinFunc = &builtinIsIPv4Sig{}
_ builtinFunc = &builtinIsIPv4CompatSig{}
_ builtinFunc = &builtinIsIPv4MappedSig{}
_ builtinFunc = &builtinIsIPv6Sig{}
_ builtinFunc = &builtinIsUUIDSig{}
_ builtinFunc = &builtinUUIDSig{}
_ builtinFunc = &builtinVitessHashSig{}
_ builtinFunc = &builtinUUIDToBinSig{}
_ builtinFunc = &builtinBinToUUIDSig{}
_ builtinFunc = &builtinNameConstIntSig{}
_ builtinFunc = &builtinNameConstRealSig{}
_ builtinFunc = &builtinNameConstDecimalSig{}
_ builtinFunc = &builtinNameConstTimeSig{}
_ builtinFunc = &builtinNameConstDurationSig{}
_ builtinFunc = &builtinNameConstStringSig{}
_ builtinFunc = &builtinNameConstJSONSig{}
_ builtinFunc = &builtinTidbShardSig{}
)
const (
tidbShardBucketCount = 256
)
type sleepFunctionClass struct {
baseFunctionClass
}
func (c *sleepFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETReal)
if err != nil {
return nil, err
}
bf.tp.SetFlen(21)
sig := &builtinSleepSig{bf}
return sig, nil
}
type builtinSleepSig struct {
baseBuiltinFunc
}
func (b *builtinSleepSig) Clone() builtinFunc {
newSig := &builtinSleepSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinSleepSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_sleep
func (b *builtinSleepSig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalReal(b.ctx, row)
if err != nil {
return 0, isNull, err
}
sessVars := b.ctx.GetSessionVars()
if isNull || val < 0 {
// for insert ignore stmt, the StrictSQLMode and ignoreErr should both be considered.
if !sessVars.StmtCtx.BadNullAsWarning {
return 0, false, errIncorrectArgs.GenWithStackByArgs("sleep")
}
err := errIncorrectArgs.GenWithStackByArgs("sleep")
sessVars.StmtCtx.AppendWarning(err)
return 0, false, nil
}
if val > math.MaxFloat64/float64(time.Second.Nanoseconds()) {
return 0, false, errIncorrectArgs.GenWithStackByArgs("sleep")
}
if isKilled := doSleep(val, sessVars); isKilled {
return 1, false, nil
}
return 0, false, nil
}
type lockFunctionClass struct {
baseFunctionClass
}
func (c *lockFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString, types.ETInt)
if err != nil {
return nil, err
}
sig := &builtinLockSig{bf}
bf.tp.SetFlen(1)
return sig, nil
}
type builtinLockSig struct {
baseBuiltinFunc
}
func (b *builtinLockSig) Clone() builtinFunc {
newSig := &builtinLockSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinLockSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_get-lock
func (b *builtinLockSig) evalInt(row chunk.Row) (int64, bool, error) {
lockName, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil {
return 0, isNull, err
}
// Validate that lockName is NOT NULL or empty string
if isNull {
return 0, false, errUserLockWrongName.GenWithStackByArgs("NULL")
}
if lockName == "" || utf8.RuneCountInString(lockName) > 64 {
return 0, false, errUserLockWrongName.GenWithStackByArgs(lockName)
}
maxTimeout := int64(variable.GetSysVar(variable.InnodbLockWaitTimeout).MaxValue)
timeout, isNullTimeout, err := b.args[1].EvalInt(b.ctx, row)
if err != nil {
return 0, false, err
}
if isNullTimeout {
timeout = 0 // Observed in MySQL, gets converted to 1s in TiDB because of min timeout.
}
// A timeout less than zero is expected to be treated as unlimited.
// Because of our implementation being based on pessimistic locks,
// We can't have a timeout greater than innodb_lock_wait_timeout.
// So users are aware, we also attach a warning.
if timeout < 0 || timeout > maxTimeout {
err := errTruncatedWrongValue.GenWithStackByArgs("get_lock", strconv.FormatInt(timeout, 10))
b.ctx.GetSessionVars().StmtCtx.AppendWarning(err)
timeout = maxTimeout
}
// Lock names are case insensitive. Because we can't rely on collations
// being enabled on the internal table, we have to lower it.
lockName = strings.ToLower(lockName)
if utf8.RuneCountInString(lockName) > 64 {
return 0, false, errIncorrectArgs.GenWithStackByArgs("get_lock")
}
err = b.ctx.GetAdvisoryLock(lockName, timeout)
if err != nil {
switch errors.Cause(err).(*terror.Error).Code() {
case mysql.ErrLockWaitTimeout:
return 0, false, nil // Another user has the lock
case mysql.ErrLockDeadlock:
// Currently this code is not reachable because each Advisory Lock
// Uses a separate session. Deadlock detection does not work across
// independent sessions.
return 0, false, errUserLockDeadlock
default:
return 0, false, err
}
}
return 1, false, nil
}
type releaseLockFunctionClass struct {
baseFunctionClass
}
func (c *releaseLockFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
sig := &builtinReleaseLockSig{bf}
bf.tp.SetFlen(1)
return sig, nil
}
type builtinReleaseLockSig struct {
baseBuiltinFunc
}
func (b *builtinReleaseLockSig) Clone() builtinFunc {
newSig := &builtinReleaseLockSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinReleaseLockSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_release-lock
func (b *builtinReleaseLockSig) evalInt(row chunk.Row) (int64, bool, error) {
lockName, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil {
return 0, isNull, err
}
// Validate that lockName is NOT NULL or empty string
if isNull {
return 0, false, errUserLockWrongName.GenWithStackByArgs("NULL")
}
if lockName == "" || utf8.RuneCountInString(lockName) > 64 {
return 0, false, errUserLockWrongName.GenWithStackByArgs(lockName)
}
// Lock names are case insensitive. Because we can't rely on collations
// being enabled on the internal table, we have to lower it.
lockName = strings.ToLower(lockName)
if utf8.RuneCountInString(lockName) > 64 {
return 0, false, errIncorrectArgs.GenWithStackByArgs("release_lock")
}
released := int64(0)
if b.ctx.ReleaseAdvisoryLock(lockName) {
released = 1
}
return released, false, nil
}
type anyValueFunctionClass struct {
baseFunctionClass
}
func (c *anyValueFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
argTp := args[0].GetType().EvalType()
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, argTp, argTp)
if err != nil {
return nil, err
}
ft := args[0].GetType().Clone()
ft.AddFlag(bf.tp.GetFlag())
*bf.tp = *ft
var sig builtinFunc
switch argTp {
case types.ETDecimal:
sig = &builtinDecimalAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_DecimalAnyValue)
case types.ETDuration:
sig = &builtinDurationAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_DurationAnyValue)
case types.ETInt:
bf.tp.SetDecimal(0)
sig = &builtinIntAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_IntAnyValue)
case types.ETJson:
sig = &builtinJSONAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_JSONAnyValue)
case types.ETReal:
sig = &builtinRealAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_RealAnyValue)
case types.ETString:
bf.tp.SetDecimal(types.UnspecifiedLength)
sig = &builtinStringAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_StringAnyValue)
case types.ETDatetime, types.ETTimestamp:
bf.tp.SetCharset(mysql.DefaultCharset)
bf.tp.SetCollate(mysql.DefaultCollationName)
bf.tp.SetFlag(0)
sig = &builtinTimeAnyValueSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_TimeAnyValue)
default:
return nil, errIncorrectArgs.GenWithStackByArgs("ANY_VALUE")
}
return sig, nil
}
type builtinDecimalAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinDecimalAnyValueSig) Clone() builtinFunc {
newSig := &builtinDecimalAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalDecimal evals a builtinDecimalAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinDecimalAnyValueSig) evalDecimal(row chunk.Row) (*types.MyDecimal, bool, error) {
return b.args[0].EvalDecimal(b.ctx, row)
}
type builtinDurationAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinDurationAnyValueSig) Clone() builtinFunc {
newSig := &builtinDurationAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalDuration evals a builtinDurationAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinDurationAnyValueSig) evalDuration(row chunk.Row) (types.Duration, bool, error) {
return b.args[0].EvalDuration(b.ctx, row)
}
type builtinIntAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinIntAnyValueSig) Clone() builtinFunc {
newSig := &builtinIntAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinIntAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinIntAnyValueSig) evalInt(row chunk.Row) (int64, bool, error) {
return b.args[0].EvalInt(b.ctx, row)
}
type builtinJSONAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinJSONAnyValueSig) Clone() builtinFunc {
newSig := &builtinJSONAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalJSON evals a builtinJSONAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinJSONAnyValueSig) evalJSON(row chunk.Row) (types.BinaryJSON, bool, error) {
return b.args[0].EvalJSON(b.ctx, row)
}
type builtinRealAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinRealAnyValueSig) Clone() builtinFunc {
newSig := &builtinRealAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalReal evals a builtinRealAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinRealAnyValueSig) evalReal(row chunk.Row) (float64, bool, error) {
return b.args[0].EvalReal(b.ctx, row)
}
type builtinStringAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinStringAnyValueSig) Clone() builtinFunc {
newSig := &builtinStringAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals a builtinStringAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinStringAnyValueSig) evalString(row chunk.Row) (string, bool, error) {
return b.args[0].EvalString(b.ctx, row)
}
type builtinTimeAnyValueSig struct {
baseBuiltinFunc
}
func (b *builtinTimeAnyValueSig) Clone() builtinFunc {
newSig := &builtinTimeAnyValueSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalTime evals a builtinTimeAnyValueSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_any-value
func (b *builtinTimeAnyValueSig) evalTime(row chunk.Row) (types.Time, bool, error) {
return b.args[0].EvalTime(b.ctx, row)
}
type defaultFunctionClass struct {
baseFunctionClass
}
func (c *defaultFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
return nil, errFunctionNotExists.GenWithStackByArgs("FUNCTION", "DEFAULT")
}
type inetAtonFunctionClass struct {
baseFunctionClass
}
func (c *inetAtonFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(21)
bf.tp.AddFlag(mysql.UnsignedFlag)
sig := &builtinInetAtonSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_InetAton)
return sig, nil
}
type builtinInetAtonSig struct {
baseBuiltinFunc
}
func (b *builtinInetAtonSig) Clone() builtinFunc {
newSig := &builtinInetAtonSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinInetAtonSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_inet-aton
func (b *builtinInetAtonSig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return 0, true, err
}
// ip address should not end with '.'.
if len(val) == 0 || val[len(val)-1] == '.' {
return 0, false, errWrongValueForType.GenWithStackByArgs("string", val, "inet_aton")
}
var (
byteResult, result uint64
dotCount int
)
for _, c := range val {
if c >= '0' && c <= '9' {
digit := uint64(c - '0')
byteResult = byteResult*10 + digit
if byteResult > 255 {
return 0, false, errWrongValueForType.GenWithStackByArgs("string", val, "inet_aton")
}
} else if c == '.' {
dotCount++
if dotCount > 3 {
return 0, false, errWrongValueForType.GenWithStackByArgs("string", val, "inet_aton")
}
result = (result << 8) + byteResult
byteResult = 0
} else {
return 0, false, errWrongValueForType.GenWithStackByArgs("string", val, "inet_aton")
}
}
// 127 -> 0.0.0.127
// 127.255 -> 127.0.0.255
// 127.256 -> NULL
// 127.2.1 -> 127.2.0.1
switch dotCount {
case 1:
result <<= 8
fallthrough
case 2:
result <<= 8
}
return int64((result << 8) + byteResult), false, nil
}
type inetNtoaFunctionClass struct {
baseFunctionClass
}
func (c *inetNtoaFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETString, types.ETInt)
if err != nil {
return nil, err
}
charset, collate := ctx.GetSessionVars().GetCharsetInfo()
bf.tp.SetCharset(charset)
bf.tp.SetCollate(collate)
bf.tp.SetFlen(93)
bf.tp.SetDecimal(0)
sig := &builtinInetNtoaSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_InetNtoa)
return sig, nil
}
type builtinInetNtoaSig struct {
baseBuiltinFunc
}
func (b *builtinInetNtoaSig) Clone() builtinFunc {
newSig := &builtinInetNtoaSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals a builtinInetNtoaSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_inet-ntoa
func (b *builtinInetNtoaSig) evalString(row chunk.Row) (string, bool, error) {
val, isNull, err := b.args[0].EvalInt(b.ctx, row)
if err != nil || isNull {
return "", true, err
}
if val < 0 || uint64(val) > math.MaxUint32 {
// not an IPv4 address.
return "", true, nil
}
ip := make(net.IP, net.IPv4len)
binary.BigEndian.PutUint32(ip, uint32(val))
ipv4 := ip.To4()
if ipv4 == nil {
// Not a vaild ipv4 address.
return "", true, nil
}
return ipv4.String(), false, nil
}
type inet6AtonFunctionClass struct {
baseFunctionClass
}
func (c *inet6AtonFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETString, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(16)
types.SetBinChsClnFlag(bf.tp)
bf.tp.SetDecimal(0)
sig := &builtinInet6AtonSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_Inet6Aton)
return sig, nil
}
type builtinInet6AtonSig struct {
baseBuiltinFunc
}
func (b *builtinInet6AtonSig) Clone() builtinFunc {
newSig := &builtinInet6AtonSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals a builtinInet6AtonSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_inet6-aton
func (b *builtinInet6AtonSig) evalString(row chunk.Row) (string, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return "", true, err
}
if len(val) == 0 {
return "", false, errWrongValueForType.GenWithStackByArgs("string", val, "inet_aton6")
}
ip := net.ParseIP(val)
if ip == nil {
return "", false, errWrongValueForType.GenWithStackByArgs("string", val, "inet_aton6")
}
var isMappedIpv6 bool
if ip.To4() != nil && strings.Contains(val, ":") {
// mapped ipv6 address.
isMappedIpv6 = true
}
var result []byte
if isMappedIpv6 || ip.To4() == nil {
result = make([]byte, net.IPv6len)
} else {
result = make([]byte, net.IPv4len)
}
if isMappedIpv6 {
copy(result[12:], ip.To4())
result[11] = 0xff
result[10] = 0xff
} else if ip.To4() == nil {
copy(result, ip.To16())
} else {
copy(result, ip.To4())
}
return string(result), false, nil
}
type inet6NtoaFunctionClass struct {
baseFunctionClass
}
func (c *inet6NtoaFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETString, types.ETString)
if err != nil {
return nil, err
}
charset, collate := ctx.GetSessionVars().GetCharsetInfo()
bf.tp.SetCharset(charset)
bf.tp.SetCollate(collate)
bf.tp.SetFlen(117)
bf.tp.SetDecimal(0)
sig := &builtinInet6NtoaSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_Inet6Ntoa)
return sig, nil
}
type builtinInet6NtoaSig struct {
baseBuiltinFunc
}
func (b *builtinInet6NtoaSig) Clone() builtinFunc {
newSig := &builtinInet6NtoaSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals a builtinInet6NtoaSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_inet6-ntoa
func (b *builtinInet6NtoaSig) evalString(row chunk.Row) (string, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return "", true, err
}
ip := net.IP(val).String()
if len(val) == net.IPv6len && !strings.Contains(ip, ":") {
ip = fmt.Sprintf("::ffff:%s", ip)
}
if net.ParseIP(ip) == nil {
return "", true, nil
}
return ip, false, nil
}
type isFreeLockFunctionClass struct {
baseFunctionClass
}
func (c *isFreeLockFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
return nil, errFunctionNotExists.GenWithStackByArgs("FUNCTION", "IS_FREE_LOCK")
}
type isIPv4FunctionClass struct {
baseFunctionClass
}
func (c *isIPv4FunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(1)
sig := &builtinIsIPv4Sig{bf}
sig.setPbCode(tipb.ScalarFuncSig_IsIPv4)
return sig, nil
}
type builtinIsIPv4Sig struct {
baseBuiltinFunc
}
func (b *builtinIsIPv4Sig) Clone() builtinFunc {
newSig := &builtinIsIPv4Sig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinIsIPv4Sig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_is-ipv4
func (b *builtinIsIPv4Sig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return 0, err != nil, err
}
if isIPv4(val) {
return 1, false, nil
}
return 0, false, nil
}
// isIPv4 checks IPv4 address which satisfying the format A.B.C.D(0<=A/B/C/D<=255).
// Mapped IPv6 address like '::ffff:1.2.3.4' would return false.
func isIPv4(ip string) bool {
// acc: keep the decimal value of each segment under check, which should between 0 and 255 for valid IPv4 address.
// pd: sentinel for '.'
dots, acc, pd := 0, 0, true
for _, c := range ip {
switch {
case '0' <= c && c <= '9':
acc = acc*10 + int(c-'0')
pd = false
case c == '.':
dots++
if dots > 3 || acc > 255 || pd {
return false
}
acc, pd = 0, true
default:
return false
}
}
if dots != 3 || acc > 255 || pd {
return false
}
return true
}
type isIPv4CompatFunctionClass struct {
baseFunctionClass
}
func (c *isIPv4CompatFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(1)
sig := &builtinIsIPv4CompatSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_IsIPv4Compat)
return sig, nil
}
type builtinIsIPv4CompatSig struct {
baseBuiltinFunc
}
func (b *builtinIsIPv4CompatSig) Clone() builtinFunc {
newSig := &builtinIsIPv4CompatSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals Is_IPv4_Compat
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_is-ipv4-compat
func (b *builtinIsIPv4CompatSig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return 0, err != nil, err
}
ipAddress := []byte(val)
if len(ipAddress) != net.IPv6len {
// Not an IPv6 address, return false
return 0, false, nil
}
prefixCompat := []byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
if !bytes.HasPrefix(ipAddress, prefixCompat) {
return 0, false, nil
}
return 1, false, nil
}
type isIPv4MappedFunctionClass struct {
baseFunctionClass
}
func (c *isIPv4MappedFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(1)
sig := &builtinIsIPv4MappedSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_IsIPv4Mapped)
return sig, nil
}
type builtinIsIPv4MappedSig struct {
baseBuiltinFunc
}
func (b *builtinIsIPv4MappedSig) Clone() builtinFunc {
newSig := &builtinIsIPv4MappedSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals Is_IPv4_Mapped
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_is-ipv4-mapped
func (b *builtinIsIPv4MappedSig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return 0, err != nil, err
}
ipAddress := []byte(val)
if len(ipAddress) != net.IPv6len {
// Not an IPv6 address, return false
return 0, false, nil
}
prefixMapped := []byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff}
if !bytes.HasPrefix(ipAddress, prefixMapped) {
return 0, false, nil
}
return 1, false, nil
}
type isIPv6FunctionClass struct {
baseFunctionClass
}
func (c *isIPv6FunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(1)
sig := &builtinIsIPv6Sig{bf}
sig.setPbCode(tipb.ScalarFuncSig_IsIPv6)
return sig, nil
}
type builtinIsIPv6Sig struct {
baseBuiltinFunc
}
func (b *builtinIsIPv6Sig) Clone() builtinFunc {
newSig := &builtinIsIPv6Sig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinIsIPv6Sig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_is-ipv6
func (b *builtinIsIPv6Sig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return 0, err != nil, err
}
ip := net.ParseIP(val)
if ip != nil && !isIPv4(val) {
return 1, false, nil
}
return 0, false, nil
}
type isUsedLockFunctionClass struct {
baseFunctionClass
}
func (c *isUsedLockFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
return nil, errFunctionNotExists.GenWithStackByArgs("FUNCTION", "IS_USED_LOCK")
}
type isUUIDFunctionClass struct {
baseFunctionClass
}
func (c *isUUIDFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETString)
if err != nil {
return nil, err
}
bf.tp.SetFlen(1)
sig := &builtinIsUUIDSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_IsUUID)
return sig, nil
}
type builtinIsUUIDSig struct {
baseBuiltinFunc
}
func (b *builtinIsUUIDSig) Clone() builtinFunc {
newSig := &builtinIsUUIDSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinIsUUIDSig.
// See https://dev.mysql.com/doc/refman/8.0/en/miscellaneous-functions.html#function_is-uuid
func (b *builtinIsUUIDSig) evalInt(row chunk.Row) (int64, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if err != nil || isNull {
return 0, isNull, err
}
if _, err = uuid.Parse(val); err != nil {
return 0, false, nil
}
return 1, false, nil
}
type masterPosWaitFunctionClass struct {
baseFunctionClass
}
func (c *masterPosWaitFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
return nil, errFunctionNotExists.GenWithStackByArgs("FUNCTION", "MASTER_POS_WAIT")
}
type nameConstFunctionClass struct {
baseFunctionClass
}
func (c *nameConstFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
argTp := args[1].GetType().EvalType()
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, argTp, types.ETString, argTp)
if err != nil {
return nil, err
}
*bf.tp = *args[1].GetType()
var sig builtinFunc
switch argTp {
case types.ETDecimal:
sig = &builtinNameConstDecimalSig{bf}
case types.ETDuration:
sig = &builtinNameConstDurationSig{bf}
case types.ETInt:
bf.tp.SetDecimal(0)
sig = &builtinNameConstIntSig{bf}
case types.ETJson:
sig = &builtinNameConstJSONSig{bf}
case types.ETReal:
sig = &builtinNameConstRealSig{bf}
case types.ETString:
bf.tp.SetDecimal(types.UnspecifiedLength)
sig = &builtinNameConstStringSig{bf}
case types.ETDatetime, types.ETTimestamp:
bf.tp.SetCharset(mysql.DefaultCharset)
bf.tp.SetCollate(mysql.DefaultCollationName)
bf.tp.SetFlag(0)
sig = &builtinNameConstTimeSig{bf}
default:
return nil, errIncorrectArgs.GenWithStackByArgs("NAME_CONST")
}
return sig, nil
}
type builtinNameConstDecimalSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstDecimalSig) Clone() builtinFunc {
newSig := &builtinNameConstDecimalSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstDecimalSig) evalDecimal(row chunk.Row) (*types.MyDecimal, bool, error) {
return b.args[1].EvalDecimal(b.ctx, row)
}
type builtinNameConstIntSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstIntSig) Clone() builtinFunc {
newSig := &builtinNameConstIntSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstIntSig) evalInt(row chunk.Row) (int64, bool, error) {
return b.args[1].EvalInt(b.ctx, row)
}
type builtinNameConstRealSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstRealSig) Clone() builtinFunc {
newSig := &builtinNameConstRealSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstRealSig) evalReal(row chunk.Row) (float64, bool, error) {
return b.args[1].EvalReal(b.ctx, row)
}
type builtinNameConstStringSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstStringSig) Clone() builtinFunc {
newSig := &builtinNameConstStringSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstStringSig) evalString(row chunk.Row) (string, bool, error) {
return b.args[1].EvalString(b.ctx, row)
}
type builtinNameConstJSONSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstJSONSig) Clone() builtinFunc {
newSig := &builtinNameConstJSONSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstJSONSig) evalJSON(row chunk.Row) (types.BinaryJSON, bool, error) {
return b.args[1].EvalJSON(b.ctx, row)
}
type builtinNameConstDurationSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstDurationSig) Clone() builtinFunc {
newSig := &builtinNameConstDurationSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstDurationSig) evalDuration(row chunk.Row) (types.Duration, bool, error) {
return b.args[1].EvalDuration(b.ctx, row)
}
type builtinNameConstTimeSig struct {
baseBuiltinFunc
}
func (b *builtinNameConstTimeSig) Clone() builtinFunc {
newSig := &builtinNameConstTimeSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
func (b *builtinNameConstTimeSig) evalTime(row chunk.Row) (types.Time, bool, error) {
return b.args[1].EvalTime(b.ctx, row)
}
type releaseAllLocksFunctionClass struct {
baseFunctionClass
}
func (c *releaseAllLocksFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt)
if err != nil {
return nil, err
}
sig := &builtinReleaseAllLocksSig{bf}
bf.tp.SetFlen(1)
return sig, nil
}
type builtinReleaseAllLocksSig struct {
baseBuiltinFunc
}
func (b *builtinReleaseAllLocksSig) Clone() builtinFunc {
newSig := &builtinReleaseAllLocksSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals a builtinReleaseAllLocksSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_release-all-locks
func (b *builtinReleaseAllLocksSig) evalInt(_ chunk.Row) (int64, bool, error) {
count := b.ctx.ReleaseAllAdvisoryLocks()
return int64(count), false, nil
}
type uuidFunctionClass struct {
baseFunctionClass
}
func (c *uuidFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETString)
if err != nil {
return nil, err
}
charset, collate := ctx.GetSessionVars().GetCharsetInfo()
bf.tp.SetCharset(charset)
bf.tp.SetCollate(collate)
bf.tp.SetFlen(36)
sig := &builtinUUIDSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_UUID)
return sig, nil
}
type builtinUUIDSig struct {
baseBuiltinFunc
}
func (b *builtinUUIDSig) Clone() builtinFunc {
newSig := &builtinUUIDSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals a builtinUUIDSig.
// See https://dev.mysql.com/doc/refman/5.7/en/miscellaneous-functions.html#function_uuid
func (b *builtinUUIDSig) evalString(_ chunk.Row) (d string, isNull bool, err error) {
var id uuid.UUID
id, err = uuid.NewUUID()
if err != nil {
return
}
d = id.String()
return
}
type uuidShortFunctionClass struct {
baseFunctionClass
}
func (c *uuidShortFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
return nil, errFunctionNotExists.GenWithStackByArgs("FUNCTION", "UUID_SHORT")
}
type vitessHashFunctionClass struct {
baseFunctionClass
}
func (c *vitessHashFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETInt)
if err != nil {
return nil, err
}
bf.tp.SetFlen(20) //64 bit unsigned
bf.tp.AddFlag(mysql.UnsignedFlag)
types.SetBinChsClnFlag(bf.tp)
sig := &builtinVitessHashSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_VitessHash)
return sig, nil
}
type builtinVitessHashSig struct {
baseBuiltinFunc
}
func (b *builtinVitessHashSig) Clone() builtinFunc {
newSig := &builtinVitessHashSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals VITESS_HASH(int64).
func (b *builtinVitessHashSig) evalInt(row chunk.Row) (int64, bool, error) {
shardKeyInt, isNull, err := b.args[0].EvalInt(b.ctx, row)
if isNull || err != nil {
return 0, true, err
}
var hashed uint64
if hashed, err = vitess.HashUint64(uint64(shardKeyInt)); err != nil {
return 0, true, err
}
return int64(hashed), false, nil
}
type uuidToBinFunctionClass struct {
baseFunctionClass
}
func (c *uuidToBinFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
argTps := []types.EvalType{types.ETString}
if len(args) == 2 {
argTps = append(argTps, types.ETInt)
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETString, argTps...)
if err != nil {
return nil, err
}
bf.tp.SetFlen(16)
types.SetBinChsClnFlag(bf.tp)
bf.tp.SetDecimal(0)
sig := &builtinUUIDToBinSig{bf}
return sig, nil
}
type builtinUUIDToBinSig struct {
baseBuiltinFunc
}
func (b *builtinUUIDToBinSig) Clone() builtinFunc {
newSig := &builtinUUIDToBinSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals UUID_TO_BIN(string_uuid, swap_flag).
// See https://dev.mysql.com/doc/refman/8.0/en/miscellaneous-functions.html#function_uuid-to-bin
func (b *builtinUUIDToBinSig) evalString(row chunk.Row) (string, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if isNull || err != nil {
return "", isNull, err
}
u, err := uuid.Parse(val)
if err != nil {
return "", false, errWrongValueForType.GenWithStackByArgs("string", val, "uuid_to_bin")
}
bin, err := u.MarshalBinary()
if err != nil {
return "", false, errWrongValueForType.GenWithStackByArgs("string", val, "uuid_to_bin")
}
flag := int64(0)
if len(b.args) == 2 {
flag, isNull, err = b.args[1].EvalInt(b.ctx, row)
if isNull {
flag = 0
}
if err != nil {
return "", false, err
}
}
if flag != 0 {
return swapBinaryUUID(bin), false, nil
}
return string(bin), false, nil
}
type binToUUIDFunctionClass struct {
baseFunctionClass
}
func (c *binToUUIDFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
argTps := []types.EvalType{types.ETString}
if len(args) == 2 {
argTps = append(argTps, types.ETInt)
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETString, argTps...)
if err != nil {
return nil, err
}
charset, collate := ctx.GetSessionVars().GetCharsetInfo()
bf.tp.SetCharset(charset)
bf.tp.SetCollate(collate)
bf.tp.SetFlen(32)
bf.tp.SetDecimal(0)
sig := &builtinBinToUUIDSig{bf}
return sig, nil
}
type builtinBinToUUIDSig struct {
baseBuiltinFunc
}
func (b *builtinBinToUUIDSig) Clone() builtinFunc {
newSig := &builtinBinToUUIDSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalString evals BIN_TO_UUID(binary_uuid, swap_flag).
// See https://dev.mysql.com/doc/refman/8.0/en/miscellaneous-functions.html#function_bin-to-uuid
func (b *builtinBinToUUIDSig) evalString(row chunk.Row) (string, bool, error) {
val, isNull, err := b.args[0].EvalString(b.ctx, row)
if isNull || err != nil {
return "", isNull, err
}
var u uuid.UUID
err = u.UnmarshalBinary([]byte(val))
if err != nil {
return "", false, errWrongValueForType.GenWithStackByArgs("string", val, "bin_to_uuid")
}
str := u.String()
flag := int64(0)
if len(b.args) == 2 {
flag, isNull, err = b.args[1].EvalInt(b.ctx, row)
if isNull {
flag = 0
}
if err != nil {
return "", false, err
}
}
if flag != 0 {
return swapStringUUID(str), false, nil
}
return str, false, nil
}
func swapBinaryUUID(bin []byte) string {
buf := make([]byte, len(bin))
copy(buf[0:2], bin[6:8])
copy(buf[2:4], bin[4:6])
copy(buf[4:8], bin[0:4])
copy(buf[8:], bin[8:])
return string(buf)
}
func swapStringUUID(str string) string {
buf := make([]byte, len(str))
copy(buf[0:4], str[9:13])
copy(buf[4:8], str[14:18])
copy(buf[8:9], str[8:9])
copy(buf[9:13], str[4:8])
copy(buf[13:14], str[13:14])
copy(buf[14:18], str[0:4])
copy(buf[18:], str[18:])
return string(buf)
}
type tidbShardFunctionClass struct {
baseFunctionClass
}
func (c *tidbShardFunctionClass) getFunction(ctx sessionctx.Context, args []Expression) (builtinFunc, error) {
if err := c.verifyArgs(args); err != nil {
return nil, err
}
bf, err := newBaseBuiltinFuncWithTp(ctx, c.funcName, args, types.ETInt, types.ETInt)
if err != nil {
return nil, err
}
bf.tp.SetFlen(4) //64 bit unsigned
bf.tp.AddFlag(mysql.UnsignedFlag)
types.SetBinChsClnFlag(bf.tp)
sig := &builtinTidbShardSig{bf}
sig.setPbCode(tipb.ScalarFuncSig_TiDBShard)
return sig, nil
}
type builtinTidbShardSig struct {
baseBuiltinFunc
}
func (b *builtinTidbShardSig) Clone() builtinFunc {
newSig := &builtinTidbShardSig{}
newSig.cloneFrom(&b.baseBuiltinFunc)
return newSig
}
// evalInt evals tidb_shard(int64).
func (b *builtinTidbShardSig) evalInt(row chunk.Row) (int64, bool, error) {
shardKeyInt, isNull, err := b.args[0].EvalInt(b.ctx, row)
if isNull || err != nil {
return 0, true, err
}
var hashed uint64
if hashed, err = vitess.HashUint64(uint64(shardKeyInt)); err != nil {
return 0, true, err
}
hashed = hashed % tidbShardBucketCount
return int64(hashed), false, nil
}
| {'content_hash': 'b1e5fcec862ff0edc14695e6e32c770d', 'timestamp': '', 'source': 'github', 'line_count': 1454, 'max_line_length': 116, 'avg_line_length': 27.440165061898213, 'alnum_prop': 0.7244222768058549, 'repo_name': 'pingcap/tidb', 'id': 'c55d7e571dd12edddc20af08d063d02c6a6b5d34', 'size': '40489', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'expression/builtin_miscellaneous.go', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Dockerfile', 'bytes': '1854'}, {'name': 'Go', 'bytes': '34056451'}, {'name': 'HTML', 'bytes': '420'}, {'name': 'Java', 'bytes': '3694'}, {'name': 'JavaScript', 'bytes': '900'}, {'name': 'Jsonnet', 'bytes': '15129'}, {'name': 'Makefile', 'bytes': '22240'}, {'name': 'Ragel', 'bytes': '3678'}, {'name': 'Shell', 'bytes': '439400'}, {'name': 'Starlark', 'bytes': '574240'}, {'name': 'TypeScript', 'bytes': '61875'}, {'name': 'Yacc', 'bytes': '353301'}]} |
define("dojox/widget/nls/bg/Wizard",({next:"Следващ",previous:"Предишен",done:"Готово"}));
| {'content_hash': '8f6b9467c7c414710be9c0dfe4d9e147', 'timestamp': '', 'source': 'github', 'line_count': 1, 'max_line_length': 90, 'avg_line_length': 91.0, 'alnum_prop': 0.7142857142857143, 'repo_name': 'brucevsked/vskeddemolist', 'id': 'd358f5784b17e86fb081d76d303c60fb0308e4c9', 'size': '122', 'binary': False, 'copies': '50', 'ref': 'refs/heads/master', 'path': 'vskeddemos/projects/jslibdemo/WebRoot/js/dojo193/dojox/widget/nls/bg/Wizard.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'ASP.NET', 'bytes': '363'}, {'name': 'ActionScript', 'bytes': '68405'}, {'name': 'Batchfile', 'bytes': '3451'}, {'name': 'C', 'bytes': '11454'}, {'name': 'C#', 'bytes': '15268'}, {'name': 'C++', 'bytes': '5041'}, {'name': 'FreeMarker', 'bytes': '35223'}, {'name': 'HTML', 'bytes': '3105'}, {'name': 'Java', 'bytes': '124955404'}, {'name': 'Less', 'bytes': '1677501'}, {'name': 'Makefile', 'bytes': '1921'}, {'name': 'PHP', 'bytes': '1418075'}, {'name': 'PLSQL', 'bytes': '3451'}, {'name': 'PLpgSQL', 'bytes': '3537'}, {'name': 'Python', 'bytes': '474'}, {'name': 'SCSS', 'bytes': '317421'}, {'name': 'Shell', 'bytes': '44618'}, {'name': 'Smarty', 'bytes': '2150'}, {'name': 'TSQL', 'bytes': '124'}, {'name': 'Vue', 'bytes': '13857'}, {'name': 'XSLT', 'bytes': '61225'}]} |
import copy
import fnmatch
import io
import itertools
import logging
import pkg_resources
import jenkins_jobs.local_yaml as local_yaml
from jenkins_jobs.constants import MAGIC_MANAGE_STRING
from jenkins_jobs.errors import JenkinsJobsException
from jenkins_jobs.registry import ModuleRegistry
from jenkins_jobs.formatter import deep_format
from jenkins_jobs.xml_config import XmlJob
logger = logging.getLogger(__name__)
def matches(what, glob_patterns):
"""
Checks if the given string, ``what``, matches any of the glob patterns in
the iterable, ``glob_patterns``
:arg str what: String that we want to test if it matches a pattern
:arg iterable glob_patterns: glob patterns to match (list, tuple, set,
etc.)
"""
return any(fnmatch.fnmatch(what, glob_pattern)
for glob_pattern in glob_patterns)
class YamlParser(object):
def __init__(self, config=None, plugins_info=None):
self.data = {}
self.jobs = []
self.xml_jobs = []
self.config = config
self.registry = ModuleRegistry(self.config, plugins_info)
self.path = ["."]
if self.config:
if config.has_section('job_builder') and \
config.has_option('job_builder', 'include_path'):
self.path = config.get('job_builder',
'include_path').split(':')
self.keep_desc = self.get_keep_desc()
self.merge_defaults = self.get_merge_defaults()
def get_keep_desc(self):
keep_desc = False
if self.config and self.config.has_section('job_builder') and \
self.config.has_option('job_builder', 'keep_descriptions'):
keep_desc = self.config.getboolean('job_builder',
'keep_descriptions')
return keep_desc
def get_merge_defaults(self):
merge_defaults = False
if self.config and self.config.has_section('job_builder') and \
self.config.has_option('job_builder', 'merge_defaults'):
merge_defaults = self.config.getboolean('job_builder',
'merge_defaults')
return merge_defaults
def parse_fp(self, fp):
data = local_yaml.load(fp, search_path=self.path)
if data:
if not isinstance(data, list):
raise JenkinsJobsException(
"The topmost collection in file '{fname}' must be a list,"
" not a {cls}".format(fname=getattr(fp, 'name', fp),
cls=type(data)))
for item in data:
cls, dfn = next(iter(item.items()))
group = self.data.get(cls, {})
if len(item.items()) > 1:
n = None
for k, v in item.items():
if k == "name":
n = v
break
# Syntax error
raise JenkinsJobsException("Syntax error, for item "
"named '{0}'. Missing indent?"
.format(n))
name = dfn['name']
if name in group:
self._handle_dups("Duplicate entry found in '{0}: '{1}' "
"already defined".format(fp.name, name))
group[name] = dfn
self.data[cls] = group
def parse(self, fn):
with io.open(fn, 'r', encoding='utf-8') as fp:
self.parse_fp(fp)
def _handle_dups(self, message):
if not (self.config and self.config.has_section('job_builder') and
self.config.getboolean('job_builder', 'allow_duplicates')):
logger.error(message)
raise JenkinsJobsException(message)
else:
logger.warn(message)
def getJob(self, name):
job = self.data.get('job', {}).get(name, None)
if not job:
return job
return self.applyDefaults(job)
def getJobGroup(self, name):
return self.data.get('job-group', {}).get(name, None)
def getJobTemplate(self, name):
job = self.data.get('job-template', {}).get(name, None)
if not job:
return job
return self.applyDefaults(job)
def applyDefaults(self, data, override_dict=None):
if override_dict is None:
override_dict = {}
whichdefaults = data.get('defaults', 'global')
defaults = copy.deepcopy(self.data.get('defaults',
{}).get(whichdefaults, {}))
if defaults == {} and whichdefaults != 'global':
raise JenkinsJobsException("Unknown defaults set: '{0}'"
.format(whichdefaults))
for key in override_dict.keys():
defaults[key] = override_dict[key]
newdata = {}
newdata.update(defaults)
if self.merge_defaults:
if newdata == {}:
newdata.update(data)
else:
self.deepUpdate(newdata, data)
else:
newdata.update(data)
return newdata
def deepUpdate(self, data, updated_data):
if hasattr(data, 'format') or (hasattr(updated_data, 'format') or
hasattr(data, '__int__') or
hasattr(updated_data, '__int__')):
return
common_keys = self._findCommonKey(data, updated_data)
for common_key in common_keys:
self._deepUpdate(common_key, data, updated_data)
diff_keys = self._findDiffKey(data, updated_data)
for diff_key in diff_keys:
data[diff_key] = updated_data[diff_key]
def _deepUpdate(self, common_key, data, updated_data):
attr = data[common_key]
updated_attr = updated_data[common_key]
if hasattr(attr, 'format') or (hasattr(updated_attr, 'format') or
hasattr(attr, '__int__') or
hasattr(updated_attr, '__int__')):
data[common_key] = updated_attr
elif hasattr(attr, 'keys'):
self.deepUpdate(attr, updated_attr)
elif hasattr(attr, '__iter__'):
for ele in updated_attr:
if hasattr(ele, 'format') and ele not in attr:
attr.append(ele)
continue
if hasattr(ele, 'keys'):
for od in attr:
if hasattr(od, 'keys') and \
self._findCommonKey(od, ele):
self.deepUpdate(od, ele)
break
else:
attr.append(ele)
def _findCommonKey(self, data, updated_data):
return list(set(data.keys()).intersection(set(updated_data.keys())))
def _findDiffKey(self, data, updated_data):
return list(set(updated_data.keys()).difference(set(data.keys())))
def formatDescription(self, job):
if self.keep_desc:
description = job.get("description", None)
else:
description = job.get("description", '')
if description is not None:
job["description"] = description + \
self.get_managed_string().lstrip()
def expandYaml(self, jobs_glob=None):
changed = True
while changed:
changed = False
for module in self.registry.modules:
if hasattr(module, 'handle_data'):
if module.handle_data(self):
changed = True
for job in self.data.get('job', {}).values():
if jobs_glob and not matches(job['name'], jobs_glob):
logger.debug("Ignoring job {0}".format(job['name']))
continue
logger.debug("Expanding job '{0}'".format(job['name']))
job = self.applyDefaults(job)
self.formatDescription(job)
self.jobs.append(job)
for project in self.data.get('project', {}).values():
logger.debug("Expanding project '{0}'".format(project['name']))
# use a set to check for duplicate job references in projects
seen = set()
for jobspec in project.get('jobs', []):
if isinstance(jobspec, dict):
# Singleton dict containing dict of job-specific params
jobname, jobparams = next(iter(jobspec.items()))
if not isinstance(jobparams, dict):
jobparams = {}
else:
jobname = jobspec
jobparams = {}
job = self.getJob(jobname)
if job:
# Just naming an existing defined job
if jobname in seen:
self._handle_dups("Duplicate job '{0}' specified "
"for project '{1}'".format(
jobname, project['name']))
seen.add(jobname)
continue
# see if it's a job group
group = self.getJobGroup(jobname)
if group:
for group_jobspec in group['jobs']:
if isinstance(group_jobspec, dict):
group_jobname, group_jobparams = \
next(iter(group_jobspec.items()))
if not isinstance(group_jobparams, dict):
group_jobparams = {}
else:
group_jobname = group_jobspec
group_jobparams = {}
job = self.getJob(group_jobname)
if job:
if group_jobname in seen:
self._handle_dups(
"Duplicate job '{0}' specified for "
"project '{1}'".format(group_jobname,
project['name']))
seen.add(group_jobname)
continue
template = self.getJobTemplate(group_jobname)
# Allow a group to override parameters set by a project
d = {}
d.update(project)
d.update(jobparams)
d.update(group)
d.update(group_jobparams)
# Except name, since the group's name is not useful
d['name'] = project['name']
if template:
self.expandYamlForTemplateJob(d, template,
jobs_glob)
continue
# see if it's a template
template = self.getJobTemplate(jobname)
if template:
d = {}
d.update(project)
d.update(jobparams)
self.expandYamlForTemplateJob(d, template, jobs_glob)
else:
raise JenkinsJobsException("Failed to find suitable "
"template named '{0}'"
.format(jobname))
# check for duplicate generated jobs
seen = set()
# walk the list in reverse so that last definition wins
for job in self.jobs[::-1]:
if job['name'] in seen:
self._handle_dups("Duplicate definitions for job '{0}' "
"specified".format(job['name']))
self.jobs.remove(job)
seen.add(job['name'])
def expandYamlForTemplateJob(self, project, template, jobs_glob=None):
dimensions = []
template_name = template['name']
# reject keys that are not useful during yaml expansion
for k in ['jobs']:
project.pop(k)
for (k, v) in project.items():
tmpk = '{{{0}}}'.format(k)
if tmpk not in template_name:
logger.debug("Variable %s not in name %s, rejecting from job"
" matrix expansion.", tmpk, template_name)
continue
if type(v) == list:
dimensions.append(zip([k] * len(v), v))
# XXX somewhat hackish to ensure we actually have a single
# pass through the loop
if len(dimensions) == 0:
dimensions = [(("", ""),)]
for values in itertools.product(*dimensions):
params = copy.deepcopy(project)
params = self.applyDefaults(params, template)
expanded_values = {}
for (k, v) in values:
if isinstance(v, dict):
inner_key = next(iter(v))
expanded_values[k] = inner_key
expanded_values.update(v[inner_key])
else:
expanded_values[k] = v
params.update(expanded_values)
params = deep_format(params, params)
allow_empty_variables = self.config \
and self.config.has_section('job_builder') \
and self.config.has_option(
'job_builder', 'allow_empty_variables') \
and self.config.getboolean(
'job_builder', 'allow_empty_variables')
for key in template.keys():
if key not in params:
params[key] = template[key]
expanded = deep_format(template, params, allow_empty_variables)
job_name = expanded.get('name')
if jobs_glob and not matches(job_name, jobs_glob):
continue
self.formatDescription(expanded)
self.jobs.append(expanded)
def get_managed_string(self):
# The \n\n is not hard coded, because they get stripped if the
# project does not otherwise have a description.
return "\n\n" + MAGIC_MANAGE_STRING
def generateXML(self):
for job in self.jobs:
self.xml_jobs.append(self.getXMLForJob(job))
def getXMLForJob(self, data):
kind = data.get('project-type', 'freestyle')
for ep in pkg_resources.iter_entry_points(
group='jenkins_jobs.projects', name=kind):
Mod = ep.load()
mod = Mod(self.registry)
xml = mod.root_xml(data)
self.gen_xml(xml, data)
job = XmlJob(xml, data['name'])
return job
def gen_xml(self, xml, data):
for module in self.registry.modules:
if hasattr(module, 'gen_xml'):
module.gen_xml(self, xml, data)
| {'content_hash': '63ec19047f80d7311023a4536803da91', 'timestamp': '', 'source': 'github', 'line_count': 370, 'max_line_length': 79, 'avg_line_length': 40.8054054054054, 'alnum_prop': 0.4939064776791628, 'repo_name': 'electrical/jenkins-job-builder', 'id': 'c95237078536d1194edcf7c2ab1bb193ec03a1c0', 'size': '15742', 'binary': False, 'copies': '1', 'ref': 'refs/heads/own_branch', 'path': 'jenkins_jobs/parser.py', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Assembly', 'bytes': '51'}, {'name': 'C++', 'bytes': '791'}, {'name': 'Python', 'bytes': '748991'}, {'name': 'Shell', 'bytes': '916'}, {'name': 'SourcePawn', 'bytes': '16'}]} |
package org.apache.camel.component.twitter.consumer.streaming;
import org.apache.camel.component.twitter.TwitterEndpoint;
import twitter4j.FilterQuery;
/**
* Consumes the filter stream
*
*/
public class FilterConsumer extends StreamingConsumer {
public FilterConsumer(TwitterEndpoint te) {
super(te);
twitterStream.filter(createFilter(te));
}
private FilterQuery createFilter(TwitterEndpoint te) {
FilterQuery filterQuery = new FilterQuery();
String allLocationsString = te.getProperties().getLocations();
if (allLocationsString != null) {
String[] locationStrings = allLocationsString.split(";");
double[][] locations = new double[locationStrings.length][2];
for (int i = 0; i < locationStrings.length; i++) {
String[] coords = locationStrings[i].split(",");
locations[i][0] = Double.valueOf(coords[0]);
locations[i][1] = Double.valueOf(coords[1]);
}
filterQuery.locations(locations);
}
String keywords = te.getProperties().getKeywords();
if (keywords != null && keywords.length() > 0) {
filterQuery.track(keywords.split(","));
}
String userIds = te.getProperties().getUserIds();
if (userIds != null) {
String[] stringUserIds = userIds.split(",");
long[] longUserIds = new long[stringUserIds.length];
for (int i = 0; i < stringUserIds.length; i++) {
longUserIds[i] = Long.valueOf(stringUserIds[i]);
}
filterQuery.follow(longUserIds);
}
if (allLocationsString == null && keywords == null && userIds == null) {
throw new IllegalArgumentException("At least one filter parameter is required");
}
filterQuery.setIncludeEntities(true);
return filterQuery;
}
}
| {'content_hash': '80b93f0b8adc34c5d4ab3cdbd6d25be3', 'timestamp': '', 'source': 'github', 'line_count': 55, 'max_line_length': 92, 'avg_line_length': 35.2, 'alnum_prop': 0.6002066115702479, 'repo_name': 'aaronwalker/camel', 'id': '1028fd220136757d5d3cb37d3982ae03363013fd', 'size': '2739', 'binary': False, 'copies': '1', 'ref': 'refs/heads/trunk', 'path': 'components/camel-twitter/src/main/java/org/apache/camel/component/twitter/consumer/streaming/FilterConsumer.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'ActionScript', 'bytes': '20202'}, {'name': 'CSS', 'bytes': '221391'}, {'name': 'Groovy', 'bytes': '2682'}, {'name': 'Haskell', 'bytes': '5970'}, {'name': 'Java', 'bytes': '27972791'}, {'name': 'JavaScript', 'bytes': '3697148'}, {'name': 'PHP', 'bytes': '88860'}, {'name': 'Ruby', 'bytes': '9910'}, {'name': 'Scala', 'bytes': '220463'}, {'name': 'Shell', 'bytes': '12865'}, {'name': 'TypeScript', 'bytes': '715'}, {'name': 'XQuery', 'bytes': '1248'}, {'name': 'XSLT', 'bytes': '53623'}]} |
using System;
using FluentScheduler.Extensions;
namespace FluentScheduler.Model
{
public class YearOnDayOfYearUnit
{
internal Schedule Schedule { get; private set; }
internal int Duration { get; private set; }
internal int DayOfYear { get; private set; }
public YearOnDayOfYearUnit(Schedule schedule, int duration, int dayOfYear)
{
Schedule = schedule;
Duration = duration;
DayOfYear = dayOfYear;
Schedule.CalculateNextRun = x => {
var nextRun = x.Date.FirstOfYear().AddDays(DayOfYear - 1);
return (x > nextRun) ? x.Date.FirstOfYear().AddYears(Duration).AddDays(DayOfYear - 1) : nextRun;
};
}
/// <summary>
/// Schedules the specified task to run at the hour and minute specified. If the hour and minute have passed, the task will execute the next scheduled year.
/// </summary>
/// <param name="hours">0-23: Represents the hour of the day</param>
/// <param name="minutes">0-59: Represents the minute of the day</param>
/// <returns></returns>
public void At(int hours, int minutes)
{
Schedule.CalculateNextRun = x => {
var nextRun = x.Date.FirstOfYear().AddDays(DayOfYear - 1).AddHours(hours).AddMinutes(minutes);
return (x > nextRun) ? x.Date.FirstOfYear().AddYears(Duration).AddDays(DayOfYear - 1).AddHours(hours).AddMinutes(minutes) : nextRun;
};
}
}
}
| {'content_hash': '22b1a3ebc4f7932750dab1a032316aae', 'timestamp': '', 'source': 'github', 'line_count': 37, 'max_line_length': 159, 'avg_line_length': 36.027027027027025, 'alnum_prop': 0.6984246061515379, 'repo_name': 'ThreeScreenStudios/FluentScheduler', 'id': '167eee2630f06bed9fcbea6af808c71926ad3bc7', 'size': '1335', 'binary': False, 'copies': '5', 'ref': 'refs/heads/master', 'path': 'FluentScheduler/Model/YearOnDayOfYearUnit.cs', 'mode': '33188', 'license': 'bsd-3-clause', 'language': []} |
package net.floodlightcontroller.core.internal;
import static org.easymock.EasyMock.anyLong;
import static org.easymock.EasyMock.anyObject;
import static org.easymock.EasyMock.createMock;
import static org.easymock.EasyMock.expect;
import static org.easymock.EasyMock.expectLastCall;
import static org.easymock.EasyMock.replay;
import static org.easymock.EasyMock.reset;
import static org.easymock.EasyMock.resetToStrict;
import static org.easymock.EasyMock.verify;
import static org.hamcrest.CoreMatchers.equalTo;
import static org.hamcrest.CoreMatchers.notNullValue;
import static org.junit.Assert.assertEquals;
import static org.junit.Assert.assertFalse;
import static org.junit.Assert.assertThat;
import static org.junit.Assert.assertTrue;
import static org.junit.Assert.fail;
import java.io.IOException;
import java.util.Arrays;
import java.util.Collections;
import java.util.HashSet;
import java.util.List;
import java.util.concurrent.TimeUnit;
import org.easymock.EasyMock;
import org.hamcrest.CoreMatchers;
import org.hamcrest.Matchers;
import io.netty.util.Timeout;
import io.netty.util.Timer;
import io.netty.util.TimerTask;
import org.junit.After;
import org.junit.Before;
import org.junit.Test;
import net.floodlightcontroller.core.HARole;
import net.floodlightcontroller.core.IOFSwitch;
import net.floodlightcontroller.core.IOFSwitch.SwitchStatus;
import net.floodlightcontroller.core.IOFSwitchBackend;
import net.floodlightcontroller.core.PortChangeEvent;
import net.floodlightcontroller.core.PortChangeType;
import net.floodlightcontroller.core.internal.OFSwitchAppHandshakePlugin.PluginResultType;
import net.floodlightcontroller.core.internal.OFSwitchHandshakeHandler.QuarantineState;
import net.floodlightcontroller.core.internal.OFSwitchHandshakeHandler.WaitAppHandshakeState;
import net.floodlightcontroller.debugcounter.DebugCounterServiceImpl;
import net.floodlightcontroller.debugcounter.IDebugCounterService;
import org.projectfloodlight.openflow.protocol.OFBadActionCode;
import org.projectfloodlight.openflow.protocol.OFBadRequestCode;
import org.projectfloodlight.openflow.protocol.OFBarrierReply;
import org.projectfloodlight.openflow.protocol.OFControllerRole;
import org.projectfloodlight.openflow.protocol.OFDescStatsReply;
import org.projectfloodlight.openflow.protocol.OFErrorMsg;
import org.projectfloodlight.openflow.protocol.OFFactory;
import org.projectfloodlight.openflow.protocol.OFFeaturesReply;
import org.projectfloodlight.openflow.protocol.OFGetConfigReply;
import org.projectfloodlight.openflow.protocol.OFMessage;
import org.projectfloodlight.openflow.protocol.OFPacketIn;
import org.projectfloodlight.openflow.protocol.OFPacketInReason;
import org.projectfloodlight.openflow.protocol.OFPortDesc;
import org.projectfloodlight.openflow.protocol.OFPortReason;
import org.projectfloodlight.openflow.protocol.OFPortStatus;
import org.projectfloodlight.openflow.protocol.OFSetConfig;
import org.projectfloodlight.openflow.protocol.OFStatsRequest;
import org.projectfloodlight.openflow.protocol.OFStatsType;
import org.projectfloodlight.openflow.protocol.OFTableFeatureProp;
import org.projectfloodlight.openflow.protocol.OFTableFeaturesStatsReply;
import org.projectfloodlight.openflow.protocol.OFType;
import org.projectfloodlight.openflow.protocol.OFVersion;
import org.projectfloodlight.openflow.protocol.match.Match;
import org.projectfloodlight.openflow.types.DatapathId;
import org.projectfloodlight.openflow.types.OFAuxId;
import org.projectfloodlight.openflow.types.OFPort;
import org.projectfloodlight.openflow.types.TableId;
import org.projectfloodlight.openflow.types.U32;
import org.projectfloodlight.openflow.types.U64;
import net.floodlightcontroller.util.LinkedHashSetWrapper;
import net.floodlightcontroller.util.OrderedCollection;
import com.google.common.collect.ImmutableList;
public abstract class OFSwitchHandlerTestBase {
protected static final DatapathId dpid = DatapathId.of(0x42L);
protected IOFSwitchManager switchManager;
protected RoleManager roleManager;
private IDebugCounterService debugCounterService;
protected OFSwitchHandshakeHandler switchHandler;
protected MockOFConnection connection;
// Use a 1.0 factory for the 1.0 test
protected final OFFactory factory = getFactory();
protected OFFeaturesReply featuresReply;
protected List<IAppHandshakePluginFactory> plugins;
private HashSet<Long> seenXids = null;
protected IOFSwitchBackend sw;
private Timer timer;
private TestHandshakePlugin handshakePlugin;
private class TestHandshakePlugin extends OFSwitchAppHandshakePlugin {
protected TestHandshakePlugin(PluginResult defaultResult, int timeoutS) {
super(defaultResult, timeoutS);
}
@Override
protected void processOFMessage(OFMessage m) {
}
@Override
protected void enterPlugin() {
}
}
public void setUpFeaturesReply() {
getFeaturesReply();
this.featuresReply = getFeaturesReply();
// Plugin set
IAppHandshakePluginFactory factory = createMock(IAppHandshakePluginFactory.class);
PluginResult result = new PluginResult(PluginResultType.QUARANTINE, "test quarantine");
handshakePlugin = new TestHandshakePlugin(result, 5);
expect(factory.createPlugin()).andReturn(handshakePlugin).anyTimes();
replay(factory);
plugins = ImmutableList.of(factory);
}
@Before
public void setUp() throws Exception {
/*
* This needs to be called explicitly to ensure the featuresReply is not null.
* Otherwise, there is no guarantee @Before will for setUpFeaturesReply() will
* call that function before our @Before setUp() here.
*/
setUpFeaturesReply();
switchManager = createMock(IOFSwitchManager.class);
roleManager = createMock(RoleManager.class);
sw = createMock(IOFSwitchBackend.class);
timer = createMock(Timer.class);
expect(timer.newTimeout(anyObject(TimerTask.class), anyLong(), anyObject(TimeUnit.class))).andReturn(EasyMock.createNiceMock(Timeout.class));
replay(timer);
seenXids = null;
// TODO: should mock IDebugCounterService and make sure
// the expected counters are updated.
debugCounterService = new DebugCounterServiceImpl();
SwitchManagerCounters counters =
new SwitchManagerCounters(debugCounterService);
expect(switchManager.getCounters()).andReturn(counters).anyTimes();
replay(switchManager);
connection = new MockOFConnection(featuresReply.getDatapathId(), OFAuxId.MAIN);
switchHandler = new OFSwitchHandshakeHandler(connection, featuresReply, switchManager, roleManager, timer);
// replay sw. Reset it if you need more specific behavior
replay(sw);
}
@After
public void tearDown() {
verifyAll();
}
private void verifyAll() {
assertThat("Unexpected messages have been captured",
connection.getMessages(),
Matchers.empty());
// verify all mocks.
verify(sw);
}
void verifyUniqueXids(OFMessage... msgs) {
verifyUniqueXids(Arrays.asList(msgs));
}
/** make sure that the transaction ids in the given messages are
* not 0 and differ between each other.
* While it's not a defect per se if the xids are we want to ensure
* we use different ones for each message we send.
*/
void verifyUniqueXids(List<OFMessage> msgs) {
if (seenXids == null)
seenXids = new HashSet<Long>();
for (OFMessage m: msgs) {
long xid = m.getXid();
assertTrue("Xid in messags is 0", xid != 0);
assertFalse("Xid " + xid + " has already been used",
seenXids.contains(xid));
seenXids.add(xid);
}
}
/*************************** abstract phases / utilities to be filled in by the subclasses */
// Factory + messages
/** @return the version-appropriate factory */
public abstract OFFactory getFactory();
/**
* @return a version appropriate features reply (different in 1.3 because it
* doesn't have ports)
*/
abstract OFFeaturesReply getFeaturesReply();
/** @return the class that's used for role requests/replies (OFNiciraRoleRequest vs.
* OFRequest)
*/
/// Role differences
abstract Class<?> getRoleRequestClass();
/** Verify that the given OFMessage is a correct RoleRequest message
* for the given role using the given xid (for the version).
*/
public abstract void verifyRoleRequest(OFMessage m,
OFControllerRole expectedRole);
/** Return a RoleReply message for the given role */
protected abstract OFMessage getRoleReply(long xid, OFControllerRole role);
/// Difference in the handshake sequence
/** OF1.3 has the PortDescStatsRequest, OF1.0 not */
abstract void moveToPreConfigReply() throws Exception;
/**
* Move the channel from scratch to WaitAppHandshakeState
* Different for OF1.0 and OF1.3 because of GenTables.
* @throws Exception
*/
@Test
public abstract void moveToWaitAppHandshakeState() throws Exception;
/**
* Move the channel from scratch to WaitSwitchDriverSubHandshake
* Different for OF1.0 and OF1.3 because of GenTables.
* @throws Exception
*/
@Test
public abstract void moveToWaitSwitchDriverSubHandshake() throws Exception;
/**
* Move the channel from scratch to WaitInitialRole
* Different for OF1.0 and OF1.3 because of Controller Connections.
* @throws Exception
*/
@Test
public abstract void moveToWaitInitialRole() throws Exception;
/*******************************************************************************************/
/** Move the channel from scratch to INIT state
This occurs upon creation of the switch handler
*/
@Test
public void testInitState() throws Exception {
assertThat(connection.getListener(), notNullValue());
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.InitState.class));
}
/** Move the channel from scratch to WAIT_CONFIG_REPLY state
* adds testing for beginHandshake() which moves the state from
* InitState to WaitConfigReply.
*/
@Test
public void moveToWaitConfigReply() throws Exception {
moveToPreConfigReply();
List<OFMessage> msgs = connection.getMessages();
assertEquals(3, msgs.size());
assertEquals(OFType.SET_CONFIG, msgs.get(0).getType());
OFSetConfig sc = (OFSetConfig)msgs.get(0);
assertEquals(0xffff, sc.getMissSendLen());
assertEquals(OFType.BARRIER_REQUEST, msgs.get(1).getType());
assertEquals(OFType.GET_CONFIG_REQUEST, msgs.get(2).getType());
verifyUniqueXids(msgs);
msgs.clear();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitConfigReplyState.class));
verifyAll();
}
/** Move the channel from scratch to WAIT_DESCRIPTION_STAT_REPLY state
* Builds on moveToWaitConfigReply()
* adds testing for WAIT_CONFIG_REPLY state
*/
@Test
public void moveToWaitDescriptionStatReply() throws Exception {
moveToWaitConfigReply();
connection.clearMessages();
OFGetConfigReply cr = factory.buildGetConfigReply()
.setMissSendLen(0xFFFF)
.build();
switchHandler.processOFMessage(cr);
OFMessage msg = connection.retrieveMessage();
assertEquals(OFType.STATS_REQUEST, msg.getType());
OFStatsRequest<?> sr = (OFStatsRequest<?>)msg;
assertEquals(OFStatsType.DESC, sr.getStatsType());
verifyUniqueXids(msg);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitDescriptionStatReplyState.class));
}
protected OFDescStatsReply createDescriptionStatsReply() {
OFDescStatsReply statsReply = factory.buildDescStatsReply()
.setDpDesc("Datapath Description")
.setHwDesc("Hardware Description")
.setMfrDesc("Manufacturer Description")
.setSwDesc("Software Description")
.setSerialNum("Serial Number")
.build();
return statsReply;
}
protected OFTableFeaturesStatsReply createTableFeaturesStatsReply() {
OFTableFeaturesStatsReply statsReply = factory.buildTableFeaturesStatsReply()
.setEntries(Collections.singletonList(factory.buildTableFeatures()
.setConfig(0)
.setMaxEntries(100)
.setMetadataMatch(U64.NO_MASK)
.setMetadataWrite(U64.NO_MASK)
.setName("MyTable")
.setTableId(TableId.of(1))
.setProperties(Collections.singletonList((OFTableFeatureProp)factory.buildTableFeaturePropMatch()
.setOxmIds(Collections.singletonList(U32.of(100)))
.build())
).build()
)
).build();
return statsReply;
}
/**
* setup the expectations for the mock switch that are needed
* after the switch is instantiated in the WAIT_DESCRIPTION_STATS STATE
* Will reset the switch
* @throws CounterException
*/
protected void setupSwitchForInstantiationWithReset()
throws Exception {
reset(sw);
sw.setFeaturesReply(featuresReply);
expectLastCall().once();
}
/**
* Tests a situation where a switch returns a QUARANTINE result. This means
* we should move the handshake handler to a quarantine state and also
* quarantine the switch in the controller.
*
* @throws Exception
*/
@Test
public void moveQuarantine() throws Exception {
moveToWaitAppHandshakeState();
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, SwitchStatus.QUARANTINED);
expectLastCall().once();
replay(switchManager);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(WaitAppHandshakeState.class));
WaitAppHandshakeState state = (WaitAppHandshakeState) switchHandler.getStateForTesting();
assertThat(state.getCurrentPlugin(), CoreMatchers.<OFSwitchAppHandshakePlugin>equalTo(handshakePlugin));
reset(sw);
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE);
sw.setStatus(SwitchStatus.QUARANTINED);
expectLastCall().once();
replay(sw);
PluginResult result = new PluginResult(PluginResultType.QUARANTINE, "test quarantine");
handshakePlugin.exitPlugin(result);
assertThat(switchHandler.getStateForTesting(),
CoreMatchers.instanceOf(QuarantineState.class));
verify(switchManager);
}
/**
* Tests a situation where a plugin returns a DISCONNECT result. This means
* we should disconnect the connection and the state should not change.
*
* @throws Exception
*/
@Test
public void failedAppHandshake() throws Exception {
moveToWaitAppHandshakeState();
assertThat(switchHandler.getStateForTesting(),
CoreMatchers.instanceOf(WaitAppHandshakeState.class));
WaitAppHandshakeState state = (WaitAppHandshakeState) switchHandler.getStateForTesting();
assertThat(state.getCurrentPlugin(), CoreMatchers.<OFSwitchAppHandshakePlugin>equalTo(handshakePlugin));
PluginResult result = new PluginResult(PluginResultType.DISCONNECT);
handshakePlugin.exitPlugin(result);
assertThat(connection.isConnected(), equalTo(false));
}
@Test
public void validAppHandshakePluginReason() throws Exception {
try{
new PluginResult(PluginResultType.QUARANTINE,"This should not cause an exception");
}catch(IllegalStateException e) {
fail("This should cause an illegal state exception");
}
}
@Test
public void invalidAppHandshakePluginReason() throws Exception {
try{
new PluginResult(PluginResultType.CONTINUE,"This should cause an exception");
fail("This should cause an illegal state exception");
}catch(IllegalStateException e) { /* Expected */ }
try{
new PluginResult(PluginResultType.DISCONNECT,"This should cause an exception");
fail("This should cause an illegal state exception");
}catch(IllegalStateException e) { /* Expected */ }
}
/**
* Move the channel from scratch to WAIT_INITIAL_ROLE state via
* WAIT_SWITCH_DRIVER_SUB_HANDSHAKE
* Does extensive testing for the WAIT_SWITCH_DRIVER_SUB_HANDSHAKE state
*
*/
@Test
public void testSwitchDriverSubHandshake()
throws Exception {
moveToWaitSwitchDriverSubHandshake();
//-------------------------------------------------
//-------------------------------------------------
// Send a message to the handler, it should be passed to the
// switch's sub-handshake handling. After this message the
// sub-handshake will be complete
// FIXME:LOJI: With Andi's fix for a default Match object we won't
// need to build/set this match object
Match match = factory.buildMatch().build();
OFMessage m = factory.buildFlowRemoved().setMatch(match).build();
resetToStrict(sw);
sw.processDriverHandshakeMessage(m);
expectLastCall().once();
expect(sw.isDriverHandshakeComplete()).andReturn(true).once();
replay(sw);
switchHandler.processOFMessage(m);
assertThat(switchHandler.getStateForTesting(),
CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitAppHandshakeState.class));
assertThat("Unexpected message captured", connection.getMessages(), Matchers.empty());
verify(sw);
}
@Test
/** Test WaitDescriptionReplyState */
public void testWaitDescriptionReplyState() throws Exception {
moveToWaitInitialRole();
}
/**
* Setup the mock switch and write capture for a role request, set the
* role and verify mocks.
* @param supportsNxRole whether the switch supports role request messages
* to setup the attribute. This must be null (don't yet know if roles
* supported: send to check) or true.
* @param role The role to send
* @throws IOException
*/
private long setupSwitchSendRoleRequestAndVerify(Boolean supportsNxRole,
OFControllerRole role) throws IOException {
assertTrue("This internal test helper method most not be called " +
"with supportsNxRole==false. Test setup broken",
supportsNxRole == null || supportsNxRole == true);
reset(sw);
expect(sw.getAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE))
.andReturn(supportsNxRole).atLeastOnce();
replay(sw);
switchHandler.sendRoleRequest(role);
OFMessage msg = connection.retrieveMessage();
verifyRoleRequest(msg, role);
verify(sw);
return msg.getXid();
}
/**
* Setup the mock switch for a role change request where the switch
* does not support roles.
*
* Needs to verify and reset the controller since we need to set
* an expectation
*/
@SuppressWarnings("unchecked")
private void setupSwitchRoleChangeUnsupported(int xid,
OFControllerRole role) {
SwitchStatus newStatus = role != OFControllerRole.ROLE_SLAVE ? SwitchStatus.MASTER : SwitchStatus.SLAVE;
boolean supportsNxRole = false;
verify(switchManager);
reset(sw, switchManager);
expect(sw.getAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE))
.andReturn(supportsNxRole).atLeastOnce();
// TODO: hmmm. While it's not incorrect that we set the attribute
// again it looks odd. Maybe change
expect(sw.getOFFactory()).andReturn(factory).anyTimes();
expect(sw.write(anyObject(OFMessage.class))).andReturn(true).anyTimes();
expect(sw.write(anyObject(Iterable.class))).andReturn(Collections.EMPTY_LIST).anyTimes();
expect(sw.getNumTables()).andStubReturn((short)0);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, supportsNxRole);
expectLastCall().anyTimes();
if (SwitchStatus.MASTER == newStatus) {
if (factory.getVersion().compareTo(OFVersion.OF_13) >= 0) {
expect(sw.getTables()).andReturn(Collections.EMPTY_LIST).once();
expect(sw.getTableFeatures(TableId.ZERO)).andReturn(TableFeatures.of(createTableFeaturesStatsReply().getEntries().get(0))).anyTimes();
}
}
sw.setControllerRole(role);
expectLastCall().once();
if (role == OFControllerRole.ROLE_SLAVE) {
sw.disconnect();
expectLastCall().once();
} else {
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE).once();
sw.setStatus(newStatus);
expectLastCall().once();
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, newStatus);
}
replay(sw, switchManager);
switchHandler.sendRoleRequest(role);
/* Now, trigger transition to master */
OFBarrierReply br = getFactory().buildBarrierReply()
.build();
switchHandler.processOFMessage(br);
verify(sw, switchManager);
}
/** Return a bad request error message with the given xid/code */
private OFMessage getBadRequestErrorMessage(OFBadRequestCode code, long xid) {
OFErrorMsg msg = factory.errorMsgs().buildBadRequestErrorMsg()
.setXid(xid)
.setCode(code)
.build();
return msg;
}
/** Return a bad action error message with the given xid/code */
private OFMessage getBadActionErrorMessage(OFBadActionCode code, long xid) {
OFErrorMsg msg = factory.errorMsgs().buildBadActionErrorMsg()
.setXid(xid)
.setCode(code)
.build();
return msg;
}
/** Move the channel from scratch to MASTER state
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*
* This method tests only the simple case that the switch supports roles
* and transitions to MASTER
*/
@SuppressWarnings("unchecked")
@Test
public void testInitialMoveToMasterWithRole() throws Exception {
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_MASTER);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// prepare mocks and inject the role reply message
reset(sw);
expect(sw.getOFFactory()).andReturn(factory).anyTimes();
expect(sw.write(anyObject(OFMessage.class))).andReturn(true).anyTimes();
expect(sw.write(anyObject(Iterable.class))).andReturn(Collections.EMPTY_LIST).anyTimes();
expect(sw.getTables()).andStubReturn(Collections.EMPTY_LIST);
expect(sw.getNumTables()).andStubReturn((short) 0);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, true);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_MASTER);
expectLastCall().once();
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE).once();
sw.setStatus(SwitchStatus.MASTER);
expectLastCall().once();
if (factory.getVersion().compareTo(OFVersion.OF_13) >= 0) {
//expect(sw.getMaxTableForTableMissFlow()).andReturn(TableId.ZERO).times(1);
expect(sw.getTableFeatures(TableId.ZERO)).andReturn(TableFeatures.of(createTableFeaturesStatsReply().getEntries().get(0))).anyTimes();
}
replay(sw);
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, SwitchStatus.MASTER);
expectLastCall().once();
replay(switchManager);
OFMessage reply = getRoleReply(xid, OFControllerRole.ROLE_MASTER);
/* Go into the MasterState */
switchHandler.processOFMessage(reply);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.MasterState.class));
}
/** Move the channel from scratch to SLAVE state
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*
* This method tests only the simple case that the switch supports roles
* and transitions to SLAVE
*/
@Test
public void testInitialMoveToSlaveWithRole() throws Exception {
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_SLAVE);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// prepare mocks and inject the role reply message
reset(sw);
sw.setAttribute(IOFSwitchBackend.SWITCH_SUPPORTS_NX_ROLE, true);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_SLAVE);
expectLastCall().once();
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE).once();
sw.setStatus(SwitchStatus.SLAVE);
expectLastCall().once();
replay(sw);
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, SwitchStatus.SLAVE);
expectLastCall().once();
replay(switchManager);
OFMessage reply = getRoleReply(xid, OFControllerRole.ROLE_SLAVE);
// sendMessageToHandler will verify and rest controller mock
switchHandler.processOFMessage(reply);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.SlaveState.class));
}
/** Move the channel from scratch to MASTER state
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*
* This method tests the case that the switch does NOT support roles.
* The channel handler still needs to send the initial request to find
* out that whether the switch supports roles.
*/
@SuppressWarnings("unchecked")
@Test
public void testInitialMoveToMasterNoRole() throws Exception {
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_MASTER);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// prepare mocks and inject the role reply message
reset(sw);
expect(sw.getOFFactory()).andReturn(factory).anyTimes();
expect(sw.write(anyObject(OFMessage.class))).andReturn(true).anyTimes();
expect(sw.write(anyObject(Iterable.class))).andReturn(Collections.EMPTY_LIST).anyTimes();
expect(sw.getNumTables()).andStubReturn((short)0);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, false);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_MASTER);
expectLastCall().once();
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE).once();
sw.setStatus(SwitchStatus.MASTER);
expectLastCall().once();
if (factory.getVersion().compareTo(OFVersion.OF_13) >= 0) {
expect(sw.getTables()).andReturn(Collections.EMPTY_LIST).once();
expect(sw.getTableFeatures(TableId.ZERO)).andReturn(TableFeatures.of(createTableFeaturesStatsReply().getEntries().get(0))).anyTimes();
}
replay(sw);
// FIXME: shouldn't use ordinal(), but OFError is broken
// Error with incorrect xid and type. Should be ignored.
OFMessage err = getBadActionErrorMessage(OFBadActionCode.BAD_TYPE, xid+1);
// sendMessageToHandler will verify and rest controller mock
switchHandler.processOFMessage(err);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Error with correct xid. Should trigger state transition
err = getBadRequestErrorMessage(OFBadRequestCode.BAD_EXPERIMENTER, xid);
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, SwitchStatus.MASTER);
expectLastCall().once();
replay(switchManager);
/* Go into the MasterState */
switchHandler.processOFMessage(err);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.MasterState.class));
}
/** Move the channel from scratch to MASTER state
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*
* We let the initial role request time out. Role support should be
* disabled but the switch should be activated.
*/
@SuppressWarnings("unchecked")
@Test
public void testInitialMoveToMasterTimeout() throws Exception {
int timeout = 50;
switchHandler.useRoleChangerWithOtherTimeoutForTesting(timeout);
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_MASTER); /* don't care about the XID, since we assume the reply is lost */
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// prepare mocks and inject the role reply message
reset(sw);
expect(sw.getOFFactory()).andReturn(factory).anyTimes();
expect(sw.write(anyObject(OFMessage.class))).andReturn(true).anyTimes();
expect(sw.write(anyObject(Iterable.class))).andReturn(Collections.EMPTY_LIST).anyTimes();
expect(sw.getNumTables()).andStubReturn((short)0);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, false);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_MASTER);
expectLastCall().once();
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE).once();
sw.setStatus(SwitchStatus.MASTER);
expectLastCall().once();
if (factory.getVersion().compareTo(OFVersion.OF_13) >= 0) {
expect(sw.getTables()).andReturn(Collections.EMPTY_LIST).once();
expect(sw.getTableFeatures(TableId.ZERO)).andReturn(TableFeatures.of(createTableFeaturesStatsReply().getEntries().get(0))).anyTimes();
}
replay(sw);
OFMessage m = factory.barrierReply();
Thread.sleep(timeout + 5);
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, SwitchStatus.MASTER);
expectLastCall().once();
replay(switchManager);
switchHandler.processOFMessage(m);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.MasterState.class));
}
/** Move the channel from scratch to SLAVE state
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*
* This method tests the case that the switch does NOT support roles.
* The channel handler still needs to send the initial request to find
* out that whether the switch supports roles.
*
*/
@Test
public void testInitialMoveToSlaveNoRole() throws Exception {
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_SLAVE);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// prepare mocks and inject the role reply message
reset(sw);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, false);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_SLAVE);
expectLastCall().once();
sw.disconnect(); // Make sure we disconnect
expectLastCall().once();
replay(sw);
// FIXME: shouldn't use ordinal(), but OFError is broken
// Error with incorrect xid and type. Should be ignored.
OFMessage err = getBadActionErrorMessage(OFBadActionCode.BAD_TYPE, xid+1);
// sendMessageToHandler will verify and rest controller mock
switchHandler.processOFMessage(err);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Error with correct xid. Should trigger state transition
err = getBadRequestErrorMessage(OFBadRequestCode.BAD_EXPERIMENTER, xid);
// sendMessageToHandler will verify and rest controller mock
switchHandler.processOFMessage(err);
}
/** Move the channel from scratch to SLAVE state
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*
* We let the initial role request time out. The switch should be
* disconnected
*/
@Test
public void testInitialMoveToSlaveTimeout() throws Exception {
int timeout = 50;
switchHandler.useRoleChangerWithOtherTimeoutForTesting(timeout);
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_SLAVE);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// prepare mocks and inject the role reply message
reset(sw);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, false);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_SLAVE);
expectLastCall().once();
sw.disconnect(); // Make sure we disconnect
expectLastCall().once();
replay(sw);
// Apparently this can be any type of message for this test?!
OFMessage m = factory.buildBarrierReply().build();
Thread.sleep(timeout+5);
switchHandler.processOFMessage(m);
}
/** Move channel from scratch to WAIT_INITIAL_STATE, then MASTER,
* then SLAVE for cases where the switch does not support roles.
* I.e., the final SLAVE transition should disconnect the switch.
*/
@Test
public void testNoRoleInitialToMasterToSlave() throws Exception {
int xid = 46;
// First, lets move the state to MASTER without role support
testInitialMoveToMasterNoRole();
assertThat(switchHandler.getStateForTesting(),
CoreMatchers.instanceOf(OFSwitchHandshakeHandler.MasterState.class));
assertThat("Unexpected messages have been captured",
connection.getMessages(),
Matchers.empty());
// try to set master role again. should be a no-op
setupSwitchRoleChangeUnsupported(xid, OFControllerRole.ROLE_MASTER);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.MasterState.class));
assertThat("Unexpected messages have been captured",
connection.getMessages(),
Matchers.empty());
setupSwitchRoleChangeUnsupported(xid, OFControllerRole.ROLE_SLAVE);
assertThat(connection.isConnected(), equalTo(false));
assertThat("Unexpected messages have been captured",
connection.getMessages(),
Matchers.empty());
}
/** Move the channel to MASTER state
* Expects that the channel is in MASTER or SLAVE state.
*
*/
@SuppressWarnings("unchecked")
public void changeRoleToMasterWithRequest() throws Exception {
assertTrue("This method can only be called when handler is in " +
"MASTER or SLAVE role", switchHandler.isHandshakeComplete());
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(true, OFControllerRole.ROLE_MASTER);
// prepare mocks and inject the role reply message
reset(sw);
expect(sw.getOFFactory()).andReturn(factory).anyTimes();
expect(sw.write(anyObject(OFMessage.class))).andReturn(true).anyTimes();
expect(sw.write(anyObject(Iterable.class))).andReturn(Collections.EMPTY_LIST).anyTimes();
expect(sw.getNumTables()).andStubReturn((short)0);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, true);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_MASTER);
expectLastCall().once();
expect(sw.getStatus()).andReturn(SwitchStatus.HANDSHAKE).once();
sw.setStatus(SwitchStatus.MASTER);
expectLastCall().once();
expect(sw.getTables()).andReturn(Collections.EMPTY_LIST).once();
replay(sw);
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.HANDSHAKE, SwitchStatus.MASTER);
expectLastCall().once();
replay(switchManager);
OFMessage reply = getRoleReply(xid, OFControllerRole.ROLE_MASTER);
switchHandler.processOFMessage(reply);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.MasterState.class));
}
/** Move the channel to SLAVE state
* Expects that the channel is in MASTER or SLAVE state.
*
*/
public void changeRoleToSlaveWithRequest() throws Exception {
assertTrue("This method can only be called when handler is in " +
"MASTER or SLAVE role", switchHandler.isHandshakeComplete());
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(true, OFControllerRole.ROLE_SLAVE);
// prepare mocks and inject the role reply message
reset(sw);
sw.setAttribute(IOFSwitch.SWITCH_SUPPORTS_NX_ROLE, true);
expectLastCall().once();
sw.setControllerRole(OFControllerRole.ROLE_SLAVE);
expectLastCall().once();
expect(sw.getStatus()).andReturn(SwitchStatus.MASTER).once();
sw.setStatus(SwitchStatus.SLAVE);
expectLastCall().once();
replay(sw);
reset(switchManager);
switchManager.switchStatusChanged(sw, SwitchStatus.MASTER, SwitchStatus.SLAVE);
expectLastCall().once();
replay(switchManager);
OFMessage reply = getRoleReply(xid, OFControllerRole.ROLE_SLAVE);
connection.getListener().messageReceived(connection, reply);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.SlaveState.class));
}
@Test
public void testMultiRoleChange1() throws Exception {
testInitialMoveToMasterWithRole();
changeRoleToMasterWithRequest();
changeRoleToSlaveWithRequest();
changeRoleToSlaveWithRequest();
changeRoleToMasterWithRequest();
changeRoleToSlaveWithRequest();
}
@Test
public void testMultiRoleChange2() throws Exception {
testInitialMoveToSlaveWithRole();
changeRoleToMasterWithRequest();
changeRoleToSlaveWithRequest();
changeRoleToSlaveWithRequest();
changeRoleToMasterWithRequest();
changeRoleToSlaveWithRequest();
}
/** Start from scratch and reply with an unexpected error to the role
* change request
* Builds on doMoveToWaitInitialRole()
* adds testing for WAIT_INITAL_ROLE state
*/
@Test
public void testInitialRoleChangeOtherError() throws Exception {
// first, move us to WAIT_INITIAL_ROLE_STATE
moveToWaitInitialRole();
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
// Set the role
long xid = setupSwitchSendRoleRequestAndVerify(null, OFControllerRole.ROLE_MASTER);
assertThat(switchHandler.getStateForTesting(), CoreMatchers.instanceOf(OFSwitchHandshakeHandler.WaitInitialRoleState.class));
OFMessage err = getBadActionErrorMessage(OFBadActionCode.BAD_TYPE, xid);
verifyExceptionCaptured(err, SwitchStateException.class);
}
/**
* Test dispatch of messages while in MASTER role
*/
@Test
public void testMessageDispatchMaster() throws Exception {
testInitialMoveToMasterWithRole();
// Send packet in. expect dispatch
OFPacketIn pi = factory.buildPacketIn()
.setReason(OFPacketInReason.NO_MATCH)
.build();
reset(switchManager);
switchManager.handleMessage(sw, pi, null);
expectLastCall().once();
replay(switchManager);
switchHandler.processOFMessage(pi);
// TODO: many more to go
}
/**
* Test port status message handling while MASTER
*
*/
@Test
public void testPortStatusMessageMaster() throws Exception {
DatapathId dpid = featuresReply.getDatapathId();
testInitialMoveToMasterWithRole();
OFPortDesc portDesc = factory.buildPortDesc()
.setName("Port1")
.setPortNo(OFPort.of(1))
.build();
OFPortStatus.Builder portStatusBuilder = factory.buildPortStatus()
.setDesc(portDesc);
// The events we expect sw.handlePortStatus to return
// We'll just use the same list for all valid OFPortReasons and add
// arbitrary events for arbitrary ports that are not necessarily
// related to the port status message. Our goal
// here is not to return the correct set of events but the make sure
// that a) sw.handlePortStatus is called
// b) the list of events sw.handlePortStatus returns is sent
// as IOFSwitchListener notifications.
OrderedCollection<PortChangeEvent> events =
new LinkedHashSetWrapper<PortChangeEvent>();
OFPortDesc.Builder pb = factory.buildPortDesc();
OFPortDesc p1 = pb.setName("eth1").setPortNo(OFPort.of(1)).build();
OFPortDesc p2 = pb.setName("eth2").setPortNo(OFPort.of(2)).build();
OFPortDesc p3 = pb.setName("eth3").setPortNo(OFPort.of(3)).build();
OFPortDesc p4 = pb.setName("eth4").setPortNo(OFPort.of(4)).build();
OFPortDesc p5 = pb.setName("eth5").setPortNo(OFPort.of(5)).build();
events.add(new PortChangeEvent(p1, PortChangeType.ADD));
events.add(new PortChangeEvent(p2, PortChangeType.DELETE));
events.add(new PortChangeEvent(p3, PortChangeType.UP));
events.add(new PortChangeEvent(p4, PortChangeType.DOWN));
events.add(new PortChangeEvent(p5, PortChangeType.OTHER_UPDATE));
for (OFPortReason reason: OFPortReason.values()) {
OFPortStatus portStatus = portStatusBuilder.setReason(reason).build();
reset(sw);
expect(sw.getId()).andReturn(dpid).anyTimes();
expect(sw.processOFPortStatus(portStatus)).andReturn(events).once();
replay(sw);
reset(switchManager);
switchManager.notifyPortChanged(sw, p1, PortChangeType.ADD);
switchManager.notifyPortChanged(sw, p2, PortChangeType.DELETE);
switchManager.notifyPortChanged(sw, p3, PortChangeType.UP);
switchManager.notifyPortChanged(sw, p4, PortChangeType.DOWN);
switchManager.notifyPortChanged(sw, p5, PortChangeType.OTHER_UPDATE);
replay(switchManager);
switchHandler.processOFMessage(portStatus);
verify(sw);
}
}
/**
* Test re-assert MASTER
*
*/
@Test
public void testReassertMaster() throws Exception {
testInitialMoveToMasterWithRole();
OFMessage err = getBadRequestErrorMessage(OFBadRequestCode.EPERM, 42);
reset(roleManager);
roleManager.reassertRole(switchHandler, HARole.ACTIVE);
expectLastCall().once();
replay(roleManager);
reset(switchManager);
switchManager.handleMessage(sw, err, null);
expectLastCall().once();
replay(switchManager);
switchHandler.processOFMessage(err);
verify(sw);
}
/**
* Verify that the given exception event capture (as returned by
* getAndInitExceptionCapture) has thrown an exception of the given
* expectedExceptionClass.
* Resets the capture
* @param err
*/
void verifyExceptionCaptured(
OFMessage err, Class<? extends Throwable> expectedExceptionClass) {
Throwable caughtEx = null;
// This should purposely cause an exception
try{
switchHandler.processOFMessage(err);
}
catch(Exception e){
// Capture the exception
caughtEx = e;
}
assertThat(caughtEx, CoreMatchers.instanceOf(expectedExceptionClass));
}
/**
* Tests the connection closed functionality before the switch handshake is complete.
* Essentially when the switch handshake is only aware of the IOFConnection.
*/
@Test
public void testConnectionClosedBeforeHandshakeComplete() {
// Test connection closed prior to being finished
reset(switchManager);
switchManager.handshakeDisconnected(dpid);
expectLastCall().once();
replay(switchManager);
switchHandler.connectionClosed(connection);
verify(switchManager);
}
/**
* Tests the connection closed functionality after the switch handshake is complete.
* Essentially when the switch handshake is aware of an IOFSwitch.
* @throws Exception
*/
@Test
public void testConnectionClosedAfterHandshakeComplete() throws Exception {
testInitialMoveToMasterWithRole();
// Test connection closed prior to being finished
reset(switchManager);
switchManager.handshakeDisconnected(dpid);
expectLastCall().once();
switchManager.switchDisconnected(sw);
expectLastCall().once();
replay(switchManager);
reset(sw);
expect(sw.getStatus()).andReturn(SwitchStatus.DISCONNECTED).anyTimes();
replay(sw);
switchHandler.connectionClosed(connection);
verify(switchManager);
verify(sw);
}
}
| {'content_hash': 'df46b0f2df296d21d787db07c62c8169', 'timestamp': '', 'source': 'github', 'line_count': 1193, 'max_line_length': 143, 'avg_line_length': 35.934618608549876, 'alnum_prop': 0.7653603918824353, 'repo_name': 'zhenshengcai/floodlight-hardware', 'id': '9f254d658bbe130ac27394707bd8fd619e825218', 'size': '42870', 'binary': False, 'copies': '10', 'ref': 'refs/heads/master', 'path': 'src/test/java/net/floodlightcontroller/core/internal/OFSwitchHandlerTestBase.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'CSS', 'bytes': '362'}, {'name': 'HTML', 'bytes': '20372'}, {'name': 'Java', 'bytes': '4040496'}, {'name': 'JavaScript', 'bytes': '110226'}, {'name': 'Makefile', 'bytes': '426'}, {'name': 'Python', 'bytes': '32743'}, {'name': 'Shell', 'bytes': '5610'}, {'name': 'Thrift', 'bytes': '7114'}]} |
using namespace seqan;
using namespace std;
int main()
{
String<Dna> haystack = "TTATTAAGCGTATAGCCCTATAAATATAA";
String<Dna> needle = "TATAA";
typedef Index<String<Dna>, FMIndex<>> TIndex;
typedef Finder<TIndex> TFinder;
TIndex index(haystack);
TFinder finder(index);
cout << "Found occurences at:\t";
while (find(finder,needle))
cout << position(finder) << " ";
cout << endl;
return 0;
} | {'content_hash': '448fef3355fb6410952d892041fc3827', 'timestamp': '', 'source': 'github', 'line_count': 19, 'max_line_length': 59, 'avg_line_length': 23.157894736842106, 'alnum_prop': 0.6409090909090909, 'repo_name': 'bkahlert/seqan-research', 'id': 'dcefc08cdcaafb0c409b266b880b7ef93e07aa59', 'size': '494', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'raw/pmsb13/pmsb13-data-20130530/sources/qhuulr654q26tohr/2013-04-11T09-50-36.102+0200/sandbox/PMSB13/apps/9.2/9.2.cpp', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'ApacheConf', 'bytes': '39014'}, {'name': 'Awk', 'bytes': '44044'}, {'name': 'Batchfile', 'bytes': '37736'}, {'name': 'C', 'bytes': '1261223'}, {'name': 'C++', 'bytes': '277576131'}, {'name': 'CMake', 'bytes': '5546616'}, {'name': 'CSS', 'bytes': '271972'}, {'name': 'GLSL', 'bytes': '2280'}, {'name': 'Groff', 'bytes': '2694006'}, {'name': 'HTML', 'bytes': '15207297'}, {'name': 'JavaScript', 'bytes': '362928'}, {'name': 'LSL', 'bytes': '22561'}, {'name': 'Makefile', 'bytes': '6418610'}, {'name': 'Objective-C', 'bytes': '3730085'}, {'name': 'PHP', 'bytes': '3302'}, {'name': 'Perl', 'bytes': '10468'}, {'name': 'PostScript', 'bytes': '22762'}, {'name': 'Python', 'bytes': '9267035'}, {'name': 'R', 'bytes': '230698'}, {'name': 'Rebol', 'bytes': '283'}, {'name': 'Shell', 'bytes': '437340'}, {'name': 'Tcl', 'bytes': '15439'}, {'name': 'TeX', 'bytes': '738415'}, {'name': 'VimL', 'bytes': '12685'}]} |
package org.fusfoundation.dicom.part10;
import org.fusfoundation.dicom.DicomString;
import org.fusfoundation.dicom.VR;
import org.fusfoundation.dicom.UID;
import org.fusfoundation.dicom.DicomObjectReader;
import org.fusfoundation.dicom.DicomException;
import org.fusfoundation.dicom.VrReader;
import org.fusfoundation.dicom.VrInputStream;
import org.fusfoundation.dicom.DicomObjectWriter;
import org.fusfoundation.dicom.DicomObject;
import org.fusfoundation.dicom.DicomNumber;
import java.io.*;
import java.util.*;
/**
*
* @author jsnell
*/
public class DicomFileReader implements VrReader {
File inputFile;
InputStream fis;
VrInputStream vis;
DicomObject metaInfo;
/** Creates a new instance of DicomFileReader */
public DicomFileReader(File file) throws DicomException, FileNotFoundException, IOException {
inputFile = file;
fis = new BufferedInputStream(new FileInputStream(file));
fis.skip(128L);
byte[] cookie = new byte[4];
fis.read(cookie);
if (cookie[0] != 'D' || cookie[1] != 'I' || cookie[2] != 'C' || cookie[3] != 'M') {
fis.close();
fis = new BufferedInputStream(new FileInputStream(file));
vis = new VrInputStream(fis, true, true);
metaInfo = new DicomObject();
metaInfo.addVR(new VR("TransferSyntaxUID", new DicomString(UID.ImplicitVRLittleEndian.toString())));
// throw new DicomException("Inavlid DICOM Part-10 file format: 'DICM' not found");
} else {
vis = new VrInputStream(fis, true, false); // meta information is Little Endian, Explicit VR
VR metaGroupTag = vis.readVR();
if(metaGroupTag.getGroup() != 2 || metaGroupTag.getElement() != 0) {
throw new DicomException("Invalid Dicom Part-10 file format: must include (0002,0000)");
}
// Read and parse the rest of the meta information
int grplen = ((DicomNumber)(metaGroupTag.getValue(0))).getIntValue();
byte[] metabuf = new byte[grplen];
fis.read(metabuf);
ByteArrayInputStream bis = new ByteArrayInputStream(metabuf);
VrInputStream mvis = new VrInputStream(bis, true, false); // little-endian, explicit
metaInfo = new DicomObject();
metaInfo.addVR(metaGroupTag);
while (mvis.available() > 0) {
VR v = mvis.readVR();
metaInfo.addVR(v);
}
String v = metaInfo.getVR("TransferSyntaxUID").getStringValue();
UID tsyn = new UID(v);
if (tsyn.equals(UID.ImplicitVRLittleEndian)) {
vis.setIsImplicitVR(true);
vis.setIsLittleEndian(true);
} else if (tsyn.equals(UID.ExplicitVRLittleEndian)) {
vis.setIsImplicitVR(false);
vis.setIsLittleEndian(true);
} else if (tsyn.equals(UID.ExplicitVRBigEndian)) {
vis.setIsImplicitVR(false);
vis.setIsLittleEndian(false);
} else { // Encapsulated transfer syntax, JPEG, RLE, etc.
vis.setIsImplicitVR(false);
vis.setIsLittleEndian(true);
}
}
}
public int available() throws IOException { return vis.available(); }
public VrInputStream getVrInputStream() { return vis; }
public VR readVR() throws IOException { return vis.readVR(); }
public DicomObject getMetaInfo() { return metaInfo; }
public void setReadPixelData(boolean value) {vis.setReadPixelData(value);}
public static void main(String[] args) {
// File file = new File("/home/jsnell/tmp/testfile");
javax.swing.JFileChooser fileDlg = new javax.swing.JFileChooser();
fileDlg.setMultiSelectionEnabled(true);
fileDlg.showOpenDialog(null);
File[] files = fileDlg.getSelectedFiles();
for (int i=0; i<files.length; i++) {
File file = files[i];
try {
DicomFileReader dfr = new DicomFileReader(file);
if (args != null && args.length >= 1 && args[0].equals("--nopixeldata")) {
dfr.setReadPixelData(false);
}
if (args != null && args.length > 1 && args[0].equals("--filter")) {
DicomObjectReader objFileStream = new DicomObjectReader(dfr);
DicomObject imageInfo = objFileStream.read();
for (int f=0; f<args.length-1; f++) {
System.out.print(/*args[f+1] + ": " + */ imageInfo.getVR(args[f+1]).getValue() + "\t");
} System.out.println();
} else {
DicomObjectReader objFileStream = new DicomObjectReader(dfr);
DicomObject imageInfo = objFileStream.read();
System.out.println("Meta Information:\n" + dfr.getMetaInfo());
System.out.println("Image Information:\n" + imageInfo);
ByteArrayOutputStream os = new ByteArrayOutputStream(640000);
DicomObjectWriter oObjStm = new DicomObjectWriter(os, true, false);
oObjStm.write(imageInfo);
ByteArrayInputStream bis = new ByteArrayInputStream(os.toByteArray());
DicomObjectReader iObjStm = new DicomObjectReader(bis, true, false);
DicomObject memobj = iObjStm.read();
System.out.println(memobj);
}
} catch (Exception e) {
System.out.println(e);
}
}
System.exit(0);
}
public void close() throws IOException {
if (vis != null) {
vis.close();
}
if (fis != null) {
fis.close();
}
}
} | {'content_hash': 'd3fd26d2d5bb24b4d4ed422d1f541ca3', 'timestamp': '', 'source': 'github', 'line_count': 147, 'max_line_length': 112, 'avg_line_length': 41.50340136054422, 'alnum_prop': 0.561055564661531, 'repo_name': 'jws2f/Kranion', 'id': 'de6d078a583e66d25e598ca2c5099c78ce80a99e', 'size': '7276', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'src/main/java/org/fusfoundation/dicom/part10/DicomFileReader.java', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'GLSL', 'bytes': '231006'}, {'name': 'Groovy', 'bytes': '8380'}, {'name': 'HTML', 'bytes': '1538'}, {'name': 'Java', 'bytes': '2427568'}, {'name': 'Makefile', 'bytes': '4815'}]} |
<?php
return [
/*
|--------------------------------------------------------------------------
| Validation Language Lines
|--------------------------------------------------------------------------
|
| The following language lines contain the default error messages used by
| the validator class. Some of these rules have multiple versions such
| as the size rules. Feel free to tweak each of these messages here.
|
*/
'accepted' => 'The :attribute must be accepted.',
'active_url' => 'The :attribute is not a valid URL.',
'after' => 'The :attribute must be a date after :date.',
'after_or_equal' => 'The :attribute must be a date after or equal to :date.',
'alpha' => 'The :attribute may only contain letters.',
'alpha_dash' => 'The :attribute may only contain letters, numbers, and dashes.',
'alpha_num' => 'The :attribute may only contain letters and numbers.',
'array' => 'The :attribute must be an array.',
'before' => 'The :attribute must be a date before :date.',
'before_or_equal' => 'The :attribute must be a date before or equal to :date.',
'between' => [
'numeric' => 'The :attribute must be between :min and :max.',
'file' => 'The :attribute must be between :min and :max kilobytes.',
'string' => 'The :attribute must be between :min and :max characters.',
'array' => 'The :attribute must have between :min and :max items.',
],
'boolean' => 'The :attribute field must be true or false.',
'confirmed' => 'The :attribute confirmation does not match.',
'date' => 'The :attribute is not a valid date.',
'date_format' => 'The :attribute does not match the format :format.',
'different' => 'The :attribute and :other must be different.',
'digits' => 'The :attribute must be :digits digits.',
'digits_between' => 'The :attribute must be between :min and :max digits.',
'dimensions' => 'The :attribute has invalid image dimensions.',
'distinct' => 'The :attribute field has a duplicate value.',
'email' => 'The :attribute must be a valid email address.',
'exists' => 'The selected :attribute is invalid.',
'file' => 'The :attribute must be a file.',
'filled' => 'The :attribute field must have a value.',
'image' => 'The :attribute must be an image.',
'in' => 'The selected :attribute is invalid.',
'in_array' => 'The :attribute field does not exist in :other.',
'integer' => 'The :attribute must be an integer.',
'ip' => 'The :attribute must be a valid IP address.',
'json' => 'The :attribute must be a valid JSON string.',
'max' => [
'numeric' => 'The :attribute may not be greater than :max.',
'file' => 'The :attribute may not be greater than :max kilobytes.',
'string' => 'The :attribute may not be greater than :max characters.',
'array' => 'The :attribute may not have more than :max items.',
],
'mimes' => 'The :attribute must be a file of type: :values.',
'mimetypes' => 'The :attribute must be a file of type: :values.',
'min' => [
'numeric' => 'The :attribute must be at least :min.',
'file' => 'The :attribute must be at least :min kilobytes.',
'string' => 'The :attribute must be at least :min characters.',
'array' => 'The :attribute must have at least :min items.',
],
'not_in' => 'The selected :attribute is invalid.',
'numeric' => 'The :attribute must be a number.',
'present' => 'The :attribute field must be present.',
'regex' => 'The :attribute format is invalid.',
'required' => 'The :attribute field is required.',
'required_if' => 'The :attribute field is required when :other is :value.',
'required_unless' => 'The :attribute field is required unless :other is in :values.',
'required_with' => 'The :attribute field is required when :values is present.',
'required_with_all' => 'The :attribute field is required when :values is present.',
'required_without' => 'The :attribute field is required when :values is not present.',
'required_without_all' => 'The :attribute field is required when none of :values are present.',
'same' => 'The :attribute and :other must match.',
'size' => [
'numeric' => 'The :attribute must be :size.',
'file' => 'The :attribute must be :size kilobytes.',
'string' => 'The :attribute must be :size characters.',
'array' => 'The :attribute must contain :size items.',
],
'string' => 'The :attribute must be a string.',
'timezone' => 'The :attribute must be a valid zone.',
'unique' => 'The :attribute has already been taken.',
'uploaded' => 'The :attribute failed to upload.',
'url' => 'The :attribute format is invalid.',
/*
|--------------------------------------------------------------------------
| Custom Validation Language Lines
|--------------------------------------------------------------------------
|
| Here you may specify custom validation messages for attributes using the
| convention "attribute.rule" to name the lines. This makes it quick to
| specify a specific custom language line for a given attribute rule.
|
*/
'custom' => [
'attribute-name' => [
'rule-name' => 'custom-message',
],
],
/*
|--------------------------------------------------------------------------
| Custom Validation Attributes
|--------------------------------------------------------------------------
|
| The following language lines are used to swap attribute place-holders
| with something more reader friendly such as E-Mail Address instead
| of "email". This simply helps us make messages a little cleaner.
|
*/
'attributes' => [],
];
| {'content_hash': '25addfe026454011838656723db1ac90', 'timestamp': '', 'source': 'github', 'line_count': 119, 'max_line_length': 99, 'avg_line_length': 48.831932773109244, 'alnum_prop': 0.5713302357597659, 'repo_name': 'kuzoncby/room-management-system', 'id': '04943ae726a87ccad00d4e7e00bc170835485a33', 'size': '5811', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'resources/lang/en/validation.php', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'ApacheConf', 'bytes': '553'}, {'name': 'HTML', 'bytes': '24058'}, {'name': 'JavaScript', 'bytes': '1886'}, {'name': 'PHP', 'bytes': '81510'}, {'name': 'Vue', 'bytes': '34307'}]} |
using Google.Api.Ads.Common.Util;
using Google.Api.Ads.Dfp.Lib;
using Google.Api.Ads.Dfp.Util.v201502;
using Google.Api.Ads.Dfp.v201502;
using System;
using System.Collections.Generic;
namespace Google.Api.Ads.Dfp.Examples.CSharp.v201502 {
/// <summary>
/// This code example gets all custom fields that apply to line items. To
/// create custom fields, run CreateCustomFields.cs.
///
/// Tags: CustomFieldService.getCustomFieldsByStatement
/// </summary>
class GetAllLineItemCustomFields : SampleBase {
/// <summary>
/// Returns a description about the code example.
/// </summary>
public override string Description {
get {
return "This code example gets all custom fields that apply to line items. To create " +
"custom fields, run CreateCustomFields.cs.";
}
}
/// <summary>
/// Main method, to run this code example as a standalone application.
/// </summary>
/// <param name="args">The command line arguments.</param>
public static void Main(string[] args) {
SampleBase codeExample = new GetAllLineItemCustomFields();
Console.WriteLine(codeExample.Description);
codeExample.Run(new DfpUser());
}
/// <summary>
/// Run the code example.
/// </summary>
/// <param name="user">The DFP user object running the code example.</param>
public override void Run(DfpUser user) {
// Get the CustomFieldService.
CustomFieldService customFieldService = (CustomFieldService) user.GetService(
DfpService.v201502.CustomFieldService);
// Create statement to select only custom fields that apply to line items.
StatementBuilder statementBuilder = new StatementBuilder()
.Where("entityType = :entityType")
.OrderBy("id ASC")
.Limit(StatementBuilder.SUGGESTED_PAGE_LIMIT)
.AddValue("entityType", CustomFieldEntityType.LINE_ITEM.ToString());
// Set default for page.
CustomFieldPage page = new CustomFieldPage();
int i = 0;
try {
do {
// Get custom fields by statement.
page = customFieldService.getCustomFieldsByStatement(statementBuilder.ToStatement());
if (page.results != null) {
foreach (CustomField customField in page.results) {
Console.WriteLine("{0}) Custom field with ID \"{1}\" and name \"{2}\" was found.", i,
customField.id, customField.name);
i++;
}
}
statementBuilder.IncreaseOffsetBy(StatementBuilder.SUGGESTED_PAGE_LIMIT);
} while (statementBuilder.GetOffset() < page.totalResultSetSize);
Console.WriteLine("Number of results found: {0}", page.totalResultSetSize);
} catch (Exception ex) {
Console.WriteLine("Failed to get all line item custom fields. Exception says \"{0}\"",
ex.Message);
}
}
}
}
| {'content_hash': '0610ef49b010f8224a4ff77fa2a9a138', 'timestamp': '', 'source': 'github', 'line_count': 78, 'max_line_length': 99, 'avg_line_length': 37.37179487179487, 'alnum_prop': 0.6483704974271012, 'repo_name': 'stevemanderson/googleads-dotnet-lib', 'id': '413888dc1b8e546e91e0f763984b029b1561359d', 'size': '3554', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'examples/Dfp/CSharp/v201502/CustomFieldService/GetAllLineItemCustomFields.cs', 'mode': '33261', 'license': 'apache-2.0', 'language': [{'name': 'ASP', 'bytes': '13220'}, {'name': 'C#', 'bytes': '15603993'}, {'name': 'CSS', 'bytes': '3082'}, {'name': 'Visual Basic', 'bytes': '1260556'}]} |
var assert = require('assert');
var should = require('should');
var ActionStrategy = require('../lib/action-strategies/action-strategy');
describe('Action Strategy', function () {
var actionStrategy;
beforeEach(function () {
actionStrategy = new ActionStrategy();
});
it('should create new instance', function (done) {
should.exist(actionStrategy);
done();
});
it('should throw `createAction` when called', function (done) {
(function () {
actionStrategy.createAction();
}).should.throw(Error);
done();
});
}); | {'content_hash': 'ac4031eb819f8b756d94bfc28679d0ae', 'timestamp': '', 'source': 'github', 'line_count': 25, 'max_line_length': 73, 'avg_line_length': 24.16, 'alnum_prop': 0.6026490066225165, 'repo_name': 'ziyasal/watch-tower', 'id': '676342ca910a48df333813b253e0cf9fd15b392c', 'size': '604', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'app/tests/action-strategy.test.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'HTML', 'bytes': '18514'}, {'name': 'JavaScript', 'bytes': '36009'}, {'name': 'Shell', 'bytes': '103'}]} |
SYNONYM
#### According to
The Catalogue of Life, 3rd January 2011
#### Published in
null
#### Original name
null
### Remarks
null | {'content_hash': 'c0391b168b7665c84cb94cf55bf8bd70', 'timestamp': '', 'source': 'github', 'line_count': 13, 'max_line_length': 39, 'avg_line_length': 10.23076923076923, 'alnum_prop': 0.6917293233082706, 'repo_name': 'mdoering/backbone', 'id': 'b584865ce7a4fb127655e449a9e11ae8ef09e0c2', 'size': '223', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'life/Plantae/Magnoliophyta/Magnoliopsida/Myrtales/Onagraceae/Chylismia/Chylismia scapoidea/ Syn. Camissonia scapoidea brachycarpa/README.md', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.program.util;
import java.util.*;
import ghidra.program.model.address.*;
import ghidra.program.model.lang.Register;
import ghidra.program.model.listing.*;
import ghidra.program.model.pcode.Varnode;
import ghidra.program.model.symbol.*;
import ghidra.util.exception.AssertException;
import ghidra.util.exception.InvalidInputException;
public class SimpleDiffUtility {
/**
* Convert a variable storage object from the specified program to a comparable variable storage
* object in the specified otherProgram. Certain variable storage (UNIQUE/HASH-based) will
* always produce a null return object.
* @param program program which contains the specified address instance
* @param storage variable storage in program
* @param otherProgram other program
* @return storage for otherProgram or null if storage can not be mapped to other program
*/
public static VariableStorage getCompatibleVariableStorage(Program program,
VariableStorage storage, Program otherProgram) {
if (storage == null || storage.size() == 0 || storage.isHashStorage()) {
return storage;
}
Varnode[] varnodes = storage.getVarnodes();
for (int i = 0; i < varnodes.length; i++) {
varnodes[i] = getCompatibleVarnode(program, varnodes[i], otherProgram);
if (varnodes[i] == null) {
return null;
}
}
try {
return new VariableStorage(otherProgram, varnodes);
}
catch (InvalidInputException e) {
throw new RuntimeException(e); // unexpected
}
}
/**
* Convert a varnode from the specified program to a comparable varnode in the
* specified otherProgram. Certain varnode addresses spaces (UNIQUE, HASH) will
* always produce a null return varnode.
* @param program program which contains the specified address instance
* @param varnode varnode in program
* @param otherProgram other program
* @return varnode for otherProgram or null if varnode can not be mapped to other program
*/
public static Varnode getCompatibleVarnode(Program program, Varnode varnode,
Program otherProgram) {
if (varnode == null || varnode.isConstant()) {
return varnode;
}
Address addr = varnode.getAddress();
if (addr.isRegisterAddress()) {
if (program.getLanguageID().equals(otherProgram.getLanguageID())) {
return varnode;
}
// TODO: Handle improperly aligned offcut register varnodes.
Register reg = program.getRegister(addr, varnode.getSize());
if (reg != null) {
Register otherReg = otherProgram.getRegister(reg.getName());
if (otherReg != null && reg.getMinimumByteSize() == otherReg.getMinimumByteSize()) {
long delta = addr.subtract(reg.getAddress());
if (delta != 0) {
return new Varnode(otherReg.getAddress().add(delta), varnode.getSize());
}
return new Varnode(otherReg.getAddress(), varnode.getSize());
}
}
return null;
}
else if (addr.isMemoryAddress() || addr.isStackAddress()) {
Address otherAddr = getCompatibleAddress(program, addr, otherProgram);
if (otherAddr != null) {
return new Varnode(otherAddr, varnode.getSize());
}
}
return null;
}
/*
* If the specified instruction is contained within a delay slot the minimum address
* of the primary instruction will be returned. If not in a delay slot, the specified
* instructions minimum address is returned.
* @param instr
* @return minimum address of primary instruction
*/
public static Address getStartOfDelaySlots(Instruction instr) {
Listing listing = instr.getProgram().getListing();
Instruction prevInstr = instr;
Address minAddr = prevInstr.getMinAddress();
try {
while (prevInstr != null && prevInstr.isInDelaySlot()) {
minAddr = prevInstr.getMinAddress();
prevInstr = listing.getInstructionContaining(minAddr.subtractNoWrap(1));
}
if (prevInstr != null) {
minAddr = prevInstr.getMinAddress();
}
}
catch (AddressOverflowException e) {
// ignore
}
return minAddr;
}
/**
* If the specified instruction is contained within a delay slot, or has delay slots,
* the maximum address of the last delay slot instruction will be returned.
* If a normal instruction is specified the instructions maximum address is returned.
* @param instr
* @return maximum address of instruction or its last delay slot
*/
public static Address getEndOfDelaySlots(Instruction instr) {
Listing listing = instr.getProgram().getListing();
Address maxAddr = instr.getMaxAddress();
try {
Instruction nextInstr = listing.getInstructionAt(maxAddr.addNoWrap(1));
while (nextInstr != null && nextInstr.isInDelaySlot()) {
maxAddr = nextInstr.getMaxAddress();
nextInstr = listing.getInstructionAt(maxAddr.addNoWrap(1));
}
}
catch (AddressOverflowException e) {
// ignore
}
return maxAddr;
}
/**
* Expand a specified address set to include complete delay slotted instructions
* which may be included at the start or end of each range within the specified
* address set.
* @param program program
* @param originalSet original address set
* @return expanded address set
*/
public static AddressSetView expandAddressSetToIncludeFullDelaySlots(Program program,
AddressSetView originalSet) {
Listing listing = program.getListing();
AddressSet expandedSet = null;
for (AddressRange originRange : originalSet.getAddressRanges()) {
Instruction instr = listing.getInstructionAt(originRange.getMinAddress());
if (instr != null && instr.isInDelaySlot()) {
// expand range up
Address newMinAddr = getStartOfDelaySlots(instr);
if (!newMinAddr.equals(originRange.getMinAddress())) {
if (expandedSet == null) {
expandedSet = new AddressSet(originalSet);
}
expandedSet.addRange(newMinAddr, instr.getMaxAddress());
}
}
instr = listing.getInstructionContaining(originRange.getMaxAddress());
if (instr != null && (instr.isInDelaySlot() || instr.getDelaySlotDepth() != 0)) {
// expand range down
Address newMaxAddr = getEndOfDelaySlots(instr);
if (!newMaxAddr.equals(originRange.getMaxAddress())) {
if (expandedSet == null) {
expandedSet = new AddressSet(originalSet);
}
expandedSet.addRange(instr.getMinAddress(), newMaxAddr);
}
}
}
return expandedSet != null ? expandedSet : originalSet;
}
/**
* Convert an address from the specified program to a comparable address in the
* specified otherProgram.
* @param program program which contains the specified address instance
* @param addr address in program
* @param otherProgram other program
* @return address for otherProgram or null if no such address exists.
*/
public static Address getCompatibleAddress(Program program, Address addr,
Program otherProgram) {
if (addr == null) {
return null;
}
if (addr.isMemoryAddress()) {
return translateMemoryAddress(addr, otherProgram, true);
}
else if (addr.isVariableAddress()) {
// TODO: We should not attempt to correlate variables by their variable address
throw new IllegalArgumentException(
"correlation of variables by their variable address not allowed");
// Address storageAddr = program.getVariableStorageManager().getStorageAddress(addr);
// if (storageAddr == null) {
// return null;
// }
// Address otherStorageAddr = getCompatibleAddress(program, storageAddr, otherProgram);
// if (otherStorageAddr == null) {
// return null;
// }
//
// Namespace namespace = program.getVariableStorageManager().getNamespace(addr);
// Namespace otherNamespace = getNamespace(program, namespace, otherProgram);
// if (otherNamespace == null) {
// return null;
// }
// return otherProgram.getVariableStorageManager().findVariableAddress(otherNamespace.getID(), otherStorageAddr);
}
else if (addr.isStackAddress()) {
return otherProgram.getAddressFactory().getStackSpace().getAddress(addr.getOffset());
}
else if (addr.isRegisterAddress()) {
if (program.getLanguage().getLanguageID().equals(
otherProgram.getLanguage().getLanguageID())) {
return addr;
}
// TODO: should we handle small varnodes within big endian registers
Register reg = program.getRegister(addr);
if (reg != null) {
Register otherReg = otherProgram.getRegister(reg.getName());
if (otherReg != null && reg.getMinimumByteSize() == otherReg.getMinimumByteSize()) {
long delta = addr.subtract(reg.getAddress());
if (delta != 0) {
return otherReg.getAddress().add(delta);
}
return otherReg.getAddress();
}
}
return null;
}
else if (addr.isExternalAddress()) {
Symbol s = program.getSymbolTable().getPrimarySymbol(addr);
if (s != null && s.isExternal()) {
s = getSymbol(s, otherProgram);
if (s != null) {
return s.getAddress();
}
}
return null;
}
else if (addr.getAddressSpace().getType() == AddressSpace.TYPE_NONE ||
addr.getAddressSpace().getType() == AddressSpace.TYPE_UNKNOWN) {
// TODO: Not sure if this is correct ??
return addr;
}
throw new IllegalArgumentException("Unsupported address type");
}
/**
* Convert an address from the specified program to a comparable address in the
* specified otherProgram.
* @param addr address in program
* @param otherProgram other program
* @param exactMatchOnly if false and addr is an overlay address, a closest match will be returned
* if possible
* @return address for otherProgram or null if no such address exists.
*/
protected static Address translateMemoryAddress(Address addr, Program otherProgram,
boolean exactMatchOnly) {
if (!addr.isMemoryAddress()) {
return null;
}
AddressSpace addrSpace = addr.getAddressSpace();
AddressSpace otherSpace = getCompatibleAddressSpace(addrSpace, otherProgram);
if (otherSpace != null) {
if (addrSpace.isOverlaySpace()) {
long offset = addr.getOffset();
if (offset < otherSpace.getMinAddress().getOffset()) {
return exactMatchOnly ? null : otherSpace.getMinAddress();
}
else if (offset > otherSpace.getMaxAddress().getOffset()) {
return exactMatchOnly ? null : otherSpace.getMaxAddress();
}
return otherSpace.getAddress(offset);
}
return otherSpace.getAddress(addr.getOffset());
}
return null;
}
public static AddressSpace getCompatibleAddressSpace(AddressSpace addrSpace,
Program otherProgram) {
AddressSpace otherSpace =
otherProgram.getAddressFactory().getAddressSpace(addrSpace.getName());
if (otherSpace != null && otherSpace.getType() == addrSpace.getType()) {
int id = addrSpace.isOverlaySpace() ? ((OverlayAddressSpace) addrSpace).getBaseSpaceID()
: addrSpace.getSpaceID();
int otherid =
otherSpace.isOverlaySpace() ? ((OverlayAddressSpace) otherSpace).getBaseSpaceID()
: otherSpace.getSpaceID();
if (id == otherid) {
if (otherSpace.isOverlaySpace()) {
long addrOffset = addrSpace.getMinAddress().getOffset();
long otherOffset = otherSpace.getMinAddress().getOffset();
if (addrOffset != otherOffset) {
return null; // Overlays didn't begin at same address.
}
}
return otherSpace;
}
}
return null;
}
/**
* Given a symbol for a specified program, get the corresponding symbol from the
* specified otherProgram.
* @param symbol symbol to look for
* @param otherProgram other program
* @return corresponding symbol for otherProgram or null if no such symbol exists.
*/
public static Symbol getSymbol(Symbol symbol, Program otherProgram) {
if (symbol == null) {
return null;
}
SymbolType symbolType = symbol.getSymbolType();
if (symbolType == SymbolType.GLOBAL) {
return otherProgram.getGlobalNamespace().getSymbol();
}
String name = symbol.getName();
Symbol otherParent = getSymbol(symbol.getParentSymbol(), otherProgram);
Namespace otherNamespace = otherParent == null ? null : (Namespace) otherParent.getObject();
if (otherNamespace == null) {
return null;
}
if (symbolType == SymbolType.LIBRARY) {
return otherProgram.getSymbolTable().getLibrarySymbol(name);
}
if (symbolType == SymbolType.CLASS) {
return otherProgram.getSymbolTable().getClassSymbol(name, otherNamespace);
}
if (symbolType == SymbolType.NAMESPACE) {
return otherProgram.getSymbolTable().getNamespaceSymbol(name, otherNamespace);
}
if (symbolType == SymbolType.PARAMETER || symbolType == SymbolType.LOCAL_VAR) {
return getVariableSymbol(symbol, otherProgram, otherNamespace);
}
if (symbolType == SymbolType.FUNCTION) {
return getOtherFunctionSymbol(symbol, otherProgram, otherNamespace);
}
if (symbolType == SymbolType.LABEL) {
return getOtherCodeSymbol(symbol, otherProgram, otherNamespace);
}
// In case any new SymbolTypes get added
throw new AssertException("Got unexpected SymbolType: " + symbolType);
}
private static Symbol getOtherCodeSymbol(Symbol symbol, Program otherProgram,
Namespace namespace) {
if (symbol.isExternal()) {
return getOtherExternalLocationSymbol(symbol, otherProgram, namespace);
}
Address otherAddress =
getCompatibleAddress(symbol.getProgram(), symbol.getAddress(), otherProgram);
if (otherAddress == null) {
return null;
}
Symbol otherSymbol =
otherProgram.getSymbolTable().getSymbol(symbol.getName(), otherAddress, namespace);
SymbolType otherType = otherSymbol == null ? null : otherSymbol.getSymbolType();
if (otherType == symbol.getSymbolType()) {
return otherSymbol;
}
return null;
}
private static Symbol getOtherFunctionSymbol(Symbol symbol, Program otherProgram,
Namespace otherNamespace) {
if (symbol.isExternal()) {
return getOtherExternalLocationSymbol(symbol, otherProgram, otherNamespace);
}
Function func = (Function) symbol.getObject();
Address entryPoint = func.getEntryPoint();
Address otherEntry = getCompatibleAddress(symbol.getProgram(), entryPoint, otherProgram);
if (otherEntry == null) {
return null;
}
func = otherProgram.getFunctionManager().getFunctionAt(otherEntry);
return func != null ? func.getSymbol() : null;
}
private static Symbol getOtherExternalLocationSymbol(Symbol symbol, Program otherProgram,
Namespace otherNamespace) {
ExternalLocation external = getExternalLocation(symbol);
SymbolTable otherSymbolTable = otherProgram.getSymbolTable();
List<Symbol> otherSymbols = otherSymbolTable.getSymbols(symbol.getName(), otherNamespace);
if (otherSymbols.size() == 1) {
Symbol s = otherSymbols.get(0);
return s.getSymbolType() == symbol.getSymbolType() ? s : null;
}
for (Symbol s : otherSymbols) {
ExternalLocation otherExternalLocation = getExternalLocation(s);
if (external.isEquivalent(otherExternalLocation)) {
return s;
}
}
return null;
}
private static ExternalLocation getExternalLocation(Symbol symbol) {
if (symbol == null) {
return null;
}
Program p = symbol.getProgram();
return p.getExternalManager().getExternalLocation(symbol);
}
private static class ExternalReferenceCount implements Comparable<ExternalReferenceCount> {
final ExternalLocation extLoc;
int refCount = 1;
int rank;
ExternalReferenceCount(ExternalLocation extLoc) {
this.extLoc = extLoc;
}
ExternalLocation getExternalLocation() {
return extLoc;
}
Symbol getSymbol() {
return extLoc.getSymbol();
}
SymbolType getSymbolType() {
return getSymbol().getSymbolType();
}
String getSymbolName() {
return getSymbol().getName();
}
String getFullNamespaceName() {
return getSymbol().getParentNamespace().getName(true);
}
@Override
public int compareTo(ExternalReferenceCount other) {
int diff = other.rank - rank;
if (diff != 0) {
return diff;
}
diff = other.refCount - refCount;
if (diff != 0) {
return diff;
}
// Sort functions before labels, SYmbolType IDs: CODE=0, FUNCTION=5
diff = other.getSymbolType().getID() - getSymbolType().getID();
if (diff != 0) {
return diff;
}
return getSymbol().getName(true).compareTo(other.getSymbol().getName(true));
}
public void setRelativeRank(Address targetAddr, String targetNamespace, String targetName) {
rank = 0;
if (targetAddr != null) {
Address myAddr = extLoc.getAddress();
if (myAddr != null && targetAddr.equals(extLoc.getAddress())) {
rank += 3; // address match
}
else if (myAddr != null) {
// If memory addresses both specified and differ - reduce rank
rank -= 3;
}
}
if (targetName != null && targetName.equals(getSymbolName())) {
rank += 2; // non-default name match
if (targetNamespace != null && targetNamespace.equals(getFullNamespaceName())) {
rank += 1; // non-default namespace match improves name match
}
}
}
}
/**
* Given an external symbol for a specified program, get the corresponding symbol,
* which has the same name and path, from the specified otherProgram.<br>
* Note: The type of the returned symbol may be different than the type of the symbol
* @param program program which contains the specified symbol instance
* @param symbol symbol to look for
* @param otherProgram other program
* @param otherRestrictedSymbolIds an optional set of symbol ID's from the other program
* which will be treated as the exclusive set of candidate symbols to consider.
* @return corresponding external symbol for otherProgram or null if no such symbol exists.
*/
public static Symbol getMatchingExternalSymbol(Program program, Symbol symbol,
Program otherProgram, Set<Long> otherRestrictedSymbolIds) {
if (symbol == null) {
return null;
}
SymbolType type = symbol.getSymbolType();
if ((type != SymbolType.FUNCTION && type != SymbolType.LABEL) || !symbol.isExternal()) {
return null;
}
ReferenceManager refMgr = program.getReferenceManager();
ExternalManager extMgr = program.getExternalManager();
ExternalLocation extLoc = extMgr.getExternalLocation(symbol);
String targetName = symbol.getSource() != SourceType.DEFAULT ? symbol.getName() : null;
String targetNamespace = symbol.getParentNamespace().getName(true);
if (targetNamespace.startsWith(Library.UNKNOWN)) {
targetNamespace = null;
}
Address targetAddr = extLoc.getAddress();
ReferenceManager otherRefMgr = otherProgram.getReferenceManager();
SymbolTable otherSymbMgr = otherProgram.getSymbolTable();
ExternalManager otherExtMgr = otherProgram.getExternalManager();
// Process references
ReferenceIterator refIter = refMgr.getReferencesTo(symbol.getAddress());
HashMap<Address, ExternalReferenceCount> matchesMap = new HashMap<>();
int totalMatchCnt = 0;
while (refIter.hasNext()) {
Reference ref = refIter.next();
Reference otherRef =
otherRefMgr.getPrimaryReferenceFrom(ref.getFromAddress(), ref.getOperandIndex());
if (otherRef == null || !otherRef.isExternalReference()) {
continue;
}
Address otherExtAddr = otherRef.getToAddress();
ExternalReferenceCount refMatch = matchesMap.get(otherExtAddr);
if (refMatch == null) {
Symbol otherSym = otherSymbMgr.getPrimarySymbol(otherExtAddr);
if (otherRestrictedSymbolIds != null &&
!otherRestrictedSymbolIds.contains(otherSym.getID())) {
continue;
}
ExternalLocation otherExtLoc = otherExtMgr.getExternalLocation(otherSym);
refMatch = new ExternalReferenceCount(otherExtLoc);
refMatch.setRelativeRank(targetAddr, targetNamespace, targetName);
matchesMap.put(otherExtAddr, refMatch);
}
else {
++refMatch.refCount;
}
if (++totalMatchCnt == 20) {
break;
}
}
// Process thunk-references (include all)
if (extLoc.isFunction()) {
Address[] thunkAddrs = extLoc.getFunction().getFunctionThunkAddresses();
if (thunkAddrs != null) {
for (Address thunkAddr : thunkAddrs) {
Symbol otherThunkSym = otherSymbMgr.getPrimarySymbol(thunkAddr);
if (otherThunkSym == null ||
otherThunkSym.getSymbolType() != SymbolType.FUNCTION) {
continue;
}
Function otherFunc = (Function) otherThunkSym.getObject();
Function otherThunkedFunc = otherFunc.getThunkedFunction(false);
if (otherThunkedFunc == null || !otherThunkedFunc.isExternal()) {
continue;
}
ExternalReferenceCount refMatch =
matchesMap.get(otherThunkedFunc.getEntryPoint());
if (refMatch == null) {
if (otherRestrictedSymbolIds != null &&
!otherRestrictedSymbolIds.contains(otherThunkedFunc.getID())) {
continue;
}
ExternalLocation otherExtLoc =
otherExtMgr.getExternalLocation(otherThunkedFunc.getSymbol());
refMatch = new ExternalReferenceCount(otherExtLoc);
refMatch.setRelativeRank(targetAddr, targetNamespace, targetName);
matchesMap.put(otherThunkedFunc.getEntryPoint(), refMatch);
}
else {
++refMatch.refCount;
}
}
}
}
if (matchesMap.isEmpty()) {
// Brute force search for match candidates using address/name
// This will occur anytime an external add occurs on program and not otherProgram
for (Symbol otherSym : otherSymbMgr.getExternalSymbols()) {
if (otherRestrictedSymbolIds != null &&
!otherRestrictedSymbolIds.contains(otherSym.getID())) {
continue;
}
boolean addIt = false;
if (targetAddr != null) {
ExternalLocation otherExtLoc = otherExtMgr.getExternalLocation(otherSym);
Address otherAddr = otherExtLoc.getAddress();
if (otherAddr != null && targetAddr.equals(otherAddr) &&
originalNamesDontConflict(extLoc, otherExtLoc)) {
addIt = true;
}
}
if (!addIt && targetName != null && targetName.equals(otherSym.getName())) {
addIt = true;
}
if (addIt) {
ExternalReferenceCount refMatch =
new ExternalReferenceCount(otherExtMgr.getExternalLocation(otherSym));
refMatch.setRelativeRank(targetAddr, targetNamespace, targetName);
matchesMap.put(otherSym.getAddress(), refMatch);
}
}
if (matchesMap.isEmpty()) {
return null;
}
}
ExternalReferenceCount[] matches =
matchesMap.values().toArray(new ExternalReferenceCount[matchesMap.size()]);
if (matches.length == 1) {
// If only one match candidate - rank of 0 is OK
return matches[0].rank >= 0 ? matches[0].getSymbol() : null;
}
// If multiple matches, rank > 0 required (i.e., must match on name and/or addr)
Arrays.sort(matches);
return matches[0].rank > 0 ? matches[0].getSymbol() : null;
}
private static boolean originalNamesDontConflict(ExternalLocation extLoc,
ExternalLocation otherExtLoc) {
if (extLoc.getOriginalImportedName() == null) {
return true;
}
if (otherExtLoc.getOriginalImportedName() == null) {
return true;
}
return extLoc.getOriginalImportedName().equals(otherExtLoc.getOriginalImportedName());
}
/**
* Given an external location for a specified program, get the corresponding external location,
* which has the same name and path, from the specified otherProgram.<br>
* Note: The type of the returned external location may be different than the type of the
* original external location.
* @param program program which contains the specified external location instance
* @param externalLocation external location to look for
* @param otherProgram other program
* @return corresponding external location for otherProgram or null if no such external location exists.
*/
public static ExternalLocation getMatchingExternalLocation(Program program,
ExternalLocation externalLocation, Program otherProgram) {
if (externalLocation == null) {
return null;
}
Symbol symbol = externalLocation.getSymbol();
if (symbol == null) {
return null;
}
Symbol matchingExternalSymbol =
getMatchingExternalSymbol(program, symbol, otherProgram, null);
if (matchingExternalSymbol == null) {
return null;
}
ExternalManager otherExternalManager = otherProgram.getExternalManager();
return otherExternalManager.getExternalLocation(matchingExternalSymbol);
}
/**
* Find the variable symbol in otherProgram which corresponds to the specified varSym.
* @param symbol variable symbol
* @param otherProgram other program
* @return the variable symbol or null
*/
public static Symbol getVariableSymbol(Symbol symbol, Program otherProgram) {
Symbol otherParent = getSymbol(symbol.getParentSymbol(), otherProgram);
Namespace namespace = otherParent == null ? null : (Namespace) otherParent.getObject();
return getVariableSymbol(symbol, otherProgram, namespace);
}
protected static Symbol getVariableSymbol(Symbol varSym, Program otherProgram,
Namespace otherNamespace) {
if (!(otherNamespace instanceof Function)) {
return null;
}
Program program = varSym.getProgram();
SymbolTable otherSymTable = otherProgram.getSymbolTable();
Variable var = (Variable) varSym.getObject();
VariableStorage otherStorage =
getCompatibleVariableStorage(program, var.getVariableStorage(), otherProgram);
if (otherStorage == null || otherStorage.isBadStorage()) {
return null;
}
Variable minVar =
getOverlappingVariable(otherSymTable, var, otherStorage, otherNamespace.getSymbol());
if (minVar != null) {
return minVar.getSymbol();
}
return null;
}
/**
* Find the variable symbol in otherFunction which corresponds to the specified varSym.
* @param varSym variable symbol
* @param otherFunction other function
* @return the variable symbol or null
*/
protected static Symbol getVariableSymbol(Symbol varSym, Function otherFunction) {
Program program = varSym.getProgram();
Program otherProgram = otherFunction.getProgram();
SymbolTable otherSymTable = otherProgram.getSymbolTable();
Variable var = (Variable) varSym.getObject();
Symbol otherFuncSym = otherFunction.getSymbol();
if (otherFuncSym == null || otherFuncSym.getSymbolType() != SymbolType.FUNCTION) {
return null;
}
VariableStorage storage =
getCompatibleVariableStorage(program, var.getVariableStorage(), otherProgram);
if (storage == null || storage.isBadStorage()) {
return null;
}
Variable minVar = getOverlappingVariable(otherSymTable, var, storage, otherFuncSym);
if (minVar != null) {
return minVar.getSymbol();
}
return null;
}
/**
* Find overlapping variable which meets the following conditions
* 1. First use offset matches
* 2. Ordinal matches (for parameters only)
* 3. Minimum or maximum address matches
* @param otherSymTable other symbol table
* @param var variable
* @param otherStorage other variable storage
* @param otherFunctionSymbol other function symbol
* @return the overlapping variable or null
*/
protected static Variable getOverlappingVariable(SymbolTable otherSymTable, Variable var,
VariableStorage otherStorage, Symbol otherFunctionSymbol) {
SymbolType symbolType = var.getSymbol().getSymbolType();
int ordinal = -1;
if (var instanceof Parameter) {
ordinal = ((Parameter) var).getOrdinal();
}
int firstUseOffset = var.getFirstUseOffset();
SymbolIterator symbolIter = otherSymTable.getSymbols(otherFunctionSymbol.getID());
while (symbolIter.hasNext()) {
Symbol s = symbolIter.next();
if (s.getSymbolType() != symbolType) {
continue;
}
Variable v = (Variable) s.getObject();
if (v instanceof Parameter && ordinal != ((Parameter) v).getOrdinal()) {
continue;
}
if (firstUseOffset != v.getFirstUseOffset()) {
continue;
}
if (v.getVariableStorage().equals(otherStorage)) {
return v;
}
}
return null;
}
}
| {'content_hash': '7252d892035db0d82dc5f7c178376da1', 'timestamp': '', 'source': 'github', 'line_count': 801, 'max_line_length': 122, 'avg_line_length': 35.098626716604244, 'alnum_prop': 0.7153731237106068, 'repo_name': 'NationalSecurityAgency/ghidra', 'id': '4667c3ac927e2a1f65b5a14ba3f120cb2fe9dca5', 'size': '28114', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/util/SimpleDiffUtility.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Assembly', 'bytes': '77536'}, {'name': 'Batchfile', 'bytes': '21610'}, {'name': 'C', 'bytes': '1132868'}, {'name': 'C++', 'bytes': '7334484'}, {'name': 'CSS', 'bytes': '75788'}, {'name': 'GAP', 'bytes': '102771'}, {'name': 'GDB', 'bytes': '3094'}, {'name': 'HTML', 'bytes': '4121163'}, {'name': 'Hack', 'bytes': '31483'}, {'name': 'Haskell', 'bytes': '453'}, {'name': 'Java', 'bytes': '88669329'}, {'name': 'JavaScript', 'bytes': '1109'}, {'name': 'Lex', 'bytes': '22193'}, {'name': 'Makefile', 'bytes': '15883'}, {'name': 'Objective-C', 'bytes': '23937'}, {'name': 'Pawn', 'bytes': '82'}, {'name': 'Python', 'bytes': '587415'}, {'name': 'Shell', 'bytes': '234945'}, {'name': 'TeX', 'bytes': '54049'}, {'name': 'XSLT', 'bytes': '15056'}, {'name': 'Xtend', 'bytes': '115955'}, {'name': 'Yacc', 'bytes': '127754'}]} |
//
// PXShapeStyler.m
// Pixate
//
// Created by Kevin Lindsey on 12/18/12.
// Copyright (c) 2012 Pixate, Inc. All rights reserved.
//
#import "PXShapeStyler.h"
#import "PXShape.h"
#import "PXEllipse.h"
#import "PXRectangle.h"
#import "PXArrowRectangle.h"
@implementation PXShapeStyler
#pragma mark - Static Methods
+ (PXShapeStyler *)sharedInstance
{
static __strong PXShapeStyler *sharedInstance = nil;
static dispatch_once_t onceToken;
dispatch_once(&onceToken, ^{
sharedInstance = [[PXShapeStyler alloc] init];
});
return sharedInstance;
}
#pragma mark - Overrides
- (NSDictionary *)declarationHandlers
{
static __strong NSDictionary *handlers = nil;
static dispatch_once_t onceToken;
dispatch_once(&onceToken, ^{
handlers = @{
@"shape" : ^(PXDeclaration *declaration, PXStylerContext *context) {
NSString *stringValue = declaration.stringValue;
if ([@"ellipse" isEqualToString:stringValue])
{
context.shape = [[PXEllipse alloc] init];
}
else if ([@"arrow-button-left" isEqualToString:stringValue])
{
context.shape = [[PXArrowRectangle alloc] initWithDirection:PXArrowRectangleDirectionLeft];
}
else if ([@"arrow-button-right" isEqualToString:stringValue])
{
context.shape = [[PXArrowRectangle alloc] initWithDirection:PXArrowRectangleDirectionRight];
}
else
{
context.shape = [[PXRectangle alloc] init];
}
},
};
});
return handlers;
}
@end
| {'content_hash': '73b7fa8a1e55573c3fe91bc885d59b7f', 'timestamp': '', 'source': 'github', 'line_count': 68, 'max_line_length': 112, 'avg_line_length': 25.264705882352942, 'alnum_prop': 0.5878928987194412, 'repo_name': 'Xaton/pixate-freestyle-ios', 'id': '9473c6da13b73634382b21455bd22d09495e7eaa', 'size': '2320', 'binary': False, 'copies': '15', 'ref': 'refs/heads/master', 'path': 'src/Core/Styling/Stylers/PXShapeStyler.m', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
namespace SharedLibrary
{
public class Consts
{
// Web Request Parameters and URLs
//I got it (Thanks to @halfer) We need to do a POST to google play url:
//https://play.google.com/store/apps/collection/topselling_free
//And we need to send this parms with it:
//start=0 <-- Start from 0;
//num=60 <-- Give back 60 apps
//numChildren=0 <-- I have no idea
//ipf=1 <-- It seems to have a connection with the header
//xhr=1 <-- page format
//If we want app from 60 to 120 we need to request it like this: start=60&num=120
public static readonly string CRAWL_URL = "https://play.google.com/store/search?q={0}&c=apps";
public static readonly string HOST = "play.google.com";
public static readonly string ORIGIN = "https://play.google.com";
public static readonly string REFERER = "https://play.google.com/store/apps";
public static readonly string INITIAL_POST_DATA = "ipf=1&xhr=1";
public static readonly string POST_DATA = "start={0}&num=48&numChildren=0&ipf=1&xhr=1";
public static readonly string APP_URL_PREFIX = "https://play.google.com";
public static readonly string ACCEPT_LANGUAGE = "Accept-Language: en-US;q=0.6,en;q=0.4,es;q=0.2";
// XPaths
public static readonly string APP_LINKS = "//div[@class='cover']/a[@class='card-content-link' and @tabindex='-1' and @aria-hidden='true']";
public static readonly string APP_NAME = "//div[@class='info-container']/div[@class='document-title' and @itemprop='name']/div";
public static readonly string APP_CATEGORY = "//div/a[@class='document-subtitle category']";
public static readonly string APP_DEV = "//div[@class='info-container']/div[@itemprop='author']/a/span[@itemprop='name']";
public static readonly string APP_TOP_DEV = "//meta[@itemprop='topDeveloperBadgeUrl']";
public static readonly string DEV_URL = "//div[@class='info-container']/div[@itemprop='author']/meta[@itemprop='url']";
public static readonly string APP_PUBLISH_DATE = "//div[@class='info-container']/div[@itemprop='author']/div[@class='document-subtitle']";
public static readonly string APP_FREE_PAID = "//span[@itemprop='offers' and @itemtype='http://schema.org/Offer']/meta[@itemprop='price']";
public static readonly string APP_REVIEWERS = "//div[@class='header-star-badge']/div[@class='stars-count']";
public static readonly string APP_DESCRIPTION = "//div[@class='show-more-content text-body' and @itemprop='description']";
public static readonly string APP_SCORE_VALUE = "//div[@class='rating-box']/div[@class='score-container']/meta[@itemprop='ratingValue']";
public static readonly string APP_SCORE_COUNT = "//div[@class='rating-box']/div[@class='score-container']/meta[@itemprop='ratingCount']";
public static readonly string APP_FIVE_STARS = "//div[@class='rating-histogram']/div[@class='rating-bar-container five']/span[@class='bar-number']";
public static readonly string APP_FOUR_STARS = "//div[@class='rating-histogram']/div[@class='rating-bar-container four']/span[@class='bar-number']";
public static readonly string APP_THREE_STARS = "//div[@class='rating-histogram']/div[@class='rating-bar-container three']/span[@class='bar-number']";
public static readonly string APP_TWO_STARS = "//div[@class='rating-histogram']/div[@class='rating-bar-container two']/span[@class='bar-number']";
public static readonly string APP_ONE_STARS = "//div[@class='rating-histogram']/div[@class='rating-bar-container one']/span[@class='bar-number']";
public static readonly string APP_COVER_IMG = "//div[@class='details-info']/div[@class='cover-container']/img[@class='cover-image']";
public static readonly string APP_UPDATE_DATE = "//div[@class='meta-info']/div[@itemprop='datePublished']";
public static readonly string APP_SIZE = "//div[@class='meta-info']/div[@itemprop='fileSize']";
public static readonly string APP_VERSION = "//div[@class='content' and @itemprop='softwareVersion']";
public static readonly string APP_INSTALLS = "//div[@class='content' and @itemprop='numDownloads']";
public static readonly string APP_CONTENT_RATING = "//div[@class='content' and @itemprop='contentRating']";
public static readonly string APP_OS_REQUIRED = "//div[@class='content' and @itemprop='operatingSystems']";
public static readonly string EXTRA_APPS = "//div[@class='card-content id-track-click id-track-impression']/a[@class='card-click-target']";
public static readonly string IN_APP_PURCHASE = "//div[@class='info-container']/div[@class='inapp-msg']";
// HTML Values
public static readonly string NO_RESULT_MESSAGE = "找不到与"; // TODO: CHANGE THIS TO YOUR OWN LANGUAGE.
// THIS CONSTANT IS USED TO CHECK FOR "NO MORE APPS" WHEN YOU PAGINATE/SCROLL THROUGH
// THE SEARCH RESULTS. THE PHRASE MEANS "NO RESULT FOR YOUR SEARCH"
// Retry Values
public static readonly int MAX_REQUEST_ERRORS = 100;
public static readonly int MAX_QUEUE_TRIES = 5;
// AWS
public static readonly string QUEUE_NAME = "PlayStoreQueue";
// MongoDB
// TODO: CHANGE TO YOUR OWN SERVER CREDENTIALS IF NEEDED
// PLEASE NOTE THAT THIS USER HAS READWRITE PERMISSIONS TO THE APPS DATABASE, SO USE IT CAREFULLY
public static readonly string MONGO_SERVER = "127.0.0.1";
public static readonly string MONGO_PORT = "27017";
public static readonly string MONGO_USER = "admin";
public static readonly string MONGO_PASS = "admin";
public static readonly string MONGO_DATABASE = "PlayStore";
public static readonly string MONGO_COLLECTION = "ProcessedApps";
public static readonly string QUEUED_APPS_COLLECTION = "QueuedApps";
public static readonly string MONGO_AUTH_DB = "PlayStore";
public static readonly int MONGO_TIMEOUT = 10000;
// Date Time Format
public static readonly string DATE_FORMAT = "yyyy MMMM dd";
}
}
| {'content_hash': '2953d120a2aa1f70917d1ba0b1b0afea', 'timestamp': '', 'source': 'github', 'line_count': 85, 'max_line_length': 161, 'avg_line_length': 77.69411764705882, 'alnum_prop': 0.6408237431859479, 'repo_name': 'swinghu/gac4net', 'id': '51f82ec6d7c9be1f20b690ca2483c0fdce4e23dc', 'size': '6614', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'GooglePlayAppsCrawler/SharedLibrary/Consts.cs', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'C#', 'bytes': '194256'}, {'name': 'HTML', 'bytes': '44890'}, {'name': 'PowerShell', 'bytes': '7908'}]} |
<!--$Id: lock_notheld.html 63573 2008-05-23 21:43:21Z trent.nelson $-->
<!--Copyright (c) 1997,2008 Oracle. All rights reserved.-->
<!--See the file LICENSE for redistribution information.-->
<html>
<head>
<title>Berkeley DB Reference Guide: Release 3.0: DB_LOCK_NOTHELD</title>
<meta name="description" content="Berkeley DB: An embedded database programmatic toolkit.">
<meta name="keywords" content="embedded,database,programmatic,toolkit,btree,hash,hashing,transaction,transactions,locking,logging,access method,access methods,Java,C,C++">
</head>
<body bgcolor=white>
<table width="100%"><tr valign=top>
<td><b><dl><dt>Berkeley DB Reference Guide:<dd>Upgrading Berkeley DB Applications</dl></b></td>
<td align=right><a href="../upgrade.3.0/rmw.html"><img src="../../images/prev.gif" alt="Prev"></a><a href="../toc.html"><img src="../../images/ref.gif" alt="Ref"></a><a href="../upgrade.3.0/eagain.html"><img src="../../images/next.gif" alt="Next"></a>
</td></tr></table>
<p align=center><b>Release 3.0: DB_LOCK_NOTHELD</b></p>
<p>Historically, the Berkeley DB lock_put and lock_vec interfaces could return
the DB_LOCK_NOTHELD error to indicate that a lock could not be released
as it was held by another locker. This error can no longer be returned
under any circumstances. The application should be searched for any
occurrences of DB_LOCK_NOTHELD. For each of these, the test and any
error processing should be removed.</p>
<table width="100%"><tr><td><br></td><td align=right><a href="../upgrade.3.0/rmw.html"><img src="../../images/prev.gif" alt="Prev"></a><a href="../toc.html"><img src="../../images/ref.gif" alt="Ref"></a><a href="../upgrade.3.0/eagain.html"><img src="../../images/next.gif" alt="Next"></a>
</td></tr></table>
<p><font size=1>Copyright (c) 1996,2008 Oracle. All rights reserved.</font>
</body>
</html>
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'bytes': '63276'}, {'name': 'Batchfile', 'bytes': '147828'}, {'name': 'BlitzBasic', 'bytes': '185102'}, {'name': 'BlitzMax', 'bytes': '2387'}, {'name': 'Boo', 'bytes': '1111'}, {'name': 'Bro', 'bytes': '7337'}, {'name': 'C', 'bytes': '108397183'}, {'name': 'C#', 'bytes': '156749'}, {'name': 'C++', 'bytes': '13535833'}, {'name': 'CLIPS', 'bytes': '6933'}, {'name': 'CMake', 'bytes': '12441'}, {'name': 'COBOL', 'bytes': '114812'}, {'name': 'CSS', 'bytes': '430375'}, {'name': 'Ceylon', 'bytes': '1387'}, {'name': 'Chapel', 'bytes': '4366'}, {'name': 'Cirru', 'bytes': '2574'}, {'name': 'Clean', 'bytes': '9679'}, {'name': 'Clojure', 'bytes': '23871'}, {'name': 'CoffeeScript', 'bytes': '20149'}, {'name': 'ColdFusion', 'bytes': '9006'}, {'name': 'Common Lisp', 'bytes': '49017'}, {'name': 'Coq', 'bytes': '66'}, {'name': 'Cucumber', 'bytes': '390'}, {'name': 'Cuda', 'bytes': '776'}, {'name': 'D', 'bytes': '7556'}, {'name': 'DIGITAL Command Language', 'bytes': '425938'}, {'name': 'DTrace', 'bytes': '6706'}, {'name': 'Dart', 'bytes': '591'}, {'name': 'Dylan', 'bytes': '6343'}, {'name': 'Ecl', 'bytes': '2599'}, {'name': 'Eiffel', 'bytes': '2145'}, {'name': 'Elixir', 'bytes': '4340'}, {'name': 'Emacs Lisp', 'bytes': '18303'}, {'name': 'Erlang', 'bytes': '5746'}, {'name': 'F#', 'bytes': '19156'}, {'name': 'FORTRAN', 'bytes': '38458'}, {'name': 'Factor', 'bytes': '10194'}, {'name': 'Fancy', 'bytes': '2581'}, {'name': 'Fantom', 'bytes': '25331'}, {'name': 'GAP', 'bytes': '29880'}, {'name': 'GLSL', 'bytes': '450'}, {'name': 'Gnuplot', 'bytes': '11501'}, {'name': 'Go', 'bytes': '5444'}, {'name': 'Golo', 'bytes': '1649'}, {'name': 'Gosu', 'bytes': '2853'}, {'name': 'Groff', 'bytes': '3458639'}, {'name': 'Groovy', 'bytes': '2586'}, {'name': 'HTML', 'bytes': '92126540'}, {'name': 'Haskell', 'bytes': '49593'}, {'name': 'Haxe', 'bytes': '16812'}, {'name': 'Hy', 'bytes': '7237'}, {'name': 'IDL', 'bytes': '2098'}, {'name': 'Idris', 'bytes': '2771'}, {'name': 'Inform 7', 'bytes': '1944'}, {'name': 'Inno Setup', 'bytes': '18796'}, {'name': 'Ioke', 'bytes': '469'}, {'name': 'Isabelle', 'bytes': '21392'}, {'name': 'Jasmin', 'bytes': '9428'}, {'name': 'Java', 'bytes': '4040623'}, {'name': 'JavaScript', 'bytes': '223927'}, {'name': 'Julia', 'bytes': '27687'}, {'name': 'KiCad', 'bytes': '475'}, {'name': 'Kotlin', 'bytes': '971'}, {'name': 'LSL', 'bytes': '160'}, {'name': 'Lasso', 'bytes': '18650'}, {'name': 'Lean', 'bytes': '6921'}, {'name': 'Limbo', 'bytes': '9891'}, {'name': 'Liquid', 'bytes': '862'}, {'name': 'LiveScript', 'bytes': '972'}, {'name': 'Logos', 'bytes': '19509'}, {'name': 'Logtalk', 'bytes': '7260'}, {'name': 'Lua', 'bytes': '8677'}, {'name': 'Makefile', 'bytes': '2053844'}, {'name': 'Mask', 'bytes': '815'}, {'name': 'Mathematica', 'bytes': '191'}, {'name': 'Max', 'bytes': '296'}, {'name': 'Modelica', 'bytes': '6213'}, {'name': 'Modula-2', 'bytes': '23838'}, {'name': 'Module Management System', 'bytes': '14798'}, {'name': 'Monkey', 'bytes': '2587'}, {'name': 'Moocode', 'bytes': '3343'}, {'name': 'MoonScript', 'bytes': '14862'}, {'name': 'Myghty', 'bytes': '3939'}, {'name': 'NSIS', 'bytes': '7663'}, {'name': 'Nemerle', 'bytes': '1517'}, {'name': 'NewLisp', 'bytes': '42726'}, {'name': 'Nimrod', 'bytes': '37191'}, {'name': 'Nit', 'bytes': '55581'}, {'name': 'Nix', 'bytes': '2448'}, {'name': 'OCaml', 'bytes': '42416'}, {'name': 'Objective-C', 'bytes': '104883'}, {'name': 'Objective-J', 'bytes': '15340'}, {'name': 'Opa', 'bytes': '172'}, {'name': 'OpenEdge ABL', 'bytes': '49943'}, {'name': 'PAWN', 'bytes': '6555'}, {'name': 'PHP', 'bytes': '68611'}, {'name': 'PLSQL', 'bytes': '45772'}, {'name': 'Pan', 'bytes': '1241'}, {'name': 'Pascal', 'bytes': '349743'}, {'name': 'Perl', 'bytes': '5931502'}, {'name': 'Perl6', 'bytes': '113623'}, {'name': 'PigLatin', 'bytes': '6657'}, {'name': 'Pike', 'bytes': '8479'}, {'name': 'PostScript', 'bytes': '18216'}, {'name': 'PowerShell', 'bytes': '14236'}, {'name': 'Prolog', 'bytes': '43750'}, {'name': 'Protocol Buffer', 'bytes': '3401'}, {'name': 'Puppet', 'bytes': '130'}, {'name': 'Python', 'bytes': '122886305'}, {'name': 'QML', 'bytes': '3912'}, {'name': 'R', 'bytes': '49247'}, {'name': 'Racket', 'bytes': '11341'}, {'name': 'Rebol', 'bytes': '17708'}, {'name': 'Red', 'bytes': '10536'}, {'name': 'Redcode', 'bytes': '830'}, {'name': 'Ruby', 'bytes': '91403'}, {'name': 'Rust', 'bytes': '6788'}, {'name': 'SAS', 'bytes': '15603'}, {'name': 'SaltStack', 'bytes': '1040'}, {'name': 'Scala', 'bytes': '730'}, {'name': 'Scheme', 'bytes': '50346'}, {'name': 'Scilab', 'bytes': '943'}, {'name': 'Shell', 'bytes': '2925518'}, {'name': 'ShellSession', 'bytes': '320'}, {'name': 'Smali', 'bytes': '832'}, {'name': 'Smalltalk', 'bytes': '158636'}, {'name': 'Smarty', 'bytes': '523'}, {'name': 'SourcePawn', 'bytes': '130'}, {'name': 'Standard ML', 'bytes': '36869'}, {'name': 'Swift', 'bytes': '2035'}, {'name': 'SystemVerilog', 'bytes': '265'}, {'name': 'Tcl', 'bytes': '6077233'}, {'name': 'TeX', 'bytes': '487999'}, {'name': 'Tea', 'bytes': '391'}, {'name': 'TypeScript', 'bytes': '535'}, {'name': 'VHDL', 'bytes': '4446'}, {'name': 'VimL', 'bytes': '32053'}, {'name': 'Visual Basic', 'bytes': '19441'}, {'name': 'XQuery', 'bytes': '4289'}, {'name': 'XS', 'bytes': '178055'}, {'name': 'XSLT', 'bytes': '1995174'}, {'name': 'Xtend', 'bytes': '727'}, {'name': 'Yacc', 'bytes': '25665'}, {'name': 'Zephir', 'bytes': '485'}, {'name': 'eC', 'bytes': '31545'}, {'name': 'mupad', 'bytes': '2442'}, {'name': 'nesC', 'bytes': '23697'}, {'name': 'xBase', 'bytes': '3349'}]} |
/** internal
* class Index
*
* Cached variant of [[Trail]]. It assumes the file system does not change
* between `find` calls. All `stat` and `entries` calls are cached for the
* lifetime of the [[Index]] object.
**/
'use strict';
// stdlib
var path = require('path');
// 3rd-party
var _ = require('lodash');
// internal
var common = require('./common');
var prop = require('./common').prop;
// HELPERS /////////////////////////////////////////////////////////////////////
// escape special chars.
// so the string could be safely used as literal in the RegExp.
function regexp_escape(str) {
return str.replace(/([.?*+{}()\[\]])/g, '\\$1');
}
// tells whenever pathname seems like a relative path or not
function is_relative(pathname) {
return (/^\.{1,2}\//).test(pathname);
}
// PRIVATE /////////////////////////////////////////////////////////////////////
// Sorts candidate matches by their extension priority.
// Extensions in the front of the `extensions` carry more weight.
function sort_matches(self, matches, basename) {
var aliases = self.aliases.get(path.extname(basename)).toArray();
return _.sortBy(matches, function (match) {
var extnames = match.replace(basename, '').split(/\./);
return extnames.reduce(function (sum, ext) {
ext = '.' + ext;
if (0 <= self.extensions.indexOf(ext)) {
return sum + self.extensions.indexOf(ext) + 1;
} else if (0 <= aliases.indexOf(ext)) {
return sum + aliases.indexOf(ext) + 11;
} else {
return sum;
}
}, 0);
});
}
// Returns a `Regexp` that matches the allowed extensions.
//
// pattern_for(self, "index.html");
// // -> /^index(.html|.htm)(.builder|.erb)*$/
function pattern_for(self, basename) {
var aliases, extname, pattern;
if (!self.__patterns__[basename]) {
extname = path.extname(basename);
aliases = self.aliases.get(extname).toArray();
if (0 === aliases.length) {
pattern = regexp_escape(basename);
} else {
basename = path.basename(basename, extname);
aliases = [extname].concat(aliases);
pattern = regexp_escape(basename) +
'(?:' + _.map(aliases, regexp_escape).join('|') + ')';
}
pattern += '(?:' + _.map(self.extensions.toArray(), regexp_escape).join('|') + ')*';
self.__patterns__[basename] = new RegExp('^' + pattern + '$');
}
return self.__patterns__[basename];
}
// Checks if the path is actually on the file system and performs
// any syscalls if necessary.
function match(self, dirname, basename, fn) {
var ret, pathname, stats, pattern, matches = self.entries(dirname);
pattern = pattern_for(self, basename);
matches = matches.filter(function (m) { return pattern.test(m); });
matches = sort_matches(self, matches, basename);
while (matches.length && undefined === ret) {
pathname = path.join(dirname, matches.shift());
stats = self.stat(pathname);
if (stats && stats.isFile()) {
ret = fn(pathname);
}
}
return ret;
}
// Returns true if `dirname` is a subdirectory of any of the `paths`
function contains_path(self, dirname) {
return _.any(self.paths.toArray(), function (path) {
return path === dirname.substr(0, path.length);
});
}
// Finds relative logical path, `../test/test_trail`. Requires a
// `base_path` for reference.
function find_in_base_path(self, logical_path, base_path, fn) {
var candidate = path.resolve(base_path, logical_path),
dirname = path.dirname(candidate),
basename = path.basename(candidate);
if (contains_path(self, dirname)) {
return match(self, dirname, basename, fn);
}
}
// Finds logical path across all `paths`
function find_in_paths(self, logical_path, fn) {
var dirname = path.dirname(logical_path),
basename = path.basename(logical_path),
paths = self.paths.toArray(),
pathname;
while (paths.length && undefined === pathname) {
pathname = match(self, path.resolve(paths.shift(), dirname), basename, fn);
}
return pathname;
}
// PUBLIC //////////////////////////////////////////////////////////////////////
/**
* new Index(root, paths, extensions, aliases)
**/
var Index = module.exports = function (root, paths, extensions, aliases) {
/** internal, read-only
* Index#root -> String
*
* Root path. This attribute is immutable.
**/
prop(this, 'root', root);
// Freeze is used here so an error is throw if a mutator method
// is called on the array. Mutating `paths`, `extensions`, or
// `aliases` would have unpredictable results.
/** read-only
* Index#paths -> Paths
*
* Immutable (frozen) [[Paths]] collection.
**/
prop(this, 'paths', paths.clone().freeze());
/** read-only
* Index#extensions -> Extensions
*
* Immutable (frozen) [[Extensions]] collection.
**/
prop(this, 'extensions', extensions.clone().freeze());
/** read-only
* Index#aliases -> Aliases
*
* Immutable map of aliases.
**/
prop(this, 'aliases', aliases.clone().freeze());
// internal cache
prop(this, '__entries__', {});
prop(this, '__patterns__', {});
prop(this, '__stats__', {});
};
/**
* Index#index -> Index
*
* Self-reference to be compatable with the [[Trail]] interface.
**/
Object.defineProperty(Index.prototype, 'index', {
get: function () {
return this;
}
});
/**
* Index#find(logical_paths[, options][, fn]) -> String
*
* The real implementation of `find`.
* [[Trail#find]] generates a one time index and delegates here.
*
* See [[Trail#find]] for usage.
**/
Index.prototype.find = function (logical_paths, options, fn) {
var pathname, base_path, logical_path;
if (!fn && _.isFunction(options)) {
fn = options;
options = {};
} else if (!fn) {
return this.find(logical_paths, options, function (p) {
return p;
});
}
options = options || {};
base_path = options.basePath || this.root;
logical_paths = _.isArray(logical_paths) ? logical_paths.slice() : [logical_paths];
while (logical_paths.length && undefined === pathname) {
logical_path = logical_paths.shift().replace(/^\//, '');
if (is_relative(logical_path)) {
pathname = find_in_base_path(this, logical_path, base_path, fn);
} else {
pathname = find_in_paths(this, logical_path, fn);
}
}
return pathname;
};
/**
* Index#entries(pathname) -> Array
* - pathname(String): Pathname to get files list for.
*
* A cached version of `fs.readdirSync` that filters out `.` files and
* `~` swap files. Returns an empty `Array` if the directory does
* not exist.
**/
Index.prototype.entries = function (pathname) {
if (!this.__entries__[pathname]) {
this.__entries__[pathname] = common.entries(pathname);
}
return this.__entries__[pathname];
};
/**
* Index#stat(pathname) -> Stats|Null
* - pathname(String): Pathname to get stats for.
*
* Cached version of `path.statsSync()`.
* Retuns `null` if file does not exists.
**/
Index.prototype.stat = function (pathname) {
if (!this.__stats__.hasOwnProperty(pathname)) {
this.__stats__[pathname] = common.stat(pathname);
}
return this.__stats__[pathname];
};
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using content::BrowserThread;
// Force all builtin modules to be referenced so they can actually run their
// DSO constructors, see http://git.io/DRIqCg.
#define REFERENCE_MODULE(name) \
extern "C" void _register_ ## name(void); \
void (*fp_register_ ## name)(void) = _register_ ## name
// Electron's builtin modules.
REFERENCE_MODULE(atom_browser_app);
REFERENCE_MODULE(atom_browser_auto_updater);
REFERENCE_MODULE(atom_browser_content_tracing);
REFERENCE_MODULE(atom_browser_dialog);
REFERENCE_MODULE(atom_browser_debugger);
REFERENCE_MODULE(atom_browser_desktop_capturer);
REFERENCE_MODULE(atom_browser_download_item);
REFERENCE_MODULE(atom_browser_menu);
REFERENCE_MODULE(atom_browser_net);
REFERENCE_MODULE(atom_browser_power_monitor);
REFERENCE_MODULE(atom_browser_power_save_blocker);
REFERENCE_MODULE(atom_browser_protocol);
REFERENCE_MODULE(atom_browser_global_shortcut);
REFERENCE_MODULE(atom_browser_render_process_preferences);
REFERENCE_MODULE(atom_browser_session);
REFERENCE_MODULE(atom_browser_system_preferences);
REFERENCE_MODULE(atom_browser_tray);
REFERENCE_MODULE(atom_browser_web_contents);
REFERENCE_MODULE(atom_browser_web_view_manager);
REFERENCE_MODULE(atom_browser_window);
REFERENCE_MODULE(atom_common_asar);
REFERENCE_MODULE(atom_common_clipboard);
REFERENCE_MODULE(atom_common_crash_reporter);
REFERENCE_MODULE(atom_common_native_image);
REFERENCE_MODULE(atom_common_screen);
REFERENCE_MODULE(atom_common_shell);
REFERENCE_MODULE(atom_common_v8_util);
REFERENCE_MODULE(atom_renderer_ipc);
REFERENCE_MODULE(atom_renderer_web_frame);
#undef REFERENCE_MODULE
// The "v8::Function::kLineOffsetNotFound" is exported in node.dll, but the
// linker can not find it, could be a bug of VS.
#if defined(OS_WIN) && !defined(DEBUG)
namespace v8 {
const int Function::kLineOffsetNotFound = -1;
}
#endif
namespace atom {
namespace {
// Convert the given vector to an array of C-strings. The strings in the
// returned vector are only guaranteed valid so long as the vector of strings
// is not modified.
std::unique_ptr<const char*[]> StringVectorToArgArray(
const std::vector<std::string>& vector) {
std::unique_ptr<const char*[]> array(new const char*[vector.size()]);
for (size_t i = 0; i < vector.size(); ++i) {
array[i] = vector[i].c_str();
}
return array;
}
base::FilePath GetResourcesPath(bool is_browser) {
auto command_line = base::CommandLine::ForCurrentProcess();
base::FilePath exec_path(command_line->GetProgram());
PathService::Get(base::FILE_EXE, &exec_path);
base::FilePath resources_path =
#if defined(OS_MACOSX)
is_browser ? exec_path.DirName().DirName().Append("Resources") :
exec_path.DirName().DirName().DirName().DirName().DirName()
.Append("Resources");
#else
exec_path.DirName().Append(FILE_PATH_LITERAL("resources"));
#endif
return resources_path;
}
} // namespace
NodeBindings::NodeBindings(bool is_browser)
: is_browser_(is_browser),
message_loop_(nullptr),
uv_loop_(uv_default_loop()),
embed_closed_(false),
uv_env_(nullptr),
weak_factory_(this) {
}
NodeBindings::~NodeBindings() {
// Quit the embed thread.
embed_closed_ = true;
uv_sem_post(&embed_sem_);
WakeupEmbedThread();
// Wait for everything to be done.
uv_thread_join(&embed_thread_);
// Clear uv.
uv_sem_destroy(&embed_sem_);
}
void NodeBindings::Initialize() {
// Open node's error reporting system for browser process.
node::g_standalone_mode = is_browser_;
node::g_upstream_node_mode = false;
#if defined(OS_LINUX)
// Get real command line in renderer process forked by zygote.
if (!is_browser_)
AtomCommandLine::InitializeFromCommandLine();
#endif
// Init node.
// (we assume node::Init would not modify the parameters under embedded mode).
node::Init(nullptr, nullptr, nullptr, nullptr);
#if defined(OS_WIN)
// uv_init overrides error mode to suppress the default crash dialog, bring
// it back if user wants to show it.
std::unique_ptr<base::Environment> env(base::Environment::Create());
if (is_browser_ || env->HasVar("ELECTRON_DEFAULT_ERROR_MODE"))
SetErrorMode(GetErrorMode() & ~SEM_NOGPFAULTERRORBOX);
#endif
}
node::Environment* NodeBindings::CreateEnvironment(
v8::Handle<v8::Context> context) {
auto args = AtomCommandLine::argv();
// Feed node the path to initialization script.
base::FilePath::StringType process_type = is_browser_ ?
FILE_PATH_LITERAL("browser") : FILE_PATH_LITERAL("renderer");
base::FilePath resources_path = GetResourcesPath(is_browser_);
base::FilePath script_path =
resources_path.Append(FILE_PATH_LITERAL("electron.asar"))
.Append(process_type)
.Append(FILE_PATH_LITERAL("init.js"));
std::string script_path_str = script_path.AsUTF8Unsafe();
args.insert(args.begin() + 1, script_path_str.c_str());
std::unique_ptr<const char*[]> c_argv = StringVectorToArgArray(args);
node::Environment* env = node::CreateEnvironment(
context->GetIsolate(), uv_default_loop(), context,
args.size(), c_argv.get(), 0, nullptr);
// Node uses the deprecated SetAutorunMicrotasks(false) mode, we should switch
// to use the scoped policy to match blink's behavior.
if (!is_browser_) {
context->GetIsolate()->SetMicrotasksPolicy(v8::MicrotasksPolicy::kScoped);
}
mate::Dictionary process(context->GetIsolate(), env->process_object());
process.Set("type", process_type);
process.Set("resourcesPath", resources_path);
// Do not set DOM globals for renderer process.
if (!is_browser_)
process.Set("_noBrowserGlobals", resources_path);
// The path to helper app.
base::FilePath helper_exec_path;
PathService::Get(content::CHILD_PROCESS_EXE, &helper_exec_path);
process.Set("helperExecPath", helper_exec_path);
// Set process._debugWaitConnect if --debug-brk was specified to stop
// the debugger on the first line
if (is_browser_ &&
base::CommandLine::ForCurrentProcess()->HasSwitch("debug-brk"))
process.Set("_debugWaitConnect", true);
return env;
}
void NodeBindings::LoadEnvironment(node::Environment* env) {
node::LoadEnvironment(env);
mate::EmitEvent(env->isolate(), env->process_object(), "loaded");
}
void NodeBindings::PrepareMessageLoop() {
DCHECK(!is_browser_ || BrowserThread::CurrentlyOn(BrowserThread::UI));
// Add dummy handle for libuv, otherwise libuv would quit when there is
// nothing to do.
uv_async_init(uv_loop_, &dummy_uv_handle_, nullptr);
// Start worker that will interrupt main loop when having uv events.
uv_sem_init(&embed_sem_, 0);
uv_thread_create(&embed_thread_, EmbedThreadRunner, this);
}
void NodeBindings::RunMessageLoop() {
DCHECK(!is_browser_ || BrowserThread::CurrentlyOn(BrowserThread::UI));
// The MessageLoop should have been created, remember the one in main thread.
message_loop_ = base::MessageLoop::current();
// Run uv loop for once to give the uv__io_poll a chance to add all events.
UvRunOnce();
}
void NodeBindings::UvRunOnce() {
DCHECK(!is_browser_ || BrowserThread::CurrentlyOn(BrowserThread::UI));
node::Environment* env = uv_env();
// Use Locker in browser process.
mate::Locker locker(env->isolate());
v8::HandleScope handle_scope(env->isolate());
// Enter node context while dealing with uv events.
v8::Context::Scope context_scope(env->context());
// Perform microtask checkpoint after running JavaScript.
v8::MicrotasksScope script_scope(env->isolate(),
v8::MicrotasksScope::kRunMicrotasks);
// Deal with uv events.
int r = uv_run(uv_loop_, UV_RUN_NOWAIT);
if (r == 0)
message_loop_->QuitWhenIdle(); // Quit from uv.
// Tell the worker thread to continue polling.
uv_sem_post(&embed_sem_);
}
void NodeBindings::WakeupMainThread() {
DCHECK(message_loop_);
message_loop_->PostTask(FROM_HERE, base::Bind(&NodeBindings::UvRunOnce,
weak_factory_.GetWeakPtr()));
}
void NodeBindings::WakeupEmbedThread() {
uv_async_send(&dummy_uv_handle_);
}
// static
void NodeBindings::EmbedThreadRunner(void *arg) {
NodeBindings* self = static_cast<NodeBindings*>(arg);
while (true) {
// Wait for the main loop to deal with events.
uv_sem_wait(&self->embed_sem_);
if (self->embed_closed_)
break;
// Wait for something to happen in uv loop.
// Note that the PollEvents() is implemented by derived classes, so when
// this class is being destructed the PollEvents() would not be available
// anymore. Because of it we must make sure we only invoke PollEvents()
// when this class is alive.
self->PollEvents();
if (self->embed_closed_)
break;
// Deal with event in main thread.
self->WakeupMainThread();
}
}
} // namespace atom
| {'content_hash': 'bff504a2893645ddca1a17d8ff416764', 'timestamp': '', 'source': 'github', 'line_count': 260, 'max_line_length': 80, 'avg_line_length': 34.03846153846154, 'alnum_prop': 0.700225988700565, 'repo_name': 'deed02392/electron', 'id': 'e869d2a7031c24175fe8b4e525a4fe78ea4927c3', 'size': '9636', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'atom/common/node_bindings.cc', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'C', 'bytes': '4055'}, {'name': 'C++', 'bytes': '2106783'}, {'name': 'HTML', 'bytes': '15853'}, {'name': 'JavaScript', 'bytes': '602085'}, {'name': 'Objective-C', 'bytes': '28871'}, {'name': 'Objective-C++', 'bytes': '192842'}, {'name': 'PowerShell', 'bytes': '99'}, {'name': 'Python', 'bytes': '95895'}, {'name': 'Shell', 'bytes': '2593'}]} |
@interface WMTableViewController : UITableViewController
@end
| {'content_hash': '68b8a432210258f57928c2f015dbb191', 'timestamp': '', 'source': 'github', 'line_count': 3, 'max_line_length': 56, 'avg_line_length': 21.0, 'alnum_prop': 0.8571428571428571, 'repo_name': 'wangmchn/WMPageController', 'id': 'cbd153d6245a432d669d08795d6aad266c0b2ca1', 'size': '227', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'WMPageControllerDemo/ViewFrameExample/ViewFrameDemo/Controllers/WMTableViewController.h', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'Objective-C', 'bytes': '166372'}, {'name': 'Ruby', 'bytes': '1114'}]} |
'use strict';
var grunt = require('grunt');
var path = require('path');
var exec = require('child_process').exec;
var execOptions = {
cwd: path.join(__dirname, '..')
};
/*
======== A Handy Little Nodeunit Reference ========
https://github.com/caolan/nodeunit
Test methods:
test.expect(numAssertions)
test.done()
Test assertions:
test.ok(value, [message])
test.equal(actual, expected, [message])
test.notEqual(actual, expected, [message])
test.deepEqual(actual, expected, [message])
test.notDeepEqual(actual, expected, [message])
test.strictEqual(actual, expected, [message])
test.notStrictEqual(actual, expected, [message])
test.throws(block, [error], [message])
test.doesNotThrow(block, [error], [message])
test.ifError(value)
*/
exports.makecsp = {
setUp: function(done) {
done();
},
default_options: function(test) {
test.expect(1);
var expected = grunt.file.readJSON('test/expected/default_options.json');
exec('grunt makecsp:default_options', execOptions, function(error, stdout){
var actual = grunt.file.readJSON('csp.json');
test.deepEqual(actual, expected, 'Should create a file called csp.json without any urls in it.');
test.done();
});
},
doubles: function(test){
test.expect(9);
var expected = grunt.file.readJSON('test/expected/doubles.json');
var expectedNbOfWarnings = 7;
var nbOfWarnings = 0;
var scriptWarns = 0;
var styleWarns = 0;
var eventWarns = 0;
var evalWarns = 0;
var jsurlWarn = false;
var isupWarn = false;
var templateWarn = 0;
var doublesPath = "test/fixtures/doubles/doubles.html:";
var templPath = "test/fixtures/doubles/javascripts/serversidetemplate.js:";
var scriptLN = [11,14,17,37];
var styleLN = [20,23,26];
var eventLN = [30,31,32,33];
var evalLN = [38,39];
var templLN = [2,3,4,5];
exec('grunt makecsp:doubles', execOptions, function(error, stdout){
var actual = grunt.file.readJSON('tmp/doubles.json');
test.deepEqual(actual, expected, 'Should create the correct tmp/doubles.json file without doubles.');
stdout.split(/\r?\n/).forEach(function(line){
if(line.indexOf("WARNING:") > -1){
nbOfWarnings++;
};
if(line.indexOf("http://isup.me,http://isup.me,http://isup.me") > -1){
isupWarn = true;
}
if(line.indexOf("javascript:alert(") > -1){
jsurlWarn = true;
}
scriptLN.forEach(function(ln){
if(line.indexOf(doublesPath+ln) > -1){
scriptWarns++;
}
});
styleLN.forEach(function(ln){
if(line.indexOf(doublesPath+ln) > -1){
styleWarns++;
}
});
eventLN.forEach(function(ln){
if(line.indexOf(doublesPath+ln) > -1){
eventWarns++;
}
});
evalLN.forEach(function(ln){
if(line.indexOf(doublesPath+ln) > -1){
evalWarns++;
}
});
templLN.forEach(function(ln){
if(line.indexOf(templPath+ln) > -1){
templateWarn++;
}
});
});
test.equal(nbOfWarnings, expectedNbOfWarnings, 'There should be '+expectedNbOfWarnings+' occurences of "WARNING:" ');
test.ok(isupWarn, "There should be a warning for http usage of isup.me");
test.ok(jsurlWarn, "There should be a warning for javascript url usage.");
test.equal(scriptWarns, scriptLN.length, 'There should be ' + scriptLN.length +' script warnings for lines: ' + scriptLN);
test.equal(styleWarns, styleLN.length, 'There should be ' + styleLN.length +' style warnings for lines: ' + styleLN);
test.equal(eventWarns, eventLN.length, 'There should be ' + eventLN.length +' inline event warnings for lines: ' + eventLN);
test.equal(evalWarns, evalLN.length, 'There should be ' + evalLN.length +' inline eval warnings for lines: ' + evalLN);
test.equal(templateWarn, templLN.length, 'There should be ' + templLN.length +' server-side template engine warnings for lines: ' + templLN);
test.done();
});
},
sae: function(test){
test.expect(1);
var expected = grunt.file.readJSON('test/expected/sae_csp.json');
exec('grunt makecsp:sae', execOptions, function(error, stdout){
var actual = grunt.file.readJSON('/vagrant/sae-server/csp.json');
test.deepEqual(actual, expected, 'Should create the correct csp.json file in /vagrant/sae-server/csp.json.');
test.done();
});
}
};
| {'content_hash': '58fd84369d01b1962cb8c513bb9c1a50', 'timestamp': '', 'source': 'github', 'line_count': 123, 'max_line_length': 143, 'avg_line_length': 34.3739837398374, 'alnum_prop': 0.6688741721854304, 'repo_name': 'dietercastel/grunt-csp-express', 'id': '354502ef7b4544331e62aed1745a00bf78a2ca32', 'size': '4228', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'test/makecsp_test.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'JavaScript', 'bytes': '15158'}]} |
package org.apache.hadoop.yarn.server.resourcemanager.reservation;
import static org.junit.Assert.assertNotNull;
import static org.junit.Assert.assertNull;
import static org.junit.Assert.assertTrue;
import static org.mockito.ArgumentMatchers.any;
import static org.mockito.Mockito.mock;
import static org.mockito.Mockito.spy;
import static org.mockito.Mockito.when;
import java.util.Collections;
import java.util.concurrent.ConcurrentHashMap;
import java.util.concurrent.ConcurrentMap;
import org.apache.hadoop.conf.Configuration;
import org.apache.hadoop.security.AccessControlException;
import org.apache.hadoop.yarn.api.records.ApplicationId;
import org.apache.hadoop.yarn.api.records.ReservationId;
import org.apache.hadoop.yarn.server.resourcemanager.RMContext;
import org.apache.hadoop.yarn.server.resourcemanager.reservation.exceptions.PlanningException;
import org.apache.hadoop.yarn.server.resourcemanager.reservation.planning.ReservationAgent;
import org.apache.hadoop.yarn.server.resourcemanager.rmapp.RMApp;
import org.apache.hadoop.yarn.server.resourcemanager.rmapp.attempt.RMAppAttempt;
import org.apache.hadoop.yarn.server.resourcemanager.scheduler.Queue;
import org.apache.hadoop.yarn.server.resourcemanager.scheduler.capacity.CSQueue;
import org.apache.hadoop.yarn.server.resourcemanager.scheduler.capacity.CapacityScheduler;
import org.apache.hadoop.yarn.server.resourcemanager.scheduler.capacity.CapacitySchedulerConfiguration;
import org.apache.hadoop.yarn.server.resourcemanager.scheduler.capacity.CapacitySchedulerContext;
import org.apache.hadoop.yarn.server.resourcemanager.scheduler.capacity.TestUtils;
import org.apache.hadoop.yarn.server.resourcemanager.security.RMContainerTokenSecretManager;
import org.apache.hadoop.yarn.server.security.ApplicationACLsManager;
import org.apache.hadoop.yarn.util.Clock;
import org.apache.hadoop.yarn.util.resource.DefaultResourceCalculator;
import org.apache.hadoop.yarn.util.resource.Resources;
import org.junit.After;
import org.junit.Assert;
import org.junit.Before;
import org.junit.Rule;
import org.junit.Test;
import org.junit.rules.TestName;
import org.mockito.ArgumentMatchers;
import org.mockito.Mockito;
public class TestCapacitySchedulerPlanFollower extends
TestSchedulerPlanFollowerBase {
private RMContext rmContext;
private RMContext spyRMContext;
private CapacitySchedulerContext csContext;
private CapacityScheduler cs;
@Rule
public TestName name = new TestName();
@Before
public void setUp() throws Exception {
CapacityScheduler spyCs = new CapacityScheduler();
cs = spy(spyCs);
scheduler = cs;
rmContext = TestUtils.getMockRMContext();
spyRMContext = spy(rmContext);
ConcurrentMap<ApplicationId, RMApp> spyApps =
spy(new ConcurrentHashMap<ApplicationId, RMApp>());
RMApp rmApp = mock(RMApp.class);
RMAppAttempt rmAppAttempt = mock(RMAppAttempt.class);
when(rmApp.getRMAppAttempt(any()))
.thenReturn(rmAppAttempt);
when(rmApp.getCurrentAppAttempt()).thenReturn(rmAppAttempt);
Mockito.doReturn(rmApp)
.when(spyApps).get(ArgumentMatchers.<ApplicationId>any());
Mockito.doReturn(true)
.when(spyApps).containsKey(ArgumentMatchers.<ApplicationId>any());
when(spyRMContext.getRMApps()).thenReturn(spyApps);
when(spyRMContext.getScheduler()).thenReturn(scheduler);
CapacitySchedulerConfiguration csConf =
new CapacitySchedulerConfiguration();
ReservationSystemTestUtil.setupQueueConfiguration(csConf);
cs.setConf(csConf);
csContext = mock(CapacitySchedulerContext.class);
when(csContext.getConfiguration()).thenReturn(csConf);
when(csContext.getConf()).thenReturn(csConf);
when(csContext.getMinimumResourceCapability()).thenReturn(minAlloc);
when(csContext.getMaximumResourceCapability()).thenReturn(maxAlloc);
when(csContext.getClusterResource()).thenReturn(
Resources.createResource(100 * 16 * GB, 100 * 32));
when(scheduler.getClusterResource()).thenReturn(
Resources.createResource(125 * GB, 125));
when(csContext.getResourceCalculator()).thenReturn(
new DefaultResourceCalculator());
RMContainerTokenSecretManager containerTokenSecretManager =
new RMContainerTokenSecretManager(csConf);
containerTokenSecretManager.rollMasterKey();
when(csContext.getContainerTokenSecretManager()).thenReturn(
containerTokenSecretManager);
cs.setRMContext(spyRMContext);
cs.init(csConf);
cs.start();
setupPlanFollower();
}
private void setupPlanFollower() throws Exception {
mClock = mock(Clock.class);
mAgent = mock(ReservationAgent.class);
String reservationQ =
ReservationSystemTestUtil.getFullReservationQueueName();
CapacitySchedulerConfiguration csConf = cs.getConfiguration();
csConf.setReservationWindow(reservationQ, 20L);
csConf.setMaximumCapacity(reservationQ, 40);
csConf.setAverageCapacity(reservationQ, 20);
policy.init(reservationQ, csConf);
}
@Test
public void testWithMoveOnExpiry() throws PlanningException,
InterruptedException, AccessControlException {
// invoke plan follower test with move
testPlanFollower(true);
}
@Test
public void testWithKillOnExpiry() throws PlanningException,
InterruptedException, AccessControlException {
// invoke plan follower test with kill
testPlanFollower(false);
}
@Override
protected void verifyCapacity(Queue defQ) {
CSQueue csQueue = (CSQueue) defQ;
assertTrue(csQueue.getCapacity() > 0.9);
}
@Override
protected void checkDefaultQueueBeforePlanFollowerRun(){
Queue defQ = getDefaultQueue();
Assert.assertEquals(0, getNumberOfApplications(defQ));
Assert.assertNotNull(defQ);
}
@Override
protected Queue getDefaultQueue() {
return cs.getQueue("dedicated" + ReservationConstants.DEFAULT_QUEUE_SUFFIX);
}
@Override
protected int getNumberOfApplications(Queue queue) {
CSQueue csQueue = (CSQueue) queue;
int numberOfApplications = csQueue.getNumApplications();
return numberOfApplications;
}
@Override
protected CapacitySchedulerPlanFollower createPlanFollower() {
CapacitySchedulerPlanFollower planFollower =
new CapacitySchedulerPlanFollower();
planFollower.init(mClock, scheduler, Collections.singletonList(plan));
return planFollower;
}
@Override
protected void assertReservationQueueExists(ReservationId r) {
CSQueue q = cs.getQueue(r.toString());
assertNotNull(q);
}
@Override
protected void assertReservationQueueExists(ReservationId r2,
double expectedCapacity, double expectedMaxCapacity) {
CSQueue q = cs.getQueue(r2.toString());
assertNotNull(q);
Assert.assertEquals(expectedCapacity, q.getCapacity(), 0.01);
Assert.assertEquals(expectedMaxCapacity, q.getMaximumCapacity(), 1.0);
}
@Override
protected void assertReservationQueueDoesNotExist(ReservationId r2) {
CSQueue q2 = cs.getQueue(r2.toString());
assertNull(q2);
}
public static ApplicationACLsManager mockAppACLsManager() {
Configuration conf = new Configuration();
return new ApplicationACLsManager(conf);
}
@After
public void tearDown() throws Exception {
if (scheduler != null) {
cs.stop();
}
}
protected Queue getReservationQueue(String reservationId) {
return cs.getQueue(reservationId);
}
}
| {'content_hash': 'dc559f1aaeb60ae17c27eb4c5b2626ee', 'timestamp': '', 'source': 'github', 'line_count': 205, 'max_line_length': 103, 'avg_line_length': 36.11707317073171, 'alnum_prop': 0.7728254997298758, 'repo_name': 'JingchengDu/hadoop', 'id': 'b4ad8be8587f981eb7f904dd089cd3e517bd2034', 'size': '8210', 'binary': False, 'copies': '10', 'ref': 'refs/heads/trunk', 'path': 'hadoop-yarn-project/hadoop-yarn/hadoop-yarn-server/hadoop-yarn-server-resourcemanager/src/test/java/org/apache/hadoop/yarn/server/resourcemanager/reservation/TestCapacitySchedulerPlanFollower.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '78534'}, {'name': 'C', 'bytes': '2024573'}, {'name': 'C++', 'bytes': '3071238'}, {'name': 'CMake', 'bytes': '145545'}, {'name': 'CSS', 'bytes': '94990'}, {'name': 'Dockerfile', 'bytes': '4613'}, {'name': 'HTML', 'bytes': '222473'}, {'name': 'Handlebars', 'bytes': '207062'}, {'name': 'Java', 'bytes': '97192222'}, {'name': 'JavaScript', 'bytes': '1274987'}, {'name': 'Python', 'bytes': '21624'}, {'name': 'SCSS', 'bytes': '23607'}, {'name': 'Shell', 'bytes': '532475'}, {'name': 'TLA', 'bytes': '14997'}, {'name': 'TSQL', 'bytes': '17801'}, {'name': 'TeX', 'bytes': '19322'}, {'name': 'XSLT', 'bytes': '18026'}]} |
package floobits.common.jgit.fnmatch;
final class CharacterHead extends AbstractHead {
private final char expectedCharacter;
protected CharacterHead(final char expectedCharacter) {
super(false);
this.expectedCharacter = expectedCharacter;
}
@Override
protected final boolean matches(final char c) {
return c == expectedCharacter;
}
}
| {'content_hash': '88fd699770c48e18a235a454a984e3f1', 'timestamp': '', 'source': 'github', 'line_count': 18, 'max_line_length': 56, 'avg_line_length': 19.555555555555557, 'alnum_prop': 0.7755681818181818, 'repo_name': 'Floobits/eclipse', 'id': '49b56ddf0c51fa216d10b0fe40d0a3b181f17d74', 'size': '2379', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'src/floobits/common/jgit/fnmatch/CharacterHead.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Java', 'bytes': '346473'}]} |
package org.apache.skywalking.apm.plugin.vertx3;
import io.vertx.core.http.HttpClientRequest;
import org.apache.skywalking.apm.agent.core.context.CarrierItem;
import org.apache.skywalking.apm.agent.core.context.ContextCarrier;
import org.apache.skywalking.apm.agent.core.context.ContextManager;
import org.apache.skywalking.apm.agent.core.context.tag.Tags;
import org.apache.skywalking.apm.agent.core.context.trace.AbstractSpan;
import org.apache.skywalking.apm.agent.core.context.trace.SpanLayer;
import org.apache.skywalking.apm.agent.core.plugin.interceptor.enhance.EnhancedInstance;
import org.apache.skywalking.apm.agent.core.plugin.interceptor.enhance.InstanceConstructorInterceptor;
import org.apache.skywalking.apm.agent.core.plugin.interceptor.enhance.InstanceMethodsAroundInterceptor;
import org.apache.skywalking.apm.agent.core.plugin.interceptor.enhance.MethodInterceptResult;
import org.apache.skywalking.apm.network.trace.component.ComponentsDefine;
import java.lang.reflect.Method;
public class HttpClientRequestImplInterceptor implements InstanceMethodsAroundInterceptor {
static class HttpClientRequestContext {
String remotePeer;
boolean usingWebClient;
VertxContext vertxContext;
boolean sent;
HttpClientRequestContext(String remotePeer) {
this.remotePeer = remotePeer;
}
}
public static class Version30XTo33XConstructorInterceptor implements InstanceConstructorInterceptor {
@Override
public void onConstruct(EnhancedInstance objInst, Object[] allArguments) {
String host = (String) allArguments[2];
int port = (Integer) allArguments[3];
objInst.setSkyWalkingDynamicField(new HttpClientRequestContext(host + ":" + port));
}
}
public static class Version34XTo37XConstructorInterceptor implements InstanceConstructorInterceptor {
@Override
public void onConstruct(EnhancedInstance objInst, Object[] allArguments) {
String host = (String) allArguments[3];
int port = (Integer) allArguments[4];
objInst.setSkyWalkingDynamicField(new HttpClientRequestContext(host + ":" + port));
}
}
public static class Version38PlusConstructorInterceptor implements InstanceConstructorInterceptor {
@Override
public void onConstruct(EnhancedInstance objInst, Object[] allArguments) {
String host = (String) allArguments[4];
int port = (Integer) allArguments[5];
objInst.setSkyWalkingDynamicField(new HttpClientRequestContext(host + ":" + port));
}
}
@Override
public void beforeMethod(EnhancedInstance objInst, Method method, Object[] allArguments, Class<?>[] argumentsTypes,
MethodInterceptResult result) {
HttpClientRequestContext requestContext = (HttpClientRequestContext) objInst.getSkyWalkingDynamicField();
if (!requestContext.sent) {
HttpClientRequest request = (HttpClientRequest) objInst;
ContextCarrier contextCarrier = new ContextCarrier();
AbstractSpan span = ContextManager.createExitSpan(toPath(request.uri()), contextCarrier,
requestContext.remotePeer);
span.setComponent(ComponentsDefine.VERTX);
SpanLayer.asHttp(span);
Tags.HTTP.METHOD.set(span, request.method().toString());
Tags.URL.set(span, request.uri());
CarrierItem next = contextCarrier.items();
while (next.hasNext()) {
next = next.next();
request.headers().add(next.getHeadKey(), next.getHeadValue());
}
requestContext.vertxContext = new VertxContext(ContextManager.capture(), span.prepareForAsync());
}
}
@Override
public Object afterMethod(EnhancedInstance objInst, Method method, Object[] allArguments, Class<?>[] argumentsTypes,
Object ret) {
HttpClientRequestContext requestContext = (HttpClientRequestContext) objInst.getSkyWalkingDynamicField();
if (!requestContext.sent) {
requestContext.sent = true;
ContextManager.stopSpan();
}
return ret;
}
@Override
public void handleMethodException(EnhancedInstance objInst, Method method, Object[] allArguments,
Class<?>[] argumentsTypes, Throwable t) {
ContextManager.activeSpan().log(t);
}
private static String toPath(String uri) {
int index = uri.indexOf("?");
if (index > -1) {
return uri.substring(0, index);
} else {
return uri;
}
}
}
| {'content_hash': '50366baee8e1e8c2c18f473f511f2064', 'timestamp': '', 'source': 'github', 'line_count': 108, 'max_line_length': 120, 'avg_line_length': 43.74074074074074, 'alnum_prop': 0.6860711261642676, 'repo_name': 'wu-sheng/sky-walking', 'id': 'd28c9f1a32aa2d3fcd6e7ca77bd68ae72034f817', 'size': '5528', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'apm-sniffer/apm-sdk-plugin/vertx-plugins/vertx-core-3.x-plugin/src/main/java/org/apache/skywalking/apm/plugin/vertx3/HttpClientRequestImplInterceptor.java', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
<?php
class Styles_Child_Theme extends Styles_Child_Updatable {
var $template;
var $styles_css;
public function __construct( $args ) {
parent::__construct( $args );
$this->template = str_replace( ' ', '-', strtolower( $this->item_name ) );
$this->styles_css = dirname( $this->plugin_file ) . '/style.css';
$this->plugin_theme_name = trim( str_replace( 'Styles:', '', $this->name ) );
$this->theme = wp_get_theme();
add_filter( 'styles_css_output', array( $this, 'styles_css_output' ) );
}
public function is_target_parent_or_child_theme_active() {
return ( $this->is_target_theme_active() || $this->is_target_parent_theme_active() );
}
public function is_target_parent_theme_active() {
if ( !is_a( $this->theme->parent() , 'WP_Theme') ) { return false; }
// Do parent or child theme header name == Styles plugin "Style Item" header?
// WARNING: Don't use this option. It's likely to change.
if ( $this->theme_name_equals_plugin_item_name( $this->theme->parent() ) ) { return true; }
// Do parent or child theme header name == Styles plugin header name?
if ( $this->theme_name_equals_plugin_name( $this->theme->parent() ) ) { return true; }
// Does the parent or child directory name == Styles directory name?
if ( $this->theme_directory_name_equals_plugin_directory_name( $this->theme->parent() ) ) { return true; }
return false;
}
public function is_target_theme_active() {
// Do parent or child theme header name == Styles plugin "Style Item" header?
// WARNING: Don't use this option. It's likely to change.
if ( $this->theme_name_equals_plugin_item_name( $this->theme ) ) { return true; }
// Do parent or child theme header name == Styles plugin header name?
if ( $this->theme_name_equals_plugin_name( $this->theme ) ) { return true; }
// Does the parent or child directory name == Styles directory name?
if ( $this->theme_directory_name_equals_plugin_directory_name( $this->theme ) ) { return true; }
return false;
}
/**
* Do parent or child theme header name == Styles plugin "Style Item" header?
* (Case insensitive)
*
* For example:
* Theme Name: Some Parent or Child Theme
* Styles Item: Some Parent or Child Theme
*
* This is an override for **weird edge cases** where the Styles plugin name
* or folder name can't match the theme name or folder name.
*
* Warning: Don't use this. It's likely to change.
*/
public function theme_name_equals_plugin_item_name( $theme ) {
if ( !is_a( $theme, 'WP_Theme') ) { return false; }
// Strip spacing and special characters in theme names
// Allows "Twenty Twelve" to match "TwentyTwelve"
$santatized_item_name = $this->sanatize_name( $this->item_name );
$santatized_theme_name = $this->sanatize_name( $theme->get('Name') );
if ( 0 === strcasecmp( $santatized_item_name, $santatized_theme_name ) ) { return true; }
return false;
}
/**
* Do parent or child theme header name == Styles plugin header name?
* (Case insensitive)
*
* For example:
* Theme Name: Some Parent or Child Theme
* Plugin Name: Styles: Some Parent or Child Theme
*
* ...would return true.
*
* "Theme Name" is in the theme header.
* "Plugin Name" is in the Styles plugin header.
*/
public function theme_name_equals_plugin_name( $theme ) {
if ( !is_a( $theme, 'WP_Theme') ) { return false; }
// Strip spacing and special characters in theme names
// Allows "Twenty Twelve" to match "TwentyTwelve"
$santatized_plugin_name = $this->sanatize_name( $this->plugin_theme_name );
$santatized_theme_name = $this->sanatize_name( $theme->get('Name') );
if ( 0 === strcasecmp( $santatized_plugin_name, $santatized_theme_name ) ) { return true; }
return false;
}
/**
* Does the parent or child directory name == Styles directory name?
* (Case insensitive)
*
* For example:
* Theme directory: some-parent-or-child-theme
* Plugin directory: styles-some-parent-or-child-theme
*/
public function theme_directory_name_equals_plugin_directory_name( $theme ) {
if ( !is_a( $theme, 'WP_Theme') ) { return false; }
if ( 0 === strcasecmp( $this->get_plugin_directory_name(), $theme->stylesheet ) ) { return true; }
return false;
}
public function get_plugin_directory_name() {
if ( isset( $this->plugin_directory_name ) ) {
return $this->plugin_directory_name;
}
$plugin_directory_name = basename( dirname( $this->plugin_file ) );
// Strip 'styles-' from the plugin directory name
$remove = 'styles-';
if ( $remove == strtolower( substr($plugin_directory_name, 0, strlen( $remove ) ) ) ) {
$plugin_directory_name = substr($plugin_directory_name, strlen( $remove ) );
}
$this->plugin_directory_name = $plugin_directory_name;
return $this->plugin_directory_name;
}
public function sanatize_name( $name ) {
return preg_replace( '/[^a-zA-Z0-9]/', '', $name );
}
public function get_json_path() {
if ( $this->is_target_parent_or_child_theme_active() ) {
$json_file = dirname( $this->plugin_file ) . '/customize.json';
return $json_file;
}else {
return false;
}
}
/**
* If styles.css exists in the plugin folder, prepend it to final CSS output
*/
public function styles_css_output( $css ) {
if ( $this->is_target_parent_or_child_theme_active() && file_exists( $this->styles_css ) ) {
$css = file_get_contents( $this->styles_css ) . $css;
}
return $css;
}
} | {'content_hash': '70c61452fec39d0a0d76d9bbdcc3f037', 'timestamp': '', 'source': 'github', 'line_count': 158, 'max_line_length': 108, 'avg_line_length': 34.360759493670884, 'alnum_prop': 0.6553693129489777, 'repo_name': 'nl-hugo/cornetrecruitment', 'id': '326c1432678d9c4b413e3c66e3e70cdd6d8f7e8a', 'size': '5429', 'binary': False, 'copies': '7', 'ref': 'refs/heads/master', 'path': 'blog/wp-content/plugins/styles/classes/styles-child-theme.php', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'CSS', 'bytes': '113984'}, {'name': 'HTML', 'bytes': '21410'}, {'name': 'JavaScript', 'bytes': '49777'}, {'name': 'PHP', 'bytes': '323749'}]} |
package org.apache.hadoop.mapred;
import java.io.File;
import java.io.FileOutputStream;
import java.io.IOException;
import java.io.PrintWriter;
import java.util.Properties;
import java.util.Set;
import java.util.TreeSet;
import javax.security.auth.login.LoginException;
import junit.framework.TestCase;
import org.apache.commons.logging.Log;
import org.apache.commons.logging.LogFactory;
import org.apache.hadoop.conf.Configuration;
import org.apache.hadoop.examples.SleepJob;
import org.apache.hadoop.fs.FileSystem;
import org.apache.hadoop.fs.Path;
import org.apache.hadoop.hdfs.MiniDFSCluster;
import org.apache.hadoop.security.UnixUserGroupInformation;
import org.apache.hadoop.security.UserGroupInformation;
public class TestQueueManager extends TestCase {
private static final Log LOG = LogFactory.getLog(TestQueueManager.class);
private MiniDFSCluster miniDFSCluster;
private MiniMRCluster miniMRCluster;
public void testDefaultQueueConfiguration() {
JobConf conf = new JobConf();
QueueManager qMgr = new QueueManager(conf);
Set<String> expQueues = new TreeSet<String>();
expQueues.add("default");
verifyQueues(expQueues, qMgr.getQueues());
// pass true so it will fail if the key is not found.
assertFalse(conf.getBoolean("mapred.acls.enabled", true));
}
public void testMultipleQueues() {
JobConf conf = new JobConf();
conf.set("mapred.queue.names", "q1,q2,Q3");
QueueManager qMgr = new QueueManager(conf);
Set<String> expQueues = new TreeSet<String>();
expQueues.add("q1");
expQueues.add("q2");
expQueues.add("Q3");
verifyQueues(expQueues, qMgr.getQueues());
}
public void testSchedulerInfo() {
JobConf conf = new JobConf();
conf.set("mapred.queue.names", "qq1,qq2");
QueueManager qMgr = new QueueManager(conf);
qMgr.setSchedulerInfo("qq1", "queueInfoForqq1");
qMgr.setSchedulerInfo("qq2", "queueInfoForqq2");
assertEquals(qMgr.getSchedulerInfo("qq2"), "queueInfoForqq2");
assertEquals(qMgr.getSchedulerInfo("qq1"), "queueInfoForqq1");
}
public void testAllEnabledACLForJobSubmission() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-submit-job", "*");
verifyJobSubmission(conf, true);
}
public void testAllDisabledACLForJobSubmission() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-submit-job", "");
verifyJobSubmission(conf, false);
}
public void testUserDisabledACLForJobSubmission() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-submit-job",
"3698-non-existent-user");
verifyJobSubmission(conf, false);
}
public void testDisabledACLForNonDefaultQueue() throws IOException {
// allow everyone in default queue
JobConf conf = setupConf("mapred.queue.default.acl-submit-job", "*");
// setup a different queue
conf.set("mapred.queue.names", "default,q1");
// setup a different acl for this queue.
conf.set("mapred.queue.q1.acl-submit-job", "dummy-user");
// verify job submission to other queue fails.
verifyJobSubmission(conf, false, "q1");
}
public void testSubmissionToInvalidQueue() throws IOException{
JobConf conf = new JobConf();
conf.set("mapred.queue.names","default");
setUpCluster(conf);
String queueName = "q1";
try {
RunningJob rjob = submitSleepJob(1, 1, 100, 100, true, null, queueName);
} catch (IOException ioe) {
assertTrue(ioe.getMessage().contains("Queue \"" + queueName + "\" does not exist"));
return;
} finally {
tearDownCluster();
}
fail("Job submission to invalid queue job shouldnot complete , it should fail with proper exception ");
}
public void testEnabledACLForNonDefaultQueue() throws IOException,
LoginException {
// login as self...
UserGroupInformation ugi = UnixUserGroupInformation.login();
String userName = ugi.getUserName();
// allow everyone in default queue
JobConf conf = setupConf("mapred.queue.default.acl-submit-job", "*");
// setup a different queue
conf.set("mapred.queue.names", "default,q2");
// setup a different acl for this queue.
conf.set("mapred.queue.q2.acl-submit-job", userName);
// verify job submission to other queue fails.
verifyJobSubmission(conf, true, "q2");
}
public void testUserEnabledACLForJobSubmission()
throws IOException, LoginException {
// login as self...
UserGroupInformation ugi = UnixUserGroupInformation.login();
String userName = ugi.getUserName();
JobConf conf = setupConf("mapred.queue.default.acl-submit-job",
"3698-junk-user," + userName
+ " 3698-junk-group1,3698-junk-group2");
verifyJobSubmission(conf, true);
}
public void testGroupsEnabledACLForJobSubmission()
throws IOException, LoginException {
// login as self, get one group, and add in allowed list.
UserGroupInformation ugi = UnixUserGroupInformation.login();
String[] groups = ugi.getGroupNames();
assertTrue(groups.length > 0);
JobConf conf = setupConf("mapred.queue.default.acl-submit-job",
"3698-junk-user1,3698-junk-user2 "
+ groups[groups.length-1]
+ ",3698-junk-group");
verifyJobSubmission(conf, true);
}
public void testAllEnabledACLForJobKill() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-administer-jobs", "*");
verifyJobKill(conf, true);
}
public void testAllDisabledACLForJobKill() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-administer-jobs", "");
verifyJobKillAsOtherUser(conf, false, "dummy-user,dummy-user-group");
}
public void testOwnerAllowedForJobKill() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-administer-jobs",
"junk-user");
verifyJobKill(conf, true);
}
public void testUserDisabledACLForJobKill() throws IOException {
//setup a cluster allowing a user to submit
JobConf conf = setupConf("mapred.queue.default.acl-administer-jobs",
"dummy-user");
verifyJobKillAsOtherUser(conf, false, "dummy-user,dummy-user-group");
}
public void testUserEnabledACLForJobKill() throws IOException,
LoginException {
// login as self...
UserGroupInformation ugi = UnixUserGroupInformation.login();
String userName = ugi.getUserName();
JobConf conf = setupConf("mapred.queue.default.acl-administer-jobs",
"dummy-user,"+userName);
verifyJobKillAsOtherUser(conf, true, "dummy-user,dummy-user-group");
}
public void testUserDisabledForJobPriorityChange() throws IOException {
JobConf conf = setupConf("mapred.queue.default.acl-administer-jobs",
"junk-user");
verifyJobPriorityChangeAsOtherUser(conf, false,
"junk-user,junk-user-group");
}
/**
* Test to verify refreshing of queue properties by using MRAdmin tool.
*
* @throws Exception
*/
public void testACLRefresh() throws Exception {
String queueConfigPath =
System.getProperty("test.build.extraconf", "build/test/extraconf");
File queueConfigFile =
new File(queueConfigPath, QueueManager.QUEUE_ACLS_FILE_NAME);
File hadoopConfigFile = new File(queueConfigPath, "mapred-site.xml");
try {
//Setting up default mapred-site.xml
Properties hadoopConfProps = new Properties();
//these properties should be retained.
hadoopConfProps.put("mapred.queue.names", "default,q1,q2");
hadoopConfProps.put("mapred.acls.enabled", "true");
//These property should always be overridden
hadoopConfProps.put("mapred.queue.default.acl-submit-job", "u1");
hadoopConfProps.put("mapred.queue.q1.acl-submit-job", "u2");
hadoopConfProps.put("mapred.queue.q2.acl-submit-job", "u1");
UtilsForTests.setUpConfigFile(hadoopConfProps, hadoopConfigFile);
//Actual property which would be used.
Properties queueConfProps = new Properties();
queueConfProps.put("mapred.queue.default.acl-submit-job", " ");
//Writing out the queue configuration file.
UtilsForTests.setUpConfigFile(queueConfProps, queueConfigFile);
//Create a new configuration to be used with QueueManager
JobConf conf = new JobConf();
QueueManager queueManager = new QueueManager(conf);
UserGroupInformation ugi = UnixUserGroupInformation.getCurrentUGI();
//Job Submission should fail because ugi to be used is set to blank.
assertFalse("User Job Submission Succeeded before refresh.",
queueManager.hasAccess("default", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertFalse("User Job Submission Succeeded before refresh.",
queueManager.hasAccess("q1", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertFalse("User Job Submission Succeeded before refresh.",
queueManager.hasAccess("q2", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
//Test job submission as alternate user.
Configuration alternateUserConfig = new Configuration();
alternateUserConfig.set("hadoop.job.ugi","u1,users");
UserGroupInformation alternateUgi =
UserGroupInformation.readFrom(alternateUserConfig);
assertTrue("Alternate User Job Submission failed before refresh.",
queueManager.hasAccess("q2", QueueManager.QueueOperation.
SUBMIT_JOB, alternateUgi));
//Set acl for the current user.
queueConfProps.put("mapred.queue.default.acl-submit-job", ugi.getUserName());
queueConfProps.put("mapred.queue.q1.acl-submit-job", ugi.getUserName());
queueConfProps.put("mapred.queue.q2.acl-submit-job", ugi.getUserName());
//write out queue-acls.xml.
UtilsForTests.setUpConfigFile(queueConfProps, queueConfigFile);
//refresh configuration
queueManager.refreshAcls(conf);
//Submission should succeed
assertTrue("User Job Submission failed after refresh.",
queueManager.hasAccess("default", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertTrue("User Job Submission failed after refresh.",
queueManager.hasAccess("q1", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertTrue("User Job Submission failed after refresh.",
queueManager.hasAccess("q2", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertFalse("Alternate User Job Submission succeeded after refresh.",
queueManager.hasAccess("q2", QueueManager.QueueOperation.
SUBMIT_JOB, alternateUgi));
//delete the ACL file.
queueConfigFile.delete();
//rewrite the mapred-site.xml
hadoopConfProps.put("mapred.acls.enabled", "true");
hadoopConfProps.put("mapred.queue.default.acl-submit-job", ugi.getUserName());
UtilsForTests.setUpConfigFile(hadoopConfProps, hadoopConfigFile);
queueManager.refreshAcls(conf);
assertTrue("User Job Submission failed after refresh and no queue acls file.",
queueManager.hasAccess("default", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
} finally{
if(queueConfigFile.exists()) {
queueConfigFile.delete();
}
if(hadoopConfigFile.exists()) {
hadoopConfigFile.delete();
}
}
}
public void testQueueAclRefreshWithInvalidConfFile() throws IOException {
String queueConfigPath =
System.getProperty("test.build.extraconf", "build/test/extraconf");
File queueConfigFile =
new File(queueConfigPath, QueueManager.QUEUE_ACLS_FILE_NAME);
File hadoopConfigFile = new File(queueConfigPath, "hadoop-site.xml");
try {
// queue properties with which the cluster is started.
Properties hadoopConfProps = new Properties();
hadoopConfProps.put("mapred.queue.names", "default,q1,q2");
hadoopConfProps.put("mapred.acls.enabled", "true");
UtilsForTests.setUpConfigFile(hadoopConfProps, hadoopConfigFile);
//properties for mapred-queue-acls.xml
Properties queueConfProps = new Properties();
UserGroupInformation ugi = UnixUserGroupInformation.getCurrentUGI();
queueConfProps.put("mapred.queue.default.acl-submit-job", ugi.getUserName());
queueConfProps.put("mapred.queue.q1.acl-submit-job", ugi.getUserName());
queueConfProps.put("mapred.queue.q2.acl-submit-job", ugi.getUserName());
UtilsForTests.setUpConfigFile(queueConfProps, queueConfigFile);
Configuration conf = new JobConf();
QueueManager queueManager = new QueueManager(conf);
//Testing access to queue.
assertTrue("User Job Submission failed.",
queueManager.hasAccess("default", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertTrue("User Job Submission failed.",
queueManager.hasAccess("q1", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertTrue("User Job Submission failed.",
queueManager.hasAccess("q2", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
//Write out a new incomplete invalid configuration file.
PrintWriter writer = new PrintWriter(new FileOutputStream(queueConfigFile));
writer.println("<configuration>");
writer.println("<property>");
writer.flush();
writer.close();
try {
//Exception to be thrown by queue manager because configuration passed
//is invalid.
queueManager.refreshAcls(conf);
fail("Refresh of ACLs should have failed with invalid conf file.");
} catch (Exception e) {
}
assertTrue("User Job Submission failed after invalid conf file refresh.",
queueManager.hasAccess("default", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertTrue("User Job Submission failed after invalid conf file refresh.",
queueManager.hasAccess("q1", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
assertTrue("User Job Submission failed after invalid conf file refresh.",
queueManager.hasAccess("q2", QueueManager.QueueOperation.
SUBMIT_JOB, ugi));
} finally {
//Cleanup the configuration files in all cases
if(hadoopConfigFile.exists()) {
hadoopConfigFile.delete();
}
if(queueConfigFile.exists()) {
queueConfigFile.delete();
}
}
}
private JobConf setupConf(String aclName, String aclValue) {
JobConf conf = new JobConf();
conf.setBoolean("mapred.acls.enabled", true);
conf.set(aclName, aclValue);
return conf;
}
private void verifyQueues(Set<String> expectedQueues,
Set<String> actualQueues) {
assertEquals(expectedQueues.size(), actualQueues.size());
for (String queue : expectedQueues) {
assertTrue(actualQueues.contains(queue));
}
}
private void verifyJobSubmission(JobConf conf, boolean shouldSucceed)
throws IOException {
verifyJobSubmission(conf, shouldSucceed, "default");
}
private void verifyJobSubmission(JobConf conf, boolean shouldSucceed,
String queue) throws IOException {
setUpCluster(conf);
try {
runAndVerifySubmission(conf, shouldSucceed, queue, null);
} finally {
tearDownCluster();
}
}
private void runAndVerifySubmission(JobConf conf, boolean shouldSucceed,
String queue, String userInfo)
throws IOException {
try {
RunningJob rjob = submitSleepJob(1, 1, 100, 100, true, userInfo, queue);
if (shouldSucceed) {
assertTrue(rjob.isSuccessful());
} else {
fail("Job submission should have failed.");
}
} catch (IOException ioe) {
if (shouldSucceed) {
throw ioe;
} else {
LOG.info("exception while submitting job: " + ioe.getMessage());
assertTrue(ioe.getMessage().
contains("cannot perform operation " +
"SUBMIT_JOB on queue " + queue));
// check if the system directory gets cleaned up or not
JobTracker jobtracker = miniMRCluster.getJobTrackerRunner().getJobTracker();
Path sysDir = new Path(jobtracker.getSystemDir());
FileSystem fs = sysDir.getFileSystem(conf);
int size = fs.listStatus(sysDir).length;
while (size > 1) { // ignore the jobtracker.info file
System.out.println("Waiting for the job files in sys directory to be cleaned up");
UtilsForTests.waitFor(100);
size = fs.listStatus(sysDir).length;
}
}
} finally {
tearDownCluster();
}
}
private void verifyJobKill(JobConf conf, boolean shouldSucceed)
throws IOException {
setUpCluster(conf);
try {
RunningJob rjob = submitSleepJob(1, 1, 1000, 1000, false);
assertFalse(rjob.isComplete());
while(rjob.mapProgress() == 0.0f) {
try {
Thread.sleep(10);
} catch (InterruptedException ie) {
break;
}
}
rjob.killJob();
while(rjob.cleanupProgress() == 0.0f) {
try {
Thread.sleep(10);
} catch (InterruptedException ie) {
break;
}
}
if (shouldSucceed) {
assertTrue(rjob.isComplete());
} else {
fail("Job kill should have failed.");
}
} catch (IOException ioe) {
if (shouldSucceed) {
throw ioe;
} else {
LOG.info("exception while submitting job: " + ioe.getMessage());
assertTrue(ioe.getMessage().
contains("cannot perform operation " +
"ADMINISTER_JOBS on queue default"));
}
} finally {
tearDownCluster();
}
}
private void verifyJobKillAsOtherUser(JobConf conf, boolean shouldSucceed,
String otherUserInfo)
throws IOException {
setUpCluster(conf);
try {
// submit a job as another user.
String userInfo = otherUserInfo;
RunningJob rjob = submitSleepJob(1, 1, 1000, 1000, false, userInfo);
assertFalse(rjob.isComplete());
//try to kill as self
try {
rjob.killJob();
if (!shouldSucceed) {
fail("should fail kill operation");
}
} catch (IOException ioe) {
if (shouldSucceed) {
throw ioe;
}
//verify it fails
LOG.info("exception while submitting job: " + ioe.getMessage());
assertTrue(ioe.getMessage().
contains("cannot perform operation " +
"ADMINISTER_JOBS on queue default"));
}
//wait for job to complete on its own
while (!rjob.isComplete()) {
try {
Thread.sleep(1000);
} catch (InterruptedException ie) {
break;
}
}
} finally {
tearDownCluster();
}
}
private void verifyJobPriorityChangeAsOtherUser(JobConf conf,
boolean shouldSucceed, String otherUserInfo)
throws IOException {
setUpCluster(conf);
try {
// submit job as another user.
String userInfo = otherUserInfo;
RunningJob rjob = submitSleepJob(1, 1, 1000, 1000, false, userInfo);
assertFalse(rjob.isComplete());
// try to change priority as self
try {
rjob.setJobPriority("VERY_LOW");
if (!shouldSucceed) {
fail("changing priority should fail.");
}
} catch (IOException ioe) {
//verify it fails
LOG.info("exception while submitting job: " + ioe.getMessage());
assertTrue(ioe.getMessage().
contains("cannot perform operation " +
"ADMINISTER_JOBS on queue default"));
}
//wait for job to complete on its own
while (!rjob.isComplete()) {
try {
Thread.sleep(1000);
} catch (InterruptedException ie) {
break;
}
}
} finally {
tearDownCluster();
}
}
private void setUpCluster(JobConf conf) throws IOException {
miniDFSCluster = new MiniDFSCluster(conf, 1, true, null);
FileSystem fileSys = miniDFSCluster.getFileSystem();
String namenode = fileSys.getUri().toString();
miniMRCluster = new MiniMRCluster(1, namenode, 3,
null, null, conf);
}
private void tearDownCluster() throws IOException {
if (miniMRCluster != null) { miniMRCluster.shutdown(); }
if (miniDFSCluster != null) { miniDFSCluster.shutdown(); }
}
private RunningJob submitSleepJob(int numMappers, int numReducers,
long mapSleepTime, long reduceSleepTime,
boolean shouldComplete)
throws IOException {
return submitSleepJob(numMappers, numReducers, mapSleepTime,
reduceSleepTime, shouldComplete, null);
}
private RunningJob submitSleepJob(int numMappers, int numReducers,
long mapSleepTime, long reduceSleepTime,
boolean shouldComplete, String userInfo)
throws IOException {
return submitSleepJob(numMappers, numReducers, mapSleepTime,
reduceSleepTime, shouldComplete, userInfo, null);
}
private RunningJob submitSleepJob(int numMappers, int numReducers,
long mapSleepTime, long reduceSleepTime,
boolean shouldComplete, String userInfo,
String queueName)
throws IOException {
JobConf clientConf = new JobConf();
clientConf.set("mapred.job.tracker", "localhost:"
+ miniMRCluster.getJobTrackerPort());
SleepJob job = new SleepJob();
job.setConf(clientConf);
clientConf = job.setupJobConf(numMappers, numReducers,
mapSleepTime, (int)mapSleepTime/100,
reduceSleepTime, (int)reduceSleepTime/100);
if (queueName != null) {
clientConf.setQueueName(queueName);
}
JobConf jc = new JobConf(clientConf);
if (userInfo != null) {
jc.set(UnixUserGroupInformation.UGI_PROPERTY_NAME, userInfo);
}
RunningJob rJob = null;
if (shouldComplete) {
rJob = JobClient.runJob(jc);
} else {
rJob = new JobClient(clientConf).submitJob(jc);
}
return rJob;
}
}
| {'content_hash': '1d5dcf5558cb5cded2ee5926d410e550', 'timestamp': '', 'source': 'github', 'line_count': 588, 'max_line_length': 110, 'avg_line_length': 39.454081632653065, 'alnum_prop': 0.635846372688478, 'repo_name': 'facebookarchive/hadoop-20', 'id': '910f90f0cdd23053215655b69297ad9d2f492b3d', 'size': '24005', 'binary': False, 'copies': '13', 'ref': 'refs/heads/master', 'path': 'src/test/org/apache/hadoop/mapred/TestQueueManager.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'AspectJ', 'bytes': '1817'}, {'name': 'C', 'bytes': '926657'}, {'name': 'C++', 'bytes': '812573'}, {'name': 'CSS', 'bytes': '39718'}, {'name': 'Java', 'bytes': '26603177'}, {'name': 'JavaScript', 'bytes': '392596'}, {'name': 'Objective-C', 'bytes': '118273'}, {'name': 'PHP', 'bytes': '152555'}, {'name': 'Perl', 'bytes': '142713'}, {'name': 'Python', 'bytes': '796073'}, {'name': 'Ruby', 'bytes': '28485'}, {'name': 'Shell', 'bytes': '1249546'}, {'name': 'Smalltalk', 'bytes': '56562'}, {'name': 'XSLT', 'bytes': '14484'}]} |
package model
import (
"fmt"
"k8s.io/kops/upup/pkg/fi"
"k8s.io/kops/upup/pkg/fi/nodeup/nodetasks"
"path/filepath"
)
// NetworkBuilder writes CNI assets
type NetworkBuilder struct {
*NodeupModelContext
}
var _ fi.ModelBuilder = &NetworkBuilder{}
func (b *NetworkBuilder) Build(c *fi.ModelBuilderContext) error {
var assetNames []string
networking := b.Cluster.Spec.Networking
if networking == nil || networking.Classic != nil {
} else if networking.Kubenet != nil {
assetNames = append(assetNames, "bridge", "host-local", "loopback")
} else if networking.External != nil {
// external is based on kubenet
assetNames = append(assetNames, "bridge", "host-local", "loopback")
} else if networking.CNI != nil || networking.Weave != nil || networking.Flannel != nil || networking.Calico != nil || networking.Canal != nil || networking.Kuberouter != nil {
assetNames = append(assetNames, "bridge", "host-local", "loopback", "ptp")
// Do we need tuning?
// TODO: Only when using flannel ?
assetNames = append(assetNames, "flannel")
} else if networking.Kopeio != nil {
// TODO combine with External
// Kopeio is based on kubenet / external
assetNames = append(assetNames, "bridge", "host-local", "loopback")
} else {
return fmt.Errorf("no networking mode set")
}
for _, assetName := range assetNames {
if err := b.addCNIBinAsset(c, assetName); err != nil {
return err
}
}
return nil
}
func (b *NetworkBuilder) addCNIBinAsset(c *fi.ModelBuilderContext, assetName string) error {
assetPath := ""
asset, err := b.Assets.Find(assetName, assetPath)
if err != nil {
return fmt.Errorf("error trying to locate asset %q: %v", assetName, err)
}
if asset == nil {
return fmt.Errorf("unable to locate asset %q", assetName)
}
t := &nodetasks.File{
Path: filepath.Join(b.CNIBinDir(), assetName),
Contents: asset,
Type: nodetasks.FileType_File,
Mode: s("0755"),
}
c.AddTask(t)
return nil
}
| {'content_hash': '84b784397e3f96c31305380d1ed809bd', 'timestamp': '', 'source': 'github', 'line_count': 71, 'max_line_length': 177, 'avg_line_length': 27.6056338028169, 'alnum_prop': 0.6821428571428572, 'repo_name': 'reactiveops/kops', 'id': '95311e05133e2e58a862a71fe34e115f442cb7f5', 'size': '2529', 'binary': False, 'copies': '4', 'ref': 'refs/heads/master', 'path': 'nodeup/pkg/model/network.go', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Go', 'bytes': '2862875'}, {'name': 'HCL', 'bytes': '222054'}, {'name': 'Makefile', 'bytes': '22216'}, {'name': 'Protocol Buffer', 'bytes': '611'}, {'name': 'Python', 'bytes': '15199'}, {'name': 'Ruby', 'bytes': '1027'}, {'name': 'Shell', 'bytes': '25759'}]} |
DIAGNOSTIC_TOOLTIP = "Diagnostic table tooltip"
DIFFERENCE_TOOLTIP = "Difference table tooltip"
PAYROLL_TOOLTIP = "Payroll info tooltip"
INCOME_TOOLTIP = "Income info tooltip"
BASE_TOOLTIP = "Base plan tooltip"
REFORM_TOOLTIP = "Reform plan tooltip"
EXPANDED_TOOLTIP = "Expanded income tooltip"
ADJUSTED_TOOLTIP = "Adjusted income tooltip"
INCOME_BINS_TOOLTIP = "Income bins tooltip"
INCOME_DECILES_TOOLTIP = "Income deciles tooltip"
| {'content_hash': 'b71888b9a9273c110db989e3cd852421', 'timestamp': '', 'source': 'github', 'line_count': 10, 'max_line_length': 49, 'avg_line_length': 43.4, 'alnum_prop': 0.7880184331797235, 'repo_name': 'zrisher/webapp-public', 'id': '53039a45819c26b9200edf2cd523cad64cff5521', 'size': '434', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'webapp/apps/taxbrain/constants.py', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '877372'}, {'name': 'HTML', 'bytes': '64722'}, {'name': 'JavaScript', 'bytes': '86106'}, {'name': 'Python', 'bytes': '406502'}, {'name': 'Shell', 'bytes': '17'}]} |
/*
MIT License http://www.opensource.org/licenses/mit-license.php
Author Tobias Koppers @sokra
*/
"use strict";
const ConcatSource = require("webpack-sources").ConcatSource;
const ModuleFilenameHelpers = require("./ModuleFilenameHelpers");
function wrapComment(str) {
if(!str.includes("\n")) return `/*! ${str} */`;
return `/*!\n * ${str.split("\n").join("\n * ")}\n */`;
}
class BannerPlugin {
constructor(options) {
if(arguments.length > 1)
throw new Error("BannerPlugin only takes one argument (pass an options object)");
if(typeof options === "string")
options = {
banner: options
};
this.options = options || {};
this.banner = this.options.raw ? options.banner : wrapComment(options.banner);
}
apply(compiler) {
let options = this.options;
let banner = this.banner;
compiler.plugin("compilation", (compilation) => {
compilation.plugin("optimize-chunk-assets", (chunks, callback) => {
chunks.forEach((chunk) => {
if(options.entryOnly && !chunk.isInitial()) return;
chunk.files
.filter(ModuleFilenameHelpers.matchObject.bind(undefined, options))
.forEach((file) =>
compilation.assets[file] = new ConcatSource(
banner, "\n", compilation.assets[file]
)
);
});
callback();
});
});
}
}
module.exports = BannerPlugin;
| {'content_hash': '14b83640a2ac8b47d2055ecb560bf17e', 'timestamp': '', 'source': 'github', 'line_count': 51, 'max_line_length': 84, 'avg_line_length': 26.07843137254902, 'alnum_prop': 0.6488721804511278, 'repo_name': 'A-HostMobile/MobileApp', 'id': '16566b23349dc052b772a2fe80241f942e1c2251', 'size': '1330', 'binary': False, 'copies': '28', 'ref': 'refs/heads/master', 'path': 'node_modules/webpack/lib/BannerPlugin.js', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '13353'}, {'name': 'C', 'bytes': '638'}, {'name': 'C#', 'bytes': '39190'}, {'name': 'C++', 'bytes': '217655'}, {'name': 'CSS', 'bytes': '98177'}, {'name': 'HTML', 'bytes': '30500'}, {'name': 'Java', 'bytes': '568515'}, {'name': 'JavaScript', 'bytes': '27484'}, {'name': 'Objective-C', 'bytes': '457829'}, {'name': 'QML', 'bytes': '2765'}, {'name': 'TypeScript', 'bytes': '39869'}]} |
/*jslint browser: true*/
/*global $, jQuery, alert, console*/
$(function () {
$('#main, #projects .wrapper').height($(window).height());
$(window).on('resize', function() {
$('#main, #projects .wrapper').height($(window).height());
});
}); | {'content_hash': '357a3eefcd533ef6530262508a86adc4', 'timestamp': '', 'source': 'github', 'line_count': 8, 'max_line_length': 66, 'avg_line_length': 32.375, 'alnum_prop': 0.5598455598455598, 'repo_name': 'JPedroMarques/SharpCalendar', 'id': 'd3e08e616df235526f5a985091c9fbf1f6a55572', 'size': '259', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'scripts/main.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '14347'}, {'name': 'HTML', 'bytes': '9689'}, {'name': 'JavaScript', 'bytes': '48419'}]} |
<?php
/**
* The template for displaying the footer.
*
* Contains the closing of the id=main div and all content after
*
* @package Minileven
*/
?>
</div><!-- #main -->
</div><!-- #page -->
<?php get_sidebar(); ?>
</div><!-- #wrapper -->
<?php
/**
* Fires before the Mobile Theme's <footer> tag.
*
* @module minileven
*
* @since 3.7.0
*/
do_action( 'jetpack_mobile_footer_before' );
?>
<footer id="colophon" role="contentinfo">
<div id="site-generator">
<?php
global $wp;
$current_url = trailingslashit( home_url( add_query_arg( array(), $wp->request ) ) );
?>
<a href="<?php echo $current_url . '?ak_action=reject_mobile'; ?>"><?php _e( 'View Full Site', 'jetpack' ); ?></a><br />
<?php
/**
* Fires after the View Full Site link in the Mobile Theme's footer.
*
* By default, a promo to download the native apps is added to this action.
*
* @module minileven
*
* @since 1.8.0
*/
do_action( 'wp_mobile_theme_footer' );
/**
* Fires before the credit links in the Mobile Theme's footer.
*
* @module minilven
*
* @since 1.8.0
*/
do_action( 'minileven_credits' );
?>
<a href="<?php echo esc_url( __( 'http://wordpress.org/', 'jetpack' ) ); ?>" target="_blank" title="<?php esc_attr_e( 'Semantic Personal Publishing Platform', 'jetpack' ); ?>" rel="generator"><?php printf( __( 'Proudly powered by %s', 'jetpack' ), 'WordPress' ); ?></a>
</div>
</footer><!-- #colophon -->
<?php wp_footer(); ?>
</body>
</html>
| {'content_hash': '205997b65690294efb73878816fea43c', 'timestamp': '', 'source': 'github', 'line_count': 66, 'max_line_length': 271, 'avg_line_length': 22.87878787878788, 'alnum_prop': 0.5788079470198676, 'repo_name': 'neilmuralee/base-theme', 'id': '762fd73393f0235799c3282d5022b198a978e08e', 'size': '1510', 'binary': False, 'copies': '54', 'ref': 'refs/heads/master', 'path': 'plugins/jetpack/modules/minileven/theme/pub/minileven/footer.php', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '1052826'}, {'name': 'HTML', 'bytes': '34569'}, {'name': 'JavaScript', 'bytes': '1218149'}, {'name': 'PHP', 'bytes': '5299864'}, {'name': 'PLSQL', 'bytes': '788942'}, {'name': 'Smarty', 'bytes': '33'}]} |
SYNONYM
#### According to
The Catalogue of Life, 3rd January 2011
#### Published in
null
#### Original name
null
### Remarks
null | {'content_hash': '5d7c453142d341e6c186446cad4e96fd', 'timestamp': '', 'source': 'github', 'line_count': 13, 'max_line_length': 39, 'avg_line_length': 10.23076923076923, 'alnum_prop': 0.6917293233082706, 'repo_name': 'mdoering/backbone', 'id': 'b918eccb6f20e956211e36d1e20f81ac71bd752c', 'size': '192', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'life/Plantae/Magnoliophyta/Magnoliopsida/Lamiales/Gesneriaceae/Besleria/Besleria lutea/ Syn. Besleria lutea intermedia/README.md', 'mode': '33188', 'license': 'apache-2.0', 'language': []} |
IF(WIN32)
# JW tested with gsl-1.8, Windows XP, MSVS 7.1
SET(GSL_POSSIBLE_ROOT_DIRS
${GSL_ROOT_DIR}
$ENV{GSL_ROOT_DIR}
${GSL_DIR}
${GSL_HOME}
"/data/jqdu/libs/lib"
"/data/jqdu/libs"
$ENV{GSL_DIR}
$ENV{GSL_HOME}
$ENV{EXTRA}
"C:/home/jw/source2/gsl-1.8"
)
FIND_PATH(GSL_INCLUDE_DIR
NAMES gsl/gsl_cdf.h gsl/gsl_randist.h
PATHS ${GSL_POSSIBLE_ROOT_DIRS}
PATH_SUFFIXES include
DOC "GSL header include dir"
)
FIND_LIBRARY(GSL_GSL_LIBRARY
NAMES gsl libgsl
PATHS ${GSL_POSSIBLE_ROOT_DIRS}
PATH_SUFFIXES lib
DOC "GSL library dir" )
FIND_LIBRARY(GSL_GSLCBLAS_LIBRARY
NAMES gslcblas libgslcblas
PATHS ${GSL_POSSIBLE_ROOT_DIRS}
PATH_SUFFIXES lib
DOC "GSL cblas library dir" )
SET(GSL_LIBRARIES ${GSL_GSL_LIBRARY})
#MESSAGE("DBG\n"
# "GSL_GSL_LIBRARY=${GSL_GSL_LIBRARY}\n"
# "GSL_GSLCBLAS_LIBRARY=${GSL_GSLCBLAS_LIBRARY}\n"
# "GSL_LIBRARIES=${GSL_LIBRARIES}")
ELSE(WIN32)
IF(UNIX)
SET(GSL_CONFIG_PREFER_PATH
"$ENV{GSL_DIR}/bin"
"$ENV{GSL_DIR}"
"$ENV{GSL_HOME}/bin"
"$ENV{GSL_HOME}"
CACHE STRING "preferred path to GSL (gsl-config)")
FIND_PROGRAM(GSL_CONFIG gsl-config
${GSL_CONFIG_PREFER_PATH}
/usr/bin/
)
# MESSAGE("DBG GSL_CONFIG ${GSL_CONFIG}")
IF (GSL_CONFIG)
# set CXXFLAGS to be fed into CXX_FLAGS by the user:
SET(GSL_CXX_FLAGS "`${GSL_CONFIG} --cflags`")
# set INCLUDE_DIRS to prefix+include
EXECUTE_PROCESS(
COMMAND ${GSL_CONFIG} --prefix
OUTPUT_VARIABLE GSL_PREFIX)
SET(GSL_INCLUDE_DIR ${GSL_PREFIX}/include CACHE STRING INTERNAL)
# set link libraries and link flags
SET(GSL_LIBRARIES "`${GSL_CONFIG} --libs`")
# extract link dirs for rpath
EXECUTE_PROCESS(
COMMAND ${GSL_CONFIG} --libs
OUTPUT_VARIABLE GSL_CONFIG_LIBS
OUTPUT_STRIP_TRAILING_WHITESPACE)
# split off the link dirs (for rpath)
# use regular expression to match wildcard equivalent "-L*<endchar>"
# with <endchar> is a space or a semicolon
STRING(REGEX MATCHALL "[-][L]([^ ;])+"
GSL_LINK_DIRECTORIES_WITH_PREFIX
"${GSL_CONFIG_LIBS}" )
# MESSAGE("DBG GSL_LINK_DIRECTORIES_WITH_PREFIX=${GSL_LINK_DIRECTORIES_WITH_PREFIX}")
# remove prefix -L because we need the pure directory for LINK_DIRECTORIES
IF (GSL_LINK_DIRECTORIES_WITH_PREFIX)
STRING(REGEX REPLACE "[-][L]" "" GSL_LINK_DIRECTORIES ${GSL_LINK_DIRECTORIES_WITH_PREFIX} )
ENDIF (GSL_LINK_DIRECTORIES_WITH_PREFIX)
SET(GSL_EXE_LINKER_FLAGS "-Wl,-rpath,${GSL_LINK_DIRECTORIES}" CACHE STRING INTERNAL)
# MESSAGE("DBG GSL_LINK_DIRECTORIES=${GSL_LINK_DIRECTORIES}")
# MESSAGE("DBG GSL_EXE_LINKER_FLAGS=${GSL_EXE_LINKER_FLAGS}")
# ADD_DEFINITIONS("-DHAVE_GSL")
# SET(GSL_DEFINITIONS "-DHAVE_GSL")
MARK_AS_ADVANCED(
GSL_CXX_FLAGS
GSL_INCLUDE_DIR
GSL_LIBRARIES
GSL_LINK_DIRECTORIES
GSL_DEFINITIONS
)
MESSAGE(STATUS "Using GSL from ${GSL_PREFIX}")
ELSE(GSL_CONFIG)
MESSAGE("FindGSL.cmake: gsl-config not found. Please set it manually. GSL_CONFIG=${GSL_CONFIG}")
ENDIF(GSL_CONFIG)
ENDIF(UNIX)
ENDIF(WIN32)
message(${GSL_CONFIG})
# MESSAGE(${GSL_LINK_DIRECTORIES})
IF(GSL_LIBRARIES)
IF(GSL_INCLUDE_DIR OR GSL_CXX_FLAGS)
SET(GSL_FOUND 1)
ENDIF(GSL_INCLUDE_DIR OR GSL_CXX_FLAGS)
ENDIF(GSL_LIBRARIES)
| {'content_hash': '2a9a209060467b602a3b0135f6546ce8', 'timestamp': '', 'source': 'github', 'line_count': 118, 'max_line_length': 102, 'avg_line_length': 29.728813559322035, 'alnum_prop': 0.6302736602052451, 'repo_name': 'godosou/smaroute', 'id': 'd71c88a8cde6eda1e726c3a9c644b16674c06501', 'size': '4201', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'src/cmake/Modules/FindGSL.cmake', 'mode': '33261', 'license': 'mit', 'language': [{'name': 'C', 'bytes': '45175'}, {'name': 'C++', 'bytes': '1737279'}, {'name': 'Perl', 'bytes': '1652'}]} |
.. _repository-scm-cvs:
================
CVS Repositories
================
Review Board supports posting and reviewing code on :rbintegration:`CVS <cvs>`
repositories. All standard CVS repository configurations can be used.
To simplify posting changes to Review Board, we recommend using RBTools_. This
ensures that the diffs are in the correct format and makes managing review
requests much easier. See :ref:`Using RBTools with CVS <rbt-post-cvs>` for more
information.
.. note::
This guide assumes that you're adding a CVS repository that's hosted
somewhere in your network or one that's accessible by your Review Board
server. Review Board requires local or network access to your repository.
Follow the documentation in the links below if your CVS repository is
hosted on one of these services, as configuration may differ.
* :ref:`SourceForge <repository-hosting-sourceforge>`
.. _RBTools: https://www.reviewboard.org/downloads/rbtools/
Installing CVS Support
======================
Before you add the repository, you will need to install the :command:`cvs`
command line tool in a system path (or in a place accessible by your web
server's process). This can be installed through your system's package
manager.
See the :ref:`installation guide <installing-cvs>` for CVS.
Adding the Repository
=====================
To configure a CVS repository, first proceed to :ref:`add the repository
<adding-repositories>` and select :guilabel:`CVS` from the
:guilabel:`Repository type` field.
You will see a :guilabel:`Path` field, which should contain the CVSROOT
for your repository. This can use any of the following CVS connection methods:
* :ref:`repository-scm-cvs-credential-cvsroots`:
* ``:gserver:``
* ``:kserver:``
* ``:pserver:``
* :ref:`repository-scm-cvs-ssh-cvsroots`:
* ``:ext:``
* ``:extssh:``
* ``:ssh:``
* :ref:`repository-scm-cvs-local-cvsroots`:
* ``:fork:``
* ``:local:``
Determining Your CVSROOT
------------------------
To determine the CVSROOT of an existing checkout, you can go to the top-most
directory of the checkout and type::
$ cat CVS/Root
This will show the CVSROOT used for your repository. You can use the value
as-is, or modify it to suit your needs. See below for more details.
.. _repository-scm-cvs-credential-cvsroots:
Credential-Based CVSROOTs
-------------------------
If you're using ``:pserver:``, ``:gserver:``, or ``:kserver:``, you're going
to need to specify credentials (a username and password) for your repository.
You can specify these credentials either in the :guilabel:`Path` field or in
the :guilabel:`Username` and :guilabel:`Password` fields.
Credentials specified in :guilabel:`Username` and :guilabel:`Password` will
only be used if using ``:pserver:``, ``:gserver:``, or ``:kserver``
connection methods, and if the credentials aren't already provided in
:guilabel:`Path`.
.. tip::
Specify the credentials outside of the CVSROOT, if possible. This will
allow RBTools_ or other clients to locate your repository by CVSROOT,
which may not be possible if it contains a username or password.
Examples
~~~~~~~~
* ``:pserver:cvs.example.com/cvsroot``
* ``:pserver:[email protected]/cvsroot``
* ``:pserver:myuser:[email protected]:1234/cvsroot``
.. _repository-scm-cvs-ssh-cvsroots:
SSH-Based CVSROOTs
------------------
If you're using ``:ext:``, ``:extssh:``, or ``:ssh:``, you will need to
:ref:`configure a SSH key <ssh-settings>` in Review Board, and grant access on
the repository. You will also need the specify the username, either in the
CVSROOT or in the :guilabel:`Username` field. The :guilabel:`Password` field
must be blank.
.. note::
The ``:server:`` connection method should not be used, as it makes use of
an internal SSH client that will not see your configured Review Board SSH
key. It's also not supported by all CVS implementations.
.. tip::
If your repository has an alternative ``:pserver:`` (or other) CVSROOT that
people can use, you may want to specify it in the :guilabel:`Mirror path`
field. This is used only for path matching when looking up repositories.
Examples
~~~~~~~~
* ``:extssh:cvs.example.com:/cvsroot``
* ``:ssh:localhost:22/cvsroot``
* ``:ssh:[email protected]:/cvsroot``
* ``:ext:[email protected]:/cvsroot``
* ``:ext:[email protected]:/cvsroot``
* ``:ext:cvs.example.com:/cvsroot``
.. _repository-scm-cvs-local-cvsroots:
Local CVSROOTs
--------------
If your repository lives on the same machine as Review Board, you can refer to
it by local path using ``:local:`` or ``:fork:``.
.. tip::
You should specify the CVSROOT that users connecting to your server would
use in the :guilabel:`Mirror path` field. This is used only for path
matching when looking up repositories.
Examples
~~~~~~~~
* ``:local:C:\CVSROOTS\myproject``
* ``:local:/home/myuser/cvsroot``
* ``:fork:/home/myuser/cvsroot``
| {'content_hash': '8ff5e8a6bd99054ba2ad642ca4bdc080', 'timestamp': '', 'source': 'github', 'line_count': 166, 'max_line_length': 79, 'avg_line_length': 29.801204819277107, 'alnum_prop': 0.7026480695370931, 'repo_name': 'davidt/reviewboard', 'id': '1b88a37fa504961f90af6f262850608c6cfee9eb', 'size': '4947', 'binary': False, 'copies': '5', 'ref': 'refs/heads/master', 'path': 'docs/manual/admin/configuration/repositories/cvs.rst', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '206392'}, {'name': 'HTML', 'bytes': '182334'}, {'name': 'JavaScript', 'bytes': '1770499'}, {'name': 'Python', 'bytes': '3842787'}, {'name': 'Shell', 'bytes': '20225'}]} |
"""
Onshape REST API
The Onshape REST API consumed by all clients. # noqa: E501
The version of the OpenAPI document: 1.113
Contact: [email protected]
Generated by: https://openapi-generator.tech
"""
from __future__ import absolute_import
import re # noqa: F401
import sys # noqa: F401
import six # noqa: F401
import nulltype # noqa: F401
from onshape_client.oas.model_utils import ( # noqa: F401
ModelComposed,
ModelNormal,
ModelSimple,
date,
datetime,
file_type,
int,
none_type,
str,
validate_get_composed_info,
)
try:
from onshape_client.oas.models import bt_parameter_spec6
except ImportError:
bt_parameter_spec6 = sys.modules["onshape_client.oas.models.bt_parameter_spec6"]
try:
from onshape_client.oas.models import bt_parameter_spec_query174_all_of
except ImportError:
bt_parameter_spec_query174_all_of = sys.modules[
"onshape_client.oas.models.bt_parameter_spec_query174_all_of"
]
try:
from onshape_client.oas.models import bt_parameter_visibility_condition177
except ImportError:
bt_parameter_visibility_condition177 = sys.modules[
"onshape_client.oas.models.bt_parameter_visibility_condition177"
]
try:
from onshape_client.oas.models import bt_query_filter183
except ImportError:
bt_query_filter183 = sys.modules["onshape_client.oas.models.bt_query_filter183"]
try:
from onshape_client.oas.models import btm_parameter1
except ImportError:
btm_parameter1 = sys.modules["onshape_client.oas.models.btm_parameter1"]
class BTParameterSpecQuery174(ModelComposed):
"""NOTE: This class is auto generated by OpenAPI Generator.
Ref: https://openapi-generator.tech
Do not edit the class manually.
Attributes:
allowed_values (dict): The key is the tuple path to the attribute
and the for var_name this is (var_name,). The value is a dict
with a capitalized key describing the allowed value and an allowed
value. These dicts store the allowed enum values.
attribute_map (dict): The key is attribute name
and the value is json key in definition.
discriminator_value_class_map (dict): A dict to go from the discriminator
variable value to the discriminator class name.
validations (dict): The key is the tuple path to the attribute
and the for var_name this is (var_name,). The value is a dict
that stores validations for max_length, min_length, max_items,
min_items, exclusive_maximum, inclusive_maximum, exclusive_minimum,
inclusive_minimum, and regex.
additional_properties_type (tuple): A tuple of classes accepted
as additional properties values.
"""
allowed_values = {
("ui_hints",): {
"OPPOSITE_DIRECTION": "OPPOSITE_DIRECTION",
"ALWAYS_HIDDEN": "ALWAYS_HIDDEN",
"SHOW_CREATE_SELECTION": "SHOW_CREATE_SELECTION",
"CONTROL_VISIBILITY": "CONTROL_VISIBILITY",
"NO_PREVIEW_PROVIDED": "NO_PREVIEW_PROVIDED",
"REMEMBER_PREVIOUS_VALUE": "REMEMBER_PREVIOUS_VALUE",
"DISPLAY_SHORT": "DISPLAY_SHORT",
"ALLOW_FEATURE_SELECTION": "ALLOW_FEATURE_SELECTION",
"MATE_CONNECTOR_AXIS_TYPE": "MATE_CONNECTOR_AXIS_TYPE",
"PRIMARY_AXIS": "PRIMARY_AXIS",
"SHOW_EXPRESSION": "SHOW_EXPRESSION",
"OPPOSITE_DIRECTION_CIRCULAR": "OPPOSITE_DIRECTION_CIRCULAR",
"SHOW_LABEL": "SHOW_LABEL",
"HORIZONTAL_ENUM": "HORIZONTAL_ENUM",
"UNCONFIGURABLE": "UNCONFIGURABLE",
"MATCH_LAST_ARRAY_ITEM": "MATCH_LAST_ARRAY_ITEM",
"COLLAPSE_ARRAY_ITEMS": "COLLAPSE_ARRAY_ITEMS",
"INITIAL_FOCUS_ON_EDIT": "INITIAL_FOCUS_ON_EDIT",
"INITIAL_FOCUS": "INITIAL_FOCUS",
"DISPLAY_CURRENT_VALUE_ONLY": "DISPLAY_CURRENT_VALUE_ONLY",
"READ_ONLY": "READ_ONLY",
"PREVENT_CREATING_NEW_MATE_CONNECTORS": "PREVENT_CREATING_NEW_MATE_CONNECTORS",
"FIRST_IN_ROW": "FIRST_IN_ROW",
"ALLOW_QUERY_ORDER": "ALLOW_QUERY_ORDER",
"PREVENT_ARRAY_REORDER": "PREVENT_ARRAY_REORDER",
"UNKNOWN": "UNKNOWN",
},
}
validations = {}
additional_properties_type = None
@staticmethod
def openapi_types():
"""
This must be a class method so a model may have properties that are
of type self, this ensures that we don't create a cyclic import
Returns
openapi_types (dict): The key is attribute name
and the value is attribute type.
"""
return {
"additional_box_select_filter": (
bt_query_filter183.BTQueryFilter183,
), # noqa: E501
"bt_type": (str,), # noqa: E501
"filter": (bt_query_filter183.BTQueryFilter183,), # noqa: E501
"max_number_of_picks": (int,), # noqa: E501
"additional_localized_strings": (int,), # noqa: E501
"column_name": (str,), # noqa: E501
"default_value": (btm_parameter1.BTMParameter1,), # noqa: E501
"icon_uri": (str,), # noqa: E501
"localizable_name": (str,), # noqa: E501
"localized_name": (str,), # noqa: E501
"parameter_id": (str,), # noqa: E501
"parameter_name": (str,), # noqa: E501
"strings_to_localize": ([str],), # noqa: E501
"ui_hint": (str,), # noqa: E501
"ui_hints": ([str],), # noqa: E501
"visibility_condition": (
bt_parameter_visibility_condition177.BTParameterVisibilityCondition177,
), # noqa: E501
}
@staticmethod
def discriminator():
return None
attribute_map = {
"additional_box_select_filter": "additionalBoxSelectFilter", # noqa: E501
"bt_type": "btType", # noqa: E501
"filter": "filter", # noqa: E501
"max_number_of_picks": "maxNumberOfPicks", # noqa: E501
"additional_localized_strings": "additionalLocalizedStrings", # noqa: E501
"column_name": "columnName", # noqa: E501
"default_value": "defaultValue", # noqa: E501
"icon_uri": "iconUri", # noqa: E501
"localizable_name": "localizableName", # noqa: E501
"localized_name": "localizedName", # noqa: E501
"parameter_id": "parameterId", # noqa: E501
"parameter_name": "parameterName", # noqa: E501
"strings_to_localize": "stringsToLocalize", # noqa: E501
"ui_hint": "uiHint", # noqa: E501
"ui_hints": "uiHints", # noqa: E501
"visibility_condition": "visibilityCondition", # noqa: E501
}
required_properties = set(
[
"_data_store",
"_check_type",
"_from_server",
"_path_to_item",
"_configuration",
"_composed_instances",
"_var_name_to_model_instances",
"_additional_properties_model_instances",
]
)
def __init__(
self,
_check_type=True,
_from_server=False,
_path_to_item=(),
_configuration=None,
**kwargs
): # noqa: E501
"""bt_parameter_spec_query174.BTParameterSpecQuery174 - a model defined in OpenAPI
Keyword Args:
_check_type (bool): if True, values for parameters in openapi_types
will be type checked and a TypeError will be
raised if the wrong type is input.
Defaults to True
_path_to_item (tuple/list): This is a list of keys or values to
drill down to the model in received_data
when deserializing a response
_from_server (bool): True if the data is from the server
False if the data is from the client (default)
_configuration (Configuration): the instance to use when
deserializing a file_type parameter.
If passed, type conversion is attempted
If omitted no type conversion is done.
additional_box_select_filter (bt_query_filter183.BTQueryFilter183): [optional] # noqa: E501
bt_type (str): [optional] # noqa: E501
filter (bt_query_filter183.BTQueryFilter183): [optional] # noqa: E501
max_number_of_picks (int): [optional] # noqa: E501
additional_localized_strings (int): [optional] # noqa: E501
column_name (str): [optional] # noqa: E501
default_value (btm_parameter1.BTMParameter1): [optional] # noqa: E501
icon_uri (str): [optional] # noqa: E501
localizable_name (str): [optional] # noqa: E501
localized_name (str): [optional] # noqa: E501
parameter_id (str): [optional] # noqa: E501
parameter_name (str): [optional] # noqa: E501
strings_to_localize ([str]): [optional] # noqa: E501
ui_hint (str): [optional] # noqa: E501
ui_hints ([str]): [optional] # noqa: E501
visibility_condition (bt_parameter_visibility_condition177.BTParameterVisibilityCondition177): [optional] # noqa: E501
"""
self._data_store = {}
self._check_type = _check_type
self._from_server = _from_server
self._path_to_item = _path_to_item
self._configuration = _configuration
constant_args = {
"_check_type": _check_type,
"_path_to_item": _path_to_item,
"_from_server": _from_server,
"_configuration": _configuration,
}
required_args = {}
# remove args whose value is Null because they are unset
required_arg_names = list(required_args.keys())
for required_arg_name in required_arg_names:
if required_args[required_arg_name] is nulltype.Null:
del required_args[required_arg_name]
model_args = {}
model_args.update(required_args)
model_args.update(kwargs)
composed_info = validate_get_composed_info(constant_args, model_args, self)
self._composed_instances = composed_info[0]
self._var_name_to_model_instances = composed_info[1]
self._additional_properties_model_instances = composed_info[2]
unused_args = composed_info[3]
for var_name, var_value in required_args.items():
setattr(self, var_name, var_value)
for var_name, var_value in six.iteritems(kwargs):
if (
var_name in unused_args
and self._configuration is not None
and self._configuration.discard_unknown_keys
and not self._additional_properties_model_instances
):
# discard variable.
continue
setattr(self, var_name, var_value)
@staticmethod
def _composed_schemas():
# we need this here to make our import statements work
# we must store _composed_schemas in here so the code is only run
# when we invoke this method. If we kept this at the class
# level we would get an error beause the class level
# code would be run when this module is imported, and these composed
# classes don't exist yet because their module has not finished
# loading
return {
"anyOf": [],
"allOf": [
bt_parameter_spec6.BTParameterSpec6,
bt_parameter_spec_query174_all_of.BTParameterSpecQuery174AllOf,
],
"oneOf": [],
}
| {'content_hash': 'bcb6f62c6a3f9edb8d1f55b62adc15b6', 'timestamp': '', 'source': 'github', 'line_count': 284, 'max_line_length': 131, 'avg_line_length': 41.63732394366197, 'alnum_prop': 0.5912896405919662, 'repo_name': 'onshape-public/onshape-clients', 'id': 'c0b56bf66139fde047b49122aa7bb5b92ea830ef', 'size': '11842', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'python/onshape_client/oas/models/bt_parameter_spec_query174.py', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '4873'}, {'name': 'Go', 'bytes': '59674'}, {'name': 'HTML', 'bytes': '3851790'}, {'name': 'JavaScript', 'bytes': '2217'}, {'name': 'Makefile', 'bytes': '559'}, {'name': 'Python', 'bytes': '7560009'}, {'name': 'Shell', 'bytes': '3475'}, {'name': 'TypeScript', 'bytes': '1412661'}]} |
package com.intellij.openapi.options.newEditor;
import com.intellij.icons.AllIcons;
import com.intellij.ide.plugins.IdeaPluginDescriptor;
import com.intellij.ide.plugins.PluginManagerCore;
import com.intellij.ide.projectView.PresentationData;
import com.intellij.ide.util.treeView.NodeDescriptor;
import com.intellij.openapi.Disposable;
import com.intellij.openapi.extensions.PluginDescriptor;
import com.intellij.openapi.options.*;
import com.intellij.openapi.options.ex.ConfigurableWrapper;
import com.intellij.openapi.options.ex.SortedConfigurableGroup;
import com.intellij.openapi.project.Project;
import com.intellij.openapi.util.ActionCallback;
import com.intellij.openapi.util.Disposer;
import com.intellij.openapi.util.registry.Registry;
import com.intellij.ui.*;
import com.intellij.ui.components.GradientViewport;
import com.intellij.ui.treeStructure.*;
import com.intellij.ui.treeStructure.filtered.FilteringTreeBuilder;
import com.intellij.ui.treeStructure.filtered.FilteringTreeStructure;
import com.intellij.util.ArrayUtil;
import com.intellij.util.ui.GraphicsUtil;
import com.intellij.util.ui.JBUI;
import com.intellij.util.ui.TextTransferable;
import com.intellij.util.ui.UIUtil;
import com.intellij.util.ui.tree.TreeUtil;
import com.intellij.util.ui.tree.WideSelectionTreeUI;
import com.intellij.util.ui.update.MergingUpdateQueue;
import com.intellij.util.ui.update.Update;
import org.jetbrains.annotations.NotNull;
import org.jetbrains.annotations.Nullable;
import javax.accessibility.Accessible;
import javax.accessibility.AccessibleContext;
import javax.accessibility.AccessibleRole;
import javax.swing.*;
import javax.swing.event.TreeExpansionEvent;
import javax.swing.event.TreeExpansionListener;
import javax.swing.event.TreeSelectionEvent;
import javax.swing.event.TreeSelectionListener;
import javax.swing.plaf.TreeUI;
import javax.swing.tree.DefaultMutableTreeNode;
import javax.swing.tree.TreeCellRenderer;
import javax.swing.tree.TreePath;
import javax.swing.tree.TreeSelectionModel;
import java.awt.*;
import java.awt.datatransfer.Transferable;
import java.awt.event.ComponentAdapter;
import java.awt.event.ComponentEvent;
import java.awt.event.KeyEvent;
import java.awt.event.MouseEvent;
import java.util.ArrayDeque;
import java.util.ArrayList;
import java.util.IdentityHashMap;
import java.util.List;
/**
* @author Sergey.Malenkov
*/
public class SettingsTreeView extends JComponent implements Accessible, Disposable, OptionsEditorColleague {
private static final int ICON_GAP = 5;
private static final String NODE_ICON = "settings.tree.view.icon";
private static final Color WRONG_CONTENT = JBColor.RED;
private static final Color MODIFIED_CONTENT = JBColor.BLUE;
public static final Color FOREGROUND = new JBColor(Gray.x1A, Gray.xBB);
final SimpleTree myTree;
final FilteringTreeBuilder myBuilder;
private final SettingsFilter myFilter;
private final MyRoot myRoot;
private final JScrollPane myScroller;
private final IdentityHashMap<Configurable, MyNode> myConfigurableToNodeMap = new IdentityHashMap<>();
private final IdentityHashMap<UnnamedConfigurable, ConfigurableWrapper> myConfigurableToWrapperMap
= new IdentityHashMap<>();
private final MergingUpdateQueue myQueue = new MergingUpdateQueue("SettingsTreeView", 150, false, this, this, this)
.setRestartTimerOnAdd(true);
private Configurable myQueuedConfigurable;
private boolean myPaintInternalInfo;
public SettingsTreeView(SettingsFilter filter, ConfigurableGroup[] groups) {
myFilter = filter;
myRoot = new MyRoot(groups);
myTree = new MyTree();
myTree.putClientProperty(WideSelectionTreeUI.TREE_TABLE_TREE_KEY, Boolean.TRUE);
myTree.setBackground(UIUtil.SIDE_PANEL_BACKGROUND);
myTree.getInputMap().clear();
TreeUtil.installActions(myTree);
myTree.setOpaque(true);
myTree.getSelectionModel().setSelectionMode(TreeSelectionModel.SINGLE_TREE_SELECTION);
myTree.setCellRenderer(new MyRenderer());
myTree.setRootVisible(false);
myTree.setShowsRootHandles(false);
myTree.setExpandableItemsEnabled(false);
RelativeFont.BOLD.install(myTree);
myTree.setTransferHandler(new TransferHandler() {
@Nullable
@Override
protected Transferable createTransferable(JComponent c) {
MyNode node = extractNode(myTree.getPathForRow(myTree.getLeadSelectionRow()));
if (node != null) {
StringBuilder sb = new StringBuilder("File | Settings");
for (String name : getPathNames(node)) {
sb.append(" | ").append(name);
}
return new TextTransferable(sb.toString());
}
return null;
}
@Override
public int getSourceActions(JComponent c) {
return COPY;
}
});
myScroller = ScrollPaneFactory.createScrollPane(null, true);
myScroller.setViewport(new GradientViewport(myTree, JBUI.insetsTop(5), true) {
private JLabel myHeader;
@Override
protected Component getHeader() {
if (0 == myTree.getY()) {
return null; // separator is not needed without scrolling
}
if (myHeader == null) {
myHeader = new JLabel();
myHeader.setForeground(FOREGROUND);
myHeader.setIconTextGap(ICON_GAP);
myHeader.setBorder(BorderFactory.createEmptyBorder(1, 10 + getLeftMargin(0), 0, 0));
}
myHeader.setFont(myTree.getFont());
myHeader.setIcon(myTree.getEmptyHandle());
int height = myHeader.getPreferredSize().height;
String group = findGroupNameAt(0, height + 3);
if (group == null || !group.equals(findGroupNameAt(0, 0))) {
return null; // do not show separator over another group
}
myHeader.setText(group);
return myHeader;
}
});
if (!Registry.is("ide.scroll.background.auto")) {
myScroller.setBackground(UIUtil.SIDE_PANEL_BACKGROUND);
myScroller.getViewport().setBackground(UIUtil.SIDE_PANEL_BACKGROUND);
myScroller.getVerticalScrollBar().setBackground(UIUtil.SIDE_PANEL_BACKGROUND);
}
add(myScroller);
myTree.addComponentListener(new ComponentAdapter() {
@Override
public void componentResized(ComponentEvent e) {
myBuilder.revalidateTree();
}
@Override
public void componentMoved(ComponentEvent e) {
myBuilder.revalidateTree();
}
@Override
public void componentShown(ComponentEvent e) {
myBuilder.revalidateTree();
}
});
myTree.getSelectionModel().addTreeSelectionListener(new TreeSelectionListener() {
public void valueChanged(TreeSelectionEvent event) {
MyNode node = extractNode(event.getNewLeadSelectionPath());
select(node == null ? null : node.myConfigurable);
}
});
if (Registry.is("show.configurables.ids.in.settings")) {
new HeldDownKeyListener() {
@Override
protected void heldKeyTriggered(JComponent component, boolean pressed) {
myPaintInternalInfo = pressed;
SettingsTreeView.this.setMinimumSize(null);
// an easy way to repaint the tree
((Tree)component).setCellRenderer(new MyRenderer());
}
}.installOn(myTree);
}
myBuilder = new MyBuilder(new SimpleTreeStructure.Impl(myRoot));
myBuilder.setFilteringMerge(300, null);
Disposer.register(this, myBuilder);
}
@NotNull
String[] getPathNames(Configurable configurable) {
return getPathNames(findNode(configurable));
}
private static String[] getPathNames(MyNode node) {
ArrayDeque<String> path = new ArrayDeque<>();
while (node != null) {
path.push(node.myDisplayName);
SimpleNode parent = node.getParent();
node = parent instanceof MyNode
? (MyNode)parent
: null;
}
return ArrayUtil.toStringArray(path);
}
static Configurable getConfigurable(SimpleNode node) {
return node instanceof MyNode
? ((MyNode)node).myConfigurable
: null;
}
@Nullable
MyNode findNode(Configurable configurable) {
ConfigurableWrapper wrapper = myConfigurableToWrapperMap.get(configurable);
return myConfigurableToNodeMap.get(wrapper != null ? wrapper : configurable);
}
@Nullable
SearchableConfigurable findConfigurableById(@NotNull String id) {
for (Configurable configurable : myConfigurableToNodeMap.keySet()) {
if (configurable instanceof SearchableConfigurable) {
SearchableConfigurable searchable = (SearchableConfigurable)configurable;
if (id.equals(searchable.getId())) {
return searchable;
}
}
}
return null;
}
@Nullable
<T extends UnnamedConfigurable> T findConfigurable(@NotNull Class<T> type) {
for (UnnamedConfigurable configurable : myConfigurableToNodeMap.keySet()) {
if (configurable instanceof ConfigurableWrapper) {
ConfigurableWrapper wrapper = (ConfigurableWrapper)configurable;
configurable = wrapper.getConfigurable();
myConfigurableToWrapperMap.put(configurable, wrapper);
}
if (type.isInstance(configurable)) {
return type.cast(configurable);
}
}
return null;
}
@Nullable
Project findConfigurableProject(@Nullable Configurable configurable) {
MyNode node = findNode(configurable);
return node == null ? null : findConfigurableProject(node, true);
}
@Nullable
private static Project findConfigurableProject(@NotNull MyNode node, boolean checkProjectLevel) {
Configurable configurable = node.myConfigurable;
Project project = node.getProject();
if (checkProjectLevel) {
Configurable.VariableProjectAppLevel wrapped = ConfigurableWrapper.cast(Configurable.VariableProjectAppLevel.class, configurable);
if (wrapped != null) return wrapped.isProjectLevel() ? project : null;
}
if (configurable instanceof ConfigurableWrapper) return project;
if (configurable instanceof SortedConfigurableGroup) return project;
SimpleNode parent = node.getParent();
return parent instanceof MyNode
? findConfigurableProject((MyNode)parent, checkProjectLevel)
: null;
}
@Nullable
private static Project prepareProject(CachingSimpleNode parent, Configurable configurable) {
if (configurable instanceof ConfigurableWrapper) {
ConfigurableWrapper wrapper = (ConfigurableWrapper)configurable;
return wrapper.getExtensionPoint().getProject();
}
if (configurable instanceof SortedConfigurableGroup) {
SortedConfigurableGroup group = (SortedConfigurableGroup)configurable;
Configurable[] configurables = group.getConfigurables();
if (configurables != null && configurables.length != 0) {
Project project = prepareProject(parent, configurables[0]);
if (project != null) {
for (int i = 1; i < configurables.length; i++) {
if (project != prepareProject(parent, configurables[i])) {
return null;
}
}
}
return project;
}
}
return parent == null ? null : parent.getProject();
}
private static int getLeftMargin(int level) {
return 3 + level * (11 + ICON_GAP);
}
@Nullable
private String findGroupNameAt(int x, int y) {
TreePath path = myTree.getClosestPathForLocation(x - myTree.getX(), y - myTree.getY());
while (path != null) {
MyNode node = extractNode(path);
if (node == null) {
return null;
}
if (myRoot == node.getParent()) {
return node.myDisplayName;
}
path = path.getParentPath();
}
return null;
}
@Nullable
private static MyNode extractNode(@Nullable Object object) {
if (object instanceof TreePath) {
TreePath path = (TreePath)object;
object = path.getLastPathComponent();
}
if (object instanceof DefaultMutableTreeNode) {
DefaultMutableTreeNode node = (DefaultMutableTreeNode)object;
object = node.getUserObject();
}
if (object instanceof FilteringTreeStructure.FilteringNode) {
FilteringTreeStructure.FilteringNode node = (FilteringTreeStructure.FilteringNode)object;
object = node.getDelegate();
}
return object instanceof MyNode
? (MyNode)object
: null;
}
@Override
public void doLayout() {
myScroller.setBounds(0, 0, getWidth(), getHeight());
}
void selectFirst() {
for (ConfigurableGroup eachGroup : myRoot.myGroups) {
Configurable[] kids = eachGroup.getConfigurables();
if (kids.length > 0) {
select(kids[0]);
return;
}
}
}
ActionCallback select(@Nullable final Configurable configurable) {
if (myBuilder.isSelectionBeingAdjusted()) {
return ActionCallback.REJECTED;
}
final ActionCallback callback = new ActionCallback();
myQueuedConfigurable = configurable;
myQueue.queue(new Update(this) {
public void run() {
if (configurable == myQueuedConfigurable) {
if (configurable == null) {
fireSelected(null, callback);
}
else {
myBuilder.getReady(this).doWhenDone(() -> {
if (configurable != myQueuedConfigurable) return;
MyNode editorNode = findNode(configurable);
FilteringTreeStructure.FilteringNode editorUiNode = myBuilder.getVisibleNodeFor(editorNode);
if (editorUiNode == null) return;
if (!myBuilder.getSelectedElements().contains(editorUiNode)) {
myBuilder.select(editorUiNode, () -> fireSelected(configurable, callback));
}
else {
myBuilder.scrollSelectionToVisible(() -> fireSelected(configurable, callback), false);
}
});
}
}
}
@Override
public void setRejected() {
super.setRejected();
callback.setRejected();
}
});
return callback;
}
private void fireSelected(Configurable configurable, ActionCallback callback) {
ConfigurableWrapper wrapper = myConfigurableToWrapperMap.get(configurable);
myFilter.myContext.fireSelected(wrapper != null ? wrapper : configurable, this).doWhenProcessed(callback.createSetDoneRunnable());
}
@Override
public void dispose() {
myQueuedConfigurable = null;
}
@Override
public ActionCallback onSelected(@Nullable Configurable configurable, Configurable oldConfigurable) {
return select(configurable);
}
@Override
public ActionCallback onModifiedAdded(Configurable configurable) {
myTree.repaint();
return ActionCallback.DONE;
}
@Override
public ActionCallback onModifiedRemoved(Configurable configurable) {
myTree.repaint();
return ActionCallback.DONE;
}
@Override
public ActionCallback onErrorsChanged() {
return ActionCallback.DONE;
}
private final class MyRoot extends CachingSimpleNode {
private final ConfigurableGroup[] myGroups;
private MyRoot(ConfigurableGroup[] groups) {
super(null);
myGroups = groups;
}
@Override
protected SimpleNode[] buildChildren() {
if (myGroups == null || myGroups.length == 0) {
return NO_CHILDREN;
}
ArrayList<MyNode> list = new ArrayList<>();
for (ConfigurableGroup group : myGroups) {
for (Configurable configurable : group.getConfigurables()) {
list.add(new MyNode(this, configurable, 0));
}
}
return list.toArray(new SimpleNode[list.size()]);
}
}
private final class MyNode extends CachingSimpleNode {
private final Configurable.Composite myComposite;
private final Configurable myConfigurable;
private final String myDisplayName;
private final int myLevel;
private MyNode(CachingSimpleNode parent, Configurable configurable, int level) {
super(prepareProject(parent, configurable), parent);
myComposite = configurable instanceof Configurable.Composite ? (Configurable.Composite)configurable : null;
myConfigurable = configurable;
String name = configurable.getDisplayName();
myDisplayName = name != null ? name.replace("\n", " ") : "{ " + configurable.getClass().getSimpleName() + " }";
myLevel = level;
}
@Override
protected SimpleNode[] buildChildren() {
if (myConfigurable != null) {
myConfigurableToNodeMap.put(myConfigurable, this);
}
if (myComposite == null) {
return NO_CHILDREN;
}
Configurable[] configurables = myComposite.getConfigurables();
if (configurables == null || configurables.length == 0) {
return NO_CHILDREN;
}
SimpleNode[] result = new SimpleNode[configurables.length];
for (int i = 0; i < configurables.length; i++) {
result[i] = new MyNode(this, configurables[i], myLevel + 1);
if (myConfigurable != null) {
myFilter.myContext.registerKid(myConfigurable, configurables[i]);
}
}
return result;
}
protected void update(PresentationData presentation) {
super.update(presentation);
presentation.addText(myDisplayName, getPlainAttributes());
}
@Override
public boolean isAlwaysLeaf() {
return myComposite == null;
}
}
private final class MyRenderer extends CellRendererPanel implements TreeCellRenderer {
final SimpleColoredComponent myTextLabel = new SimpleColoredComponent();
final JLabel myNodeIcon = new JLabel();
final JLabel myProjectIcon = new JLabel();
MyRenderer() {
setLayout(new BorderLayout(ICON_GAP, 0));
myNodeIcon.setName(NODE_ICON);
myTextLabel.setOpaque(false);
add(BorderLayout.CENTER, myTextLabel);
add(BorderLayout.WEST, myNodeIcon);
add(BorderLayout.EAST, myProjectIcon);
setBorder(BorderFactory.createEmptyBorder(1, 10, 3, 10));
}
@Override
public AccessibleContext getAccessibleContext() {
if (accessibleContext == null) {
accessibleContext = new MyAccessibleContext();
}
return accessibleContext;
}
// TODO: consider making MyRenderer a subclass of SimpleColoredComponent.
// This should eliminate the need to add this accessibility stuff.
private class MyAccessibleContext extends JPanel.AccessibleJPanel {
@Override
public String getAccessibleName() {
return myTextLabel.getCharSequence(true).toString();
}
}
public Component getTreeCellRendererComponent(JTree tree,
Object value,
boolean selected,
boolean expanded,
boolean leaf,
int row,
boolean focused) {
myTextLabel.clear();
setPreferredSize(null);
MyNode node = extractNode(value);
boolean isGroup = node != null && myRoot == node.getParent();
String name = node != null ? node.myDisplayName : String.valueOf(value);
myTextLabel.append(name, isGroup ? SimpleTextAttributes.REGULAR_BOLD_ATTRIBUTES : SimpleTextAttributes.REGULAR_ATTRIBUTES);
myTextLabel.setFont(isGroup ? myTree.getFont() : UIUtil.getLabelFont());
// update font color for modified configurables
myTextLabel.setForeground(selected ? UIUtil.getTreeSelectionForeground() : FOREGROUND);
if (!selected && node != null) {
Configurable configurable = node.myConfigurable;
if (configurable != null) {
if (myFilter.myContext.getErrors().containsKey(configurable)) {
myTextLabel.setForeground(WRONG_CONTENT);
}
else if (myFilter.myContext.getModified().contains(configurable)) {
myTextLabel.setForeground(MODIFIED_CONTENT);
}
}
}
// configure project icon
Project project = null;
if (node != null) {
project = findConfigurableProject(node, false);
}
Configurable configurable = null;
if(node != null)
configurable = node.myConfigurable;
setProjectIcon(myProjectIcon, configurable, project, selected);
// configure node icon
Icon nodeIcon = null;
if (value instanceof DefaultMutableTreeNode) {
DefaultMutableTreeNode treeNode = (DefaultMutableTreeNode)value;
if (0 == treeNode.getChildCount()) {
nodeIcon = myTree.getEmptyHandle();
}
else {
nodeIcon = myTree.isExpanded(new TreePath(treeNode.getPath()))
? myTree.getExpandedHandle()
: myTree.getCollapsedHandle();
}
}
myNodeIcon.setIcon(nodeIcon);
if (node != null && myPaintInternalInfo) {
String id = node.myConfigurable instanceof ConfigurableWrapper ? ((ConfigurableWrapper)node.myConfigurable).getId() :
node.myConfigurable instanceof SearchableConfigurable ? ((SearchableConfigurable)node.myConfigurable).getId() :
node.myConfigurable.getClass().getSimpleName();
PluginDescriptor plugin = node.myConfigurable instanceof ConfigurableWrapper ? ((ConfigurableWrapper)node.myConfigurable).getExtensionPoint().getPluginDescriptor() : null;
String pluginId = plugin == null ? null : plugin.getPluginId().getIdString();
String pluginName = pluginId == null || PluginManagerCore.CORE_PLUGIN_ID.equals(pluginId) ? null :
plugin instanceof IdeaPluginDescriptor ? ((IdeaPluginDescriptor)plugin).getName() : pluginId;
myTextLabel.append(" ", SimpleTextAttributes.REGULAR_ATTRIBUTES, false);
myTextLabel.append(pluginName == null ? id : id + " (" + pluginName + ")", SimpleTextAttributes.GRAYED_SMALL_ATTRIBUTES, false);
}
// calculate minimum size
if (node != null && tree.isVisible()) {
int width = getLeftMargin(node.myLevel) + getPreferredSize().width;
Insets insets = tree.getInsets();
if (insets != null) {
width += insets.left + insets.right;
}
JScrollBar bar = myScroller.getVerticalScrollBar();
if (bar != null && bar.isVisible()) {
width += bar.getWidth();
}
width = Math.min(width, 300); // maximal width for minimum size
JComponent view = SettingsTreeView.this;
Dimension size = view.getMinimumSize();
if (size.width < width) {
size.width = width;
view.setMinimumSize(size);
view.revalidate();
view.repaint();
}
}
return this;
}
}
protected void setProjectIcon(JLabel projectIcon, Configurable configurable, @Nullable Project project, boolean selected) {
if (project != null) {
projectIcon.setIcon(selected
? AllIcons.General.ProjectConfigurableSelected
: AllIcons.General.ProjectConfigurable);
projectIcon.setToolTipText(OptionsBundle.message(project.isDefault()
? "configurable.default.project.tooltip"
: "configurable.current.project.tooltip"));
projectIcon.setVisible(true);
}
else {
projectIcon.setVisible(false);
}
}
private final class MyTree extends SimpleTree {
@Override
public String getToolTipText(MouseEvent event) {
if (event != null) {
Component component = getDeepestRendererComponentAt(event.getX(), event.getY());
if (component instanceof JLabel) {
JLabel label = (JLabel)component;
if (label.getIcon() != null) {
String text = label.getToolTipText();
if (text != null) {
return text;
}
}
}
}
return super.getToolTipText(event);
}
@Override
protected boolean paintNodes() {
return false;
}
@Override
protected boolean highlightSingleNode() {
return false;
}
@Override
public void setUI(TreeUI ui) {
super.setUI(ui instanceof MyTreeUi ? ui : new MyTreeUi());
}
@Override
protected boolean isCustomUI() {
return true;
}
@Override
protected void configureUiHelper(TreeUIHelper helper) {
}
@Override
public boolean getScrollableTracksViewportWidth() {
return true;
}
@Override
public void processKeyEvent(KeyEvent e) {
TreePath path = myTree.getSelectionPath();
if (path != null) {
if (e.getKeyCode() == KeyEvent.VK_LEFT) {
if (isExpanded(path)) {
collapsePath(path);
return;
}
}
else if (e.getKeyCode() == KeyEvent.VK_RIGHT) {
if (isCollapsed(path)) {
expandPath(path);
return;
}
}
}
super.processKeyEvent(e);
}
@Override
protected void processMouseEvent(MouseEvent event) {
MyTreeUi ui = (MyTreeUi)myTree.getUI();
if (!ui.processMouseEvent(event)) {
super.processMouseEvent(event);
}
}
}
private static final class MyTreeUi extends WideSelectionTreeUI {
boolean processMouseEvent(MouseEvent event) {
if (super.tree instanceof SimpleTree) {
SimpleTree tree = (SimpleTree)super.tree;
boolean toggleNow = MouseEvent.MOUSE_RELEASED == event.getID()
&& UIUtil.isActionClick(event, MouseEvent.MOUSE_RELEASED)
&& !isToggleEvent(event);
if (toggleNow || MouseEvent.MOUSE_PRESSED == event.getID()) {
Component component = tree.getDeepestRendererComponentAt(event.getX(), event.getY());
if (component != null && NODE_ICON.equals(component.getName())) {
if (toggleNow) {
toggleExpandState(tree.getPathForLocation(event.getX(), event.getY()));
}
event.consume();
return true;
}
}
}
return false;
}
@Override
protected boolean shouldPaintExpandControl(TreePath path,
int row,
boolean isExpanded,
boolean hasBeenExpanded,
boolean isLeaf) {
return false;
}
@Override
protected void paintHorizontalPartOfLeg(Graphics g,
Rectangle clipBounds,
Insets insets,
Rectangle bounds,
TreePath path,
int row,
boolean isExpanded,
boolean hasBeenExpanded,
boolean isLeaf) {
}
@Override
protected void paintVerticalPartOfLeg(Graphics g, Rectangle clipBounds, Insets insets, TreePath path) {
}
@Override
public void paint(Graphics g, JComponent c) {
GraphicsUtil.setupAntialiasing(g);
super.paint(g, c);
}
@Override
protected void paintRow(Graphics g,
Rectangle clipBounds,
Insets insets,
Rectangle bounds,
TreePath path,
int row,
boolean isExpanded,
boolean hasBeenExpanded,
boolean isLeaf) {
if (tree != null) {
bounds.width = tree.getWidth();
Container parent = tree.getParent();
if (parent instanceof JViewport) {
JViewport viewport = (JViewport)parent;
bounds.width = viewport.getWidth() - viewport.getViewPosition().x - insets.right / 2;
}
bounds.width -= bounds.x;
}
super.paintRow(g, clipBounds, insets, bounds, path, row, isExpanded, hasBeenExpanded, isLeaf);
}
@Override
protected int getRowX(int row, int depth) {
return getLeftMargin(depth - 1);
}
}
private final class MyBuilder extends FilteringTreeBuilder {
List<Object> myToExpandOnResetFilter;
boolean myRefilteringNow;
boolean myWasHoldingFilter;
public MyBuilder(SimpleTreeStructure structure) {
super(myTree, myFilter, structure, null);
myTree.addTreeExpansionListener(new TreeExpansionListener() {
public void treeExpanded(TreeExpansionEvent event) {
invalidateExpansions();
}
public void treeCollapsed(TreeExpansionEvent event) {
invalidateExpansions();
}
});
}
private void invalidateExpansions() {
if (!myRefilteringNow) {
myToExpandOnResetFilter = null;
}
}
@Override
protected boolean isSelectable(Object object) {
return object instanceof MyNode;
}
@Override
public boolean isAutoExpandNode(NodeDescriptor nodeDescriptor) {
return myFilter.myContext.isHoldingFilter();
}
@Override
public boolean isToEnsureSelectionOnFocusGained() {
return false;
}
@Override
protected ActionCallback refilterNow(Object preferredSelection, boolean adjustSelection) {
final List<Object> toRestore = new ArrayList<>();
if (myFilter.myContext.isHoldingFilter() && !myWasHoldingFilter && myToExpandOnResetFilter == null) {
myToExpandOnResetFilter = myBuilder.getUi().getExpandedElements();
}
else if (!myFilter.myContext.isHoldingFilter() && myWasHoldingFilter && myToExpandOnResetFilter != null) {
toRestore.addAll(myToExpandOnResetFilter);
myToExpandOnResetFilter = null;
}
myWasHoldingFilter = myFilter.myContext.isHoldingFilter();
ActionCallback result = super.refilterNow(preferredSelection, adjustSelection);
myRefilteringNow = true;
return result.doWhenDone(() -> {
myRefilteringNow = false;
if (!myFilter.myContext.isHoldingFilter() && getSelectedElements().isEmpty()) {
restoreExpandedState(toRestore);
}
});
}
private void restoreExpandedState(List<Object> toRestore) {
TreePath[] selected = myTree.getSelectionPaths();
if (selected == null) {
selected = new TreePath[0];
}
List<TreePath> toCollapse = new ArrayList<>();
for (int eachRow = 0; eachRow < myTree.getRowCount(); eachRow++) {
if (!myTree.isExpanded(eachRow)) continue;
TreePath eachVisiblePath = myTree.getPathForRow(eachRow);
if (eachVisiblePath == null) continue;
Object eachElement = myBuilder.getElementFor(eachVisiblePath.getLastPathComponent());
if (toRestore.contains(eachElement)) continue;
for (TreePath eachSelected : selected) {
if (!eachVisiblePath.isDescendant(eachSelected)) {
toCollapse.add(eachVisiblePath);
}
}
}
for (TreePath each : toCollapse) {
myTree.collapsePath(each);
}
}
}
@Override
public AccessibleContext getAccessibleContext() {
if (accessibleContext == null) {
accessibleContext = new AccessibleSettingsTreeView();
}
return accessibleContext;
}
protected class AccessibleSettingsTreeView extends AccessibleJComponent {
@Override
public AccessibleRole getAccessibleRole() {
return AccessibleRole.PANEL;
}
}
}
| {'content_hash': '1f7b270230173dd7db482865ef90db74', 'timestamp': '', 'source': 'github', 'line_count': 901, 'max_line_length': 179, 'avg_line_length': 35.01442841287459, 'alnum_prop': 0.6520540129326741, 'repo_name': 'da1z/intellij-community', 'id': '4faf5ea69ee019afb43ae5f7588dd17c628e0ab5', 'size': '32148', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'platform/platform-impl/src/com/intellij/openapi/options/newEditor/SettingsTreeView.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'AMPL', 'bytes': '20665'}, {'name': 'AspectJ', 'bytes': '182'}, {'name': 'Batchfile', 'bytes': '61131'}, {'name': 'C', 'bytes': '213044'}, {'name': 'C#', 'bytes': '1264'}, {'name': 'C++', 'bytes': '181560'}, {'name': 'CMake', 'bytes': '1675'}, {'name': 'CSS', 'bytes': '172743'}, {'name': 'CoffeeScript', 'bytes': '1759'}, {'name': 'DTrace', 'bytes': '578'}, {'name': 'Erlang', 'bytes': '10'}, {'name': 'Groovy', 'bytes': '3356487'}, {'name': 'HLSL', 'bytes': '57'}, {'name': 'HTML', 'bytes': '1903378'}, {'name': 'J', 'bytes': '5050'}, {'name': 'Java', 'bytes': '168760745'}, {'name': 'JavaScript', 'bytes': '148969'}, {'name': 'Jupyter Notebook', 'bytes': '93222'}, {'name': 'Kotlin', 'bytes': '5493011'}, {'name': 'Lex', 'bytes': '148791'}, {'name': 'Makefile', 'bytes': '2352'}, {'name': 'NSIS', 'bytes': '51699'}, {'name': 'Objective-C', 'bytes': '27309'}, {'name': 'PHP', 'bytes': '2425'}, {'name': 'Perl', 'bytes': '962'}, {'name': 'Python', 'bytes': '25962640'}, {'name': 'Roff', 'bytes': '37534'}, {'name': 'Ruby', 'bytes': '1217'}, {'name': 'Shell', 'bytes': '64132'}, {'name': 'Smalltalk', 'bytes': '338'}, {'name': 'TeX', 'bytes': '25473'}, {'name': 'Thrift', 'bytes': '1846'}, {'name': 'TypeScript', 'bytes': '9469'}, {'name': 'Visual Basic', 'bytes': '77'}, {'name': 'XSLT', 'bytes': '113040'}]} |
#ifndef CCAT_MESSAGE_AGGREGATOR_EVENT_H
#define CCAT_MESSAGE_AGGREGATOR_EVENT_H
#include <client.h>
void addEventToAggregator(CatEvent * pEvent);
void sendEventData();
void initCatEventAggregator();
void destroyCatEventAggregator();
#endif //CCAT_MESSAGE_AGGREGATOR_EVENT_H
| {'content_hash': 'bf3c53f8fd60781be44b1627889fa90d', 'timestamp': '', 'source': 'github', 'line_count': 15, 'max_line_length': 45, 'avg_line_length': 18.733333333333334, 'alnum_prop': 0.7900355871886121, 'repo_name': 'dianping/cat', 'id': 'd05c036e75eb7f1922e4cefe61b9bcf98ef74f5b', 'size': '1149', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'lib/erlang/c_src/src/ccat/message_aggregator_event.h', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'C', 'bytes': '991092'}, {'name': 'C#', 'bytes': '291403'}, {'name': 'C++', 'bytes': '18146'}, {'name': 'CMake', 'bytes': '34620'}, {'name': 'Dockerfile', 'bytes': '803'}, {'name': 'Erlang', 'bytes': '11752'}, {'name': 'FreeMarker', 'bytes': '82593'}, {'name': 'Go', 'bytes': '17986'}, {'name': 'Java', 'bytes': '20359094'}, {'name': 'Less', 'bytes': '650677'}, {'name': 'Makefile', 'bytes': '3092'}, {'name': 'Python', 'bytes': '45967'}, {'name': 'Scala', 'bytes': '8692'}, {'name': 'Shell', 'bytes': '1705'}, {'name': 'Smarty', 'bytes': '2397'}]} |
package de.bmw.carit.acme.api;
/**
* Represents a module type.
*/
public enum ModuleType
{
/**
* A static module (aka: lib).
*/
Static,
/**
* A dynamic module (aka: dll).
*/
Dynamic,
/**
* An executable (aka: exe).
*/
Exe;
/**
* Parses a string and returns the representing module type.
*
* @param type
* The type. If null or unknown, 'Static' is returned.
* @return The representing module type as enumeration member.
*/
public static ModuleType fromString(String type)
{
if (type != null)
{
if (type.equalsIgnoreCase(Dynamic.toString()))
{
return Dynamic;
}
if (type.equalsIgnoreCase(Exe.toString()))
{
return Exe;
}
}
return Static; // default
}
}
| {'content_hash': 'eecd9874c48558b5066e95ef9630e097', 'timestamp': '', 'source': 'github', 'line_count': 47, 'max_line_length': 69, 'avg_line_length': 19.29787234042553, 'alnum_prop': 0.49173098125689085, 'repo_name': 'bmwcarit/acme', 'id': '2245965d186fa6cf275dde96c1757b8ba41d584e', 'size': '1505', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'jACME/jACME/src/de/bmw/carit/acme/api/ModuleType.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'C++', 'bytes': '55941'}, {'name': 'Java', 'bytes': '153889'}, {'name': 'JavaScript', 'bytes': '75668'}, {'name': 'Objective-C', 'bytes': '4130'}, {'name': 'Shell', 'bytes': '4272'}]} |
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<h2 title="Uses of Interface org.apache.solr.util.SolrCLI.Tool" class="title">Uses of Interface<br>org.apache.solr.util.SolrCLI.Tool</h2>
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<th class="colFirst" scope="col">Package</th>
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<td class="colFirst"><a href="#org.apache.solr.util">org.apache.solr.util</a></td>
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<div class="block">
Common utility classes used throughout Solr</div>
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<h3>Uses of <a href="../../../../../org/apache/solr/util/SolrCLI.Tool.html" title="interface in org.apache.solr.util">SolrCLI.Tool</a> in <a href="../../../../../org/apache/solr/util/package-summary.html">org.apache.solr.util</a></h3>
<table border="0" cellpadding="3" cellspacing="0" summary="Use table, listing classes, and an explanation">
<caption><span>Classes in <a href="../../../../../org/apache/solr/util/package-summary.html">org.apache.solr.util</a> that implement <a href="../../../../../org/apache/solr/util/SolrCLI.Tool.html" title="interface in org.apache.solr.util">SolrCLI.Tool</a></span><span class="tabEnd"> </span></caption>
<tr>
<th class="colFirst" scope="col">Modifier and Type</th>
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<td class="colFirst"><code>static class </code></td>
<td class="colLast"><code><strong><a href="../../../../../org/apache/solr/util/SolrCLI.ApiTool.html" title="class in org.apache.solr.util">SolrCLI.ApiTool</a></strong></code>
<div class="block">Used to send an arbitrary HTTP request to a Solr API endpoint.</div>
</td>
</tr>
<tr class="rowColor">
<td class="colFirst"><code>static class </code></td>
<td class="colLast"><code><strong><a href="../../../../../org/apache/solr/util/SolrCLI.HealthcheckTool.html" title="class in org.apache.solr.util">SolrCLI.HealthcheckTool</a></strong></code>
<div class="block">Requests health information about a specific collection in SolrCloud.</div>
</td>
</tr>
<tr class="altColor">
<td class="colFirst"><code>static class </code></td>
<td class="colLast"><code><strong><a href="../../../../../org/apache/solr/util/SolrCLI.SolrCloudTool.html" title="class in org.apache.solr.util">SolrCLI.SolrCloudTool</a></strong></code>
<div class="block">Helps build SolrCloud aware tools by initializing a CloudSolrServer
instance before running the tool.</div>
</td>
</tr>
<tr class="rowColor">
<td class="colFirst"><code>static class </code></td>
<td class="colLast"><code><strong><a href="../../../../../org/apache/solr/util/SolrCLI.StatusTool.html" title="class in org.apache.solr.util">SolrCLI.StatusTool</a></strong></code>
<div class="block">Get the status of a Solr server.</div>
</td>
</tr>
</tbody>
</table>
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| {'content_hash': '3dfd831fe9c32f4a03950362aded81d0', 'timestamp': '', 'source': 'github', 'line_count': 195, 'max_line_length': 306, 'avg_line_length': 40.08717948717949, 'alnum_prop': 0.6270947933990022, 'repo_name': 'jamesvanmil/solr_config', 'id': 'cf61ada3f790cd2e83018c2c20bbb265eae60541', 'size': '7817', 'binary': False, 'copies': '2', 'ref': 'refs/heads/master', 'path': 'docs/solr-core/org/apache/solr/util/class-use/SolrCLI.Tool.html', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'CSS', 'bytes': '310805'}, {'name': 'JavaScript', 'bytes': '1019096'}, {'name': 'Shell', 'bytes': '70598'}, {'name': 'XSLT', 'bytes': '124615'}]} |
/**
* @file dohost.cpp
*
* Implementation of functions for THOST.
*
* @author Marian Cerny
*
* @date 2004
*/
//=========================================================================
// Included files
//=========================================================================
#include "cfg.h"
#include "doalloc.h"
#include <string>
#include "dohost.h"
#include "donet.h"
using std::string;
//=========================================================================
// THOST
//=========================================================================
THOST::THOST (int incoming_message_queue_size, in_port_t listen_port,
int outgoing_message_queue_size)
{
listener = NEW TNET_LISTENER (incoming_message_queue_size, listen_port);
talker = NEW TNET_TALKER (outgoing_message_queue_size);
handler = NEW TNET_MESSAGE_HANDLER ();
dispatcher = NEW TNET_DISPATCHER (listener->GetMessageQueue (), handler);
listener->ConsumerIsAttached (dispatcher->GetThread ());
}
/**
* Constructor.
*
* @param incoming_message_queue_size Size of queue for incoming messages.
* @param listen_port Port on which #listener should listen.
*/
THOST::THOST (int incoming_message_queue_size, in_port_t listen_port,
int outgoing_message_queue_size, in_addr remote_address,
in_port_t remote_port)
{
talker = NEW TNET_TALKER (outgoing_message_queue_size, remote_address,
remote_port);
listener = NEW TNET_LISTENER (incoming_message_queue_size, listen_port);
handler = NEW TNET_MESSAGE_HANDLER ();
dispatcher = NEW TNET_DISPATCHER (listener->GetMessageQueue (), handler);
listener->ConsumerIsAttached (dispatcher->GetThread ());
listener->AddListenerByFileDescriptor (remote_address, remote_port, talker->GetRemoteFiledescriptor (0));
}
THOST::~THOST ()
{
delete talker;
/* Order in which objects are deleted must be: listener, dispatcher, handler!
*/
delete listener;
delete dispatcher;
delete handler;
}
/**
* Sends chat message to all connected hosts.
*
* @param chat_message Message content.
*/
void THOST::SendChatMessage (string chat_message) {
TNET_MESSAGE *m = pool_net_messages->GetFromPool();
m->Init_send(net_protocol_chat_message, 0);
m->PackString (chat_message);
SendMessage (m);
}
/**
* Sends chat message to all connected hosts.
*
* @param chat_message Message content.
*/
void THOST::SendDisconnect (T_BYTE player_id) {
TNET_MESSAGE *m = pool_net_messages->GetFromPool();
m->Init_send(net_protocol_disconnect, 0);
m->PackByte (player_id);
SendMessage (m);
}
//=========================================================================
// END
//=========================================================================
// vim:ts=2:sw=2:et:
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'use strict';
var _ = require('lodash');
var moment = require('moment');
var ObjectID = require('bson-objectid');
module.exports = {
get: function * () {
var widgetId = this.params.widgetId;
var timePeriod = this.request.query.timePeriod;
var widgetsCollection = this.mongo.collection('monitor.widgets');
// Get the widget details
var widget = yield widgetsCollection.findOne({ _id: ObjectID(this.params.widgetId) });
var conditions = {
serviceId: widget.serviceId
};
if (widget.hostIds) {
conditions.hostId = { $in: widget.hostIds };
}
var chart = _.defaultsDeep(widget.chart, {
});
let stats = yield this.mongo.collection('monitor.stats.hourly').findOne(conditions, {
sort: { createdAt: -1 }
});
console.log('Stats:', stats);
this.status = 200;
this.body = chart;
}
} | {'content_hash': 'fdf6ed4a45dec3c376ef05be04fbf88a', 'timestamp': '', 'source': 'github', 'line_count': 38, 'max_line_length': 94, 'avg_line_length': 25.05263157894737, 'alnum_prop': 0.5756302521008403, 'repo_name': 'clusterfcuk/clusterfcuk-monitor', 'id': '7ea51e2d6effb046325a372494ddd0ea4c5f3a95', 'size': '952', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'src/ui/routes/ajax/pie.js', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '38'}, {'name': 'HTML', 'bytes': '1916'}, {'name': 'JavaScript', 'bytes': '1982328'}]} |
package org.apache.stratos.manager.user.management;
import org.apache.commons.logging.Log;
import org.apache.commons.logging.LogFactory;
import org.apache.stratos.common.beans.UserInfoBean;
import org.apache.stratos.manager.user.management.exception.UserManagerException;
import org.wso2.carbon.user.api.UserStoreException;
import org.wso2.carbon.user.api.UserStoreManager;
import org.wso2.carbon.user.core.UserCoreConstants;
import java.util.ArrayList;
import java.util.HashMap;
import java.util.List;
import java.util.Map;
/**
* This Class provides the operations related to adding/updating/deleting and listing users using
* the carbon UserStoreManager in the particular tenant space
* TODO : Update the util class to be able to support multiple roles for user
*/
public class StratosUserManagerUtils {
private transient static final Log log = LogFactory.getLog(StratosUserManagerUtils.class);
private static final String INTERNAL_EVERYONE_ROLE = "Internal/everyone";
private static final String GET_ALL_USERS_WILD_CARD = "*";
/**
* Add a user to the user-store of the particular tenant
*
* @param userStoreManager UserStoreManager
* @param userInfoBean UserInfoBean
* @throws UserManagerException
*/
public static void addUser(UserStoreManager userStoreManager, UserInfoBean userInfoBean)
throws UserManagerException {
if (log.isDebugEnabled()) {
log.debug("Creating new User: " + userInfoBean.getUserName());
}
String[] roles = new String[1];
roles[0] = userInfoBean.getRole();
Map<String, String> claims = new HashMap<String, String>();
//set firstname, lastname and email as user claims
claims.put(UserCoreConstants.ClaimTypeURIs.EMAIL_ADDRESS, userInfoBean.getEmail());
claims.put(UserCoreConstants.ClaimTypeURIs.GIVEN_NAME, userInfoBean.getFirstName());
claims.put(UserCoreConstants.ClaimTypeURIs.SURNAME, userInfoBean.getLastName());
try {
userStoreManager.addUser(userInfoBean.getUserName(), userInfoBean.getCredential(), roles, claims, userInfoBean.getProfileName());
} catch (UserStoreException e) {
String msg = "Error in adding user " + userInfoBean.getUserName() + " to User Store";
log.error(msg, e);
throw new UserManagerException(e.getMessage());
}
}
/**
* Delete the user with the given username in the relevant tenant space
*
* @param userStoreManager UserStoreManager
* @param userName UserName
* @throws UserManagerException
*/
public static void removeUser(UserStoreManager userStoreManager, String userName)
throws UserManagerException {
try {
if (userStoreManager.isExistingUser(userName)) {
userStoreManager.deleteUser(userName);
} else {
String msg = "Requested user " + userName + " does not exist";
throw new UserManagerException(msg);
}
} catch (UserStoreException e) {
String msg = "Error in deleting the user " + userName + " from User Store";
log.error(msg, e);
throw new UserManagerException(msg, e);
}
}
/**
* Updates the user info given the new UserInfoBean
*
* @param userStoreManager UserStoreManager
* @param userInfoBean UserInfoBean
* @throws UserManagerException
*/
public static void updateUser(UserStoreManager userStoreManager, UserInfoBean userInfoBean)
throws UserManagerException {
try {
if (userStoreManager.isExistingUser(userInfoBean.getUserName())) {
if (log.isDebugEnabled()) {
log.debug("Updating User " + userInfoBean.getUserName());
}
String[] newRoles = new String[1];
newRoles[0] = userInfoBean.getRole();
userStoreManager.updateRoleListOfUser(userInfoBean.getUserName(), getRefinedListOfRolesOfUser(userStoreManager, userInfoBean.getUserName()), newRoles);
userStoreManager.setUserClaimValue(userInfoBean.getUserName(), UserCoreConstants.ClaimTypeURIs.EMAIL_ADDRESS, userInfoBean.getEmail(), userInfoBean.getProfileName());
userStoreManager.setUserClaimValue(userInfoBean.getUserName(), UserCoreConstants.ClaimTypeURIs.GIVEN_NAME, userInfoBean.getFirstName(), userInfoBean.getProfileName());
userStoreManager.setUserClaimValue(userInfoBean.getUserName(), UserCoreConstants.ClaimTypeURIs.SURNAME, userInfoBean.getLastName(), userInfoBean.getProfileName());
userStoreManager.updateCredentialByAdmin(userInfoBean.getUserName(), userInfoBean.getCredential());
} else {
String msg = "Requested user " + userInfoBean.getUserName() + " does not exist";
throw new UserManagerException(msg);
}
} catch (UserStoreException e) {
String msg = "Error in updating the user " + userInfoBean.getUserName() + " in User Store";
log.error(msg, e);
throw new UserManagerException(msg, e);
}
}
/**
* Get a List of usernames and associated Roles as a UserInfoBean
*
* @param userStoreManager UserStoreManager
* @return List<UserInfoBean>
* @throws UserManagerException
*/
public static List<UserInfoBean> getAllUsers(UserStoreManager userStoreManager)
throws UserManagerException {
String[] users;
List<UserInfoBean> userList = new ArrayList<UserInfoBean>();
try {
users = userStoreManager.listUsers(GET_ALL_USERS_WILD_CARD, -1);
} catch (UserStoreException e) {
String msg = "Error in listing the users in User Store";
log.error(msg, e);
throw new UserManagerException(msg, e);
}
//Iterate through the list of users and retrieve their roles
for (String user : users) {
UserInfoBean userInfoBean = new UserInfoBean();
userInfoBean.setUserName(user);
String[] refinedListOfRolesOfUser = getRefinedListOfRolesOfUser(userStoreManager, user);
//TODO : Should support multiple roles for user
if (refinedListOfRolesOfUser.length != 0) {
userInfoBean.setRole(getRefinedListOfRolesOfUser(userStoreManager, user)[0]);
} else {
userInfoBean.setRole(INTERNAL_EVERYONE_ROLE);
}
userList.add(userInfoBean);
}
return userList;
}
/**
* Get the List of userRoles except the Internal/everyone role
*
* @param userStoreManager UserStoreManager
* @param username Username of the user
* @return String[]
* @throws UserManagerException
*/
private static String[] getRefinedListOfRolesOfUser(UserStoreManager userStoreManager, String username)
throws UserManagerException {
ArrayList<String> rolesWithoutEveryoneRole = new ArrayList<String>();
try {
String[] allUserRoles = userStoreManager.getRoleListOfUser(username);
for (String role : allUserRoles) {
if (!role.equals(INTERNAL_EVERYONE_ROLE)) {
rolesWithoutEveryoneRole.add(role);
}
}
String[] rolesWithoutEveryoneRoleArray = new String[rolesWithoutEveryoneRole.size()];
return rolesWithoutEveryoneRole.toArray(rolesWithoutEveryoneRoleArray);
} catch (UserStoreException e) {
String msg = "Error in listing the roles of user " + username + " in User Store";
log.error(msg, e);
throw new UserManagerException(msg, e);
}
}
}
| {'content_hash': '03725500df1abe8081b5c717e9e7c532', 'timestamp': '', 'source': 'github', 'line_count': 191, 'max_line_length': 183, 'avg_line_length': 41.1413612565445, 'alnum_prop': 0.6572919317892594, 'repo_name': 'dinithis/stratos', 'id': '06fcfb7734c2953a29108ef5bb8e4f23ee013701', 'size': '8664', 'binary': False, 'copies': '7', 'ref': 'refs/heads/master', 'path': 'components/org.apache.stratos.manager/src/main/java/org/apache/stratos/manager/user/management/StratosUserManagerUtils.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'Batchfile', 'bytes': '17184'}, {'name': 'C', 'bytes': '27195'}, {'name': 'CSS', 'bytes': '71867'}, {'name': 'HTML', 'bytes': '7586'}, {'name': 'Handlebars', 'bytes': '136406'}, {'name': 'Java', 'bytes': '5946275'}, {'name': 'JavaScript', 'bytes': '743237'}, {'name': 'Python', 'bytes': '518762'}, {'name': 'Ruby', 'bytes': '3546'}, {'name': 'Shell', 'bytes': '124630'}]} |
"""
Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
"""
from resource_management import *
from kafka_handler import kafka
class Kafka(Script):
def install(self, env):
#import params
self.install_packages(env)
#env.set_params(params)
#self.configure(env)
def start(self, env):
import params
env.set_params(params)
self.configure(env)
kafka(action='start')
def stop(self, env):
import params
env.set_params(params)
kafka(action='stop')
def configure(self, env):
import params
env.set_params(params)
kafka(action='config')
def status(self, env):
kafka(action='status')
if __name__ == "__main__":
Kafka().execute()
| {'content_hash': '0195768ed48deec3e76ec37096a5c1cd', 'timestamp': '', 'source': 'github', 'line_count': 54, 'max_line_length': 72, 'avg_line_length': 26.055555555555557, 'alnum_prop': 0.7249466950959488, 'repo_name': 'keedio/keedio-stacks', 'id': '021e0df3156f44d3aec2fa08969eb5fa1922e81f', 'size': '1407', 'binary': False, 'copies': '1', 'ref': 'refs/heads/development', 'path': 'KEEDIO/1.1/services/KAFKA/package/scripts/kafka.py', 'mode': '33261', 'license': 'apache-2.0', 'language': [{'name': 'Makefile', 'bytes': '386'}, {'name': 'Python', 'bytes': '1080418'}, {'name': 'Shell', 'bytes': '50473'}]} |
.bootstrap-select.btn-group:not(.input-group-btn),
.bootstrap-select.btn-group[class*="span"] {
float: none;
display: inline-block;
margin-bottom: 10px;
margin-left: 0;
}
.form-search .bootstrap-select.btn-group,
.form-inline .bootstrap-select.btn-group,
.form-horizontal .bootstrap-select.btn-group {
margin-bottom: 0;
}
.bootstrap-select.form-control {
margin-bottom: 0;
padding: 0;
border: none;
}
.bootstrap-select.btn-group.pull-right,
.bootstrap-select.btn-group[class*="span"].pull-right,
.row-fluid .bootstrap-select.btn-group[class*="span"].pull-right {
float: right;
}
.input-append .bootstrap-select.btn-group {
margin-left: -1px;
}
.input-prepend .bootstrap-select.btn-group {
margin-right: -1px;
}
.bootstrap-select:not([class*="span"]):not([class*="col-"]):not([class*="form-control"]):not(.input-group-btn) {
width: 220px;
}
.bootstrap-select {
/*width: 220px\9; IE8 and below*/
width: 220px\0; /*IE9 and below*/
}
.bootstrap-select.form-control:not([class*="span"]) {
width: 100%;
}
.bootstrap-select > .btn {
width: 100%;
padding-right: 25px;
}
.error .bootstrap-select .btn {
/*border: 1px solid #b94a48;*/
}
.bootstrap-select.show-menu-arrow.open > .btn {
z-index: 2051;
}
.bootstrap-select .btn:focus {
/*outline: thin dotted #333333 !important;
outline: 5px auto -webkit-focus-ring-color !important;
outline-offset: -2px;*/
}
.bootstrap-select.btn-group .btn .filter-option {
display: inline-block;
overflow: hidden;
width: 100%;
float: left;
text-align: left;
}
.bootstrap-select.btn-group .btn .caret {
position: absolute;
top: 50%;
right: 12px;
margin-top: -2px;
vertical-align: middle;
}
.bootstrap-select.btn-group > .disabled,
.bootstrap-select.btn-group .dropdown-menu li.disabled > a {
cursor: not-allowed;
}
.bootstrap-select.btn-group > .disabled:focus {
outline: none !important;
}
.bootstrap-select.btn-group[class*="span"] .btn {
width: 100%;
}
.bootstrap-select.btn-group .dropdown-menu {
min-width: 100%;
z-index: 2000;
-webkit-box-sizing: border-box;
-moz-box-sizing: border-box;
box-sizing: border-box;
}
.bootstrap-select.btn-group .dropdown-menu.inner {
position: static;
border: 0;
padding: 0;
margin: 0;
-webkit-border-radius: 0;
-moz-border-radius: 0;
border-radius: 0;
-webkit-box-shadow: none;
-moz-box-shadow: none;
box-shadow: none;
}
.bootstrap-select.btn-group .dropdown-menu dt {
display: block;
padding: 3px 20px;
cursor: default;
}
.bootstrap-select.btn-group .div-contain {
overflow: hidden;
}
.bootstrap-select.btn-group .dropdown-menu li {
position: relative;
}
.bootstrap-select.btn-group .dropdown-menu li > a.opt {
position: relative;
padding-left: 35px;
}
.bootstrap-select.btn-group .dropdown-menu li > a {
cursor: pointer;
}
.bootstrap-select.btn-group .dropdown-menu li > dt small {
font-weight: normal;
}
.bootstrap-select.btn-group.show-tick .dropdown-menu li.selected a i.check-mark {
position: absolute;
display: inline-block;
right: 15px;
margin-top: 2.5px;
}
.bootstrap-select.btn-group .dropdown-menu li a i.check-mark {
display: none;
}
.bootstrap-select.btn-group.show-tick .dropdown-menu li a span.text {
margin-right: 34px;
}
.bootstrap-select.btn-group .dropdown-menu li small {
padding-left: 0.5em;
}
.bootstrap-select.btn-group .dropdown-menu li:not(.disabled) > a:hover small,
.bootstrap-select.btn-group .dropdown-menu li:not(.disabled) > a:focus small,
.bootstrap-select.btn-group .dropdown-menu li.active:not(.disabled) > a small {
color: #64b1d8;
color: rgba(255,255,255,0.4);
}
.bootstrap-select.btn-group .dropdown-menu li > dt small {
font-weight: normal;
}
.bootstrap-select.show-menu-arrow .dropdown-toggle:before {
content: '';
display: inline-block;
border-left: 7px solid transparent;
border-right: 7px solid transparent;
border-bottom: 7px solid #CCC;
border-bottom-color: rgba(0, 0, 0, 0.2);
position: absolute;
bottom: -4px;
left: 9px;
display: none;
}
.bootstrap-select.show-menu-arrow .dropdown-toggle:after {
content: '';
display: inline-block;
border-left: 6px solid transparent;
border-right: 6px solid transparent;
border-bottom: 6px solid white;
position: absolute;
bottom: -4px;
left: 10px;
display: none;
}
.bootstrap-select.show-menu-arrow.dropup .dropdown-toggle:before {
bottom: auto;
top: -3px;
border-top: 7px solid #ccc;
border-bottom: 0;
border-top-color: rgba(0, 0, 0, 0.2);
}
.bootstrap-select.show-menu-arrow.dropup .dropdown-toggle:after {
bottom: auto;
top: -3px;
border-top: 6px solid #ffffff;
border-bottom: 0;
}
.bootstrap-select.show-menu-arrow.pull-right .dropdown-toggle:before {
right: 12px;
left: auto;
}
.bootstrap-select.show-menu-arrow.pull-right .dropdown-toggle:after {
right: 13px;
left: auto;
}
.bootstrap-select.show-menu-arrow.open > .dropdown-toggle:before,
.bootstrap-select.show-menu-arrow.open > .dropdown-toggle:after {
display: block;
}
.bootstrap-select.btn-group .no-results {
padding: 3px;
background: #f5f5f5;
margin: 0 5px;
}
.bootstrap-select.btn-group .dropdown-menu .notify {
position: absolute;
bottom: 5px;
width: 96%;
margin: 0 2%;
min-height: 26px;
padding: 3px 5px;
background: #f5f5f5;
border: 1px solid #e3e3e3;
/*box-shadow: inset 0 1px 1px rgba(0,0,0,0.05);*/
pointer-events: none;
opacity: 0.9;
-webkit-box-sizing: border-box;
-moz-box-sizing: border-box;
box-sizing: border-box;
}
.mobile-device {
position: absolute;
top: 0;
left: 0;
display: block !important;
width: 100%;
height: 100% !important;
opacity: 0;
}
.bootstrap-select.fit-width {
width: auto !important;
}
.bootstrap-select.btn-group.fit-width .btn .filter-option {
position: static;
}
.bootstrap-select.btn-group.fit-width .btn .caret {
position: static;
top: auto;
margin-top: -1px;
}
.control-group.error .bootstrap-select .dropdown-toggle{
/*border-color: #b94a48;*/
}
.bootstrap-select-searchbox,
.bootstrap-select .bs-actionsbox {
padding: 4px 8px;
}
.bootstrap-select .bs-actionsbox {
float: left;
width: 100%;
-webkit-box-sizing: border-box;
-moz-box-sizing: border-box;
box-sizing: border-box;
}
.bootstrap-select-searchbox + .bs-actionsbox {
padding: 0 8px 4px;
}
.bootstrap-select-searchbox input {
margin-bottom: 0;
}
.bootstrap-select .bs-actionsbox .btn-group button {
width: 50%;
} | {'content_hash': 'e0af12ed4f241d8fd6a31826f60dde9c', 'timestamp': '', 'source': 'github', 'line_count': 303, 'max_line_length': 112, 'avg_line_length': 22.38943894389439, 'alnum_prop': 0.6563974056603774, 'repo_name': 'juano-/nutrem', 'id': '79095c679feb379529ccdad6e0d2ecc1fa8f9a28', 'size': '6941', 'binary': False, 'copies': '4', 'ref': 'refs/heads/master', 'path': 'web-assets/assets/css/plugins/select/bootstrap-select.css', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'ApacheConf', 'bytes': '240'}, {'name': 'CSS', 'bytes': '62808'}, {'name': 'HTML', 'bytes': '8429724'}, {'name': 'JavaScript', 'bytes': '265266'}, {'name': 'PHP', 'bytes': '1784330'}]} |
module PublicActivity
# Main module extending classes we want to keep track of.
module Tracked
extend ActiveSupport::Concern
# A shortcut method for setting custom key, owner and parameters of {Activity}
# in one line. Accepts a hash with 3 keys:
# :key, :owner, :params. You can specify all of them or just the ones you want to overwrite.
#
# == Options
#
# [:key]
# See {Common#activity_key}
# [:owner]
# See {Common#activity_owner}
# [:params]
# See {Common#activity_params}
# [:recipient]
# Set the recipient for this activity. Useful for private notifications, which should only be visible to a certain user. See {Common#activity_recipient}.
# @example
#
# @article = Article.new
# @article.title = "New article"
# @article.activity :key => "my.custom.article.key", :owner => @article.author, :params => {:title => @article.title}
# @article.save
# @article.activities.last.key #=> "my.custom.article.key"
# @article.activities.last.parameters #=> {:title => "New article"}
#
# @param options [Hash] instance options to set on the tracked model
# @return [nil]
def activity(options = {})
rest = options.clone
self.activity_key = rest.delete(:key) if rest[:key]
self.activity_owner = rest.delete(:owner) if rest[:owner]
self.activity_params = rest.delete(:params) if rest[:params]
self.activity_recipient = rest.delete(:recipient) if rest[:recipient]
self.activity_custom_fields = rest if rest.count > 0
nil
end
# Module with basic +tracked+ method that enables tracking models.
module ClassMethods
# Adds required callbacks for creating and updating
# tracked models and adds +activities+ relation for listing
# associated activities.
#
# == Parameters:
# [:owner]
# Specify the owner of the {Activity} (person responsible for the action).
# It can be a Proc, Symbol or an ActiveRecord object:
# == Examples:
#
# tracked :owner => :author
# tracked :owner => proc {|o| o.author}
#
# Keep in mind that owner relation is polymorphic, so you can't just
# provide id number of the owner object.
# [:recipient]
# Specify the recipient of the {Activity}
# It can be a Proc, Symbol, or an ActiveRecord object
# == Examples:
#
# tracked :recipient => :author
# tracked :recipient => proc {|o| o.author}
#
# Keep in mind that recipient relation is polymorphic, so you can't just
# provide id number of the owner object.
# [:params]
# Accepts a Hash with custom parameters you want to pass to i18n.translate
# method. It is later used in {Renderable#text} method.
# == Example:
# class Article < ActiveRecord::Base
# include PublicActivity::Model
# tracked :params => {
# :title => :title,
# :author_name => "Michael",
# :category_name => proc {|controller, model_instance| model_instance.category.name},
# :summary => proc {|controller, model_instance| truncate(model.text, :length => 30)}
# }
# end
#
# Values in the :params hash can either be an *exact* *value*, a *Proc/Lambda* executed before saving the activity or a *Symbol*
# which is a an attribute or a method name executed on the tracked model's instance.
#
# Everything specified here has a lower priority than parameters
# specified directly in {#activity} method.
# So treat it as a place where you provide 'default' values or where you
# specify what data should be gathered for every activity.
# For more dynamic settings refer to {Activity} model documentation.
# [:skip_defaults]
# Disables recording of activities on create/update/destroy leaving that to programmer's choice. Check {PublicActivity::Common#create_activity}
# for a guide on how to manually record activities.
# [:only]
# Accepts a symbol or an array of symbols, of which any combination of the three is accepted:
# * _:create_
# * _:update_
# * _:destroy_
# Selecting one or more of these will make PublicActivity create activities
# automatically for the tracked model on selected actions.
#
# Resulting activities will have have keys assigned to, respectively:
# * _article.create_
# * _article.update_
# * _article.destroy_
# Since only three options are valid,
# see _:except_ option for a shorter version
# [:except]
# Accepts a symbol or an array of symbols with values like in _:only_, above.
# Values provided will be subtracted from all default actions:
# (create, update, destroy).
#
# So, passing _create_ would track and automatically create
# activities on _update_ and _destroy_ actions,
# but not on the _create_ action.
# [:on]
# Accepts a Hash with key being the *action* on which to execute *value* (proc)
# Currently supported only for CRUD actions which are enabled in _:only_
# or _:except_ options on this method.
#
# Key-value pairs in this option define callbacks that can decide
# whether to create an activity or not. Procs have two attributes for
# use: _model_ and _controller_. If the proc returns true, the activity
# will be created, if not, then activity will not be saved.
#
# == Example:
# # app/models/article.rb
# tracked :on => {:update => proc {|model, controller| model.published? }}
#
# In the example above, given a model Article with boolean column _published_.
# The activities with key _article.update_ will only be created
# if the published status is set to true on that article.
# @param opts [Hash] options
# @return [nil] options
def tracked(opts = {})
options = opts.clone
all_options = [:create, :update, :destroy]
if !options.has_key?(:skip_defaults) && !options[:only] && !options[:except]
include Creation
include Destruction
include Update
end
options.delete(:skip_defaults)
if options[:except]
options[:only] = all_options - Array(options.delete(:except))
end
if options[:only]
Array(options[:only]).each do |opt|
if opt.eql?(:create)
include Creation
elsif opt.eql?(:destroy)
include Destruction
elsif opt.eql?(:update)
include Update
end
end
options.delete(:only)
end
if options[:owner]
self.activity_owner_global = options.delete(:owner)
end
if options[:recipient]
self.activity_recipient_global = options.delete(:recipient)
end
if options[:params]
self.activity_params_global = options.delete(:params)
end
if options.has_key?(:on) and options[:on].is_a? Hash
self.activity_hooks = options.delete(:on).select {|_, v| v.is_a? Proc}.symbolize_keys
end
options.each do |k, v|
self.activity_custom_fields_global[k] = v
end
nil
end
end
end
end
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package io.reactivex.rxjava3.internal.operators.flowable;
import static org.junit.Assert.fail;
import static org.mockito.ArgumentMatchers.any;
import static org.mockito.Mockito.*;
import java.util.List;
import org.junit.*;
import org.reactivestreams.*;
import io.reactivex.rxjava3.core.*;
import io.reactivex.rxjava3.exceptions.TestException;
import io.reactivex.rxjava3.functions.*;
import io.reactivex.rxjava3.internal.functions.Functions;
import io.reactivex.rxjava3.internal.subscriptions.BooleanSubscription;
import io.reactivex.rxjava3.plugins.RxJavaPlugins;
import io.reactivex.rxjava3.processors.*;
import io.reactivex.rxjava3.subscribers.TestSubscriber;
import io.reactivex.rxjava3.testsupport.*;
public class FlowableTakeWhileTest extends RxJavaTest {
@Test
public void takeWhile1() {
Flowable<Integer> w = Flowable.just(1, 2, 3);
Flowable<Integer> take = w.takeWhile(new Predicate<Integer>() {
@Override
public boolean test(Integer input) {
return input < 3;
}
});
Subscriber<Integer> subscriber = TestHelper.mockSubscriber();
take.subscribe(subscriber);
verify(subscriber, times(1)).onNext(1);
verify(subscriber, times(1)).onNext(2);
verify(subscriber, never()).onNext(3);
verify(subscriber, never()).onError(any(Throwable.class));
verify(subscriber, times(1)).onComplete();
}
@Test
public void takeWhileOnSubject1() {
FlowableProcessor<Integer> s = PublishProcessor.create();
Flowable<Integer> take = s.takeWhile(new Predicate<Integer>() {
@Override
public boolean test(Integer input) {
return input < 3;
}
});
Subscriber<Integer> subscriber = TestHelper.mockSubscriber();
take.subscribe(subscriber);
s.onNext(1);
s.onNext(2);
s.onNext(3);
s.onNext(4);
s.onNext(5);
s.onComplete();
verify(subscriber, times(1)).onNext(1);
verify(subscriber, times(1)).onNext(2);
verify(subscriber, never()).onNext(3);
verify(subscriber, never()).onNext(4);
verify(subscriber, never()).onNext(5);
verify(subscriber, never()).onError(any(Throwable.class));
verify(subscriber, times(1)).onComplete();
}
@Test
public void takeWhile2() {
Flowable<String> w = Flowable.just("one", "two", "three");
Flowable<String> take = w.takeWhile(new Predicate<String>() {
int index;
@Override
public boolean test(String input) {
return index++ < 2;
}
});
Subscriber<String> subscriber = TestHelper.mockSubscriber();
take.subscribe(subscriber);
verify(subscriber, times(1)).onNext("one");
verify(subscriber, times(1)).onNext("two");
verify(subscriber, never()).onNext("three");
verify(subscriber, never()).onError(any(Throwable.class));
verify(subscriber, times(1)).onComplete();
}
@Test
public void takeWhileDoesntLeakErrors() {
List<Throwable> errors = TestHelper.trackPluginErrors();
try {
Flowable<String> source = Flowable.unsafeCreate(new Publisher<String>() {
@Override
public void subscribe(Subscriber<? super String> subscriber) {
subscriber.onSubscribe(new BooleanSubscription());
subscriber.onNext("one");
subscriber.onError(new TestException("test failed"));
}
});
source.takeWhile(new Predicate<String>() {
@Override
public boolean test(String s) {
return false;
}
}).blockingLast("");
TestHelper.assertUndeliverable(errors, 0, TestException.class, "test failed");
} finally {
RxJavaPlugins.reset();
}
}
@Test
public void takeWhileProtectsPredicateCall() {
TestFlowable source = new TestFlowable(mock(Subscription.class), "one");
final RuntimeException testException = new RuntimeException("test exception");
Subscriber<String> subscriber = TestHelper.mockSubscriber();
Flowable<String> take = Flowable.unsafeCreate(source)
.takeWhile(new Predicate<String>() {
@Override
public boolean test(String s) {
throw testException;
}
});
take.subscribe(subscriber);
// wait for the Flowable to complete
try {
source.t.join();
} catch (Throwable e) {
e.printStackTrace();
fail(e.getMessage());
}
verify(subscriber, never()).onNext(any(String.class));
verify(subscriber, times(1)).onError(testException);
}
@Test
public void unsubscribeAfterTake() {
Subscription s = mock(Subscription.class);
TestFlowable w = new TestFlowable(s, "one", "two", "three");
Subscriber<String> subscriber = TestHelper.mockSubscriber();
Flowable<String> take = Flowable.unsafeCreate(w)
.takeWhile(new Predicate<String>() {
int index;
@Override
public boolean test(String s) {
return index++ < 1;
}
});
take.subscribe(subscriber);
// wait for the Flowable to complete
try {
w.t.join();
} catch (Throwable e) {
e.printStackTrace();
fail(e.getMessage());
}
System.out.println("TestFlowable thread finished");
verify(subscriber, times(1)).onNext("one");
verify(subscriber, never()).onNext("two");
verify(subscriber, never()).onNext("three");
verify(s, times(1)).cancel();
}
private static class TestFlowable implements Publisher<String> {
final Subscription upstream;
final String[] values;
Thread t;
TestFlowable(Subscription s, String... values) {
this.upstream = s;
this.values = values;
}
@Override
public void subscribe(final Subscriber<? super String> subscriber) {
System.out.println("TestFlowable subscribed to ...");
subscriber.onSubscribe(upstream);
t = new Thread(new Runnable() {
@Override
public void run() {
try {
System.out.println("running TestFlowable thread");
for (String s : values) {
System.out.println("TestFlowable onNext: " + s);
subscriber.onNext(s);
}
subscriber.onComplete();
} catch (Throwable e) {
throw new RuntimeException(e);
}
}
});
System.out.println("starting TestFlowable thread");
t.start();
System.out.println("done starting TestFlowable thread");
}
}
@Test
public void backpressure() {
Flowable<Integer> source = Flowable.range(1, 1000).takeWhile(new Predicate<Integer>() {
@Override
public boolean test(Integer t1) {
return t1 < 100;
}
});
TestSubscriber<Integer> ts = new TestSubscriber<>(5L);
source.subscribe(ts);
ts.assertNoErrors();
ts.assertValues(1, 2, 3, 4, 5);
ts.request(5);
ts.assertNoErrors();
ts.assertValues(1, 2, 3, 4, 5, 6, 7, 8, 9, 10);
}
@Test
public void noUnsubscribeDownstream() {
Flowable<Integer> source = Flowable.range(1, 1000).takeWhile(new Predicate<Integer>() {
@Override
public boolean test(Integer t1) {
return t1 < 2;
}
});
TestSubscriber<Integer> ts = new TestSubscriber<>();
source.subscribe(ts);
ts.assertNoErrors();
ts.assertValue(1);
Assert.assertFalse("Unsubscribed!", ts.isCancelled());
}
@Test
public void errorCauseIncludesLastValue() {
TestSubscriberEx<String> ts = new TestSubscriberEx<>();
Flowable.just("abc").takeWhile(new Predicate<String>() {
@Override
public boolean test(String t1) {
throw new TestException();
}
}).subscribe(ts);
ts.assertTerminated();
ts.assertNoValues();
ts.assertError(TestException.class);
// FIXME last cause value not recorded
// assertTrue(ts.getOnErrorEvents().get(0).getCause().getMessage().contains("abc"));
}
@Test
public void dispose() {
TestHelper.checkDisposed(PublishProcessor.create().takeWhile(Functions.alwaysTrue()));
}
@Test
public void doubleOnSubscribe() {
TestHelper.checkDoubleOnSubscribeFlowable(new Function<Flowable<Object>, Flowable<Object>>() {
@Override
public Flowable<Object> apply(Flowable<Object> f) throws Exception {
return f.takeWhile(Functions.alwaysTrue());
}
});
}
@Test
public void badSource() {
new Flowable<Integer>() {
@Override
protected void subscribeActual(Subscriber<? super Integer> subscriber) {
subscriber.onSubscribe(new BooleanSubscription());
subscriber.onComplete();
subscriber.onComplete();
}
}
.takeWhile(Functions.alwaysTrue())
.test()
.assertResult();
}
}
| {'content_hash': '5cccd9a1c1e98a981d1a348bfd7cf00c', 'timestamp': '', 'source': 'github', 'line_count': 306, 'max_line_length': 102, 'avg_line_length': 31.9281045751634, 'alnum_prop': 0.5696008188331627, 'repo_name': 'reactivex/rxjava', 'id': '805420f094c10d4168d654251038ec827e4e6eb4', 'size': '10373', 'binary': False, 'copies': '2', 'ref': 'refs/heads/3.x', 'path': 'src/test/java/io/reactivex/rxjava3/internal/operators/flowable/FlowableTakeWhileTest.java', 'mode': '33188', 'license': 'apache-2.0', 'language': [{'name': 'CSS', 'bytes': '12875'}, {'name': 'Java', 'bytes': '16361730'}, {'name': 'Shell', 'bytes': '3148'}]} |
using namespace Gaffer;
using namespace GafferScene;
using namespace Imath;
static IECore::InternedString g_camerasSetName( "__cameras" );
IE_CORE_DEFINERUNTIMETYPED( Camera );
size_t Camera::g_firstPlugIndex = 0;
Camera::Camera( const std::string &name )
: ObjectSource( name, "camera" )
{
storeIndexOfNextChild( g_firstPlugIndex );
addChild( new StringPlug( "projection", Plug::In, "perspective" ) );
addChild( new FloatPlug( "fieldOfView", Plug::In, 50.0f, 0.0f, 180.0f ) );
addChild( new V2fPlug( "clippingPlanes", Plug::In, V2f( 0.01, 100000 ), V2f( 0 ) ) );
}
Camera::~Camera()
{
}
Gaffer::StringPlug *Camera::projectionPlug()
{
return getChild<StringPlug>( g_firstPlugIndex );
}
const Gaffer::StringPlug *Camera::projectionPlug() const
{
return getChild<StringPlug>( g_firstPlugIndex );
}
Gaffer::FloatPlug *Camera::fieldOfViewPlug()
{
return getChild<FloatPlug>( g_firstPlugIndex + 1 );
}
const Gaffer::FloatPlug *Camera::fieldOfViewPlug() const
{
return getChild<FloatPlug>( g_firstPlugIndex + 1 );
}
Gaffer::V2fPlug *Camera::clippingPlanesPlug()
{
return getChild<V2fPlug>( g_firstPlugIndex + 2 );
}
const Gaffer::V2fPlug *Camera::clippingPlanesPlug() const
{
return getChild<V2fPlug>( g_firstPlugIndex + 2 );
}
void Camera::affects( const Plug *input, AffectedPlugsContainer &outputs ) const
{
ObjectSource::affects( input, outputs );
if(
input == projectionPlug() ||
input == fieldOfViewPlug() ||
input->parent<Plug>() == clippingPlanesPlug()
)
{
outputs.push_back( sourcePlug() );
}
}
void Camera::hashSource( const Gaffer::Context *context, IECore::MurmurHash &h ) const
{
projectionPlug()->hash( h );
fieldOfViewPlug()->hash( h );
clippingPlanesPlug()->hash( h );
}
IECore::ConstObjectPtr Camera::computeSource( const Context *context ) const
{
IECore::CameraPtr result = new IECore::Camera;
result->parameters()["projection"] = new IECore::StringData( projectionPlug()->getValue() );
result->parameters()["projection:fov"] = new IECore::FloatData( fieldOfViewPlug()->getValue() );
result->parameters()["clippingPlanes"] = new IECore::V2fData( clippingPlanesPlug()->getValue() );
return result;
}
IECore::InternedString Camera::standardSetName() const
{
return g_camerasSetName;
}
| {'content_hash': '08100845529aa55d995c106cee746100', 'timestamp': '', 'source': 'github', 'line_count': 87, 'max_line_length': 98, 'avg_line_length': 25.816091954022987, 'alnum_prop': 0.7163846838824577, 'repo_name': 'goddardl/gaffer', 'id': '6a20dbd8e9f83e158df365d92d438806ba09fcc0', 'size': '4304', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'src/GafferScene/Camera.cpp', 'mode': '33188', 'license': 'bsd-3-clause', 'language': [{'name': 'C', 'bytes': '2228'}, {'name': 'C++', 'bytes': '4178625'}, {'name': 'GLSL', 'bytes': '6250'}, {'name': 'Python', 'bytes': '4152621'}, {'name': 'Shell', 'bytes': '8787'}, {'name': 'Slash', 'bytes': '36371'}]} |
using System;
using System.IO;
using JetBrains.Annotations;
namespace AldursLab.WurmAssistant.Launcher.Modules
{
public interface IDebug
{
void Write(string text);
void Clear();
}
public class TextDebug : IDebug
{
readonly string filePath;
public TextDebug([NotNull] string filePath)
{
if (filePath == null) throw new ArgumentNullException("filePath");
this.filePath = filePath;
}
public void Write(string text)
{
File.AppendAllText(filePath, text);
}
public void Clear()
{
if (File.Exists(filePath)) File.Delete(filePath);
}
}
}
| {'content_hash': 'd5b1734a037531e9d67d3a54909d8c19', 'timestamp': '', 'source': 'github', 'line_count': 33, 'max_line_length': 78, 'avg_line_length': 21.333333333333332, 'alnum_prop': 0.5767045454545454, 'repo_name': 'mdsolver/WurmAssistant3', 'id': '8fb050a15a952f8b855206bf27ac2853f0413166', 'size': '706', 'binary': False, 'copies': '3', 'ref': 'refs/heads/master', 'path': 'src/Launchers/LauncherV2/WurmAssistant.Launcher/Modules/TextDebug.cs', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'ASP', 'bytes': '127'}, {'name': 'Batchfile', 'bytes': '664'}, {'name': 'C#', 'bytes': '4528738'}, {'name': 'CSS', 'bytes': '4494'}, {'name': 'HTML', 'bytes': '8586'}, {'name': 'JavaScript', 'bytes': '19429'}, {'name': 'PowerShell', 'bytes': '139'}, {'name': 'Shell', 'bytes': '1508'}]} |
from __future__ import division
import simpy
from numpy import random
__all__ = ['Attacker', 'Malware']
NOMINAL_TIME_TO_LEARN = 10
class Attacker(SimpyMixin, object):
"""
A cyber attacker entity.
:param env:
:param competency:
:param associates:
:type env:
:type competency:
:type associates:
:func scan:
:func attack:
"""
def __init__(self, competency=0.5, associates=None,
vulnerability_manager=None, known_vulnerabilities=None, *args, **kwargs):
super(Attacker, self).__init__(*args, **kwargs)
self.competency = competency
self.associates = [] if associates is None else associates
self.vulnerability_manager = vulnerability_manager
self.targets = self.filter_store()
self.known_vulnerabilities = self.filter_store()
if instance(known_vulnerabilities, list):
for vulnerability in known_vulnerabilities:
_ = yield self.known_vulnerabilities(vulnerability)
self.scanning = self.process(self.scan())
self.attacking = self.process(self.attack())
self.learning = self.process(self.learn())
def scan(self):
""" Scan for potential targets. """
while True:
# Scan for a target
def attack(self, target):
""" Attack a target """
while True:
pass
#
def learn(self):
""" Learn new vulnerabilities """
while True:
_ = yield self.timeout(NOMINAL_TIME_TO_LEARN / self.competence ** 4)
zero_days = [v for v in self.vulnerability_manager.vulnerabilities.items if v.zero_day]
_ = yield self.process(add_vulnerability(random.choice(zero_days)))
def add_vulnerability(self, vulnerability):
_ = yield self.known_vulnerabilities.put(vulnerability)
class Malware(SimpyMixin, object):
"""
Malware that can spread through a network (e.g., virus, trojan, worm).
:param owner: attacker that owns the malware
:param controllable: whether or not the malware is controllable by the owner
:type owner: :class:`dacdam.attacker.Attacker`
:type controllable: bool
"""
def __init__(self, owner=None, controllable=False, *args, **kwargs):
super(Malware, self).__init__(*args, **kwargs)
self.owner = owner
self.controllable = controllable
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from __future__ import with_statement
import codecs, datetime, glob, os, sys, textwrap
import FileGenerator
def FindModules(lexFile):
modules = []
with open(lexFile) as f:
for l in f.readlines():
if l.startswith("LexerModule"):
l = l.replace("(", " ")
modules.append(l.split()[1])
return modules
# Properties that start with lexer. or fold. are automatically found but there are some
# older properties that don't follow this pattern so must be explicitly listed.
knownIrregularProperties = [
"fold",
"styling.within.preprocessor",
"tab.timmy.whinge.level",
"asp.default.language",
"html.tags.case.sensitive",
"ps.level",
"ps.tokenize",
"sql.backslash.escapes",
"nsis.uservars",
"nsis.ignorecase"
]
def FindProperties(lexFile):
properties = {}
with open(lexFile) as f:
for l in f.readlines():
if ("GetProperty" in l or "DefineProperty" in l) and "\"" in l:
l = l.strip()
if not l.startswith("//"): # Drop comments
propertyName = l.split("\"")[1]
if propertyName.lower() == propertyName:
# Only allow lower case property names
if propertyName in knownIrregularProperties or \
propertyName.startswith("fold.") or \
propertyName.startswith("lexer."):
properties[propertyName] = 1
return properties
def FindPropertyDocumentation(lexFile):
documents = {}
with open(lexFile) as f:
name = ""
for l in f.readlines():
l = l.strip()
if "// property " in l:
propertyName = l.split()[2]
if propertyName.lower() == propertyName:
# Only allow lower case property names
name = propertyName
documents[name] = ""
elif "DefineProperty" in l and "\"" in l:
propertyName = l.split("\"")[1]
if propertyName.lower() == propertyName:
# Only allow lower case property names
name = propertyName
documents[name] = ""
elif name:
if l.startswith("//"):
if documents[name]:
documents[name] += " "
documents[name] += l[2:].strip()
elif l.startswith("\""):
l = l[1:].strip()
if l.endswith(";"):
l = l[:-1].strip()
if l.endswith(")"):
l = l[:-1].strip()
if l.endswith("\""):
l = l[:-1]
# Fix escaped double quotes
l = l.replace("\\\"", "\"")
documents[name] += l
else:
name = ""
for name in list(documents.keys()):
if documents[name] == "":
del documents[name]
return documents
def FindCredits(historyFile):
credits = []
stage = 0
with codecs.open(historyFile, "r", "utf-8") as f:
for l in f.readlines():
l = l.strip()
if stage == 0 and l == "<table>":
stage = 1
elif stage == 1 and l == "</table>":
stage = 2
if stage == 1 and l.startswith("<td>"):
credit = l[4:-5]
if "<a" in l:
title, a, rest = credit.partition("<a href=")
urlplus, bracket, end = rest.partition(">")
name = end.split("<")[0]
url = urlplus[1:-1]
credit = title.strip()
if credit:
credit += " "
credit += name + " " + url
credits.append(credit)
return credits
def ciCompare(a,b):
return cmp(a.lower(), b.lower())
def ciKey(a):
return a.lower()
def SortListInsensitive(l):
try: # Try key function
l.sort(key=ciKey)
except TypeError: # Earlier version of Python, so use comparison function
l.sort(ciCompare)
class ScintillaData:
def __init__(self, scintillaRoot):
# Discover verion information
with open(scintillaRoot + "version.txt") as f:
self.version = f.read().strip()
self.versionDotted = self.version[0] + '.' + self.version[1] + '.' + \
self.version[2]
self.versionCommad = self.version[0] + ', ' + self.version[1] + ', ' + \
self.version[2] + ', 0'
with open(scintillaRoot + "doc/index.html") as f:
self.dateModified = [l for l in f.readlines() if "Date.Modified" in l]\
[0].split('\"')[3]
# 20130602
# index.html, SciTE.html
dtModified = datetime.datetime.strptime(self.dateModified, "%Y%m%d")
self.yearModified = self.dateModified[0:4]
monthModified = dtModified.strftime("%B")
dayModified = "%d" % dtModified.day
self.mdyModified = monthModified + " " + dayModified + " " + self.yearModified
# May 22 2013
# index.html, SciTE.html
self.dmyModified = dayModified + " " + monthModified + " " + self.yearModified
# 22 May 2013
# ScintillaHistory.html -- only first should change
self.myModified = monthModified + " " + self.yearModified
# Find all the lexer source code files
lexFilePaths = glob.glob(scintillaRoot + "lexers/Lex*.cxx")
SortListInsensitive(lexFilePaths)
self.lexFiles = [os.path.basename(f)[:-4] for f in lexFilePaths]
self.lexerModules = []
lexerProperties = set()
self.propertyDocuments = {}
for lexFile in lexFilePaths:
self.lexerModules.extend(FindModules(lexFile))
for k in FindProperties(lexFile).keys():
lexerProperties.add(k)
documents = FindPropertyDocumentation(lexFile)
for k in documents.keys():
if k not in self.propertyDocuments:
self.propertyDocuments[k] = documents[k]
SortListInsensitive(self.lexerModules)
self.lexerProperties = list(lexerProperties)
SortListInsensitive(self.lexerProperties)
self.credits = FindCredits(scintillaRoot + "doc/ScintillaHistory.html")
def printWrapped(text):
print(textwrap.fill(text, subsequent_indent=" "))
if __name__=="__main__":
sci = ScintillaData("../")
print("Version %s %s %s" % (sci.version, sci.versionDotted, sci.versionCommad))
print("Date last modified %s %s %s %s %s" % (
sci.dateModified, sci.yearModified, sci.mdyModified, sci.dmyModified, sci.myModified))
printWrapped(str(len(sci.lexFiles)) + " lexer files: " + ", ".join(sci.lexFiles))
printWrapped(str(len(sci.lexerModules)) + " lexer modules: " + ", ".join(sci.lexerModules))
printWrapped("Lexer properties: " + ", ".join(sci.lexerProperties))
print("Lexer property documentation:")
documentProperties = list(sci.propertyDocuments.keys())
SortListInsensitive(documentProperties)
for k in documentProperties:
print(" " + k)
print(textwrap.fill(sci.propertyDocuments[k], initial_indent=" ",
subsequent_indent=" "))
print("Credits:")
for c in sci.credits:
if sys.version_info[0] == 2:
print(" " + c.encode("utf-8"))
else:
sys.stdout.buffer.write(b" " + c.encode("utf-8") + b"\n")
| {'content_hash': '23fd6d5153a9f91723538cba4efa19b9', 'timestamp': '', 'source': 'github', 'line_count': 195, 'max_line_length': 95, 'avg_line_length': 39.61538461538461, 'alnum_prop': 0.5268608414239482, 'repo_name': 'septag/bgfx', 'id': 'f9c7718bf4f70dc001f434ae5803ce20d2e2dddc', 'size': '8599', 'binary': False, 'copies': '68', 'ref': 'refs/heads/master', 'path': '3rdparty/scintilla/scripts/ScintillaData.py', 'mode': '33188', 'license': 'bsd-2-clause', 'language': [{'name': 'C', 'bytes': '947577'}, {'name': 'C++', 'bytes': '1979711'}, {'name': 'Lua', 'bytes': '37877'}, {'name': 'Makefile', 'bytes': '28243'}, {'name': 'Objective-C', 'bytes': '24324'}, {'name': 'Objective-C++', 'bytes': '146841'}, {'name': 'Scala', 'bytes': '3786'}, {'name': 'Shell', 'bytes': '36518'}, {'name': 'SuperCollider', 'bytes': '4733'}]} |
my-cpp-projects
====
### [STORM](https://github.com/pjc0247/STORM)
mysql ORM for C++.
```cpp
auto = results = query
->where("nickname", "foo")
->limit(5)
->find_many();
for(auto result : results)
cout<<(*result)["level"]<<endl;
```
### [lemon](https://github.com/pjc02478/lemon)
Coroutines for C++
```cpp
void func(){
printf("begin func\n");
delay(time::second(2));
printf("after 2 secs\n");
delay(time::second(1));
printf("after 1 sec\n");
}
```
### [DynamicThreadPool](https://github.com/pjc0247/DynamicProcessPool)
```cpp
void worker(int item) {
printf("item queued %d\n", item);
}
auto pool = new DynamicProcessPool<int>(4, 8, 200, worker);
pool->enqueue(1);
pool->enqueue(2);
pool->enqueue(3);
```
### [base64-cpp](https://github.com/pjc0247/base64-c)
### [EventPie](https://github.com/pjc0247/EventPie)
| {'content_hash': '63932a453cbda27fc52bcc3cd0f1d8cc', 'timestamp': '', 'source': 'github', 'line_count': 42, 'max_line_length': 70, 'avg_line_length': 20.023809523809526, 'alnum_prop': 0.633769322235434, 'repo_name': 'pjc0247/pjc0247.github.io', 'id': '9fce9b71cd119c9026a3369569300f72b5492a30', 'size': '841', 'binary': False, 'copies': '1', 'ref': 'refs/heads/master', 'path': 'my-cpp-projecs/readme.md', 'mode': '33188', 'license': 'mit', 'language': [{'name': 'CSS', 'bytes': '12747637'}, {'name': 'HTML', 'bytes': '46888056'}, {'name': 'JavaScript', 'bytes': '6099322'}, {'name': 'Less', 'bytes': '78481'}, {'name': 'PHP', 'bytes': '710344'}, {'name': 'Roff', 'bytes': '6177'}, {'name': 'SCSS', 'bytes': '79489'}]} |
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