code
stringlengths 3
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stringlengths 4
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| path
stringlengths 3
942
| language
stringclasses 30
values | license
stringclasses 15
values | size
int32 3
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|
|---|---|---|---|---|---|
/********
* This file is part of Ext.NET.
*
* Ext.NET is free software: you can redistribute it and/or modify
* it under the terms of the GNU AFFERO GENERAL PUBLIC LICENSE as
* published by the Free Software Foundation, either version 3 of the
* License, or (at your option) any later version.
*
* Ext.NET is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU AFFERO GENERAL PUBLIC LICENSE for more details.
*
* You should have received a copy of the GNU AFFERO GENERAL PUBLIC LICENSE
* along with Ext.NET. If not, see <http://www.gnu.org/licenses/>.
*
*
* @version : 1.2.0 - Ext.NET Pro License
* @author : Ext.NET, Inc. http://www.ext.net/
* @date : 2011-09-12
* @copyright : Copyright (c) 2006-2011, Ext.NET, Inc. (http://www.ext.net/). All rights reserved.
* @license : GNU AFFERO GENERAL PUBLIC LICENSE (AGPL) 3.0.
* See license.txt and http://www.ext.net/license/.
* See AGPL License at http://www.gnu.org/licenses/agpl-3.0.txt
********/
using System.ComponentModel;
using System.Web;
namespace Ext.Net
{
/// <summary>
///
/// </summary>
[Description("")]
public abstract partial class Node : StateManagedItem
{
private static readonly object idCounter = new object();
/// <summary>
///
/// </summary>
[Description("")]
protected Node() { }
/// <summary>
///
/// </summary>
/// <returns></returns>
[Description("")]
public int GetID()
{
lock (idCounter)
{
object obj = HttpContext.Current.Items["_uniqueTreeNodeID"];
int id = 0;
if (obj != null)
{
id = (int)obj;
id++;
}
HttpContext.Current.Items["_uniqueTreeNodeID"] = id;
return id;
}
}
private readonly string autoID="";
/// <summary>
/// The id for this node. If one is not specified, one is generated.
/// </summary>
[ConfigOption("id")]
[Category("2. Node")]
[DefaultValue("")]
[NotifyParentProperty(true)]
[Description("The id for this node. If one is not specified, one is generated.")]
public virtual string NodeID
{
get
{
return (string)this.ViewState["NodeID"] ?? this.autoID;
}
set
{
this.ViewState["NodeID"] = value;
}
}
/// <summary>
/// True if this node is a leaf and does not have children
/// </summary>
[ConfigOption]
[Category("2. Node")]
[DefaultValue(false)]
[NotifyParentProperty(true)]
[Description("True if this node is a leaf and does not have children")]
public virtual bool Leaf
{
get
{
object obj = this.ViewState["Leaf"];
return (obj == null) ? false : (bool) obj;
}
set
{
this.ViewState["Leaf"] = value;
}
}
}
} | daowzq/ExtNet | ext.net.community/Ext.Net/Ext/Tree/Node.cs | C# | agpl-3.0 | 3,366 |
<?php
/**
* @copyright Copyright (c) 2016, ownCloud, Inc.
*
* @author Björn Schießle <[email protected]>
*
* @license AGPL-3.0
*
* This code is free software: you can redistribute it and/or modify
* it under the terms of the GNU Affero General Public License, version 3,
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Affero General Public License for more details.
*
* You should have received a copy of the GNU Affero General Public License, version 3,
* along with this program. If not, see <http://www.gnu.org/licenses/>
*
*/
namespace OCA\FederatedFileSharing\AppInfo;
use OC\AppFramework\Utility\SimpleContainer;
use OCA\FederatedFileSharing\AddressHandler;
use OCA\FederatedFileSharing\Controller\RequestHandlerController;
use OCA\FederatedFileSharing\FederatedShareProvider;
use OCA\FederatedFileSharing\Notifications;
use OCP\AppFramework\App;
class Application extends App {
/** @var FederatedShareProvider */
protected $federatedShareProvider;
public function __construct() {
parent::__construct('federatedfilesharing');
$container = $this->getContainer();
$server = $container->getServer();
$container->registerService('RequestHandlerController', function(SimpleContainer $c) use ($server) {
$addressHandler = new AddressHandler(
$server->getURLGenerator(),
$server->getL10N('federatedfilesharing')
);
$notification = new Notifications(
$addressHandler,
$server->getHTTPClientService(),
new \OCA\FederatedFileSharing\DiscoveryManager(
$server->getMemCacheFactory(),
$server->getHTTPClientService()
),
\OC::$server->getJobList()
);
return new RequestHandlerController(
$c->query('AppName'),
$server->getRequest(),
$this->getFederatedShareProvider(),
$server->getDatabaseConnection(),
$server->getShareManager(),
$notification,
$addressHandler,
$server->getUserManager()
);
});
}
/**
* register personal and admin settings page
*/
public function registerSettings() {
\OCP\App::registerPersonal('federatedfilesharing', 'settings-personal');
}
/**
* get instance of federated share provider
*
* @return FederatedShareProvider
*/
public function getFederatedShareProvider() {
if ($this->federatedShareProvider === null) {
$this->initFederatedShareProvider();
}
return $this->federatedShareProvider;
}
/**
* initialize federated share provider
*/
protected function initFederatedShareProvider() {
$addressHandler = new \OCA\FederatedFileSharing\AddressHandler(
\OC::$server->getURLGenerator(),
\OC::$server->getL10N('federatedfilesharing')
);
$discoveryManager = new \OCA\FederatedFileSharing\DiscoveryManager(
\OC::$server->getMemCacheFactory(),
\OC::$server->getHTTPClientService()
);
$notifications = new \OCA\FederatedFileSharing\Notifications(
$addressHandler,
\OC::$server->getHTTPClientService(),
$discoveryManager,
\OC::$server->getJobList()
);
$tokenHandler = new \OCA\FederatedFileSharing\TokenHandler(
\OC::$server->getSecureRandom()
);
$this->federatedShareProvider = new \OCA\FederatedFileSharing\FederatedShareProvider(
\OC::$server->getDatabaseConnection(),
$addressHandler,
$notifications,
$tokenHandler,
\OC::$server->getL10N('federatedfilesharing'),
\OC::$server->getLogger(),
\OC::$server->getLazyRootFolder(),
\OC::$server->getConfig(),
\OC::$server->getUserManager()
);
}
}
| jbicha/server | apps/federatedfilesharing/lib/AppInfo/Application.php | PHP | agpl-3.0 | 3,656 |
/*
* Copyright (C) 2005,2006,2007 MaNGOS <http://www.mangosproject.org/>
* Copyright (C) 2007-2008 Ascent Team <http://www.ascentemu.com/>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _COORDMODELMAPPING_H_
#define _COORDMODELMAPPING_H_
#include <G3D/Table.h>
#include <G3D/Array.h>
using namespace G3D;
/**
This Class is a helper Class to convert the raw vector data into BSP-Trees.
We read the directory file of the raw data output and build logical groups.
Models with a lot of vectors are not merged into a resulting model, but separated into an additional file.
*/
namespace VMAP
{
#define MIN_VERTICES_FOR_OWN_CONTAINER_FILE 65000
// if we are in an instance
#define MIN_INST_VERTICES_FOR_OWN_CONTAINER_FILE 40000
//=====================================================
class NameCollection
{
public:
Array<std::string> iMainFiles;
Array<std::string> iSingeFiles;
void appendToMain(std::string pStr) { iMainFiles.append(pStr); }
void appendToSingle(std::string pStr) { iSingeFiles.append(pStr); }
size_t size() { return (iMainFiles.size() + iSingeFiles.size()); }
};
//=====================================================
class CMappingEntry
{
private:
int xPos;
int yPos;
unsigned int iMapId;
Array<std::string> iFilenames;
public:
CMappingEntry() { };
CMappingEntry(unsigned int pMapId, const int pXPos, const int pYPos)
{
iMapId = pMapId;
xPos = pXPos; yPos = pYPos;
};
~CMappingEntry() {};
void addFilename(char *pName);
const std::string getKeyString() const;
inline const Array<std::string>& getFilenames() const { return(iFilenames); }
static const std::string getKeyString(unsigned int pMapId, int pXPos, int pYPos)
{
char b[100];
sprintf(b,"%03u_%d_%d", pMapId, pXPos, pYPos);
return(std::string(b));
}
};
//=====================================================
class CoordModelMapping
{
private:
Table<std::string, CMappingEntry *> iMapObjectFiles;
Table<std::string, std::string> iProcesseSingleFiles;
Array<unsigned int> iMapIds;
Array<unsigned int> iWorldAreaGroups;
bool (*iFilterMethod)(char *pName);
inline void addCMappingEntry(CMappingEntry* pCMappingEntry)
{
iMapObjectFiles.set(pCMappingEntry->getKeyString(), pCMappingEntry);
}
inline CMappingEntry* getCMappingEntry(const std::string& pKey)
{
if(iMapObjectFiles.containsKey(pKey))
return(iMapObjectFiles.get(pKey));
else
return 0;
}
public:
CoordModelMapping() { iFilterMethod = NULL; }
virtual ~CoordModelMapping();
bool readCoordinateMapping(const std::string& pDirectoryFileName);
const NameCollection getFilenamesForCoordinate(unsigned int pMapId, int xPos, int yPos);
static unsigned int getMapIdFromFilename(std::string pName)
{
size_t spos;
spos = pName.find_last_of('/');
std::string basename = pName.substr(0, spos);
spos = basename.find_last_of('/');
std::string groupname = basename.substr(spos+1, basename.length());
unsigned int mapId = atoi(groupname.c_str());
return(mapId);
}
const Array<unsigned int>& getMaps() const { return iMapIds; }
inline bool isAlreadyProcessedSingleFile(std::string pName) { return(iProcesseSingleFiles.containsKey(pName)); }
inline void addAlreadyProcessedSingleFile(std::string pName) { iProcesseSingleFiles.set(pName,pName); }
inline void addWorldAreaMap(unsigned int pMapId)
{
if(!iWorldAreaGroups.contains(pMapId))
{
iWorldAreaGroups.append(pMapId);
}
}
inline bool isWorldAreaMap(unsigned int pMapId) { return(iWorldAreaGroups.contains(pMapId)); }
void setModelNameFilterMethod(bool (*pFilterMethod)(char *pName)) { iFilterMethod = pFilterMethod; }
};
}
#endif /*_COORDMODELMAPPING_H_*/
| Tulba/wowtbc | src/collision/vmap/CoordModelMapping.h | C | agpl-3.0 | 5,427 |
/*
* This file is part of ToroDB.
*
* ToroDB is free software: you can redistribute it and/or modify
* it under the terms of the GNU Affero General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ToroDB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Affero General Public License for more details.
*
* You should have received a copy of the GNU Affero General Public License
* along with ToroDB. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright (c) 2014, 8Kdata Technology
*
*/
package com.torodb.torod.db.postgresql.meta.tables;
import com.google.common.collect.AbstractIterator;
import com.torodb.torod.core.exceptions.ToroImplementationException;
import com.torodb.torod.core.subdocument.*;
import com.torodb.torod.db.postgresql.IdsFilter;
import com.torodb.torod.db.postgresql.converters.jooq.SubdocValueConverter;
import com.torodb.torod.db.postgresql.converters.jooq.ValueToJooqConverterProvider;
import com.torodb.torod.db.postgresql.meta.CollectionSchema;
import com.torodb.torod.db.postgresql.meta.tables.records.SubDocTableRecord;
import com.torodb.torod.core.subdocument.values.Value;
import com.torodb.torod.db.postgresql.converters.BasicTypeToSqlType;
import edu.umd.cs.findbugs.annotations.SuppressFBWarnings;
import java.io.Serializable;
import java.sql.DatabaseMetaData;
import java.sql.ResultSet;
import java.sql.SQLException;
import java.sql.Types;
import java.util.Iterator;
import java.util.regex.Matcher;
import java.util.regex.Pattern;
import javax.annotation.Nonnull;
import org.jooq.*;
import org.jooq.impl.AbstractKeys;
import org.jooq.impl.DSL;
import org.jooq.impl.SQLDataType;
import org.jooq.impl.TableImpl;
/**
*
*/
public class SubDocTable extends TableImpl<SubDocTableRecord> {
private static final long serialVersionUID = 1197457693;
private static final Pattern TABLE_ID_PATTERN
= Pattern.compile("t_([0-9]+)$");
private static final Pattern LIKE_DID_PATTERN = Pattern.compile("_*did");
private static final Pattern LIKE_INDEX_PATTERN = Pattern.compile("_*index");
public static final String DID_COLUMN_NAME = "did";
public static final String INDEX_COLUMN_NAME = "index";
private final SubDocType erasuredType;
/**
* JOOQ cannot fetch tables whose records don't have default constructor, so
* {@link SubDocTableRecord} cannot be fetched. We use this generic table as
* a table with the same name but a generic record and a
* {@link RecordMapper} to fetch elements of SubDocTables.
*/
private Table<Record> genericTable;
private Identity<SubDocTableRecord, Integer> identityRoot;
private final TableField<SubDocTableRecord, Integer> didField
= createField(DID_COLUMN_NAME, SQLDataType.INTEGER.nullable(false), this, "");
private final TableField<SubDocTableRecord, Integer> indexField
= createField(INDEX_COLUMN_NAME, SQLDataType.INTEGER.nullable(true), this, "");
public SubDocTable(
String tableName,
CollectionSchema schema,
DatabaseMetaData metadata
) {
this(
tableName,
schema,
null,
extractSimpleType(
schema.getName(),
tableName,
metadata
)
);
}
public SubDocTable(CollectionSchema schema, SubDocType type, int typeId) {
this(getSubDocTableName(typeId), schema, null, type);
}
private SubDocTable(String alias, Schema schema, Table<SubDocTableRecord> aliased, @Nonnull SubDocType type) {
this(alias, schema, aliased, null, type);
}
private SubDocTable(String alias, Schema schema, Table<SubDocTableRecord> aliased, Field<?>[] parameters, @Nonnull SubDocType type) {
super(alias, schema, aliased, parameters, "");
this.erasuredType = type;
for (SubDocAttribute attibute : type.getAttributes()) {
String fieldName = toColumnName(attibute.getKey());
SubdocValueConverter converter
= ValueToJooqConverterProvider.getConverter(attibute.getType());
createField(
fieldName,
converter.getDataType(),
this,
"",
converter);
}
}
@SuppressFBWarnings("SIC_INNER_SHOULD_BE_STATIC_ANON")
public Iterable<Field<? extends Value<? extends Serializable>>> getSubDocFields() {
final Iterator<Field<? extends Value<? extends Serializable>>> iterator
= new AbstractIterator<Field<? extends Value<? extends Serializable>>>() {
Iterator<String> attIt
= erasuredType.getAttributeKeys().iterator();
@Override
protected Field<? extends Value<? extends Serializable>> computeNext() {
if (!attIt.hasNext()) {
endOfData();
return null;
}
return (Field<? extends Value<? extends Serializable>>) field(attIt.next());
}
};
return new Iterable<Field<? extends Value<? extends Serializable>>>() {
@Override
public Iterator<Field<? extends Value<? extends Serializable>>> iterator() {
return iterator;
}
};
}
public static boolean isSubDocTable(String name) {
return getSubDocTypeId(name) != null;
}
private static Integer getSubDocTypeId(String name) {
Matcher matcher = TABLE_ID_PATTERN.matcher(name);
if (matcher.find()) {
return Integer.parseInt(matcher.group(1));
}
return null;
}
private static String getSubDocTableName(int typeId) {
return "t_" + typeId;
}
private static SubDocType extractSimpleType(
String schemaName,
String tableName,
DatabaseMetaData metadata
) {
try {
SubDocType.Builder builder = new SubDocType.Builder();
ResultSet columns
= metadata.getColumns(null, schemaName, tableName, null);
while (columns.next()) {
String columnName = columns.getString("COLUMN_NAME");
if (SubDocTable.isSpecialColumn(columnName)) {
continue;
}
int intColumnType = columns.getInt("DATA_TYPE");
String stringColumnType = columns.getString("TYPE_NAME");
BasicType basicType = BasicTypeToSqlType.getInstance().toBasicType(
columnName,
intColumnType,
stringColumnType
);
String attName = toAttributeName(columnName);
builder.add(new SubDocAttribute(attName, basicType));
}
return builder.build();
}
catch (SQLException ex) {
throw new ToroImplementationException(
"Torod cannot start",
ex
);
}
}
public TableField<SubDocTableRecord, Integer> getDidColumn() {
return didField;
}
public TableField<SubDocTableRecord, Integer> getIndexColumn() {
return indexField;
}
public Table<Record> getGenericTable() {
if (genericTable == null) {
genericTable = DSL.tableByName(getSchema().getName(), getName());
}
return genericTable;
}
public int getTypeId() {
Integer id = SubDocTable.getSubDocTypeId(getName());
assert id != null;
return id;
}
public SubDocType getSubDocType() {
return erasuredType;
}
private static boolean isSpecialColumn(String columnName) {
return columnName.equals(DID_COLUMN_NAME)
|| columnName.equals(INDEX_COLUMN_NAME);
}
public static String toColumnName(String attName) {
Matcher matcher = LIKE_DID_PATTERN.matcher(attName);
if (matcher.find()) {
return "_" + attName;
}
matcher = LIKE_INDEX_PATTERN.matcher(attName);
if (matcher.find()) {
return "_" + attName;
}
return IdsFilter.escapeAttributeName(attName);
}
public static String toAttributeName(String fieldName) {
Matcher matcher = LIKE_DID_PATTERN.matcher(fieldName);
if (matcher.find()) {
return fieldName.substring(1);
}
matcher = LIKE_INDEX_PATTERN.matcher(fieldName);
if (matcher.find()) {
return fieldName.substring(1);
}
return fieldName;
}
/**
* The class holding records for this type
* <p>
* @return
*/
@Override
public Class<SubDocTableRecord> getRecordType() {
return SubDocTableRecord.class;
}
/**
* {@inheritDoc}
* <p>
* @return
*/
@Override
public Identity<SubDocTableRecord, Integer> getIdentity() {
if (identityRoot == null) {
synchronized (this) {
identityRoot = IdentityFactory.createIdentity(this);
}
}
return identityRoot;
}
/**
* {@inheritDoc}
* <p>
* @param alias
* @return
*/
@Override
public SubDocTable as(String alias) {
return new SubDocTable(alias, getSchema(), this, getSubDocType());
}
/**
* Rename this table
* <p>
* @param name
* @return
*/
public SubDocTable rename(String name) {
return new SubDocTable(name, getSchema(), null, getSubDocType());
}
@Override
public int hashCode() {
return super.hashCode();
}
@Override
public boolean equals(Object obj) {
return super.equals(obj);
}
private static class IdentityFactory extends AbstractKeys {
public static Identity<SubDocTableRecord, Integer> createIdentity(SubDocTable table) {
return createIdentity(table, table.didField);
}
}
}
| fhuertas/torodb | torod/db-wrappers/postgresql/src/main/java/com/torodb/torod/db/postgresql/meta/tables/SubDocTable.java | Java | agpl-3.0 | 10,450 |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<!-- NewPage -->
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<head>
<!-- Generated by javadoc (version 1.7.0_75) on Mon Jan 23 21:20:20 IST 2017 -->
<title>Deprecated List</title>
<meta name="date" content="2017-01-23">
<link rel="stylesheet" type="text/css" href="stylesheet.css" title="Style">
</head>
<body>
<script type="text/javascript"><!--
if (location.href.indexOf('is-external=true') == -1) {
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| RishiGupta12/SerialPundit | javadocs/usb/deprecated-list.html | HTML | agpl-3.0 | 3,320 |
/**
* Copyright (C) 2001-2015 by RapidMiner and the contributors
*
* Complete list of developers available at our web site:
*
* http://rapidminer.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Affero General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Affero General Public License for more details.
*
* You should have received a copy of the GNU Affero General Public License
* along with this program. If not, see http://www.gnu.org/licenses/.
*/
package com.rapidminer.gui.new_plotter.configuration;
import com.rapidminer.gui.new_plotter.listener.AggregationWindowingListener;
import com.rapidminer.gui.new_plotter.utility.AggregatedValueRange;
import com.rapidminer.gui.new_plotter.utility.ValueRange;
import java.util.LinkedList;
import java.util.List;
/**
* This class can be used to create cumulative plots.
*
* Used as a parameter to the grouping creation functions it tells the ValueGrouping to include
* values from a certain amount of groups from the left or from the right in a group. To include all
* values left of the current group in the current group, set grabLeft to -1. grabLeft works
* analogously.
*
* If there are less than grabLeft groups on the left of the current group, all left groups are
* taken.
*
* @author Marius Helf
*
*/
public class AggregationWindowing implements Cloneable {
private int grabLeft = 0;
private int grabRight = 0;
private boolean includeIncompleteGroups = true;
private List<AggregationWindowingListener> listeners = new LinkedList<AggregationWindowingListener>();
public AggregationWindowing(int grabLeft, int grabRight, boolean includeIncompleteGroups) {
super();
this.grabLeft = grabLeft;
this.grabRight = grabRight;
this.includeIncompleteGroups = includeIncompleteGroups;
}
public int getGrabLeft() {
return grabLeft;
}
public void setGrabLeft(int grabLeft) {
if (grabLeft != this.grabLeft) {
this.grabLeft = grabLeft;
fireAggregationWindowingChanged();
}
}
public int getGrabRight() {
return grabRight;
}
public void setGrabRight(int grabRight) {
if (grabRight != this.grabRight) {
this.grabRight = grabRight;
fireAggregationWindowingChanged();
}
}
/**
* @return the includeIncompleteGroups
*/
public boolean isIncludingIncompleteGroups() {
return includeIncompleteGroups;
}
/**
* @param includeIncompleteGroups
* the includeIncompleteGroups to set
*/
public void setIncludeIncompleteGroups(boolean includeIncompleteGroups) {
if (includeIncompleteGroups != this.includeIncompleteGroups) {
this.includeIncompleteGroups = includeIncompleteGroups;
fireAggregationWindowingChanged();
}
}
/**
* Creates a new grouping model (i.e. a list of {@link ValueRange}s) with this aggregation
* windowing applied. Does not change the input grouping.
*
* When includeIncompleteGroups is false, the resulting list will contain null values for the
* the incomplete groups.
*/
public List<ValueRange> applyOnGrouping(List<ValueRange> grouping) {
if (grabLeft == 0 && grabRight == 0) {
return grouping;
}
LinkedList<ValueRange> leftGrabbedList = new LinkedList<ValueRange>();
LinkedList<ValueRange> rightGrabbedList = new LinkedList<ValueRange>();
List<ValueRange> cumulatedGrouping = new LinkedList<ValueRange>();
ValueRange currentRange = null;
for (ValueRange range : grouping) {
rightGrabbedList.add(range);
if (currentRange != null) {
leftGrabbedList.add(currentRange);
if (grabLeft > -1 && leftGrabbedList.size() > grabLeft) {
leftGrabbedList.removeFirst();
}
}
if (grabRight > -1 && rightGrabbedList.size() > grabRight) {
currentRange = rightGrabbedList.removeFirst();
}
// check if we want to add the current range
boolean addAggregatedRange = false;
if (currentRange != null) {
if (includeIncompleteGroups) {
addAggregatedRange = true;
} else if (grabLeft == -1) {
addAggregatedRange = true;
} else if (leftGrabbedList.size() >= grabLeft) {
addAggregatedRange = true;
}
}
// add current range
if (addAggregatedRange) {
AggregatedValueRange aggregatedRange = createAggregatedRange(leftGrabbedList, rightGrabbedList, currentRange);
cumulatedGrouping.add(aggregatedRange);
} else if (currentRange != null) {
cumulatedGrouping.add(null);
}
}
if (includeIncompleteGroups || grabRight == -1) {
while (!rightGrabbedList.isEmpty()) {
if (currentRange != null) {
leftGrabbedList.add(currentRange);
}
currentRange = rightGrabbedList.removeFirst();
if (grabLeft > -1 && leftGrabbedList.size() > grabLeft) {
leftGrabbedList.removeFirst();
}
cumulatedGrouping.add(createAggregatedRange(leftGrabbedList, rightGrabbedList, currentRange));
}
} else {
while (cumulatedGrouping.size() < grouping.size()) {
cumulatedGrouping.add(null);
}
}
return cumulatedGrouping;
}
private AggregatedValueRange createAggregatedRange(LinkedList<ValueRange> leftGrabbedList,
LinkedList<ValueRange> rightGrabbedList, ValueRange currentRange) {
AggregatedValueRange aggregatedRange = new AggregatedValueRange();
aggregatedRange.addSubRange(currentRange);
for (ValueRange subRange : leftGrabbedList) {
aggregatedRange.addSubRange(subRange);
}
for (ValueRange subRange : rightGrabbedList) {
aggregatedRange.addSubRange(subRange);
}
return aggregatedRange;
}
public void addAggregationWindowingListener(AggregationWindowingListener l) {
listeners.add(l);
}
public void removeAggregationWindowingListener(AggregationWindowingListener l) {
listeners.remove(l);
}
private void fireAggregationWindowingChanged() {
for (AggregationWindowingListener l : listeners) {
l.aggregationWindowingChanged(this);
}
}
@Override
public AggregationWindowing clone() {
AggregationWindowing clone = new AggregationWindowing(grabLeft, grabRight, includeIncompleteGroups);
return clone;
}
}
| brtonnies/rapidminer-studio | src/main/java/com/rapidminer/gui/new_plotter/configuration/AggregationWindowing.java | Java | agpl-3.0 | 6,534 |
<?php
require_javascript('og/modules/doubleListSelCtrl.js');
if (!isset($for_task)) $for_task = false;
// build columm list
$list = array();
if (is_array($columns)) {
foreach ($columns as $colid) {
if ($colid != '') {
$list[] = array(
'id' => $colid,
'text' => '',
'selected' => true,
);
}
}
}
$options = array();
foreach ($allowed_columns as $acol) {
$add = true;
foreach ($list as $k => $item) {
if ($acol['id'] == $item['id'] ){
$list[$k]['text'] = $acol['name'];
$add = false;
break;
}
}
if ($add) {
$list[] = array(
'id' => $acol['id'],
'text' => $acol['name'],
'selected' => false,
);
}
if(!isset($order_by) || $order_by == '') $order_by = 'updated_on';
if (!str_starts_with($acol['id'], "dim_") && $acol['id']!='time' && $acol['id']!='billing') {
$options[] = option_tag($acol['name'], $acol['id'], $acol['id'] == $order_by ? array('selected' => 'selected') : null);
}
}
// Render Order By combos
if (!$for_task){
echo label_tag(lang('order by'), $genid . 'reportFormOrderBy', true, array('id' => 'orderByLbl'));
echo select_box('report[order_by]', $options, array('id' => 'report[order_by]', 'style' => 'width:200px;'));
$asc = option_tag(lang('ascending'), 'asc', $order_by_asc ? array('selected' => 'selected') : null);
$desc = option_tag(lang('descending'), 'desc', !$order_by_asc ? array('selected' => 'selected') : null);
echo select_box('report[order_by_asc]', array($asc, $desc), array('id' => 'report[order_by_asc]', 'style' => 'width:120px;'));
echo "<br /><br />";
}
// Render Column lists
echo label_tag(lang('columns to print'), 'columns');
echo doubleListSelect("columns", $list, array('id' => $genid."columns", 'size' => 20));
echo '<span class="desc">' . lang('columns to print desc') . '</span>';
?> | rsnlamatrice/groupware | application/views/reporting/column_list.php | PHP | agpl-3.0 | 1,852 |
from .models import route53_backend
mock_route53 = route53_backend.decorator
| GbalsaC/bitnamiP | venv/lib/python2.7/site-packages/moto/route53/__init__.py | Python | agpl-3.0 | 77 |
#ifndef GAIASVMUTILS_H
#define GAIASVMUTILS_H
#include "dataset.h"
#include "svm.h"
namespace gaia2 {
namespace svm {
QStringList createClassMapping(const DataSet* dataset,
const QString& className);
void writeTrainingSetToFile(const QString& filename, const DataSet* dataset,
const QString& className, const Region& region);
struct svm_problem
dataSetToLibsvmProblem(const DataSet* dataset, const QString& className, const Region& region,
const QStringList& classList);
/**
* Frees the memory that's been allocated for the problem by the
* dataSetToLibsvmProblem function.
*/
void destroyProblem(const struct svm_problem& prob);
} // namespace svm
} // namespace gaia2
#endif // GAIASVMUTILS_H
| ChristianFrisson/gaia | src/3rdparty/libsvm/gaiasvmutils.h | C | agpl-3.0 | 792 |
"""
Tests for courseware middleware
"""
from django.http import Http404
from django.test.client import RequestFactory
from lms.djangoapps.courseware.exceptions import Redirect
from lms.djangoapps.courseware.middleware import RedirectMiddleware
from xmodule.modulestore.tests.django_utils import SharedModuleStoreTestCase # lint-amnesty, pylint: disable=wrong-import-order
from xmodule.modulestore.tests.factories import CourseFactory # lint-amnesty, pylint: disable=wrong-import-order
class CoursewareMiddlewareTestCase(SharedModuleStoreTestCase):
"""Tests that courseware middleware is correctly redirected"""
@classmethod
def setUpClass(cls):
super().setUpClass()
cls.course = CourseFactory.create()
@staticmethod
def get_headers(cache_response):
"""
Django 3.2 has no ._headers
See https://docs.djangoproject.com/en/3.2/releases/3.2/#requests-and-responses
"""
if hasattr(cache_response, '_headers'):
headers = cache_response._headers.copy() # pylint: disable=protected-access
else:
headers = {k.lower(): (k, v) for k, v in cache_response.items()}
return headers
def test_process_404(self):
"""A 404 should not trigger anything"""
request = RequestFactory().get("dummy_url")
response = RedirectMiddleware().process_exception(
request, Http404()
)
assert response is None
def test_redirect_exceptions(self):
"""
Unit tests for handling of Redirect exceptions.
"""
request = RequestFactory().get("dummy_url")
test_url = '/test_url'
exception = Redirect(test_url)
response = RedirectMiddleware().process_exception(
request, exception
)
assert response.status_code == 302
headers = self.get_headers(response)
target_url = headers['location'][1]
assert target_url.endswith(test_url)
| edx/edx-platform | lms/djangoapps/courseware/tests/test_middleware.py | Python | agpl-3.0 | 1,978 |
// Copyright 2012, 2013 Canonical Ltd.
// Licensed under the AGPLv3, see LICENCE file for details.
package commands
import (
"fmt"
"net"
"os"
"os/exec"
"strings"
"time"
"github.com/juju/cmd"
"github.com/juju/names"
"github.com/juju/utils"
"github.com/juju/utils/ssh"
"launchpad.net/gnuflag"
"github.com/juju/juju/cmd/envcmd"
"github.com/juju/juju/environs/config"
)
func newSSHCommand() cmd.Command {
return envcmd.Wrap(&sshCommand{})
}
// sshCommand is responsible for launching a ssh shell on a given unit or machine.
type sshCommand struct {
SSHCommon
}
// SSHCommon provides common methods for sshCommand, SCPCommand and DebugHooksCommand.
type SSHCommon struct {
envcmd.EnvCommandBase
proxy bool
pty bool
Target string
Args []string
apiClient sshAPIClient
apiAddr string
}
func (c *SSHCommon) SetFlags(f *gnuflag.FlagSet) {
f.BoolVar(&c.proxy, "proxy", true, "proxy through the API server")
f.BoolVar(&c.pty, "pty", true, "enable pseudo-tty allocation")
}
// setProxyCommand sets the proxy command option.
func (c *SSHCommon) setProxyCommand(options *ssh.Options) error {
apiServerHost, _, err := net.SplitHostPort(c.apiAddr)
if err != nil {
return fmt.Errorf("failed to get proxy address: %v", err)
}
juju, err := getJujuExecutable()
if err != nil {
return fmt.Errorf("failed to get juju executable path: %v", err)
}
options.SetProxyCommand(juju, "ssh", "--proxy=false", "--pty=false", apiServerHost, "nc", "%h", "%p")
return nil
}
const sshDoc = `
Launch an ssh shell on the machine identified by the <target> parameter.
<target> can be either a machine id as listed by "juju status" in the
"machines" section or a unit name as listed in the "services" section.
Any extra parameters are passed as extra parameters to the ssh command.
Examples:
Connect to machine 0:
juju ssh 0
Connect to machine 1 and run 'uname -a':
juju ssh 1 uname -a
Connect to the first mysql unit:
juju ssh mysql/0
Connect to the first mysql unit and run 'ls -la /var/log/juju':
juju ssh mysql/0 ls -la /var/log/juju
Connect to the first jenkins unit as the user jenkins:
juju ssh jenkins@jenkins/0
`
func (c *sshCommand) Info() *cmd.Info {
return &cmd.Info{
Name: "ssh",
Args: "<target> [<ssh args>...]",
Purpose: "launch an ssh shell on a given unit or machine",
Doc: sshDoc,
}
}
func (c *sshCommand) Init(args []string) error {
if len(args) == 0 {
return fmt.Errorf("no target name specified")
}
c.Target, c.Args = args[0], args[1:]
return nil
}
// getJujuExecutable returns the path to the juju
// executable, or an error if it could not be found.
var getJujuExecutable = func() (string, error) {
return exec.LookPath(os.Args[0])
}
// getSSHOptions configures and returns SSH options and proxy settings.
func (c *SSHCommon) getSSHOptions(enablePty bool) (*ssh.Options, error) {
var options ssh.Options
// TODO(waigani) do not save fingerprint only until this bug is addressed:
// lp:892552. Also see lp:1334481.
options.SetKnownHostsFile("/dev/null")
if enablePty {
options.EnablePTY()
}
var err error
if c.proxy, err = c.proxySSH(); err != nil {
return nil, err
} else if c.proxy {
if err := c.setProxyCommand(&options); err != nil {
return nil, err
}
}
return &options, nil
}
// Run resolves c.Target to a machine, to the address of a i
// machine or unit forks ssh passing any arguments provided.
func (c *sshCommand) Run(ctx *cmd.Context) error {
if c.apiClient == nil {
// If the apClient is not already opened and it is opened
// by ensureAPIClient, then close it when we're done.
defer func() {
if c.apiClient != nil {
c.apiClient.Close()
c.apiClient = nil
}
}()
}
options, err := c.getSSHOptions(c.pty)
if err != nil {
return err
}
user, host, err := c.userHostFromTarget(c.Target)
if err != nil {
return err
}
cmd := ssh.Command(user+"@"+host, c.Args, options)
cmd.Stdin = ctx.Stdin
cmd.Stdout = ctx.Stdout
cmd.Stderr = ctx.Stderr
return cmd.Run()
}
// proxySSH returns true iff both c.proxy and
// the proxy-ssh environment configuration
// are true.
func (c *SSHCommon) proxySSH() (bool, error) {
if !c.proxy {
return false, nil
}
if _, err := c.ensureAPIClient(); err != nil {
return false, err
}
var cfg *config.Config
attrs, err := c.apiClient.EnvironmentGet()
if err == nil {
cfg, err = config.New(config.NoDefaults, attrs)
}
if err != nil {
return false, err
}
logger.Debugf("proxy-ssh is %v", cfg.ProxySSH())
return cfg.ProxySSH(), nil
}
func (c *SSHCommon) ensureAPIClient() (sshAPIClient, error) {
if c.apiClient != nil {
return c.apiClient, nil
}
return c.initAPIClient()
}
// initAPIClient initialises the API connection.
// It is the caller's responsibility to close the connection.
func (c *SSHCommon) initAPIClient() (sshAPIClient, error) {
st, err := c.NewAPIRoot()
if err != nil {
return nil, err
}
c.apiClient = st.Client()
c.apiAddr = st.Addr()
return c.apiClient, nil
}
type sshAPIClient interface {
EnvironmentGet() (map[string]interface{}, error)
PublicAddress(target string) (string, error)
PrivateAddress(target string) (string, error)
ServiceCharmRelations(service string) ([]string, error)
Close() error
}
// attemptStarter is an interface corresponding to utils.AttemptStrategy
type attemptStarter interface {
Start() attempt
}
type attempt interface {
Next() bool
}
type attemptStrategy utils.AttemptStrategy
func (s attemptStrategy) Start() attempt {
return utils.AttemptStrategy(s).Start()
}
var sshHostFromTargetAttemptStrategy attemptStarter = attemptStrategy{
Total: 5 * time.Second,
Delay: 500 * time.Millisecond,
}
func (c *SSHCommon) userHostFromTarget(target string) (user, host string, err error) {
if i := strings.IndexRune(target, '@'); i != -1 {
user = target[:i]
target = target[i+1:]
} else {
user = "ubuntu"
}
// If the target is neither a machine nor a unit,
// assume it's a hostname and try it directly.
if !names.IsValidMachine(target) && !names.IsValidUnit(target) {
return user, target, nil
}
// A target may not initially have an address (e.g. the
// address updater hasn't yet run), so we must do this in
// a loop.
if _, err := c.ensureAPIClient(); err != nil {
return "", "", err
}
for a := sshHostFromTargetAttemptStrategy.Start(); a.Next(); {
var addr string
if c.proxy {
addr, err = c.apiClient.PrivateAddress(target)
} else {
addr, err = c.apiClient.PublicAddress(target)
}
if err == nil {
return user, addr, nil
}
}
return "", "", err
}
// AllowInterspersedFlags for ssh/scp is set to false so that
// flags after the unit name are passed through to ssh, for eg.
// `juju ssh -v service-name/0 uname -a`.
func (c *SSHCommon) AllowInterspersedFlags() bool {
return false
}
| fwereade/juju | cmd/juju/commands/ssh.go | GO | agpl-3.0 | 6,820 |
<?php
return array(
'does_not_exist' => 'Fabrikant eksistere ikke.',
'assoc_users' => 'Denne producent er i øjeblikket forbundet med mindst en model og kan ikke slettes. Opdater dine modeller for ikke længere at henvise til denne producent, og prøv igen.',
'create' => array(
'error' => 'Producenten blev ikke oprettet, prøv igen.',
'success' => 'Producenten blev oprettet med succes.'
),
'update' => array(
'error' => 'Producenten blev ikke opdateret, prøv igen',
'success' => 'Producent opdateret med succes.'
),
'delete' => array(
'confirm' => 'Er du sikker på, at du vil slette denne producent?',
'error' => 'Der opstod et problem ved at slette producenten. Prøv igen.',
'success' => 'Fabrikanten blev slettet med succes.'
)
);
| GeoffYoung/snipe-it | resources/lang/da/admin/manufacturers/message.php | PHP | agpl-3.0 | 842 |
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="utf-8">
<title>LTSpline</title>
<link rel="stylesheet" href="http://yui.yahooapis.com/3.8.0pr2/build/cssgrids/cssgrids-min.css">
<link rel="stylesheet" href="../assets/vendor/prettify/prettify-min.css">
<link rel="stylesheet" href="../assets/css/main.css" id="site_styles">
<script src="http://ajax.googleapis.com/ajax/libs/jquery/1.8.3/jquery.min.js"></script>
<script>
(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){
(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),
m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)
})(window,document,'script','//www.google-analytics.com/analytics.js','ga');
ga('create', 'UA-23694672-1', 'dentedpixel.com');
ga('send', 'pageview');
</script>
<script src="../assets/js/leantween.js"></script>
<link rel="shortcut icon" type="image/png" href="../assets/favicon.png">
<script src="http://yui.yahooapis.com/combo?3.8.0pr2/build/yui/yui-min.js"></script>
</head>
<body class="yui3-skin-sam">
<div id="doc">
<div id="hd" class="yui3-g header">
<div class="yui3-u-3-4">
<h1><a href="http://dentedpixel.com/developer-diary/leantween-speed-comparison-to-itween/"><img src="http://s3.amazonaws.com/dentedpixel.com/LeanTween/leantween-logo.png" title=""></a></h1> <div style="position:absolute; left:146px; top:90px;">- Developed by <a href="http://www.dentedpixel.com">Dented Pixel</a></div>
</div>
<div class="yui3-u-1-4 version">
<em style="margin-top:2px">API Docs for: LeanTween 2.50</em><br>
<table id="support">
<tr>
<td>
<h3 style="margin:7px 0 3px 0; width: 200px;">Support LeanTween!</h3>
<!--<a href="http://www.amazon.com/?tag=carbcutt-20&camp=1&creative=4365&linkCode=ez&ref-refURL=" target="_blank">Click this link</a> before your<br>next Amazon shopping spree!<br>
-->
</td>
<td><!--
<a href="http://www.amazon.com/?tag=carbcutt-20&camp=1&creative=4365&linkCode=ez&ref-refURL=" target="_blank"><img src="http://dentedpixel.com/LeanTweenDocumentation/assets/img/amz.gif" width="148" height="40" title="shop amazon" /></a>-->
<form action="https://www.paypal.com/cgi-bin/webscr" method="post" style="margin-top:5px;">
<!--<div style="margin:2px 0px 6px 24px; float:left;">or </div>-->
<input type="hidden" name="cmd" value="_s-xclick">
<input type="hidden" name="hosted_button_id" value="YJPUT3RAK5VL8">
<input type="image" src="https://www.paypalobjects.com/en_US/i/btn/btn_donate_LG.gif" border="0" name="submit" alt="PayPal - The safer, easier way to pay online!">
<img alt="" border="0" src="https://www.paypalobjects.com/en_US/i/scr/pixel.gif" width="1" height="1">
</form>
</td>
</tr>
</table>
</div>
<h4 style="position:absolute; top:80px; right:7px; width:500px; letter-spacing:normal; word-spacing:normal; font-size:9pt; text-align:right; font-style: italic;">Maintaining and adding new features takes time, your support is appreciated.</h4>
</div>
<div id="bd" class="yui3-g">
<div class="yui3-u-1-4">
<div id="docs-sidebar" class="sidebar apidocs">
<div id="api-list">
<h2 class="off-left">APIs</h2>
<div id="api-tabview" class="tabview">
<ul class="tabs">
<li><a href="#api-classes">Classes</a></li>
<li><a href="#api-modules">Modules</a></li>
</ul>
<div id="api-tabview-filter">
<input type="search" id="api-filter" placeholder="Type to filter APIs">
</div>
<div id="api-tabview-panel">
<ul id="api-classes" class="apis classes">
<li><a href="../classes/LeanAudio.html">LeanAudio</a></li>
<li><a href="../classes/LeanAudioOptions.html">LeanAudioOptions</a></li>
<li><a href="../classes/LeanSmooth.html">LeanSmooth</a></li>
<li><a href="../classes/LeanTween.html">LeanTween</a></li>
<li><a href="../classes/LeanTweenType.html">LeanTweenType</a></li>
<li><a href="../classes/LTBezierPath.html">LTBezierPath</a></li>
<li><a href="../classes/LTDescr.html">LTDescr</a></li>
<li><a href="../classes/LTEvent.html">LTEvent</a></li>
<li><a href="../classes/LTRect.html">LTRect</a></li>
<li><a href="../classes/LTSeq.html">LTSeq</a></li>
<li><a href="../classes/LTSpline.html">LTSpline</a></li>
</ul>
<ul id="api-modules" class="apis modules">
</ul>
</div>
</div>
</div>
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<h2>More From<br><a href="http://www.dentedpixel.com">Dented Pixel</a></h2><br>
<a href="https://www.assetstore.unity3d.com/en/#!/content/9455" target="_blank"><img src="http://dentedpixel.com/assets/LTEditor-doc-icon.jpg" width="175" height="175" /><br>Create tweens with: Visual Editor. Sculpt complex spline paths.</a>
<br>
<a href="https://itunes.apple.com/us/app/monkeyshines/id530998075?mt=8" target="_blank"><img src="http://a1.mzstatic.com/us/r30/Purple3/v4/d4/2b/ce/d42bce69-b3d3-d7f8-88e9-caa92664b5b1/icon350x350.jpeg" width="175" height="175" /><br>RIN - A swinging good time!</a>
<br>
<a href="https://itunes.apple.com/us/app/princess-piano/id445283531?mt=8" target="_blank"><img src="http://a3.mzstatic.com/us/r1000/096/Purple/v4/8c/1e/05/8c1e0590-db82-1d72-2956-2b6470f37ed0/mza_4230031260893485317.175x175-75.jpg" width="175" height="175" /><br>Princess Piano - Learn musical notation<br>in this melodious adventure!</a>
</div>
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<h1>LTSpline Class</h1>
<div class="box meta">
<div class="foundat">
Defined in: <a href="../files/LeanTween.cs.html#l3155"><code>LeanTween.cs:3155</code></a>
</div>
</div>
<div class="box intro">
<p>Animate along a set of points that need to be in the format: controlPoint, point1, point2.... pointLast, endControlPoint <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="constructor">
<h2>Constructor</h2>
<div id="method_LTSpline" class="method item">
<h3 class="name"><code>LTSpline</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>pts</code>
</li>
</ul><span class="paren">)</span>
</div>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3155"><code>LeanTween.cs:3155</code></a>
</p>
</div>
<div class="description">
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">pts</code>
<span class="type">Vector3 Array</span>
<div class="param-description">
<p>A set of points that define the points the path will pass through (starting with starting control point, and ending with a control point)<br />
<i><strong>Note:</strong> The first and last item just define the angle of the end points, they are not actually used in the spline path itself. If you do not care about the angle you can jus set the first two items and last two items as the same value.</i></p>
</div>
</li>
</ul>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>LTSpline ltSpline = new LTSpline( new Vector3[] { new Vector3(0f,0f,0f),new Vector3(0f,0f,0f), new Vector3(0f,0.5f,0f), new Vector3(1f,1f,0f), new Vector3(1f,1f,0f)} );<br /><br />
LeanTween.moveSpline(lt, ltSpline.vec3, 4.0f).setOrientToPath(true).setDelay(1f).setEase(LeanTweenType.easeInOutQuad); // animate <br />
Vector3 pt = ltSpline.point( 0.6f ); // retrieve a point along the path</p>
</div>
</div>
</div>
</div>
<div id="classdocs" class="tabview">
<ul class="api-class-tabs">
<li class="api-class-tab index"><a href="#index">Index</a></li>
<li class="api-class-tab methods"><a href="#methods">Methods</a></li>
<li class="api-class-tab properties"><a href="#properties">Properties</a></li>
</ul>
<div>
<div id="index" class="api-class-tabpanel index">
<h2 class="off-left">Item Index</h2>
<div class="index-section methods">
<h3>Methods</h3>
<ul class="index-list methods">
<li class="index-item method">
<a href="#method_place">place</a>
</li>
<li class="index-item method">
<a href="#method_place">place</a>
</li>
<li class="index-item method">
<a href="#method_placeLocal">placeLocal</a>
</li>
<li class="index-item method">
<a href="#method_placeLocal">placeLocal</a>
</li>
<li class="index-item method">
<a href="#method_point">point</a>
</li>
<li class="index-item method">
<a href="#method_ratioAtPoint">ratioAtPoint</a>
</li>
</ul>
</div>
<div class="index-section properties">
<h3>Properties</h3>
<ul class="index-list properties">
<li class="index-item property">
<a href="#property_distance distance of the spline (in unity units)">distance distance of the spline (in unity units)</a>
</li>
</ul>
</div>
</div>
<div id="methods" class="api-class-tabpanel">
<h2 class="off-left">Methods</h2>
<div id="method_place" class="method item">
<h3 class="name"><code>place</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>transform:Transform</code>
</li>
<li class="arg">
<code>ratio:float</code>
</li>
</ul><span class="paren">)</span>
</div>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3373"><code>LeanTween.cs:3373</code></a>
</p>
</div>
<div class="description">
<p>Place an object along a certain point on the path (facing the direction perpendicular to the path) <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">transform:Transform</code>
<span class="type">Transform</span>
<div class="param-description">
<p>the transform of the object you wish to place along the path</p>
</div>
</li>
<li class="param">
<code class="param-name">ratio:float</code>
<span class="type">Float</span>
<div class="param-description">
<p>ratio of the point along the path you wish to receive (0-1)</p>
</div>
</li>
</ul>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>ltPath.place( transform, 0.6f );</p>
</div>
</div>
</div>
<div id="method_place" class="method item">
<h3 class="name"><code>place</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>transform:Transform</code>
</li>
<li class="arg">
<code>ratio:float</code>
</li>
<li class="arg">
<code>rotation:Vector3</code>
</li>
</ul><span class="paren">)</span>
</div>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3386"><code>LeanTween.cs:3386</code></a>
</p>
</div>
<div class="description">
<p>Place an object along a certain point on the path, with it facing a certain direction perpendicular to the path <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">transform:Transform</code>
<span class="type">Transform</span>
<div class="param-description">
<p>the transform of the object you wish to place along the path</p>
</div>
</li>
<li class="param">
<code class="param-name">ratio:float</code>
<span class="type">Float</span>
<div class="param-description">
<p>ratio of the point along the path you wish to receive (0-1)</p>
</div>
</li>
<li class="param">
<code class="param-name">rotation:Vector3</code>
<span class="type">Vector3</span>
<div class="param-description">
<p>the direction in which to place the transform ex: Vector3.up</p>
</div>
</li>
</ul>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>ltPath.place( transform, 0.6f, Vector3.left );</p>
</div>
</div>
</div>
<div id="method_placeLocal" class="method item">
<h3 class="name"><code>placeLocal</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>transform:Transform</code>
</li>
<li class="arg">
<code>ratio:float</code>
</li>
</ul><span class="paren">)</span>
</div>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3405"><code>LeanTween.cs:3405</code></a>
</p>
</div>
<div class="description">
<p>Place an object along a certain point on the path (facing the direction perpendicular to the path) - Local Space, not world-space <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">transform:Transform</code>
<span class="type">Transform</span>
<div class="param-description">
<p>the transform of the object you wish to place along the path</p>
</div>
</li>
<li class="param">
<code class="param-name">ratio:float</code>
<span class="type">Float</span>
<div class="param-description">
<p>ratio of the point along the path you wish to receive (0-1)</p>
</div>
</li>
</ul>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>ltPath.placeLocal( transform, 0.6f );</p>
</div>
</div>
</div>
<div id="method_placeLocal" class="method item">
<h3 class="name"><code>placeLocal</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>transform:Transform</code>
</li>
<li class="arg">
<code>ratio:float</code>
</li>
<li class="arg">
<code>rotation:Vector3</code>
</li>
</ul><span class="paren">)</span>
</div>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3418"><code>LeanTween.cs:3418</code></a>
</p>
</div>
<div class="description">
<p>Place an object along a certain point on the path, with it facing a certain direction perpendicular to the path - Local Space, not world-space <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">transform:Transform</code>
<span class="type">Transform</span>
<div class="param-description">
<p>the transform of the object you wish to place along the path</p>
</div>
</li>
<li class="param">
<code class="param-name">ratio:float</code>
<span class="type">Float</span>
<div class="param-description">
<p>ratio of the point along the path you wish to receive (0-1)</p>
</div>
</li>
<li class="param">
<code class="param-name">rotation:Vector3</code>
<span class="type">Vector3</span>
<div class="param-description">
<p>the direction in which to place the transform ex: Vector3.up</p>
</div>
</li>
</ul>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>ltPath.placeLocal( transform, 0.6f, Vector3.left );</p>
</div>
</div>
</div>
<div id="method_point" class="method item">
<h3 class="name"><code>point</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>ratio:float</code>
</li>
</ul><span class="paren">)</span>
</div>
<span class="returns-inline">
<span class="type">Vector3</span>
</span>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3332"><code>LeanTween.cs:3332</code></a>
</p>
</div>
<div class="description">
<p>Retrieve a point along a path <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">ratio:float</code>
<span class="type">Float</span>
<div class="param-description">
<p>ratio of the point along the path you wish to receive (0-1)</p>
</div>
</li>
</ul>
</div>
<div class="returns">
<h4>Returns:</h4>
<div class="returns-description">
<span class="type">Vector3</span>:
<p>Vector3 position of the point along the path</p>
</div>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>transform.position = ltSpline.point( 0.6f );</p>
</div>
</div>
</div>
<div id="method_ratioAtPoint" class="method item">
<h3 class="name"><code>ratioAtPoint</code></h3>
<div class="args">
<span class="paren">(</span><ul class="args-list inline commas">
<li class="arg">
<code>point:Vector3</code>
</li>
</ul><span class="paren">)</span>
</div>
<span class="returns-inline">
<span class="type">Float</span>
</span>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3308"><code>LeanTween.cs:3308</code></a>
</p>
</div>
<div class="description">
<p>Retrieve a point along a path <summary>Move a GameObject to a certain location</summary></p>
</div>
<div class="params">
<h4>Parameters:</h4>
<ul class="params-list">
<li class="param">
<code class="param-name">point:Vector3</code>
<span class="type">Vector3</span>
<div class="param-description">
<p>given a current location it makes the best approximiation of where it is along the path ratio-wise (0-1)</p>
</div>
</li>
</ul>
</div>
<div class="returns">
<h4>Returns:</h4>
<div class="returns-description">
<span class="type">Float</span>:
<p>float of ratio along the path</p>
</div>
</div>
<div class="example">
<h4>Example:</h4>
<div class="example-content">
<p>ratioIter = ltSpline.ratioAtPoint( transform.position );</p>
</div>
</div>
</div>
</div>
<div id="properties" class="api-class-tabpanel">
<h2 class="off-left">Properties</h2>
<div id="property_distance distance of the spline (in unity units)" class="property item">
<h3 class="name"><code>distance distance of the spline (in unity units)</code></h3>
<span class="type">Float</span>
<div class="meta">
<p>
Defined in
<a href="../files/LeanTween.cs.html#l3171"><code>LeanTween.cs:3171</code></a>
</p>
</div>
<div class="description">
</div>
</div>
</div>
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| unitystation/unitystation | UnityProject/Assets/Standard Assets/LeanTween/Documentation/classes/LTSpline.html | HTML | agpl-3.0 | 52,076 |
import Sofa
import SofaTest
import SofaPython.Tools
OBJ = SofaPython.Tools.localPath( __file__, "beam.obj" )
RAW = SofaPython.Tools.localPath( __file__, "beam.raw" )
##Check if calling Mapping::init() change anything
#
#The trick is to know that if the option evaluateShapeFunction is activated
#in the ImageGaussPointSampler then a sampler::bwdInit() must be called
#to update weights using gauss points.
class Controller(SofaTest.Controller):
def initGraph(self,node):
self.success = 1
self.count = 0
return 0
def createGraph(self,node):
self.node = node
return 0
def initAndCheckMapping(self, node):
mapping = node
oldWeights = mapping.findData("weights").value
oldWeightGradients = mapping.findData("weightGradients").value
oldWeightHessians = mapping.findData("weightHessians").value
mapping.init()
newWeights = mapping.findData("weights").value
newWeightGradients = mapping.findData("weightGradients").value
newWeightHessians = mapping.findData("weightHessians").value
if ( (oldWeights != newWeights) and (oldWeightGradients != newWeightGradients) and (oldWeightHessians != newWeightHessians) ):
self.success = 0
else:
self.success = 1
return 0
def onEndAnimationStep(self,dt):
return 0
def onBeginAnimationStep(self,dt):
self.count+=1
if(self.count == 2):
barycentricMapping = self.root.getChild("barycentricFrame").getChild("behavior").getObject("mapping")
self.initAndCheckMapping(barycentricMapping)
if(self.success == 0):
self.sendFailure("(Barycentric Shape Function) calling init once again changed linearMapping weights for no reason")
voronoiMapping = self.root.getChild("voronoiFrame").getChild("behavior").getObject("mapping")
self.initAndCheckMapping(voronoiMapping)
if(self.success == 0):
self.sendFailure("(Voronoi Shape Function) calling init once again changed linearMapping weights for no reason")
self.sendSuccess();
return 0
def createBarycentricFrame( parentNode, name ):
node = parentNode.createChild(name)
#Solver
node.createObject('EulerImplicit', name='integrator')
node.createObject('CGLinearSolver', name='linearSolver', iterations='200', tolerance="1e-15", threshold='1.0e-15')
#Frame
dofPosition="0 1.0 -0.999 1 0 0 0 1 0 0 0 1 " + "0 1.0 0.999 1 0 0 0 1 0 0 0 1 "
node.createObject('MechanicalObject', template='Affine', name='dofs', position=dofPosition, showObject='true,', showObjectScale='0.5')
node.createObject('UniformMass', template='Affine',totalMass='0.01')
#Constraint
node.createObject('BoxROI', name='roi', template='Vec3d', box="-1 -2 -1.2 1 2 -0.8", drawBoxes='true', drawSize=1)
node.createObject('FixedConstraint', indices="@[-1].indices")
#Shape function
node.createObject('MeshTopology', edges="0 0 0 1 1 1")
node.createObject('BarycentricShapeFunction', name="shapeFunc")
#Integration point sampling
behaviorNode = node.createChild('behavior')
behaviorNode.createObject("TopologyGaussPointSampler", name="sampler", inPosition="@../dofs.rest_position", showSamplesScale="0.1", drawMode="0")
behaviorNode.createObject('MechanicalObject', name="intePts", template='F332', showObject="true", showObjectScale="0.05")
behaviorNode.createObject('LinearMapping', name="mapping", template='Affine,F332', showDeformationGradientScale='0.2', showSampleScale="0", printLog="false")
#Behavior
eNode = behaviorNode.createChild('E')
eNode.createObject( 'MechanicalObject', name='E', template='E332' )
eNode.createObject( 'CorotationalStrainMapping', template='F332,E332', printLog='false' )
eNode.createObject( 'HookeForceField', template='E332', youngModulus='100', poissonRatio='0', viscosity='0' )
#Visu child node
visuNode = node.createChild('Visu')
visuNode.createObject('OglModel', template="ExtVec3f", name='Visual',filename=OBJ, translation="0 1 0")
visuNode.createObject('LinearMapping', template='Affine,ExtVec3f')
def createVoronoiFrame( parentNode, name ):
node = parentNode.createChild(name)
#Solver
node.createObject('EulerImplicit', name='integrator')
node.createObject('CGLinearSolver', name='linearSolver', iterations='200', tolerance="1e-15", threshold='1.0e-15')
#Frame
node.createObject("MeshObjLoader", name="mesh", filename=OBJ, triangulate="1")
node.createObject("ImageContainer", name="image", template="ImageUC", filename=RAW, drawBB="false")
node.createObject("ImageSampler", name="sampler", template="ImageUC", src="@image", method="1", param="0", fixedPosition="0 0 -0.999 0 0 0.999", printLog="false")
node.createObject("MergeMeshes", name="merged", nbMeshes="2", position1="@sampler.fixedPosition", position2="@sampler.position")
#node.createObject("ImageViewer", template="ImageB", name="viewer", src="@image")
node.createObject('MechanicalObject', template='Affine', name='dofs', src="@merged", showObject='true,', showObjectScale='0.5')
#Shape function
node.createObject('VoronoiShapeFunction', name="shapeFunc", position='@dofs.rest_position', src='@image', useDijkstra="true", method="0", nbRef="4")
#Uniform Mass
node.createObject('UniformMass', template='Affine',totalMass='0.01')
#Constraint
node.createObject('BoxROI', name='roi', template='Vec3d', box="-1 -2.0 -1.2 1 2.0 -0.8", drawBoxes='true', drawSize=1)
node.createObject('FixedConstraint', indices="@[-1].indices")
#Gauss point sampling
behaviorNode = node.createChild('behavior')
behaviorNode.createObject('ImageGaussPointSampler', name='sampler', indices='@../shapeFunc.indices', weights='@../shapeFunc.weights', transform='@../shapeFunc.transform', method='2', order='4', targetNumber='1', printLog='false', showSamplesScale=0.1, drawMode=0, evaluateShapeFunction="false")
behaviorNode.createObject('MechanicalObject', name="intePts", template='F332', showObject="false", showObjectScale="0.05")
behaviorNode.createObject('LinearMapping', name="mapping", template='Affine,F332', assembleJ='true', showDeformationGradientScale='0.2', printLog="false")
#Behavior
eNode = behaviorNode.createChild('E')
eNode.createObject( 'MechanicalObject', name='E', template='E332' )
eNode.createObject( 'CorotationalStrainMapping', template='F332,E332', printLog='false' )
eNode.createObject( 'HookeForceField', template='E332', youngModulus='100', poissonRatio='0', viscosity='0' )
#Visu child node
visuNode = node.createChild('Visu')
visuNode.createObject('OglModel', template="ExtVec3f", name='Visual',filename=OBJ)
visuNode.createObject('LinearMapping', template='Affine,ExtVec3f')
return node
def createScene( root ) :
#Root node data
root.findData('dt').value=0.001
root.findData('gravity').value='0 -10 0'
#Required setting
root.createObject('RequiredPlugin', name="flexible", pluginName='Flexible', printLog="false")
root.createObject('RequiredPlugin', name="image", pluginName='image', printLog="false")
#VisuStyle
root.createObject('VisualStyle', name='visuStyle', displayFlags='showWireframe showBehaviorModels')
#Animation Loop
root.createObject('DefaultAnimationLoop');
root.createObject('DefaultVisualManagerLoop');
#Python Script Controller
root.createObject('PythonScriptController', filename = __file__, classname='Controller')
createVoronoiFrame(root, 'voronoiFrame');
createBarycentricFrame(root, 'barycentricFrame');
| FabienPean/sofa | applications/plugins/Flexible/Flexible_test/scenes/python/reInitMapping.py | Python | lgpl-2.1 | 7,714 |
// ---------------------------------------------------------------------
//
// Copyright (C) 1999 - 2016 by the deal.II authors
//
// This file is part of the deal.II library.
//
// The deal.II library is free software; you can use it, redistribute
// it, and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
// The full text of the license can be found in the file LICENSE at
// the top level of the deal.II distribution.
//
// ---------------------------------------------------------------------
#include <deal.II/grid/grid_generator.h>
#include <deal.II/grid/grid_reordering.h>
#include <deal.II/grid/grid_tools.h>
#include <deal.II/grid/tria.h>
#include <deal.II/grid/tria_accessor.h>
#include <deal.II/grid/tria_iterator.h>
#include <deal.II/grid/tria_boundary_lib.h>
#include <deal.II/grid/intergrid_map.h>
#include <deal.II/distributed/tria.h>
#include <deal.II/distributed/shared_tria.h>
#include <iostream>
#include <cmath>
#include <limits>
DEAL_II_NAMESPACE_OPEN
namespace GridGenerator
{
namespace
{
// Corner points of the cube [-1,1]^3
const Point<3> hexahedron[8] =
{
Point<3>(-1,-1,-1),
Point<3>(+1,-1,-1),
Point<3>(-1,+1,-1),
Point<3>(+1,+1,-1),
Point<3>(-1,-1,+1),
Point<3>(+1,-1,+1),
Point<3>(-1,+1,+1),
Point<3>(+1,+1,+1)
};
// Octahedron inscribed in the cube
// [-1,1]^3
const Point<3> octahedron[6] =
{
Point<3>(-1, 0, 0),
Point<3>( 1, 0, 0),
Point<3>( 0,-1, 0),
Point<3>( 0, 1, 0),
Point<3>( 0, 0,-1),
Point<3>( 0, 0, 1)
};
/**
* Perform the action specified by the @p colorize flag of the
* hyper_rectangle() function of this class.
*/
template <int dim, int spacedim>
void
colorize_hyper_rectangle (Triangulation<dim,spacedim> &tria)
{
// there is nothing to do in 1d
if (dim > 1)
{
// there is only one cell, so
// simple task
const typename Triangulation<dim,spacedim>::cell_iterator
cell = tria.begin();
for (unsigned int f=0; f<GeometryInfo<dim>::faces_per_cell; ++f)
cell->face(f)->set_boundary_id (f);
}
}
template<int spacedim>
void
colorize_subdivided_hyper_rectangle (Triangulation<1,spacedim> &tria,
const Point<spacedim> &,
const Point<spacedim> &,
const double)
{
for (typename Triangulation<1,spacedim>::cell_iterator cell = tria.begin();
cell != tria.end(); ++cell)
if (cell->center()(0) > 0)
cell->set_material_id(1);
// boundary indicators are set to
// 0 (left) and 1 (right) by default.
}
template <int dim, int spacedim>
void
colorize_subdivided_hyper_rectangle (Triangulation<dim,spacedim> &tria,
const Point<spacedim> &p1,
const Point<spacedim> &p2,
const double epsilon)
{
// run through all faces and check
// if one of their center coordinates matches
// one of the corner points. Comparisons
// are made using an epsilon which
// should be smaller than the smallest cell
// diameter.
typename Triangulation<dim,spacedim>::face_iterator face = tria.begin_face(),
endface = tria.end_face();
for (; face!=endface; ++face)
if (face->at_boundary())
if (face->boundary_id() == 0)
{
const Point<spacedim> center (face->center());
if (std::abs(center(0)-p1[0]) < epsilon)
face->set_boundary_id(0);
else if (std::abs(center(0) - p2[0]) < epsilon)
face->set_boundary_id(1);
else if (dim > 1 && std::abs(center(1) - p1[1]) < epsilon)
face->set_boundary_id(2);
else if (dim > 1 && std::abs(center(1) - p2[1]) < epsilon)
face->set_boundary_id(3);
else if (dim > 2 && std::abs(center(2) - p1[2]) < epsilon)
face->set_boundary_id(4);
else if (dim > 2 && std::abs(center(2) - p2[2]) < epsilon)
face->set_boundary_id(5);
else
// triangulation says it
// is on the boundary,
// but we could not find
// on which boundary.
Assert (false, ExcInternalError());
}
for (typename Triangulation<dim,spacedim>::cell_iterator cell = tria.begin();
cell != tria.end(); ++cell)
{
char id = 0;
for (unsigned int d=0; d<dim; ++d)
if (cell->center()(d) > 0)
id += (1 << d);
cell->set_material_id(id);
}
}
/**
* Assign boundary number zero to the inner shell boundary and 1 to the
* outer.
*/
void
colorize_hyper_shell (Triangulation<2> &tria,
const Point<2> &,
const double,
const double)
{
// In spite of receiving geometrical
// data, we do this only based on
// topology.
// For the mesh based on cube,
// this is highly irregular
for (Triangulation<2>::cell_iterator cell = tria.begin ();
cell != tria.end (); ++cell)
{
Assert(cell->face(2)->at_boundary(), ExcInternalError());
cell->face (2)->set_all_boundary_ids (1);
}
}
/**
* Assign boundary number zero to the inner shell boundary and 1 to the
* outer.
*/
void
colorize_hyper_shell (Triangulation<3> &tria,
const Point<3> &,
const double,
const double)
{
// the following uses a good amount
// of knowledge about the
// orientation of cells. this is
// probably not good style...
if (tria.n_cells() == 6)
{
Triangulation<3>::cell_iterator cell = tria.begin();
Assert (cell->face(4)->at_boundary(), ExcInternalError());
cell->face(4)->set_all_boundary_ids(1);
++cell;
Assert (cell->face(2)->at_boundary(), ExcInternalError());
cell->face(2)->set_all_boundary_ids(1);
++cell;
Assert (cell->face(2)->at_boundary(), ExcInternalError());
cell->face(2)->set_all_boundary_ids(1);
++cell;
Assert (cell->face(0)->at_boundary(), ExcInternalError());
cell->face(0)->set_all_boundary_ids(1);
++cell;
Assert (cell->face(2)->at_boundary(), ExcInternalError());
cell->face(2)->set_all_boundary_ids(1);
++cell;
Assert (cell->face(0)->at_boundary(), ExcInternalError());
cell->face(0)->set_all_boundary_ids(1);
}
else if (tria.n_cells() == 12)
{
// again use some internal
// knowledge
for (Triangulation<3>::cell_iterator cell = tria.begin();
cell != tria.end(); ++cell)
{
Assert (cell->face(5)->at_boundary(), ExcInternalError());
cell->face(5)->set_all_boundary_ids(1);
}
}
else if (tria.n_cells() == 96)
{
// the 96-cell hypershell is
// based on a once refined
// 12-cell mesh. consequently,
// since the outer faces all
// are face_no==5 above, so
// they are here (unless they
// are in the interior). Use
// this to assign boundary
// indicators, but also make
// sure that we encounter
// exactly 48 such faces
unsigned int count = 0;
for (Triangulation<3>::cell_iterator cell = tria.begin();
cell != tria.end(); ++cell)
if (cell->face(5)->at_boundary())
{
cell->face(5)->set_all_boundary_ids(1);
++count;
}
Assert (count == 48, ExcInternalError());
}
else
Assert (false, ExcNotImplemented());
}
/**
* Assign boundary number zero the inner shell boundary, one to the outer
* shell boundary, two to the face with x=0, three to the face with y=0,
* four to the face with z=0.
*/
void
colorize_quarter_hyper_shell(Triangulation<3> &tria,
const Point<3> ¢er,
const double inner_radius,
const double outer_radius)
{
if (tria.n_cells() != 3)
AssertThrow (false, ExcNotImplemented());
double middle = (outer_radius-inner_radius)/2e0 + inner_radius;
double eps = 1e-3*middle;
Triangulation<3>::cell_iterator cell = tria.begin();
for (; cell!=tria.end(); ++cell)
for (unsigned int f=0; f<GeometryInfo<3>::faces_per_cell; ++f)
{
if (!cell->face(f)->at_boundary())
continue;
double radius = cell->face(f)->center().norm() - center.norm();
if (std::fabs(cell->face(f)->center()(0)) < eps ) // x = 0 set boundary 2
{
cell->face(f)->set_boundary_id(2);
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
if (cell->face(f)->line(j)->at_boundary())
if (std::fabs(cell->face(f)->line(j)->vertex(0).norm() - cell->face(f)->line(j)->vertex(1).norm()) > eps)
cell->face(f)->line(j)->set_boundary_id(2);
}
else if (std::fabs(cell->face(f)->center()(1)) < eps) // y = 0 set boundary 3
{
cell->face(f)->set_boundary_id(3);
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
if (cell->face(f)->line(j)->at_boundary())
if (std::fabs(cell->face(f)->line(j)->vertex(0).norm() - cell->face(f)->line(j)->vertex(1).norm()) > eps)
cell->face(f)->line(j)->set_boundary_id(3);
}
else if (std::fabs(cell->face(f)->center()(2)) < eps ) // z = 0 set boundary 4
{
cell->face(f)->set_boundary_id(4);
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
if (cell->face(f)->line(j)->at_boundary())
if (std::fabs(cell->face(f)->line(j)->vertex(0).norm() - cell->face(f)->line(j)->vertex(1).norm()) > eps)
cell->face(f)->line(j)->set_boundary_id(4);
}
else if (radius < middle) // inner radius set boundary 0
{
cell->face(f)->set_boundary_id(0);
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
if (cell->face(f)->line(j)->at_boundary())
if (std::fabs(cell->face(f)->line(j)->vertex(0).norm() - cell->face(f)->line(j)->vertex(1).norm()) < eps)
cell->face(f)->line(j)->set_boundary_id(0);
}
else if (radius > middle) // outer radius set boundary 1
{
cell->face(f)->set_boundary_id(1);
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
if (cell->face(f)->line(j)->at_boundary())
if (std::fabs(cell->face(f)->line(j)->vertex(0).norm() - cell->face(f)->line(j)->vertex(1).norm()) < eps)
cell->face(f)->line(j)->set_boundary_id(1);
}
else
AssertThrow (false, ExcInternalError());
}
}
}
template <int dim, int spacedim>
void
hyper_rectangle (Triangulation<dim,spacedim> &tria,
const Point<dim> &p_1,
const Point<dim> &p_2,
const bool colorize)
{
// First, extend dimensions from dim to spacedim and
// normalize such that p1 is lower in all coordinate
// directions. Additional entries will be 0.
Point<spacedim> p1, p2;
for (unsigned int i=0; i<dim; ++i)
{
p1(i) = std::min(p_1(i), p_2(i));
p2(i) = std::max(p_1(i), p_2(i));
}
std::vector<Point<spacedim> > vertices (GeometryInfo<dim>::vertices_per_cell);
switch (dim)
{
case 1:
vertices[0] = p1;
vertices[1] = p2;
break;
case 2:
vertices[0] = vertices[1] = p1;
vertices[2] = vertices[3] = p2;
vertices[1](0) = p2(0);
vertices[2](0) = p1(0);
break;
case 3:
vertices[0] = vertices[1] = vertices[2] = vertices[3] = p1;
vertices[4] = vertices[5] = vertices[6] = vertices[7] = p2;
vertices[1](0) = p2(0);
vertices[2](1) = p2(1);
vertices[3](0) = p2(0);
vertices[3](1) = p2(1);
vertices[4](0) = p1(0);
vertices[4](1) = p1(1);
vertices[5](1) = p1(1);
vertices[6](0) = p1(0);
break;
default:
Assert (false, ExcNotImplemented ());
}
// Prepare cell data
std::vector<CellData<dim> > cells (1);
for (unsigned int i=0; i<GeometryInfo<dim>::vertices_per_cell; ++i)
cells[0].vertices[i] = i;
cells[0].material_id = 0;
tria.create_triangulation (vertices, cells, SubCellData());
// Assign boundary indicators
if (colorize)
colorize_hyper_rectangle (tria);
}
template <int dim, int spacedim>
void hyper_cube (Triangulation<dim,spacedim> &tria,
const double left,
const double right,
const bool colorize)
{
Assert (left < right,
ExcMessage ("Invalid left-to-right bounds of hypercube"));
Point<dim> p1, p2;
for (unsigned int i=0; i<dim; ++i)
{
p1(i) = left;
p2(i) = right;
}
hyper_rectangle (tria, p1, p2, colorize);
}
template <int dim>
void
simplex(Triangulation<dim> &tria,
const std::vector<Point<dim> > &vertices)
{
AssertDimension(vertices.size(), dim+1);
Assert(dim>1, ExcNotImplemented());
Assert(dim<4, ExcNotImplemented());
#ifdef DEBUG
Tensor<2,dim> vector_matrix;
for (unsigned int d=0; d<dim; ++d)
for (unsigned int c=1; c<=dim; ++c)
vector_matrix[c-1][d] = vertices[c](d) - vertices[0](d);
Assert(determinant(vector_matrix) > 0., ExcMessage("Vertices of simplex must form a right handed system"));
#endif
// Set up the vertices by first copying into points.
std::vector<Point<dim> > points = vertices;
Point<dim> center;
// Compute the edge midpoints and add up everything to compute the
// center point.
for (unsigned int i=0; i<=dim; ++i)
{
points.push_back(0.5*(points[i]+points[(i+1)%(dim+1)]));
center += points[i];
}
if (dim>2)
{
// In 3D, we have some more edges to deal with
for (unsigned int i=1; i<dim; ++i)
points.push_back(0.5*(points[i-1]+points[i+1]));
// And we need face midpoints
for (unsigned int i=0; i<=dim; ++i)
points.push_back(1./3.*
(points[i]+
points[(i+1)%(dim+1)]+
points[(i+2)%(dim+1)]));
}
points.push_back((1./(dim+1))*center);
std::vector<CellData<dim> > cells(dim+1);
switch (dim)
{
case 2:
AssertDimension(points.size(), 7);
cells[0].vertices[0] = 0;
cells[0].vertices[1] = 3;
cells[0].vertices[2] = 5;
cells[0].vertices[3] = 6;
cells[0].material_id = 0;
cells[1].vertices[0] = 3;
cells[1].vertices[1] = 1;
cells[1].vertices[2] = 6;
cells[1].vertices[3] = 4;
cells[1].material_id = 0;
cells[2].vertices[0] = 5;
cells[2].vertices[1] = 6;
cells[2].vertices[2] = 2;
cells[2].vertices[3] = 4;
cells[2].material_id = 0;
break;
case 3:
AssertDimension(points.size(), 15);
cells[0].vertices[0] = 0;
cells[0].vertices[1] = 4;
cells[0].vertices[2] = 8;
cells[0].vertices[3] = 10;
cells[0].vertices[4] = 7;
cells[0].vertices[5] = 13;
cells[0].vertices[6] = 12;
cells[0].vertices[7] = 14;
cells[0].material_id = 0;
cells[1].vertices[0] = 4;
cells[1].vertices[1] = 1;
cells[1].vertices[2] = 10;
cells[1].vertices[3] = 5;
cells[1].vertices[4] = 13;
cells[1].vertices[5] = 9;
cells[1].vertices[6] = 14;
cells[1].vertices[7] = 11;
cells[1].material_id = 0;
cells[2].vertices[0] = 8;
cells[2].vertices[1] = 10;
cells[2].vertices[2] = 2;
cells[2].vertices[3] = 5;
cells[2].vertices[4] = 12;
cells[2].vertices[5] = 14;
cells[2].vertices[6] = 6;
cells[2].vertices[7] = 11;
cells[2].material_id = 0;
cells[3].vertices[0] = 7;
cells[3].vertices[1] = 13;
cells[3].vertices[2] = 12;
cells[3].vertices[3] = 14;
cells[3].vertices[4] = 3;
cells[3].vertices[5] = 9;
cells[3].vertices[6] = 6;
cells[3].vertices[7] = 11;
cells[3].material_id = 0;
break;
default:
Assert(false, ExcNotImplemented());
}
tria.create_triangulation (points, cells, SubCellData());
}
void
moebius (Triangulation<3> &tria,
const unsigned int n_cells,
const unsigned int n_rotations,
const double R,
const double r)
{
const unsigned int dim=3;
Assert (n_cells>4, ExcMessage("More than 4 cells are needed to create a moebius grid."));
Assert (r>0 && R>0, ExcMessage("Outer and inner radius must be positive."));
Assert (R>r, ExcMessage("Outer radius must be greater than inner radius."));
std::vector<Point<dim> > vertices (4*n_cells);
double beta_step=n_rotations*numbers::PI/2.0/n_cells;
double alpha_step=2.0*numbers::PI/n_cells;
for (unsigned int i=0; i<n_cells; ++i)
for (unsigned int j=0; j<4; ++j)
{
vertices[4*i+j][0]=R*std::cos(i*alpha_step)+r*std::cos(i*beta_step+j*numbers::PI/2.0)*std::cos(i*alpha_step);
vertices[4*i+j][1]=R*std::sin(i*alpha_step)+r*std::cos(i*beta_step+j*numbers::PI/2.0)*std::sin(i*alpha_step);
vertices[4*i+j][2]=r*std::sin(i*beta_step+j*numbers::PI/2.0);
}
unsigned int offset=0;
std::vector<CellData<dim> > cells (n_cells);
for (unsigned int i=0; i<n_cells; ++i)
{
for (unsigned int j=0; j<2; ++j)
{
cells[i].vertices[0+4*j]=offset+0+4*j;
cells[i].vertices[1+4*j]=offset+3+4*j;
cells[i].vertices[2+4*j]=offset+2+4*j;
cells[i].vertices[3+4*j]=offset+1+4*j;
}
offset+=4;
cells[i].material_id=0;
}
// now correct the last four vertices
cells[n_cells-1].vertices[4]=(0+n_rotations)%4;
cells[n_cells-1].vertices[5]=(3+n_rotations)%4;
cells[n_cells-1].vertices[6]=(2+n_rotations)%4;
cells[n_cells-1].vertices[7]=(1+n_rotations)%4;
GridReordering<dim>::invert_all_cells_of_negative_grid(vertices,cells);
tria.create_triangulation_compatibility (vertices, cells, SubCellData());
}
template<>
void
torus<2,3> (Triangulation<2,3> &tria,
const double R,
const double r)
{
Assert (R>r, ExcMessage("Outer radius R must be greater than the inner "
"radius r."));
Assert (r>0.0, ExcMessage("The inner radius r must be positive."));
const unsigned int dim=2;
const unsigned int spacedim=3;
std::vector<Point<spacedim> > vertices (16);
vertices[0]=Point<spacedim>(R-r,0,0);
vertices[1]=Point<spacedim>(R,-r,0);
vertices[2]=Point<spacedim>(R+r,0,0);
vertices[3]=Point<spacedim>(R, r,0);
vertices[4]=Point<spacedim>(0,0,R-r);
vertices[5]=Point<spacedim>(0,-r,R);
vertices[6]=Point<spacedim>(0,0,R+r);
vertices[7]=Point<spacedim>(0,r,R);
vertices[8]=Point<spacedim>(-(R-r),0,0);
vertices[9]=Point<spacedim>(-R,-r,0);
vertices[10]=Point<spacedim>(-(R+r),0,0);
vertices[11]=Point<spacedim>(-R, r,0);
vertices[12]=Point<spacedim>(0,0,-(R-r));
vertices[13]=Point<spacedim>(0,-r,-R);
vertices[14]=Point<spacedim>(0,0,-(R+r));
vertices[15]=Point<spacedim>(0,r,-R);
std::vector<CellData<dim> > cells (16);
//Right Hand Orientation
cells[0].vertices[0] = 0;
cells[0].vertices[1] = 4;
cells[0].vertices[2] = 7;
cells[0].vertices[3] = 3;
cells[0].material_id = 0;
cells[1].vertices[0] = 1;
cells[1].vertices[1] = 5;
cells[1].vertices[2] = 4;
cells[1].vertices[3] = 0;
cells[1].material_id = 0;
cells[2].vertices[0] = 2;
cells[2].vertices[1] = 6;
cells[2].vertices[2] = 5;
cells[2].vertices[3] = 1;
cells[2].material_id = 0;
cells[3].vertices[0] = 3;
cells[3].vertices[1] = 7;
cells[3].vertices[2] = 6;
cells[3].vertices[3] = 2;
cells[3].material_id = 0;
cells[4].vertices[0] = 4;
cells[4].vertices[1] = 8;
cells[4].vertices[2] = 11;
cells[4].vertices[3] = 7;
cells[4].material_id = 0;
cells[5].vertices[0] = 5;
cells[5].vertices[1] = 9;
cells[5].vertices[2] = 8;
cells[5].vertices[3] = 4;
cells[5].material_id = 0;
cells[6].vertices[0] = 6;
cells[6].vertices[1] = 10;
cells[6].vertices[2] = 9;
cells[6].vertices[3] = 5;
cells[6].material_id = 0;
cells[7].vertices[0] = 7;
cells[7].vertices[1] = 11;
cells[7].vertices[2] = 10;
cells[7].vertices[3] = 6;
cells[7].material_id = 0;
cells[8].vertices[0] = 8;
cells[8].vertices[1] = 12;
cells[8].vertices[2] = 15;
cells[8].vertices[3] = 11;
cells[8].material_id = 0;
cells[9].vertices[0] = 9;
cells[9].vertices[1] = 13;
cells[9].vertices[2] = 12;
cells[9].vertices[3] = 8;
cells[9].material_id = 0;
cells[10].vertices[0] = 10;
cells[10].vertices[1] = 14;
cells[10].vertices[2] = 13;
cells[10].vertices[3] = 9;
cells[10].material_id = 0;
cells[11].vertices[0] = 11;
cells[11].vertices[1] = 15;
cells[11].vertices[2] = 14;
cells[11].vertices[3] = 10;
cells[11].material_id = 0;
cells[12].vertices[0] = 12;
cells[12].vertices[1] = 0;
cells[12].vertices[2] = 3;
cells[12].vertices[3] = 15;
cells[12].material_id = 0;
cells[13].vertices[0] = 13;
cells[13].vertices[1] = 1;
cells[13].vertices[2] = 0;
cells[13].vertices[3] = 12;
cells[13].material_id = 0;
cells[14].vertices[0] = 14;
cells[14].vertices[1] = 2;
cells[14].vertices[2] = 1;
cells[14].vertices[3] = 13;
cells[14].material_id = 0;
cells[15].vertices[0] = 15;
cells[15].vertices[1] = 3;
cells[15].vertices[2] = 2;
cells[15].vertices[3] = 14;
cells[15].material_id = 0;
// Must call this to be able to create a
// correct triangulation in dealii, read
// GridReordering<> doc
GridReordering<dim,spacedim>::reorder_cells (cells);
tria.create_triangulation_compatibility (vertices, cells, SubCellData());
tria.set_all_manifold_ids(0);
}
template<>
void
torus<3,3> (Triangulation<3,3> &tria,
const double R,
const double r)
{
Assert (R>r, ExcMessage("Outer radius R must be greater than the inner "
"radius r."));
Assert (r>0.0, ExcMessage("The inner radius r must be positive."));
// abuse the moebius function to generate a torus for us
GridGenerator::moebius(tria,
6 /*n_cells*/,
0 /*n_rotations*/,
R,
r);
// rotate by 90 degrees around the x axis to make the torus sit in the
// x-z plane instead of the x-y plane to be consistent with the other
// torus() function.
GridTools::rotate(numbers::PI/2.0, 0, tria);
// set manifolds as documented
tria.set_all_manifold_ids(1);
tria.set_all_manifold_ids_on_boundary(0);
}
template <int dim>
void
general_cell (Triangulation<dim> &tria,
const std::vector<Point<dim> > &vertices,
const bool colorize)
{
Assert (vertices.size() == dealii::GeometryInfo<dim>::vertices_per_cell,
ExcMessage("Wrong number of vertices."));
// First create a hyper_rectangle and then deform it.
hyper_cube(tria, 0, 1, colorize);
typename Triangulation<dim>::active_cell_iterator cell = tria.begin_active();
for (unsigned int i=0; i<GeometryInfo<dim>::vertices_per_cell; ++i)
cell->vertex(i) = vertices[i];
// Check that the order of the vertices makes sense, i.e., the volume of the
// cell is positive.
Assert(GridTools::volume(tria) > 0.,
ExcMessage("The volume of the cell is not greater than zero. "
"This could be due to the wrong ordering of the vertices."));
}
template<>
void
parallelogram (Triangulation<3> &,
const Point<3> ( &/*corners*/)[3],
const bool /*colorize*/)
{
Assert (false, ExcNotImplemented());
}
template<>
void
parallelogram (Triangulation<1> &,
const Point<1> ( &/*corners*/)[1],
const bool /*colorize*/)
{
Assert (false, ExcNotImplemented());
}
// Implementation for 2D only
template<>
void
parallelogram (Triangulation<2> &tria,
const Point<2> (&corners)[2],
const bool colorize)
{
Point<2> origin;
std_cxx11::array<Tensor<1,2>,2> edges;
edges[0] = corners[0];
edges[1] = corners[1];
std::vector<unsigned int> subdivisions;
subdivided_parallelepiped<2,2>(tria, origin, edges, subdivisions, colorize);
}
template<int dim>
void
parallelepiped (Triangulation<dim> &tria,
const Point<dim> (&corners) [dim],
const bool colorize)
{
unsigned int n_subdivisions [dim];
for (unsigned int i=0; i<dim; ++i)
n_subdivisions[i] = 1;
// and call the function below
subdivided_parallelepiped (tria, n_subdivisions,
corners,
colorize);
}
template<int dim>
void
subdivided_parallelepiped (Triangulation<dim> &tria,
const unsigned int n_subdivisions,
const Point<dim> (&corners) [dim],
const bool colorize)
{
// Equalise number of subdivisions in each dim-direction, their
// validity will be checked later
unsigned int n_subdivisions_ [dim];
for (unsigned int i=0; i<dim; ++i)
n_subdivisions_[i] = n_subdivisions;
// and call the function below
subdivided_parallelepiped (tria, n_subdivisions_,
corners,
colorize);
}
template<int dim>
void
subdivided_parallelepiped (Triangulation<dim> &tria,
#ifndef _MSC_VER
const unsigned int(&n_subdivisions)[dim],
#else
const unsigned int *n_subdivisions,
#endif
const Point<dim> (&corners) [dim],
const bool colorize)
{
Point<dim> origin;
std::vector<unsigned int> subdivisions;
std_cxx11::array<Tensor<1,dim>,dim> edges;
for (unsigned int i=0; i<dim; ++i)
{
subdivisions.push_back(n_subdivisions[i]);
edges[i] = corners[i];
}
subdivided_parallelepiped<dim,dim> (tria, origin, edges, subdivisions, colorize);
}
// Parallelepiped implementation in 1d, 2d, and 3d. @note The
// implementation in 1d is similar to hyper_rectangle(), and in 2d is
// similar to parallelogram().
//
// The GridReordering::reorder_grid is made use of towards the end of
// this function. Thus the triangulation is explicitly constructed for
// all dim here since it is slightly different in that respect
// (cf. hyper_rectangle(), parallelogram()).
template <int dim, int spacedim>
void
subdivided_parallelepiped (Triangulation<dim, spacedim> &tria,
const Point<spacedim> &origin,
const std_cxx11::array<Tensor<1,spacedim>,dim> &edges,
const std::vector<unsigned int> &subdivisions,
const bool colorize)
{
std::vector<unsigned int> compute_subdivisions = subdivisions;
if (compute_subdivisions.size() == 0)
{
compute_subdivisions.resize(dim, 1);
}
Assert(compute_subdivisions.size()==dim,
ExcMessage("One subdivision must be provided for each dimension."));
// check subdivisions
for (unsigned int i=0; i<dim; ++i)
{
Assert (compute_subdivisions[i]>0, ExcInvalidRepetitions(subdivisions[i]));
Assert (edges[i].norm()>0,
ExcMessage("Edges in subdivided_parallelepiped() must not be degenerate."));
}
/*
* Verify that the edge points to the right in 1D, vectors are oriented in
* a counter clockwise direction in 2D, or form a right handed system in
* 3D.
*/
bool twisted_data = false;
switch (dim)
{
case 1:
{
twisted_data = (edges[0][0] < 0);
break;
}
case 2:
{
if (spacedim == 2) // this check does not make sense otherwise
{
const double plane_normal = edges[0][0]*edges[1][1] - edges[0][1]*edges[1][0];
twisted_data = (plane_normal < 0.0);
}
break;
}
case 3:
{
// Check that the first two vectors are not linear combinations to
// avoid zero division later on.
Assert(std::abs(edges[0]*edges[1]
/(edges[0].norm()*edges[1].norm())
- 1.0) > 1.0e-15,
ExcMessage("Edges in subdivided_parallelepiped() must point in"
" different directions."));
const Tensor<1, spacedim> plane_normal = cross_product_3d
(edges[0], edges[1]);
/*
* Ensure that edges 1, 2, and 3 form a right-handed set of
* vectors. This works by applying the definition of the dot product
*
* cos(theta) = dot(x, y)/(norm(x)*norm(y))
*
* and then, since the normal vector and third edge should both point
* away from the plane formed by the first two edges, the angle
* between them must be between 0 and pi/2; hence we just need
*
* 0 < dot(x, y).
*/
twisted_data = (plane_normal*edges[2] < 0.0);
break;
}
default:
Assert(false, ExcInternalError());
}
(void)twisted_data; // make the static analyzer happy
Assert(!twisted_data,
ExcInvalidInputOrientation
("The triangulation you are trying to create will consist of cells"
" with negative measures. This is usually the result of input data"
" that does not define a right-handed coordinate system. The usual"
" fix for this is to ensure that in 1D the given point is to the"
" right of the origin (or the given edge tensor is positive), in 2D"
" that the two edges (and their cross product) obey the right-hand"
" rule (which may usually be done by switching the order of the"
" points or edge tensors), or in 3D that the edges form a"
" right-handed coordinate system (which may also be accomplished by"
" switching the order of the first two points or edge tensors)."));
// Check corners do not overlap (unique)
for (unsigned int i=0; i<dim; ++i)
for (unsigned int j=i+1; j<dim; ++j)
Assert ((edges[i]!=edges[j]),
ExcMessage ("Degenerate edges of subdivided_parallelepiped encountered."));
// Create a list of points
std::vector<Point<spacedim> > points;
switch (dim)
{
case 1:
for (unsigned int x=0; x<=compute_subdivisions[0]; ++x)
points.push_back (origin + edges[0]/compute_subdivisions[0]*x);
break;
case 2:
for (unsigned int y=0; y<=compute_subdivisions[1]; ++y)
for (unsigned int x=0; x<=compute_subdivisions[0]; ++x)
points.push_back (origin
+ edges[0]/compute_subdivisions[0]*x
+ edges[1]/compute_subdivisions[1]*y);
break;
case 3:
for (unsigned int z=0; z<=compute_subdivisions[2]; ++z)
for (unsigned int y=0; y<=compute_subdivisions[1]; ++y)
for (unsigned int x=0; x<=compute_subdivisions[0]; ++x)
points.push_back (
origin
+ edges[0]/compute_subdivisions[0]*x
+ edges[1]/compute_subdivisions[1]*y
+ edges[2]/compute_subdivisions[2]*z);
break;
default:
Assert (false, ExcNotImplemented());
}
// Prepare cell data
unsigned int n_cells = 1;
for (unsigned int i=0; i<dim; ++i)
n_cells *= compute_subdivisions[i];
std::vector<CellData<dim> > cells (n_cells);
// Create fixed ordering of
switch (dim)
{
case 1:
for (unsigned int x=0; x<compute_subdivisions[0]; ++x)
{
cells[x].vertices[0] = x;
cells[x].vertices[1] = x+1;
// wipe material id
cells[x].material_id = 0;
}
break;
case 2:
{
// Shorthand
const unsigned int n_dy = compute_subdivisions[1];
const unsigned int n_dx = compute_subdivisions[0];
for (unsigned int y=0; y<n_dy; ++y)
for (unsigned int x=0; x<n_dx; ++x)
{
const unsigned int c = y*n_dx + x;
cells[c].vertices[0] = y*(n_dx+1) + x;
cells[c].vertices[1] = y*(n_dx+1) + x+1;
cells[c].vertices[2] = (y+1)*(n_dx+1) + x;
cells[c].vertices[3] = (y+1)*(n_dx+1) + x+1;
// wipe material id
cells[c].material_id = 0;
}
}
break;
case 3:
{
// Shorthand
const unsigned int n_dz = compute_subdivisions[2];
const unsigned int n_dy = compute_subdivisions[1];
const unsigned int n_dx = compute_subdivisions[0];
for (unsigned int z=0; z<n_dz; ++z)
for (unsigned int y=0; y<n_dy; ++y)
for (unsigned int x=0; x<n_dx; ++x)
{
const unsigned int c = z*n_dy*n_dx + y*n_dx + x;
cells[c].vertices[0] = z*(n_dy+1)*(n_dx+1) + y*(n_dx+1) + x;
cells[c].vertices[1] = z*(n_dy+1)*(n_dx+1) + y*(n_dx+1) + x+1;
cells[c].vertices[2] = z*(n_dy+1)*(n_dx+1) + (y+1)*(n_dx+1) + x;
cells[c].vertices[3] = z*(n_dy+1)*(n_dx+1) + (y+1)*(n_dx+1) + x+1;
cells[c].vertices[4] = (z+1)*(n_dy+1)*(n_dx+1) + y*(n_dx+1) + x;
cells[c].vertices[5] = (z+1)*(n_dy+1)*(n_dx+1) + y*(n_dx+1) + x+1;
cells[c].vertices[6] = (z+1)*(n_dy+1)*(n_dx+1) + (y+1)*(n_dx+1) + x;
cells[c].vertices[7] = (z+1)*(n_dy+1)*(n_dx+1) + (y+1)*(n_dx+1) + x+1;
// wipe material id
cells[c].material_id = 0;
}
break;
}
default:
Assert (false, ExcNotImplemented());
}
// Create triangulation
// reorder the cells to ensure that they satisfy the convention for
// edge and face directions
GridReordering<dim>::reorder_cells(cells, true);
tria.create_triangulation (points, cells, SubCellData());
// Finally assign boundary indicators according to hyper_rectangle
if (colorize)
{
typename Triangulation<dim>::active_cell_iterator
cell = tria.begin_active(),
endc = tria.end();
for (; cell!=endc; ++cell)
{
for (unsigned int face=0; face<GeometryInfo<dim>::faces_per_cell; ++face)
{
if (cell->face(face)->at_boundary())
cell->face(face)->set_boundary_id(face);
}
}
}
}
template <int dim, int spacedim>
void
subdivided_hyper_cube (Triangulation<dim,spacedim> &tria,
const unsigned int repetitions,
const double left,
const double right)
{
Assert (repetitions >= 1, ExcInvalidRepetitions(repetitions));
Assert (left < right,
ExcMessage ("Invalid left-to-right bounds of hypercube"));
Point<dim> p0, p1;
for (unsigned int i=0; i<dim; ++i)
{
p0[i] = left;
p1[i] = right;
}
std::vector<unsigned int> reps(dim, repetitions);
subdivided_hyper_rectangle(tria, reps, p0, p1);
}
template <int dim, int spacedim>
void
subdivided_hyper_rectangle (
Triangulation<dim, spacedim> &tria,
const std::vector<unsigned int> &repetitions,
const Point<dim> &p_1,
const Point<dim> &p_2,
const bool colorize)
{
Assert(repetitions.size() == dim,
ExcInvalidRepetitionsDimension(dim));
// First, extend dimensions from dim to spacedim and
// normalize such that p1 is lower in all coordinate
// directions. Additional entries will be 0.
Point<spacedim> p1, p2;
for (unsigned int i=0; i<dim; ++i)
{
p1(i) = std::min(p_1(i), p_2(i));
p2(i) = std::max(p_1(i), p_2(i));
}
// calculate deltas and validate input
std::vector<Point<spacedim> > delta(dim);
for (unsigned int i=0; i<dim; ++i)
{
Assert (repetitions[i] >= 1, ExcInvalidRepetitions(repetitions[i]));
delta[i][i] = (p2[i]-p1[i])/repetitions[i];
Assert(delta[i][i]>0.0,
ExcMessage("The first dim entries of coordinates of p1 and p2 need to be different."));
}
// then generate the points
std::vector<Point<spacedim> > points;
switch (dim)
{
case 1:
for (unsigned int x=0; x<=repetitions[0]; ++x)
points.push_back (p1+(double)x*delta[0]);
break;
case 2:
for (unsigned int y=0; y<=repetitions[1]; ++y)
for (unsigned int x=0; x<=repetitions[0]; ++x)
points.push_back (p1+(double)x*delta[0]
+(double)y*delta[1]);
break;
case 3:
for (unsigned int z=0; z<=repetitions[2]; ++z)
for (unsigned int y=0; y<=repetitions[1]; ++y)
for (unsigned int x=0; x<=repetitions[0]; ++x)
points.push_back (p1+(double)x*delta[0] +
(double)y*delta[1] + (double)z*delta[2]);
break;
default:
Assert (false, ExcNotImplemented());
}
// next create the cells
std::vector<CellData<dim> > cells;
switch (dim)
{
case 1:
{
cells.resize (repetitions[0]);
for (unsigned int x=0; x<repetitions[0]; ++x)
{
cells[x].vertices[0] = x;
cells[x].vertices[1] = x+1;
cells[x].material_id = 0;
}
break;
}
case 2:
{
cells.resize (repetitions[1]*repetitions[0]);
for (unsigned int y=0; y<repetitions[1]; ++y)
for (unsigned int x=0; x<repetitions[0]; ++x)
{
const unsigned int c = x+y*repetitions[0];
cells[c].vertices[0] = y*(repetitions[0]+1)+x;
cells[c].vertices[1] = y*(repetitions[0]+1)+x+1;
cells[c].vertices[2] = (y+1)*(repetitions[0]+1)+x;
cells[c].vertices[3] = (y+1)*(repetitions[0]+1)+x+1;
cells[c].material_id = 0;
}
break;
}
case 3:
{
const unsigned int n_x = (repetitions[0]+1);
const unsigned int n_xy = (repetitions[0]+1)*(repetitions[1]+1);
cells.resize (repetitions[2]*repetitions[1]*repetitions[0]);
for (unsigned int z=0; z<repetitions[2]; ++z)
for (unsigned int y=0; y<repetitions[1]; ++y)
for (unsigned int x=0; x<repetitions[0]; ++x)
{
const unsigned int c = x+y*repetitions[0] +
z*repetitions[0]*repetitions[1];
cells[c].vertices[0] = z*n_xy + y*n_x + x;
cells[c].vertices[1] = z*n_xy + y*n_x + x+1;
cells[c].vertices[2] = z*n_xy + (y+1)*n_x + x;
cells[c].vertices[3] = z*n_xy + (y+1)*n_x + x+1;
cells[c].vertices[4] = (z+1)*n_xy + y*n_x + x;
cells[c].vertices[5] = (z+1)*n_xy + y*n_x + x+1;
cells[c].vertices[6] = (z+1)*n_xy + (y+1)*n_x + x;
cells[c].vertices[7] = (z+1)*n_xy + (y+1)*n_x + x+1;
cells[c].material_id = 0;
}
break;
}
default:
Assert (false, ExcNotImplemented());
}
tria.create_triangulation (points, cells, SubCellData());
if (colorize)
{
// to colorize, run through all
// faces of all cells and set
// boundary indicator to the
// correct value if it was 0.
// use a large epsilon to
// compare numbers to avoid
// roundoff problems.
double epsilon = 10;
for (unsigned int i=0; i<dim; ++i)
epsilon = std::min(epsilon, 0.01*delta[i][i]);
Assert (epsilon > 0,
ExcMessage ("The distance between corner points must be positive."))
// actual code is external since
// 1-D is different from 2/3D.
colorize_subdivided_hyper_rectangle (tria, p1, p2, epsilon);
}
}
template <int dim>
void
subdivided_hyper_rectangle(
Triangulation<dim> &tria,
const std::vector<std::vector<double> > &step_sz,
const Point<dim> &p_1,
const Point<dim> &p_2,
const bool colorize)
{
Assert(step_sz.size() == dim,
ExcInvalidRepetitionsDimension(dim));
// First, normalize input such that
// p1 is lower in all coordinate
// directions and check the consistency of
// step sizes, i.e. that they all
// add up to the sizes specified by
// p_1 and p_2
Point<dim> p1(p_1);
Point<dim> p2(p_2);
std::vector< std::vector<double> > step_sizes(step_sz);
for (unsigned int i=0; i<dim; ++i)
{
if (p1(i) > p2(i))
{
std::swap (p1(i), p2(i));
std::reverse (step_sizes[i].begin(), step_sizes[i].end());
}
double x = 0;
for (unsigned int j=0; j<step_sizes.at(i).size(); j++)
x += step_sizes[i][j];
Assert(std::fabs(x - (p2(i)-p1(i))) <= 1e-12*std::fabs(x),
ExcInvalidRepetitions (i) );
}
// then generate the necessary
// points
std::vector<Point<dim> > points;
switch (dim)
{
case 1:
{
double x=0;
for (unsigned int i=0; ; ++i)
{
points.push_back (Point<dim> (p1[0]+x));
// form partial sums. in
// the last run through
// avoid accessing
// non-existent values
// and exit early instead
if (i == step_sizes[0].size())
break;
x += step_sizes[0][i];
}
break;
}
case 2:
{
double y=0;
for (unsigned int j=0; ; ++j)
{
double x=0;
for (unsigned int i=0; ; ++i)
{
points.push_back (Point<dim> (p1[0]+x,
p1[1]+y));
if (i == step_sizes[0].size())
break;
x += step_sizes[0][i];
}
if (j == step_sizes[1].size())
break;
y += step_sizes[1][j];
}
break;
}
case 3:
{
double z=0;
for (unsigned int k=0; ; ++k)
{
double y=0;
for (unsigned int j=0; ; ++j)
{
double x=0;
for (unsigned int i=0; ; ++i)
{
points.push_back (Point<dim> (p1[0]+x,
p1[1]+y,
p1[2]+z));
if (i == step_sizes[0].size())
break;
x += step_sizes[0][i];
}
if (j == step_sizes[1].size())
break;
y += step_sizes[1][j];
}
if (k == step_sizes[2].size())
break;
z += step_sizes[2][k];
}
break;
}
default:
Assert (false, ExcNotImplemented());
}
// next create the cells
// Prepare cell data
std::vector<CellData<dim> > cells;
switch (dim)
{
case 1:
{
cells.resize (step_sizes[0].size());
for (unsigned int x=0; x<step_sizes[0].size(); ++x)
{
cells[x].vertices[0] = x;
cells[x].vertices[1] = x+1;
cells[x].material_id = 0;
}
break;
}
case 2:
{
cells.resize (step_sizes[1].size()*step_sizes[0].size());
for (unsigned int y=0; y<step_sizes[1].size(); ++y)
for (unsigned int x=0; x<step_sizes[0].size(); ++x)
{
const unsigned int c = x+y*step_sizes[0].size();
cells[c].vertices[0] = y*(step_sizes[0].size()+1)+x;
cells[c].vertices[1] = y*(step_sizes[0].size()+1)+x+1;
cells[c].vertices[2] = (y+1)*(step_sizes[0].size()+1)+x;
cells[c].vertices[3] = (y+1)*(step_sizes[0].size()+1)+x+1;
cells[c].material_id = 0;
}
break;
}
case 3:
{
const unsigned int n_x = (step_sizes[0].size()+1);
const unsigned int n_xy = (step_sizes[0].size()+1)*(step_sizes[1].size()+1);
cells.resize (step_sizes[2].size()*step_sizes[1].size()*step_sizes[0].size());
for (unsigned int z=0; z<step_sizes[2].size(); ++z)
for (unsigned int y=0; y<step_sizes[1].size(); ++y)
for (unsigned int x=0; x<step_sizes[0].size(); ++x)
{
const unsigned int c = x+y*step_sizes[0].size() +
z*step_sizes[0].size()*step_sizes[1].size();
cells[c].vertices[0] = z*n_xy + y*n_x + x;
cells[c].vertices[1] = z*n_xy + y*n_x + x+1;
cells[c].vertices[2] = z*n_xy + (y+1)*n_x + x;
cells[c].vertices[3] = z*n_xy + (y+1)*n_x + x+1;
cells[c].vertices[4] = (z+1)*n_xy + y*n_x + x;
cells[c].vertices[5] = (z+1)*n_xy + y*n_x + x+1;
cells[c].vertices[6] = (z+1)*n_xy + (y+1)*n_x + x;
cells[c].vertices[7] = (z+1)*n_xy + (y+1)*n_x + x+1;
cells[c].material_id = 0;
}
break;
}
default:
Assert (false, ExcNotImplemented());
}
tria.create_triangulation (points, cells, SubCellData());
if (colorize)
{
// to colorize, run through all
// faces of all cells and set
// boundary indicator to the
// correct value if it was 0.
// use a large epsilon to
// compare numbers to avoid
// roundoff problems.
double min_size = *std::min_element (step_sizes[0].begin(),
step_sizes[0].end());
for (unsigned int i=1; i<dim; ++i)
min_size = std::min (min_size,
*std::min_element (step_sizes[i].begin(),
step_sizes[i].end()));
const double epsilon = 0.01 * min_size;
// actual code is external since
// 1-D is different from 2/3D.
colorize_subdivided_hyper_rectangle (tria, p1, p2, epsilon);
}
}
template <>
void
subdivided_hyper_rectangle (
Triangulation<1> &tria,
const std::vector< std::vector<double> > &spacing,
const Point<1> &p,
const Table<1,types::material_id> &material_id,
const bool colorize)
{
Assert(spacing.size() == 1,
ExcInvalidRepetitionsDimension(1));
const unsigned int n_cells = material_id.size(0);
Assert(spacing[0].size() == n_cells,
ExcInvalidRepetitionsDimension(1));
double delta = std::numeric_limits<double>::max();
for (unsigned int i=0; i<n_cells; i++)
{
Assert (spacing[0][i] >= 0, ExcInvalidRepetitions(-1));
delta = std::min (delta, spacing[0][i]);
}
// generate the necessary points
std::vector<Point<1> > points;
double ax = p[0];
for (unsigned int x=0; x<=n_cells; ++x)
{
points.push_back (Point<1> (ax));
if (x<n_cells)
ax += spacing[0][x];
}
// create the cells
unsigned int n_val_cells = 0;
for (unsigned int i=0; i<n_cells; i++)
if (material_id[i]!=numbers::invalid_material_id) n_val_cells++;
std::vector<CellData<1> > cells(n_val_cells);
unsigned int id = 0;
for (unsigned int x=0; x<n_cells; ++x)
if (material_id[x] != numbers::invalid_material_id)
{
cells[id].vertices[0] = x;
cells[id].vertices[1] = x+1;
cells[id].material_id = material_id[x];
id++;
}
// create triangulation
SubCellData t;
GridTools::delete_unused_vertices (points, cells, t);
tria.create_triangulation (points, cells, t);
// set boundary indicator
if (colorize)
Assert (false, ExcNotImplemented());
}
template <>
void
subdivided_hyper_rectangle (
Triangulation<2> &tria,
const std::vector< std::vector<double> > &spacing,
const Point<2> &p,
const Table<2,types::material_id> &material_id,
const bool colorize)
{
Assert(spacing.size() == 2,
ExcInvalidRepetitionsDimension(2));
std::vector<unsigned int> repetitions(2);
unsigned int n_cells = 1;
double delta = std::numeric_limits<double>::max();
for (unsigned int i=0; i<2; i++)
{
repetitions[i] = spacing[i].size();
n_cells *= repetitions[i];
for (unsigned int j=0; j<repetitions[i]; j++)
{
Assert (spacing[i][j] >= 0, ExcInvalidRepetitions(-1));
delta = std::min (delta, spacing[i][j]);
}
Assert(material_id.size(i) == repetitions[i],
ExcInvalidRepetitionsDimension(i));
}
// generate the necessary points
std::vector<Point<2> > points;
double ay = p[1];
for (unsigned int y=0; y<=repetitions[1]; ++y)
{
double ax = p[0];
for (unsigned int x=0; x<=repetitions[0]; ++x)
{
points.push_back (Point<2> (ax,ay));
if (x<repetitions[0])
ax += spacing[0][x];
}
if (y<repetitions[1])
ay += spacing[1][y];
}
// create the cells
unsigned int n_val_cells = 0;
for (unsigned int i=0; i<material_id.size(0); i++)
for (unsigned int j=0; j<material_id.size(1); j++)
if (material_id[i][j] != numbers::invalid_material_id)
n_val_cells++;
std::vector<CellData<2> > cells(n_val_cells);
unsigned int id = 0;
for (unsigned int y=0; y<repetitions[1]; ++y)
for (unsigned int x=0; x<repetitions[0]; ++x)
if (material_id[x][y]!=numbers::invalid_material_id)
{
cells[id].vertices[0] = y*(repetitions[0]+1)+x;
cells[id].vertices[1] = y*(repetitions[0]+1)+x+1;
cells[id].vertices[2] = (y+1)*(repetitions[0]+1)+x;
cells[id].vertices[3] = (y+1)*(repetitions[0]+1)+x+1;
cells[id].material_id = material_id[x][y];
id++;
}
// create triangulation
SubCellData t;
GridTools::delete_unused_vertices (points, cells, t);
tria.create_triangulation (points, cells, t);
// set boundary indicator
if (colorize)
{
double eps = 0.01 * delta;
Triangulation<2>::cell_iterator cell = tria.begin(),
endc = tria.end();
for (; cell !=endc; ++cell)
{
Point<2> cell_center = cell->center();
for (unsigned int f=0; f<GeometryInfo<2>::faces_per_cell; ++f)
if (cell->face(f)->boundary_id() == 0)
{
Point<2> face_center = cell->face(f)->center();
for (unsigned int i=0; i<2; ++i)
{
if (face_center[i]<cell_center[i]-eps)
cell->face(f)->set_boundary_id(i*2);
if (face_center[i]>cell_center[i]+eps)
cell->face(f)->set_boundary_id(i*2+1);
}
}
}
}
}
template <>
void
subdivided_hyper_rectangle (
Triangulation<3> &tria,
const std::vector< std::vector<double> > &spacing,
const Point<3> &p,
const Table<3,types::material_id> &material_id,
const bool colorize)
{
const unsigned int dim = 3;
Assert(spacing.size() == dim,
ExcInvalidRepetitionsDimension(dim));
std::vector<unsigned int > repetitions(dim);
unsigned int n_cells = 1;
double delta = std::numeric_limits<double>::max();
for (unsigned int i=0; i<dim; i++)
{
repetitions[i] = spacing[i].size();
n_cells *= repetitions[i];
for (unsigned int j=0; j<repetitions[i]; j++)
{
Assert (spacing[i][j] >= 0, ExcInvalidRepetitions(-1));
delta = std::min (delta, spacing[i][j]);
}
Assert(material_id.size(i) == repetitions[i],
ExcInvalidRepetitionsDimension(i));
}
// generate the necessary points
std::vector<Point<dim> > points;
double az = p[2];
for (unsigned int z=0; z<=repetitions[2]; ++z)
{
double ay = p[1];
for (unsigned int y=0; y<=repetitions[1]; ++y)
{
double ax = p[0];
for (unsigned int x=0; x<=repetitions[0]; ++x)
{
points.push_back (Point<dim> (ax,ay,az));
if (x<repetitions[0])
ax += spacing[0][x];
}
if (y<repetitions[1])
ay += spacing[1][y];
}
if (z<repetitions[2])
az += spacing[2][z];
}
// create the cells
unsigned int n_val_cells = 0;
for (unsigned int i=0; i<material_id.size(0); i++)
for (unsigned int j=0; j<material_id.size(1); j++)
for (unsigned int k=0; k<material_id.size(2); k++)
if (material_id[i][j][k]!=numbers::invalid_material_id)
n_val_cells++;
std::vector<CellData<dim> > cells(n_val_cells);
unsigned int id = 0;
const unsigned int n_x = (repetitions[0]+1);
const unsigned int n_xy = (repetitions[0]+1)*(repetitions[1]+1);
for (unsigned int z=0; z<repetitions[2]; ++z)
for (unsigned int y=0; y<repetitions[1]; ++y)
for (unsigned int x=0; x<repetitions[0]; ++x)
if (material_id[x][y][z]!=numbers::invalid_material_id)
{
cells[id].vertices[0] = z*n_xy + y*n_x + x;
cells[id].vertices[1] = z*n_xy + y*n_x + x+1;
cells[id].vertices[2] = z*n_xy + (y+1)*n_x + x;
cells[id].vertices[3] = z*n_xy + (y+1)*n_x + x+1;
cells[id].vertices[4] = (z+1)*n_xy + y*n_x + x;
cells[id].vertices[5] = (z+1)*n_xy + y*n_x + x+1;
cells[id].vertices[6] = (z+1)*n_xy + (y+1)*n_x + x;
cells[id].vertices[7] = (z+1)*n_xy + (y+1)*n_x + x+1;
cells[id].material_id = material_id[x][y][z];
id++;
}
// create triangulation
SubCellData t;
GridTools::delete_unused_vertices (points, cells, t);
tria.create_triangulation (points, cells, t);
// set boundary indicator
if (colorize && dim>1)
{
double eps = 0.01 * delta;
Triangulation<dim>::cell_iterator cell = tria.begin(),
endc = tria.end();
for (; cell !=endc; ++cell)
{
Point<dim> cell_center = cell->center();
for (unsigned int f=0; f<GeometryInfo<dim>::faces_per_cell; ++f)
if (cell->face(f)->boundary_id() == 0)
{
Point<dim> face_center = cell->face(f)->center();
for (unsigned int i=0; i<dim; ++i)
{
if (face_center[i]<cell_center[i]-eps)
cell->face(f)->set_boundary_id(i*2);
if (face_center[i]>cell_center[i]+eps)
cell->face(f)->set_boundary_id(i*2+1);
}
}
}
}
}
template <int dim, int spacedim>
void
cheese (
Triangulation<dim, spacedim> &tria,
const std::vector<unsigned int> &holes)
{
AssertDimension(holes.size(), dim);
// The corner points of the first cell. If there is a desire at
// some point to change the geometry of the cells, they can be
// made an argument to the function.
Point<spacedim> p1;
Point<spacedim> p2;
for (unsigned int d=0; d<dim; ++d)
p2(d) = 1.;
// then check that all repetitions
// are >= 1, and calculate deltas
// convert repetitions from double
// to int by taking the ceiling.
std::vector<Point<spacedim> > delta(dim);
unsigned int repetitions[dim];
for (unsigned int i=0; i<dim; ++i)
{
Assert (holes[i] >= 1, ExcMessage("At least one hole needed in each direction"));
repetitions[i] = 2*holes[i]+1;
delta[i][i] = (p2[i]-p1[i]);
}
// then generate the necessary
// points
std::vector<Point<spacedim> > points;
switch (dim)
{
case 1:
for (unsigned int x=0; x<=repetitions[0]; ++x)
points.push_back (p1+(double)x*delta[0]);
break;
case 2:
for (unsigned int y=0; y<=repetitions[1]; ++y)
for (unsigned int x=0; x<=repetitions[0]; ++x)
points.push_back (p1+(double)x*delta[0]
+(double)y*delta[1]);
break;
case 3:
for (unsigned int z=0; z<=repetitions[2]; ++z)
for (unsigned int y=0; y<=repetitions[1]; ++y)
for (unsigned int x=0; x<=repetitions[0]; ++x)
points.push_back (p1+(double)x*delta[0] +
(double)y*delta[1] + (double)z*delta[2]);
break;
default:
Assert (false, ExcNotImplemented());
}
// next create the cells
// Prepare cell data
std::vector<CellData<dim> > cells;
switch (dim)
{
case 2:
{
cells.resize (repetitions[1]*repetitions[0]-holes[1]*holes[0]);
unsigned int c=0;
for (unsigned int y=0; y<repetitions[1]; ++y)
for (unsigned int x=0; x<repetitions[0]; ++x)
{
if ((x%2 == 1) && (y%2 ==1)) continue;
Assert(c<cells.size(), ExcInternalError());
cells[c].vertices[0] = y*(repetitions[0]+1)+x;
cells[c].vertices[1] = y*(repetitions[0]+1)+x+1;
cells[c].vertices[2] = (y+1)*(repetitions[0]+1)+x;
cells[c].vertices[3] = (y+1)*(repetitions[0]+1)+x+1;
cells[c].material_id = 0;
++c;
}
break;
}
case 3:
{
const unsigned int n_x = (repetitions[0]+1);
const unsigned int n_xy = (repetitions[0]+1)*(repetitions[1]+1);
cells.resize (repetitions[2]*repetitions[1]*repetitions[0]);
unsigned int c=0;
for (unsigned int z=0; z<repetitions[2]; ++z)
for (unsigned int y=0; y<repetitions[1]; ++y)
for (unsigned int x=0; x<repetitions[0]; ++x)
{
Assert(c<cells.size(),ExcInternalError());
cells[c].vertices[0] = z*n_xy + y*n_x + x;
cells[c].vertices[1] = z*n_xy + y*n_x + x+1;
cells[c].vertices[2] = z*n_xy + (y+1)*n_x + x;
cells[c].vertices[3] = z*n_xy + (y+1)*n_x + x+1;
cells[c].vertices[4] = (z+1)*n_xy + y*n_x + x;
cells[c].vertices[5] = (z+1)*n_xy + y*n_x + x+1;
cells[c].vertices[6] = (z+1)*n_xy + (y+1)*n_x + x;
cells[c].vertices[7] = (z+1)*n_xy + (y+1)*n_x + x+1;
cells[c].material_id = 0;
++c;
}
break;
}
default:
Assert (false, ExcNotImplemented());
}
tria.create_triangulation (points, cells, SubCellData());
}
template <int dim, int spacedim>
void hyper_cross(Triangulation<dim, spacedim> &tria,
const std::vector<unsigned int> &sizes,
const bool colorize)
{
AssertDimension(sizes.size(), GeometryInfo<dim>::faces_per_cell);
Assert(dim>1, ExcNotImplemented());
Assert(dim<4, ExcNotImplemented());
// If there is a desire at some point to change the geometry of
// the cells, this tensor can be made an argument to the function.
Tensor<1,dim> dimensions;
for (unsigned int d=0; d<dim; ++d)
dimensions[d] = 1.;
std::vector<Point<spacedim> > points;
unsigned int n_cells = 1;
for (unsigned int i=0; i<GeometryInfo<dim>::faces_per_cell; ++i)
n_cells += sizes[i];
std::vector<CellData<dim> > cells(n_cells);
// Vertices of the center cell
for (unsigned int i=0; i<GeometryInfo<dim>::vertices_per_cell; ++i)
{
Point<spacedim> p;
for (unsigned int d=0; d<dim; ++d)
p(d) = 0.5 * dimensions[d] *
GeometryInfo<dim>::unit_normal_orientation[GeometryInfo<dim>::vertex_to_face[i][d]];
points.push_back(p);
cells[0].vertices[i] = i;
}
cells[0].material_id = 0;
// The index of the first cell of the leg.
unsigned int cell_index = 1;
// The legs of the cross
for (unsigned int face=0; face<GeometryInfo<dim>::faces_per_cell; ++face)
{
const unsigned int oface = GeometryInfo<dim>::opposite_face[face];
const unsigned int dir = GeometryInfo<dim>::unit_normal_direction[face];
// We are moving in the direction of face
for (unsigned int j=0; j<sizes[face]; ++j,++cell_index)
{
const unsigned int last_cell = (j==0) ? 0U : (cell_index-1);
for (unsigned int v=0; v<GeometryInfo<dim>::vertices_per_face; ++v)
{
const unsigned int cellv = GeometryInfo<dim>::face_to_cell_vertices(face, v);
const unsigned int ocellv = GeometryInfo<dim>::face_to_cell_vertices(oface, v);
// First the vertices which already exist
cells[cell_index].vertices[ocellv] = cells[last_cell].vertices[cellv];
// Now the new vertices
cells[cell_index].vertices[cellv] = points.size();
Point<spacedim> p = points[cells[cell_index].vertices[ocellv]];
p(dir) += GeometryInfo<dim>::unit_normal_orientation[face] * dimensions[dir];
points.push_back(p);
}
cells[cell_index].material_id = (colorize) ? (face+1U) : 0U;
}
}
tria.create_triangulation (points, cells, SubCellData());
}
template <>
void hyper_cube_slit (Triangulation<1> &,
const double,
const double,
const bool)
{
Assert (false, ExcNotImplemented());
}
template <>
void enclosed_hyper_cube (Triangulation<1> &,
const double,
const double,
const double,
const bool)
{
Assert (false, ExcNotImplemented());
}
template <>
void hyper_L (Triangulation<1> &,
const double,
const double,
const bool)
{
Assert (false, ExcNotImplemented());
}
template <>
void hyper_ball (Triangulation<1> &,
const Point<1> &,
const double)
{
Assert (false, ExcNotImplemented());
}
template <>
void cylinder (Triangulation<1> &,
const double,
const double)
{
Assert (false, ExcNotImplemented());
}
template <>
void truncated_cone (Triangulation<1> &,
const double,
const double,
const double)
{
Assert (false, ExcNotImplemented());
}
template <>
void hyper_shell (Triangulation<1> &,
const Point<1> &,
const double,
const double,
const unsigned int ,
const bool)
{
Assert (false, ExcNotImplemented());
}
template <>
void cylinder_shell (Triangulation<1> &,
const double,
const double,
const double,
const unsigned int ,
const unsigned int )
{
Assert (false, ExcNotImplemented());
}
template <>
void
quarter_hyper_ball (Triangulation<1> &,
const Point<1> &,
const double)
{
Assert (false, ExcNotImplemented());
}
template <>
void
half_hyper_ball (Triangulation<1> &,
const Point<1> &,
const double)
{
Assert (false, ExcNotImplemented());
}
template <>
void
half_hyper_shell (Triangulation<1> &,
const Point<1> &,
const double,
const double,
const unsigned int ,
const bool)
{
Assert (false, ExcNotImplemented());
}
template <>
void quarter_hyper_shell (Triangulation<1> &,
const Point<1> &,
const double,
const double,
const unsigned int ,
const bool)
{
Assert (false, ExcNotImplemented());
}
template <>
void enclosed_hyper_cube (Triangulation<2> &tria,
const double left,
const double right,
const double thickness,
const bool colorize)
{
Assert(left<right,
ExcMessage ("Invalid left-to-right bounds of enclosed hypercube"));
std::vector<Point<2> > vertices(16);
double coords[4];
coords[0] = left-thickness;
coords[1] = left;
coords[2] = right;
coords[3] = right+thickness;
unsigned int k=0;
for (unsigned int i0=0; i0<4; ++i0)
for (unsigned int i1=0; i1<4; ++i1)
vertices[k++] = Point<2>(coords[i1], coords[i0]);
const types::material_id materials[9] = { 5, 4, 6,
1, 0, 2,
9, 8,10
};
std::vector<CellData<2> > cells(9);
k = 0;
for (unsigned int i0=0; i0<3; ++i0)
for (unsigned int i1=0; i1<3; ++i1)
{
cells[k].vertices[0] = i1+4*i0;
cells[k].vertices[1] = i1+4*i0+1;
cells[k].vertices[2] = i1+4*i0+4;
cells[k].vertices[3] = i1+4*i0+5;
if (colorize)
cells[k].material_id = materials[k];
++k;
}
tria.create_triangulation (vertices,
cells,
SubCellData()); // no boundary information
}
// Implementation for 2D only
template <>
void
hyper_cube_slit (Triangulation<2> &tria,
const double left,
const double right,
const bool colorize)
{
const double rl2=(right+left)/2;
const Point<2> vertices[10] = { Point<2>(left, left ),
Point<2>(rl2, left ),
Point<2>(rl2, rl2 ),
Point<2>(left, rl2 ),
Point<2>(right,left ),
Point<2>(right,rl2 ),
Point<2>(rl2, right),
Point<2>(left, right),
Point<2>(right,right),
Point<2>(rl2, left )
};
const int cell_vertices[4][4] = { { 0,1,3,2 },
{ 9,4,2,5 },
{ 3,2,7,6 },
{ 2,5,6,8 }
};
std::vector<CellData<2> > cells (4, CellData<2>());
for (unsigned int i=0; i<4; ++i)
{
for (unsigned int j=0; j<4; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<2> >(&vertices[0], &vertices[10]),
cells,
SubCellData()); // no boundary information
if (colorize)
{
Triangulation<2>::cell_iterator cell = tria.begin();
cell->face(1)->set_boundary_id(1);
++cell;
cell->face(0)->set_boundary_id(2);
}
}
template <>
void truncated_cone (Triangulation<2> &triangulation,
const double radius_0,
const double radius_1,
const double half_length)
{
Point<2> vertices_tmp[4];
vertices_tmp[0] = Point<2> (-half_length, -radius_0);
vertices_tmp[1] = Point<2> (half_length, -radius_1);
vertices_tmp[2] = Point<2> (-half_length, radius_0);
vertices_tmp[3] = Point<2> (half_length, radius_1);
const std::vector<Point<2> > vertices (&vertices_tmp[0], &vertices_tmp[4]);
unsigned int cell_vertices[1][GeometryInfo<2>::vertices_per_cell];
for (unsigned int i = 0; i < GeometryInfo<2>::vertices_per_cell; ++i)
cell_vertices[0][i] = i;
std::vector<CellData<2> > cells (1, CellData<2> ());
for (unsigned int i = 0; i < GeometryInfo<2>::vertices_per_cell; ++i)
cells[0].vertices[i] = cell_vertices[0][i];
cells[0].material_id = 0;
triangulation.create_triangulation (vertices, cells, SubCellData ());
Triangulation<2>::cell_iterator cell = triangulation.begin ();
cell->face (0)->set_boundary_id (1);
cell->face (1)->set_boundary_id (2);
for (unsigned int i = 2; i < 4; ++i)
cell->face (i)->set_boundary_id (0);
}
// Implementation for 2D only
template <>
void
hyper_L (Triangulation<2> &tria,
const double a,
const double b,
const bool colorize)
{
const Point<2> vertices[8] = { Point<2> (a,a),
Point<2> ((a+b)/2,a),
Point<2> (b,a),
Point<2> (a,(a+b)/2),
Point<2> ((a+b)/2,(a+b)/2),
Point<2> (b,(a+b)/2),
Point<2> (a,b),
Point<2> ((a+b)/2,b)
};
const int cell_vertices[3][4] = {{0, 1, 3, 4},
{1, 2, 4, 5},
{3, 4, 6, 7}
};
std::vector<CellData<2> > cells (3, CellData<2>());
for (unsigned int i=0; i<3; ++i)
{
for (unsigned int j=0; j<4; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<2> >(&vertices[0], &vertices[8]),
cells,
SubCellData());
if (colorize)
{
Triangulation<2>::cell_iterator cell = tria.begin();
cell->face(0)->set_boundary_id(0);
cell->face(2)->set_boundary_id(1);
cell++;
cell->face(1)->set_boundary_id(2);
cell->face(2)->set_boundary_id(1);
cell->face(3)->set_boundary_id(3);
cell++;
cell->face(0)->set_boundary_id(0);
cell->face(1)->set_boundary_id(4);
cell->face(3)->set_boundary_id(5);
}
}
// Implementation for 2D only
template <>
void
hyper_ball (Triangulation<2> &tria,
const Point<2> &p,
const double radius)
{
// equilibrate cell sizes at
// transition from the inner part
// to the radial cells
const double a = 1./(1+std::sqrt(2.0));
const Point<2> vertices[8] = { p+Point<2>(-1,-1) *(radius/std::sqrt(2.0)),
p+Point<2>(+1,-1) *(radius/std::sqrt(2.0)),
p+Point<2>(-1,-1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(+1,-1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(-1,+1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(+1,+1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(-1,+1) *(radius/std::sqrt(2.0)),
p+Point<2>(+1,+1) *(radius/std::sqrt(2.0))
};
const int cell_vertices[5][4] = {{0, 1, 2, 3},
{0, 2, 6, 4},
{2, 3, 4, 5},
{1, 7, 3, 5},
{6, 4, 7, 5}
};
std::vector<CellData<2> > cells (5, CellData<2>());
for (unsigned int i=0; i<5; ++i)
{
for (unsigned int j=0; j<4; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<2> >(&vertices[0], &vertices[8]),
cells,
SubCellData()); // no boundary information
}
template <>
void hyper_shell (Triangulation<2> &tria,
const Point<2> ¢er,
const double inner_radius,
const double outer_radius,
const unsigned int n_cells,
const bool colorize)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
const double pi = numbers::PI;
// determine the number of cells
// for the grid. if not provided by
// the user determine it such that
// the length of each cell on the
// median (in the middle between
// the two circles) is equal to its
// radial extent (which is the
// difference between the two
// radii)
const unsigned int N = (n_cells == 0 ?
static_cast<unsigned int>
(std::ceil((2*pi* (outer_radius + inner_radius)/2) /
(outer_radius - inner_radius))) :
n_cells);
// set up N vertices on the
// outer and N vertices on
// the inner circle. the
// first N ones are on the
// outer one, and all are
// numbered counter-clockwise
std::vector<Point<2> > vertices(2*N);
for (unsigned int i=0; i<N; ++i)
{
vertices[i] = Point<2>( std::cos(2*pi * i/N),
std::sin(2*pi * i/N)) * outer_radius;
vertices[i+N] = vertices[i] * (inner_radius/outer_radius);
vertices[i] += center;
vertices[i+N] += center;
};
std::vector<CellData<2> > cells (N, CellData<2>());
for (unsigned int i=0; i<N; ++i)
{
cells[i].vertices[0] = i;
cells[i].vertices[1] = (i+1)%N;
cells[i].vertices[2] = N+i;
cells[i].vertices[3] = N+((i+1)%N);
cells[i].material_id = 0;
};
tria.create_triangulation (
vertices, cells, SubCellData());
if (colorize)
colorize_hyper_shell(tria, center, inner_radius, outer_radius);
}
// Implementation for 2D only
template <>
void
cylinder (Triangulation<2> &tria,
const double radius,
const double half_length)
{
Point<2> p1 (-half_length, -radius);
Point<2> p2 (half_length, radius);
hyper_rectangle(tria, p1, p2, true);
Triangulation<2>::face_iterator f = tria.begin_face();
Triangulation<2>::face_iterator end = tria.end_face();
while (f != end)
{
switch (f->boundary_id())
{
case 0:
f->set_boundary_id(1);
break;
case 1:
f->set_boundary_id(2);
break;
default:
f->set_boundary_id(0);
break;
}
++f;
}
}
// Implementation for 2D only
template <>
void cylinder_shell (Triangulation<2> &,
const double,
const double,
const double,
const unsigned int,
const unsigned int)
{
Assert (false, ExcNotImplemented());
}
template <>
void
quarter_hyper_ball (Triangulation<2> &tria,
const Point<2> &p,
const double radius)
{
const unsigned int dim = 2;
// equilibrate cell sizes at
// transition from the inner part
// to the radial cells
const Point<dim> vertices[7]
= { p+Point<dim>(0,0) *radius,
p+Point<dim>(+1,0) *radius,
p+Point<dim>(+1,0) *(radius/2),
p+Point<dim>(0,+1) *(radius/2),
p+Point<dim>(+1,+1) *(radius/(2*sqrt(2.0))),
p+Point<dim>(0,+1) *radius,
p+Point<dim>(+1,+1) *(radius/std::sqrt(2.0))
};
const int cell_vertices[3][4]
= {{0, 2, 3, 4},
{1, 6, 2, 4},
{5, 3, 6, 4}
};
std::vector<CellData<dim> > cells (3, CellData<dim>());
for (unsigned int i=0; i<3; ++i)
{
for (unsigned int j=0; j<4; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<dim> >(&vertices[0], &vertices[7]),
cells,
SubCellData()); // no boundary information
Triangulation<dim>::cell_iterator cell = tria.begin();
Triangulation<dim>::cell_iterator end = tria.end();
while (cell != end)
{
for (unsigned int i=0; i<GeometryInfo<dim>::faces_per_cell; ++i)
{
if (cell->face(i)->boundary_id() == numbers::internal_face_boundary_id)
continue;
// If one the components is the same as the respective
// component of the center, then this is part of the plane
if (cell->face(i)->center()(0) < p(0)+1.e-5 * radius
|| cell->face(i)->center()(1) < p(1)+1.e-5 * radius)
cell->face(i)->set_boundary_id(1);
}
++cell;
}
}
template <>
void
half_hyper_ball (Triangulation<2> &tria,
const Point<2> &p,
const double radius)
{
// equilibrate cell sizes at
// transition from the inner part
// to the radial cells
const double a = 1./(1+std::sqrt(2.0));
const Point<2> vertices[8] = { p+Point<2>(0,-1) *radius,
p+Point<2>(+1,-1) *(radius/std::sqrt(2.0)),
p+Point<2>(0,-1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(+1,-1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(0,+1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(+1,+1) *(radius/std::sqrt(2.0)*a),
p+Point<2>(0,+1) *radius,
p+Point<2>(+1,+1) *(radius/std::sqrt(2.0))
};
const int cell_vertices[5][4] = {{0, 1, 2, 3},
{2, 3, 4, 5},
{1, 7, 3, 5},
{6, 4, 7, 5}
};
std::vector<CellData<2> > cells (4, CellData<2>());
for (unsigned int i=0; i<4; ++i)
{
for (unsigned int j=0; j<4; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<2> >(&vertices[0], &vertices[8]),
cells,
SubCellData()); // no boundary information
Triangulation<2>::cell_iterator cell = tria.begin();
Triangulation<2>::cell_iterator end = tria.end();
while (cell != end)
{
for (unsigned int i=0; i<GeometryInfo<2>::faces_per_cell; ++i)
{
if (cell->face(i)->boundary_id() == numbers::internal_face_boundary_id)
continue;
// If x is zero, then this is part of the plane
if (cell->face(i)->center()(0) < p(0)+1.e-5 * radius)
cell->face(i)->set_boundary_id(1);
}
++cell;
}
}
// Implementation for 2D only
template <>
void
half_hyper_shell (Triangulation<2> &tria,
const Point<2> ¢er,
const double inner_radius,
const double outer_radius,
const unsigned int n_cells,
const bool colorize)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
const double pi = numbers::PI;
// determine the number of cells
// for the grid. if not provided by
// the user determine it such that
// the length of each cell on the
// median (in the middle between
// the two circles) is equal to its
// radial extent (which is the
// difference between the two
// radii)
const unsigned int N = (n_cells == 0 ?
static_cast<unsigned int>
(std::ceil((pi* (outer_radius + inner_radius)/2) /
(outer_radius - inner_radius))) :
n_cells);
// set up N+1 vertices on the
// outer and N+1 vertices on
// the inner circle. the
// first N+1 ones are on the
// outer one, and all are
// numbered counter-clockwise
std::vector<Point<2> > vertices(2*(N+1));
for (unsigned int i=0; i<=N; ++i)
{
// enforce that the x-coordinates
// of the first and last point of
// each half-circle are exactly
// zero (contrary to what we may
// compute using the imprecise
// value of pi)
vertices[i] = Point<2>( ( (i==0) || (i==N) ?
0 :
std::cos(pi * i/N - pi/2) ),
std::sin(pi * i/N - pi/2)) * outer_radius;
vertices[i+N+1] = vertices[i] * (inner_radius/outer_radius);
vertices[i] += center;
vertices[i+N+1] += center;
};
std::vector<CellData<2> > cells (N, CellData<2>());
for (unsigned int i=0; i<N; ++i)
{
cells[i].vertices[0] = i;
cells[i].vertices[1] = (i+1)%(N+1);
cells[i].vertices[2] = N+1+i;
cells[i].vertices[3] = N+1+((i+1)%(N+1));
cells[i].material_id = 0;
};
tria.create_triangulation (vertices, cells, SubCellData());
if (colorize)
{
Triangulation<2>::cell_iterator cell = tria.begin();
for (; cell!=tria.end(); ++cell)
{
cell->face(2)->set_boundary_id(1);
}
tria.begin()->face(0)->set_boundary_id(3);
tria.last()->face(1)->set_boundary_id(2);
}
}
template <>
void quarter_hyper_shell (Triangulation<2> &tria,
const Point<2> ¢er,
const double inner_radius,
const double outer_radius,
const unsigned int n_cells,
const bool colorize)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
const double pi = numbers::PI;
// determine the number of cells
// for the grid. if not provided by
// the user determine it such that
// the length of each cell on the
// median (in the middle between
// the two circles) is equal to its
// radial extent (which is the
// difference between the two
// radii)
const unsigned int N = (n_cells == 0 ?
static_cast<unsigned int>
(std::ceil((pi* (outer_radius + inner_radius)/4) /
(outer_radius - inner_radius))) :
n_cells);
// set up N+1 vertices on the
// outer and N+1 vertices on
// the inner circle. the
// first N+1 ones are on the
// outer one, and all are
// numbered counter-clockwise
std::vector<Point<2> > vertices(2*(N+1));
for (unsigned int i=0; i<=N; ++i)
{
// enforce that the x-coordinates
// of the last point is exactly
// zero (contrary to what we may
// compute using the imprecise
// value of pi)
vertices[i] = Point<2>( ( (i==N) ?
0 :
std::cos(pi * i/N/2) ),
std::sin(pi * i/N/2)) * outer_radius;
vertices[i+N+1] = vertices[i] * (inner_radius/outer_radius);
vertices[i] += center;
vertices[i+N+1] += center;
};
std::vector<CellData<2> > cells (N, CellData<2>());
for (unsigned int i=0; i<N; ++i)
{
cells[i].vertices[0] = i;
cells[i].vertices[1] = (i+1)%(N+1);
cells[i].vertices[2] = N+1+i;
cells[i].vertices[3] = N+1+((i+1)%(N+1));
cells[i].material_id = 0;
};
tria.create_triangulation (vertices, cells, SubCellData());
if (colorize)
{
Triangulation<2>::cell_iterator cell = tria.begin();
for (; cell!=tria.end(); ++cell)
{
cell->face(2)->set_boundary_id(1);
}
tria.begin()->face(0)->set_boundary_id(3);
tria.last()->face(1)->set_boundary_id(2);
}
}
// Implementation for 3D only
template <>
void hyper_cube_slit (Triangulation<3> &tria,
const double left,
const double right,
const bool colorize)
{
const double rl2=(right+left)/2;
const double len = (right-left)/2.;
const Point<3> vertices[20] =
{
Point<3>(left, left , -len/2.),
Point<3>(rl2, left , -len/2.),
Point<3>(rl2, rl2 , -len/2.),
Point<3>(left, rl2 , -len/2.),
Point<3>(right,left , -len/2.),
Point<3>(right,rl2 , -len/2.),
Point<3>(rl2, right, -len/2.),
Point<3>(left, right, -len/2.),
Point<3>(right,right, -len/2.),
Point<3>(rl2, left , -len/2.),
Point<3>(left, left , len/2.),
Point<3>(rl2, left , len/2.),
Point<3>(rl2, rl2 , len/2.),
Point<3>(left, rl2 , len/2.),
Point<3>(right,left , len/2.),
Point<3>(right,rl2 , len/2.),
Point<3>(rl2, right, len/2.),
Point<3>(left, right, len/2.),
Point<3>(right,right, len/2.),
Point<3>(rl2, left , len/2.)
};
const int cell_vertices[4][8] = { { 0,1,3,2, 10, 11, 13, 12 },
{ 9,4,2,5, 19,14, 12, 15 },
{ 3,2,7,6,13,12,17,16 },
{ 2,5,6,8,12,15,16,18 }
};
std::vector<CellData<3> > cells (4, CellData<3>());
for (unsigned int i=0; i<4; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<3> >(&vertices[0], &vertices[20]),
cells,
SubCellData()); // no boundary information
if (colorize)
{
Triangulation<3>::cell_iterator cell = tria.begin();
cell->face(1)->set_boundary_id(1);
++cell;
cell->face(0)->set_boundary_id(2);
}
}
// Implementation for 3D only
template <>
void enclosed_hyper_cube (Triangulation<3> &tria,
const double left,
const double right,
const double thickness,
const bool colorize)
{
Assert(left<right,
ExcMessage ("Invalid left-to-right bounds of enclosed hypercube"));
std::vector<Point<3> > vertices(64);
double coords[4];
coords[0] = left-thickness;
coords[1] = left;
coords[2] = right;
coords[3] = right+thickness;
unsigned int k=0;
for (unsigned int z=0; z<4; ++z)
for (unsigned int y=0; y<4; ++y)
for (unsigned int x=0; x<4; ++x)
vertices[k++] = Point<3>(coords[x], coords[y], coords[z]);
const types::material_id materials[27] =
{
21,20,22,
17,16,18,
25,24,26,
5 , 4, 6,
1 , 0, 2,
9 , 8,10,
37,36,38,
33,32,34,
41,40,42
};
std::vector<CellData<3> > cells(27);
k = 0;
for (unsigned int z=0; z<3; ++z)
for (unsigned int y=0; y<3; ++y)
for (unsigned int x=0; x<3; ++x)
{
cells[k].vertices[0] = x+4*y+16*z;
cells[k].vertices[1] = x+4*y+16*z+1;
cells[k].vertices[2] = x+4*y+16*z+4;
cells[k].vertices[3] = x+4*y+16*z+5;
cells[k].vertices[4] = x+4*y+16*z+16;
cells[k].vertices[5] = x+4*y+16*z+17;
cells[k].vertices[6] = x+4*y+16*z+20;
cells[k].vertices[7] = x+4*y+16*z+21;
if (colorize)
cells[k].material_id = materials[k];
++k;
}
tria.create_triangulation (
vertices,
cells,
SubCellData()); // no boundary information
}
template <>
void truncated_cone (Triangulation<3> &triangulation,
const double radius_0,
const double radius_1,
const double half_length)
{
// Determine number of cells and vertices
const unsigned int
n_cells = static_cast<unsigned int>(std::ceil (half_length /
std::max (radius_0,
radius_1)));
const unsigned int n_vertices = 4 * (n_cells + 1);
std::vector<Point<3> > vertices_tmp(n_vertices);
vertices_tmp[0] = Point<3> (-half_length, 0, -radius_0);
vertices_tmp[1] = Point<3> (-half_length, radius_0, 0);
vertices_tmp[2] = Point<3> (-half_length, -radius_0, 0);
vertices_tmp[3] = Point<3> (-half_length, 0, radius_0);
const double dx = 2 * half_length / n_cells;
for (unsigned int i = 0; i < n_cells; ++i)
{
vertices_tmp[4 * (i + 1)]
= vertices_tmp[4 * i] +
Point<3> (dx, 0, 0.5 * (radius_0 - radius_1) * dx / half_length);
vertices_tmp[4 * i + 5]
= vertices_tmp[4 * i + 1] +
Point<3> (dx, 0.5 * (radius_1 - radius_0) * dx / half_length, 0);
vertices_tmp[4 * i + 6]
= vertices_tmp[4 * i + 2] +
Point<3> (dx, 0.5 * (radius_0 - radius_1) * dx / half_length, 0);
vertices_tmp[4 * i + 7]
= vertices_tmp[4 * i + 3] +
Point<3> (dx, 0, 0.5 * (radius_1 - radius_0) * dx / half_length);
}
const std::vector<Point<3> > vertices (vertices_tmp.begin(),
vertices_tmp.end());
Table<2,unsigned int> cell_vertices(n_cells,GeometryInfo<3>::vertices_per_cell);
for (unsigned int i = 0; i < n_cells; ++i)
for (unsigned int j = 0; j < GeometryInfo<3>::vertices_per_cell; ++j)
cell_vertices[i][j] = 4 * i + j;
std::vector<CellData<3> > cells (n_cells, CellData<3> ());
for (unsigned int i = 0; i < n_cells; ++i)
{
for (unsigned int j = 0; j < GeometryInfo<3>::vertices_per_cell; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
}
triangulation.create_triangulation (vertices, cells, SubCellData ());
for (Triangulation<3>::cell_iterator cell = triangulation.begin ();
cell != triangulation.end (); ++cell)
{
if (cell->vertex (0) (0) == -half_length)
{
cell->face (4)->set_boundary_id (1);
for (unsigned int i = 0; i < 4; ++i)
cell->line (i)->set_boundary_id (0);
}
if (cell->vertex (4) (0) == half_length)
{
cell->face (5)->set_boundary_id (2);
for (unsigned int i = 4; i < 8; ++i)
cell->line (i)->set_boundary_id (0);
}
for (unsigned int i = 0; i < 4; ++i)
cell->face (i)->set_boundary_id (0);
}
}
// Implementation for 3D only
template <>
void
hyper_L (Triangulation<3> &tria,
const double a,
const double b,
const bool colorize)
{
// we slice out the top back right
// part of the cube
const Point<3> vertices[26]
=
{
// front face of the big cube
Point<3> (a, a,a),
Point<3> ((a+b)/2,a,a),
Point<3> (b, a,a),
Point<3> (a, a,(a+b)/2),
Point<3> ((a+b)/2,a,(a+b)/2),
Point<3> (b, a,(a+b)/2),
Point<3> (a, a,b),
Point<3> ((a+b)/2,a,b),
Point<3> (b, a,b),
// middle face of the big cube
Point<3> (a, (a+b)/2,a),
Point<3> ((a+b)/2,(a+b)/2,a),
Point<3> (b, (a+b)/2,a),
Point<3> (a, (a+b)/2,(a+b)/2),
Point<3> ((a+b)/2,(a+b)/2,(a+b)/2),
Point<3> (b, (a+b)/2,(a+b)/2),
Point<3> (a, (a+b)/2,b),
Point<3> ((a+b)/2,(a+b)/2,b),
Point<3> (b, (a+b)/2,b),
// back face of the big cube
// last (top right) point is missing
Point<3> (a, b,a),
Point<3> ((a+b)/2,b,a),
Point<3> (b, b,a),
Point<3> (a, b,(a+b)/2),
Point<3> ((a+b)/2,b,(a+b)/2),
Point<3> (b, b,(a+b)/2),
Point<3> (a, b,b),
Point<3> ((a+b)/2,b,b)
};
const int cell_vertices[7][8] = {{0, 1, 9, 10, 3, 4, 12, 13},
{1, 2, 10, 11, 4, 5, 13, 14},
{3, 4, 12, 13, 6, 7, 15, 16},
{4, 5, 13, 14, 7, 8, 16, 17},
{9, 10, 18, 19, 12, 13, 21, 22},
{10, 11, 19, 20, 13, 14, 22, 23},
{12, 13, 21, 22, 15, 16, 24, 25}
};
std::vector<CellData<3> > cells (7, CellData<3>());
for (unsigned int i=0; i<7; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<3> >(&vertices[0], &vertices[26]),
cells,
SubCellData()); // no boundary information
if (colorize)
{
Assert (false, ExcNotImplemented());
}
}
// Implementation for 3D only
template <>
void
hyper_ball (Triangulation<3> &tria,
const Point<3> &p,
const double radius)
{
const double a = 1./(1+std::sqrt(3.0)); // equilibrate cell sizes at transition
// from the inner part to the radial
// cells
const unsigned int n_vertices = 16;
const Point<3> vertices[n_vertices]
=
{
// first the vertices of the inner
// cell
p+Point<3>(-1,-1,-1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(+1,-1,-1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(+1,-1,+1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(-1,-1,+1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(-1,+1,-1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(+1,+1,-1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(+1,+1,+1) *(radius/std::sqrt(3.0)*a),
p+Point<3>(-1,+1,+1) *(radius/std::sqrt(3.0)*a),
// now the eight vertices at
// the outer sphere
p+Point<3>(-1,-1,-1) *(radius/std::sqrt(3.0)),
p+Point<3>(+1,-1,-1) *(radius/std::sqrt(3.0)),
p+Point<3>(+1,-1,+1) *(radius/std::sqrt(3.0)),
p+Point<3>(-1,-1,+1) *(radius/std::sqrt(3.0)),
p+Point<3>(-1,+1,-1) *(radius/std::sqrt(3.0)),
p+Point<3>(+1,+1,-1) *(radius/std::sqrt(3.0)),
p+Point<3>(+1,+1,+1) *(radius/std::sqrt(3.0)),
p+Point<3>(-1,+1,+1) *(radius/std::sqrt(3.0)),
};
// one needs to draw the seven cubes to
// understand what's going on here
const unsigned int n_cells = 7;
const int cell_vertices[n_cells][8] = {{0, 1, 4, 5, 3, 2, 7, 6}, // center
{8, 9, 12, 13, 0, 1, 4, 5}, // bottom
{9, 13, 1, 5, 10, 14, 2, 6}, // right
{11, 10, 3, 2, 15, 14, 7, 6}, // top
{8, 0, 12, 4, 11, 3, 15, 7}, // left
{8, 9, 0, 1, 11, 10, 3, 2}, // front
{12, 4, 13, 5, 15, 7, 14, 6}
}; // back
std::vector<CellData<3> > cells (n_cells, CellData<3>());
for (unsigned int i=0; i<n_cells; ++i)
{
for (unsigned int j=0; j<GeometryInfo<3>::vertices_per_cell; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<3> >(&vertices[0], &vertices[n_vertices]),
cells,
SubCellData()); // no boundary information
}
template <int dim, int spacedim>
void
hyper_sphere (Triangulation<dim,spacedim> &tria,
const Point<spacedim> &p,
const double radius)
{
Triangulation<spacedim> volume_mesh;
GridGenerator::hyper_ball(volume_mesh,p,radius);
std::set<types::boundary_id> boundary_ids;
boundary_ids.insert (0);
GridGenerator::extract_boundary_mesh (volume_mesh, tria,
boundary_ids);
}
// Implementation for 3D only
template <>
void
cylinder (Triangulation<3> &tria,
const double radius,
const double half_length)
{
// Copy the base from hyper_ball<3>
// and transform it to yz
const double d = radius/std::sqrt(2.0);
const double a = d/(1+std::sqrt(2.0));
Point<3> vertices[24] =
{
Point<3>(-d, -half_length,-d),
Point<3>( d, -half_length,-d),
Point<3>(-a, -half_length,-a),
Point<3>( a, -half_length,-a),
Point<3>(-a, -half_length, a),
Point<3>( a, -half_length, a),
Point<3>(-d, -half_length, d),
Point<3>( d, -half_length, d),
Point<3>(-d, 0,-d),
Point<3>( d, 0,-d),
Point<3>(-a, 0,-a),
Point<3>( a, 0,-a),
Point<3>(-a, 0, a),
Point<3>( a, 0, a),
Point<3>(-d, 0, d),
Point<3>( d, 0, d),
Point<3>(-d, half_length,-d),
Point<3>( d, half_length,-d),
Point<3>(-a, half_length,-a),
Point<3>( a, half_length,-a),
Point<3>(-a, half_length, a),
Point<3>( a, half_length, a),
Point<3>(-d, half_length, d),
Point<3>( d, half_length, d),
};
// Turn cylinder such that y->x
for (unsigned int i=0; i<24; ++i)
{
const double h = vertices[i](1);
vertices[i](1) = -vertices[i](0);
vertices[i](0) = h;
}
int cell_vertices[10][8] =
{
{0, 1, 8, 9, 2, 3, 10, 11},
{0, 2, 8, 10, 6, 4, 14, 12},
{2, 3, 10, 11, 4, 5, 12, 13},
{1, 7, 9, 15, 3, 5, 11, 13},
{6, 4, 14, 12, 7, 5, 15, 13}
};
for (unsigned int i=0; i<5; ++i)
for (unsigned int j=0; j<8; ++j)
cell_vertices[i+5][j] = cell_vertices[i][j]+8;
std::vector<CellData<3> > cells (10, CellData<3>());
for (unsigned int i=0; i<10; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<3> >(&vertices[0], &vertices[24]),
cells,
SubCellData()); // no boundary information
// set boundary indicators for the
// faces at the ends to 1 and 2,
// respectively. note that we also
// have to deal with those lines
// that are purely in the interior
// of the ends. we determine whether
// an edge is purely in the
// interior if one of its vertices
// is at coordinates '+-a' as set
// above
Triangulation<3>::cell_iterator cell = tria.begin();
Triangulation<3>::cell_iterator end = tria.end();
for (; cell != end; ++cell)
for (unsigned int i=0; i<GeometryInfo<3>::faces_per_cell; ++i)
if (cell->at_boundary(i))
{
if (cell->face(i)->center()(0) > half_length-1.e-5)
{
cell->face(i)->set_boundary_id(2);
for (unsigned int e=0; e<GeometryInfo<3>::lines_per_face; ++e)
if ((std::fabs(cell->face(i)->line(e)->vertex(0)[1]) == a) ||
(std::fabs(cell->face(i)->line(e)->vertex(0)[2]) == a) ||
(std::fabs(cell->face(i)->line(e)->vertex(1)[1]) == a) ||
(std::fabs(cell->face(i)->line(e)->vertex(1)[2]) == a))
cell->face(i)->line(e)->set_boundary_id(2);
}
else if (cell->face(i)->center()(0) < -half_length+1.e-5)
{
cell->face(i)->set_boundary_id(1);
for (unsigned int e=0; e<GeometryInfo<3>::lines_per_face; ++e)
if ((std::fabs(cell->face(i)->line(e)->vertex(0)[1]) == a) ||
(std::fabs(cell->face(i)->line(e)->vertex(0)[2]) == a) ||
(std::fabs(cell->face(i)->line(e)->vertex(1)[1]) == a) ||
(std::fabs(cell->face(i)->line(e)->vertex(1)[2]) == a))
cell->face(i)->line(e)->set_boundary_id(1);
}
}
}
template <>
void
quarter_hyper_ball (Triangulation<3> &tria,
const Point<3> ¢er,
const double radius)
{
const unsigned int dim = 3;
// equilibrate cell sizes at
// transition from the inner part
// to the radial cells
const Point<dim> vertices[15]
= { center+Point<dim>(0,0,0) *radius,
center+Point<dim>(+1,0,0) *radius,
center+Point<dim>(+1,0,0) *(radius/2.),
center+Point<dim>(0,+1,0) *(radius/2.),
center+Point<dim>(+1,+1,0) *(radius/(2*sqrt(2.0))),
center+Point<dim>(0,+1,0) *radius,
center+Point<dim>(+1,+1,0) *(radius/std::sqrt(2.0)),
center+Point<dim>(0,0,1) *radius/2.,
center+Point<dim>(+1,0,1) *radius/std::sqrt(2.0),
center+Point<dim>(+1,0,1) *(radius/(2*std::sqrt(2.0))),
center+Point<dim>(0,+1,1) *(radius/(2*std::sqrt(2.0))),
center+Point<dim>(+1,+1,1) *(radius/(2*std::sqrt(3.0))),
center+Point<dim>(0,+1,1) *radius/std::sqrt(2.0),
center+Point<dim>(+1,+1,1) *(radius/(std::sqrt(3.0))),
center+Point<dim>(0,0,1) *radius
};
const int cell_vertices[4][8]
= {{0, 2, 3, 4, 7, 9, 10, 11},
{1, 6, 2, 4, 8, 13, 9, 11},
{5, 3, 6, 4, 12, 10, 13, 11},
{7,9,10,11,14,8,12,13}
};
std::vector<CellData<dim> > cells (4, CellData<dim>());
for (unsigned int i=0; i<4; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<dim> >(&vertices[0], &vertices[15]),
cells,
SubCellData()); // no boundary information
Triangulation<dim>::cell_iterator cell = tria.begin();
Triangulation<dim>::cell_iterator end = tria.end();
while (cell != end)
{
for (unsigned int i=0; i<GeometryInfo<dim>::faces_per_cell; ++i)
{
if (cell->face(i)->boundary_id() == numbers::internal_face_boundary_id)
continue;
// If x,y or z is zero, then this is part of the plane
if (cell->face(i)->center()(0) < center(0)+1.e-5 * radius
|| cell->face(i)->center()(1) < center(1)+1.e-5 * radius
|| cell->face(i)->center()(2) < center(2)+1.e-5 * radius)
{
cell->face(i)->set_boundary_id(1);
// also set the boundary indicators of the bounding lines,
// unless both vertices are on the perimeter
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
{
const Point<3> line_vertices[2]
= { cell->face(i)->line(j)->vertex(0),
cell->face(i)->line(j)->vertex(1)
};
if ((std::fabs(line_vertices[0].distance(center)-radius) >
1e-5*radius)
||
(std::fabs(line_vertices[1].distance(center)-radius) >
1e-5*radius))
cell->face(i)->line(j)->set_boundary_id(1);
}
}
}
++cell;
}
}
// Implementation for 3D only
template <>
void
half_hyper_ball (Triangulation<3> &tria,
const Point<3> ¢er,
const double radius)
{
// These are for the two lower squares
const double d = radius/std::sqrt(2.0);
const double a = d/(1+std::sqrt(2.0));
// These are for the two upper square
const double b = a/2.0;
const double c = d/2.0;
// And so are these
const double hb = radius*std::sqrt(3.0)/4.0;
const double hc = radius*std::sqrt(3.0)/2.0;
Point<3> vertices[16] =
{
center+Point<3>( 0, d, -d),
center+Point<3>( 0, -d, -d),
center+Point<3>( 0, a, -a),
center+Point<3>( 0, -a, -a),
center+Point<3>( 0, a, a),
center+Point<3>( 0, -a, a),
center+Point<3>( 0, d, d),
center+Point<3>( 0, -d, d),
center+Point<3>(hc, c, -c),
center+Point<3>(hc, -c, -c),
center+Point<3>(hb, b, -b),
center+Point<3>(hb, -b, -b),
center+Point<3>(hb, b, b),
center+Point<3>(hb, -b, b),
center+Point<3>(hc, c, c),
center+Point<3>(hc, -c, c),
};
int cell_vertices[6][8] =
{
{0, 1, 8, 9, 2, 3, 10, 11},
{0, 2, 8, 10, 6, 4, 14, 12},
{2, 3, 10, 11, 4, 5, 12, 13},
{1, 7, 9, 15, 3, 5, 11, 13},
{6, 4, 14, 12, 7, 5, 15, 13},
{8, 10, 9, 11, 14, 12, 15, 13}
};
std::vector<CellData<3> > cells (6, CellData<3>());
for (unsigned int i=0; i<6; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<3> >(&vertices[0], &vertices[16]),
cells,
SubCellData()); // no boundary information
Triangulation<3>::cell_iterator cell = tria.begin();
Triangulation<3>::cell_iterator end = tria.end();
// go over all faces. for the ones on the flat face, set boundary
// indicator for face and edges to one; the rest will remain at
// zero but we have to pay attention to those edges that are
// at the perimeter of the flat face since they should not be
// set to one
while (cell != end)
{
for (unsigned int i=0; i<GeometryInfo<3>::faces_per_cell; ++i)
{
if (!cell->at_boundary(i))
continue;
// If the center is on the plane x=0, this is a planar element. set
// its boundary indicator. also set the boundary indicators of the
// bounding faces unless both vertices are on the perimeter
if (cell->face(i)->center()(0) < center(0)+1.e-5*radius)
{
cell->face(i)->set_boundary_id(1);
for (unsigned int j=0; j<GeometryInfo<3>::lines_per_face; ++j)
{
const Point<3> line_vertices[2]
= { cell->face(i)->line(j)->vertex(0),
cell->face(i)->line(j)->vertex(1)
};
if ((std::fabs(line_vertices[0].distance(center)-radius) >
1e-5*radius)
||
(std::fabs(line_vertices[1].distance(center)-radius) >
1e-5*radius))
cell->face(i)->line(j)->set_boundary_id(1);
}
}
}
++cell;
}
}
template <>
void
hyper_shell (Triangulation<3> &tria,
const Point<3> &p,
const double inner_radius,
const double outer_radius,
const unsigned int n_cells,
const bool colorize)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
const unsigned int n = (n_cells==0) ? 6 : n_cells;
const double irad = inner_radius/std::sqrt(3.0);
const double orad = outer_radius/std::sqrt(3.0);
std::vector<Point<3> > vertices;
std::vector<CellData<3> > cells;
// Start with the shell bounded by
// two nested cubes
if (n == 6)
{
for (unsigned int i=0; i<8; ++i)
vertices.push_back(p+hexahedron[i]*irad);
for (unsigned int i=0; i<8; ++i)
vertices.push_back(p+hexahedron[i]*orad);
const unsigned int n_cells = 6;
const int cell_vertices[n_cells][8] =
{
{8, 9, 10, 11, 0, 1, 2, 3}, // bottom
{9, 11, 1, 3, 13, 15, 5, 7}, // right
{12, 13, 4, 5, 14, 15, 6, 7}, // top
{8, 0, 10, 2, 12, 4, 14, 6}, // left
{8, 9, 0, 1, 12, 13, 4, 5}, // front
{10, 2, 11, 3, 14, 6, 15, 7}
}; // back
cells.resize(n_cells, CellData<3>());
for (unsigned int i=0; i<n_cells; ++i)
{
for (unsigned int j=0; j<GeometryInfo<3>::vertices_per_cell; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
}
tria.create_triangulation (vertices, cells, SubCellData());
}
// A more regular subdivision can
// be obtained by two nested
// rhombic dodecahedra
else if (n == 12)
{
for (unsigned int i=0; i<8; ++i)
vertices.push_back(p+hexahedron[i]*irad);
for (unsigned int i=0; i<6; ++i)
vertices.push_back(p+octahedron[i]*inner_radius);
for (unsigned int i=0; i<8; ++i)
vertices.push_back(p+hexahedron[i]*orad);
for (unsigned int i=0; i<6; ++i)
vertices.push_back(p+octahedron[i]*outer_radius);
const unsigned int n_cells = 12;
const unsigned int rhombi[n_cells][4] =
{
{ 10, 4, 0, 8},
{ 4, 13, 8, 6},
{ 10, 5, 4, 13},
{ 1, 9, 10, 5},
{ 9, 7, 5, 13},
{ 7, 11, 13, 6},
{ 9, 3, 7, 11},
{ 1, 12, 9, 3},
{ 12, 2, 3, 11},
{ 2, 8, 11, 6},
{ 12, 0, 2, 8},
{ 1, 10, 12, 0}
};
cells.resize(n_cells, CellData<3>());
for (unsigned int i=0; i<n_cells; ++i)
{
for (unsigned int j=0; j<4; ++j)
{
cells[i].vertices[j ] = rhombi[i][j];
cells[i].vertices[j+4] = rhombi[i][j] + 14;
}
cells[i].material_id = 0;
}
tria.create_triangulation (vertices, cells, SubCellData());
}
else if (n == 96)
{
// create a triangulation based on the
// 12-cell one where we refine the mesh
// once and then re-arrange all
// interior nodes so that the mesh is
// the least distorted
HyperShellBoundary<3> boundary (p);
Triangulation<3> tmp;
hyper_shell (tmp, p, inner_radius, outer_radius, 12);
tmp.set_boundary(0, boundary);
tmp.set_boundary(1, boundary);
tmp.refine_global (1);
// let's determine the distance at
// which the interior nodes should be
// from the center. let's say we
// measure distances in multiples of
// outer_radius and call
// r=inner_radius.
//
// then note
// that we now have 48 faces on the
// inner and 48 on the outer sphere,
// each with an area of approximately
// 4*pi/48*r^2 and 4*pi/48, for
// a face edge length of approximately
// sqrt(pi/12)*r and sqrt(pi/12)
//
// let's say we put the interior nodes
// at a distance rho, then a measure of
// deformation for the inner cells
// would be
// di=max(sqrt(pi/12)*r/(rho-r),
// (rho-r)/sqrt(pi/12)/r)
// and for the outer cells
// do=max(sqrt(pi/12)/(1-rho),
// (1-rho)/sqrt(pi/12))
//
// we now seek a rho so that the
// deformation of cells on the inside
// and outside is equal. there are in
// principle four possibilities for one
// of the branches of do== one of the
// branches of di, though not all of
// them satisfy do==di, of
// course. however, we are not
// interested in cases where the inner
// cell is long and skinny and the
// outer one tall -- yes, they have the
// same aspect ratio, but in different
// space directions.
//
// so it only boils down to the
// following two possibilities: the
// first branch of each max(.,.)
// functions are equal, or the second
// one are. on the other hand, since
// they two branches are reciprocals of
// each other, if one pair of branches
// is equal, so is the other
//
// this yields the following equation
// for rho:
// sqrt(pi/12)*r/(rho-r)
// == sqrt(pi/12)/(1-rho)
// with solution rho=2r/(1+r)
const double r = inner_radius / outer_radius;
const double rho = 2*r/(1+r);
// then this is the distance of the
// interior nodes from the center:
const double middle_radius = rho * outer_radius;
// mark vertices we've already moved or
// that we want to ignore: we don't
// want to move vertices at the inner
// or outer boundaries
std::vector<bool> vertex_already_treated (tmp.n_vertices(), false);
for (Triangulation<3>::active_cell_iterator cell = tmp.begin_active();
cell != tmp.end(); ++cell)
for (unsigned int f=0; f<GeometryInfo<3>::faces_per_cell; ++f)
if (cell->at_boundary(f))
for (unsigned int v=0; v<GeometryInfo<3>::vertices_per_face; ++v)
vertex_already_treated[cell->face(f)->vertex_index(v)] = true;
// now move the remaining vertices
for (Triangulation<3>::active_cell_iterator cell = tmp.begin_active();
cell != tmp.end(); ++cell)
for (unsigned int v=0; v<GeometryInfo<3>::vertices_per_cell; ++v)
if (vertex_already_treated[cell->vertex_index(v)] == false)
{
// this is a new interior
// vertex. mesh refinement may
// have placed it at a number
// of places in radial
// direction and oftentimes not
// in a particularly good
// one. move it to halfway
// between inner and outer
// sphere
const Tensor<1,3> old_distance = cell->vertex(v) - p;
const double old_radius = cell->vertex(v).distance(p);
cell->vertex(v) = p + old_distance * (middle_radius / old_radius);
vertex_already_treated[cell->vertex_index(v)] = true;
}
// now copy the resulting level 1 cells
// into the new triangulation,
cells.resize(tmp.n_active_cells(), CellData<3>());
for (Triangulation<3>::active_cell_iterator cell = tmp.begin_active();
cell != tmp.end(); ++cell)
{
const unsigned int cell_index = cell->active_cell_index();
for (unsigned int v=0; v<GeometryInfo<3>::vertices_per_cell; ++v)
cells[cell_index].vertices[v] = cell->vertex_index(v);
cells[cell_index].material_id = 0;
}
tria.create_triangulation (tmp.get_vertices(), cells, SubCellData());
}
else
{
Assert(false, ExcMessage ("Invalid number of coarse mesh cells."));
}
if (colorize)
colorize_hyper_shell(tria, p, inner_radius, outer_radius);
}
// Implementation for 3D only
template <>
void
half_hyper_shell (Triangulation<3> &tria,
const Point<3> ¢er,
const double inner_radius,
const double outer_radius,
const unsigned int n,
const bool colorize)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
if (n <= 5)
{
// These are for the two lower squares
const double d = outer_radius/std::sqrt(2.0);
const double a = inner_radius/std::sqrt(2.0);
// These are for the two upper square
const double b = a/2.0;
const double c = d/2.0;
// And so are these
const double hb = inner_radius*std::sqrt(3.0)/2.0;
const double hc = outer_radius*std::sqrt(3.0)/2.0;
Point<3> vertices[16] =
{
center+Point<3>( 0, d, -d),
center+Point<3>( 0, -d, -d),
center+Point<3>( 0, a, -a),
center+Point<3>( 0, -a, -a),
center+Point<3>( 0, a, a),
center+Point<3>( 0, -a, a),
center+Point<3>( 0, d, d),
center+Point<3>( 0, -d, d),
center+Point<3>(hc, c, -c),
center+Point<3>(hc, -c, -c),
center+Point<3>(hb, b, -b),
center+Point<3>(hb, -b, -b),
center+Point<3>(hb, b, b),
center+Point<3>(hb, -b, b),
center+Point<3>(hc, c, c),
center+Point<3>(hc, -c, c),
};
int cell_vertices[5][8] =
{
{0, 1, 8, 9, 2, 3, 10, 11},
{0, 2, 8, 10, 6, 4, 14, 12},
{1, 7, 9, 15, 3, 5, 11, 13},
{6, 4, 14, 12, 7, 5, 15, 13},
{8, 10, 9, 11, 14, 12, 15, 13}
};
std::vector<CellData<3> > cells (5, CellData<3>());
for (unsigned int i=0; i<5; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
};
tria.create_triangulation (
std::vector<Point<3> >(&vertices[0], &vertices[16]),
cells,
SubCellData()); // no boundary information
}
else
{
Assert(false, ExcIndexRange(n, 0, 5));
}
if (colorize)
{
// We want to use a standard boundary description where
// the boundary is not curved. Hence set boundary id 2 to
// to all faces in a first step.
Triangulation<3>::cell_iterator cell = tria.begin();
for (; cell!=tria.end(); ++cell)
for (unsigned int i=0; i<GeometryInfo<3>::faces_per_cell; ++i)
if (cell->at_boundary(i))
cell->face(i)->set_all_boundary_ids(2);
// Next look for the curved boundaries. If the x value of the
// center of the face is not equal to center(0), we're on a curved
// boundary. Then decide whether the center is nearer to the inner
// or outer boundary to set the correct boundary id.
for (cell=tria.begin(); cell!=tria.end(); ++cell)
for (unsigned int i=0; i<GeometryInfo<3>::faces_per_cell; ++i)
if (cell->at_boundary(i))
{
const Triangulation<3>::face_iterator face
= cell->face(i);
const Point<3> face_center (face->center());
if (std::abs(face_center(0)-center(0)) > 1.e-6 * face_center.norm())
{
if (std::abs((face_center-center).norm()-inner_radius) <
std::abs((face_center-center).norm()-outer_radius))
face->set_all_boundary_ids(0);
else
face->set_all_boundary_ids(1);
}
}
}
}
// Implementation for 3D only
template <>
void quarter_hyper_shell (Triangulation<3> &tria,
const Point<3> ¢er,
const double inner_radius,
const double outer_radius,
const unsigned int n,
const bool colorize)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
if (n == 0 || n == 3)
{
const double a = inner_radius*std::sqrt(2.0)/2e0;
const double b = outer_radius*std::sqrt(2.0)/2e0;
const double c = a*std::sqrt(3.0)/2e0;
const double d = b*std::sqrt(3.0)/2e0;
const double e = outer_radius/2e0;
const double h = inner_radius/2e0;
std::vector<Point<3> > vertices;
vertices.push_back (center+Point<3>( 0, inner_radius, 0)); //0
vertices.push_back (center+Point<3>( a, a, 0)); //1
vertices.push_back (center+Point<3>( b, b, 0)); //2
vertices.push_back (center+Point<3>( 0, outer_radius, 0)); //3
vertices.push_back (center+Point<3>( 0, a , a)); //4
vertices.push_back (center+Point<3>( c, c , h)); //5
vertices.push_back (center+Point<3>( d, d , e)); //6
vertices.push_back (center+Point<3>( 0, b , b)); //7
vertices.push_back (center+Point<3>( inner_radius, 0 , 0)); //8
vertices.push_back (center+Point<3>( outer_radius, 0 , 0)); //9
vertices.push_back (center+Point<3>( a, 0 , a)); //10
vertices.push_back (center+Point<3>( b, 0 , b)); //11
vertices.push_back (center+Point<3>( 0, 0 , inner_radius)); //12
vertices.push_back (center+Point<3>( 0, 0 , outer_radius)); //13
const int cell_vertices[3][8] =
{
{0, 1, 3, 2, 4, 5, 7, 6},
{1, 8, 2, 9, 5, 10, 6, 11},
{4, 5, 7, 6, 12, 10, 13, 11},
};
std::vector<CellData<3> > cells(3);
for (unsigned int i=0; i<3; ++i)
{
for (unsigned int j=0; j<8; ++j)
cells[i].vertices[j] = cell_vertices[i][j];
cells[i].material_id = 0;
}
tria.create_triangulation ( vertices, cells, SubCellData()); // no boundary information
}
else
{
AssertThrow(false, ExcNotImplemented());
}
if (colorize)
colorize_quarter_hyper_shell(tria, center, inner_radius, outer_radius);
}
// Implementation for 3D only
template <>
void cylinder_shell (Triangulation<3> &tria,
const double length,
const double inner_radius,
const double outer_radius,
const unsigned int n_radial_cells,
const unsigned int n_axial_cells)
{
Assert ((inner_radius > 0) && (inner_radius < outer_radius),
ExcInvalidRadii ());
const double pi = numbers::PI;
// determine the number of cells
// for the grid. if not provided by
// the user determine it such that
// the length of each cell on the
// median (in the middle between
// the two circles) is equal to its
// radial extent (which is the
// difference between the two
// radii)
const unsigned int N_r = (n_radial_cells == 0 ?
static_cast<unsigned int>
(std::ceil((2*pi* (outer_radius + inner_radius)/2) /
(outer_radius - inner_radius))) :
n_radial_cells);
const unsigned int N_z = (n_axial_cells == 0 ?
static_cast<unsigned int>
(std::ceil (length /
(2*pi*(outer_radius + inner_radius)/2/N_r))) :
n_axial_cells);
// set up N vertices on the
// outer and N vertices on
// the inner circle. the
// first N ones are on the
// outer one, and all are
// numbered counter-clockwise
std::vector<Point<2> > vertices_2d(2*N_r);
for (unsigned int i=0; i<N_r; ++i)
{
vertices_2d[i] = Point<2>( std::cos(2*pi * i/N_r),
std::sin(2*pi * i/N_r)) * outer_radius;
vertices_2d[i+N_r] = vertices_2d[i] * (inner_radius/outer_radius);
};
std::vector<Point<3> > vertices_3d;
vertices_3d.reserve (2*N_r*(N_z+1));
for (unsigned int j=0; j<=N_z; ++j)
for (unsigned int i=0; i<2*N_r; ++i)
{
const Point<3> v (vertices_2d[i][0],
vertices_2d[i][1],
j*length/N_z);
vertices_3d.push_back (v);
}
std::vector<CellData<3> > cells (N_r*N_z, CellData<3>());
for (unsigned int j=0; j<N_z; ++j)
for (unsigned int i=0; i<N_r; ++i)
{
cells[i+j*N_r].vertices[0] = i + (j+1)*2*N_r;
cells[i+j*N_r].vertices[1] = (i+1)%N_r + (j+1)*2*N_r;
cells[i+j*N_r].vertices[2] = i + j*2*N_r;
cells[i+j*N_r].vertices[3] = (i+1)%N_r + j*2*N_r;
cells[i+j*N_r].vertices[4] = N_r+i + (j+1)*2*N_r;
cells[i+j*N_r].vertices[5] = N_r+((i+1)%N_r) + (j+1)*2*N_r;
cells[i+j*N_r].vertices[6] = N_r+i + j*2*N_r;
cells[i+j*N_r].vertices[7] = N_r+((i+1)%N_r) + j*2*N_r;
cells[i+j*N_r].material_id = 0;
}
tria.create_triangulation (
vertices_3d, cells, SubCellData());
}
template <int dim, int spacedim>
void
merge_triangulations (const Triangulation<dim, spacedim> &triangulation_1,
const Triangulation<dim, spacedim> &triangulation_2,
Triangulation<dim, spacedim> &result)
{
Assert (triangulation_1.n_levels() == 1,
ExcMessage ("The input triangulations must be coarse meshes."));
Assert (triangulation_2.n_levels() == 1,
ExcMessage ("The input triangulations must be coarse meshes."));
// get the union of the set of vertices
std::vector<Point<spacedim> > vertices = triangulation_1.get_vertices();
vertices.insert (vertices.end(),
triangulation_2.get_vertices().begin(),
triangulation_2.get_vertices().end());
// now form the union of the set of cells
std::vector<CellData<dim> > cells;
cells.reserve (triangulation_1.n_cells() + triangulation_2.n_cells());
for (typename Triangulation<dim,spacedim>::cell_iterator
cell = triangulation_1.begin(); cell != triangulation_1.end(); ++cell)
{
CellData<dim> this_cell;
for (unsigned int v=0; v<GeometryInfo<dim>::vertices_per_cell; ++v)
this_cell.vertices[v] = cell->vertex_index(v);
this_cell.material_id = cell->material_id();
cells.push_back (this_cell);
}
// now do the same for the other other mesh. note that we have to
// translate the vertex indices
for (typename Triangulation<dim,spacedim>::cell_iterator
cell = triangulation_2.begin(); cell != triangulation_2.end(); ++cell)
{
CellData<dim> this_cell;
for (unsigned int v=0; v<GeometryInfo<dim>::vertices_per_cell; ++v)
this_cell.vertices[v] = cell->vertex_index(v) + triangulation_1.n_vertices();
this_cell.material_id = cell->material_id();
cells.push_back (this_cell);
}
// throw out duplicated vertices from the two meshes, reorder vertices as
// necessary and create the triangulation
SubCellData subcell_data;
std::vector<unsigned int> considered_vertices;
GridTools::delete_duplicated_vertices (vertices, cells,
subcell_data,
considered_vertices);
// reorder the cells to ensure that they satisfy the convention for
// edge and face directions
GridReordering<dim, spacedim>::reorder_cells(cells, true);
result.clear ();
result.create_triangulation (vertices, cells, subcell_data);
}
template <int dim, int spacedim>
void
create_union_triangulation (const Triangulation<dim, spacedim> &triangulation_1,
const Triangulation<dim, spacedim> &triangulation_2,
Triangulation<dim, spacedim> &result)
{
Assert (GridTools::have_same_coarse_mesh (triangulation_1, triangulation_2),
ExcMessage ("The two input triangulations are not derived from "
"the same coarse mesh as required."));
Assert ((dynamic_cast<const parallel::distributed::Triangulation<dim,spacedim>*>(&triangulation_1) == 0)
&&
(dynamic_cast<const parallel::distributed::Triangulation<dim,spacedim>*>(&triangulation_2) == 0),
ExcMessage ("The source triangulations for this function must both "
"be available entirely locally, and not be distributed "
"triangulations."));
// first copy triangulation_1, and
// then do as many iterations as
// there are levels in
// triangulation_2 to refine
// additional cells. since this is
// the maximum number of
// refinements to get from the
// coarse grid to triangulation_2,
// it is clear that this is also
// the maximum number of
// refinements to get from any cell
// on triangulation_1 to
// triangulation_2
result.clear ();
result.copy_triangulation (triangulation_1);
for (unsigned int iteration=0; iteration<triangulation_2.n_levels();
++iteration)
{
InterGridMap<Triangulation<dim, spacedim> > intergrid_map;
intergrid_map.make_mapping (result, triangulation_2);
bool any_cell_flagged = false;
for (typename Triangulation<dim, spacedim>::active_cell_iterator
result_cell = result.begin_active();
result_cell != result.end(); ++result_cell)
if (intergrid_map[result_cell]->has_children())
{
any_cell_flagged = true;
result_cell->set_refine_flag ();
}
if (any_cell_flagged == false)
break;
else
result.execute_coarsening_and_refinement();
}
}
template <int dim, int spacedim>
void
create_triangulation_with_removed_cells (const Triangulation<dim, spacedim> &input_triangulation,
const std::set<typename Triangulation<dim, spacedim>::active_cell_iterator> &cells_to_remove,
Triangulation<dim, spacedim> &result)
{
// simply copy the vertices; we will later strip those
// that turn out to be unused
std::vector<Point<spacedim> > vertices = input_triangulation.get_vertices();
// the loop through the cells and copy stuff, excluding
// the ones we are to remove
std::vector<CellData<dim> > cells;
for (typename Triangulation<dim,spacedim>::active_cell_iterator
cell = input_triangulation.begin_active(); cell != input_triangulation.end(); ++cell)
if (cells_to_remove.find(cell) == cells_to_remove.end())
{
Assert (static_cast<unsigned int>(cell->level()) == input_triangulation.n_levels()-1,
ExcMessage ("Your input triangulation appears to have "
"adaptively refined cells. This is not allowed. You can "
"only call this function on a triangulation in which "
"all cells are on the same refinement level."));
CellData<dim> this_cell;
for (unsigned int v=0; v<GeometryInfo<dim>::vertices_per_cell; ++v)
this_cell.vertices[v] = cell->vertex_index(v);
this_cell.material_id = cell->material_id();
cells.push_back (this_cell);
}
// throw out duplicated vertices from the two meshes, reorder vertices as
// necessary and create the triangulation
SubCellData subcell_data;
std::vector<unsigned int> considered_vertices;
GridTools::delete_duplicated_vertices (vertices, cells,
subcell_data,
considered_vertices);
// then clear the old triangulation and create the new one
result.clear ();
result.create_triangulation (vertices, cells, subcell_data);
}
void
extrude_triangulation(const Triangulation<2, 2> &input,
const unsigned int n_slices,
const double height,
Triangulation<3,3> &result)
{
Assert (input.n_levels() == 1,
ExcMessage ("The input triangulation must be a coarse mesh, i.e., it must "
"not have been refined."));
Assert(result.n_cells()==0,
ExcMessage("The output triangulation object needs to be empty."));
Assert(height>0,
ExcMessage("The given height for extrusion must be positive."));
Assert(n_slices>=2,
ExcMessage("The number of slices for extrusion must be at least 2."));
std::vector<Point<3> > points(n_slices*input.n_vertices());
std::vector<CellData<3> > cells;
cells.reserve((n_slices-1)*input.n_active_cells());
// copy the array of points as many times as there will be slices,
// one slice at a time
for (unsigned int slice=0; slice<n_slices; ++slice)
{
for (unsigned int i=0; i<input.n_vertices(); ++i)
{
const Point<2> &v = input.get_vertices()[i];
points[slice*input.n_vertices()+i](0) = v(0);
points[slice*input.n_vertices()+i](1) = v(1);
points[slice*input.n_vertices()+i](2) = height * slice / (n_slices-1);
}
}
// then create the cells of each of the slices, one stack at a
// time
for (Triangulation<2,2>::cell_iterator
cell = input.begin(); cell != input.end(); ++cell)
{
for (unsigned int slice=0; slice<n_slices-1; ++slice)
{
CellData<3> this_cell;
for (unsigned int v=0; v<GeometryInfo<2>::vertices_per_cell; ++v)
{
this_cell.vertices[v]
= cell->vertex_index(v)+slice*input.n_vertices();
this_cell.vertices[v+GeometryInfo<2>::vertices_per_cell]
= cell->vertex_index(v)+(slice+1)*input.n_vertices();
}
this_cell.material_id = cell->material_id();
cells.push_back(this_cell);
}
}
// next, create face data for all of the outer faces for which the
// boundary indicator will not be equal to zero (where we would
// explicitly set it to something that is already the default --
// no need to do that)
SubCellData s;
types::boundary_id max_boundary_id=0;
s.boundary_quads.reserve(input.n_active_lines()*(n_slices-1) + input.n_active_cells()*2);
for (Triangulation<2,2>::cell_iterator
cell = input.begin(); cell != input.end(); ++cell)
{
CellData<2> quad;
for (unsigned int f=0; f<4; ++f)
if (cell->at_boundary(f)
&&
(cell->face(f)->boundary_id() != 0))
{
quad.boundary_id = cell->face(f)->boundary_id();
max_boundary_id = std::max(max_boundary_id, quad.boundary_id);
for (unsigned int slice=0; slice<n_slices-1; ++slice)
{
quad.vertices[0] = cell->face(f)->vertex_index(0)+slice*input.n_vertices();
quad.vertices[1] = cell->face(f)->vertex_index(1)+slice*input.n_vertices();
quad.vertices[2] = cell->face(f)->vertex_index(0)+(slice+1)*input.n_vertices();
quad.vertices[3] = cell->face(f)->vertex_index(1)+(slice+1)*input.n_vertices();
s.boundary_quads.push_back(quad);
}
}
}
// then mark the bottom and top boundaries of the extruded mesh
// with max_boundary_id+1 and max_boundary_id+2. check that this
// remains valid
Assert ((max_boundary_id != numbers::invalid_boundary_id) &&
(max_boundary_id+1 != numbers::invalid_boundary_id) &&
(max_boundary_id+2 != numbers::invalid_boundary_id),
ExcMessage ("The input triangulation to this function is using boundary "
"indicators in a range that do not allow using "
"max_boundary_id+1 and max_boundary_id+2 as boundary "
"indicators for the bottom and top faces of the "
"extruded triangulation."));
for (Triangulation<2,2>::cell_iterator
cell = input.begin(); cell != input.end(); ++cell)
{
CellData<2> quad;
quad.boundary_id = max_boundary_id + 1;
quad.vertices[0] = cell->vertex_index(0);
quad.vertices[1] = cell->vertex_index(1);
quad.vertices[2] = cell->vertex_index(2);
quad.vertices[3] = cell->vertex_index(3);
s.boundary_quads.push_back(quad);
quad.boundary_id = max_boundary_id + 2;
for (int i=0; i<4; ++i)
quad.vertices[i] += (n_slices-1)*input.n_vertices();
s.boundary_quads.push_back(quad);
}
// use all of this to finally create the extruded 3d
// triangulation. it is not necessary to call
// GridReordering<3,3>::reorder_cells because the cells we have
// constructed above are automatically correctly oriented. this is
// because the 2d base mesh is always correctly oriented, and
// extruding it automatically yields a correctly oriented 3d mesh,
// as discussed in the edge orientation paper mentioned in the
// introduction to the GridReordering class.
result.create_triangulation (points,
cells,
s);
}
template <>
void hyper_cube_with_cylindrical_hole (Triangulation<1> &,
const double,
const double,
const double,
const unsigned int,
bool)
{
Assert(false, ExcNotImplemented());
}
template <>
void
hyper_cube_with_cylindrical_hole (Triangulation<2> &triangulation,
const double inner_radius,
const double outer_radius,
const double, // width,
const unsigned int, // width_repetition,
bool colorize)
{
const int dim = 2;
Assert(inner_radius < outer_radius,
ExcMessage("outer_radius has to be bigger than inner_radius."));
Point<dim> center;
// We create an hyper_shell in two dimensions, and then we modify it.
hyper_shell (triangulation,
center, inner_radius, outer_radius,
8);
Triangulation<dim>::active_cell_iterator
cell = triangulation.begin_active(),
endc = triangulation.end();
std::vector<bool> treated_vertices(triangulation.n_vertices(), false);
for (; cell != endc; ++cell)
{
for (unsigned int f=0; f<GeometryInfo<dim>::faces_per_cell; ++f)
if (cell->face(f)->at_boundary())
{
for (unsigned int v=0; v < GeometryInfo<dim>::vertices_per_face; ++v)
{
unsigned int vv = cell->face(f)->vertex_index(v);
if (treated_vertices[vv] == false)
{
treated_vertices[vv] = true;
switch (vv)
{
case 1:
cell->face(f)->vertex(v) = center+Point<dim>(outer_radius,outer_radius);
break;
case 3:
cell->face(f)->vertex(v) = center+Point<dim>(-outer_radius,outer_radius);
break;
case 5:
cell->face(f)->vertex(v) = center+Point<dim>(-outer_radius,-outer_radius);
break;
case 7:
cell->face(f)->vertex(v) = center+Point<dim>(outer_radius,-outer_radius);
default:
break;
}
}
}
}
}
double eps = 1e-3 * outer_radius;
cell = triangulation.begin_active();
for (; cell != endc; ++cell)
{
for (unsigned int f=0; f<GeometryInfo<dim>::faces_per_cell; ++f)
if (cell->face(f)->at_boundary())
{
double dx = cell->face(f)->center()(0) - center(0);
double dy = cell->face(f)->center()(1) - center(1);
if (colorize)
{
if (std::abs(dx + outer_radius) < eps)
cell->face(f)->set_boundary_id(0);
else if (std::abs(dx - outer_radius) < eps)
cell->face(f)->set_boundary_id(1);
else if (std::abs(dy + outer_radius) < eps)
cell->face(f)->set_boundary_id(2);
else if (std::abs(dy - outer_radius) < eps)
cell->face(f)->set_boundary_id(3);
else
cell->face(f)->set_boundary_id(4);
}
else
{
double d = (cell->face(f)->center() - center).norm();
if (d-inner_radius < 0)
cell->face(f)->set_boundary_id(1);
else
cell->face(f)->set_boundary_id(0);
}
}
}
}
template <>
void hyper_cube_with_cylindrical_hole(Triangulation<3> &triangulation,
const double inner_radius,
const double outer_radius,
const double L,
const unsigned int Nz,
bool colorize)
{
const int dim = 3;
Assert(inner_radius < outer_radius,
ExcMessage("outer_radius has to be bigger than inner_radius."));
Assert(L > 0,
ExcMessage("Must give positive extension L"));
Assert(Nz >= 1, ExcLowerRange(1, Nz));
cylinder_shell (triangulation,
L, inner_radius, outer_radius,
8,
Nz);
Triangulation<dim>::active_cell_iterator
cell = triangulation.begin_active(),
endc = triangulation.end();
std::vector<bool> treated_vertices(triangulation.n_vertices(), false);
for (; cell != endc; ++cell)
{
for (unsigned int f=0; f<GeometryInfo<dim>::faces_per_cell; ++f)
if (cell->face(f)->at_boundary())
{
for (unsigned int v=0; v < GeometryInfo<dim>::vertices_per_face; ++v)
{
unsigned int vv = cell->face(f)->vertex_index(v);
if (treated_vertices[vv] == false)
{
treated_vertices[vv] = true;
for (unsigned int i=0; i<=Nz; ++i)
{
double d = ((double) i)*L/((double) Nz);
switch (vv-i*16)
{
case 1:
cell->face(f)->vertex(v) = Point<dim>(outer_radius,outer_radius,d);
break;
case 3:
cell->face(f)->vertex(v) = Point<dim>(-outer_radius,outer_radius,d);
break;
case 5:
cell->face(f)->vertex(v) = Point<dim>(-outer_radius,-outer_radius,d);
break;
case 7:
cell->face(f)->vertex(v) = Point<dim>(outer_radius,-outer_radius,d);
break;
default:
break;
}
}
}
}
}
}
double eps = 1e-3 * outer_radius;
cell = triangulation.begin_active();
for (; cell != endc; ++cell)
{
for (unsigned int f=0; f<GeometryInfo<dim>::faces_per_cell; ++f)
if (cell->face(f)->at_boundary())
{
double dx = cell->face(f)->center()(0);
double dy = cell->face(f)->center()(1);
double dz = cell->face(f)->center()(2);
if (colorize)
{
if (std::abs(dx + outer_radius) < eps)
cell->face(f)->set_boundary_id(0);
else if (std::abs(dx - outer_radius) < eps)
cell->face(f)->set_boundary_id(1);
else if (std::abs(dy + outer_radius) < eps)
cell->face(f)->set_boundary_id(2);
else if (std::abs(dy - outer_radius) < eps)
cell->face(f)->set_boundary_id(3);
else if (std::abs(dz) < eps)
cell->face(f)->set_boundary_id(4);
else if (std::abs(dz - L) < eps)
cell->face(f)->set_boundary_id(5);
else
{
cell->face(f)->set_boundary_id(6);
for (unsigned int l=0; l<GeometryInfo<dim>::lines_per_face; ++l)
cell->face(f)->line(l)->set_boundary_id(6);
}
}
else
{
Point<dim> c = cell->face(f)->center();
c(2) = 0;
double d = c.norm();
if (d-inner_radius < 0)
{
cell->face(f)->set_boundary_id(1);
for (unsigned int l=0; l<GeometryInfo<dim>::lines_per_face; ++l)
cell->face(f)->line(l)->set_boundary_id(1);
}
else
cell->face(f)->set_boundary_id(0);
}
}
}
}
template <int dim, int spacedim1, int spacedim2>
void flatten_triangulation(const Triangulation<dim, spacedim1> &in_tria,
Triangulation<dim,spacedim2> &out_tria)
{
const parallel::distributed::Triangulation<dim, spacedim1> *pt =
dynamic_cast<const parallel::distributed::Triangulation<dim, spacedim1> *>(&in_tria);
(void)pt;
Assert (pt == NULL,
ExcMessage("Cannot use this function on parallel::distributed::Triangulation."));
std::vector<Point<spacedim2> > v;
std::vector<CellData<dim> > cells;
SubCellData subcelldata;
const unsigned int spacedim = std::min(spacedim1,spacedim2);
const std::vector<Point<spacedim1> > &in_vertices = in_tria.get_vertices();
v.resize(in_vertices.size());
for (unsigned int i=0; i<in_vertices.size(); ++i)
for (unsigned int d=0; d<spacedim; ++d)
v[i][d] = in_vertices[i][d];
cells.resize(in_tria.n_active_cells());
typename Triangulation<dim,spacedim1>::active_cell_iterator
cell = in_tria.begin_active(),
endc = in_tria.end();
for (unsigned int id=0; cell != endc; ++cell, ++id)
{
for (unsigned int i=0; i<GeometryInfo<dim>::vertices_per_cell; ++i)
cells[id].vertices[i] = cell->vertex_index(i);
cells[id].material_id = cell->material_id();
cells[id].manifold_id = cell->manifold_id();
}
if (dim>1)
{
typename Triangulation<dim,spacedim1>::active_face_iterator
face = in_tria.begin_active_face(),
endf = in_tria.end_face();
// Face counter for both dim == 2 and dim == 3
unsigned int f=0;
switch (dim)
{
case 2:
{
subcelldata.boundary_lines.resize(in_tria.n_active_faces());
for (; face != endf; ++face)
if (face->at_boundary())
{
for (unsigned int i=0; i<GeometryInfo<dim>::vertices_per_face; ++i)
subcelldata.boundary_lines[f].vertices[i] = face->vertex_index(i);
subcelldata.boundary_lines[f].boundary_id = face->boundary_id();
subcelldata.boundary_lines[f].manifold_id = face->manifold_id();
++f;
}
subcelldata.boundary_lines.resize(f);
}
break;
case 3:
{
subcelldata.boundary_quads.resize(in_tria.n_active_faces());
for (; face != endf; ++face)
if (face->at_boundary())
{
for (unsigned int i=0; i<GeometryInfo<dim>::vertices_per_face; ++i)
subcelldata.boundary_quads[f].vertices[i] = face->vertex_index(i);
subcelldata.boundary_quads[f].boundary_id = face->boundary_id();
subcelldata.boundary_quads[f].manifold_id = face->manifold_id();
++f;
}
subcelldata.boundary_quads.resize(f);
}
break;
default:
Assert(false, ExcInternalError());
}
}
out_tria.create_triangulation(v, cells, subcelldata);
}
template <template <int,int> class MeshType, int dim, int spacedim>
#ifndef _MSC_VER
std::map<typename MeshType<dim-1,spacedim>::cell_iterator,
typename MeshType<dim,spacedim>::face_iterator>
#else
typename ExtractBoundaryMesh<MeshType,dim,spacedim>::return_type
#endif
extract_boundary_mesh (const MeshType<dim,spacedim> &volume_mesh,
MeshType<dim-1,spacedim> &surface_mesh,
const std::set<types::boundary_id> &boundary_ids)
{
Assert ((dynamic_cast<const parallel::distributed::Triangulation<dim,spacedim>*>
(&volume_mesh.get_triangulation())
== 0),
ExcNotImplemented());
// This function works using the following assumption:
// Triangulation::create_triangulation(...) will create cells that preserve
// the order of cells passed in using the CellData argument; also,
// that it will not reorder the vertices.
std::map<typename MeshType<dim-1,spacedim>::cell_iterator,
typename MeshType<dim,spacedim>::face_iterator>
surface_to_volume_mapping;
const unsigned int boundary_dim = dim-1; //dimension of the boundary mesh
// First create surface mesh and mapping
// from only level(0) cells of volume_mesh
std::vector<typename MeshType<dim,spacedim>::face_iterator>
mapping; // temporary map for level==0
std::vector< bool > touched (volume_mesh.get_triangulation().n_vertices(), false);
std::vector< CellData< boundary_dim > > cells;
SubCellData subcell_data;
std::vector< Point<spacedim> > vertices;
std::map<unsigned int,unsigned int> map_vert_index; //volume vertex indices to surf ones
for (typename MeshType<dim,spacedim>::cell_iterator
cell = volume_mesh.begin(0);
cell != volume_mesh.end(0);
++cell)
for (unsigned int i=0; i < GeometryInfo<dim>::faces_per_cell; ++i)
{
const typename MeshType<dim,spacedim>::face_iterator
face = cell->face(i);
if ( face->at_boundary()
&&
(boundary_ids.empty() ||
( boundary_ids.find(face->boundary_id()) != boundary_ids.end())) )
{
CellData< boundary_dim > c_data;
for (unsigned int j=0;
j<GeometryInfo<boundary_dim>::vertices_per_cell; ++j)
{
const unsigned int v_index = face->vertex_index(j);
if ( !touched[v_index] )
{
vertices.push_back(face->vertex(j));
map_vert_index[v_index] = vertices.size() - 1;
touched[v_index] = true;
}
c_data.vertices[j] = map_vert_index[v_index];
c_data.material_id = static_cast<types::material_id>(face->boundary_id());
}
// if we start from a 3d mesh, then we have copied the
// vertex information in the same order in which they
// appear in the face; however, this means that we
// impart a coordinate system that is right-handed when
// looked at *from the outside* of the cell if the
// current face has index 0, 2, 4 within a 3d cell, but
// right-handed when looked at *from the inside* for the
// other faces. we fix this by flipping opposite
// vertices if we are on a face 1, 3, 5
if (dim == 3)
if (i % 2 == 1)
std::swap (c_data.vertices[1], c_data.vertices[2]);
// in 3d, we also need to make sure we copy the manifold
// indicators from the edges of the volume mesh to the
// edges of the surface mesh
//
// one might think that we we can also prescribe
// boundary indicators for edges, but this is only
// possible for edges that aren't just on the boundary
// of the domain (all of the edges we consider are!) but
// that would actually end up at the boundary of the
// surface mesh. there is no easy way to check this, so
// we simply don't do it and instead set it to an
// invalid value that makes sure
// Triangulation::create_triangulation doesn't copy it
if (dim == 3)
for (unsigned int e=0; e<4; ++e)
{
// see if we already saw this edge from a
// neighboring face, either in this or the reverse
// orientation. if so, skip it.
{
bool edge_found = false;
for (unsigned int i=0; i<subcell_data.boundary_lines.size(); ++i)
if (((subcell_data.boundary_lines[i].vertices[0]
== map_vert_index[face->line(e)->vertex_index(0)])
&&
(subcell_data.boundary_lines[i].vertices[1]
== map_vert_index[face->line(e)->vertex_index(1)]))
||
((subcell_data.boundary_lines[i].vertices[0]
== map_vert_index[face->line(e)->vertex_index(1)])
&&
(subcell_data.boundary_lines[i].vertices[1]
== map_vert_index[face->line(e)->vertex_index(0)])))
{
edge_found = true;
break;
}
if (edge_found == true)
continue; // try next edge of current face
}
CellData<1> edge;
edge.vertices[0] = map_vert_index[face->line(e)->vertex_index(0)];
edge.vertices[1] = map_vert_index[face->line(e)->vertex_index(1)];
edge.boundary_id = numbers::internal_face_boundary_id;
edge.manifold_id = face->line(e)->manifold_id();
subcell_data.boundary_lines.push_back (edge);
}
cells.push_back(c_data);
mapping.push_back(face);
}
}
// create level 0 surface triangulation
Assert (cells.size() > 0, ExcMessage ("No boundary faces selected"));
const_cast<Triangulation<dim-1,spacedim>&>(surface_mesh.get_triangulation())
.create_triangulation (vertices, cells, subcell_data);
// Make the actual mapping
for (typename MeshType<dim-1,spacedim>::active_cell_iterator
cell = surface_mesh.begin(0);
cell!=surface_mesh.end(0); ++cell)
surface_to_volume_mapping[cell] = mapping.at(cell->index());
do
{
bool changed = false;
for (typename MeshType<dim-1,spacedim>::active_cell_iterator
cell = surface_mesh.begin_active(); cell!=surface_mesh.end(); ++cell)
if (surface_to_volume_mapping[cell]->has_children() == true )
{
cell->set_refine_flag ();
changed = true;
}
if (changed)
{
const_cast<Triangulation<dim-1,spacedim>&>(surface_mesh.get_triangulation())
.execute_coarsening_and_refinement();
for (typename MeshType<dim-1,spacedim>::cell_iterator
surface_cell = surface_mesh.begin(); surface_cell!=surface_mesh.end(); ++surface_cell)
for (unsigned int c=0; c<surface_cell->n_children(); c++)
if (surface_to_volume_mapping.find(surface_cell->child(c)) == surface_to_volume_mapping.end())
surface_to_volume_mapping[surface_cell->child(c)]
= surface_to_volume_mapping[surface_cell]->child(c);
}
else
break;
}
while (true);
return surface_to_volume_mapping;
}
}
// explicit instantiations
namespace GridGenerator
{
template void
hyper_sphere< 1 , 2 > (Triangulation< 1 , 2> &,
const Point<2> ¢er,
const double radius);
template void
hyper_sphere< 2 , 3 > (Triangulation< 2 , 3> &,
const Point<3> ¢er,
const double radius);
}
#include "grid_generator.inst"
DEAL_II_NAMESPACE_CLOSE
| shakirbsm/dealii | source/grid/grid_generator.cc | C++ | lgpl-2.1 | 160,471 |
'''
Package contains all original tank tool plugins
'''
| asekretenko/yandex-tank | yandextank/plugins/__init__.py | Python | lgpl-2.1 | 56 |
# Copyright 2013-2020 Lawrence Livermore National Security, LLC and other
# Spack Project Developers. See the top-level COPYRIGHT file for details.
#
# SPDX-License-Identifier: (Apache-2.0 OR MIT)
from spack import *
class PyProgressbar2(PythonPackage):
"""A progress bar for Python 2 and Python 3"""
homepage = "https://github.com/WoLpH/python-progressbar"
url = "https://pypi.io/packages/source/p/progressbar2/progressbar2-3.50.1.tar.gz"
version('3.50.1', sha256='2c21c14482016162852c8265da03886c2b4dea6f84e5a817ad9b39f6bd82a772')
version('3.39.3', sha256='8e5b5419e04193bb7c3fea71579937bbbcd64c26472b929718c2fe7ec420fe39')
depends_on('py-setuptools', type='build')
depends_on('py-six', type=('build', 'run'))
depends_on('[email protected]:', type=('build', 'run'))
| iulian787/spack | var/spack/repos/builtin/packages/py-progressbar2/package.py | Python | lgpl-2.1 | 816 |
/*
* BioJava development code
*
* This code may be freely distributed and modified under the
* terms of the GNU Lesser General Public Licence. This should
* be distributed with the code. If you do not have a copy,
* see:
*
* http://www.gnu.org/copyleft/lesser.html
*
* Copyright for this code is held jointly by the individual
* authors. These should be listed in @author doc comments.
*
* For more information on the BioJava project and its aims,
* or to join the biojava-l mailing list, visit the home page
* at:
*
* http://www.biojava.org/
*
* Created on Apr 6, 2010
* Author: Andreas Prlic
*
*/
package org.biojava.nbio.structure.align.webstart;
import javax.swing.*;
import javax.swing.UIManager.LookAndFeelInfo;
public class AligUIManager
{
public static void setLookAndFeel(){
try {
String system = UIManager.getSystemLookAndFeelClassName();
if ( system != null) {
//System.out.println("setting look and feel to " + system);
UIManager.setLookAndFeel(system);
}
//System.out.println("Installed Look And Feels:");
LookAndFeelInfo[] feels = UIManager.getInstalledLookAndFeels();
if ( feels != null){
//for ( LookAndFeelInfo info: feels){
//System.out.println(info.getName() + " " + info.getClassName());
// }
}
//System.out.println("Auxiliary Look And Feels:");
// LookAndFeel[] looks = UIManager.getAuxiliaryLookAndFeels();
//printLookAndFeel(looks);
} catch ( Exception e ) {
e.printStackTrace();
}
}
// private static void printLookAndFeel(LookAndFeel[] looks)
// {
//
// if ( looks != null){
// System.out.println("got " + looks.length + " lookAndFeels");
// for (LookAndFeel laf : looks){
// System.out.println(laf.getDescription());
// }
// } else {
// System.out.println("No other LookAndFeels found.");
// }
//
// }
}
| fionakim/biojava | biojava-structure-gui/src/main/java/org/biojava/nbio/structure/align/webstart/AligUIManager.java | Java | lgpl-2.1 | 2,143 |
/****************************************************************/
/* MOOSE - Multiphysics Object Oriented Simulation Environment */
/* */
/* All contents are licensed under LGPL V2.1 */
/* See LICENSE for full restrictions */
/****************************************************************/
#include "CrystalPlasticityStateVariable.h"
#include <fstream>
template <>
InputParameters
validParams<CrystalPlasticityStateVariable>()
{
InputParameters params = validParams<CrystalPlasticityUOBase>();
params.addParam<FileName>(
"state_variable_file_name",
"",
"Name of the file containing the initial values of slip system resistances");
MooseEnum intvar_read_options("file_input inline_input user_input", "inline_input");
params.addParam<MooseEnum>(
"intvar_read_type",
intvar_read_options,
"Read from options for initial value of internal variables: Default from .i file");
params.addParam<std::vector<unsigned int>>("groups",
"To group the initial values on different "
"slip systems 'format: [start end)', i.e.'0 "
"4 8 11' groups 0-3, 4-7 and 8-11 ");
params.addParam<std::vector<Real>>("group_values",
"The initial values correspoinding to each "
"group, i.e. '0.0 1.0 2.0' means 0-4 = 0.0, "
"4-8 = 1.0 and 8-12 = 2.0 ");
params.addParam<std::vector<std::string>>("uo_state_var_evol_rate_comp_name",
"Name of state variable evolution rate component "
"property: Same as state variable evolution rate "
"component user object specified in input file.");
params.addParam<Real>("zero", 0.0, "Numerical zero for interval variable");
params.addParam<std::vector<Real>>("scale_factor", "Scale factor of individual component.");
params.addClassDescription(
"Crystal plasticity state variable class. Override the virtual functions in your class");
return params;
}
CrystalPlasticityStateVariable::CrystalPlasticityStateVariable(const InputParameters & parameters)
: CrystalPlasticityUOBase(parameters),
_num_mat_state_var_evol_rate_comps(
parameters.get<std::vector<std::string>>("uo_state_var_evol_rate_comp_name").size()),
_mat_prop_state_var(getMaterialProperty<std::vector<Real>>(_name)),
_mat_prop_state_var_old(getMaterialPropertyOld<std::vector<Real>>(_name)),
_state_variable_file_name(getParam<FileName>("state_variable_file_name")),
_intvar_read_type(getParam<MooseEnum>("intvar_read_type")),
_groups(getParam<std::vector<unsigned int>>("groups")),
_group_values(getParam<std::vector<Real>>("group_values")),
_zero(getParam<Real>("zero")),
_scale_factor(getParam<std::vector<Real>>("scale_factor"))
{
if (_scale_factor.size() != _num_mat_state_var_evol_rate_comps)
mooseError("CrystalPlasticityStateVariable: Scale factor should be have the same size of "
"evolution rate components.");
_mat_prop_state_var_evol_rate_comps.resize(_num_mat_state_var_evol_rate_comps);
for (unsigned int i = 0; i < _num_mat_state_var_evol_rate_comps; ++i)
_mat_prop_state_var_evol_rate_comps[i] = &getMaterialProperty<std::vector<Real>>(
parameters.get<std::vector<std::string>>("uo_state_var_evol_rate_comp_name")[i]);
}
void
CrystalPlasticityStateVariable::initSlipSysProps(std::vector<Real> & val,
const Point & q_point) const
{
switch (_intvar_read_type)
{
case 0:
readInitialValueFromFile(val);
break;
case 1:
readInitialValueFromInline(val);
break;
case 2:
provideInitialValueByUser(val, q_point);
break;
default:
mooseError("CrystalPlasticityStateVariable: Read option for initial value of internal "
"variables is not supported.");
}
for (unsigned int i = 0; i < _variable_size; ++i)
if (val[i] <= 0.0)
mooseError("CrystalPlasticityStateVariable: Value of state variables ", i, " non positive");
}
void
CrystalPlasticityStateVariable::readInitialValueFromFile(std::vector<Real> & val) const
{
MooseUtils::checkFileReadable(_state_variable_file_name);
std::ifstream file;
file.open(_state_variable_file_name.c_str());
for (unsigned int i = 0; i < _variable_size; ++i)
if (!(file >> val[i]))
mooseError("Error CrystalPlasticityStateVariable: Premature end of state_variable file");
file.close();
}
void
CrystalPlasticityStateVariable::readInitialValueFromInline(std::vector<Real> & val) const
{
if (_groups.size() <= 0)
mooseError("CrystalPlasticityStateVariable: Error in reading initial state variable values: "
"Specify input in .i file or in state_variable file");
else if (_groups.size() != (_group_values.size() + 1))
mooseError(
"CrystalPlasticityStateVariable: The size of the groups and group_values does not match.");
for (unsigned int i = 0; i < _groups.size() - 1; ++i)
{
unsigned int is, ie;
is = _groups[i];
ie = _groups[i + 1] - 1;
if (is > ie)
mooseError("CrystalPlasticityStateVariable: Start index is = ",
is,
" should be greater than end index ie = ",
ie,
" in state variable read");
for (unsigned int j = is; j <= ie; ++j)
val[j] = _group_values[i];
}
}
void
CrystalPlasticityStateVariable::provideInitialValueByUser(std::vector<Real> & /*val*/,
const Point & /*q_point*/) const
{
mooseError("Error CrystalPlasticityStateVariable: User has to overwrite "
"'provideInitialValueByUser' function"
"in order to provide specific initial values based on quadrature point location.");
}
bool
CrystalPlasticityStateVariable::updateStateVariable(unsigned int qp,
Real dt,
std::vector<Real> & val) const
{
for (unsigned int i = 0; i < _variable_size; ++i)
{
val[i] = 0.0;
for (unsigned int j = 0; j < _num_mat_state_var_evol_rate_comps; j++)
val[i] += (*_mat_prop_state_var_evol_rate_comps[j])[qp][i] * dt * _scale_factor[j];
}
for (unsigned int i = 0; i < _variable_size; ++i)
{
if (_mat_prop_state_var_old[qp][i] < _zero && val[i] < 0.0)
val[i] = _mat_prop_state_var_old[qp][i];
else
val[i] = _mat_prop_state_var_old[qp][i] + val[i];
if (val[i] < 0.0)
return false;
}
return true;
}
| yipenggao/moose | modules/tensor_mechanics/src/userobjects/CrystalPlasticityStateVariable.C | C++ | lgpl-2.1 | 6,893 |
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org.reprap.utilities</FONT>
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Class FunctionTable</H2>
<PRE>
java.lang.Object
<IMG SRC="../../../resources/inherit.gif" ALT="extended by "><B>org.reprap.utilities.FunctionTable</B>
</PRE>
<HR>
<DL>
<DT><PRE> class <B>FunctionTable</B><DT>extends java.lang.Object</DL>
</PRE>
<P>
<DL>
<DT><B>Author:</B></DT>
<DD>adrian</DD>
</DL>
<HR>
<P>
<!-- =========== FIELD SUMMARY =========== -->
<A NAME="field_summary"><!-- --></A>
<TABLE BORDER="1" WIDTH="100%" CELLPADDING="3" CELLSPACING="0" SUMMARY="">
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<B>Field Summary</B></FONT></TH>
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<TR BGCOLOR="white" CLASS="TableRowColor">
<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE>(package private) boolean</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#allFalse">allFalse</A></B></CODE>
<BR>
</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE>(package private) boolean</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#allTrue">allTrue</A></B></CODE>
<BR>
</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE>(package private) java.util.List<<A HREF="../../../org/reprap/utilities/TableRow.html" title="class in org.reprap.utilities">TableRow</A>></CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#rows">rows</A></B></CODE>
<BR>
</TD>
</TR>
</TABLE>
<!-- ======== CONSTRUCTOR SUMMARY ======== -->
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<TABLE BORDER="1" WIDTH="100%" CELLPADDING="3" CELLSPACING="0" SUMMARY="">
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<B>Constructor Summary</B></FONT></TH>
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<TR BGCOLOR="white" CLASS="TableRowColor">
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#FunctionTable()">FunctionTable</A></B>()</CODE>
<BR>
</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#FunctionTable(org.reprap.utilities.BooleanExpression)">FunctionTable</A></B>(<A HREF="../../../org/reprap/utilities/BooleanExpression.html" title="class in org.reprap.utilities">BooleanExpression</A> b)</CODE>
<BR>
</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#FunctionTable(org.reprap.utilities.BooleanExpression, org.reprap.utilities.Variable, org.reprap.utilities.Variable, boolean)">FunctionTable</A></B>(<A HREF="../../../org/reprap/utilities/BooleanExpression.html" title="class in org.reprap.utilities">BooleanExpression</A> b,
<A HREF="../../../org/reprap/utilities/Variable.html" title="class in org.reprap.utilities">Variable</A> v,
<A HREF="../../../org/reprap/utilities/Variable.html" title="class in org.reprap.utilities">Variable</A> equal_v,
boolean opposite)</CODE>
<BR>
</TD>
</TR>
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<!-- ========== METHOD SUMMARY =========== -->
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<B>Method Summary</B></FONT></TH>
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<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE> void</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#addRow(org.reprap.utilities.Variable[], boolean)">addRow</A></B>(<A HREF="../../../org/reprap/utilities/Variable.html" title="class in org.reprap.utilities">Variable</A>[] v,
boolean b)</CODE>
<BR>
Add a new row to the function table</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE> boolean</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#allOnes()">allOnes</A></B>()</CODE>
<BR>
</TD>
</TR>
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<CODE> boolean</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#allZeros()">allZeros</A></B>()</CODE>
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</TD>
</TR>
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<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE> int</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#entries()">entries</A></B>()</CODE>
<BR>
</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE>(package private) static boolean</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#same(org.reprap.utilities.FunctionTable, org.reprap.utilities.FunctionTable)">same</A></B>(<A HREF="../../../org/reprap/utilities/FunctionTable.html" title="class in org.reprap.utilities">FunctionTable</A> a,
<A HREF="../../../org/reprap/utilities/FunctionTable.html" title="class in org.reprap.utilities">FunctionTable</A> b)</CODE>
<BR>
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<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE> void</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#tableCheck()">tableCheck</A></B>()</CODE>
<BR>
</TD>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD ALIGN="right" VALIGN="top" WIDTH="1%"><FONT SIZE="-1">
<CODE> java.lang.String</CODE></FONT></TD>
<TD><CODE><B><A HREF="../../../org/reprap/utilities/FunctionTable.html#toString()">toString</A></B>()</CODE>
<BR>
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<TABLE BORDER="1" WIDTH="100%" CELLPADDING="3" CELLSPACING="0" SUMMARY="">
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<TH ALIGN="left"><B>Methods inherited from class java.lang.Object</B></TH>
</TR>
<TR BGCOLOR="white" CLASS="TableRowColor">
<TD><CODE>clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait</CODE></TD>
</TR>
</TABLE>
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<!-- ============ FIELD DETAIL =========== -->
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<B>Field Detail</B></FONT></TH>
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<A NAME="rows"><!-- --></A><H3>
rows</H3>
<PRE>
java.util.List<<A HREF="../../../org/reprap/utilities/TableRow.html" title="class in org.reprap.utilities">TableRow</A>> <B>rows</B></PRE>
<DL>
<DL>
</DL>
</DL>
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<A NAME="allFalse"><!-- --></A><H3>
allFalse</H3>
<PRE>
boolean <B>allFalse</B></PRE>
<DL>
<DL>
</DL>
</DL>
<HR>
<A NAME="allTrue"><!-- --></A><H3>
allTrue</H3>
<PRE>
boolean <B>allTrue</B></PRE>
<DL>
<DL>
</DL>
</DL>
<!-- ========= CONSTRUCTOR DETAIL ======== -->
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<A NAME="FunctionTable()"><!-- --></A><H3>
FunctionTable</H3>
<PRE>
public <B>FunctionTable</B>()</PRE>
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</DL>
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<A NAME="FunctionTable(org.reprap.utilities.BooleanExpression)"><!-- --></A><H3>
FunctionTable</H3>
<PRE>
public <B>FunctionTable</B>(<A HREF="../../../org/reprap/utilities/BooleanExpression.html" title="class in org.reprap.utilities">BooleanExpression</A> b)</PRE>
<DL>
<DL>
<DT><B>Parameters:</B><DD><CODE>b</CODE> - </DL>
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<A NAME="FunctionTable(org.reprap.utilities.BooleanExpression, org.reprap.utilities.Variable, org.reprap.utilities.Variable, boolean)"><!-- --></A><H3>
FunctionTable</H3>
<PRE>
public <B>FunctionTable</B>(<A HREF="../../../org/reprap/utilities/BooleanExpression.html" title="class in org.reprap.utilities">BooleanExpression</A> b,
<A HREF="../../../org/reprap/utilities/Variable.html" title="class in org.reprap.utilities">Variable</A> v,
<A HREF="../../../org/reprap/utilities/Variable.html" title="class in org.reprap.utilities">Variable</A> equal_v,
boolean opposite)</PRE>
<DL>
<DL>
<DT><B>Parameters:</B><DD><CODE>b</CODE> - <DD><CODE>a</CODE> - <DD><CODE>equal_a</CODE> - </DL>
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<A NAME="addRow(org.reprap.utilities.Variable[], boolean)"><!-- --></A><H3>
addRow</H3>
<PRE>
public void <B>addRow</B>(<A HREF="../../../org/reprap/utilities/Variable.html" title="class in org.reprap.utilities">Variable</A>[] v,
boolean b)</PRE>
<DL>
<DD>Add a new row to the function table
<P>
<DD><DL>
<DT><B>Parameters:</B><DD><CODE>v</CODE> - <DD><CODE>b</CODE> - </DL>
</DD>
</DL>
<HR>
<A NAME="tableCheck()"><!-- --></A><H3>
tableCheck</H3>
<PRE>
public void <B>tableCheck</B>()</PRE>
<DL>
<DD><DL>
</DL>
</DD>
</DL>
<HR>
<A NAME="allOnes()"><!-- --></A><H3>
allOnes</H3>
<PRE>
public boolean <B>allOnes</B>()</PRE>
<DL>
<DD><DL>
</DL>
</DD>
</DL>
<HR>
<A NAME="allZeros()"><!-- --></A><H3>
allZeros</H3>
<PRE>
public boolean <B>allZeros</B>()</PRE>
<DL>
<DD><DL>
</DL>
</DD>
</DL>
<HR>
<A NAME="entries()"><!-- --></A><H3>
entries</H3>
<PRE>
public int <B>entries</B>()</PRE>
<DL>
<DD><DL>
</DL>
</DD>
</DL>
<HR>
<A NAME="same(org.reprap.utilities.FunctionTable, org.reprap.utilities.FunctionTable)"><!-- --></A><H3>
same</H3>
<PRE>
static boolean <B>same</B>(<A HREF="../../../org/reprap/utilities/FunctionTable.html" title="class in org.reprap.utilities">FunctionTable</A> a,
<A HREF="../../../org/reprap/utilities/FunctionTable.html" title="class in org.reprap.utilities">FunctionTable</A> b)</PRE>
<DL>
<DD><DL>
<DT><B>Parameters:</B><DD><CODE>a</CODE> - <DD><CODE>b</CODE> -
<DT><B>Returns:</B><DD></DL>
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<A NAME="toString()"><!-- --></A><H3>
toString</H3>
<PRE>
public java.lang.String <B>toString</B>()</PRE>
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<DD><DL>
<DT><B>Overrides:</B><DD><CODE>toString</CODE> in class <CODE>java.lang.Object</CODE></DL>
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| alex1818/host | doc/org/reprap/utilities/FunctionTable.html | HTML | lgpl-2.1 | 18,480 |
/**********************************************************************
* Minolta Dimage V digital camera communication library *
* Copyright © 2000,2001 Gus Hartmann *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License as *
* published by the Free Software Foundation; either version 2 of *
* the License, or (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public *
* License along with this program; if not, write to the Free *
* Software Foundation, Inc., 59 Temple Place, Suite 330, *
* Boston, MA 02111-1307 USA *
* *
**********************************************************************/
/* $Id$ */
#include "config.h"
#include "dimagev.h"
#define GP_MODULE "dimagev"
/* This is the parent function, who calls most of the functions below.
It returns GP_ERROR if it cannot get the camera data, and GP_OK otherwise.
The subroutines will print out more detained information should they fail.
*/
int dimagev_get_camera_data(dimagev_t *dimagev) {
dimagev_packet *p, *raw;
unsigned char char_buffer;
/* Check the device. */
if ( dimagev->dev == NULL ) {
GP_DEBUG( "dimagev_get_camera_data::device not valid");
return GP_ERROR_BAD_PARAMETERS;
}
/* Let's say hello and get the current status. */
if ( ( p = dimagev_make_packet(DIMAGEV_GET_DATA, 1, 0)) == NULL ) {
GP_DEBUG( "dimagev_get_camera_data::unable to allocate packet");
return GP_ERROR_NO_MEMORY;
}
if ( gp_port_write(dimagev->dev, (char*)p->buffer, p->length) < GP_OK ) {
GP_DEBUG( "dimagev_get_camera_data::unable to write packet");
free(p);
return GP_ERROR_IO;
} else if ( gp_port_read(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_get_camera_data::no response from camera");
free(p);
return GP_ERROR_IO;
}
free(p);
switch ( char_buffer ) {
case DIMAGEV_ACK:
break;
case DIMAGEV_NAK:
GP_DEBUG( "dimagev_get_camera_data::camera did not acknowledge transmission");
return GP_ERROR_IO;
case DIMAGEV_CAN:
GP_DEBUG( "dimagev_get_camera_data::camera cancels transmission");
return GP_ERROR_IO;
default:
GP_DEBUG( "dimagev_get_camera_data::camera responded with unknown value %x", char_buffer);
return GP_ERROR_IO;
}
if ( ( p = dimagev_read_packet(dimagev) ) == NULL ) {
GP_DEBUG( "dimagev_get_camera_data::unable to read packet");
return GP_ERROR_IO;
}
char_buffer = DIMAGEV_EOT;
if ( gp_port_write(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_get_camera_data::unable to send EOT");
free(p);
return GP_ERROR_IO;
}
if ( gp_port_read(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_get_camera_data::no response from camera");
free(p);
return GP_ERROR_IO;
}
switch ( char_buffer ) {
case DIMAGEV_ACK:
break;
case DIMAGEV_NAK:
GP_DEBUG( "dimagev_get_camera_data::camera did not acknowledge transmission");
free(p);
return GP_ERROR_IO;
case DIMAGEV_CAN:
GP_DEBUG( "dimagev_get_camera_data::camera cancels transmission");
free(p);
return GP_ERROR_IO;
default:
GP_DEBUG( "dimagev_get_camera_data::camera responded with unknown value %x", char_buffer);
free(p);
return GP_ERROR_IO;
}
if ( ( raw = dimagev_strip_packet(p) ) == NULL ) {
GP_DEBUG( "dimagev_get_camera_data::unable to strip data packet");
free(p);
return GP_ERROR;
}
if ( ( dimagev->data = dimagev_import_camera_data(raw->buffer)) == NULL ) {
GP_DEBUG( "dimagev_get_camera_data::unable to read camera data");
free(raw);
free(p);
return GP_ERROR;
}
/* Sure it *should* get freed automagically, but why take the risk? */
free(p);
free(raw);
return GP_OK;
}
/* This function sends the contents of a dimagev_data_t to the current camera.
This allows many changes to be made (e.g. entering host mode and record
mode) while only sending a single set_data command.
*/
int dimagev_send_data(dimagev_t *dimagev) {
dimagev_packet *p;
unsigned char *export_data, char_buffer;
if ( dimagev == NULL ) {
GP_DEBUG( "dimagev_send_data::unable to use NULL dimagev_t");
return GP_ERROR_BAD_PARAMETERS;
}
if ( ( export_data = dimagev_export_camera_data(dimagev->data) ) == NULL ) {
GP_DEBUG( "dimagev_send_data::unable to export camera data");
return GP_ERROR;
}
dimagev_dump_camera_data(dimagev->data);
if ( ( p = dimagev_make_packet(DIMAGEV_SET_DATA, 1, 0) ) == NULL ) {
GP_DEBUG( "dimagev_send_data::unable to create set_data packet");
free(export_data);
return GP_ERROR_NO_MEMORY;
}
if ( gp_port_write(dimagev->dev, (char*)p->buffer, p->length) < GP_OK ) {
GP_DEBUG( "dimagev_send_data::unable to send set_data packet");
free(p);
free(export_data);
return GP_ERROR_IO;
} else if ( gp_port_read(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_send_data::no response from camera - trying to send NAK");
free(p);
free(export_data);
return GP_ERROR_IO;
}
free(p);
switch ( char_buffer ) {
case DIMAGEV_ACK:
break;
case DIMAGEV_NAK:
GP_DEBUG( "dimagev_send_data::camera did not acknowledge transmission");
free(export_data);
return GP_ERROR_IO;
case DIMAGEV_CAN:
GP_DEBUG( "dimagev_send_data::camera cancels transmission");
free(export_data);
return GP_ERROR_IO;
default:
GP_DEBUG( "dimagev_send_data::camera responded with unknown value %x", char_buffer);
free(export_data);
return GP_ERROR_IO;
}
if ( ( p = dimagev_make_packet(export_data, 9, 1) ) == NULL ) {
GP_DEBUG( "dimagev_send_data::unable to create set_data packet");
free(export_data);
return GP_ERROR_NO_MEMORY;
}
free(export_data);
if ( gp_port_write(dimagev->dev, (char*)p->buffer, p->length) < GP_OK ) {
GP_DEBUG( "dimagev_send_data::unable to send data packet");
free(p);
return GP_ERROR_IO;
}
free(p);
if ( gp_port_read(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_send_data::no response from camera");
return GP_ERROR_IO;
}
switch ( char_buffer ) {
case DIMAGEV_ACK:
break;
case DIMAGEV_NAK:
GP_DEBUG( "dimagev_send_data::camera did not acknowledge transmission");
return GP_ERROR_IO;
case DIMAGEV_CAN:
GP_DEBUG( "dimagev_send_data::camera cancels transmission");
return GP_ERROR_IO;
default:
GP_DEBUG( "dimagev_send_data::camera responded with unknown value %x", char_buffer);
return GP_ERROR_IO;
}
char_buffer = DIMAGEV_EOT;
if ( gp_port_write(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_send_data::unable to send EOT");
return GP_ERROR_IO;
}
if ( gp_port_read(dimagev->dev, (char*)&char_buffer, 1) < GP_OK ) {
GP_DEBUG( "dimagev_send_data::no response from camera");
return GP_ERROR_IO;
}
switch ( char_buffer ) {
case DIMAGEV_ACK:
break;
case DIMAGEV_NAK:
GP_DEBUG( "dimagev_send_data::camera did not acknowledge transmission");
return GP_ERROR_IO;
case DIMAGEV_CAN:
GP_DEBUG( "dimagev_send_data::camera cancels transmission");
return GP_ERROR_IO;
default:
GP_DEBUG( "dimagev_send_data::camera responded with unknown value %x", char_buffer);
return GP_ERROR_IO;
}
if ( sleep(3) != 0 ) {
GP_DEBUG( "dimagev_send_data::sleep() returned non-zero value");
}
return GP_OK;
}
/* This function populates and retuens a dimagev_data_t with the values
contained inside an array of bytes, as returned by the Dimage V. See
the description of these fields in the appropriate header file for
more information on the bit-packing done here.
*/
dimagev_data_t *dimagev_import_camera_data(unsigned char *raw_data) {
dimagev_data_t *processed_data;
if ( raw_data == NULL ) {
return NULL;
}
if ( ( processed_data = malloc(sizeof(dimagev_data_t)) ) == NULL ) {
return NULL;
}
/* They really pack those bit fields. */
processed_data->host_mode = ( raw_data[0] & 0x80) >> 7;
processed_data->exposure_valid = (raw_data[0] & 0x40 ) >> 6;
processed_data->date_valid = (raw_data[0] & 0x20 ) >> 5;
processed_data->self_timer_mode = (raw_data[0] & 0x10 ) >> 4;
processed_data->flash_mode = ( raw_data[0] & 0x0C ) >> 2;
processed_data->quality_setting = ( raw_data[0] & 0x02 ) >> 1;
processed_data->play_rec_mode = (raw_data[0] & 0x01 );
processed_data->year = dimagev_bcd_to_decimal(raw_data[1]);
processed_data->month = dimagev_bcd_to_decimal(raw_data[2]);
processed_data->day = dimagev_bcd_to_decimal(raw_data[3]);
processed_data->hour = dimagev_bcd_to_decimal(raw_data[4]);
processed_data->minute = dimagev_bcd_to_decimal(raw_data[5]);
processed_data->second = dimagev_bcd_to_decimal(raw_data[6]);
processed_data->exposure_correction = raw_data[7];
processed_data->valid = ( raw_data[8] & 0x80) >> 7;
processed_data->id_number = ( raw_data[8] & 0x7F);
return processed_data;
}
unsigned char *dimagev_export_camera_data(dimagev_data_t *good_data) {
unsigned char *export_data;
if ( ( export_data = malloc(9) ) == NULL ) {
perror("dimagev_export_camera_data::unable to allocate buffer");
return NULL;
}
export_data[0] = (unsigned char) 0;
export_data[0] = export_data[0] | ( ( ( good_data->host_mode ) << 7 ) & 0x80 );
export_data[0] = export_data[0] | ( ( ( good_data->exposure_valid ) << 6 ) & 0x40 );
export_data[0] = export_data[0] | ( ( ( good_data->date_valid ) << 5 ) & 0x20 );
export_data[0] = export_data[0] | ( ( ( good_data->self_timer_mode ) << 4 ) & 0x10 );
export_data[0] = export_data[0] | ( ( ( good_data->flash_mode ) << 2 ) & 0x0C );
export_data[0] = export_data[0] | ( ( ( good_data->quality_setting ) << 1 ) & 0x02 );
export_data[0] = export_data[0] | ( ( ( good_data->play_rec_mode )) & 0x01 );
export_data[1] = (unsigned char) 0;
export_data[1] = dimagev_decimal_to_bcd(good_data->year);
export_data[2] = (unsigned char) 0;
export_data[2] = dimagev_decimal_to_bcd(good_data->month);
export_data[3] = (unsigned char) 0;
export_data[3] = dimagev_decimal_to_bcd(good_data->day);
export_data[4] = (unsigned char) 0;
export_data[4] = dimagev_decimal_to_bcd(good_data->hour);
export_data[5] = (unsigned char) 0;
export_data[5] = dimagev_decimal_to_bcd(good_data->minute);
export_data[6] = (unsigned char) 0;
export_data[6] = dimagev_decimal_to_bcd(good_data->second);
export_data[7] = (unsigned char) 0;
export_data[7] = good_data->exposure_correction;
export_data[8] = (unsigned char) 0;
export_data[8] = export_data[8] & ( ( ( good_data->valid ) << 7 ) & 0x80 );
export_data[8] = export_data[8] & ( ( ( good_data->id_number ) ) & 0x7F );
return export_data;
}
void dimagev_dump_camera_data(dimagev_data_t *data) {
GP_DEBUG( "========= Begin Camera Data =========");
GP_DEBUG( "Host mode: %s ( %d )", data->host_mode != (unsigned char) 0 ? "Host mode" : "Camera mode", data->host_mode);
GP_DEBUG( "Exposure valid: %s ( %d )", data->exposure_valid != (unsigned char) 0 ? "Valid" : "Not Valid", data->exposure_valid);
GP_DEBUG( "Exposure correction: %d", (signed char)data->exposure_correction);
GP_DEBUG( "Date valid: %s ( %d )", data->date_valid != (unsigned char) 0 ? "Valid" : "Not Valid", data->exposure_valid);
GP_DEBUG( "Self timer mode: %s ( %d )", data->self_timer_mode != (unsigned char) 0 ? "Yes" : "No", data->self_timer_mode);
GP_DEBUG( "Flash mode: ");
switch ( data->flash_mode ) {
case 0:
GP_DEBUG( "\tAuto ( 0 )");
break;
case 1:
GP_DEBUG( "\tForce Flash ( 1 )");
break;
case 2:
GP_DEBUG( "\tProhibit Flash ( 2 )");
break;
default:
GP_DEBUG( "\tInvalid mode for flash ( %d )", data->flash_mode);
break;
}
GP_DEBUG( "Quality mode: %s ( %d )", data->quality_setting ? "High" : "Low", data->quality_setting);
GP_DEBUG( "Play or Record mode: %s ( %d )", data->play_rec_mode != (unsigned char) 0 ? "Record" : "Play", data->play_rec_mode);
GP_DEBUG( "Date: %02d/%02d/%02d %02d:%02d:%02d", data->year, data->month, data->day, data->hour, data->minute, data->second);
GP_DEBUG( "Card ID Valid: %s ( %d )", data->valid != (unsigned char) 0 ? "Valid" : "Invalid", data->valid);
GP_DEBUG( "Card ID Data: %02x", data->id_number);
GP_DEBUG( "========== End Camera Data ==========");
return;
}
/* This function gets the current system time, sets the contents of the current
dimagev->data struct appropriately, and then sends the data.
*/
int dimagev_set_date(dimagev_t *dimagev) {
struct tm *this_time;
time_t now;
if ( dimagev == NULL ) {
return GP_ERROR_BAD_PARAMETERS;
}
if ( ( now = time(NULL) ) < 0 ) {
GP_DEBUG( "dimagev_set_date::unable to get system time");
return GP_ERROR;
}
if ( ( this_time = localtime(&now) ) == NULL ) {
GP_DEBUG( "dimagev_set_date::unable to convert system time to local time");
return GP_ERROR;
}
GP_DEBUG( "Setting clock to %02d/%02d/%02d %02d:%02d:%02d", this_time->tm_year % 100, ( this_time->tm_mon + 1 ), this_time->tm_mday, this_time->tm_hour, this_time->tm_min, this_time->tm_sec);
dimagev->data->date_valid = (unsigned char) 1;
dimagev->data->year = (unsigned char) ( this_time->tm_year % 100 );
dimagev->data->month = (unsigned char) ( this_time->tm_mon + 1 );
dimagev->data->day = (unsigned char) this_time->tm_mday;
dimagev->data->hour = (unsigned char) this_time->tm_hour;
dimagev->data->minute = (unsigned char) this_time->tm_min;
dimagev->data->second = (unsigned char) this_time->tm_sec;
if ( dimagev_send_data(dimagev) < GP_OK ) {
GP_DEBUG( "dimagev_set_date::unable to set time");
return GP_ERROR_IO;
}
/* So we don't set this date again later by mistake. */
dimagev->data->date_valid = (unsigned char) 0;
if ( dimagev_send_data(dimagev) < GP_OK ) {
GP_DEBUG( "dimagev_set_date::unable to set time");
return GP_ERROR_IO;
}
return GP_OK;
}
| Asofa/libgphoto2 | camlibs/minolta/dimagev/data.c | C | lgpl-2.1 | 14,399 |
/* Swfdec
* Copyright (C) 2007 Benjamin Otte <[email protected]>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301 USA
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <string.h>
#include "swfdec_ringbuffer.h"
SwfdecRingBuffer *
swfdec_ring_buffer_new (guint element_size, guint size)
{
SwfdecRingBuffer *buffer;
g_return_val_if_fail (element_size > 0, NULL);
g_return_val_if_fail (size > 1, NULL);
buffer = g_new0 (SwfdecRingBuffer, 1);
buffer->element_size = element_size;
buffer->size = size;
buffer->data = g_malloc (element_size * size);
return buffer;
}
void
swfdec_ring_buffer_free (SwfdecRingBuffer *buffer)
{
g_return_if_fail (buffer != NULL);
g_free (buffer->data);
g_free (buffer);
}
guint
swfdec_ring_buffer_get_size (SwfdecRingBuffer *buffer)
{
g_return_val_if_fail (buffer != NULL, 0);
return buffer->size;
}
#define GET_ELEMENT(buffer,idx) (buffer->data + buffer->element_size * (idx))
void
swfdec_ring_buffer_set_size (SwfdecRingBuffer *buffer, guint new_size)
{
g_return_if_fail (buffer != NULL);
g_return_if_fail (buffer->size < new_size);
buffer->data = g_realloc (buffer->data, buffer->element_size * new_size);
if (buffer->tail <= buffer->head && buffer->n_elements) {
memmove (GET_ELEMENT (buffer, buffer->head + new_size - buffer->size),
GET_ELEMENT (buffer, buffer->head),
buffer->element_size * (buffer->size - buffer->head));
buffer->head += new_size - buffer->size;
}
buffer->size = new_size;
}
guint
swfdec_ring_buffer_get_n_elements (SwfdecRingBuffer *buffer)
{
g_return_val_if_fail (buffer != NULL, 0);
return buffer->n_elements;
}
gpointer
swfdec_ring_buffer_push (SwfdecRingBuffer *buffer)
{
gpointer ret;
g_return_val_if_fail (buffer != NULL, NULL);
if (buffer->n_elements == buffer->size)
return NULL;
ret = GET_ELEMENT (buffer, buffer->tail);
buffer->tail = (buffer->tail + 1) % buffer->size;
buffer->n_elements++;
return ret;
}
gpointer
swfdec_ring_buffer_pop (SwfdecRingBuffer *buffer)
{
gpointer ret;
g_return_val_if_fail (buffer != NULL, NULL);
if (buffer->n_elements == 0)
return NULL;
ret = GET_ELEMENT (buffer, buffer->head);
buffer->head = (buffer->head + 1) % buffer->size;
buffer->n_elements--;
return ret;
}
gpointer
swfdec_ring_buffer_peek_nth (SwfdecRingBuffer *buffer, guint id)
{
g_return_val_if_fail (buffer != NULL, NULL);
g_return_val_if_fail (id < buffer->n_elements, NULL);
id = (buffer->head + id) % buffer->size;
return GET_ELEMENT (buffer, id);
}
| freedesktop-unofficial-mirror/swfdec__swfdec | swfdec/swfdec_ringbuffer.c | C | lgpl-2.1 | 3,233 |
#!/usr/bin/env python
# -*- coding: utf-8 -*-
#
# driver libcaca test drivers program
# Copyright (c) 2010 Alex Foulon <[email protected]>
#
# This file is a Python port of "examples/driver.c"
# which is:
# Copyright (c) 2006-2010 Sam Hocevar <[email protected]>
# All Rights Reserverd
#
# This library is free software. It comes without any warranty, to
# the extent permitted by applicable law. You can redistribute it
# and/or modify it under the terms of the Do What the Fuck You Want
# to Public License, Version 2, as published by Sam Hocevar. See
# http://www.wtfpl.net/ for more details.
#
import sys
import caca
from caca.canvas import Canvas, CanvasError
from caca.display import Display, DisplayError, Event
def main():
""" Main function. """
lst = caca.get_display_driver_list()
cur = 0
try:
cv = Canvas(0, 0)
dp = Display(cv)
except (CanvasError, DisplayError) as err:
sys.stderr.write("%s\n" % err)
sys.exit(127)
cv.set_color_ansi(caca.COLOR_WHITE, caca.COLOR_BLACK)
while True:
cv.put_str(1, 0, "Available drivers:")
cur_driver = dp.get_driver()
n = 0
for driver, desc in lst:
if driver == cur_driver:
cv.put_str(2, n + 2, "%s %s (%s)" % ('*', driver, desc))
else:
cv.put_str(2, n + 2, "%s %s (%s)" % (' ', driver, desc))
n += 1
cv.put_str(2, n + 3, "Switching driver in 5 seconds")
dp.refresh()
if dp.get_event(caca.EVENT_KEY_PRESS, Event(), 5000000):
break
cur += 1
if cur < len(lst) and lst[cur][0] == "raw":
cur += 1
if cur >= len(lst):
cur = 0
dp.set_driver(lst[cur][0])
if __name__ == "__main__":
main()
| mcfiredrill/libcaca-old | python/examples/driver.py | Python | lgpl-2.1 | 1,812 |
/*
* This library is part of OpenCms -
* the Open Source Content Management System
*
* Copyright (c) Alkacon Software GmbH (http://www.alkacon.com)
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* For further information about Alkacon Software, please see the
* company website: http://www.alkacon.com
*
* For further information about OpenCms, please see the
* project website: http://www.opencms.org
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
package org.opencms.ade.containerpage.client.ui;
import org.opencms.gwt.client.ui.CmsList;
import org.opencms.gwt.client.ui.CmsListItem;
import org.opencms.gwt.client.ui.CmsScrollPanel;
import com.google.gwt.user.client.ui.Composite;
/**
* Base class for clipboard tabs.<p>
*/
public abstract class A_CmsClipboardTab extends Composite {
/**
* Adds an item to the list.<p>
*
* @param item the item to add
*/
public void addListItem(CmsListItem item) {
getList().add(item);
}
/**
* Clears the list.<p>
*/
public void clearList() {
getList().clear();
}
/**
* Returns the item list.<p>
*
* @return the item list
*/
public abstract CmsList<CmsListItem> getList();
/**
* Returns the height required by the tab content.<p>
*
* @return the tab content height
*/
public int getRequiredHeight() {
return getList().getElement().getClientHeight() + 17;
}
/**
* Returns the scroll panel.<p>
*
* @return the scroll panel
*/
public abstract CmsScrollPanel getScrollPanel();
/**
* Replaces the item with the same id if present.<p>
*
* @param item the new item
*/
public void replaceItem(CmsListItem item) {
CmsListItem oldItem = getList().getItem(item.getId());
if (oldItem != null) {
int index = getList().getWidgetIndex(oldItem);
getList().removeItem(oldItem);
if (index >= getList().getWidgetCount()) {
getList().addItem(item);
} else {
getList().insertItem(item, index);
}
}
}
}
| victos/opencms-core | src-gwt/org/opencms/ade/containerpage/client/ui/A_CmsClipboardTab.java | Java | lgpl-2.1 | 2,806 |
/*
* genetik - Genetic Kernel Library
*
* Copyright (C) 2006 Alessandro Bahgat Shehata, Daniele Castagna
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* Alessandro Bahgat Shehata - ale (DOT) bahgat (AT) gmail (DOT) com
* Daniele Castagna - daniele (DOT) castagna (AT) gmail (DOT) com
*
*/
/*!
@file src/gp/st/IndividualFactory.h
*/
#ifndef GENETIK_GP_ST_INDIVIDUALFACTORY
#define GENETIK_GP_ST_INDIVIDUALFACTORY
#include "../IndividualFactory.h"
namespace genetiK
{
namespace gp
{
namespace st
{
typedef unsigned char GeneType;
/*! @brief IndividualFactory: GP-ST-specific %IndividualFactory.
This class extends the genetiK::gp::Individual class. It represents an individual as a
typed gene tree.
@ingroup st
*/
class IndividualFactory : public gp::IndividualFactory
{
private:
GeneType rootType;
GeneType nextGeneType;
unsigned char maxHeight;
public:
/*! @brief Creates a factory that creates Individual objects for the Strongly Typed Genetic Programming
@param maxHeight max height of the tree
@param treeInitialization Tree initialization method: FULL or GROW
@param rootType the type of the root gene
@see ETreeInitialization
@see gp::IndividualFactory
*/
IndividualFactory(unsigned char maxHeight,gp::ETreeInitialization treeInitialization,GeneType rootType);
/*! @brief Destructor
*/
virtual ~IndividualFactory();
/*! @brief abstract generate function
This function must be extended by sublcasses to generate appropriate individuals.
@return a new Individual
*/
genetiK::Individual* generate()=0;
/*! @brief return the type of the next gene to be created
Specifies the type of the next gene to be created.
@return the type of the next gene
@see generateGene(EGenerateGeneFlags flags)
*/
GeneType getNextType() const{ return nextGeneType; }
/*! @brief set the type of the next gene to be created
Specifies the next type of the gene to be created.
@param nextGeneType the type of the next gene
@see generateGene(EGenerateGeneFlags flags)
*/
void setNextType(const GeneType nextGeneType) { this->nextGeneType = nextGeneType; }
/*! @brief generate a new branch
This function generate a new branch.
@param height the max height of the new branch
@param treeInitialization GROW or FULL
@return the new branch
*/
virtual gp::Gene* generateBranch(unsigned char height,ETreeInitialization treeInitialization);
protected:
/*! @brief abstract generate gene function
This function must be extended by sublcasses to generate appropriate gene.
This function returns a random gene obeying the rules specified in flags and the nextGeneType returning a new random gene of type getNextType().
If the new created gene doesn't satisfy the specified rules, an Exception will be thrown
@param flags TERMINAL for a gene with arity equal to 1 and FUNCTION for a gene with greter or equal to 1. If both the flags are specified, you should return a random gene (TERMINAL or FUNCTION)
@return a random gene
@see getNextType();
*/
virtual gp::Gene* generateGene(EGenerateGeneFlags flags)=0;
/*! @brief generate a new tree
It simply calls the generateBranch with the appropriate height and root type.
@return the new tree
@see generateBranch
*/
virtual gp::Gene* generateTree();
/*!@brief populate a node generating all its subbranches
This method generates all branchRoot subbranches.
@param branchRoot the gene to be populated
@param height the max height of the subbranches
*/
virtual void generateChildren(gp::Gene* branchRoot, unsigned char height);
};
}
}
}
#endif
| abahgat/genetik | src/gp/st/IndividualFactory.h | C | lgpl-2.1 | 4,338 |
/*
* This library is part of OpenCms -
* the Open Source Content Management System
*
* Copyright (c) Alkacon Software GmbH (http://www.alkacon.com)
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* For further information about Alkacon Software GmbH, please see the
* company website: http://www.alkacon.com
*
* For further information about OpenCms, please see the
* project website: http://www.opencms.org
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
package org.opencms.widgets;
import org.opencms.file.CmsObject;
import org.opencms.i18n.CmsEncoder;
import org.opencms.workplace.galleries.A_CmsAjaxGallery;
/**
* Base class for non-editable "HTML display only" widget implementations.<p>
*
* @since 6.0.0
*/
public abstract class A_CmsHtmlGalleryWidget extends A_CmsGalleryWidget {
/**
* Creates a html gallery widget with the specified combo options.<p>
*
* @param configuration the configuration (possible options) for the combo box
*/
public A_CmsHtmlGalleryWidget(String configuration) {
super(configuration);
}
/**
* Creates a new html gallery widget.<p>
*/
protected A_CmsHtmlGalleryWidget() {
// empty constructor is required for class registration
this("");
}
/**
* @see org.opencms.widgets.I_CmsWidget#getDialogWidget(org.opencms.file.CmsObject, org.opencms.widgets.I_CmsWidgetDialog, org.opencms.widgets.I_CmsWidgetParameter)
*/
@Override
public String getDialogWidget(CmsObject cms, I_CmsWidgetDialog widgetDialog, I_CmsWidgetParameter param) {
String id = param.getId();
long idHash = id.hashCode();
if (idHash < 0) {
// negative hash codes will not work as JS variable names, so convert them
idHash = -idHash;
// add 2^32 to the value to ensure that it is unique
idHash += 4294967296L;
}
StringBuffer result = new StringBuffer(128);
result.append("<td class=\"xmlTd\">");
result.append("<table border=\"0\" cellpadding=\"0\" cellspacing=\"0\" class=\"maxwidth\">");
result.append("<input type=\"hidden\" value=\"");
String fieldValue = param.getStringValue(cms);
result.append(CmsEncoder.escapeXml(fieldValue));
result.append("\" name=\"");
result.append(id);
result.append("\" id=\"");
result.append(id);
result.append("\">");
result.append("<tr><td style=\"width: 100%;\">");
// note that using "xmlHtmlGallery" here is ok since this is the formatting display area which is identical
// for all widgets based on this class
result.append("<div class=\"xmlHtmlGallery\" unselectable=\"on\" id=\"");
result.append(getNameLower());
result.append(".");
result.append(id);
result.append("\"><div>");
result.append("</td>");
result.append(widgetDialog.dialogHorizontalSpacer(10));
result.append(
"<td><table class=\"editorbuttonbackground\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\"><tr>");
result.append(
widgetDialog.button(
"javascript:open"
+ getNameUpper()
+ "Gallery('"
+ A_CmsAjaxGallery.MODE_WIDGET
+ "', '"
+ id
+ "' , '"
+ idHash
+ "');",
null,
getNameLower() + "gallery",
Messages.getButtonName(getNameLower()),
widgetDialog.getButtonStyle()));
// reset button
result.append(
widgetDialog.button(
"javascript:reset" + getNameUpper() + "Gallery('" + id + "');",
null,
"erase",
Messages.GUI_BUTTON_ERASE_0,
widgetDialog.getButtonStyle()));
result.append("</tr></table>");
result.append("</td></tr>");
result.append("<script type=\"text/javascript\">check");
result.append(getNameUpper());
result.append("Content('");
result.append(id);
result.append("');</script>");
result.append("</table>");
result.append("</td>");
// reads the configuration String for this widget
CmsGalleryWidgetConfiguration configuration = new CmsGalleryWidgetConfiguration(
cms,
widgetDialog.getMessages(),
param,
getConfiguration());
result.append("\n<script type=\"text/javascript\">");
result.append("\nvar startupFolder").append(idHash).append(" = \"").append(configuration.getStartup()).append(
"\";");
result.append("\nvar startupType").append(idHash).append(" = \"").append(configuration.getType()).append("\";");
result.append("\n</script>");
return result.toString();
}
/**
* @see org.opencms.widgets.I_CmsADEWidget#getWidgetName()
*/
@Override
public String getWidgetName() {
return A_CmsHtmlGalleryWidget.class.getName();
}
/**
* @see org.opencms.widgets.A_CmsGalleryWidget#showPreview(java.lang.String)
*/
@Override
public boolean showPreview(String value) {
// not required for HTML display galleries
return false;
}
} | victos/opencms-core | src/org/opencms/widgets/A_CmsHtmlGalleryWidget.java | Java | lgpl-2.1 | 6,021 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.9.1"/>
<title>Xerces-C++: XMLValidator.hpp File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
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<div id="titlearea">
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<tbody>
<tr style="height: 56px;">
<td style="padding-left: 0.5em;">
<div id="projectname">Xerces-C++
 <span id="projectnumber">3.1.2</span>
</div>
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<li class="navelem"><a class="el" href="dir_901b4356d5f32ee418b4c714d07fb65a.html">src</a></li><li class="navelem"><a class="el" href="dir_477226ead712f319998d821c029f7620.html">xercesc</a></li><li class="navelem"><a class="el" href="dir_41aef2f7a87f1ae87976cc1bb7e908ff.html">framework</a></li> </ul>
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<a href="#nested-classes">Classes</a> </div>
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<div class="contents">
<p><a href="XMLValidator_8hpp_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Classes</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">class  </td><td class="memItemRight" valign="bottom"><a class="el" href="classXMLValidator.html">XMLValidator</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">This abstract class provides the interface for all validators. <a href="classXMLValidator.html#details">More...</a><br /></td></tr>
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| kctan0805/vdpm | share/xercesc/xerces-c-3.1.2/doc/html/apiDocs-3/XMLValidator_8hpp.html | HTML | lgpl-2.1 | 3,274 |
##############################################################################
# Copyright (c) 2013-2017, Lawrence Livermore National Security, LLC.
# Produced at the Lawrence Livermore National Laboratory.
#
# This file is part of Spack.
# Created by Todd Gamblin, [email protected], All rights reserved.
# LLNL-CODE-647188
#
# For details, see https://github.com/llnl/spack
# Please also see the NOTICE and LICENSE files for our notice and the LGPL.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License (as
# published by the Free Software Foundation) version 2.1, February 1999.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the IMPLIED WARRANTY OF
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the terms and
# conditions of the GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
##############################################################################
from spack.architecture import Platform, Target
from spack.architecture import OperatingSystem as OS
class Test(Platform):
priority = 1000000
front_end = 'x86_32'
back_end = 'x86_64'
default = 'x86_64'
front_os = 'redhat6'
back_os = 'debian6'
default_os = 'debian6'
def __init__(self):
super(Test, self).__init__('test')
self.add_target(self.default, Target(self.default))
self.add_target(self.front_end, Target(self.front_end))
self.add_operating_system(self.default_os, OS('debian', 6))
self.add_operating_system(self.front_os, OS('redhat', 6))
@classmethod
def detect(self):
return True
| TheTimmy/spack | lib/spack/spack/platforms/test.py | Python | lgpl-2.1 | 1,930 |
/**
* module Conversion
* submodule Color Conversion
* @for p5
* @requires core
*/
'use strict';
/**
* Conversions adapted from <http://www.easyrgb.com/math.html>.
*
* In these functions, hue is always in the range [0,1); all other components
* are in the range [0,1]. 'Brightness' and 'value' are used interchangeably.
*/
var p5 = require('../core/core');
p5.ColorConversion = {};
/**
* Convert an HSBA array to HSLA.
*/
p5.ColorConversion._hsbaToHSLA = function(hsba) {
var hue = hsba[0];
var sat = hsba[1];
var val = hsba[2];
// Calculate lightness.
var li = (2 - sat) * val / 2;
// Convert saturation.
if (li !== 0) {
if (li === 1) {
sat = 0;
} else if (li < 0.5) {
sat = sat / (2 - sat);
} else {
sat = sat * val / (2 - li * 2);
}
}
// Hue and alpha stay the same.
return [hue, sat, li, hsba[3]];
};
/**
* Convert an HSBA array to RGBA.
*/
p5.ColorConversion._hsbaToRGBA = function(hsba) {
var hue = hsba[0] * 6; // We will split hue into 6 sectors.
var sat = hsba[1];
var val = hsba[2];
var RGBA = [];
if (sat === 0) {
RGBA = [val, val, val, hsba[3]]; // Return early if grayscale.
} else {
var sector = Math.floor(hue);
var tint1 = val * (1 - sat);
var tint2 = val * (1 - sat * (hue - sector));
var tint3 = val * (1 - sat * (1 + sector - hue));
var red, green, blue;
if (sector === 1) { // Yellow to green.
red = tint2;
green = val;
blue = tint1;
} else if (sector === 2) { // Green to cyan.
red = tint1;
green = val;
blue = tint3;
} else if (sector === 3) { // Cyan to blue.
red = tint1;
green = tint2;
blue = val;
} else if (sector === 4) { // Blue to magenta.
red = tint3;
green = tint1;
blue = val;
} else if (sector === 5) { // Magenta to red.
red = val;
green = tint1;
blue = tint2;
} else { // Red to yellow (sector could be 0 or 6).
red = val;
green = tint3;
blue = tint1;
}
RGBA = [red, green, blue, hsba[3]];
}
return RGBA;
};
/**
* Convert an HSLA array to HSBA.
*/
p5.ColorConversion._hslaToHSBA = function(hsla) {
var hue = hsla[0];
var sat = hsla[1];
var li = hsla[2];
// Calculate brightness.
var val;
if (li < 0.5) {
val = (1 + sat) * li;
} else {
val = li + sat - li * sat;
}
// Convert saturation.
sat = 2 * (val - li) / val;
// Hue and alpha stay the same.
return [hue, sat, val, hsla[3]];
};
/**
* Convert an HSLA array to RGBA.
*
* We need to change basis from HSLA to something that can be more easily be
* projected onto RGBA. We will choose hue and brightness as our first two
* components, and pick a convenient third one ('zest') so that we don't need
* to calculate formal HSBA saturation.
*/
p5.ColorConversion._hslaToRGBA = function(hsla){
var hue = hsla[0] * 6; // We will split hue into 6 sectors.
var sat = hsla[1];
var li = hsla[2];
var RGBA = [];
if (sat === 0) {
RGBA = [li, li, li, hsla[3]]; // Return early if grayscale.
} else {
// Calculate brightness.
var val;
if (li < 0.5) {
val = (1 + sat) * li;
} else {
val = li + sat - li * sat;
}
// Define zest.
var zest = 2 * li - val;
// Implement projection (project onto green by default).
var hzvToRGB = function(hue, zest, val) {
if (hue < 0) { // Hue must wrap to allow projection onto red and blue.
hue += 6;
} else if (hue >= 6) {
hue -= 6;
}
if (hue < 1) { // Red to yellow (increasing green).
return (zest + (val - zest) * hue);
} else if (hue < 3) { // Yellow to cyan (greatest green).
return val;
} else if (hue < 4) { // Cyan to blue (decreasing green).
return (zest + (val - zest) * (4 - hue));
} else { // Blue to red (least green).
return zest;
}
};
// Perform projections, offsetting hue as necessary.
RGBA = [hzvToRGB(hue + 2, zest, val),
hzvToRGB(hue , zest, val),
hzvToRGB(hue - 2, zest, val),
hsla[3]];
}
return RGBA;
};
/**
* Convert an RGBA array to HSBA.
*/
p5.ColorConversion._rgbaToHSBA = function(rgba) {
var red = rgba[0];
var green = rgba[1];
var blue = rgba[2];
var val = Math.max(red, green, blue);
var chroma = val - Math.min(red, green, blue);
var hue, sat;
if (chroma === 0) { // Return early if grayscale.
hue = 0;
sat = 0;
}
else {
sat = chroma / val;
if (red === val) { // Magenta to yellow.
hue = (green - blue) / chroma;
} else if (green === val) { // Yellow to cyan.
hue = 2 + (blue - red) / chroma;
} else if (blue === val) { // Cyan to magenta.
hue = 4 + (red - green) / chroma;
}
if (hue < 0) { // Confine hue to the interval [0, 1).
hue += 6;
} else if (hue >= 6) {
hue -= 6;
}
}
return [hue / 6, sat, val, rgba[3]];
};
/**
* Convert an RGBA array to HSLA.
*/
p5.ColorConversion._rgbaToHSLA = function(rgba) {
var red = rgba[0];
var green = rgba[1];
var blue = rgba[2];
var val = Math.max(red, green, blue);
var min = Math.min(red, green, blue);
var li = val + min; // We will halve this later.
var chroma = val - min;
var hue, sat;
if (chroma === 0) { // Return early if grayscale.
hue = 0;
sat = 0;
} else {
if (li < 1) {
sat = chroma / li;
} else {
sat = chroma / (2 - li);
}
if (red === val) { // Magenta to yellow.
hue = (green - blue) / chroma;
} else if (green === val) { // Yellow to cyan.
hue = 2 + (blue - red) / chroma;
} else if (blue === val) { // Cyan to magenta.
hue = 4 + (red - green) / chroma;
}
if (hue < 0) { // Confine hue to the interval [0, 1).
hue += 6;
} else if (hue >= 6) {
hue -= 6;
}
}
return [hue / 6, sat, li / 2, rgba[3]];
};
module.exports = p5.ColorConversion;
| kadamwhite/p5.js | src/color/color_conversion.js | JavaScript | lgpl-2.1 | 5,998 |
/* reamer byte writer
*
* Copyright (C) 2009 Sebastian Dröge <[email protected]>.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Library General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Library General Public License for more details.
*
* You should have received a copy of the GNU Library General Public
* License along with this library; if not, write to the
* Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#define BYTE_WRITER_DISABLE_INLINES
#include "bytewriter.h"
/**
* SECTION:bytewriter
* @short_description: Writes different integer, string and floating point
* types to a memory buffer and allows reading
*
* #ByteWriter provides a byte writer and reader that can write/read different
* integer and floating point types to/from a memory buffer. It provides functions
* for writing/reading signed/unsigned, little/big endian integers of 8, 16, 24,
* 32 and 64 bits and functions for reading little/big endian floating points numbers of
* 32 and 64 bits. It also provides functions to write/read NUL-terminated strings
* in various character encodings.
*/
/**
* byte_writer_new:
*
* Creates a new, empty #ByteWriter instance
*
* Free-function: byte_writer_free
*
* Returns: (transfer full): a new, empty #ByteWriter instance
*/
ByteWriter *
byte_writer_new (void)
{
ByteWriter *ret = g_slice_new0 (ByteWriter);
if (ret)
ret->owned = TRUE;
return ret;
}
/**
* byte_writer_new_with_size:
* @size: Initial size of data
* @fixed: If %TRUE the data can't be reallocated
*
* Creates a new #ByteWriter instance with the given
* initial data size.
*
* Free-function: byte_writer_free
*
* Returns: (transfer full): a new #ByteWriter instance
*/
ByteWriter *
byte_writer_new_with_size (uint32_t size, bool fixed)
{
ByteWriter *ret = byte_writer_new ();
if (ret) {
ret->alloc_size = size;
ret->parent.data = g_malloc (ret->alloc_size);
ret->fixed = fixed;
ret->owned = TRUE;
}
return ret;
}
/**
* byte_writer_new_with_data:
* @data: Memory area for writing
* @size: Size of @data in bytes
* @initialized: If %TRUE the complete data can be read from the beginning
*
* Creates a new #ByteWriter instance with the given
* memory area. If @initialized is %TRUE it is possible to
* read @size bytes from the #ByteWriter from the beginning.
*
* Free-function: byte_writer_free
*
* Returns: (transfer full): a new #ByteWriter instance
*/
ByteWriter *
byte_writer_new_with_data (uint8_t * data, uint32_t size, bool initialized)
{
ByteWriter *ret = byte_writer_new ();
if (ret) {
ret->parent.data = data;
ret->parent.size = (initialized) ? size : 0;
ret->alloc_size = size;
ret->fixed = TRUE;
ret->owned = FALSE;
}
return ret;
}
/**
* byte_writer_init:
* @writer: #ByteWriter instance
*
* Initializes @writer to an empty instance
*/
void
byte_writer_init (ByteWriter * writer)
{
g_return_if_fail (writer != NULL);
memset (writer, 0, sizeof (ByteWriter));
writer->owned = TRUE;
}
/**
* byte_writer_init_with_size:
* @writer: #ByteWriter instance
* @size: Initial size of data
* @fixed: If %TRUE the data can't be reallocated
*
* Initializes @writer with the given initial data size.
*/
void
byte_writer_init_with_size (ByteWriter * writer, uint32_t size,
bool fixed)
{
g_return_if_fail (writer != NULL);
byte_writer_init (writer);
writer->parent.data = g_malloc (size);
writer->alloc_size = size;
writer->fixed = fixed;
writer->owned = TRUE;
}
/**
* byte_writer_init_with_data:
* @writer: #ByteWriter instance
* @data: (array length=size) (transfer none): Memory area for writing
* @size: Size of @data in bytes
* @initialized: If %TRUE the complete data can be read from the beginning
*
* Initializes @writer with the given
* memory area. If @initialized is %TRUE it is possible to
* read @size bytes from the #ByteWriter from the beginning.
*/
void
byte_writer_init_with_data (ByteWriter * writer, uint8_t * data,
uint32_t size, bool initialized)
{
g_return_if_fail (writer != NULL);
byte_writer_init (writer);
writer->parent.data = data;
writer->parent.size = (initialized) ? size : 0;
writer->alloc_size = size;
writer->fixed = TRUE;
writer->owned = FALSE;
}
/**
* byte_writer_reset:
* @writer: #ByteWriter instance
*
* Resets @writer and frees the data if it's
* owned by @writer.
*/
void
byte_writer_reset (ByteWriter * writer)
{
g_return_if_fail (writer != NULL);
if (writer->owned)
g_free ((uint8_t *) writer->parent.data);
memset (writer, 0, sizeof (ByteWriter));
}
/**
* byte_writer_reset_and_get_data:
* @writer: #ByteWriter instance
*
* Resets @writer and returns the current data.
*
* Free-function: g_free
*
* Returns: (array) (transfer full): the current data. g_free() after
* usage.
*/
uint8_t *
byte_writer_reset_and_get_data (ByteWriter * writer)
{
uint8_t *data;
g_return_val_if_fail (writer != NULL, NULL);
data = (uint8_t *) writer->parent.data;
if (!writer->owned)
data = g_memdup (data, writer->parent.size);
writer->parent.data = NULL;
byte_writer_reset (writer);
return data;
}
#if 0
/**
* byte_writer_reset_and_get_buffer:
* @writer: #ByteWriter instance
*
* Resets @writer and returns the current data as buffer.
*
* Free-function: buffer_unref
*
* Returns: (transfer full): the current data as buffer. buffer_unref()
* after usage.
*/
Buffer *
byte_writer_reset_and_get_buffer (ByteWriter * writer)
{
Buffer *buffer;
void* data;
size_t size;
g_return_val_if_fail (writer != NULL, NULL);
size = writer->parent.size;
data = byte_writer_reset_and_get_data (writer);
buffer = buffer_new ();
if (data != NULL) {
buffer_append_memory (buffer,
memory_new_wrapped (0, data, size, 0, size, data, g_free));
}
return buffer;
}
#endif
/**
* byte_writer_free:
* @writer: (in) (transfer full): #ByteWriter instance
*
* Frees @writer and all memory allocated by it.
*/
void
byte_writer_free (ByteWriter * writer)
{
g_return_if_fail (writer != NULL);
byte_writer_reset (writer);
g_slice_free (ByteWriter, writer);
}
/**
* byte_writer_free_and_get_data:
* @writer: (in) (transfer full): #ByteWriter instance
*
* Frees @writer and all memory allocated by it except
* the current data, which is returned.
*
* Free-function: g_free
*
* Returns: (transfer full): the current data. g_free() after usage.
*/
uint8_t *
byte_writer_free_and_get_data (ByteWriter * writer)
{
uint8_t *data;
g_return_val_if_fail (writer != NULL, NULL);
data = byte_writer_reset_and_get_data (writer);
g_slice_free (ByteWriter, writer);
return data;
}
#if 0
/**
* byte_writer_free_and_get_buffer:
* @writer: (in) (transfer full): #ByteWriter instance
*
* Frees @writer and all memory allocated by it except
* the current data, which is returned as #Buffer.
*
* Free-function: buffer_unref
*
* Returns: (transfer full): the current data as buffer. buffer_unref()
* after usage.
*/
Buffer *
byte_writer_free_and_get_buffer (ByteWriter * writer)
{
Buffer *buffer;
g_return_val_if_fail (writer != NULL, NULL);
buffer = byte_writer_reset_and_get_buffer (writer);
g_slice_free (ByteWriter, writer);
return buffer;
}
#endif
/**
* byte_writer_get_remaining:
* @writer: #ByteWriter instance
*
* Returns the remaining size of data that can still be written. If
* -1 is returned the remaining size is only limited by system resources.
*
* Returns: the remaining size of data that can still be written
*/
uint32_t
byte_writer_get_remaining (const ByteWriter * writer)
{
g_return_val_if_fail (writer != NULL, -1);
if (!writer->fixed)
return -1;
else
return writer->alloc_size - writer->parent.byte;
}
/**
* byte_writer_ensure_free_space:
* @writer: #ByteWriter instance
* @size: Number of bytes that should be available
*
* Checks if enough free space from the current write cursor is
* available and reallocates if necessary.
*
* Returns: %TRUE if at least @size bytes are still available
*/
bool
byte_writer_ensure_free_space (ByteWriter * writer, uint32_t size)
{
return _byte_writer_ensure_free_space_inline (writer, size);
}
#define CREATE_WRITE_FUNC(bits,type,name,write_func) \
bool \
byte_writer_put_##name (ByteWriter *writer, type val) \
{ \
return _byte_writer_put_##name##_inline (writer, val); \
}
CREATE_WRITE_FUNC (8, uint8_t, uint8, GST_WRITE_UINT8);
CREATE_WRITE_FUNC (8, int8_t, int8, GST_WRITE_UINT8);
CREATE_WRITE_FUNC (16, uint16_t, uint16_le, GST_WRITE_UINT16_LE);
CREATE_WRITE_FUNC (16, uint16_t, uint16_be, GST_WRITE_UINT16_BE);
CREATE_WRITE_FUNC (16, int16_t, int16_le, GST_WRITE_UINT16_LE);
CREATE_WRITE_FUNC (16, int16_t, int16_be, GST_WRITE_UINT16_BE);
CREATE_WRITE_FUNC (24, uint32_t, uint24_le, GST_WRITE_UINT24_LE);
CREATE_WRITE_FUNC (24, uint32_t, uint24_be, GST_WRITE_UINT24_BE);
CREATE_WRITE_FUNC (24, int32_t, int24_le, GST_WRITE_UINT24_LE);
CREATE_WRITE_FUNC (24, int32_t, int24_be, GST_WRITE_UINT24_BE);
CREATE_WRITE_FUNC (32, uint32_t, uint32_le, GST_WRITE_UINT32_LE);
CREATE_WRITE_FUNC (32, uint32_t, uint32_be, GST_WRITE_UINT32_BE);
CREATE_WRITE_FUNC (32, int32_t, int32_le, GST_WRITE_UINT32_LE);
CREATE_WRITE_FUNC (32, int32_t, int32_be, GST_WRITE_UINT32_BE);
CREATE_WRITE_FUNC (64, uint64_t, uint64_le, GST_WRITE_UINT64_LE);
CREATE_WRITE_FUNC (64, uint64_t, uint64_be, GST_WRITE_UINT64_BE);
CREATE_WRITE_FUNC (64, int64_t, int64_le, GST_WRITE_UINT64_LE);
CREATE_WRITE_FUNC (64, int64_t, int64_be, GST_WRITE_UINT64_BE);
CREATE_WRITE_FUNC (32, float, float32_be, GST_WRITE_FLOAT_BE);
CREATE_WRITE_FUNC (32, float, float32_le, GST_WRITE_FLOAT_LE);
CREATE_WRITE_FUNC (64, double, float64_be, GST_WRITE_DOUBLE_BE);
CREATE_WRITE_FUNC (64, double, float64_le, GST_WRITE_DOUBLE_LE);
bool
byte_writer_put_data (ByteWriter * writer, const uint8_t * data,
uint32_t size)
{
return _byte_writer_put_data_inline (writer, data, size);
}
bool
byte_writer_fill (ByteWriter * writer, uint8_t value, uint32_t size)
{
return _byte_writer_fill_inline (writer, value, size);
}
#define CREATE_WRITE_STRING_FUNC(bits,type) \
bool \
byte_writer_put_string_utf##bits (ByteWriter *writer, const type * data) \
{ \
uint32_t size = 0; \
\
g_return_val_if_fail (writer != NULL, FALSE); \
\
/* endianness does not matter if we are looking for a NUL terminator */ \
while (data[size] != 0) { \
/* have prevent overflow */ \
if (G_UNLIKELY (size == G_MAXUINT)) \
return FALSE; \
++size; \
} \
++size; \
\
if (G_UNLIKELY (!_byte_writer_ensure_free_space_inline(writer, size * (bits / 8)))) \
return FALSE; \
\
_byte_writer_put_data_inline (writer, (const uint8_t *) data, size * (bits / 8)); \
\
return TRUE; \
}
CREATE_WRITE_STRING_FUNC (8, char);
CREATE_WRITE_STRING_FUNC (16, uint16_t);
CREATE_WRITE_STRING_FUNC (32, uint32_t);
/**
* byte_writer_put_uint8:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned 8 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint16_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned big endian 16 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint24_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned big endian 24 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint32_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned big endian 32 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint64_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned big endian 64 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint16_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned little endian 16 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint24_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned little endian 24 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint32_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned little endian 32 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_uint64_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a unsigned little endian 64 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int8:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed 8 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int16_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed big endian 16 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int24_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed big endian 24 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int32_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed big endian 32 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int64_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed big endian 64 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int16_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed little endian 16 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int24_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed little endian 24 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int32_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed little endian 32 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_int64_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a signed little endian 64 bit integer to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_float32_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a big endian 32 bit float to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_float64_be:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a big endian 64 bit float to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_float32_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a little endian 32 bit float to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_float64_le:
* @writer: #ByteWriter instance
* @val: Value to write
*
* Writes a little endian 64 bit float to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_string_utf8:
* @writer: #ByteWriter instance
* @data: (transfer none) (array zero-terminated=1) (type utf8): UTF8 string to
* write
*
* Writes a NUL-terminated UTF8 string to @writer (including the terminator).
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_string_utf16:
* @writer: #ByteWriter instance
* @data: (transfer none) (array zero-terminated=1): UTF16 string to write
*
* Writes a NUL-terminated UTF16 string to @writer (including the terminator).
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_string_utf32:
* @writer: #ByteWriter instance
* @data: (transfer none) (array zero-terminated=1): UTF32 string to write
*
* Writes a NUL-terminated UTF32 string to @writer (including the terminator).
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_data:
* @writer: #ByteWriter instance
* @data: (transfer none) (array length=size): Data to write
* @size: Size of @data in bytes
*
* Writes @size bytes of @data to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_fill:
* @writer: #ByteWriter instance
* @value: Value to be written
* @size: Number of bytes to be written
*
* Writes @size bytes containing @value to @writer.
*
* Returns: %TRUE if the value could be written
*/
/**
* byte_writer_put_buffer:
* @writer: #ByteWriter instance
* @buffer: (transfer none): source #Buffer
* @offset: offset to copy from
* @size: total size to copy. If -1, all data is copied
*
* Writes @size bytes of @data to @writer.
*
* Returns: %TRUE if the data could be written
*
*/
| BtbN/libyami | codecparsers/bytewriter.c | C | lgpl-2.1 | 17,505 |
import org.jcsp.lang.*;
// LaunchControl is a process to control the launch of a space rocket.
// It is configured with a countdown time in seconds -- this must be above
// a minimum threshold, MIN_COUNTDOWN, else the launch is immediately aborted.
// There are two control lines, abort and hold, that respectively abort
// or hold the launch if signalled. The hold is released by a second
// signal on the same line.
// During countdown, the count is reported by outputting on the countdown channel.
// If not aborted, LaunchControl fires the rocket (by outputting on its fire
// channel) when the countdown reaches zero. An ABORTED launch is also reported
// on this fire channel.
// After a successful or aborted launch, LaunchControl terminates.
public class LaunchControl implements CSProcess {
public static final int MIN_COUNTDOWN = 10;
public static final int FIRED = 0;
public static final int HOLDING = -1;
public static final int ABORTED = -2;
private final int start;
private final AltingChannelInputInt abort;
private final AltingChannelInputInt hold;
private final ChannelOutputInt countdown;
private final ChannelOutputInt fire;
private int status;
public LaunchControl (final int start,
final AltingChannelInputInt abort,
final AltingChannelInputInt hold,
final ChannelOutputInt countdown,
final ChannelOutputInt fire) {
this.start = start;
this.abort = abort;
this.hold = hold;
this.countdown = countdown;
this.fire = fire;
}
public int getStatus () { // inspection method
return status; // not to be used while running!
}
public void run () {
final CSTimer tim = new CSTimer (); // JCSP timers have
final long oneSecond = 1000; // millisecond granularity
long timeout = tim.read () + oneSecond; // compute first timeout
final Alternative alt =
new Alternative (new Guard[] {abort, hold, tim});
final int ABORT = 0;
final int HOLD = 1;
final int TICK = 2;
int count = start;
boolean counting = (start >= MIN_COUNTDOWN); // abort if bad start
while ((count > 0) && counting) {
countdown.write (count); // public address system
tim.setAlarm (timeout); // set next timeout
switch (alt.priSelect ()) {
case ABORT: // abort signalled
abort.read (); // clear the signal
counting = false;
break;
case HOLD: // hold signalled
long timeLeft = timeout - tim.read (); // time till next tick
hold.read (); // clear the signal
fire.write (HOLDING); // signal rocket
hold.read (); // wait for the release
timeout = tim.read () + timeLeft; // recompute next timeout
fire.write (HOLDING); // signal rocket
break;
case TICK: // timeout expired
count--;
timeout += oneSecond; // compute next timeout
break;
}
}
status = (counting) ? FIRED : ABORTED; // set status attribute
fire.write (status); // signal rocket (go/nogo)
if (counting) countdown.write (0); // complete countdown
}
}
| rickb777/jcsp | src/jcsp-demos/doc-ex/jcsp/lang/LaunchControl.java | Java | lgpl-2.1 | 3,744 |
/******************************************************************************
* SOFA, Simulation Open-Framework Architecture, development version *
* (c) 2006-2017 INRIA, USTL, UJF, CNRS, MGH *
* *
* This program is free software; you can redistribute it and/or modify it *
* under the terms of the GNU Lesser General Public License as published by *
* the Free Software Foundation; either version 2.1 of the License, or (at *
* your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT *
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License *
* for more details. *
* *
* You should have received a copy of the GNU Lesser General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
*******************************************************************************
* Authors: The SOFA Team and external contributors (see Authors.txt) *
* *
* Contact information: [email protected] *
******************************************************************************/
#include <SofaTest/Python_test.h>
namespace sofa {
// static build of the test list
static struct Tests : public Python_test_list
{
Tests()
{
static const std::string scenePath = std::string(SOFABASEMECHANICS_TEST_PYTHON_DIR);
addTest( "MechanicalObject_test.py", scenePath );
}
} tests;
// run test list
INSTANTIATE_TEST_CASE_P(Batch,
Python_scene_test,
::testing::ValuesIn(tests.list));
TEST_P(Python_scene_test, sofa_python_scene_tests)
{
run(GetParam());
}
} // namespace sofa
| FabienPean/sofa | SofaKernel/modules/SofaBaseMechanics/SofaBaseMechanics_test/python_test_list.cpp | C++ | lgpl-2.1 | 2,253 |
/* Copyright (c) 2015 D. Mackay. All rights reserved. */
@interface PropertyDef : Def
{
id unit;
id compdec;
id classdef;
}
@property BOOL isCopy, isNonAtomic;
- classdef:aClass;
- compdec:aDec;
- synth;
- gen;
@end
| JX7P/JXObjC | objc/oclib/propdef.h | C | lgpl-2.1 | 233 |
/****************************************************************************
**
** Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
** All rights reserved.
** Contact: Nokia Corporation ([email protected])
**
** This file is part of the QtXmlPatterns module of the Qt Toolkit.
**
** $QT_BEGIN_LICENSE:LGPL$
** GNU Lesser General Public License Usage
** This file may be used under the terms of the GNU Lesser General Public
** License version 2.1 as published by the Free Software Foundation and
** appearing in the file LICENSE.LGPL included in the packaging of this
** file. Please review the following information to ensure the GNU Lesser
** General Public License version 2.1 requirements will be met:
** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** In addition, as a special exception, Nokia gives you certain additional
** rights. These rights are described in the Nokia Qt LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
** GNU General Public License Usage
** Alternatively, this file may be used under the terms of the GNU General
** Public License version 3.0 as published by the Free Software Foundation
** and appearing in the file LICENSE.GPL included in the packaging of this
** file. Please review the following information to ensure the GNU General
** Public License version 3.0 requirements will be met:
** http://www.gnu.org/copyleft/gpl.html.
**
** Other Usage
** Alternatively, this file may be used in accordance with the terms and
** conditions contained in a signed written agreement between you and Nokia.
**
**
**
**
**
** $QT_END_LICENSE$
**
****************************************************************************/
#include "qxsdschemacontext_p.h"
#include "qderivedinteger_p.h"
#include "qderivedstring_p.h"
#include "qxsdschematypesfactory_p.h"
QT_BEGIN_NAMESPACE
using namespace QPatternist;
XsdSchemaContext::XsdSchemaContext(const NamePool::Ptr &namePool)
: m_namePool(namePool)
, m_networkAccessManager(0)
, m_uriResolver(0)
, m_messageHandler(0)
{
}
NamePool::Ptr XsdSchemaContext::namePool() const
{
return m_namePool;
}
QUrl XsdSchemaContext::baseURI() const
{
return m_baseURI;
}
void XsdSchemaContext::setBaseURI(const QUrl &uri)
{
m_baseURI = uri;
}
void XsdSchemaContext::setNetworkAccessManager(QNetworkAccessManager *accessManager)
{
m_networkAccessManager = accessManager;
}
QNetworkAccessManager* XsdSchemaContext::networkAccessManager() const
{
return m_networkAccessManager;
}
void XsdSchemaContext::setMessageHandler(QAbstractMessageHandler *handler)
{
m_messageHandler = handler;
}
QAbstractMessageHandler* XsdSchemaContext::messageHandler() const
{
return m_messageHandler;
}
QSourceLocation XsdSchemaContext::locationFor(const SourceLocationReflection *const) const
{
return QSourceLocation();
}
void XsdSchemaContext::setUriResolver(const QAbstractUriResolver *uriResolver)
{
m_uriResolver = uriResolver;
}
const QAbstractUriResolver* XsdSchemaContext::uriResolver() const
{
return m_uriResolver;
}
XsdFacet::Hash XsdSchemaContext::facetsForType(const AnySimpleType::Ptr &type) const
{
if (type->isDefinedBySchema())
return XsdSimpleType::Ptr(type)->facets();
else {
if (m_builtinTypesFacetList.isEmpty())
m_builtinTypesFacetList = setupBuiltinTypesFacetList();
return m_builtinTypesFacetList.value(type);
}
}
SchemaTypeFactory::Ptr XsdSchemaContext::schemaTypeFactory() const
{
if (!m_schemaTypeFactory)
m_schemaTypeFactory = SchemaTypeFactory::Ptr(new XsdSchemaTypesFactory(m_namePool));
return m_schemaTypeFactory;
}
QHash<SchemaType::Ptr, XsdFacet::Hash> XsdSchemaContext::setupBuiltinTypesFacetList() const
{
QHash<SchemaType::Ptr, XsdFacet::Hash> hash;
const XsdFacet::Ptr fixedCollapseWhiteSpace(new XsdFacet());
fixedCollapseWhiteSpace->setType(XsdFacet::WhiteSpace);
fixedCollapseWhiteSpace->setValue(DerivedString<TypeString>::fromLexical(m_namePool, XsdSchemaToken::toString(XsdSchemaToken::Collapse)));
fixedCollapseWhiteSpace->setFixed(true);
const XsdFacet::Ptr collapseWhiteSpace(new XsdFacet());
collapseWhiteSpace->setType(XsdFacet::WhiteSpace);
collapseWhiteSpace->setValue(DerivedString<TypeString>::fromLexical(m_namePool, XsdSchemaToken::toString(XsdSchemaToken::Collapse)));
collapseWhiteSpace->setFixed(false);
const XsdFacet::Ptr preserveWhiteSpace(new XsdFacet());
preserveWhiteSpace->setType(XsdFacet::WhiteSpace);
preserveWhiteSpace->setValue(DerivedString<TypeString>::fromLexical(m_namePool, XsdSchemaToken::toString(XsdSchemaToken::Preserve)));
preserveWhiteSpace->setFixed(false);
const XsdFacet::Ptr replaceWhiteSpace(new XsdFacet());
replaceWhiteSpace->setType(XsdFacet::WhiteSpace);
replaceWhiteSpace->setValue(DerivedString<TypeString>::fromLexical(m_namePool, XsdSchemaToken::toString(XsdSchemaToken::Replace)));
replaceWhiteSpace->setFixed(false);
const XsdFacet::Ptr fixedZeroFractionDigits(new XsdFacet());
fixedZeroFractionDigits->setType(XsdFacet::FractionDigits);
fixedZeroFractionDigits->setValue(DerivedInteger<TypeNonNegativeInteger>::fromValue(m_namePool, 0));
fixedZeroFractionDigits->setFixed(true);
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsString];
facets.insert(preserveWhiteSpace->type(), preserveWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsBoolean];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsDecimal];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsFloat];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsDouble];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsDuration];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsDateTime];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsTime];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsDate];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsGYearMonth];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsGYear];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsGMonthDay];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsGDay];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsGMonth];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsHexBinary];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsBase64Binary];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsAnyURI];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsQName];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNOTATION];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNormalizedString];
facets.insert(replaceWhiteSpace->type(), replaceWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsToken];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsLanguage];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
const XsdFacet::Ptr pattern(new XsdFacet());
pattern->setType(XsdFacet::Pattern);
pattern->setMultiValue(AtomicValue::List() << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("[a-zA-Z]{1,8}(-[a-zA-Z0-9]{1,8})*")));
facets.insert(pattern->type(), pattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNMTOKEN];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
const XsdFacet::Ptr pattern(new XsdFacet());
pattern->setType(XsdFacet::Pattern);
pattern->setMultiValue(AtomicValue::List() << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("\\c+")));
facets.insert(pattern->type(), pattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsName];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
const XsdFacet::Ptr pattern(new XsdFacet());
pattern->setType(XsdFacet::Pattern);
pattern->setMultiValue(AtomicValue::List() << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("\\i\\c*")));
facets.insert(pattern->type(), pattern);
}
const XsdFacet::Ptr ncNamePattern(new XsdFacet());
{
ncNamePattern->setType(XsdFacet::Pattern);
AtomicValue::List patterns;
patterns << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("\\i\\c*"));
patterns << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("[\\i-[:]][\\c-[:]]*"));
ncNamePattern->setMultiValue(patterns);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNCName];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
facets.insert(ncNamePattern->type(), ncNamePattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsID];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
facets.insert(ncNamePattern->type(), ncNamePattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsIDREF];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
facets.insert(ncNamePattern->type(), ncNamePattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsENTITY];
facets.insert(collapseWhiteSpace->type(), collapseWhiteSpace);
facets.insert(ncNamePattern->type(), ncNamePattern);
}
const XsdFacet::Ptr integerPattern(new XsdFacet());
integerPattern->setType(XsdFacet::Pattern);
integerPattern->setMultiValue(AtomicValue::List() << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("[\\-+]?[0-9]+")));
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsInteger];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNonPositiveInteger];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("0")));
facets.insert(maxInclusive->type(), maxInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNegativeInteger];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("-1")));
facets.insert(maxInclusive->type(), maxInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsLong];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("9223372036854775807")));
facets.insert(maxInclusive->type(), maxInclusive);
const XsdFacet::Ptr minInclusive(new XsdFacet());
minInclusive->setType(XsdFacet::MinimumInclusive);
minInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("-9223372036854775808")));
facets.insert(minInclusive->type(), minInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsInt];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("2147483647")));
facets.insert(maxInclusive->type(), maxInclusive);
const XsdFacet::Ptr minInclusive(new XsdFacet());
minInclusive->setType(XsdFacet::MinimumInclusive);
minInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("-2147483648")));
facets.insert(minInclusive->type(), minInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsShort];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("32767")));
facets.insert(maxInclusive->type(), maxInclusive);
const XsdFacet::Ptr minInclusive(new XsdFacet());
minInclusive->setType(XsdFacet::MinimumInclusive);
minInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("-32768")));
facets.insert(minInclusive->type(), minInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsByte];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("127")));
facets.insert(maxInclusive->type(), maxInclusive);
const XsdFacet::Ptr minInclusive(new XsdFacet());
minInclusive->setType(XsdFacet::MinimumInclusive);
minInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("-128")));
facets.insert(minInclusive->type(), minInclusive);
}
const XsdFacet::Ptr unsignedMinInclusive(new XsdFacet());
unsignedMinInclusive->setType(XsdFacet::MinimumInclusive);
unsignedMinInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("0")));
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsNonNegativeInteger];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
facets.insert(unsignedMinInclusive->type(), unsignedMinInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsUnsignedLong];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
facets.insert(unsignedMinInclusive->type(), unsignedMinInclusive);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("18446744073709551615")));
facets.insert(maxInclusive->type(), maxInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsUnsignedInt];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
facets.insert(unsignedMinInclusive->type(), unsignedMinInclusive);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("4294967295")));
facets.insert(maxInclusive->type(), maxInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsUnsignedShort];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
facets.insert(unsignedMinInclusive->type(), unsignedMinInclusive);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("65535")));
facets.insert(maxInclusive->type(), maxInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsUnsignedByte];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
facets.insert(integerPattern->type(), integerPattern);
facets.insert(unsignedMinInclusive->type(), unsignedMinInclusive);
const XsdFacet::Ptr maxInclusive(new XsdFacet());
maxInclusive->setType(XsdFacet::MaximumInclusive);
maxInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("255")));
facets.insert(maxInclusive->type(), maxInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsPositiveInteger];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
facets.insert(fixedZeroFractionDigits->type(), fixedZeroFractionDigits);
const XsdFacet::Ptr minInclusive(new XsdFacet());
minInclusive->setType(XsdFacet::MinimumInclusive);
minInclusive->setValue(DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("1")));
facets.insert(minInclusive->type(), minInclusive);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsYearMonthDuration];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
const XsdFacet::Ptr pattern(new XsdFacet());
pattern->setType(XsdFacet::Pattern);
pattern->setMultiValue(AtomicValue::List() << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("[^DT]*")));
facets.insert(pattern->type(), pattern);
}
{
XsdFacet::Hash &facets = hash[BuiltinTypes::xsDayTimeDuration];
facets.insert(fixedCollapseWhiteSpace->type(), fixedCollapseWhiteSpace);
const XsdFacet::Ptr pattern(new XsdFacet());
pattern->setType(XsdFacet::Pattern);
pattern->setMultiValue(AtomicValue::List() << DerivedString<TypeString>::fromLexical(m_namePool, QString::fromLatin1("[^YM]*(T.*)?")));
facets.insert(pattern->type(), pattern);
}
return hash;
}
QT_END_NAMESPACE
| kobolabs/qt-everywhere-4.8.0 | src/xmlpatterns/schema/qxsdschemacontext.cpp | C++ | lgpl-2.1 | 21,311 |
/*
HawkNL cross platform network library
Copyright (C) 2000-2003 Phil Frisbie, Jr. ([email protected])
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.
Or go to http://www.gnu.org/copyleft/lgpl.html
*/
#include <string.h>
#include <stdio.h>
#include <stdint.h>
#if defined (_WIN32_WCE)
#define errno GetLastError()
#else
#include <errno.h>
#endif
#include "nlinternal.h"
#ifdef WINDOWS_APP
/* Windows systems */
#include "wsock.h"
#else
/* Unix-style systems or macs with posix support */
#include <netinet/in.h> /* for ntohs and htons */
#endif
#ifdef NL_INCLUDE_LOOPBACK
#include "loopback.h"
static NLaddress loopback_ouraddress;
static NLint loopgroup;
static volatile NLboolean reuseaddress = NL_FALSE;
static NLmutex portlock; /* In memory of my step-father, Don Portlock,
who passed away Jan 12, 2001 - Phil */
static volatile uint16_t newport = 1024;
static NLushort loopback_getNextPort(void)
{
(void)nlMutexLock(&portlock);
++newport;
if(newport < 1024)
{
newport = 1024;
}
(void)nlMutexUnlock(&portlock);
return newport;
}
static NLboolean loopback_ScanPort(NLushort port, NLenum type)
{
NLint numsockets = NL_MAX_GROUP_SOCKETS;
NLsocket temp[NL_MAX_GROUP_SOCKETS];
if(reuseaddress == NL_TRUE)
{
return NL_TRUE;
}
if(nlGroupGetSockets(loopgroup, (NLsocket *)&temp, &numsockets) == NL_FALSE)
{
return NL_FALSE;
}
if(numsockets == 0)
{
return NL_TRUE;
}
while(numsockets-- > 0)
{
nl_socket_t *sock = nlSockets[temp[numsockets]];
if(sock->type == type && sock->localport == port)
{
return NL_FALSE;
}
}
return NL_TRUE;
}
static NLushort loopback_TryPort(NLushort port, NLenum type)
{
NLint ntries = 500; /* this is to prevent an infinite loop */
if(port > 0)
{
if(loopback_ScanPort(port, type) == NL_TRUE)
{
return port;
}
else
{
return 0;
}
}
/* let's find our own port number */
while(ntries-- > 0)
{
port = loopback_getNextPort();
if(loopback_ScanPort(port, type) == NL_TRUE)
{
return port;
}
}
return 0;
}
NLboolean loopback_Init(void)
{
loopgroup = nlGroupCreate();
if(loopgroup == NL_INVALID)
{
return NL_FALSE;
}
return NL_TRUE;
}
void loopback_Shutdown(void)
{
(void)nlGroupDestroy(loopgroup);
}
NLboolean loopback_Listen(NLsocket socket)
{
nl_socket_t *sock = nlSockets[socket];
NLint i = NL_MAX_ACCEPT;
if(sock->type == NL_BROADCAST)
{
nlSetError(NL_WRONG_TYPE);
return NL_FALSE;
}
sock->listen = NL_TRUE;
while(i-- > 0)
{
sock->ext->accept[i] = NL_INVALID;
}
return NL_TRUE;
}
NLsocket loopback_AcceptConnection(NLsocket socket)
{
nl_socket_t *sock = nlSockets[socket];
if(sock->listen == NL_FALSE)
{
nlSetError(NL_NOT_LISTEN);
return NL_INVALID;
}
if(sock->inuse == NL_FALSE)
{
/* socket was closed by nlShutdown */
nlSetError(NL_INVALID_SOCKET);
return NL_INVALID;
}
if(sock->ext == NULL)
{
/* socket was closed on another thread */
nlSetError(NL_INVALID_SOCKET);
return NL_INVALID;
}
if(sock->ext->accept[0] != NL_INVALID)
{
NLsocket newsocket;
NLsocket osock = sock->ext->accept[0];
nl_socket_t *othersock = nlSockets[osock];
/* make sure the other socket is valid */
if(nlIsValidSocket(osock) == NL_FALSE)
{
NLint i;
for(i=1;i<NL_MAX_ACCEPT;i++)
{
sock->ext->accept[i-1] = sock->ext->accept[i];
}
sock->ext->accept[NL_MAX_ACCEPT-1] = NL_INVALID;
return loopback_AcceptConnection(socket);
}
newsocket = loopback_Open(0, sock->type);
if(newsocket != NL_INVALID)
{
NLint i;
nl_socket_t *newsock = nlSockets[newsocket];
/* we must unlock the socket briefly or else nlConnect will deadlock */
nlUnlockSocket(socket, NL_BOTH);
if(nlLockSocket(osock, NL_READ) == NL_FALSE)
{
return NL_INVALID;
}
(void)nlLockSocket(socket, NL_BOTH);
/* do the connecting */
newsock->ext->consock = osock;
newsock->remoteport = othersock->localport;
othersock->ext->consock = newsocket;
othersock->remoteport = newsock->localport;
newsock->connected = NL_TRUE;
loopback_SetAddrPort(&othersock->addressin, othersock->remoteport);
loopback_SetAddrPort(&newsock->addressin, newsock->remoteport);
othersock->connected = NL_TRUE;
othersock->connecting = NL_FALSE;
/* move the accept que down one */
for(i=1;i<NL_MAX_ACCEPT;i++)
{
sock->ext->accept[i-1] = sock->ext->accept[i];
}
sock->ext->accept[NL_MAX_ACCEPT-1] = NL_INVALID;
nlUnlockSocket(socket, NL_BOTH);
nlUnlockSocket(osock, NL_READ);
(void)nlLockSocket(socket, NL_BOTH);
return newsocket;
}
}
nlSetError(NL_NO_PENDING);
return NL_INVALID;
}
NLsocket loopback_Open(NLushort port, NLenum type)
{
nl_socket_t *newsock;
NLsocket newsocket;
NLint i;
NLushort lport;
switch (type) {
case NL_RELIABLE:
case NL_UNRELIABLE:
case NL_RELIABLE_PACKETS:
case NL_BROADCAST:
break;
default:
nlSetError(NL_INVALID_ENUM);
return NL_INVALID;
}
lport = loopback_TryPort(port, type);
if(lport == 0)
{
nlSetError(NL_INVALID_PORT);
return NL_INVALID;
}
newsocket = nlGetNewSocket();
if(newsocket == NL_INVALID)
{
return NL_INVALID;
}
if(nlLockSocket(newsocket, NL_BOTH) == NL_FALSE)
{
return NL_INVALID;
}
newsock = nlSockets[newsocket];
newsock->type = type;
newsock->localport = lport;
if(type == NL_BROADCAST)
{
newsock->remoteport = lport;
}
if((newsock->ext = (nl_extra_t *)malloc(sizeof(nl_extra_t))) == NULL)
{
nlSetError(NL_OUT_OF_MEMORY);
nlUnlockSocket(newsocket, NL_BOTH);
loopback_Close(newsocket);
return NL_INVALID;
}
/* clear out the structure */
memset(newsock->ext, 0, sizeof(nl_extra_t));
for(i=0;i<NL_NUM_PACKETS;i++)
{
NLboolean err = NL_FALSE;
/* malloc the max packet length plus two bytes for the port number */
if((newsock->ext->inpacket[i] = (NLbyte *)malloc((size_t)(NL_MAX_PACKET_LENGTH + 2))) == NULL)
{
nlSetError(NL_OUT_OF_MEMORY);
err = NL_TRUE;
}
if(err == NL_TRUE)
{
while(i-- > 0)
{
free(newsock->ext->inpacket[i]);
}
nlUnlockSocket(newsocket, NL_BOTH);
loopback_Close(newsocket);
return NL_INVALID;
}
}
(void)nlGroupAddSocket(loopgroup, newsocket);
nlUnlockSocket(newsocket, NL_BOTH);
return newsocket;
}
NLboolean loopback_Connect(NLsocket socket, const NLaddress *address)
{
nl_socket_t *sock = nlSockets[socket];
NLushort port;
NLint numsockets = NL_MAX_GROUP_SOCKETS;
NLsocket temp[NL_MAX_GROUP_SOCKETS];
/* no need to connect a broadcast socket */
if(sock->type == NL_BROADCAST)
{
nlSetError(NL_WRONG_TYPE);
}
port = loopback_GetPortFromAddr(address);
/* make sure socket is not already connected */
if(sock->connected == NL_TRUE || sock->connecting == NL_TRUE)
{
nlSetError(NL_CON_REFUSED);
return NL_FALSE;
}
if(nlGroupGetSockets(loopgroup, (NLsocket *)&temp, &numsockets) == NL_FALSE)
{
return NL_FALSE;
}
if(numsockets == 0)
{
return NL_FALSE;
}
while(numsockets-- > 0)
{
NLsocket s = temp[numsockets];
nl_socket_t *othersock = nlSockets[s];
if(sock->type == othersock->type && port == othersock->localport
&& othersock->listen == NL_TRUE && othersock->connected == NL_FALSE
&& othersock->connecting == NL_FALSE)
{
/* we found the right socket, so connect */
NLint i;
if(nlLockSocket(s, NL_BOTH) == NL_FALSE)
{
return NL_FALSE;
}
for(i=0;i<NL_MAX_ACCEPT;i++)
{
if(othersock->ext->accept[i] == NL_INVALID)
{
othersock->ext->accept[i] = socket;
sock->connecting = NL_TRUE;
sock->ext->consock = s;
nlUnlockSocket(s, NL_BOTH);
if(sock->blocking == NL_TRUE)
{
nlUnlockSocket(socket, NL_BOTH);
/* wait for nlAccept to be called */
while(sock->connecting == NL_TRUE)
{
if(sock->inuse == NL_FALSE)
{
/* nlShutdown has been called */
nlSetError(NL_INVALID_SOCKET);
return NL_FALSE;
}
nlThreadSleep(NL_CONNECT_SLEEP);
}
(void)nlLockSocket(socket, NL_BOTH);
}
return NL_TRUE;
}
}
nlUnlockSocket(s, NL_BOTH);
}
}
nlSetError(NL_CON_REFUSED);
return NL_FALSE;
}
void loopback_Close(NLsocket socket)
{
nl_socket_t *sock = nlSockets[socket];
int i;
if(sock->connected == NL_TRUE || sock->connecting == NL_TRUE)
{
/* break the connection */
nl_socket_t *othersock = nlSockets[sock->ext->consock];
if(othersock->ext != NULL)
{
othersock->ext->consock = NL_INVALID;
}
othersock->connected = NL_FALSE;
sock->connected = NL_FALSE;
sock->listen = NL_FALSE;
if(sock->type != NL_BROADCAST)
{
/* this allows nlPollGroup to report socket is readable */
/* so that the app can get the NL_SOCK_DISCONNECT message*/
if(othersock->ext != NULL)
{
othersock->ext->inlen[othersock->ext->nextinused] = -1;
}
}
}
for(i=0;i<NL_NUM_PACKETS;i++)
{
void /*@owned@*/*t = sock->ext->inpacket[i];
free(t);
sock->ext->inpacket[i] = NULL;
}
free(sock->ext);
sock->ext = NULL;
}
NLint loopback_Read(NLsocket socket, NLvoid *buffer, NLint nbytes)
{
nl_socket_t *sock = nlSockets[socket];
NLint len = sock->ext->inlen[sock->ext->nextinused];
NLint c = 0;
NLushort port;
if(sock->blocking == NL_TRUE)
{
while(len == 0)
{
nlUnlockSocket(socket, NL_READ);
nlThreadSleep(10);
if(sock->inuse == NL_FALSE)
{
/* nlShutdown has been called */
nlSetError(NL_INVALID_SOCKET);
return NL_INVALID;
}
(void)nlLockSocket(socket, NL_READ);
len = sock->ext->inlen[sock->ext->nextinused];
}
}
if(len > 0)
{
if(len > nbytes)
{
nlSetError(NL_BUFFER_SIZE);
return NL_INVALID;
}
if(sock->connecting == NL_TRUE)
{
nlSetError(NL_CON_PENDING);
return NL_INVALID;
}
/* get the port number */
readShort(sock->ext->inpacket[sock->ext->nextinused], c, port);
loopback_SetAddrPort(&sock->addressin, port);
/* copy the packet */
memcpy(buffer, sock->ext->inpacket[sock->ext->nextinused] + 2, (size_t)len);
/* zero out length and set up for next packet */
sock->ext->inlen[sock->ext->nextinused] = 0;
sock->ext->nextinused++;
if(sock->ext->nextinused >= NL_NUM_PACKETS)
{
sock->ext->nextinused = 0;
}
}
/* check for broken connection */
else if((len == -1) || (sock->connected == NL_TRUE && sock->ext->consock == NL_INVALID)
|| (sock->connected == NL_FALSE && sock->type != NL_BROADCAST))
{
nlSetError(NL_SOCK_DISCONNECT);
return NL_INVALID;
}
return len;
}
static NLint loopback_WritePacket(NLsocket to, const NLvoid *buffer, NLint nbytes, NLushort fromport)
{
nl_socket_t *sock = nlSockets[to];
NLint i, j;
NLint c = 0;
/* check the packet size */
if(nbytes > NL_MAX_PACKET_LENGTH)
{
nlSetError(NL_PACKET_SIZE);
return NL_INVALID;
}
if(nlLockSocket(to, NL_READ) == NL_FALSE)
{
return NL_INVALID;
}
/* make sure we have an empty packet buffer */
if(sock->ext->nextinfree == NL_INVALID)
{
/* all buffers were filled by last write */
/* check to see if any were emptied by a read */
i = NL_NUM_PACKETS;
j = sock->ext->nextinused;
while(i-- > 0)
{
if(sock->ext->inlen[j] == 0)
{
/* found the first free */
sock->ext->nextinfree = j;
break;
}
j++;
if(j >= NL_NUM_PACKETS)
{
j = 0;
}
}
if(sock->ext->nextinfree == NL_INVALID)
{
nlUnlockSocket(to, NL_READ);
/* none are free */
if(sock->type == NL_RELIABLE || sock->type == NL_RELIABLE_PACKETS)
{
return 0;
}
else
{
/* silently fail */
return nbytes;
}
}
}
/* write the port number */
writeShort(sock->ext->inpacket[sock->ext->nextinfree], c, fromport);
/* copy the packet buffer */
memcpy(sock->ext->inpacket[sock->ext->nextinfree] + 2, buffer, (size_t)nbytes);
sock->ext->inlen[sock->ext->nextinfree] = nbytes;
sock->ext->nextinfree++;
if(sock->ext->nextinfree >= NL_NUM_PACKETS)
{
sock->ext->nextinfree = 0;
}
/* check for full packet buffers */
if(sock->ext->inlen[sock->ext->nextinfree] != 0)
{
sock->ext->nextinfree = NL_INVALID;
}
nlUnlockSocket(to, NL_READ);
return nbytes;
}
NLint loopback_Write(NLsocket socket, const NLvoid *buffer, NLint nbytes)
{
nl_socket_t *sock = nlSockets[socket];
nl_socket_t *othersock;
NLsocket s[NL_MAX_GROUP_SOCKETS];
NLint number = NL_MAX_GROUP_SOCKETS;
NLint i;
NLint count;
switch (sock->type) {
case NL_RELIABLE:
case NL_RELIABLE_PACKETS:
default:
{
if(sock->connected == NL_TRUE)
{
/* check for broken connection */
if(sock->ext->consock == NL_INVALID)
{
nlSetError(NL_SOCK_DISCONNECT);
return NL_INVALID;
}
count = loopback_WritePacket(sock->ext->consock, buffer, nbytes, sock->localport);
}
else if(sock->connecting == NL_TRUE)
{
nlSetError(NL_CON_PENDING);
return NL_INVALID;
}
else
{
nlSetError(NL_SOCK_DISCONNECT);
return NL_INVALID;
}
}
break;
case NL_UNRELIABLE:
{
if(sock->connected == NL_TRUE)
{
/* check for broken connection */
if(sock->ext->consock == NL_INVALID)
{
nlSetError(NL_SOCK_DISCONNECT);
return NL_INVALID;
}
count = loopback_WritePacket(sock->ext->consock, buffer, nbytes, sock->localport);
}
else if(sock->connecting == NL_TRUE)
{
nlSetError(NL_CON_PENDING);
return NL_INVALID;
}
/* unconnected UDP emulation */
count = nbytes;
(void)nlGroupGetSockets(loopgroup, (NLsocket *)s, &number);
for(i=0;i<number;i++)
{
if(nlIsValidSocket(s[i]) == NL_TRUE)
{
othersock = nlSockets[s[i]];
if(sock->remoteport == othersock->localport &&
othersock->connected == NL_FALSE &&
sock->type == othersock->type)
{
(void)loopback_WritePacket(s[i], buffer, nbytes, sock->localport);
}
}
}
}
break;
case NL_BROADCAST:
{
count = nbytes;
(void)nlGroupGetSockets(loopgroup, (NLsocket *)s, &number);
for(i=0;i<number;i++)
{
if(nlIsValidSocket(s[i]) == NL_TRUE)
{
othersock = nlSockets[s[i]];
if(sock->localport == othersock->localport &&
sock->type == othersock->type)
{
(void)loopback_WritePacket(s[i], buffer, nbytes, sock->localport);
}
}
}
}
}
return count;
}
NLchar *loopback_AddrToString(const NLaddress *address, NLchar *string)
{
_stprintf(string, TEXT("127.0.0.1:%u"), loopback_GetPortFromAddr(address));
return string;
}
NLboolean loopback_StringToAddr(const NLchar *string, NLaddress *address)
{
NLchar *st;
NLint port;
memset(address, 0, sizeof(NLaddress));
address->valid = NL_TRUE;
/* check for a port number */
st = _tcschr(string, TEXT(':'));
if(st != NULL)
{
st++;
port = _ttoi(st);
if(port < 0 || port > 65535)
{
nlSetError(NL_BAD_ADDR);
address->valid = NL_FALSE;
return NL_FALSE;
}
loopback_SetAddrPort(address, (NLushort)port);
}
return NL_TRUE;
}
NLboolean loopback_GetLocalAddr(NLsocket socket, NLaddress *address)
{
nl_socket_t *sock = nlSockets[socket];
memset(address, 0, sizeof(NLaddress));
loopback_SetAddrPort(address, sock->localport);
address->valid = NL_TRUE;
return NL_TRUE;
}
NLaddress *loopback_GetAllLocalAddr(NLint *count)
{
*count = 1;
memset(&loopback_ouraddress, 0, sizeof(NLaddress));
loopback_ouraddress.valid = NL_TRUE;
return &loopback_ouraddress;
}
NLboolean loopback_SetLocalAddr(const NLaddress *address)
{
/* this is just to keep compilers happy */
if(address == NULL)
{
return NL_FALSE;
}
return NL_TRUE;
}
NLchar *loopback_GetNameFromAddr(const NLaddress *address, NLchar *name)
{
_stprintf(name, TEXT("%s:%u"), TEXT("localhost"), loopback_GetPortFromAddr(address));
return name;
}
NLboolean loopback_GetNameFromAddrAsync(const NLaddress *address, NLchar *name)
{
(void)loopback_GetNameFromAddr(address, name);
return NL_TRUE;
}
NLboolean loopback_GetAddrFromName(const NLchar *name, NLaddress *address)
{
return loopback_StringToAddr(name, address);
}
NLboolean loopback_GetAddrFromNameAsync(const NLchar *name, NLaddress *address)
{
return loopback_GetAddrFromName(name, address);
}
NLboolean loopback_AddrCompare(const NLaddress *address1, const NLaddress *address2)
{
if(*(NLushort *)(&address1->addr[0]) == *(NLushort *)(&address2->addr[0]))
{
return NL_TRUE;
}
return NL_FALSE;
}
NLushort loopback_GetPortFromAddr(const NLaddress *address)
{
return *(NLushort *)(&address->addr[0]);
}
void loopback_SetAddrPort(NLaddress *address, NLushort port)
{
*(NLushort *)(&address->addr[0]) = port;
}
NLint loopback_GetSystemError(void)
{
return errno;
}
NLint loopback_PollGroup(NLint group, NLenum name, NLsocket *sockets, NLint number, NLint timeout)
{
NLint count = 0;
NLint numsockets = NL_MAX_GROUP_SOCKETS;
NLsocket temp[NL_MAX_GROUP_SOCKETS];
NLtime end, now;
nlGroupLock();
if(nlGroupGetSocketsINT(group, (NLsocket *)&temp, &numsockets) == NL_FALSE)
{
/* any error is set by nlGroupGetSockets */
nlGroupUnlock();
return NL_INVALID;
}
nlGroupUnlock();
if(numsockets == 0)
{
return 0;
}
(void)nlTime(&now);
end.seconds = now.seconds;
end.mseconds = now.mseconds;
if(timeout > 0)
{
end.mseconds += timeout;
while(end.mseconds > 999)
{
end.mseconds -= 1000;
end.seconds++;
}
}
while(count == 0)
{
switch(name) {
case NL_READ_STATUS:
{
NLint i = 0;
NLint j = numsockets;
while(j-- > 0)
{
/* check for a packet */
nl_socket_t *sock;
if(nlIsValidSocket(temp[i]) != NL_TRUE)
{
nlSetError(NL_INVALID_SOCKET);
return NL_INVALID;
}
sock = nlSockets[temp[i]];
if(sock->ext->inlen[sock->ext->nextinused] != 0)
{
*sockets = temp[i];
sockets++;
count++;
if(count > number)
{
nlSetError(NL_BUFFER_SIZE);
return NL_INVALID;
}
}
i++;
}
}
break;
case NL_WRITE_STATUS:
{
NLint i = 0;
NLint j = numsockets;
while(j-- > 0)
{
nl_socket_t *sock;
if(nlIsValidSocket(temp[i]) != NL_TRUE)
{
nlSetError(NL_INVALID_SOCKET);
return NL_INVALID;
}
sock = nlSockets[temp[i]];
/* check for a free packet if reliable and connected */
if((sock->type == NL_TCP || sock->type == NL_TCP_PACKETS)
&& (sock->connecting == NL_TRUE || sock->connected == NL_TRUE))
{
nl_socket_t *othersock = nlSockets[sock->ext->consock];
if(othersock->ext->nextinfree == NL_INVALID)
{
continue;
}
}
/* add the socket to the list */
*sockets = temp[i];
sockets++;
count++;
if(count > number)
{
nlSetError(NL_BUFFER_SIZE);
return NL_INVALID;
}
i++;
}
}
break;
case NL_ERROR_STATUS:
{
NLint i = 0;
NLint j = numsockets;
while(j-- > 0)
{
nl_socket_t *sock;
if(nlIsValidSocket(temp[i]) != NL_TRUE)
{
nlSetError(NL_INVALID_SOCKET);
return NL_INVALID;
}
sock = nlSockets[temp[i]];
if(sock->connected == NL_FALSE && sock->type != NL_UDP_BROADCAST)
{
/* add the socket to the list */
*sockets = temp[i];
sockets++;
count++;
if(count > number)
{
nlSetError(NL_BUFFER_SIZE);
return NL_INVALID;
}
i++;
}
}
}
break;
default:
nlSetError(NL_INVALID_ENUM);
return NL_INVALID;
}
if(timeout != 0)
{
nlThreadSleep(1);
(void)nlTime(&now);
if(timeout > 0 && (now.seconds > end.seconds || (now.seconds == end.seconds && now.mseconds > end.mseconds)))
break;
}
else
{
break;
}
}
return count;
}
NLboolean loopback_Hint(NLenum name, NLint arg)
{
switch (name) {
case NL_REUSE_ADDRESS:
reuseaddress = (NLboolean)(arg != 0 ? NL_TRUE : NL_FALSE);
break;
default:
nlSetError(NL_INVALID_ENUM);
return NL_FALSE;
}
return NL_TRUE;
}
#endif /* NL_INCLUDE_LOOPBACK */
| ProfessorKaos64/openlierox | libs/hawknl/src/loopback.c | C | lgpl-2.1 | 27,238 |
/****************************************************************************
**
** Copyright (C) 2014 Digia Plc and/or its subsidiary(-ies).
** Contact: http://www.qt-project.org/legal
**
** This file is part of Qt Creator.
**
** Commercial License Usage
** Licensees holding valid commercial Qt licenses may use this file in
** accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and Digia. For licensing terms and
** conditions see http://qt.digia.com/licensing. For further information
** use the contact form at http://qt.digia.com/contact-us.
**
** GNU Lesser General Public License Usage
** Alternatively, this file may be used under the terms of the GNU Lesser
** General Public License version 2.1 as published by the Free Software
** Foundation and appearing in the file LICENSE.LGPL included in the
** packaging of this file. Please review the following information to
** ensure the GNU Lesser General Public License version 2.1 requirements
** will be met: http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** In addition, as a special exception, Digia gives you certain additional
** rights. These rights are described in the Digia Qt LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
****************************************************************************/
#include "qtquickappwizard.h"
#include "qtquickapp.h"
#include "qtquickappwizardpages.h"
#include "../qmakeprojectmanagerconstants.h"
#include <qtsupport/qtsupportconstants.h>
#include <qtsupport/baseqtversion.h>
#include <projectexplorer/projectexplorerconstants.h>
#include <projectexplorer/targetsetuppage.h>
#include <QIcon>
namespace QmakeProjectManager {
namespace Internal {
class QtQuickAppWizardDialog : public AbstractMobileAppWizardDialog
{
Q_OBJECT
public:
explicit QtQuickAppWizardDialog(QWidget *parent, const Core::WizardDialogParameters ¶meters);
TemplateInfo templateInfo() const;
protected:
void initializePage(int id);
private:
QtQuickComponentSetPage *m_componentSetPage;
};
QtQuickAppWizardDialog::QtQuickAppWizardDialog(QWidget *parent,
const Core::WizardDialogParameters ¶meters)
: AbstractMobileAppWizardDialog(parent,
QtSupport::QtVersionNumber(4, 7, 0),
QtSupport::QtVersionNumber(5, INT_MAX, INT_MAX), parameters)
{
setWindowTitle(tr("New Qt Quick Application"));
setIntroDescription(tr("This wizard generates a Qt Quick Application project."));
m_componentSetPage = new Internal::QtQuickComponentSetPage;
addPageWithTitle(m_componentSetPage, tr("Component Set"));
addKitsPage();
}
void QtQuickAppWizardDialog::initializePage(int id)
{
if (page(id) == kitsPage()) {
QStringList stringList =
templateInfo().featuresRequired.split(QLatin1Char(','), QString::SkipEmptyParts);
Core::FeatureSet features;
foreach (const QString &string, stringList) {
Core::Feature feature(Core::Id::fromString(string.trimmed()));
features |= feature;
}
setRequiredFeatures(features);
updateKitsPage();
}
AbstractMobileAppWizardDialog::initializePage(id);
}
TemplateInfo QtQuickAppWizardDialog::templateInfo() const
{
return m_componentSetPage->templateInfo();
}
class QtQuickAppWizardPrivate
{
class QtQuickApp *app;
class QtQuickAppWizardDialog *wizardDialog;
friend class QtQuickAppWizard;
};
QtQuickAppWizard::QtQuickAppWizard()
: d(new QtQuickAppWizardPrivate)
{
setWizardKind(ProjectWizard);
setIcon(QIcon(QLatin1String(QmakeProjectManager::Constants::ICON_QTQUICK_APP)));
setId(QLatin1String("D.QMLA Application"));
setCategory(QLatin1String(ProjectExplorer::Constants::QT_APPLICATION_WIZARD_CATEGORY));
setDisplayCategory(QLatin1String(ProjectExplorer::Constants::QT_APPLICATION_WIZARD_CATEGORY_DISPLAY));
setDisplayName(tr("Qt Quick Application"));
setDescription(tr("Creates a Qt Quick application project that can contain both QML and C++ code."));
setRequiredFeatures(Core::Feature(QtSupport::Constants::FEATURE_QT_QUICK));
d->app = new QtQuickApp;
d->wizardDialog = 0;
}
QtQuickAppWizard::~QtQuickAppWizard()
{
delete d->app;
delete d;
}
AbstractMobileAppWizardDialog *QtQuickAppWizard::createWizardDialogInternal(QWidget *parent,
const Core::WizardDialogParameters ¶meters) const
{
d->wizardDialog = new QtQuickAppWizardDialog(parent, parameters);
return d->wizardDialog;
}
void QtQuickAppWizard::projectPathChanged(const QString &path) const
{
if (d->wizardDialog->kitsPage())
d->wizardDialog->kitsPage()->setProjectPath(path);
}
void QtQuickAppWizard::prepareGenerateFiles(const QWizard *w,
QString *errorMessage) const
{
Q_UNUSED(errorMessage)
const QtQuickAppWizardDialog *wizard = qobject_cast<const QtQuickAppWizardDialog*>(w);
d->app->setTemplateInfo(wizard->templateInfo());
}
QString QtQuickAppWizard::fileToOpenPostGeneration() const
{
return d->app->path(QtQuickApp::MainQml);
}
AbstractMobileApp *QtQuickAppWizard::app() const
{
return d->app;
}
AbstractMobileAppWizardDialog *QtQuickAppWizard::wizardDialog() const
{
return d->wizardDialog;
}
} // namespace Internal
} // namespace QmakeProjectManager
#include "qtquickappwizard.moc"
| omniacreator/qtcreator | src/plugins/qmakeprojectmanager/wizards/qtquickappwizard.cpp | C++ | lgpl-2.1 | 5,614 |
#include "myobject.h"
#include <moc_myobject.cpp>
| qt-labs/qbs | tests/auto/blackbox/testdata-qt/included-moc-cpp/myobject.cpp | C++ | lgpl-2.1 | 51 |
/** @file patest_callbackstop.c
@ingroup test_src
@brief Test the paComplete callback result code.
@author Ross Bencina <[email protected]>
*/
/*
* $Id: patest_callbackstop.c 1294 2007-10-24 20:51:22Z bjornroche $
*
* This program uses the PortAudio Portable Audio Library.
* For more information see: http://www.portaudio.com/
* Copyright (c) 1999-2000 Ross Bencina and Phil Burk
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* The text above constitutes the entire PortAudio license; however,
* the PortAudio community also makes the following non-binding requests:
*
* Any person wishing to distribute modifications to the Software is
* requested to send the modifications to the original developer so that
* they can be incorporated into the canonical version. It is also
* requested that these non-binding requests be included along with the
* license above.
*/
#include <stdio.h>
#include <math.h>
#include "portaudio.h"
#define NUM_SECONDS (5)
#define NUM_LOOPS (4)
#define SAMPLE_RATE (44100)
#define FRAMES_PER_BUFFER (67)
#ifndef M_PI
#define M_PI (3.14159265)
#endif
#define TABLE_SIZE (200)
typedef struct
{
float sine[TABLE_SIZE];
int phase;
unsigned long generatedFramesCount;
volatile int callbackReturnedPaComplete;
volatile int callbackInvokedAfterReturningPaComplete;
char message[100];
}
TestData;
/*
This routine will be called by the PortAudio stream when audio is needed.
It may be called at interrupt level on some machines so don't do anything
that could mess up the system like calling malloc() or free().
*/
static int TestCallback( const void *input, void *output,
unsigned long frameCount,
const PaStreamCallbackTimeInfo* timeInfo,
PaStreamCallbackFlags statusFlags,
void *userData )
{
TestData *data = (TestData*)userData;
float *out = (float*)output;
unsigned long i;
float x;
(void) input; /* Prevent unused variable warnings. */
(void) timeInfo;
(void) statusFlags;
if( data->callbackReturnedPaComplete )
data->callbackInvokedAfterReturningPaComplete = 1;
for( i=0; i<frameCount; i++ )
{
/* generate tone */
x = data->sine[ data->phase++ ];
if( data->phase >= TABLE_SIZE )
data->phase -= TABLE_SIZE;
*out++ = x; /* left */
*out++ = x; /* right */
}
data->generatedFramesCount += frameCount;
if( data->generatedFramesCount >= (NUM_SECONDS * SAMPLE_RATE) )
{
data->callbackReturnedPaComplete = 1;
return paComplete;
}
else
{
return paContinue;
}
}
/*
* This routine is called by portaudio when playback is done.
*/
static void StreamFinished( void* userData )
{
TestData *data = (TestData *) userData;
printf( "Stream Completed: %s\n", data->message );
}
/*----------------------------------------------------------------------------*/
int main(void);
int main(void)
{
PaStreamParameters outputParameters;
PaStream *stream;
PaError err;
TestData data;
int i, j;
printf( "PortAudio Test: output sine wave. SR = %d, BufSize = %d\n",
SAMPLE_RATE, FRAMES_PER_BUFFER );
/* initialise sinusoidal wavetable */
for( i=0; i<TABLE_SIZE; i++ )
{
data.sine[i] = (float) sin( ((double)i/(double)TABLE_SIZE) * M_PI * 2. );
}
err = Pa_Initialize();
if( err != paNoError ) goto error;
outputParameters.device = Pa_GetDefaultOutputDevice();
if (outputParameters.device == paNoDevice) {
fprintf(stderr,"Error: No default output device.\n");
goto error;
}
outputParameters.channelCount = 2; /* stereo output */
outputParameters.sampleFormat = paFloat32; /* 32 bit floating point output */
outputParameters.suggestedLatency = Pa_GetDeviceInfo( outputParameters.device )->defaultLowOutputLatency;
outputParameters.hostApiSpecificStreamInfo = NULL;
err = Pa_OpenStream(
&stream,
NULL, /* no input */
&outputParameters,
SAMPLE_RATE,
FRAMES_PER_BUFFER,
paClipOff, /* output will be in-range, so no need to clip */
TestCallback,
&data );
if( err != paNoError ) goto error;
sprintf( data.message, "Loop: XX" );
err = Pa_SetStreamFinishedCallback( stream, &StreamFinished );
if( err != paNoError ) goto error;
printf("Repeating test %d times.\n", NUM_LOOPS );
for( i=0; i < NUM_LOOPS; ++i )
{
data.phase = 0;
data.generatedFramesCount = 0;
data.callbackReturnedPaComplete = 0;
data.callbackInvokedAfterReturningPaComplete = 0;
sprintf( data.message, "Loop: %d", i );
err = Pa_StartStream( stream );
if( err != paNoError ) goto error;
printf("Play for %d seconds.\n", NUM_SECONDS );
/* wait for the callback to complete generating NUM_SECONDS of tone */
do
{
Pa_Sleep( 500 );
}
while( !data.callbackReturnedPaComplete );
printf( "Callback returned paComplete.\n" );
printf( "Waiting for buffers to finish playing...\n" );
/* wait for stream to become inactive,
or for a timeout of approximately NUM_SECONDS
*/
j = 0;
while( (err = Pa_IsStreamActive( stream )) == 1 && j < NUM_SECONDS * 2 )
{
printf(".\n" );
Pa_Sleep( 500 );
++j;
}
if( err < 0 )
{
goto error;
}
else if( err == 1 )
{
printf( "TEST FAILED: Timed out waiting for buffers to finish playing.\n" );
}
else
{
printf("Buffers finished.\n" );
}
if( data.callbackInvokedAfterReturningPaComplete )
{
printf( "TEST FAILED: Callback was invoked after returning paComplete.\n" );
}
err = Pa_StopStream( stream );
if( err != paNoError ) goto error;
printf( "sleeping for 1 second...\n" );
Pa_Sleep( 1000 );
}
err = Pa_CloseStream( stream );
if( err != paNoError ) goto error;
Pa_Terminate();
printf("Test finished.\n");
return err;
error:
Pa_Terminate();
fprintf( stderr, "An error occured while using the portaudio stream\n" );
fprintf( stderr, "Error number: %d\n", err );
fprintf( stderr, "Error message: %s\n", Pa_GetErrorText( err ) );
return err;
}
| litalidev/sipxtapi | sipXmediaLib/contrib/portaudio_v19/test/patest_callbackstop.c | C | lgpl-2.1 | 7,765 |
/*
* Copyright (c) 2014, 2016, Codice
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
package org.codice.imaging.cgm;
import java.awt.Graphics2D;
import java.awt.Point;
import java.io.IOException;
class VdcExtentElement extends ElementHelpers implements AbstractElement {
private VdcExtent vdcExtent;
VdcExtentElement() {
super(CgmIdentifier.VDC_EXTENT);
}
@Override
public void readParameters(final CgmInputReader dataReader, final int parameterListLength) throws IOException {
Point lowerLeft = dataReader.readPoint();
Point upperRight = dataReader.readPoint();
vdcExtent = new VdcExtent(lowerLeft, upperRight);
}
@Override
public void addStringDescription(final StringBuilder builder) {
builder.append("\tVDC Extent: ");
builder.append(vdcExtent.toString());
builder.append(System.lineSeparator());
}
@Override
public void render(final Graphics2D g2, final CgmGraphicState graphicState) {
graphicState.setVdcExtent(vdcExtent);
double scaleX = 1.0;
double translateX = 0.0;
if (vdcExtent.isIncreasingLeft()) {
scaleX = -1.0;
translateX = graphicState.getSizeX();
}
double scaleY = 1.0;
double translateY = 0.0;
if (!vdcExtent.isIncreasingUp()) {
scaleY = -1.0;
translateY = (graphicState.getSizeY());
}
if (scaleX < 0) {
g2.translate(translateX, 0);
}
if (scaleY < 0) {
g2.translate(0, translateY);
}
g2.scale(scaleX, scaleY);
}
}
| bradh/imaging-nitf | cgm/src/main/java/org/codice/imaging/cgm/VdcExtentElement.java | Java | lgpl-2.1 | 2,988 |
/**
* @file
* Header for showing progress dialogs.
*
* @author Jeremy A. Mowery [email protected]
* @author Jason Tang [email protected]
*
* Copyright (C) 2006-2007 Tresys Technology, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef PROGRESS_H
#define PROGRESS_H
typedef struct progress progress_t;
#include "toplevel.h"
#include <apol/policy.h>
#include <poldiff/poldiff.h>
/**
* Allocate and return a new progress dialog object.
*
* @param top Toplevel object that will control the progress object.
*
* @return An initialized progress object, or NULL upon error. The
* caller is responsible for calling progress_destroy() afterwards.
*/
progress_t *progress_create(toplevel_t * top);
/**
* Destroy a progress dialog. Does nothing if the pointer is already
* NULL.
*
* @param prefs Reference to a progress object to destroy. This will
* be set to NULL afterwards.
*/
void progress_destroy(progress_t ** progress);
/**
* Display a progress dialog.
*
* @param progress Progress dialog to show.
* @param title Title for the progress window.
*/
void progress_show(progress_t * progress, const char *title);
/**
* Hide the progress dialog. Note that this does not actually destroy
* the object.
*
* @param progress Progress dialog to hide.
*/
void progress_hide(progress_t * progress);
/* the rest of these are for multi-threaded progress dialog */
/**
* Block the current thread until the progress dialog receives a done
* signal via progress_done() or progress_abort(). The dialog will
* periodically awake and update the user interface, based upon
* message received by its handle implementations.
*
* @param progress Progress object to wait against.
*
* @return 0 if the progress object got a progress_done(), < 0 if
* progress_abort().
*/
int progress_wait(progress_t * progress);
/**
* Signal to a progress object that this thread is ending
* successfully. This will cause all threads waiting upon the
* progress object to resume.
*
* @param progress Progress object to signal completion.
*/
void progress_done(progress_t * progress);
/**
* Signal to a progress object that this thread completed with
* warnings. This will cause all threads waiting upon the progress
* object to resume.
*
* @param progress Progress object to signal completion.
* @param reason Explanation for warning, or NULL to use most recently
* written message as the reason.
*/
void progress_warn(progress_t * progress, char *reason, ...) __attribute__ ((format(printf, 2, 3)));
/**
* Signal to a progress object that this thread is aborting. This
* will cause all threads waiting upon the progress object to resume.
*
* @param progress Progress object to signal completion.
* @param reason Explanation for abort, or NULL to abort for no
* reason. The most recently written message will be used as the
* reason.
*/
void progress_abort(progress_t * progress, char *reason, ...) __attribute__ ((format(printf, 2, 3)));
/**
* Have the progress dialog show a message upon its next refresh.
*
* @param progress Progress object to update.
* @param fmt Format for string to display.
*/
void progress_update(progress_t * progress, char *fmt, ...) __attribute__ ((format(printf, 2, 3)));
/**
* Implementation of libpoldiff's message callback function. This
* will route messages generated by libpoldiff to the progress
* dialog's display. To use this, pass the progress_t object as
* poldiff_create()'s callback_arg parameter.
*/
void progress_poldiff_handle_func(void *arg, const poldiff_t * diff, int level, const char *fmt, va_list va_args);
/**
* Implementation of a libapol message callback function. This will
* route messages generated by libapol to the progress dialog's
* display. To use this, pass the progress_t object as
* apol_policy_open()'s varg parameter.
*/
void progress_apol_handle_func(void *varg, const apol_policy_t * p, int level, const char *fmt, va_list argp);
#endif
| pasis/setools | sediff/progress.h | C | lgpl-2.1 | 4,665 |
/* GLib testing framework examples and tests
* Copyright (C) 2008 Imendio AB
* Authors: Tim Janik
*
* This work is provided "as is"; redistribution and modification
* in whole or in part, in any medium, physical or electronic is
* permitted without restriction.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* In no event shall the authors or contributors be liable for any
* direct, indirect, incidental, special, exemplary, or consequential
* damages (including, but not limited to, procurement of substitute
* goods or services; loss of use, data, or profits; or business
* interruption) however caused and on any theory of liability, whether
* in contract, strict liability, or tort (including negligence or
* otherwise) arising in any way out of the use of this software, even
* if advised of the possibility of such damage.
*/
#define GLIB_DISABLE_DEPRECATION_WARNINGS
#include <glib.h>
#include <glib-object.h>
static volatile int mtsafe_call_counter = 0; /* multi thread safe call counter */
static int unsafe_call_counter = 0; /* single-threaded call counter */
static GCond sync_cond;
static GMutex sync_mutex;
#define NUM_COUNTER_INCREMENTS 100000
static void
call_counter_init (gpointer tclass)
{
int i;
for (i = 0; i < NUM_COUNTER_INCREMENTS; i++)
{
int saved_unsafe_call_counter = unsafe_call_counter;
g_atomic_int_add (&mtsafe_call_counter, 1); /* real call count update */
g_thread_yield(); /* let concurrent threads corrupt the unsafe_call_counter state */
unsafe_call_counter = 1 + saved_unsafe_call_counter; /* non-atomic counter update */
}
}
static void interface_per_class_init (void) { call_counter_init (NULL); }
/* define 3 test interfaces */
typedef GTypeInterface MyFace0Interface;
static GType my_face0_get_type (void);
G_DEFINE_INTERFACE (MyFace0, my_face0, G_TYPE_OBJECT)
static void my_face0_default_init (MyFace0Interface *iface) { call_counter_init (iface); }
typedef GTypeInterface MyFace1Interface;
static GType my_face1_get_type (void);
G_DEFINE_INTERFACE (MyFace1, my_face1, G_TYPE_OBJECT)
static void my_face1_default_init (MyFace1Interface *iface) { call_counter_init (iface); }
/* define 3 test objects, adding interfaces 0 & 1, and adding interface 2 after class initialization */
typedef GObject MyTester0;
typedef GObjectClass MyTester0Class;
static GType my_tester0_get_type (void);
G_DEFINE_TYPE_WITH_CODE (MyTester0, my_tester0, G_TYPE_OBJECT,
G_IMPLEMENT_INTERFACE (my_face0_get_type(), interface_per_class_init)
G_IMPLEMENT_INTERFACE (my_face1_get_type(), interface_per_class_init))
static void my_tester0_init (MyTester0*t) {}
static void my_tester0_class_init (MyTester0Class*c) { call_counter_init (c); }
typedef GObject MyTester1;
typedef GObjectClass MyTester1Class;
/* Disabled for now (see https://bugzilla.gnome.org/show_bug.cgi?id=687659) */
#if 0
typedef GTypeInterface MyFace2Interface;
static GType my_face2_get_type (void);
G_DEFINE_INTERFACE (MyFace2, my_face2, G_TYPE_OBJECT)
static void my_face2_default_init (MyFace2Interface *iface) { call_counter_init (iface); }
static GType my_tester1_get_type (void);
G_DEFINE_TYPE_WITH_CODE (MyTester1, my_tester1, G_TYPE_OBJECT,
G_IMPLEMENT_INTERFACE (my_face0_get_type(), interface_per_class_init)
G_IMPLEMENT_INTERFACE (my_face1_get_type(), interface_per_class_init))
static void my_tester1_init (MyTester1*t) {}
static void my_tester1_class_init (MyTester1Class*c) { call_counter_init (c); }
typedef GObject MyTester2;
typedef GObjectClass MyTester2Class;
static GType my_tester2_get_type (void);
G_DEFINE_TYPE_WITH_CODE (MyTester2, my_tester2, G_TYPE_OBJECT,
G_IMPLEMENT_INTERFACE (my_face0_get_type(), interface_per_class_init)
G_IMPLEMENT_INTERFACE (my_face1_get_type(), interface_per_class_init))
static void my_tester2_init (MyTester2*t) {}
static void my_tester2_class_init (MyTester2Class*c) { call_counter_init (c); }
static gpointer
tester_init_thread (gpointer data)
{
const GInterfaceInfo face2_interface_info = { (GInterfaceInitFunc) interface_per_class_init, NULL, NULL };
gpointer klass;
/* first, syncronize with other threads,
* then run interface and class initializers,
* using unsafe_call_counter concurrently
*/
g_mutex_lock (&sync_mutex);
g_mutex_unlock (&sync_mutex);
/* test default interface initialization for face0 */
g_type_default_interface_unref (g_type_default_interface_ref (my_face0_get_type()));
/* test class initialization, face0 per-class initializer, face1 default and per-class initializer */
klass = g_type_class_ref ((GType) data);
/* test face2 default and per-class initializer, after class_init */
g_type_add_interface_static (G_TYPE_FROM_CLASS (klass), my_face2_get_type(), &face2_interface_info);
/* cleanups */
g_type_class_unref (klass);
return NULL;
}
static void
test_threaded_class_init (void)
{
GThread *t1, *t2, *t3;
/* pause newly created threads */
g_mutex_lock (&sync_mutex);
/* create threads */
t1 = g_thread_create (tester_init_thread, (gpointer) my_tester0_get_type(), TRUE, NULL);
t2 = g_thread_create (tester_init_thread, (gpointer) my_tester1_get_type(), TRUE, NULL);
t3 = g_thread_create (tester_init_thread, (gpointer) my_tester2_get_type(), TRUE, NULL);
/* execute threads */
g_mutex_unlock (&sync_mutex);
while (g_atomic_int_get (&mtsafe_call_counter) < (3 + 3 + 3 * 3) * NUM_COUNTER_INCREMENTS)
{
if (g_test_verbose())
g_printerr ("Initializers counted: %u\n", g_atomic_int_get (&mtsafe_call_counter));
g_usleep (50 * 1000); /* wait for threads to complete */
}
if (g_test_verbose())
g_printerr ("Total initializers: %u\n", g_atomic_int_get (&mtsafe_call_counter));
/* ensure non-corrupted counter updates */
g_assert_cmpint (g_atomic_int_get (&mtsafe_call_counter), ==, unsafe_call_counter);
g_thread_join (t1);
g_thread_join (t2);
g_thread_join (t3);
}
#endif
typedef struct {
GObject parent;
char *name;
} PropTester;
typedef GObjectClass PropTesterClass;
static GType prop_tester_get_type (void);
G_DEFINE_TYPE (PropTester, prop_tester, G_TYPE_OBJECT)
#define PROP_NAME 1
static void
prop_tester_init (PropTester* t)
{
if (t->name == NULL)
; /* neds unit test framework initialization: g_test_bug ("race initializing properties"); */
}
static void
prop_tester_set_property (GObject *object,
guint property_id,
const GValue *value,
GParamSpec *pspec)
{}
static void
prop_tester_class_init (PropTesterClass *c)
{
int i;
GParamSpec *param;
GObjectClass *gobject_class = G_OBJECT_CLASS (c);
gobject_class->set_property = prop_tester_set_property; /* silence GObject checks */
g_mutex_lock (&sync_mutex);
g_cond_signal (&sync_cond);
g_mutex_unlock (&sync_mutex);
for (i = 0; i < 100; i++) /* wait a bit. */
g_thread_yield();
call_counter_init (c);
param = g_param_spec_string ("name", "name_i18n",
"yet-more-wasteful-i18n",
NULL,
G_PARAM_CONSTRUCT_ONLY | G_PARAM_WRITABLE |
G_PARAM_STATIC_NAME | G_PARAM_STATIC_BLURB |
G_PARAM_STATIC_NICK);
g_object_class_install_property (gobject_class, PROP_NAME, param);
}
static gpointer
object_create (gpointer data)
{
GObject *obj = g_object_new (prop_tester_get_type(), "name", "fish", NULL);
g_object_unref (obj);
return NULL;
}
static void
test_threaded_object_init (void)
{
GThread *creator;
g_mutex_lock (&sync_mutex);
creator = g_thread_create (object_create, NULL, TRUE, NULL);
/* really provoke the race */
g_cond_wait (&sync_cond, &sync_mutex);
object_create (NULL);
g_mutex_unlock (&sync_mutex);
g_thread_join (creator);
}
typedef struct {
MyTester0 *strong;
guint unref_delay;
} UnrefInThreadData;
static gpointer
unref_in_thread (gpointer p)
{
UnrefInThreadData *data = p;
g_usleep (data->unref_delay);
g_object_unref (data->strong);
return NULL;
}
/* undefine to see this test fail without GWeakRef */
#define HAVE_G_WEAK_REF
#define SLEEP_MIN_USEC 1
#define SLEEP_MAX_USEC 10
static void
test_threaded_weak_ref (void)
{
guint i;
guint get_wins = 0, unref_wins = 0;
guint n;
if (g_test_thorough ())
n = NUM_COUNTER_INCREMENTS;
else
n = NUM_COUNTER_INCREMENTS / 20;
#ifdef G_OS_WIN32
/* On Windows usleep has millisecond resolution and gets rounded up
* leading to the test running for a long time. */
n /= 10;
#endif
for (i = 0; i < n; i++)
{
UnrefInThreadData data;
#ifdef HAVE_G_WEAK_REF
/* GWeakRef<MyTester0> in C++ terms */
GWeakRef weak;
#else
gpointer weak;
#endif
MyTester0 *strengthened;
guint get_delay;
GThread *thread;
GError *error = NULL;
if (g_test_verbose () && (i % (n/20)) == 0)
g_printerr ("%u%%\n", ((i * 100) / n));
/* Have an object and a weak ref to it */
data.strong = g_object_new (my_tester0_get_type (), NULL);
#ifdef HAVE_G_WEAK_REF
g_weak_ref_init (&weak, data.strong);
#else
weak = data.strong;
g_object_add_weak_pointer ((GObject *) weak, &weak);
#endif
/* Delay for a random time on each side of the race, to perturb the
* timing. Ideally, we want each side to win half the races; on
* smcv's laptop, these timings are about right.
*/
data.unref_delay = g_random_int_range (SLEEP_MIN_USEC / 2, SLEEP_MAX_USEC / 2);
get_delay = g_random_int_range (SLEEP_MIN_USEC, SLEEP_MAX_USEC);
/* One half of the race is to unref the shared object */
thread = g_thread_create (unref_in_thread, &data, TRUE, &error);
g_assert_no_error (error);
/* The other half of the race is to get the object from the "global
* singleton"
*/
g_usleep (get_delay);
#ifdef HAVE_G_WEAK_REF
strengthened = g_weak_ref_get (&weak);
#else
/* Spot the unsafe pointer access! In GDBusConnection this is rather
* better-hidden, but ends up with essentially the same thing, albeit
* cleared in dispose() rather than by a traditional weak pointer
*/
strengthened = weak;
if (strengthened != NULL)
g_object_ref (strengthened);
#endif
if (strengthened != NULL)
g_assert (G_IS_OBJECT (strengthened));
/* Wait for the thread to run */
g_thread_join (thread);
if (strengthened != NULL)
{
get_wins++;
g_assert (G_IS_OBJECT (strengthened));
g_object_unref (strengthened);
}
else
{
unref_wins++;
}
#ifdef HAVE_G_WEAK_REF
g_weak_ref_clear (&weak);
#else
if (weak != NULL)
g_object_remove_weak_pointer (weak, &weak);
#endif
}
if (g_test_verbose ())
g_printerr ("Race won by get %u times, unref %u times\n",
get_wins, unref_wins);
}
int
main (int argc,
char *argv[])
{
g_test_init (&argc, &argv, NULL);
/* g_test_add_func ("/GObject/threaded-class-init", test_threaded_class_init); */
g_test_add_func ("/GObject/threaded-object-init", test_threaded_object_init);
g_test_add_func ("/GObject/threaded-weak-ref", test_threaded_weak_ref);
return g_test_run();
}
| endlessm/glib | gobject/tests/threadtests.c | C | lgpl-2.1 | 11,565 |
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<div class="refnamediv">
<h2><span class="refentrytitle">Function template operator<<</span></h2>
<p>boost::log::operator<<</p>
</div>
<h2 xmlns:rev="http://www.cs.rpi.edu/~gregod/boost/tools/doc/revision" class="refsynopsisdiv-title">Synopsis</h2>
<div xmlns:rev="http://www.cs.rpi.edu/~gregod/boost/tools/doc/revision" class="refsynopsisdiv"><pre class="synopsis"><span class="comment">// In header: <<a class="link" href="../../attributes.html#header.boost.log.attributes.attribute_name_hpp" title="Header <boost/log/attributes/attribute_name.hpp>">boost/log/attributes/attribute_name.hpp</a>>
</span>
<span class="keyword">template</span><span class="special"><</span><span class="keyword">typename</span> CharT<span class="special">,</span> <span class="keyword">typename</span> TraitsT<span class="special">></span>
<span class="identifier">std</span><span class="special">::</span><span class="identifier">basic_ostream</span><span class="special"><</span> <span class="identifier">CharT</span><span class="special">,</span> <span class="identifier">TraitsT</span> <span class="special">></span> <span class="special">&</span>
<span class="keyword">operator</span><span class="special"><<</span><span class="special">(</span><span class="identifier">std</span><span class="special">::</span><span class="identifier">basic_ostream</span><span class="special"><</span> <span class="identifier">CharT</span><span class="special">,</span> <span class="identifier">TraitsT</span> <span class="special">></span> <span class="special">&</span> strm<span class="special">,</span>
<a class="link" href="attribute_name.html" title="Class attribute_name">attribute_name</a> <span class="keyword">const</span> <span class="special">&</span> name<span class="special">)</span><span class="special">;</span></pre></div>
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<td align="right"><div class="copyright-footer">Copyright © 2007-2021 Andrey Semashev<p>
Distributed under the Boost Software License, Version 1.0. (See accompanying
file LICENSE_1_0.txt or copy at <a href="http://www.boost.org/LICENSE_1_0.txt" target="_top">http://www.boost.org/LICENSE_1_0.txt</a>).
</p>
</div></td>
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| qianqians/abelkhan | cpp_component/3rdparty/boost/libs/log/doc/html/boost/log/operator_idm23683.html | HTML | lgpl-2.1 | 4,455 |
/****************************************************************************
**
** Copyright (C) 2014 Digia Plc and/or its subsidiary(-ies).
** Contact: http://www.qt-project.org/legal
**
** This file is part of Qt Creator.
**
** Commercial License Usage
** Licensees holding valid commercial Qt licenses may use this file in
** accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and Digia. For licensing terms and
** conditions see http://qt.digia.com/licensing. For further information
** use the contact form at http://qt.digia.com/contact-us.
**
** GNU Lesser General Public License Usage
** Alternatively, this file may be used under the terms of the GNU Lesser
** General Public License version 2.1 as published by the Free Software
** Foundation and appearing in the file LICENSE.LGPL included in the
** packaging of this file. Please review the following information to
** ensure the GNU Lesser General Public License version 2.1 requirements
** will be met: http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** In addition, as a special exception, Digia gives you certain additional
** rights. These rights are described in the Digia Qt LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
****************************************************************************/
#include "settingspage.h"
#include "designersettings.h"
#include "qmldesignerconstants.h"
#include "qmldesignerplugin.h"
#include <qmljseditor/qmljseditorconstants.h>
#include <QTextStream>
using namespace QmlDesigner;
using namespace QmlDesigner::Internal;
SettingsPageWidget::SettingsPageWidget(QWidget *parent) :
QWidget(parent)
{
m_ui.setupUi(this);
connect(m_ui.designerEnableDebuggerCheckBox, SIGNAL(toggled(bool)), this, SLOT(debugViewEnabledToggled(bool)));
}
DesignerSettings SettingsPageWidget::settings() const
{
DesignerSettings designerSettings;
designerSettings.itemSpacing = m_ui.spinItemSpacing->value();
designerSettings.containerPadding = m_ui.spinSnapMargin->value();
designerSettings.canvasWidth = m_ui.spinCanvasWidth->value();
designerSettings.canvasHeight = m_ui.spinCanvasHeight->value();
designerSettings.warningsInDesigner = m_ui.designerWarningsCheckBox->isChecked();
designerSettings.designerWarningsInEditor = m_ui.designerWarningsInEditorCheckBox->isChecked();
designerSettings.showDebugView = m_ui.designerShowDebuggerCheckBox->isChecked();
designerSettings.enableDebugView = m_ui.designerEnableDebuggerCheckBox->isChecked();
return designerSettings;
}
void SettingsPageWidget::setSettings(const DesignerSettings &designerSettings)
{
m_ui.spinItemSpacing->setValue(designerSettings.itemSpacing);
m_ui.spinSnapMargin->setValue(designerSettings.containerPadding);
m_ui.spinCanvasWidth->setValue(designerSettings.canvasWidth);
m_ui.spinCanvasHeight->setValue(designerSettings.canvasHeight);
m_ui.designerWarningsCheckBox->setChecked(designerSettings.warningsInDesigner);
m_ui.designerWarningsInEditorCheckBox->setChecked(designerSettings.designerWarningsInEditor);
m_ui.designerShowDebuggerCheckBox->setChecked(designerSettings.showDebugView);
m_ui.designerEnableDebuggerCheckBox->setChecked(designerSettings.enableDebugView);
}
void SettingsPageWidget::debugViewEnabledToggled(bool b)
{
if (b && ! m_ui.designerShowDebuggerCheckBox->isChecked())
m_ui.designerShowDebuggerCheckBox->setChecked(true);
}
SettingsPage::SettingsPage() :
m_widget(0)
{
setId("B.QmlDesigner");
setDisplayName(tr("Qt Quick Designer"));
setCategory(QmlJSEditor::Constants::SETTINGS_CATEGORY_QML);
setDisplayCategory(QCoreApplication::translate("QmlJSEditor",
QmlJSEditor::Constants::SETTINGS_TR_CATEGORY_QML));
setCategoryIcon(QLatin1String(Constants::SETTINGS_CATEGORY_QML_ICON));
}
QWidget *SettingsPage::widget()
{
if (!m_widget) {
m_widget = new SettingsPageWidget;
m_widget->setSettings(QmlDesignerPlugin::instance()->settings());
}
return m_widget;
}
void SettingsPage::apply()
{
if (!m_widget) // page was never shown
return;
QmlDesignerPlugin::instance()->setSettings(m_widget->settings());
}
void SettingsPage::finish()
{
delete m_widget;
}
| omniacreator/qtcreator | src/plugins/qmldesigner/settingspage.cpp | C++ | lgpl-2.1 | 4,395 |
// bdconv.C -- Bulk density convertion for select models.
//
// Copyright 2008 Per Abrahamsen and KVL.
//
// This file is part of Daisy.
//
// Daisy is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser Public License as published by
// the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// Daisy is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser Public License for more details.
//
// You should have received a copy of the GNU Lesser Public License
// along with Daisy; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define BUILD_DLL
#include "bdconv.h"
#include "geometry.h"
#include "soil.h"
#include "volume.h"
#include "units.h"
#include "assertion.h"
#include "mathlib.h"
#include <sstream>
double
BD_convert::operator()(double value) const
{
#if 0
if (!std::isnormal (value))
return 0.0;
std::ostringstream tmp;
tmp << "value = " << value << ", bulk = " << bulk
<< ", in (value) = " << in (value) << ", in (value) / bulk = "
<< in (value) / bulk << ", result = " << out (in (value) / bulk);
Assertion::message (tmp.str ());
#endif
daisy_assert (bulk > 0.0);
return out (in (value) / bulk);
}
bool
BD_convert::valid (double value) const
{
daisy_assert (bulk > 0.0);
return in.valid (value) && out.valid (in (value) / bulk);
}
BD_convert::BD_convert (const Units& units, const symbol has, const symbol want,
const symbol bulk_unit)
: in (units.get_convertion (has, bulk_unit)),
out (units.get_convertion (Units::dry_soil_fraction (), want)),
bulk (-42.42e42)
{
#if 0
std::ostringstream tmp;
tmp << "has = " << has << ", bulk_unit = " << bulk_unit
<< ", dsf = " << Units::dry_soil_fraction () << ", want = " << want;
Assertion::message (tmp.str ());
#endif
}
// bdconv.C ends here.
| sativa/daisy-model | bdconv.C | C++ | lgpl-2.1 | 2,095 |
/// \file
/// \ingroup tutorial_tmva
/// \notebook
/// TMVA Classification Example Using a Convolutional Neural Network
///
/// This is an example of using a CNN in TMVA. We do classification using a toy image data set
/// that is generated when running the example macro
///
/// \macro_image
/// \macro_output
/// \macro_code
///
/// \author Lorenzo Moneta
/***
# TMVA Classification Example Using a Convolutional Neural Network
**/
/// Helper function to create input images data
/// we create a signal and background 2D histograms from 2d gaussians
/// with a location (means in X and Y) different for each event
/// The difference between signal and background is in the gaussian width.
/// The width for the bakground gaussian is slightly larger than the signal width by few % values
///
///
void MakeImagesTree(int n, int nh, int nw)
{
// image size (nh x nw)
const int ntot = nh * nw;
const TString fileOutName = TString::Format("images_data_%dx%d.root", nh, nw);
const int nRndmEvts = 10000; // number of events we use to fill each image
double delta_sigma = 0.1; // 5% difference in the sigma
double pixelNoise = 5;
double sX1 = 3;
double sY1 = 3;
double sX2 = sX1 + delta_sigma;
double sY2 = sY1 - delta_sigma;
auto h1 = new TH2D("h1", "h1", nh, 0, 10, nw, 0, 10);
auto h2 = new TH2D("h2", "h2", nh, 0, 10, nw, 0, 10);
auto f1 = new TF2("f1", "xygaus");
auto f2 = new TF2("f2", "xygaus");
TTree sgn("sig_tree", "signal_tree");
TTree bkg("bkg_tree", "bakground_tree");
TFile f(fileOutName, "RECREATE");
std::vector<float> x1(ntot);
std::vector<float> x2(ntot);
// create signal and background trees with a single branch
// an std::vector<float> of size nh x nw containing the image data
std::vector<float> *px1 = &x1;
std::vector<float> *px2 = &x2;
bkg.Branch("vars", "std::vector<float>", &px1);
sgn.Branch("vars", "std::vector<float>", &px2);
// std::cout << "create tree " << std::endl;
sgn.SetDirectory(&f);
bkg.SetDirectory(&f);
f1->SetParameters(1, 5, sX1, 5, sY1);
f2->SetParameters(1, 5, sX2, 5, sY2);
gRandom->SetSeed(0);
std::cout << "Filling ROOT tree " << std::endl;
for (int i = 0; i < n; ++i) {
if (i % 1000 == 0)
std::cout << "Generating image event ... " << i << std::endl;
h1->Reset();
h2->Reset();
// generate random means in range [3,7] to be not too much on the border
f1->SetParameter(1, gRandom->Uniform(3, 7));
f1->SetParameter(3, gRandom->Uniform(3, 7));
f2->SetParameter(1, gRandom->Uniform(3, 7));
f2->SetParameter(3, gRandom->Uniform(3, 7));
h1->FillRandom("f1", nRndmEvts);
h2->FillRandom("f2", nRndmEvts);
for (int k = 0; k < nh; ++k) {
for (int l = 0; l < nw; ++l) {
int m = k * nw + l;
// add some noise in each bin
x1[m] = h1->GetBinContent(k + 1, l + 1) + gRandom->Gaus(0, pixelNoise);
x2[m] = h2->GetBinContent(k + 1, l + 1) + gRandom->Gaus(0, pixelNoise);
}
}
sgn.Fill();
bkg.Fill();
}
sgn.Write();
bkg.Write();
Info("MakeImagesTree", "Signal and background tree with images data written to the file %s", f.GetName());
sgn.Print();
bkg.Print();
f.Close();
}
void TMVA_CNN_Classification(std::vector<bool> opt = {1, 1, 1, 1})
{
bool useTMVACNN = (opt.size() > 0) ? opt[0] : false;
bool useKerasCNN = (opt.size() > 1) ? opt[1] : false;
bool useTMVADNN = (opt.size() > 2) ? opt[2] : false;
bool useTMVABDT = (opt.size() > 3) ? opt[3] : false;
#ifndef R__HAS_TMVACPU
#ifndef R__HAS_TMVAGPU
Warning("TMVA_CNN_Classification",
"TMVA is not build with GPU or CPU multi-thread support. Cannot use TMVA Deep Learning for CNN");
useTMVACNN = false;
#endif
#endif
bool writeOutputFile = true;
int num_threads = 0; // use default threads
TMVA::Tools::Instance();
// do enable MT running
if (num_threads >= 0) {
ROOT::EnableImplicitMT(num_threads);
if (num_threads > 0) gSystem->Setenv("OMP_NUM_THREADS", TString::Format("%d",num_threads));
}
else
gSystem->Setenv("OMP_NUM_THREADS", "1");
std::cout << "Running with nthreads = " << ROOT::GetThreadPoolSize() << std::endl;
#ifdef R__HAS_PYMVA
gSystem->Setenv("KERAS_BACKEND", "tensorflow");
// for using Keras
TMVA::PyMethodBase::PyInitialize();
#else
useKerasCNN = false;
#endif
TFile *outputFile = nullptr;
if (writeOutputFile)
outputFile = TFile::Open("TMVA_CNN_ClassificationOutput.root", "RECREATE");
/***
## Create TMVA Factory
Create the Factory class. Later you can choose the methods
whose performance you'd like to investigate.
The factory is the major TMVA object you have to interact with. Here is the list of parameters you need to pass
- The first argument is the base of the name of all the output
weightfiles in the directory weight/ that will be created with the
method parameters
- The second argument is the output file for the training results
- The third argument is a string option defining some general configuration for the TMVA session.
For example all TMVA output can be suppressed by removing the "!" (not) in front of the "Silent" argument in the
option string
- note that we disable any pre-transformation of the input variables and we avoid computing correlations between
input variables
***/
TMVA::Factory factory(
"TMVA_CNN_Classification", outputFile,
"!V:ROC:!Silent:Color:AnalysisType=Classification:Transformations=None:!Correlations");
/***
## Declare DataLoader(s)
The next step is to declare the DataLoader class that deals with input variables
Define the input variables that shall be used for the MVA training
note that you may also use variable expressions, which can be parsed by TTree::Draw( "expression" )]
In this case the input data consists of an image of 16x16 pixels. Each single pixel is a branch in a ROOT TTree
**/
TMVA::DataLoader *loader = new TMVA::DataLoader("dataset");
/***
## Setup Dataset(s)
Define input data file and signal and background trees
**/
int imgSize = 16 * 16;
TString inputFileName = "images_data_16x16.root";
// TString inputFileName = "/home/moneta/data/sample_images_32x32.gsoc.root";
bool fileExist = !gSystem->AccessPathName(inputFileName);
// if file does not exists create it
if (!fileExist) {
MakeImagesTree(5000, 16, 16);
}
// TString inputFileName = "tmva_class_example.root";
auto inputFile = TFile::Open(inputFileName);
if (!inputFile) {
Error("TMVA_CNN_Classification", "Error opening input file %s - exit", inputFileName.Data());
return;
}
// --- Register the training and test trees
TTree *signalTree = (TTree *)inputFile->Get("sig_tree");
TTree *backgroundTree = (TTree *)inputFile->Get("bkg_tree");
int nEventsSig = signalTree->GetEntries();
int nEventsBkg = backgroundTree->GetEntries();
// global event weights per tree (see below for setting event-wise weights)
Double_t signalWeight = 1.0;
Double_t backgroundWeight = 1.0;
// You can add an arbitrary number of signal or background trees
loader->AddSignalTree(signalTree, signalWeight);
loader->AddBackgroundTree(backgroundTree, backgroundWeight);
/// add event variables (image)
/// use new method (from ROOT 6.20 to add a variable array for all image data)
loader->AddVariablesArray("vars", imgSize);
// Set individual event weights (the variables must exist in the original TTree)
// for signal : factory->SetSignalWeightExpression ("weight1*weight2");
// for background: factory->SetBackgroundWeightExpression("weight1*weight2");
// loader->SetBackgroundWeightExpression( "weight" );
// Apply additional cuts on the signal and background samples (can be different)
TCut mycuts = ""; // for example: TCut mycuts = "abs(var1)<0.5 && abs(var2-0.5)<1";
TCut mycutb = ""; // for example: TCut mycutb = "abs(var1)<0.5";
// Tell the factory how to use the training and testing events
//
// If no numbers of events are given, half of the events in the tree are used
// for training, and the other half for testing:
// loader->PrepareTrainingAndTestTree( mycut, "SplitMode=random:!V" );
// It is possible also to specify the number of training and testing events,
// note we disable the computation of the correlation matrix of the input variables
int nTrainSig = 0.8 * nEventsSig;
int nTrainBkg = 0.8 * nEventsBkg;
// build the string options for DataLoader::PrepareTrainingAndTestTree
TString prepareOptions = TString::Format(
"nTrain_Signal=%d:nTrain_Background=%d:SplitMode=Random:SplitSeed=100:NormMode=NumEvents:!V:!CalcCorrelations",
nTrainSig, nTrainBkg);
loader->PrepareTrainingAndTestTree(mycuts, mycutb, prepareOptions);
/***
DataSetInfo : [dataset] : Added class "Signal"
: Add Tree sig_tree of type Signal with 10000 events
DataSetInfo : [dataset] : Added class "Background"
: Add Tree bkg_tree of type Background with 10000 events
**/
// signalTree->Print();
/****
# Booking Methods
Here we book the TMVA methods. We book a Boosted Decision Tree method (BDT)
**/
// Boosted Decision Trees
if (useTMVABDT) {
factory.BookMethod(loader, TMVA::Types::kBDT, "BDT",
"!V:NTrees=400:MinNodeSize=2.5%:MaxDepth=2:BoostType=AdaBoost:AdaBoostBeta=0.5:"
"UseBaggedBoost:BaggedSampleFraction=0.5:SeparationType=GiniIndex:nCuts=20");
}
/**
#### Booking Deep Neural Network
Here we book the DNN of TMVA. See the example TMVA_Higgs_Classification.C for a detailed description of the
options
**/
if (useTMVADNN) {
TString layoutString(
"Layout=DENSE|100|RELU,BNORM,DENSE|100|RELU,BNORM,DENSE|100|RELU,BNORM,DENSE|100|RELU,DENSE|1|LINEAR");
// Training strategies
// one can catenate several training strings with different parameters (e.g. learning rates or regularizations
// parameters) The training string must be concatenates with the `|` delimiter
TString trainingString1("LearningRate=1e-3,Momentum=0.9,Repetitions=1,"
"ConvergenceSteps=5,BatchSize=100,TestRepetitions=1,"
"MaxEpochs=20,WeightDecay=1e-4,Regularization=None,"
"Optimizer=ADAM,DropConfig=0.0+0.0+0.0+0.");
TString trainingStrategyString("TrainingStrategy=");
trainingStrategyString += trainingString1; // + "|" + trainingString2 + ....
// Build now the full DNN Option string
TString dnnOptions("!H:V:ErrorStrategy=CROSSENTROPY:VarTransform=None:"
"WeightInitialization=XAVIER");
dnnOptions.Append(":");
dnnOptions.Append(layoutString);
dnnOptions.Append(":");
dnnOptions.Append(trainingStrategyString);
TString dnnMethodName = "TMVA_DNN_CPU";
// use GPU if available
#ifdef R__HAS_TMVAGPU
dnnOptions += ":Architecture=GPU";
dnnMethodName = "TMVA_DNN_GPU";
#elif defined(R__HAS_TMVACPU)
dnnOptions += ":Architecture=CPU";
#endif
factory.BookMethod(loader, TMVA::Types::kDL, dnnMethodName, dnnOptions);
}
/***
### Book Convolutional Neural Network in TMVA
For building a CNN one needs to define
- Input Layout : number of channels (in this case = 1) | image height | image width
- Batch Layout : batch size | number of channels | image size = (height*width)
Then one add Convolutional layers and MaxPool layers.
- For Convolutional layer the option string has to be:
- CONV | number of units | filter height | filter width | stride height | stride width | padding height | paddig
width | activation function
- note in this case we are using a filer 3x3 and padding=1 and stride=1 so we get the output dimension of the
conv layer equal to the input
- note we use after the first convolutional layer a batch normalization layer. This seems to help significatly the
convergence
- For the MaxPool layer:
- MAXPOOL | pool height | pool width | stride height | stride width
The RESHAPE layer is needed to flatten the output before the Dense layer
Note that to run the CNN is required to have CPU or GPU support
***/
if (useTMVACNN) {
TString inputLayoutString("InputLayout=1|16|16");
// Batch Layout
TString layoutString("Layout=CONV|10|3|3|1|1|1|1|RELU,BNORM,CONV|10|3|3|1|1|1|1|RELU,MAXPOOL|2|2|1|1,"
"RESHAPE|FLAT,DENSE|100|RELU,DENSE|1|LINEAR");
// Training strategies.
TString trainingString1("LearningRate=1e-3,Momentum=0.9,Repetitions=1,"
"ConvergenceSteps=5,BatchSize=100,TestRepetitions=1,"
"MaxEpochs=20,WeightDecay=1e-4,Regularization=None,"
"Optimizer=ADAM,DropConfig=0.0+0.0+0.0+0.0");
TString trainingStrategyString("TrainingStrategy=");
trainingStrategyString +=
trainingString1; // + "|" + trainingString2 + "|" + trainingString3; for concatenating more training strings
// Build full CNN Options.
TString cnnOptions("!H:V:ErrorStrategy=CROSSENTROPY:VarTransform=None:"
"WeightInitialization=XAVIER");
cnnOptions.Append(":");
cnnOptions.Append(inputLayoutString);
cnnOptions.Append(":");
cnnOptions.Append(layoutString);
cnnOptions.Append(":");
cnnOptions.Append(trainingStrategyString);
//// New DL (CNN)
TString cnnMethodName = "TMVA_CNN_CPU";
// use GPU if available
#ifdef R__HAS_TMVAGPU
cnnOptions += ":Architecture=GPU";
cnnMethodName = "TMVA_CNN_GPU";
#else
cnnOptions += ":Architecture=CPU";
cnnMethodName = "TMVA_CNN_CPU";
#endif
factory.BookMethod(loader, TMVA::Types::kDL, cnnMethodName, cnnOptions);
}
/**
### Book Convolutional Neural Network in Keras using a generated model
**/
if (useKerasCNN) {
Info("TMVA_CNN_Classification", "Building convolutional keras model");
// create python script which can be executed
// crceate 2 conv2d layer + maxpool + dense
TMacro m;
m.AddLine("import keras");
m.AddLine("from keras.models import Sequential");
m.AddLine("from keras.optimizers import Adam");
m.AddLine(
"from keras.layers import Input, Dense, Dropout, Flatten, Conv2D, MaxPooling2D, Reshape, BatchNormalization");
m.AddLine("");
m.AddLine("model = keras.models.Sequential() ");
m.AddLine("model.add(Reshape((16, 16, 1), input_shape = (256, )))");
m.AddLine("model.add(Conv2D(10, kernel_size = (3, 3), kernel_initializer = 'glorot_normal',activation = "
"'relu', padding = 'same'))");
m.AddLine("model.add(BatchNormalization())");
m.AddLine("model.add(Conv2D(10, kernel_size = (3, 3), kernel_initializer = 'glorot_normal',activation = "
"'relu', padding = 'same'))");
// m.AddLine("model.add(BatchNormalization())");
m.AddLine("model.add(MaxPooling2D(pool_size = (2, 2), strides = (1,1))) ");
m.AddLine("model.add(Flatten())");
m.AddLine("model.add(Dense(256, activation = 'relu')) ");
m.AddLine("model.add(Dense(2, activation = 'sigmoid')) ");
m.AddLine("model.compile(loss = 'binary_crossentropy', optimizer = Adam(lr = 0.001), metrics = ['accuracy'])");
m.AddLine("model.save('model_cnn.h5')");
m.AddLine("model.summary()");
m.SaveSource("make_cnn_model.py");
// execute
gSystem->Exec("python make_cnn_model.py");
if (gSystem->AccessPathName("model_cnn.h5")) {
Warning("TMVA_CNN_Classification", "Error creating Keras model file - skip using Keras");
} else {
// book PyKeras method only if Keras model could be created
Info("TMVA_CNN_Classification", "Booking Keras CNN model");
factory.BookMethod(
loader, TMVA::Types::kPyKeras, "PyKeras",
"H:!V:VarTransform=None:FilenameModel=model_cnn.h5:"
"FilenameTrainedModel=trained_model_cnn.h5:NumEpochs=20:BatchSize=100:"
"GpuOptions=allow_growth=True"); // needed for RTX NVidia card and to avoid TF allocates all GPU memory
}
}
//// ## Train Methods
factory.TrainAllMethods();
/// ## Test and Evaluate Methods
factory.TestAllMethods();
factory.EvaluateAllMethods();
/// ## Plot ROC Curve
auto c1 = factory.GetROCCurve(loader);
c1->Draw();
// close outputfile to save output file
outputFile->Close();
}
| karies/root | tutorials/tmva/TMVA_CNN_Classification.C | C++ | lgpl-2.1 | 16,917 |
#define _GNU_SOURCE
#include <sys/socket.h>
#include <netdb.h>
#include <string.h>
#include <netinet/in.h>
struct hostent *gethostbyname2(const char *name, int af)
{
static struct hostent h;
static long buf[512/sizeof(long)];
struct hostent *res;
if (gethostbyname2_r(name, af, &h,
(void *)buf, sizeof buf, &res, &h_errno)) return 0;
return &h;
}
| davidlazar/musl | src/network/gethostbyname2.c | C | lgpl-2.1 | 356 |
/*
* Class representing FITS file.
* Copyright (C) 2008 Petr Kubanek <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "expander.h"
#include "error.h"
#include "valuearray.h"
#include "iniparser.h"
#include <fitsio.h>
#include <sstream>
#include <list>
/** Defines for FitsFile flags. */
#define IMAGE_SAVE 0x01
#define IMAGE_NOT_SAVE 0x02
#define IMAGE_KEEP_DATA 0x04
#define IMAGE_DONT_DELETE_DATA 0x08
#define IMAGE_CANNOT_LOAD 0x10
// user defined flag
#define IMAGE_FLAG_USER1 0x20
namespace rts2image
{
/**
* Class with table column informations. Used to temorary store
* table data.
*
* @author Petr Kubanek <[email protected]>
*/
class ColumnData
{
public:
ColumnData (std::string _name, std::vector <double> _data);
ColumnData (std::string _name, std::vector <int> _data, bool isBoolean);
~ColumnData () { if (data) free (data); }
std::string name;
size_t len;
const char *type;
int ftype;
void *data;
};
/**
* Hold data which should be written to the FITS file.
*
* @author Petr Kubanek <[email protected]>
*/
class TableData:public std::list <ColumnData *>
{
public:
TableData (const char *_name, double _date)
{
name = std::string (_name);
date = _date;
}
virtual ~TableData ()
{
for (std::list <ColumnData *>::iterator iter = begin (); iter != end (); iter++)
delete *iter;
}
const char *getName () { return name.c_str (); }
double getDate () { return date; }
void addColumn (ColumnData *new_data) { push_back (new_data); }
private:
std::string name;
double date;
};
/**
* Class representing FITS file. This class represents FITS file. Usually you
* will be looking for rts2image::Image class for image, or for Rts2FitsTable for
* FITS table. This class only creates FITS file and manage keywords at primary
* extension.
*
* @author Petr Kubanek <[email protected]>
*/
class FitsFile: public rts2core::Expander
{
public:
/**
* Creates file only in memory, do not write anything on disk.
*/
FitsFile ();
/**
* Copy constructor.
*
* @param in_file FitsFile to copy to this structure.
* Reference to fits file in original file will be deleted
* (NULLed).
*/
FitsFile (FitsFile * in_fitsfile);
/**
* Create FITS file from filename.
*
* @param _filename Filename of the image.
*/
FitsFile (const char *_filename, bool _overwrite);
/**
* Set only expansion date.
*
* @param _tv
*/
FitsFile (const struct timeval *_tv);
/**
* Create FITS file from expand path. Uses given date for date related file expansion.
*
*
* @param _expression Input expression.
* @param _tv Timeval used for expansio of time-related keywords in expression.
*/
FitsFile (const char *_expression, const struct timeval *_tv, bool _overwrite);
virtual ~FitsFile (void);
virtual void openFile (const char *_filename = NULL, bool readOnly = false, bool _verbose = false);
/**
* Return pointer to fitsfile structure.
*
* @return fitsfile pointer.
*/
fitsfile *getFitsFile () { return ffile; }
/**
* Overwrite expand, so if expand is forced to open the file, it will close fits file afterwards.
*/
virtual std::string expand (std::string expression, bool onlyAlphaNum = false);
/**
* Load given template file. Template file specifies values
* which should be written to the FITS headers, and general
* FITS file conventions.
*
* @param fn template file path
*/
void loadTemplate (const char *fn);
void setTemplate (rts2core::IniParser *temp) { templateFile = temp; }
/**
* Return absolute filename. As filename is created in
* setFileName() call and it is check if it's absolute,
* the returned string is always absolute (e.g. begins with /).
*
* @return Filename of this FITS file.
* @see setFileName()
*/
const char *getFileName () { return fileName; }
/**
* Return absolute filename.
*/
const char *getAbsoluteFileName () { return absoluteFileName; }
/**
* Close file.
*
* @return -1 on error, 0 on success
*/
virtual int closeFile ();
std::string replaceHeader (const char *name);
void setValue (const char *name, bool value, const char *comment);
void setValue (const char *name, int value, const char *comment);
void setValue (const char *name, long value, const char *comment);
void setValue (const char *name, float value, const char *comment);
void setValue (const char *name, double value, const char *comment);
void setValue (const char *name, char value, const char *comment);
void setValue (const char *name, const char *value, const char *comment);
void setValue (const char *name, time_t * sec, suseconds_t usec, const char *comment);
// write rectangle in IRAF notation - e.g. as [x:y,w:h]
void setValueRectange (const char *name, double x, double y, double w, double h, const char *comment);
// that method is used to update DATE - creation date entry - for other file then ffile
void setCreationDate (fitsfile * out_file = NULL);
void getValue (const char *name, bool & value, bool required = false, char *comment = NULL);
void getValue (const char *name, int &value, bool required = false, char *comment = NULL);
void getValue (const char *name, long &value, bool required = false, char *comment = NULL);
void getValue (const char *name, float &value, bool required = false, char *comment = NULL);
void getValue (const char *name, double &value, bool required = false, char *comment = NULL);
void getValue (const char *name, char &value, bool required = false, char *comment = NULL);
void getValue (const char *name, char *value, int valLen, const char* defVal = NULL, bool required = false, char *comment = NULL);
void getValue (const char *name, char **value, int valLen, bool required = false, char *comment = NULL);
void getValueRa (const char *name, double &value, bool required = false, char *comment = NULL);
void getValueDec (const char *name, double &value, bool required = false, char *comment = NULL);
/**
* Get double value from image.
*
* @param name Value name.
* @return Value
* @throw KeyNotFound
*/
double getValue (const char *name);
void getValues (const char *name, int *values, int num, bool required = false, int nstart = 1);
void getValues (const char *name, long *values, int num, bool required = false, int nstart = 1);
void getValues (const char *name, double *values, int num, bool required = false, int nstart = 1);
void getValues (const char *name, char **values, int num, bool required = false, int nstart = 1);
/**
* Write header template to FITS headers. Current frame in
* multichannel/extensions image is used.
*
* @param hc config section holding template to write
*/
void writeTemplate (rts2core::IniSection *hc);
/**
* Add template values to already existing file.
*
* @param templ template to add - PRIMARY will get to primary headers, CHANNELx will get to to extensions
*/
void addTemplate (rts2core::IniParser *templ);
/**
* Append FITS file as extension to the current file.
*
* @param afile file which extension will be appended
* @param index index of extension to append, counted from 1
*/
void appendFITS (const char *afile, int index = 1);
void appendFITS (fitsfile *affile, const char *ename = NULL, int index = 1);
/**
* Move current HDU.
*/
void moveHDU (int hdu, int *hdutype = NULL);
/**
* Return total number of HDUs.
*/
int getTotalHDUs ();
/**
* Appends history string.
*
* @param history History keyword which will be appended.
*
* @throw ErrorSettingKey
*/
void writeHistory (const char *history);
/**
* Append comment to FITS file.
*
* @param comment Comment which will be appended to FITS file comments.
*
* @throw ErrorSettingKey
*/
void writeComment (const char *comment);
/**
* Create table extension from DoubleArray
*/
int writeArray (const char *extname, TableData *values);
/**
* Return true if image shall be written to disk before it is closed.
*
* @return True if images shall be written.
*/
bool shouldSaveImage () { return (flags & IMAGE_SAVE); }
/**
* Return explanation for fits errors. This method returns only
* explanation for the latest failed call. There is not a history
* of errors messages.
*
* @return Explanation for current fits_status.
*/
std::string getFitsErrors ();
protected:
int fits_status;
int flags;
// template - header config file
rts2core::IniParser *templateFile;
void setFileName (const char *_filename);
/**
* @param _overwrite if true, existing file will be overwritten
*/
virtual int createFile (bool _overwrite = false);
int createFile (const char *_filename, bool _overwrite = false);
int createFile (std::string _filename, bool _overwrite = false);
void setFitsFile (fitsfile *_fitsfile) { ffile = _fitsfile; }
int fitsStatusValue (const char *valname, const char *operation);
void fitsStatusSetValue (const char *valname, bool required = true);
void fitsStatusGetValue (const char *valname, bool required);
bool isMemImage () { return memFile; }
private:
/**
* Pointer to fits file.
*/
fitsfile *ffile;
char *fileName;
char *absoluteFileName;
bool memFile;
bool memOverwrite;
size_t *memsize;
void **imgbuf;
};
/**
* Thrown where we cannot find header in the image.
*
* @author Petr Kubanek <[email protected]>
*/
class KeyNotFound:public rts2core::Error
{
public:
KeyNotFound (FitsFile *_image, const char *_header):rts2core::Error ()
{
std::ostringstream _os;
_os << "keyword " << _header << " missing in file " << _image->getFileName () << ":" << _image->getFitsErrors ();
setMsg (_os.str ());
}
};
/**
* Thrown when file cannot be opened.
*
* @author Petr Kubanek <[email protected]>
*/
class ErrorOpeningFitsFile: public rts2core::Error
{
public:
ErrorOpeningFitsFile (const char *filename):rts2core::Error ()
{
setMsg (std::string ("Cannot open file ") + filename);
}
};
class ErrorSettingKey: public rts2core::Error
{
public:
ErrorSettingKey (FitsFile *ff, const char *valname):rts2core::Error ()
{
setMsg (std::string ("Cannot set key ") + valname + std::string (":") + ff->getFitsErrors ());
}
};
};
| RTS2/rts2 | include/rts2fits/fitsfile.h | C | lgpl-3.0 | 11,134 |
/********************************************************************
* Copyright (C) 2015 Lou Rosas
* This file is part of many applications registered with
* the GNU General Public License as published
* by the Free Software Foundation; either version 3 of the License,
* or (at your option) any later version.
* PaceCalculator is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program.
* If not, see <http://www.gnu.org/licenses/>.
********************************************************************/
import java.lang.*;
import java.util.*;
import myclasses.*;
import rosas.lou.clock.StopWatch;
import rosas.lou.clock.Clock;
import rosas.lou.clock.StopWatchView;
//import javax.usb.*;
public class StopWatchApp{
static public void main(String [] args){
new StopWatchApp();
}
public StopWatchApp(){
new StopWatchView();
}
}
| lourosas/onewireweatherstation | bin/StopWatchApp.java | Java | lgpl-3.0 | 1,116 |
/*
* Copyright (C) EntityAPI Team
*
* This file is part of EntityAPI.
*
* EntityAPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* EntityAPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with EntityAPI. If not, see <http://www.gnu.org/licenses/>.
*/
package org.entityapi.nms.v1_7_R1.entity.mind.behaviour;
import net.minecraft.server.v1_7_R1.EntityLiving;
import org.entityapi.api.entity.ControllableEntity;
import org.entityapi.api.entity.mind.behaviour.OneTimeBehaviourGoal;
public abstract class OneTimeBehaviourGoalBase<T extends ControllableEntity, S extends EntityLiving> extends BehaviourGoalBase<T, S> implements OneTimeBehaviourGoal<T> {
protected OneTimeBehaviourGoalBase(T controllableEntity) {
super(controllableEntity);
}
@Override
public boolean isContinuous() {
return false;
}
@Override
public abstract boolean isFinished();
} | EntityAPIDev/EntityAPI | modules/v1_7_R4/src/main/java/org/entityapi/nms/v1_7_R4/entity/mind/behaviour/OneTimeBehaviourGoalBase.java | Java | lgpl-3.0 | 1,360 |
/* Mesquite (package mesquite.io). Copyright 2000 and onward, D. Maddison and W. Maddison.
Disclaimer: The Mesquite source code is lengthy and we are few. There are no doubt inefficiencies and goofs in this code.
The commenting leaves much to be desired. Please approach this source code with the spirit of helping out.
Perhaps with your help we can be more than a few, and make Mesquite better.
Mesquite is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY.
Mesquite's web site is http://mesquiteproject.org
This source code and its compiled class files are free and modifiable under the terms of
GNU Lesser General Public License. (http://www.gnu.org/copyleft/lesser.html)
*/
package mesquite.io.InterpretGenBankProt;
/*~~ */
import java.util.*;
import java.awt.*;
import mesquite.lib.*;
import mesquite.lib.characters.*;
import mesquite.lib.duties.*;
import mesquite.categ.lib.*;
import mesquite.io.lib.*;
/* ============ a file interpreter for DNA/RNA GenBank files ============*/
public class InterpretGenBankProt extends InterpretGenBank {
/*.................................................................................................................*/
public boolean canImport(Class dataClass){
return (dataClass==ProteinState.class);
}
/*.................................................................................................................*/
public CharacterData createData(CharactersManager charTask, Taxa taxa) {
return charTask.newCharacterData(taxa, 0, ProteinData.DATATYPENAME); //
}
boolean badImportWarningGiven = false;
/*.................................................................................................................*/
public void setGenBankState(CharacterData data, int ic, int it, char c) {
((ProteinData)data).setState(ic,it,c);
if (CategoricalState.isImpossible(((CategoricalData)data).getState(ic,it))){
data.badImport = true;
MesquiteTrunk.errorReportedDuringRun = true;
if (!badImportWarningGiven)
discreetAlert("THE DATA WILL BE INCORRECTLY IMPORTED. The imported sequence includes symbols not interpretable as Protein sequence data. If this is a DNA data file, please use the Genbank DNA interpreter. " +
"Also, please ensure this is not an rtf or zip file or other format that is not simple text. This warning may not be given again, but you may see subsequent warnings about impossible states.");
badImportWarningGiven = true;
}
}
/*.................................................................................................................*/
public String getName() {
return "GenBank/GenPept (Protein)";
}
/*.................................................................................................................*/
/** returns an explanation of what the module does.*/
public String getExplanation() {
return "Imports GenBank/GenPept files that consist of amino acid sequence data." ;
}
}
| MesquiteProject/MesquiteCore | Source/mesquite/io/InterpretGenBankProt/InterpretGenBankProt.java | Java | lgpl-3.0 | 3,018 |
FROM ubuntu:xenial
ENV PATH=/usr/lib/go-1.9/bin:$PATH
RUN \
apt-get update && apt-get upgrade -q -y && \
apt-get install -y --no-install-recommends golang-1.9 git make gcc libc-dev ca-certificates && \
git clone --depth 1 --branch release/1.8 https://github.com/ethereum/go-ethereum && \
(cd go-ethereum && make geth) && \
cp go-ethereum/build/bin/geth /geth && \
apt-get remove -y golang-1.9 git make gcc libc-dev && apt autoremove -y && apt-get clean && \
rm -rf /go-ethereum
EXPOSE 8545
EXPOSE 30303
ENTRYPOINT ["/geth"]
| wuestholz/go-ethereum | containers/docker/master-ubuntu/Dockerfile | Dockerfile | lgpl-3.0 | 542 |
package com.jediterm.terminal.ui.settings;
import com.jediterm.terminal.TtyConnector;
import javax.swing.*;
/**
* @author traff
*/
public interface TabbedSettingsProvider extends SettingsProvider {
boolean shouldCloseTabOnLogout(TtyConnector ttyConnector);
String tabName(TtyConnector ttyConnector, String sessionName);
KeyStroke[] getNextTabKeyStrokes();
KeyStroke[] getPreviousTabKeyStrokes();
}
| patsimm/jediterm | src-terminal/com/jediterm/terminal/ui/settings/TabbedSettingsProvider.java | Java | lgpl-3.0 | 414 |
/*
* #%L
* Alfresco Data model classes
* %%
* Copyright (C) 2005 - 2016 Alfresco Software Limited
* %%
* This file is part of the Alfresco software.
* If the software was purchased under a paid Alfresco license, the terms of
* the paid license agreement will prevail. Otherwise, the software is
* provided under the following open source license terms:
*
* Alfresco is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Alfresco is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with Alfresco. If not, see <http://www.gnu.org/licenses/>.
* #L%
*/
package org.alfresco.opencmis.dictionary;
import java.util.Collection;
import org.alfresco.service.namespace.QName;
/**
* Filters QNames and excludes any
* that are in a predefined list.
*
* @author steveglover
* @author Gethin James
*/
public interface QNameFilter
{
public static final String WILDCARD = "*";
/**
* Filters out any QName defined in the "excludedTypes" property
*
* @param typesToFilter - original list
* @return the filtered list
*/
Collection<QName> filterQName(Collection<QName> typesToFilter);
/**
* Indicates that this QName should be excluded.
* @param typeQName QName
* @return boolean true if it is excluded
*/
boolean isExcluded(QName typeQName);
/**
* Exclude the type
*
* @param typeQName the type to exclude
*
*/
void setExcluded(QName typeQName, boolean excluded);
void initFilter();
}
| Alfresco/community-edition | projects/data-model/source/java/org/alfresco/opencmis/dictionary/QNameFilter.java | Java | lgpl-3.0 | 2,029 |
//
// System.Runtime.InteropServices/RuntimeEnvironment.cs
//
// Authors:
// Dominik Fretz ([email protected])
// Sebastien Pouliot ([email protected])
//
// (C) 2003 Dominik Fretz
// Copyright (C) 2004-2005 Novell, Inc (http://www.novell.com)
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
using System.IO;
using System.Reflection;
using System.Runtime.InteropServices;
using System.Security;
using System.Security.Permissions;
namespace System.Runtime.InteropServices
{
[ComVisible (true)]
public class RuntimeEnvironment
{
public RuntimeEnvironment ()
{
}
public static string SystemConfigurationFile {
get {
// GetMachineConfigPath is internal and not protected by CAS
string path = Environment.GetMachineConfigPath ();
if (SecurityManager.SecurityEnabled) {
new FileIOPermission (FileIOPermissionAccess.PathDiscovery, path).Demand ();
}
return path;
}
}
public static bool FromGlobalAccessCache (Assembly a)
{
// yes, this will throw a NullReferenceException (just like MS, reported as ...)
return a.GlobalAssemblyCache;
}
public static string GetRuntimeDirectory ()
{
return Path.GetDirectoryName (typeof (int).Assembly.Location);
}
#if NET_4_0
[SecuritySafeCritical]
#else
[SecurityPermission (SecurityAction.Demand, UnmanagedCode = true)]
#endif
public static string GetSystemVersion ()
{
return "v" + Environment.Version.Major + "." + Environment.Version.Minor + "." + Environment.Version.Build;
}
}
}
| edwinspire/VSharp | v#/corlib/System.Runtime.InteropServices/RuntimeEnvironment.cs | C# | lgpl-3.0 | 2,535 |
<?php
/**
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @category tests
* @package log4php
* @license http://www.apache.org/licenses/LICENSE-2.0 Apache License, Version 2.0
* @version $Revision: 1374580 $
* @link http://logging.apache.org/log4php
*/
error_reporting(E_ALL | E_STRICT);
// Required for testing logging of sessionID in pattern layout
session_start();
date_default_timezone_set('Europe/London');
// Define a temp dir where tests may write to
$tmpDir = dirname(__FILE__) . '/../../../target/temp/phpunit';
if (!is_dir($tmpDir)) {
mkdir($tmpDir, 0777, true);
}
define('PHPUNIT_TEMP_DIR', realpath($tmpDir));
// Make the path to the configurations dir for easier access
$confDir = dirname(__FILE__) . '/../resources/configs';
define('PHPUNIT_CONFIG_DIR', realpath($confDir));
require dirname(__FILE__) . '/../../main/php/Logger.php';
require dirname(__FILE__) . DIRECTORY_SEPARATOR . 'LoggerTestHelper.php';
| MobiusMedical/sg-oc | lib/apache-log4php-2.3.0/src/test/php/bootstrap.php | PHP | lgpl-3.0 | 1,711 |
var gulp = require('gulp');
var $ = require('gulp-load-plugins')();
var path = require('path');
var exec = require('child_process').exec;
var fs = require('fs');
var runSequence = require('run-sequence');
var del = require('del');
var vinylPaths = require('vinyl-paths');
var clean = function(){ return vinylPaths(del) };
var vfs = require('vinyl-fs');
var transform = require('vinyl-transform');
var buffer = require('vinyl-buffer');
var browserifyHeader = require('browserify-header');
var notifier = require('node-notifier');
var watchify = require('watchify');
var browserify = require('browserify');
var source = require('vinyl-source-stream'); // converts node streams into vinyl streams
var benchmarkVersion = '2.3.15'; // old version to test against for benchmarks
var benchmarkVersionUrl = 'https://raw.githubusercontent.com/cytoscape/cytoscape.js/v' + benchmarkVersion + '/dist/cytoscape.js';
var weaverVersion = 'master';
var weaverUrlBase = 'https://raw.githubusercontent.com/maxkfranz/weaver/' + weaverVersion + '/';
var addWeaverUrlBase = function( path ){
return weaverUrlBase + path;
};
var weaverSrc = [
'src/thread.js',
'src/fabric.js',
'src/thread-node-fork.js'
].map( addWeaverUrlBase );
var weaverTest = [
'test/thread.js',
'test/fabric.js',
'test/requires/foo.js'
].map( addWeaverUrlBase );
var weaverTestReqs = [
'test/requires/foo.js'
].map( addWeaverUrlBase );
var version; // used for marking builds w/ version etc
var paths = {
sourceEntry: 'src/index.js',
preamble: 'src/preamble.js',
nodethreadName: 'thread-node-fork.js',
nodethreadSrc: [
'src/preamble.js',
'src/thread-node-fork.js'
],
debugFiles: [
'build/cytoscape.js'
],
testFiles: [
'build/cytoscape.js'
],
docs: {
js: [
'documentation/js/fastclick.js',
'documentation/js/jquery.js',
'documentation/js/cytoscape.js',
'documentation/js/load.js',
'documentation/js/script.js'
],
css: [
'documentation/css/reset.css',
'documentation/css/font-awesome.css',
'documentation/css/highlight/github.css',
'documentation/css/style.css'
]
}
};
var browserifyOpts = {
entries: paths.sourceEntry,
debug: true,
builtins: [],
bundleExternal: false,
detectGlobals: false,
standalone: 'cytoscape',
cache: {}, // for watchify
packageCache: {} // for watchify
};
var logError = function( err ){
notifier.notify({ title: 'Cytoscape.js', message: 'Error: ' + err.message });
$.util.log( $.util.colors.red('Error in watch:'), $.util.colors.red(err) );
};
// update these if you don't have a unix like env or these programmes aren't in your $PATH
var $GIT = 'git';
var $RM = 'rm -rf';
var $CP = 'cp -R';
var $TEMP_DIR = '/tmp';
var $DOC_DIR = 'documentation';
var $DL_DIR = 'download';
var $NPM = 'npm';
var $METEOR = 'meteor';
var $SPM = 'spm';
var replaceShellVars = function( cmds ){
return cmds.map(function( cmd ){
return cmd
//.replace(/\$VERSION/g, version)
.replace(/\$GIT/g, 'git')
.replace(/\$RM/g, 'rm -rf')
.replace(/\$CP/g, 'cp -R')
.replace(/\$TEMP_DIR/g, '/tmp')
.replace(/\$DOC_DIR/g, 'documentation')
.replace(/\$DL_DIR/g, 'download')
.replace(/\$NPM/g, 'npm')
.replace(/\$METEOR/g, 'meteor')
.replace(/\$SPM/g, 'spm')
;
});
};
gulp.task('default', ['build'], function( next ){
next();
});
gulp.task('version', function( next ){
var now = new Date();
version = process.env['VERSION'];
if( version ){
done();
} else {
exec('git rev-parse HEAD', function( error, stdout, stderr ){
var sha = stdout.substring(0, 10); // shorten so not huge filename
version = [ 'snapshot', sha, +now ].join('-');
done();
});
}
function done(){
console.log('Using version number `%s` for building', version);
next();
}
});
gulp.task('confver', ['version'], function(){
return gulp.src('.')
.pipe( $.prompt.confirm({ message: 'Are you sure version `' + version + '` is OK to publish?' }) )
;
});
gulp.task('clean', function(){
return gulp.src(['build'])
.pipe( clean({ read: false }) )
;
});
// gulp.task('format', function(){
// return gulp.src('src/**/*.js')
// .pipe( jscs({
// fix: true,
// configPath: '.jscsrc'
// }) )
// .pipe( gulp.dest('formatted') ) // TODO move to src after confirming .jscsrc
// ;
// });
gulp.task('format', $.shell.task([
'./node_modules/jscs/bin/jscs src/** --fix'
]));
gulp.task('concat', ['version', 'nodeworker'], function(){
return browserify( browserifyOpts )
.plugin( browserifyHeader, { file: paths.preamble } )
.bundle()
.on( 'error', logError )
.pipe( source('cytoscape.js') )
.pipe( buffer() )
.pipe( $.derequire() )
.pipe( $.replace('{{VERSION}}', version) )
.pipe( gulp.dest('build') )
;
});
gulp.task('build-unmin', ['version', 'nodeworker'], function(){
return browserify( browserifyOpts )
.plugin( browserifyHeader, { file: paths.preamble } )
.bundle()
.on( 'error', logError )
.pipe( source('cytoscape.js') )
.pipe( buffer() )
.pipe( $.sourcemaps.init({ loadMaps: true }) )
.pipe( $.derequire() )
.pipe( $.replace('{{VERSION}}', version) )
.pipe( $.sourcemaps.write('.') )
.pipe( gulp.dest('build') )
;
});
gulp.task('build-min', ['version', 'nodeworker'], function(){
return browserify( browserifyOpts )
.plugin( browserifyHeader, { file: paths.preamble } )
.bundle()
.on( 'error', logError )
.pipe( source('cytoscape.min.js') )
.pipe( buffer() )
.pipe( $.sourcemaps.init({ loadMaps: true }) )
.pipe( $.derequire() )
.pipe( $.replace('{{VERSION}}', version) )
.pipe( $.uglify({ mangle: true, preserveComments: 'some' }) )
.pipe( $.sourcemaps.write('.') )
.pipe( gulp.dest('build') )
;
});
gulp.task('build', ['build-unmin', 'build-min'], function( next ){
next();
});
gulp.task('nodeworker', ['version'], function(){
return gulp.src( paths.nodethreadSrc )
.pipe( $.replace('{{VERSION}}', version) )
.pipe( $.concat(paths.nodethreadName) )
.pipe( gulp.dest('build') )
;
});
gulp.task('debugrefs', function(){
return gulp.src('debug/index.html')
.pipe( $.inject( gulp.src(paths.debugFiles, { read: false }), {
addPrefix: '..',
addRootSlash: false
} ) )
.pipe( gulp.dest('debug') )
;
});
gulp.task('testrefs', function(){
return gulp.src('test/index.html')
.pipe( $.inject( gulp.src(paths.testFiles, { read: false }), {
addPrefix: '..',
addRootSlash: false
} ) )
.pipe( gulp.dest('test') )
;
});
gulp.task('testlist', function(){
return gulp.src('test/index.html')
.pipe( $.inject( gulp.src('test/*.js', { read: false }), {
addPrefix: '',
ignorePath: 'test',
addRootSlash: false,
starttag: '<!-- inject:test:{{ext}} -->'
} ) )
.pipe( gulp.dest('test') )
;
});
gulp.task('refs', function(next){
runSequence( 'debugrefs', 'testrefs', 'testlist', next );
});
gulp.task('zip', ['version', 'build'], function(){
return gulp.src([
'build/cytoscape.js',
'build/cytoscape.js.map',
'build/cytoscape.min.js',
'build/cytoscape.min.js.map',
'LGPL-LICENSE.txt',
'lib/*.js'
])
.pipe( $.zip('cytoscape.js-' + version + '.zip') )
.pipe( gulp.dest('build') )
;
});
gulp.task('test', ['concat'], function(next){
return gulp.src('test/*.js')
.pipe( $.mocha({
reporter: 'spec'
}) )
;
});
gulp.task('weaver-src', function(){
return $.download( weaverSrc )
.pipe( $.replace('weaver', 'cytoscape') )
.pipe( gulp.dest('src') )
;
});
gulp.task('weaver-test', function(){
return $.download( weaverTest )
.pipe( $.replace('weaver', 'cytoscape') )
.pipe( gulp.dest('test') )
;
});
gulp.task('weaver-test-reqs', function(){
return $.download( weaverTestReqs )
.pipe( gulp.dest('test/requires') )
;
});
gulp.task('weaver', function(next){
return runSequence(['weaver-src', 'weaver-test', 'weaver-test-reqs'], next);
});
gulp.task('benchmark-old-ver', function(){
return $.download( benchmarkVersionUrl )
.pipe(gulp.dest("benchmark/CySuite"));
});
gulp.task('benchmark', ['concat', 'benchmark-old-ver'], function(next){
gulp.src('benchmark/*.js')
.pipe( $.benchmark() )
;
});
gulp.task('benchmark-single', ['concat', 'benchmark-old-ver'], function(next){
gulp.src('benchmark/single/index.js')
.pipe( $.benchmark() )
;
});
gulp.task('docsver', ['version'], function(){
return gulp.src('documentation/docmaker.json')
.pipe( $.replace(/\"version\"\:\s*\".*?\"/, '"version": "' + version + '"') )
.pipe( gulp.dest('documentation') )
;
});
gulp.task('docsjs', ['version', 'build'], function(){
return gulp.src([
'build/cytoscape.js',
'build/cytoscape.min.js',
'lib/*.js'
])
.pipe( gulp.dest('documentation/js') )
.pipe( gulp.dest('documentation/api/cytoscape.js-' + version) )
.pipe( gulp.dest('documentation/api/cytoscape.js-latest') )
;
});
gulp.task('docsdl', ['version', 'zip'], function(){
return gulp.src('build/cytoscape.js-' + version + '.zip')
.pipe( gulp.dest('documentation/download') )
;
});
gulp.task('docsbuildlist', ['docsdl'], function(next){
var cwd = process.cwd();
process.chdir('./documentation/download');
require('./documentation/download/dlmaker')(function(){
process.chdir( cwd );
next();
});
});
gulp.task('snapshotpush', ['docsdl'], function(){
return gulp.src('')
.pipe( $.shell( replaceShellVars([
'$RM $TEMP_DIR/cytoscape.js',
'$GIT clone -b gh-pages https://github.com/cytoscape/cytoscape.js.git $TEMP_DIR/cytoscape.js',
'$CP $DOC_DIR/$DL_DIR/* $TEMP_DIR/cytoscape.js/$DL_DIR',
]) ) )
.pipe( $.shell( replaceShellVars([
'$GIT add -A',
'$GIT commit -a -m "updating list of builds"',
'$GIT push origin'
]), { cwd: $TEMP_DIR + '/cytoscape.js' } ) )
;
});
gulp.task('docs', function(next){
var cwd = process.cwd();
process.chdir('./documentation');
require('./documentation/docmaker')( function(){
process.chdir( cwd );
next();
} );
});
gulp.task('docsmin', function(next){
runSequence( 'docs', 'docsminrefs', 'docshtmlmin', next );
});
gulp.task('docsclean', function(next){
return gulp.src(['documentation/js/all.min.js', 'documentation/css/all.min.css', 'documentation/index.html'])
.pipe( clean({ read: false }) )
;
});
gulp.task('docshtmlmin', function(){
return gulp.src('documentation/index.html')
.pipe( $.htmlmin({
collapseWhitespace: true,
keepClosingSlash: true
}) )
.pipe( gulp.dest('documentation') )
;
});
gulp.task('docsjsmin', function(){
return gulp.src( paths.docs.js )
.pipe( $.concat('all.min.js') )
.pipe( $.uglify({
mangle: true
}) )
.pipe( gulp.dest('documentation/js') )
;
});
gulp.task('docscssmin', function(){
return gulp.src( paths.docs.css )
.pipe( $.concat('all.min.css') )
.pipe( $.cssmin() )
.pipe( gulp.dest('documentation/css') )
;
});
gulp.task('docsminrefs', ['docscssmin', 'docsjsmin'], function(){
return gulp.src('documentation/index.html')
.pipe( $.inject( gulp.src([ 'documentation/js/all.min.js', 'documentation/css/all.min.css' ] ), {
addRootSlash: false,
ignorePath: 'documentation'
} ) )
.pipe( gulp.dest('documentation') )
;
});
gulp.task('docsrefs', function(){
return gulp.src([ 'documentation/index.html', 'documentation/template.html' ])
.pipe( $.inject( gulp.src(paths.docs.js.$.concat( paths.docs.css ), { read: false }), {
addRootSlash: false,
ignorePath: 'documentation'
} ) )
.pipe( gulp.dest('documentation') )
;
});
gulp.task('docsdemoshots', function(next){ return next(); // disable for now since phantomjs doesn't work for this usecase
var cwd = process.cwd();
process.chdir('./documentation');
require('./documentation/demoshots')( function(){
process.chdir( cwd );
next();
} );
});
gulp.task('docsdemodl', function(){
var docmaker = require('./documentation/docmaker.json');
var demos = docmaker.sections.filter(function(s){
return s.demos != null || s.demo != null;
}).map(function( s ){
return s.demos || [ s.demo ];
}).map(function( ds ){
return ds.map(function(d){
return 'https://gist.github.com/' + d.id + '/download';
});
}).reduce(function(prevDs, currDs){
return prevDs.concat( currDs );
}, []);
return $.download( demos )
.pipe( $.unzip() )
.pipe( $.rename(function( path ){
// console.log(path)
var match = path.dirname.match(/^(.+)\-master$/);
if( match ){
path.dirname = match[1];
}
}) )
.pipe( $.replace(/".*cytoscape(\.min){0,1}\.js"/, '"../../js/cytoscape.min.js"') )
.pipe( gulp.dest('documentation/demos') )
;
});
gulp.task('docspub', function(next){
runSequence( 'version', 'docsver', 'docsjs', 'docsbuildlist', 'docsdemoshots', 'docsdemodl', 'docsmin', next );
});
gulp.task('docsrebuild', function(next){
runSequence( 'docsmin', next );
});
gulp.task('pkgver', ['version'], function(){
return gulp.src([
'package.json',
'bower.json'
])
.pipe( $.replace(/\"version\"\:\s*\".*?\"/, '"version": "' + version + '"') )
.pipe( gulp.dest('./') )
;
});
gulp.task('dist', ['build'], function(){
return gulp.src([
'build/cytoscape.js',
'build/cytoscape.js.map',
'build/cytoscape.min.js',
'build/cytoscape.min.js.map',
'build/' + paths.nodethreadName
])
.pipe( gulp.dest('dist') )
;
});
gulp.task('pubprep', function(next){
runSequence('pkgver', 'dist', 'docspub', 'pubpush', next);
});
gulp.task('pubpush', $.shell.task( replaceShellVars([
'$GIT add -A',
'$GIT commit -m "preparing to publish $VERSION"',
'$GIT push'
]) ));
gulp.task('publish', ['pubprep'], function(next){
runSequence('confver', 'tag', 'docspush', 'npm', 'spm', 'meteor', next);
});
gulp.task('tag', $.shell.task( replaceShellVars([
'$GIT tag -a v$VERSION -m "v$VERSION"',
'$GIT push origin v$VERSION'
]) ));
gulp.task('docspush', function(){
return gulp.src('')
.pipe( $.shell( replaceShellVars([
'$RM $TEMP_DIR/cytoscape.js',
'$GIT clone -b gh-pages https://github.com/cytoscape/cytoscape.js.git $TEMP_DIR/cytoscape.js',
'$CP $DOC_DIR/* $TEMP_DIR/cytoscape.js',
]) ) )
.pipe( $.shell( replaceShellVars([
'$GIT add -A',
'$GIT commit -a -m "updating docs to $VERSION"',
'$GIT push origin'
]), { cwd: $TEMP_DIR + '/cytoscape.js' } ) )
;
});
gulp.task('unstabledocspush', function(){
return gulp.src('')
.pipe( $.shell( replaceShellVars([
'$RM $TEMP_DIR/cytoscape.js',
'$GIT clone -b gh-pages https://github.com/cytoscape/cytoscape.js.git $TEMP_DIR/cytoscape.js',
'$CP $DOC_DIR/* $TEMP_DIR/cytoscape.js/unstable',
]) ) )
.pipe( $.shell( replaceShellVars([
'$GIT add -A',
'$GIT commit -a -m "updating unstable docs to $VERSION"',
'$GIT push origin'
]), { cwd: $TEMP_DIR + '/cytoscape.js' } ) )
;
});
// browserify debug build
gulp.task('browserify', function(){
var b = browserify( browserifyOpts );
return b.bundle()
.pipe( source('cytoscape.browserify.js') )
.pipe( buffer() )
.pipe( $.derequire() )
.pipe( gulp.dest('build') )
;
});
gulp.task('sniper', ['browserify'], $.shell.task( replaceShellVars([
'$NPM run sniper'
]) ));
gulp.task('npm', $.shell.task( replaceShellVars([
'$NPM publish .'
]) ));
gulp.task('meteor', $.shell.task( replaceShellVars([
'$METEOR publish'
]) ));
gulp.task('spm', $.shell.task( replaceShellVars([
'$SPM publish'
]) ));
gulp.task('watch', function(next){
$.livereload.listen();
gulp.watch('test/*.js', ['testlist'])
.on('added deleted', function( event ){
console.log('File ' + event.path + ' was ' + event.type + ', updating test refs in pages...');
})
;
var b = watchify( browserify( browserifyOpts ), { poll: true } );
var rebuild = function(){
return b.bundle()
.on( 'error', logError )
.pipe( source('cytoscape.js') )
.pipe( buffer() )
.pipe( $.derequire() )
.pipe( gulp.dest('build') )
.pipe( $.livereload() )
;
};
rebuild();
b.on('update', rebuild);
next();
});
// http://www.jshint.com/docs/options/
gulp.task('lint', function(){
return gulp.src( 'src/**' )
.pipe( $.jshint({
newcap: false,
funcscope: true,
laxbreak: true,
loopfunc: true,
strict: true,
globalstrict: true,
unused: 'vars',
eqnull: true,
sub: true,
shadow: true,
laxcomma: true,
globals: {
'Path2D': true,
'require': true,
'module': true,
'document': true,
'window': true,
'setTimeout': true,
'clearTimeout': true,
'MutationObserver': true,
'__dirname': true,
'Image': true,
'Blob': true,
'Worker': true,
'DocumentTouch': true,
'HTMLElement': true,
'navigator': true
}
}) )
.pipe( $.jshint.reporter( require('jshint-stylish') ) )
;
});
| avikpal/cytoscape.js | gulpfile.js | JavaScript | lgpl-3.0 | 17,266 |
/*
* @BEGIN LICENSE
*
* Psi4: an open-source quantum chemistry software package
*
* Copyright (c) 2007-2019 The Psi4 Developers.
*
* The copyrights for code used from other parties are included in
* the corresponding files.
*
* This file is part of Psi4.
*
* Psi4 is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, version 3.
*
* Psi4 is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License along
* with Psi4; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* @END LICENSE
*/
#include "psi4/libqt/qt.h"
#include "defines.h"
#include "dfocc.h"
using namespace psi;
namespace psi {
namespace dfoccwave {
void DFOCC::mp3_WmnijT2() {
// defs
SharedTensor2d K, T, Tnew, U, Tau, W, X;
SharedTensor2d M, L, I, Y, S, A;
SharedTensor2d V, Vs, Va, Ts, Ta;
timer_on("WmnijT2");
// W_mnij = <mn|ij>
W = SharedTensor2d(new Tensor2d("W <MN|IJ>", naoccA, naoccA, naoccA, naoccA));
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (IJ|KL)", naoccA, naoccA, naoccA, naoccA));
K->gemm(true, false, bQijA, bQijA, 1.0, 0.0);
W->sort(1324, K, 1.0, 0.0);
K.reset();
// t_ij^ab <= \sum_{m,n} T_mn^ab Wmnij
// (+)T(ij, ab) = 1/2 (T_ij^ab + T_ji^ab) * (2 - \delta_{ij})
// (-)T(ij, ab) = 1/2 (T_ij^ab - T_ji^ab) * (2 - \delta_{ij})
U = SharedTensor2d(new Tensor2d("T2 <IJ|AB>", naoccA, naoccA, navirA, navirA));
U->sort(1324, t2, 1.0, 0.0);
Ts = SharedTensor2d(new Tensor2d("(+)tT [I>=J|A>=B]", ntri_ijAA, ntri_abAA));
Ta = SharedTensor2d(new Tensor2d("(-)tT [I>=J|A>=B]", ntri_ijAA, ntri_abAA));
Ts->symm_row_packed4(U);
Ta->antisymm_row_packed4(U);
U.reset();
// Form (+/-)W(m>=n, i>=j)
Vs = SharedTensor2d(new Tensor2d("(+)W [M>=N|I>=J]", ntri_ijAA, ntri_ijAA));
Va = SharedTensor2d(new Tensor2d("(-)W [M>=N|I>=J]", ntri_ijAA, ntri_ijAA));
Vs->symm4(W);
Va->antisymm4(W);
W.reset();
// Symmetric & Anti-symmetric contributions
S = SharedTensor2d(new Tensor2d("S (I>=J, A>=B)", ntri_ijAA, ntri_abAA));
A = SharedTensor2d(new Tensor2d("A (I>=J, A>=B)", ntri_ijAA, ntri_abAA));
S->gemm(true, false, Vs, Ts, 1.0, 0.0);
A->gemm(true, false, Va, Ta, 1.0, 0.0);
Ts.reset();
Ta.reset();
Vs.reset();
Va.reset();
// T(ia,jb) <-- S(a>=b,i>=j) + A(a>=b,i>=j)
Tnew = SharedTensor2d(new Tensor2d("New T2_2 (IA|JB)", naoccA, navirA, naoccA, navirA));
// Tnew->read_symm(psio_, PSIF_DFOCC_AMPS);
#pragma omp parallel for
for (int a = 0; a < navirA; ++a) {
for (int b = 0; b < navirA; ++b) {
int ab = index2(a, b);
for (int i = 0; i < naoccA; ++i) {
int ia = ia_idxAA->get(i, a);
for (int j = 0; j < naoccA; ++j) {
int jb = ia_idxAA->get(j, b);
int ij = index2(i, j);
int perm1 = (i > j) ? 1 : -1;
int perm2 = (a > b) ? 1 : -1;
double value = S->get(ij, ab) + (perm1 * perm2 * A->get(ij, ab));
Tnew->add(ia, jb, value);
}
}
}
}
S.reset();
A.reset();
Tnew->write_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmnijT2");
} // end mp3_WmnijT2
//======================================================================
// WmnijT2AA
//======================================================================
void DFOCC::mp3_WmnijT2AA() {
// defs
SharedTensor2d K, T, Tnew, U, Tau, W, X;
SharedTensor2d M, L, I, Y, S, A;
SharedTensor2d V, Vs, Va, Ts, Ta;
timer_on("WmnijT2");
// W_mnij = <mn||ij>
W = SharedTensor2d(new Tensor2d("W <MN|IJ>", naoccA, naoccA, naoccA, naoccA));
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (IJ|KL)", naoccA, naoccA, naoccA, naoccA));
K->gemm(true, false, bQijA, bQijA, 1.0, 0.0);
W->sort(1324, K, 1.0, 0.0);
W->sort(1342, K, -1.0, 1.0);
K.reset();
// t_ij^ab <= 1/2 \sum_{m,n} T_mn^ab Wmnij
// (-)T(ij, ab) = 1/2 (T_ij^ab - T_ji^ab) * (2 - \delta_{ij})
U = SharedTensor2d(new Tensor2d("T2_1 <IJ|AB>", naoccA, naoccA, navirA, navirA));
U->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
Ta = SharedTensor2d(new Tensor2d("(-)tT [I>=J|A>=B]", ntri_ijAA, ntri_abAA));
Ta->antisymm_row_packed4(U);
U.reset();
// Form (-)W(m>=n, i>=j)
Va = SharedTensor2d(new Tensor2d("(-)W [M>=N|I>=J]", ntri_ijAA, ntri_ijAA));
Va->antisymm4(W);
W.reset();
// Anti-symmetric contributions
A = SharedTensor2d(new Tensor2d("A (I>=J, A>=B)", ntri_ijAA, ntri_abAA));
A->gemm(true, false, Va, Ta, 0.5, 0.0);
Ta.reset();
Va.reset();
// T(ia,jb) <-- A(a>=b,i>=j)
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <IJ|AB>", naoccA, naoccA, navirA, navirA));
// Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
#pragma omp parallel for
for (int a = 0; a < navirA; ++a) {
for (int b = 0; b < navirA; ++b) {
int ab = index2(a, b);
int ab2 = ab_idxAA->get(a, b);
for (int i = 0; i < naoccA; ++i) {
for (int j = 0; j < naoccA; ++j) {
int ij2 = ij_idxAA->get(i, j);
int ij = index2(i, j);
int perm1 = (i > j) ? 1 : -1;
int perm2 = (a > b) ? 1 : -1;
double value = perm1 * perm2 * A->get(ij, ab);
Tnew->add(ij2, ab2, value);
}
}
}
}
A.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
/*
// t_ij^ab <= 1/2 \sum_{m,n} T_mn^ab Wmnij
T = SharedTensor2d(new Tensor2d("T2_1 <IJ|AB>", naoccA, naoccA, navirA, navirA));
T->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
T->print();
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <IJ|AB>", naoccA, naoccA, navirA, navirA));
Tnew->gemm(true, false, W, T, 0.5, 0.0);
W.reset();
T.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew->print();
Tnew.reset();
*/
timer_off("WmnijT2");
} // end mp3_WmnijT2AA
//======================================================================
// WmnijT2BB
//======================================================================
void DFOCC::mp3_WmnijT2BB() {
// defs
SharedTensor2d K, T, Tnew, U, Tau, W, X;
SharedTensor2d M, L, I, Y, S, A;
SharedTensor2d V, Vs, Va, Ts, Ta;
timer_on("WmnijT2");
// W_mnij = <mn||ij>
W = SharedTensor2d(new Tensor2d("W <mn|ij>", naoccB, naoccB, naoccB, naoccB));
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (ij|kl)", naoccB, naoccB, naoccB, naoccB));
K->gemm(true, false, bQijB, bQijB, 1.0, 0.0);
W->sort(1324, K, 1.0, 0.0);
W->sort(1342, K, -1.0, 1.0);
K.reset();
// t_ij^ab <= 1/2 \sum_{m,n} T_mn^ab Wmnij
// (-)T(ij, ab) = 1/2 (T_ij^ab - T_ji^ab) * (2 - \delta_{ij})
U = SharedTensor2d(new Tensor2d("T2_1 <ij|ab>", naoccB, naoccB, navirB, navirB));
U->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
Ta = SharedTensor2d(new Tensor2d("(-)tT [I>=J|A>=B]", ntri_ijBB, ntri_abBB));
Ta->antisymm_row_packed4(U);
U.reset();
// Form (-)W(m>=n, i>=j)
Va = SharedTensor2d(new Tensor2d("(-)W [M>=N|I>=J]", ntri_ijBB, ntri_ijBB));
Va->antisymm4(W);
W.reset();
// Anti-symmetric contributions
A = SharedTensor2d(new Tensor2d("A (I>=J, A>=B)", ntri_ijBB, ntri_abBB));
A->gemm(true, false, Va, Ta, 1.0, 0.0);
Ta.reset();
Va.reset();
// T(ia,jb) <-- A(a>=b,i>=j)
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <ij|ab>", naoccB, naoccB, navirB, navirB));
// Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
#pragma omp parallel for
for (int a = 0; a < navirB; ++a) {
for (int b = 0; b < navirB; ++b) {
int ab = index2(a, b);
int ab2 = ab_idxBB->get(a, b);
for (int i = 0; i < naoccB; ++i) {
for (int j = 0; j < naoccB; ++j) {
int ij2 = ij_idxBB->get(i, j);
int ij = index2(i, j);
int perm1 = (i > j) ? 1 : -1;
int perm2 = (a > b) ? 1 : -1;
double value = perm1 * perm2 * A->get(ij, ab);
Tnew->add(ij2, ab2, 0.5 * value);
}
}
}
}
A.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmnijT2");
} // end mp3_WmnijT2BB
//======================================================================
// WmnijT2AB
//======================================================================
void DFOCC::mp3_WmnijT2AB() {
// defs
SharedTensor2d K, T, Tnew, U, Tau, W, X;
timer_on("WmnijT2");
// W_mnij = <mn|ij>
W = SharedTensor2d(new Tensor2d("W <Mn|Ij>", naoccA, naoccB, naoccA, naoccB));
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (IJ|kl)", naoccA, naoccA, naoccB, naoccB));
K->gemm(true, false, bQijA, bQijB, 1.0, 0.0);
W->sort(1324, K, 1.0, 0.0);
K.reset();
// t_Ij^Ab <= \sum_{M,n} T_Mn^Ab W_MnIj
T = SharedTensor2d(new Tensor2d("T2_1 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
T->read(psio_, PSIF_DFOCC_AMPS);
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
Tnew->gemm(true, false, W, T, 1.0, 0.0);
T.reset();
W.reset();
// Tnew->cont444(false, 1, 2, 3, 4, W, false, 1, 2, 3, 4, T, 1.0, 0.0); // it works
// Tnew->cont444(true, 1, 2, 3, 4, W, true, 1, 2, 3, 4, T, 1.0, 0.0); // it works, W and T are deleted
// Tnew->cont444("IjAb", "MnIj", "MnAb", true, true, W, T, 1.0, 0.0); // it works, W and T are deleted
Tnew->write(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmnijT2");
} // end mp3_WmnijT2AB
//======================================================================
// WmbejT2
//======================================================================
void DFOCC::mp3_WmbejT2() {
// defs
SharedTensor2d K, L, T, T1, Tnew, U, Tau, W, W2, X, Y;
timer_on("WmbejT2");
// W_mbej = W(me,jb)
// W(me,jb) <= (me|jb)
W = SharedTensor2d(new Tensor2d("W (ME|JB)", naoccA, navirA, naoccA, navirA));
W->gemm(true, false, bQiaA, bQiaA, 1.0, 0.0);
W->write(psio_, PSIF_DFOCC_AMPS);
W.reset();
// W_mbje = W'(me,jb)
// W'(me,jb) <= <me|jb>
W = SharedTensor2d(new Tensor2d("Wp (ME|JB)", naoccA, navirA, naoccA, navirA));
L = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (IJ|AB)", naoccA, naoccA, navirA, navirA));
L->gemm(true, false, bQijA, bQabA, 1.0, 0.0);
W->sort(1324, L, 1.0, 0.0);
L.reset();
// t_ij^ab <= 1/2*C(ia,jb) + 1/2*C(jb,ia) + C(ja,ib) + C(ib,ja)
// t_ij^ab <= Ct(ia,jb) + 2*Ct(ib,ja)
// C(ia,jb) = -\sum_{me} t_mi^ae W'(me,jb) = -\sum_{me} T'(ia,me) W'(me,jb)
U = SharedTensor2d(new Tensor2d("T2p (IA|JB)", naoccA, navirA, naoccA, navirA));
ccsd_t2_prime_amps(U, t2);
Y = SharedTensor2d(new Tensor2d("C2 (IA|JB)", naoccA, navirA, naoccA, navirA));
Y->gemm(false, false, U, W, -1.0, 0.0);
U.reset();
X = SharedTensor2d(new Tensor2d("C2+D2 (IA|JB)", naoccA, navirA, naoccA, navirA));
X->sort(1432, Y, 1.0, 0.0);
X->axpy(Y, 0.5);
Y.reset();
// t_ij^ab <= D(ia,jb) + D(jb,ia)
// D_ij^ab = 1/2 \sum_{me} u_im^ae [2*W(me,jb) - W'(me,jb)]
Y = SharedTensor2d(new Tensor2d("2*W-W' (ME|JB)", naoccA, navirA, naoccA, navirA));
Y->axpy(W, -1.0);
W.reset();
W2 = SharedTensor2d(new Tensor2d("W (ME|JB)", naoccA, navirA, naoccA, navirA));
W2->read(psio_, PSIF_DFOCC_AMPS);
Y->axpy(W2, 2.0);
W2.reset();
U = SharedTensor2d(new Tensor2d("U2 (IA|JB)", naoccA, navirA, naoccA, navirA));
ccsd_u2_amps(U, t2);
X->gemm(false, false, U, Y, 0.5, 1.0);
U.reset();
Y.reset();
X->symmetrize();
Tnew = SharedTensor2d(new Tensor2d("New T2_2 (IA|JB)", naoccA, navirA, naoccA, navirA));
Tnew->read_symm(psio_, PSIF_DFOCC_AMPS);
Tnew->axpy(X, 2.0);
X.reset();
Tnew->write_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmbejT2");
} // end mp3_WmbejT2
//======================================================================
// WmbejT2AA
//======================================================================
void DFOCC::mp3_WmbejT2AA() {
// defs
SharedTensor2d K, L, T, T1, Tnew, U, Tau, W, W2, X, Y;
timer_on("WmbejT2");
// W_MBEJ = W(ME,JB)
// W(ME,JB) = (ME|JB) - <ME|JB>
W = SharedTensor2d(new Tensor2d("W (ME|JB)", naoccA, navirA, naoccA, navirA));
W->gemm(true, false, bQiaA, bQiaA, 1.0, 0.0);
L = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (IJ|AB)", naoccA, naoccA, navirA, navirA));
L->gemm(true, false, bQijA, bQabA, 1.0, 0.0);
W->sort(1324, L, -1.0, 1.0);
L.reset();
// X(IA,JB) = \sum(ME) T(IA,ME) W(ME,JB)
// T(IJ,AB) <= P_(IJ) * P_(AB) X(IA,JB)
T = SharedTensor2d(new Tensor2d("T2_1 <IJ|AB>", naoccA, naoccA, navirA, navirA));
T->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
U = SharedTensor2d(new Tensor2d("T2_1 (IA|JB)", naoccA, navirA, naoccA, navirA));
U->sort(1324, T, 1.0, 0.0);
T.reset();
X = SharedTensor2d(new Tensor2d("X (IA|JB)", naoccA, navirA, naoccA, navirA));
X->gemm(false, false, U, W, 1.0, 0.0);
U.reset();
W.reset();
/*
// Experimental: The following two examples work, too.
T = SharedTensor2d(new Tensor2d("T2_1 <IJ|AB>", naoccA, naoccA, navirA, navirA));
T->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
X = SharedTensor2d(new Tensor2d("X (IA|JB)", naoccA, navirA, naoccA, navirA));
//X->cont444("IAJB", "IMAE", "MEJB", true, false, T, W, 1.0, 0.0);
//X->cont444("IAJB", "IMAE", "MEJB", T, W, 1.0, 0.0);
*/
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <IJ|AB>", naoccA, naoccA, navirA, navirA));
Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew->P_ijab(X);
X.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
// W_MbEJ = W(ME,jb)
// W(ME,jb) = (ME|jb)
W = SharedTensor2d(new Tensor2d("W (ME|jb)", naoccA, navirA, naoccB, navirB));
W->gemm(true, false, bQiaA, bQiaB, 1.0, 0.0);
// X(IA,JB) = \sum(me) T(IA,me) W(JB,me)
// T(IJ,AB) <= P_(IJ) * P_(AB) X(IA,JB)
T = SharedTensor2d(new Tensor2d("T2_1 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
T->read(psio_, PSIF_DFOCC_AMPS);
U = SharedTensor2d(new Tensor2d("T2_1 (IA|jb)", naoccA, navirA, naoccB, navirB));
U->sort(1324, T, 1.0, 0.0);
T.reset();
X = SharedTensor2d(new Tensor2d("X (IA|JB)", naoccA, navirA, naoccA, navirA));
X->gemm(false, true, U, W, 1.0, 0.0);
U.reset();
W.reset();
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <IJ|AB>", naoccA, naoccA, navirA, navirA));
Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew->P_ijab(X);
X.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmbejT2");
} // end mp3_WmbejT2AA
//======================================================================
// WmbejT2BB
//======================================================================
void DFOCC::mp3_WmbejT2BB() {
// defs
SharedTensor2d K, L, T, T1, Tnew, U, Tau, W, W2, X, Y;
timer_on("WmbejT2");
// W_mbej = W(me,jb)
// W(me,jb) = (me|jb) - <me|jb>
W = SharedTensor2d(new Tensor2d("W (me|jb)", naoccB, navirB, naoccB, navirB));
W->gemm(true, false, bQiaB, bQiaB, 1.0, 0.0);
L = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (ij|ab)", naoccB, naoccB, navirB, navirB));
L->gemm(true, false, bQijB, bQabB, 1.0, 0.0);
W->sort(1324, L, -1.0, 1.0);
L.reset();
// X(ia,jb) = \sum(me) T(ia,me) W(me,jb)
// T(ij,ab) <= P_(ij) * P_(ab) X(ia,jb)
T = SharedTensor2d(new Tensor2d("T2_1 <ij|ab>", naoccB, naoccB, navirB, navirB));
T->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
U = SharedTensor2d(new Tensor2d("T2_1 (ia|jb)", naoccB, navirB, naoccB, navirB));
U->sort(1324, T, 1.0, 0.0);
T.reset();
X = SharedTensor2d(new Tensor2d("X (ia|jb)", naoccB, navirB, naoccB, navirB));
X->gemm(false, false, U, W, 1.0, 0.0);
U.reset();
W.reset();
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <ij|ab>", naoccB, naoccB, navirB, navirB));
Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew->P_ijab(X);
X.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
// W_MbEJ = W(ME,jb)
// W(ME,jb) = (ME|jb)
W = SharedTensor2d(new Tensor2d("W (ME|jb)", naoccA, navirA, naoccB, navirB));
W->gemm(true, false, bQiaA, bQiaB, 1.0, 0.0);
// X(ia,jb) = \sum(ME) T(ME,ia) W(ME,jb)
// T(ij,ab) <= P_(ij) * P_(ab) X(ia,jb)
T = SharedTensor2d(new Tensor2d("T2_1 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
T->read(psio_, PSIF_DFOCC_AMPS);
U = SharedTensor2d(new Tensor2d("T2_1 (IA|jb)", naoccA, navirA, naoccB, navirB));
U->sort(1324, T, 1.0, 0.0);
T.reset();
X = SharedTensor2d(new Tensor2d("X (ia|jb)", naoccB, navirB, naoccB, navirB));
X->gemm(true, false, U, W, 1.0, 0.0);
U.reset();
W.reset();
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <ij|ab>", naoccB, naoccB, navirB, navirB));
Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew->P_ijab(X);
X.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmbejT2");
} // end mp3_WmbejT2BB
//======================================================================
// WmbejT2AB
//======================================================================
void DFOCC::mp3_WmbejT2AB() {
// defs
SharedTensor2d K, L, T, T1, Tnew, U, Tau, W, W2, X, Y;
timer_on("WmbejT2");
// Read
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
Tnew->read(psio_, PSIF_DFOCC_AMPS);
// W_MBEJ = W(ME,JB)
// W(ME,JB) = (ME|JB) - <ME|JB>
W = SharedTensor2d(new Tensor2d("W (ME|JB)", naoccA, navirA, naoccA, navirA));
W->gemm(true, false, bQiaA, bQiaA, 1.0, 0.0);
L = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (IJ|AB)", naoccA, naoccA, navirA, navirA));
L->gemm(true, false, bQijA, bQabA, 1.0, 0.0);
W->sort(1324, L, -1.0, 1.0);
L.reset();
// X(IA,jb) = \sum(ME) T(ME,jb) W(ME,IA)
// T(Ij,Ab) <= X(IA,jb)
T = SharedTensor2d(new Tensor2d("T2_1 (IA|jb)", naoccA, navirA, naoccB, navirB));
T->read(psio_, PSIF_DFOCC_AMPS);
X = SharedTensor2d(new Tensor2d("X (IA|jb)", naoccA, navirA, naoccB, navirB));
X->gemm(true, false, W, T, 1.0, 0.0);
T.reset();
W.reset();
Tnew->sort(1324, X, 1.0, 1.0);
X.reset();
// W_mbej = W(me,jb)
// W(me,jb) = (me|jb) - <me|jb>
W = SharedTensor2d(new Tensor2d("W (me|jb)", naoccB, navirB, naoccB, navirB));
W->gemm(true, false, bQiaB, bQiaB, 1.0, 0.0);
L = SharedTensor2d(new Tensor2d("DF_BASIS_CC MO Ints (ij|ab)", naoccB, naoccB, navirB, navirB));
L->gemm(true, false, bQijB, bQabB, 1.0, 0.0);
W->sort(1324, L, -1.0, 1.0);
L.reset();
// X(IA,jb) = \sum(me) T(IA,me) W(me,jb)
// T(Ij,Ab) <= X(IA,jb)
T = SharedTensor2d(new Tensor2d("T2_1 (IA|jb)", naoccA, navirA, naoccB, navirB));
T->read(psio_, PSIF_DFOCC_AMPS);
X = SharedTensor2d(new Tensor2d("X (IA|jb)", naoccA, navirA, naoccB, navirB));
X->gemm(false, false, T, W, 1.0, 0.0);
T.reset();
W.reset();
Tnew->sort(1324, X, 1.0, 1.0);
X.reset();
// W_MbEJ = W(ME,jb)
// W(ME,jb) = (ME|jb)
W = SharedTensor2d(new Tensor2d("W (ME|jb)", naoccA, navirA, naoccB, navirB));
W->gemm(true, false, bQiaA, bQiaB, 1.0, 0.0);
// X(IA,jb) = \sum(ME) T(IA,ME) W(ME,jb)
// T(Ij,Ab) <= X(IA,jb)
T = SharedTensor2d(new Tensor2d("T2_1 (IA|JB)", naoccA, navirA, naoccA, navirA));
T->read_symm(psio_, PSIF_DFOCC_AMPS);
X = SharedTensor2d(new Tensor2d("X (IA|jb)", naoccA, navirA, naoccB, navirB));
X->gemm(false, false, T, W, 1.0, 0.0);
T.reset();
Tnew->sort(1324, X, 1.0, 1.0);
X.reset();
// X(IA,jb) = \sum(me) T(me,jb) W(IA,me)
// T(Ij,Ab) <= X(IA,jb)
T = SharedTensor2d(new Tensor2d("T2_1 (ia|jb)", naoccB, navirB, naoccB, navirB));
T->read_symm(psio_, PSIF_DFOCC_AMPS);
X = SharedTensor2d(new Tensor2d("X (IA|jb)", naoccA, navirA, naoccB, navirB));
X->gemm(false, false, W, T, 1.0, 0.0);
T.reset();
W.reset();
Tnew->sort(1324, X, 1.0, 1.0);
X.reset();
// W_mBEj = W(mE,jB)
// W(mE,jB) = - <mE|jB> = -(EB|mj)
W = SharedTensor2d(new Tensor2d("W (mE|jB)", naoccB, navirA, naoccB, navirA));
K = SharedTensor2d(new Tensor2d("Int (EB|mj)", navirA, navirA, naoccB, naoccB));
K->gemm(true, false, bQabA, bQijB, 1.0, 0.0);
W->sort(3142, K, -1.0, 0.0);
K.reset();
// X(Ib,jA) = \sum(mE) T(Im,Eb) W(mE,jA) = \sum(me) T'(Ib,mE) W(mE,jA)
// T(Ij,Ab) <= X(Ib,jA)
U = SharedTensor2d(new Tensor2d("T2_1 (IA|jb)", naoccA, navirA, naoccB, navirB));
U->read(psio_, PSIF_DFOCC_AMPS);
T = SharedTensor2d(new Tensor2d("T2_1 (Ib|jA)", naoccA, navirB, naoccB, navirA));
T->sort(1432, U, 1.0, 0.0);
U.reset();
X = SharedTensor2d(new Tensor2d("X (Ib|jA)", naoccA, navirB, naoccB, navirA));
X->gemm(false, false, T, W, 1.0, 0.0);
T.reset();
W.reset();
Tnew->sort(1342, X, 1.0, 1.0);
X.reset();
// W_MbeJ = W(Me,Jb)
// W(Me,Jb) = - <Me|Jb> = -(MJ|eb)
W = SharedTensor2d(new Tensor2d("W (Me|Jb)", naoccA, navirB, naoccA, navirB));
K = SharedTensor2d(new Tensor2d("Int (MJ|eb)", naoccA, naoccA, navirB, navirB));
K->gemm(true, false, bQijA, bQabB, 1.0, 0.0);
W->sort(1324, K, -1.0, 0.0);
K.reset();
// X(Ib,jA) = \sum(Me) T(Mj,Ae) W(Me,Ib) = \sum(me) T'(Me,jA) W(Me,Ib)
// T(Ij,Ab) <= X(Ib,jA)
U = SharedTensor2d(new Tensor2d("T2_1 (IA|jb)", naoccA, navirA, naoccB, navirB));
U->read(psio_, PSIF_DFOCC_AMPS);
T = SharedTensor2d(new Tensor2d("T2_1 (Ib|jA)", naoccA, navirB, naoccB, navirA));
T->sort(1432, U, 1.0, 0.0);
U.reset();
X = SharedTensor2d(new Tensor2d("X (Ib|jA)", naoccA, navirB, naoccB, navirA));
X->gemm(true, false, W, T, 1.0, 0.0);
T.reset();
W.reset();
Tnew->sort(1342, X, 1.0, 1.0);
X.reset();
// Write
Tnew->write(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WmbejT2");
} // end mp3_WmbejT2AB
//======================================================================
// WabefT2
//======================================================================
void DFOCC::mp3_WabefT2() {
// defs
SharedTensor2d K, M, L, I, T, Tnew, U, Tau, W, X, Y, S, A;
SharedTensor2d V, Vs, Ts, Va, Ta;
timer_on("WabefT2");
// t_ij^ab <= \sum_{ef} T_ij^ef <ab|ef>
// (+)T(ij, ab) = 1/2 (T_ij^ab + T_ji^ab) * (2 - \delta_{ab})
// (-)T(ij, ab) = 1/2 (T_ij^ab - T_ji^ab) * (2 - \delta_{ab})
U = SharedTensor2d(new Tensor2d("(+)T [I>=J|A>=B]", ntri_ijAA, ntri_abAA));
T = SharedTensor2d(new Tensor2d("(-)T [I>=J|A>=B]", ntri_ijAA, ntri_abAA));
#pragma omp parallel for
for (int i = 0; i < naoccA; ++i) {
for (int j = 0; j <= i; ++j) {
int ij = index2(i, j);
for (int a = 0; a < navirA; ++a) {
int ia = ia_idxAA->get(i, a);
int ja = ia_idxAA->get(j, a);
for (int b = 0; b <= a; ++b) {
double perm = (a == b ? 1.0 : 2.0);
int ab = index2(a, b);
int jb = ia_idxAA->get(j, b);
int ib = ia_idxAA->get(i, b);
double value1 = 0.5 * perm * (t2->get(ia, jb) + t2->get(ja, ib));
double value2 = 0.5 * perm * (t2->get(ia, jb) - t2->get(ja, ib));
U->set(ij, ab, value1);
T->set(ij, ab, value2);
}
}
}
}
// Read B(Q,ab)
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC B (AB|Q)", navirA * navirA, nQ));
K = bQabA->transpose();
// malloc
I = SharedTensor2d(new Tensor2d("I[A] <BF|E>", navirA * navirA, navirA));
Vs = SharedTensor2d(new Tensor2d("(+)V[A] (B, E>=F)", navirA, ntri_abAA));
Va = SharedTensor2d(new Tensor2d("(-)V[A] (B, E>=F)", navirA, ntri_abAA));
Ts = SharedTensor2d(new Tensor2d("(+)T[A] (B, I>=J)", navirA, ntri_ijAA));
Ta = SharedTensor2d(new Tensor2d("(-)T[B] (B, I>=J)", navirA, ntri_ijAA));
// Symmetric & Anti-symmetric contributions
S = SharedTensor2d(new Tensor2d("S (A>=B, I>=J)", ntri_abAA, ntri_ijAA));
A = SharedTensor2d(new Tensor2d("A (A>=B, I>=J)", ntri_abAA, ntri_ijAA));
// Main loop
for (int a = 0; a < navirA; ++a) {
int nb = a + 1;
// Form V[a](bf,e) = \sum_{Q} B(bfQ)*B(aeQ) cost = V^4N/2
I->contract(false, true, navirA * nb, navirA, nQ, K, K, 0, a * navirA * nQ, 1.0, 0.0);
// Form (+)V[a](b, e>=f)
#pragma omp parallel for
for (int b = 0; b <= a; ++b) {
for (int e = 0; e < navirA; ++e) {
int be = e + (b * navirA);
for (int f = 0; f <= e; ++f) {
int ef = index2(e, f);
int bf = f + (b * navirA);
double value1 = 0.5 * (I->get(bf, e) + I->get(be, f));
double value2 = 0.5 * (I->get(bf, e) - I->get(be, f));
Vs->set(b, ef, value1);
Va->set(b, ef, value2);
}
}
}
// Form T[a](b, i>=j) = \sum_{e>=f} Tau(i>=j,e>=f) V[a](b, e>=f)
Ts->contract(false, true, nb, ntri_ijAA, ntri_abAA, Vs, U, 1.0, 0.0);
Ta->contract(false, true, nb, ntri_ijAA, ntri_abAA, Va, T, 1.0, 0.0);
// Form S(ij,ab) & A(ij,ab)
#pragma omp parallel for
for (int b = 0; b <= a; ++b) {
int ab = index2(a, b);
for (int i = 0; i < naoccA; ++i) {
for (int j = 0; j <= i; ++j) {
int ij = index2(i, j);
S->add(ab, ij, Ts->get(b, ij));
A->add(ab, ij, Ta->get(b, ij));
}
}
}
}
K.reset();
I.reset();
Vs.reset();
Va.reset();
Ts.reset();
Ta.reset();
U.reset();
T.reset();
// T(ia,jb) <-- S(a>=b,i>=j) + A(a>=b,i>=j)
Tnew = SharedTensor2d(new Tensor2d("New T2_2 (IA|JB)", naoccA, navirA, naoccA, navirA));
Tnew->read_symm(psio_, PSIF_DFOCC_AMPS);
#pragma omp parallel for
for (int a = 0; a < navirA; ++a) {
for (int b = 0; b < navirA; ++b) {
int ab = index2(a, b);
for (int i = 0; i < naoccA; ++i) {
int ia = ia_idxAA->get(i, a);
for (int j = 0; j < naoccA; ++j) {
int jb = ia_idxAA->get(j, b);
int ij = index2(i, j);
int perm1 = (i > j) ? 1 : -1;
int perm2 = (a > b) ? 1 : -1;
double value = S->get(ab, ij) + (perm1 * perm2 * A->get(ab, ij));
Tnew->add(ia, jb, value);
}
}
}
}
S.reset();
A.reset();
Tnew->write_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WabefT2");
} // end mp3_WabefT2
//======================================================================
// WabefT2AA
//======================================================================
void DFOCC::mp3_WabefT2AA() {
// defs
SharedTensor2d K, M, L, I, T, Tnew, U, Tau, W, X, Y, S, A;
SharedTensor2d V, Vs, Ts, Va, Ta;
timer_on("WabefT2");
// t_ij^ab <= 1/2 \sum_{ef} T_ij^ef <ab||ef> = \sum_{ef} T_ij^ef <ab|ef>
// (-)T(ij, ab) = 1/2 (T_ij^ab - T_ji^ab) * (2 - \delta_{ab})
X = SharedTensor2d(new Tensor2d("T2_1 <IJ|AB>", naoccA, naoccA, navirA, navirA));
X->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
T = SharedTensor2d(new Tensor2d("(-)T [I>=J|A>=B]", ntri_ijAA, ntri_abAA));
T->antisymm_col_packed4(X);
X.reset();
// Read B(Q,ab)
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC B (AB|Q)", navirA * navirA, nQ));
K = bQabA->transpose();
// malloc
I = SharedTensor2d(new Tensor2d("I[A] <BF|E>", navirA * navirA, navirA));
Va = SharedTensor2d(new Tensor2d("(-)V[A] (B, E>=F)", navirA, ntri_abAA));
Ta = SharedTensor2d(new Tensor2d("(-)T[B] (B, I>=J)", navirA, ntri_ijAA));
// Anti-symmetric contributions
A = SharedTensor2d(new Tensor2d("A (A>=B, I>=J)", ntri_abAA, ntri_ijAA));
// Main loop
for (int a = 0; a < navirA; ++a) {
int nb = a + 1;
// Form V[a](bf,e) = \sum_{Q} B(bfQ)*B(aeQ) cost = V^4N/2
I->contract(false, true, navirA * nb, navirA, nQ, K, K, 0, a * navirA * nQ, 1.0, 0.0);
// Form (+)V[a](b, e>=f)
#pragma omp parallel for
for (int b = 0; b <= a; ++b) {
for (int e = 0; e < navirA; ++e) {
int be = e + (b * navirA);
for (int f = 0; f <= e; ++f) {
int ef = index2(e, f);
int bf = f + (b * navirA);
double value2 = 0.5 * (I->get(bf, e) - I->get(be, f));
Va->set(b, ef, value2);
}
}
}
// Form T[a](b, i>=j) = 1/2\sum_{e>=f} Tau(i>=j,e>=f) V[a](b, e>=f)
Ta->contract(false, true, nb, ntri_ijAA, ntri_abAA, Va, T, 1.0, 0.0);
// Form A(ij,ab)
#pragma omp parallel for
for (int b = 0; b <= a; ++b) {
int ab = index2(a, b);
for (int i = 0; i < naoccA; ++i) {
for (int j = 0; j <= i; ++j) {
int ij = index2(i, j);
A->add(ab, ij, Ta->get(b, ij));
}
}
}
}
K.reset();
I.reset();
Va.reset();
Ta.reset();
T.reset();
// T(ia,jb) <-- A(a>=b,i>=j)
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <IJ|AB>", naoccA, naoccA, navirA, navirA));
Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
#pragma omp parallel for
for (int a = 0; a < navirA; ++a) {
for (int b = 0; b < navirA; ++b) {
int ab = index2(a, b);
int ab2 = ab_idxAA->get(a, b);
for (int i = 0; i < naoccA; ++i) {
for (int j = 0; j < naoccA; ++j) {
int ij2 = ij_idxAA->get(i, j);
int ij = index2(i, j);
int perm1 = (i > j) ? 1 : -1;
int perm2 = (a > b) ? 1 : -1;
double value = perm1 * perm2 * A->get(ab, ij);
Tnew->add(ij2, ab2, value);
}
}
}
}
A.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WabefT2");
} // end mp3_WabefT2AA
//======================================================================
// WabefT2BB
//======================================================================
void DFOCC::mp3_WabefT2BB() {
// defs
SharedTensor2d K, M, L, I, T, Tnew, U, Tau, W, X, Y, S, A;
SharedTensor2d V, Vs, Ts, Va, Ta;
timer_on("WabefT2");
// t_ij^ab <= 1/2 \sum_{ef} T_ij^ef <ab||ef> = \sum_{ef} T_ij^ef <ab|ef>
// (-)T(ij, ab) = 1/2 (T_ij^ab - T_ji^ab) * (2 - \delta_{ab})
X = SharedTensor2d(new Tensor2d("T2_1 <ij|ab>", naoccB, naoccB, navirB, navirB));
X->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
T = SharedTensor2d(new Tensor2d("(-)T [I>=J|A>=B]", ntri_ijBB, ntri_abBB));
T->antisymm_col_packed4(X);
X.reset();
// Read B(Q,ab)
K = SharedTensor2d(new Tensor2d("DF_BASIS_CC B (ab|Q)", navirB * navirB, nQ));
K = bQabB->transpose();
// malloc
I = SharedTensor2d(new Tensor2d("I[A] <BF|E>", navirB * navirB, navirB));
Va = SharedTensor2d(new Tensor2d("(-)V[A] (B, E>=F)", navirB, ntri_abBB));
Ta = SharedTensor2d(new Tensor2d("(-)T[B] (B, I>=J)", navirB, ntri_ijBB));
// Anti-symmetric contributions
A = SharedTensor2d(new Tensor2d("A (A>=B, I>=J)", ntri_abBB, ntri_ijBB));
// Main loop
for (int a = 0; a < navirB; ++a) {
int nb = a + 1;
// Form V[a](bf,e) = \sum_{Q} B(bfQ)*B(aeQ) cost = V^4N/2
I->contract(false, true, navirB * nb, navirB, nQ, K, K, 0, a * navirB * nQ, 1.0, 0.0);
// Form (+)V[a](b, e>=f)
#pragma omp parallel for
for (int b = 0; b <= a; ++b) {
for (int e = 0; e < navirB; ++e) {
int be = e + (b * navirB);
for (int f = 0; f <= e; ++f) {
int ef = index2(e, f);
int bf = f + (b * navirB);
double value2 = 0.5 * (I->get(bf, e) - I->get(be, f));
Va->set(b, ef, value2);
}
}
}
// Form T[a](b, i>=j) = \sum_{e>=f} Tau(i>=j,e>=f) V[a](b, e>=f)
Ta->contract(false, true, nb, ntri_ijBB, ntri_abBB, Va, T, 1.0, 0.0);
// Form A(ij,ab)
#pragma omp parallel for
for (int b = 0; b <= a; ++b) {
int ab = index2(a, b);
for (int i = 0; i < naoccB; ++i) {
for (int j = 0; j <= i; ++j) {
int ij = index2(i, j);
A->add(ab, ij, Ta->get(b, ij));
}
}
}
}
K.reset();
I.reset();
Va.reset();
Ta.reset();
T.reset();
// T(ia,jb) <-- A(a>=b,i>=j)
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <ij|ab>", naoccB, naoccB, navirB, navirB));
Tnew->read_anti_symm(psio_, PSIF_DFOCC_AMPS);
#pragma omp parallel for
for (int a = 0; a < navirB; ++a) {
for (int b = 0; b < navirB; ++b) {
int ab = index2(a, b);
int ab2 = ab_idxBB->get(a, b);
for (int i = 0; i < naoccB; ++i) {
for (int j = 0; j < naoccB; ++j) {
int ij2 = ij_idxBB->get(i, j);
int ij = index2(i, j);
int perm1 = (i > j) ? 1 : -1;
int perm2 = (a > b) ? 1 : -1;
double value = perm1 * perm2 * A->get(ab, ij);
Tnew->add(ij2, ab2, value);
}
}
}
}
A.reset();
Tnew->write_anti_symm(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WabefT2");
} // end mp3_WabefT2BB
//======================================================================
// WabefT2AB
//======================================================================
void DFOCC::mp3_WabefT2AB() {
// defs
SharedTensor2d K, M, L, I, J, T, Tnew, U, Tau, W, X, Y, S, A;
timer_on("WabefT2");
// Read
Tnew = SharedTensor2d(new Tensor2d("New T2_2 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
Tnew->read(psio_, PSIF_DFOCC_AMPS);
// t_Ij^Ab <= \sum_{Ef} T_Ij^Ef <Ab|Ef>
T = SharedTensor2d(new Tensor2d("T2_1 <Ij|Ab>", naoccA, naoccB, navirA, navirB));
T->read(psio_, PSIF_DFOCC_AMPS);
// malloc
J = SharedTensor2d(new Tensor2d("J[A] <E|bf>", navirA, navirB * navirB));
I = SharedTensor2d(new Tensor2d("I[A] <b|Ef>", navirB, navirA * navirB));
X = SharedTensor2d(new Tensor2d("T[A] <b|Ij>", navirB, naoccA * naoccB));
K = SharedTensor2d(new Tensor2d("B[A] <E|Q>", navirA, nQ));
// Main loop
for (int a = 0; a < navirA; ++a) {
// Form B[A](e,Q)
#pragma omp parallel for
for (int Q = 0; Q < nQ; ++Q) {
for (int e = 0; e < navirA; ++e) {
int ae = ab_idxAA->get(a, e);
K->set(e, Q, bQabA->get(Q, ae));
}
}
// Form J[A](E,bf) = \sum_{Q} B[A](e,Q) * B(Q,bf)
J->gemm(false, false, K, bQabB, 1.0, 0.0);
// Form I[A](b,Ef)
#pragma omp parallel for
for (int b = 0; b < navirB; ++b) {
for (int e = 0; e < navirA; ++e) {
for (int f = 0; f < navirB; ++f) {
int bf = f + (b * navirB);
int ef = ab_idxAB->get(e, f);
I->set(b, ef, J->get(e, bf));
}
}
}
// Form T[A](b,Ij) = \sum_{Ef} I[A](b, Ef) T(Ij,Ef)
X->gemm(false, true, I, T, 1.0, 0.0);
// T[A](b,Ij) --> T(Ij,Ab)
#pragma omp parallel for
for (int b = 0; b < navirB; ++b) {
int ab = ab_idxAB->get(a, b);
for (int i = 0; i < naoccA; ++i) {
for (int j = 0; j < naoccB; ++j) {
int ij = ij_idxAB->get(i, j);
Tnew->add(ij, ab, X->get(b, ij));
}
}
}
}
K.reset();
J.reset();
I.reset();
T.reset();
X.reset();
/*
// <Ab|Ef> = (AE|bf)
J = SharedTensor2d(new Tensor2d("J (AE|bf)", navirA, navirA, navirB, navirB));
J->gemm(true, false, bQabA, bQabB, 1.0, 0.0);
I = SharedTensor2d(new Tensor2d("I <Ab|Ef>", navirA, navirB, navirA, navirB));
I->sort(1324, J, 1.0, 0.0);
J.reset();
// t_Ij^Ab <= \sum_{Ef} T_Ij^Ef <Ab|Ef>
Tnew->gemm(false, true, T, I, 1.0, 1.0);
I.reset();
T.reset();
*/
// Write
Tnew->write(psio_, PSIF_DFOCC_AMPS);
Tnew.reset();
timer_off("WabefT2");
} // end mp3_WabefT2AB
} // namespace dfoccwave
} // namespace psi
| dgasmith/psi4 | psi4/src/psi4/dfocc/mp3_W_intr.cc | C++ | lgpl-3.0 | 37,479 |
#include "testutils/QueueMapTest.h"
#include <boost/optional/optional_io.hpp>
class QueueMapPeekTest: public QueueMapTest {};
TEST_F(QueueMapPeekTest, PoppingFromEmpty) {
EXPECT_EQ(boost::none, peek());
}
TEST_F(QueueMapPeekTest, PushingOne) {
push(3, 2);
EXPECT_EQ(2, peek().value());
}
TEST_F(QueueMapPeekTest, PushingTwo) {
push(2, 3);
push(3, 4);
EXPECT_EQ(3, peek().value());
EXPECT_EQ(3, peek().value());
EXPECT_EQ(3, pop().value());
EXPECT_EQ(4, peek().value());
EXPECT_EQ(4, peek().value());
EXPECT_EQ(4, pop().value());
EXPECT_EQ(boost::none, peek());
EXPECT_EQ(boost::none, pop());
}
TEST_F(QueueMapPeekTest, AfterPushingTwoAndPoppingFirst) {
push(2, 3);
push(3, 4);
pop(2);
EXPECT_EQ(boost::none, pop(2));
EXPECT_EQ(4, peek().value());
}
| davesteele/cryfs | test/blockstore/implementations/caching/cache/QueueMapTest_Peek.cpp | C++ | lgpl-3.0 | 790 |
-- sessions table used for database sessions
begin;
---------------------------------------------------------------------------
create table sessions (
id varchar primary key,
data text,
inserted timestamptz(0) default current_timestamp,
updated timestamptz(0) default current_timestamp
);
---------------------------------------------------------------------------
commit;
| BlackEarth/bweb | bweb/models/psql/sessions.sql | SQL | lgpl-3.0 | 414 |
<?php
// PHP security model doesnt allow to require php files in current directory
// but.. /tmp is in path.. and well.. /home looks legit too.
// looks like a good security model :D</ironic>
//
// PHP Warning: include(): open_basedir restriction in effect. File(...) is
// not within the allowed path(s): (/srv/http/:/home/:/tmp/:/usr/share/pear/)
// in /opt/prg/radare2/r2-bindings/php5/test-r_core.php on line 3
// Use system() as long as it's not banned by the default security restrictions
// like copy() does :D
system ("cp r_core.php /tmp");
require "/tmp/r_core.php";
print "[[ PHP-Radare shell ]]\n";
$c = new RCore ();
$c->file_open ("/bin/ls", 0, 0);
$c->prompt_loop ();
?>
| glandium/radare2 | r2-bindings/php5/test-r_core.php | PHP | lgpl-3.0 | 689 |
package cn.wensiqun.asmsupport.sample.client.json.demo;
/**
* Contains data for the subdivisions associated with an IP address.
*
* This record is returned by all the end points except the Country end point.
*/
final public class Subdivision {
private Integer confidence;
private String isoCode;
public Integer getConfidence() {
return confidence;
}
public void setConfidence(Integer confidence) {
this.confidence = confidence;
}
public String getIsoCode() {
return isoCode;
}
public void setIsoCode(String isoCode) {
this.isoCode = isoCode;
}
} | IBYoung/asmsupport | asmsupport-sample/src/main/java/cn/wensiqun/asmsupport/sample/client/json/demo/Subdivision.java | Java | lgpl-3.0 | 638 |
# encoding: utf-8
"""
Utilities for getting information about IPython and the system it's running in.
"""
#-----------------------------------------------------------------------------
# Copyright (C) 2008-2011 The IPython Development Team
#
# Distributed under the terms of the BSD License. The full license is in
# the file COPYING, distributed as part of this software.
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
# Imports
#-----------------------------------------------------------------------------
import os
import platform
import pprint
import sys
import subprocess
from ConfigParser import ConfigParser
from IPython.core import release
from IPython.utils import py3compat, _sysinfo, encoding
#-----------------------------------------------------------------------------
# Code
#-----------------------------------------------------------------------------
def pkg_commit_hash(pkg_path):
"""Get short form of commit hash given directory `pkg_path`
We get the commit hash from (in order of preference):
* IPython.utils._sysinfo.commit
* git output, if we are in a git repository
If these fail, we return a not-found placeholder tuple
Parameters
----------
pkg_path : str
directory containing package
only used for getting commit from active repo
Returns
-------
hash_from : str
Where we got the hash from - description
hash_str : str
short form of hash
"""
# Try and get commit from written commit text file
if _sysinfo.commit:
return "installation", _sysinfo.commit
# maybe we are in a repository
proc = subprocess.Popen('git rev-parse --short HEAD',
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
cwd=pkg_path, shell=True)
repo_commit, _ = proc.communicate()
if repo_commit:
return 'repository', repo_commit.strip()
return '(none found)', '<not found>'
def pkg_info(pkg_path):
"""Return dict describing the context of this package
Parameters
----------
pkg_path : str
path containing __init__.py for package
Returns
-------
context : dict
with named parameters of interest
"""
src, hsh = pkg_commit_hash(pkg_path)
return dict(
ipython_version=release.version,
ipython_path=pkg_path,
commit_source=src,
commit_hash=hsh,
sys_version=sys.version,
sys_executable=sys.executable,
sys_platform=sys.platform,
platform=platform.platform(),
os_name=os.name,
default_encoding=encoding.DEFAULT_ENCODING,
)
@py3compat.doctest_refactor_print
def sys_info():
"""Return useful information about IPython and the system, as a string.
Example
-------
In [2]: print sys_info()
{'commit_hash': '144fdae', # random
'commit_source': 'repository',
'ipython_path': '/home/fperez/usr/lib/python2.6/site-packages/IPython',
'ipython_version': '0.11.dev',
'os_name': 'posix',
'platform': 'Linux-2.6.35-22-generic-i686-with-Ubuntu-10.10-maverick',
'sys_executable': '/usr/bin/python',
'sys_platform': 'linux2',
'sys_version': '2.6.6 (r266:84292, Sep 15 2010, 15:52:39) \\n[GCC 4.4.5]'}
"""
p = os.path
path = p.dirname(p.abspath(p.join(__file__, '..')))
return pprint.pformat(pkg_info(path))
def _num_cpus_unix():
"""Return the number of active CPUs on a Unix system."""
return os.sysconf("SC_NPROCESSORS_ONLN")
def _num_cpus_darwin():
"""Return the number of active CPUs on a Darwin system."""
p = subprocess.Popen(['sysctl','-n','hw.ncpu'],stdout=subprocess.PIPE)
return p.stdout.read()
def _num_cpus_windows():
"""Return the number of active CPUs on a Windows system."""
return os.environ.get("NUMBER_OF_PROCESSORS")
def num_cpus():
"""Return the effective number of CPUs in the system as an integer.
This cross-platform function makes an attempt at finding the total number of
available CPUs in the system, as returned by various underlying system and
python calls.
If it can't find a sensible answer, it returns 1 (though an error *may* make
it return a large positive number that's actually incorrect).
"""
# Many thanks to the Parallel Python project (http://www.parallelpython.com)
# for the names of the keys we needed to look up for this function. This
# code was inspired by their equivalent function.
ncpufuncs = {'Linux':_num_cpus_unix,
'Darwin':_num_cpus_darwin,
'Windows':_num_cpus_windows,
# On Vista, python < 2.5.2 has a bug and returns 'Microsoft'
# See http://bugs.python.org/issue1082 for details.
'Microsoft':_num_cpus_windows,
}
ncpufunc = ncpufuncs.get(platform.system(),
# default to unix version (Solaris, AIX, etc)
_num_cpus_unix)
try:
ncpus = max(1,int(ncpufunc()))
except:
ncpus = 1
return ncpus
| cloud9ers/gurumate | environment/lib/python2.7/site-packages/IPython/utils/sysinfo.py | Python | lgpl-3.0 | 5,232 |
/*
* SonarQube, open source software quality management tool.
* Copyright (C) 2008-2014 SonarSource
* mailto:contact AT sonarsource DOT com
*
* SonarQube is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
*
* SonarQube is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
package org.sonar.api.utils;
import java.io.NotSerializableException;
import java.io.ObjectInputStream;
import java.io.ObjectOutputStream;
import java.lang.ref.Reference;
import java.lang.ref.SoftReference;
import java.text.DateFormat;
import java.text.FieldPosition;
import java.text.ParsePosition;
import java.text.SimpleDateFormat;
import java.util.Date;
import javax.annotation.CheckForNull;
import javax.annotation.Nullable;
/**
* Parses and formats <a href="http://en.wikipedia.org/wiki/ISO_8601">ISO 8601</a> dates.
* This class is thread-safe.
*
* @since 2.7
*/
public final class DateUtils {
public static final String DATE_FORMAT = "yyyy-MM-dd";
public static final String DATETIME_FORMAT = "yyyy-MM-dd'T'HH:mm:ssZ";
private static final ThreadSafeDateFormat THREAD_SAFE_DATE_FORMAT = new ThreadSafeDateFormat(DATE_FORMAT);
private static final ThreadSafeDateFormat THREAD_SAFE_DATETIME_FORMAT = new ThreadSafeDateFormat(DATETIME_FORMAT);
private DateUtils() {
}
public static String formatDate(Date d) {
return THREAD_SAFE_DATE_FORMAT.format(d);
}
public static String formatDateTime(Date d) {
return THREAD_SAFE_DATETIME_FORMAT.format(d);
}
public static String formatDateTimeNullSafe(@Nullable Date date) {
return date == null ? "" : THREAD_SAFE_DATETIME_FORMAT.format(date);
}
@CheckForNull
public static Date longToDate(@Nullable Long time) {
return time == null ? null : new Date(time);
}
@CheckForNull
public static Long dateToLong(@Nullable Date date) {
return date == null ? null : date.getTime();
}
/**
* @param s string in format {@link #DATE_FORMAT}
* @throws SonarException when string cannot be parsed
*/
public static Date parseDate(String s) {
ParsePosition pos = new ParsePosition(0);
Date result = THREAD_SAFE_DATE_FORMAT.parse(s, pos);
if (pos.getIndex() != s.length()) {
throw new SonarException("The date '" + s + "' does not respect format '" + DATE_FORMAT + "'");
}
return result;
}
/**
* Parse format {@link #DATE_FORMAT}. This method never throws exception.
*
* @param s any string
* @return the date, {@code null} if parsing error or if parameter is {@code null}
* @since 3.0
*/
@CheckForNull
public static Date parseDateQuietly(@Nullable String s) {
Date date = null;
if (s != null) {
try {
date = parseDate(s);
} catch (RuntimeException e) {
// ignore
}
}
return date;
}
/**
* @param s string in format {@link #DATETIME_FORMAT}
* @throws SonarException when string cannot be parsed
*/
public static Date parseDateTime(String s) {
ParsePosition pos = new ParsePosition(0);
Date result = THREAD_SAFE_DATETIME_FORMAT.parse(s, pos);
if (pos.getIndex() != s.length()) {
throw new SonarException("The date '" + s + "' does not respect format '" + DATETIME_FORMAT + "'");
}
return result;
}
/**
* Parse format {@link #DATETIME_FORMAT}. This method never throws exception.
*
* @param s any string
* @return the datetime, {@code null} if parsing error or if parameter is {@code null}
*/
@CheckForNull
public static Date parseDateTimeQuietly(@Nullable String s) {
Date datetime = null;
if (s != null) {
try {
datetime = parseDateTime(s);
} catch (RuntimeException e) {
// ignore
}
}
return datetime;
}
public static Date addDays(Date date, int numberOfDays) {
return org.apache.commons.lang.time.DateUtils.addDays(date, numberOfDays);
}
static class ThreadSafeDateFormat extends DateFormat {
private final String format;
private final ThreadLocal<Reference<DateFormat>> cache = new ThreadLocal<Reference<DateFormat>>() {
@Override
public Reference<DateFormat> get() {
Reference<DateFormat> softRef = super.get();
if (softRef == null || softRef.get() == null) {
SimpleDateFormat sdf = new SimpleDateFormat(format);
sdf.setLenient(false);
softRef = new SoftReference<DateFormat>(sdf);
super.set(softRef);
}
return softRef;
}
};
ThreadSafeDateFormat(String format) {
this.format = format;
}
private DateFormat getDateFormat() {
return (DateFormat) ((Reference) cache.get()).get();
}
@Override
public StringBuffer format(Date date, StringBuffer toAppendTo, FieldPosition fieldPosition) {
return getDateFormat().format(date, toAppendTo, fieldPosition);
}
@Override
public Date parse(String source, ParsePosition pos) {
return getDateFormat().parse(source, pos);
}
private void readObject(ObjectInputStream ois) throws NotSerializableException {
throw new NotSerializableException();
}
private void writeObject(ObjectOutputStream ois) throws NotSerializableException {
throw new NotSerializableException();
}
}
}
| abbeyj/sonarqube | sonar-plugin-api/src/main/java/org/sonar/api/utils/DateUtils.java | Java | lgpl-3.0 | 5,841 |
--Copyright (C) 2010 <SWGEmu>
--This File is part of Core3.
--This program is free software; you can redistribute
--it and/or modify it under the terms of the GNU Lesser
--General Public License as published by the Free Software
--Foundation; either version 2 of the License,
--or (at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--See the GNU Lesser General Public License for
--more details.
--You should have received a copy of the GNU Lesser General
--Public License along with this program; if not, write to
--the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--Linking Engine3 statically or dynamically with other modules
--is making a combined work based on Engine3.
--Thus, the terms and conditions of the GNU Lesser General Public License
--cover the whole combination.
--In addition, as a special exception, the copyright holders of Engine3
--give you permission to combine Engine3 program with free software
--programs or libraries that are released under the GNU LGPL and with
--code included in the standard release of Core3 under the GNU LGPL
--license (or modified versions of such code, with unchanged license).
--You may copy and distribute such a system following the terms of the
--GNU LGPL for Engine3 and the licenses of the other code concerned,
--provided that you include the source code of that other code when
--and as the GNU LGPL requires distribution of source code.
--Note that people who make modified versions of Engine3 are not obligated
--to grant this special exception for their modified versions;
--it is their choice whether to do so. The GNU Lesser General Public License
--gives permission to release a modified version without this exception;
--this exception also makes it possible to release a modified version
object_tangible_component_weapon_rancor_tooth_quest = object_tangible_component_weapon_shared_rancor_tooth_quest:new {
}
ObjectTemplates:addTemplate(object_tangible_component_weapon_rancor_tooth_quest, "object/tangible/component/weapon/rancor_tooth_quest.iff")
| kidaa/Awakening-Core3 | bin/scripts/object/tangible/component/weapon/rancor_tooth_quest.lua | Lua | lgpl-3.0 | 2,264 |
// Copyright 2016 The go-ethereum Authors
// This file is part of the go-ethereum library.
//
// The go-ethereum library is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The go-ethereum library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with the go-ethereum library. If not, see <http://www.gnu.org/licenses/>.
package kademlia
import (
"fmt"
"math"
"math/rand"
"os"
"path/filepath"
"reflect"
"testing"
"testing/quick"
"time"
)
var (
quickrand = rand.New(rand.NewSource(time.Now().Unix()))
quickcfgFindClosest = &quick.Config{MaxCount: 50, Rand: quickrand}
quickcfgBootStrap = &quick.Config{MaxCount: 100, Rand: quickrand}
)
type testNode struct {
addr Address
}
func (n *testNode) String() string {
return fmt.Sprintf("%x", n.addr[:])
}
func (n *testNode) Addr() Address {
return n.addr
}
func (n *testNode) Drop() {
}
func (n *testNode) Url() string {
return ""
}
func (n *testNode) LastActive() time.Time {
return time.Now()
}
func TestOn(t *testing.T) {
addr, ok1 := gen(Address{}, quickrand).(Address)
other, ok2 := gen(Address{}, quickrand).(Address)
if !ok1 || !ok2 {
t.Errorf("oops")
}
kad := New(addr, NewDefaultKadParams())
err := kad.On(&testNode{addr: other}, nil)
_ = err
}
func TestBootstrap(t *testing.T) {
test := func(test *bootstrapTest) bool {
// for any node kad.le, Target and N
params := NewDefaultKadParams()
params.MaxProx = test.MaxProx
params.BucketSize = test.BucketSize
params.ProxBinSize = test.BucketSize
kad := New(test.Self, params)
var err error
for p := 0; p < 9; p++ {
var nrs []*NodeRecord
n := math.Pow(float64(2), float64(7-p))
for i := 0; i < int(n); i++ {
addr := RandomAddressAt(test.Self, p)
nrs = append(nrs, &NodeRecord{
Addr: addr,
})
}
kad.Add(nrs)
}
node := &testNode{test.Self}
n := 0
for n < 100 {
err = kad.On(node, nil)
if err != nil {
t.Fatalf("backend not accepting node: %v", err)
}
record, need, _ := kad.Suggest()
if !need {
break
}
n++
if record == nil {
continue
}
node = &testNode{record.Addr}
}
exp := test.BucketSize * (test.MaxProx + 1)
if kad.Count() != exp {
t.Errorf("incorrect number of peers, expected %d, got %d\n%v", exp, kad.Count(), kad)
return false
}
return true
}
if err := quick.Check(test, quickcfgBootStrap); err != nil {
t.Error(err)
}
}
func TestFindClosest(t *testing.T) {
test := func(test *FindClosestTest) bool {
// for any node kad.le, Target and N
params := NewDefaultKadParams()
params.MaxProx = 7
kad := New(test.Self, params)
var err error
for _, node := range test.All {
err = kad.On(node, nil)
if err != nil && err.Error() != "bucket full" {
t.Fatalf("backend not accepting node: %v", err)
}
}
if len(test.All) == 0 || test.N == 0 {
return true
}
nodes := kad.FindClosest(test.Target, test.N)
// check that the number of results is min(N, kad.len)
wantN := test.N
if tlen := kad.Count(); tlen < test.N {
wantN = tlen
}
if len(nodes) != wantN {
t.Errorf("wrong number of nodes: got %d, want %d", len(nodes), wantN)
return false
}
if hasDuplicates(nodes) {
t.Errorf("result contains duplicates")
return false
}
if !sortedByDistanceTo(test.Target, nodes) {
t.Errorf("result is not sorted by distance to target")
return false
}
// check that the result nodes have minimum distance to target.
farthestResult := nodes[len(nodes)-1].Addr()
for i, b := range kad.buckets {
for j, n := range b {
if contains(nodes, n.Addr()) {
continue // don't run the check below for nodes in result
}
if test.Target.ProxCmp(n.Addr(), farthestResult) < 0 {
_ = i * j
t.Errorf("kad.le contains node that is closer to target but it's not in result")
return false
}
}
}
return true
}
if err := quick.Check(test, quickcfgFindClosest); err != nil {
t.Error(err)
}
}
type proxTest struct {
add bool
index int
addr Address
}
var (
addresses []Address
)
func TestProxAdjust(t *testing.T) {
r := rand.New(rand.NewSource(time.Now().UnixNano()))
self := gen(Address{}, r).(Address)
params := NewDefaultKadParams()
params.MaxProx = 7
kad := New(self, params)
var err error
for i := 0; i < 100; i++ {
a := gen(Address{}, r).(Address)
addresses = append(addresses, a)
err = kad.On(&testNode{addr: a}, nil)
if err != nil && err.Error() != "bucket full" {
t.Fatalf("backend not accepting node: %v", err)
}
if !kad.proxCheck(t) {
return
}
}
test := func(test *proxTest) bool {
node := &testNode{test.addr}
if test.add {
kad.On(node, nil)
} else {
kad.Off(node, nil)
}
return kad.proxCheck(t)
}
if err := quick.Check(test, quickcfgFindClosest); err != nil {
t.Error(err)
}
}
func TestSaveLoad(t *testing.T) {
r := rand.New(rand.NewSource(time.Now().UnixNano()))
addresses := gen([]Address{}, r).([]Address)
self := RandomAddress()
params := NewDefaultKadParams()
params.MaxProx = 7
kad := New(self, params)
var err error
for _, a := range addresses {
err = kad.On(&testNode{addr: a}, nil)
if err != nil && err.Error() != "bucket full" {
t.Fatalf("backend not accepting node: %v", err)
}
}
nodes := kad.FindClosest(self, 100)
path := filepath.Join(os.TempDir(), "bzz-kad-test-save-load.peers")
err = kad.Save(path, nil)
if err != nil && err.Error() != "bucket full" {
t.Fatalf("unepected error saving kaddb: %v", err)
}
kad = New(self, params)
err = kad.Load(path, nil)
if err != nil && err.Error() != "bucket full" {
t.Fatalf("unepected error loading kaddb: %v", err)
}
for _, b := range kad.db.Nodes {
for _, node := range b {
err = kad.On(&testNode{node.Addr}, nil)
if err != nil && err.Error() != "bucket full" {
t.Fatalf("backend not accepting node: %v", err)
}
}
}
loadednodes := kad.FindClosest(self, 100)
for i, node := range loadednodes {
if nodes[i].Addr() != node.Addr() {
t.Errorf("node mismatch at %d/%d: %v != %v", i, len(nodes), nodes[i].Addr(), node.Addr())
}
}
}
func (self *Kademlia) proxCheck(t *testing.T) bool {
var sum int
for i, b := range self.buckets {
l := len(b)
// if we are in the high prox multibucket
if i >= self.proxLimit {
sum += l
} else if l == 0 {
t.Errorf("bucket %d empty, yet proxLimit is %d\n%v", len(b), self.proxLimit, self)
return false
}
}
// check if merged high prox bucket does not exceed size
if sum > 0 {
if sum != self.proxSize {
t.Errorf("proxSize incorrect, expected %v, got %v", sum, self.proxSize)
return false
}
last := len(self.buckets[self.proxLimit])
if last > 0 && sum >= self.ProxBinSize+last {
t.Errorf("proxLimit %v incorrect, redundant non-empty bucket %d added to proxBin with %v (target %v)\n%v", self.proxLimit, last, sum-last, self.ProxBinSize, self)
return false
}
if self.proxLimit > 0 && sum < self.ProxBinSize {
t.Errorf("proxLimit %v incorrect. proxSize %v is less than target %v, yet there is more peers", self.proxLimit, sum, self.ProxBinSize)
return false
}
}
return true
}
type bootstrapTest struct {
MaxProx int
BucketSize int
Self Address
}
func (*bootstrapTest) Generate(rand *rand.Rand, size int) reflect.Value {
t := &bootstrapTest{
Self: gen(Address{}, rand).(Address),
MaxProx: 5 + rand.Intn(2),
BucketSize: rand.Intn(3) + 1,
}
return reflect.ValueOf(t)
}
type FindClosestTest struct {
Self Address
Target Address
All []Node
N int
}
func (c FindClosestTest) String() string {
return fmt.Sprintf("A: %064x\nT: %064x\n(%d)\n", c.Self[:], c.Target[:], c.N)
}
func (*FindClosestTest) Generate(rand *rand.Rand, size int) reflect.Value {
t := &FindClosestTest{
Self: gen(Address{}, rand).(Address),
Target: gen(Address{}, rand).(Address),
N: rand.Intn(bucketSize),
}
for _, a := range gen([]Address{}, rand).([]Address) {
t.All = append(t.All, &testNode{addr: a})
}
return reflect.ValueOf(t)
}
func (*proxTest) Generate(rand *rand.Rand, size int) reflect.Value {
var add bool
if rand.Intn(1) == 0 {
add = true
}
var t *proxTest
if add {
t = &proxTest{
addr: gen(Address{}, rand).(Address),
add: add,
}
} else {
t = &proxTest{
index: rand.Intn(len(addresses)),
add: add,
}
}
return reflect.ValueOf(t)
}
func hasDuplicates(slice []Node) bool {
seen := make(map[Address]bool)
for _, node := range slice {
if seen[node.Addr()] {
return true
}
seen[node.Addr()] = true
}
return false
}
func contains(nodes []Node, addr Address) bool {
for _, n := range nodes {
if n.Addr() == addr {
return true
}
}
return false
}
// gen wraps quick.Value so it's easier to use.
// it generates a random value of the given value's type.
func gen(typ interface{}, rand *rand.Rand) interface{} {
v, ok := quick.Value(reflect.TypeOf(typ), rand)
if !ok {
panic(fmt.Sprintf("couldn't generate random value of type %T", typ))
}
return v.Interface()
}
| vvelikodny/go-ethereum | swarm/network/kademlia/kademlia_test.go | GO | lgpl-3.0 | 9,467 |
--Copyright (C) 2010 <SWGEmu>
--This File is part of Core3.
--This program is free software; you can redistribute
--it and/or modify it under the terms of the GNU Lesser
--General Public License as published by the Free Software
--Foundation; either version 2 of the License,
--or (at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--See the GNU Lesser General Public License for
--more details.
--You should have received a copy of the GNU Lesser General
--Public License along with this program; if not, write to
--the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--Linking Engine3 statically or dynamically with other modules
--is making a combined work based on Engine3.
--Thus, the terms and conditions of the GNU Lesser General Public License
--cover the whole combination.
--In addition, as a special exception, the copyright holders of Engine3
--give you permission to combine Engine3 program with free software
--programs or libraries that are released under the GNU LGPL and with
--code included in the standard release of Core3 under the GNU LGPL
--license (or modified versions of such code, with unchanged license).
--You may copy and distribute such a system following the terms of the
--GNU LGPL for Engine3 and the licenses of the other code concerned,
--provided that you include the source code of that other code when
--and as the GNU LGPL requires distribution of source code.
--Note that people who make modified versions of Engine3 are not obligated
--to grant this special exception for their modified versions;
--it is their choice whether to do so. The GNU Lesser General Public License
--gives permission to release a modified version without this exception;
--this exception also makes it possible to release a modified version
object_static_structure_naboo_seawall_rocks_naboo_theed_style_2 = object_static_structure_naboo_shared_seawall_rocks_naboo_theed_style_2:new {
}
ObjectTemplates:addTemplate(object_static_structure_naboo_seawall_rocks_naboo_theed_style_2, "object/static/structure/naboo/seawall_rocks_naboo_theed_style_2.iff")
| kidaa/Awakening-Core3 | bin/scripts/object/static/structure/naboo/seawall_rocks_naboo_theed_style_2.lua | Lua | lgpl-3.0 | 2,312 |
--Copyright (C) 2010 <SWGEmu>
--This File is part of Core3.
--This program is free software; you can redistribute
--it and/or modify it under the terms of the GNU Lesser
--General Public License as published by the Free Software
--Foundation; either version 2 of the License,
--or (at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--See the GNU Lesser General Public License for
--more details.
--You should have received a copy of the GNU Lesser General
--Public License along with this program; if not, write to
--the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--Linking Engine3 statically or dynamically with other modules
--is making a combined work based on Engine3.
--Thus, the terms and conditions of the GNU Lesser General Public License
--cover the whole combination.
--In addition, as a special exception, the copyright holders of Engine3
--give you permission to combine Engine3 program with free software
--programs or libraries that are released under the GNU LGPL and with
--code included in the standard release of Core3 under the GNU LGPL
--license (or modified versions of such code, with unchanged license).
--You may copy and distribute such a system following the terms of the
--GNU LGPL for Engine3 and the licenses of the other code concerned,
--provided that you include the source code of that other code when
--and as the GNU LGPL requires distribution of source code.
--Note that people who make modified versions of Engine3 are not obligated
--to grant this special exception for their modified versions;
--it is their choice whether to do so. The GNU Lesser General Public License
--gives permission to release a modified version without this exception;
--this exception also makes it possible to release a modified version
object_tangible_component_item_quest_item_variance_throttle = object_tangible_component_item_quest_item_shared_variance_throttle:new {
}
ObjectTemplates:addTemplate(object_tangible_component_item_quest_item_variance_throttle, "object/tangible/component/item/quest_item/variance_throttle.iff")
| kidaa/Awakening-Core3 | bin/scripts/object/tangible/component/item/quest_item/variance_throttle.lua | Lua | lgpl-3.0 | 2,296 |
//
// PolicyVersion.cs
//
// Author:
// Igor Zelmanovich <[email protected]>
//
// Copyright (C) 2008 Mainsoft, Inc. http://www.mainsoft.com
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
using System;
using System.Collections.Generic;
using System.Text;
namespace System.ServiceModel.Description
{
public sealed class PolicyVersion
{
static PolicyVersion _policy12 = new PolicyVersion ("http://schemas.xmlsoap.org/ws/2004/09/policy");
static PolicyVersion _policy15 = new PolicyVersion ("http://www.w3.org/ns/ws-policy");
readonly string _namespace;
private PolicyVersion (string @namespace) {
_namespace = @namespace;
}
public static PolicyVersion Default {
get { return _policy12; }
}
public static PolicyVersion Policy12 {
get { return _policy12; }
}
public static PolicyVersion Policy15 {
get { return _policy15; }
}
public string Namespace {
get { return _namespace; }
}
public override string ToString () {
return Namespace;
}
}
}
| edwinspire/VSharp | class/System.ServiceModel/System.ServiceModel.Description/PolicyVersion.cs | C# | lgpl-3.0 | 2,039 |
<?php
/*
* This file is part of the Thelia package.
* http://www.thelia.net
*
* (c) OpenStudio <[email protected]>
*
* For the full copyright and license information, please view the LICENSE
* file that was distributed with this source code.
*/
namespace Thelia\Model;
use Thelia\Model\Base\CountryAreaQuery as BaseCountryAreaQuery;
/**
* Skeleton subclass for performing query and update operations on the 'country_area' table.
*
* You should add additional methods to this class to meet the
* application requirements. This class will only be generated as
* long as it does not already exist in the output directory.
*/
class CountryAreaQuery extends BaseCountryAreaQuery
{
public static function findByCountryAndState(Country $country, State $state = null)
{
$response = null;
if (null !== $state) {
$countryAreaList = self::create()
->filterByCountryId($country->getId())
->filterByStateId($state->getId())
->find();
if (\count($countryAreaList) > 0) {
return $countryAreaList;
}
}
$countryAreaList = self::create()
->filterByCountryId($country->getId())
->filterByStateId(null)
->find()
;
return $countryAreaList;
}
}
| thelia/core | lib/Thelia/Model/CountryAreaQuery.php | PHP | lgpl-3.0 | 1,340 |
--Copyright (C) 2010 <SWGEmu>
--This File is part of Core3.
--This program is free software; you can redistribute
--it and/or modify it under the terms of the GNU Lesser
--General Public License as published by the Free Software
--Foundation; either version 2 of the License,
--or (at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--See the GNU Lesser General Public License for
--more details.
--You should have received a copy of the GNU Lesser General
--Public License along with this program; if not, write to
--the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--Linking Engine3 statically or dynamically with other modules
--is making a combined work based on Engine3.
--Thus, the terms and conditions of the GNU Lesser General Public License
--cover the whole combination.
--In addition, as a special exception, the copyright holders of Engine3
--give you permission to combine Engine3 program with free software
--programs or libraries that are released under the GNU LGPL and with
--code included in the standard release of Core3 under the GNU LGPL
--license (or modified versions of such code, with unchanged license).
--You may copy and distribute such a system following the terms of the
--GNU LGPL for Engine3 and the licenses of the other code concerned,
--provided that you include the source code of that other code when
--and as the GNU LGPL requires distribution of source code.
--Note that people who make modified versions of Engine3 are not obligated
--to grant this special exception for their modified versions;
--it is their choice whether to do so. The GNU Lesser General Public License
--gives permission to release a modified version without this exception;
--this exception also makes it possible to release a modified version
object_mobile_dressed_cobral_hooligan_bith_female_01 = object_mobile_shared_dressed_cobral_hooligan_bith_female_01:new {
}
ObjectTemplates:addTemplate(object_mobile_dressed_cobral_hooligan_bith_female_01, "object/mobile/dressed_cobral_hooligan_bith_female_01.iff")
| kidaa/Awakening-Core3 | bin/scripts/object/mobile/dressed_cobral_hooligan_bith_female_01.lua | Lua | lgpl-3.0 | 2,268 |
/*
* EncFS Java Library
* Copyright (C) 2011 Mark R. Pariente
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*/
package org.mrpdaemon.sec.encfs;
public abstract class EncFSException extends Exception {
private static final long serialVersionUID = 1L;
EncFSException(String message) {
super(message);
}
EncFSException(Throwable cause) {
super(cause);
}
}
| triplein/plsql-encfs | src/org/mrpdaemon/sec/encfs/EncFSException.java | Java | lgpl-3.0 | 842 |
<?php
/*
* This file is part of the Thelia package.
* http://www.thelia.net
*
* (c) OpenStudio <[email protected]>
*
* For the full copyright and license information, please view the LICENSE
* file that was distributed with this source code.
*/
namespace Thelia\Core\Event\Template;
use Thelia\Model\Template;
class TemplateDeleteAttributeEvent extends TemplateEvent
{
protected $attribute_id;
public function __construct(Template $template, $attribute_id)
{
parent::__construct($template);
$this->attribute_id = $attribute_id;
}
public function getAttributeId()
{
return $this->attribute_id;
}
public function setAttributeId($attribute_id)
{
$this->attribute_id = $attribute_id;
return $this;
}
}
| thelia/core | lib/Thelia/Core/Event/Template/TemplateDeleteAttributeEvent.php | PHP | lgpl-3.0 | 793 |
package Genome::VariantReporting::Reporter::FullReporter;
use strict;
use warnings;
use Genome;
use List::Util qw( min );
class Genome::VariantReporting::Reporter::FullReporter {
is => [ 'Genome::VariantReporting::Reporter::WithHeaderAndSampleNames'],
has => [
],
};
sub name {
return 'full';
}
sub requires_interpreters {
return qw(position vep info-tags variant-type min-coverage min-coverage-observed max-vaf-observed variant-callers many-samples-vaf rsid caf);
}
sub headers {
my $self = shift;
my @headers = qw/
chromosome_name
start
stop
reference
variant
variant_type
transcript_name
trv_type
trv_type_category
amino_acid_change
default_gene_name
ensembl_gene_id
inSegDup
AML_RMG
rsid
caf
max_alt_af
onTarget
MeetsMinDepthCutoff
/;
push @headers, $self->_single_vaf_headers;
push @headers, qw/
min_coverage_observed
max_normal_vaf_observed
max_tumor_vaf_observed
variant_callers
variant_caller_count
/;
push @headers, $self->_per_library_vaf_headers;
return @headers;
}
sub _single_vaf_headers {
my $self = shift;
return $self->create_sample_specific_field_names([_single_vaf_fields()], [$self->sample_names]);
}
sub _per_library_vaf_headers {
my $self = shift;
return $self->create_sample_specific_field_names([_per_library_vaf_fields()], [$self->sample_names]);
}
sub _single_vaf_fields {
return qw/
vaf
ref_count
var_count
/;
}
sub _per_library_vaf_fields {
return qw/
per_library_var_count
per_library_ref_count
per_library_vaf
/;
}
sub _header_to_info_tag_conversion {
return {
AML_RMG => 'AML_RMG',
inSegDup => 'SEG_DUP',
onTarget => 'ON_TARGET',
}
}
sub report {
my $self = shift;
my $interpretations = shift;
my %fields = $self->available_fields_dict();
for my $allele (keys %{$interpretations->{($self->requires_interpreters)[0]}}) {
for my $header ($self->headers()) {
my $interpreter = $fields{$header}->{interpreter};
my $field = $fields{$header}->{field};
if ($header eq 'inSegDup' || $header eq 'onTarget' || $header eq 'AML_RMG') {
my $info_tags = $interpretations->{$interpreter}->{$allele}->{$field};
$self->_print_info_tag(_header_to_info_tag_conversion()->{$header}, $info_tags);
}
elsif ($header eq 'variant_callers') {
my @variant_callers = @{$interpretations->{$interpreter}->{$allele}->{$field}};
$self->_output_fh->print($self->_format(join(", ", @variant_callers)) . "\t");
}
# If we don't have an interpreter that provides this field, handle it cleanly if the field is known unavailable
elsif ($self->header_is_unavailable($header)) {
$self->_output_fh->print( $self->_format() . "\t");
}
elsif ($interpreter) {
$self->_output_fh->print($self->_format($interpretations->{$interpreter}->{$allele}->{$field}) . "\t");
}
else {
# We use $header here because $field will be undefined due to it not being in an interpreter
die $self->error_message("Field (%s) is not available from any of the interpreters provided", $header);
}
}
$self->_output_fh->print("\n");
}
}
sub available_fields_dict {
my $self = shift;
my %available_fields = $self->SUPER::available_fields_dict();
for my $info_tag_field (qw/inSegDup onTarget AML_RMG/) {
$available_fields{$info_tag_field} = {
interpreter => 'info-tags',
field => 'info_tags',
};
}
$available_fields{MeetsMinDepthCutoff} = {
interpreter => 'min-coverage',
field => 'filter_status',
};
return %available_fields;
}
sub _print_info_tag {
my ($self, $info_tag, $info_tags_string) = @_;
if ($info_tags_string =~ /$info_tag/) {
$self->_output_fh->print($self->_format(1) . "\t");
}
else {
$self->_output_fh->print($self->_format(0) . "\t");
}
}
1;
| ebelter/genome | lib/perl/Genome/VariantReporting/Reporter/FullReporter.pm | Perl | lgpl-3.0 | 4,340 |
// -*- C++ -*-
/*!
* @file DataFlowComponentBase.cpp
* @brief DataFlowParticipant RT-Component base class
* @date $Date: 2007-04-13 15:44:03 $
* @author Noriaki Ando <[email protected]>
*
* Copyright (C) 2006
* Task-intelligence Research Group,
* Intelligent Systems Research Institute,
* National Institute of
* Advanced Industrial Science and Technology (AIST), Japan
* All rights reserved.
*
* $Id: DataFlowComponentBase.cpp 1339 2009-05-18 05:59:27Z n-ando $
*
*/
#include <rtm/RTC.h>
#include <rtm/DataFlowComponentBase.h>
#include <rtm/Manager.h>
#include <iostream>
namespace RTC
{
/*!
* @if jp
* @brief ¥³¥ó¥¹¥È¥é¥¯¥¿
* @else
* @brief Constructor
* @endif
*/
DataFlowComponentBase::DataFlowComponentBase(Manager* manager)
: RTObject_impl(manager)
{
// m_ref = OpenRTM::DataFlowComponent::_duplicate(this->_this());
// m_objref = RTC::RTObject::_duplicate(m_ref);
}
/*!
* @if jp
* @brief ¥Ç¥¹¥È¥é¥¯¥¿
* @else
* @brief Destructor
* @endif
*/
DataFlowComponentBase::~DataFlowComponentBase()
{
}
/*!
* @if jp
* @brief ½é´ü²½
* @else
* @brief Initialization
* @endif
*/
void DataFlowComponentBase::init()
{
}
}; // namespace RTC
| yosuke/OpenRTM-aist-portable | src/lib/rtm/DataFlowComponentBase.cpp | C++ | lgpl-3.0 | 1,275 |
/*------------------------------------------------------------------*-
Delay_T0.H (v1.00)
------------------------------------------------------------------
- See Delay_T0.C for details.
COPYRIGHT
---------
This code is from the book:
PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
[Pearson Education, 2001; ISBN: 0-201-33138-1].
This code is copyright (c) 2001 by Michael J. Pont.
See book for copyright details and other information.
-*------------------------------------------------------------------*/
// ------ Public function prototypes -------------------------------
void Hardware_Delay_T0(const tLong);
/*------------------------------------------------------------------*-
---- END OF FILE -------------------------------------------------
-*------------------------------------------------------------------*/
| hyller/CodeLibrary | Patterns_for_Time_Triggered_Emb/11/H_Delay/Delay.h | C | unlicense | 915 |
/*************************************************************************//**
* This file has been modified from the original as follows:
* - added macro #define HSE_VALUE 8000000 for the STM32F4-Discovery board
* - added macro #define STM32F40XX 1 for the STM32F4-Discovery board
* - added macro #define __FPU_PRESENT 1 for the STM32F4-Discovery board
*
* Quantum Leaps, www.state-machine.com
* 2015-03-18
****************************************************************************/
/**
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V1.2.1
* @date 19-September-2013
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F4xx devices.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_STDPERIPH_DRIVER"
* - To change few application-specific parameters such as the HSE
* crystal frequency
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripherals registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx
* @{
*/
#ifndef __STM32F4xx_H
#define __STM32F4xx_H
/**
* @attention
* The following macros are specific to the STM32F4-Discovery board.
* The macro "HSE_VALUE" overrides the define in "stm32f4xx.h" file, where it
* is set to 25MHz. You need to adjust this value if you use other olsillator
* in your project.
*/
#define HSE_VALUE 8000000
#define STM32F40XX 1
#define __FPU_PRESENT 1
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
/** @addtogroup Library_configuration_section
* @{
*/
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx)
/* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
/* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
/* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
STM32F439IG and STM32F439II Devices */
/* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
#endif
/* Old STM32F40XX definition, maintained for legacy purpose */
#ifdef STM32F40XX
#define STM32F40_41xxx
#endif /* STM32F40XX */
/* Old STM32F427X definition, maintained for legacy purpose */
#ifdef STM32F427X
#define STM32F427_437xx
#endif /* STM32F427X */
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor */
#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx)
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
#if !defined (USE_STDPERIPH_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_STDPERIPH_DRIVER */
#endif /* USE_STDPERIPH_DRIVER */
/**
* @brief In the following line adjust the value of External High Speed oscillator (HSE)
used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */
#endif /* HSE_STARTUP_TIMEOUT */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief STM32F4XX Standard Peripherals Library version number V1.2.0
*/
#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
|(__STM32F4XX_STDPERIPH_VERSION_RC))
/**
* @}
*/
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @brief STM32F4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
#if defined (STM32F40_41xxx)
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FSMC_IRQn = 48, /*!< FSMC global Interrupt */
SDIO_IRQn = 49, /*!< SDIO global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
FPU_IRQn = 81 /*!< FPU global interrupt */
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx)
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDIO_IRQn = 49, /*!< SDIO global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
UART7_IRQn = 82, /*!< UART7 global interrupt */
UART8_IRQn = 83, /*!< UART8 global interrupt */
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
#endif /* STM32F427_437xx */
#if defined (STM32F429_439xx)
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDIO_IRQn = 49, /*!< SDIO global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
ETH_IRQn = 61, /*!< Ethernet global Interrupt */
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
UART7_IRQn = 82, /*!< UART7 global interrupt */
UART8_IRQn = 83, /*!< UART8 global interrupt */
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
LTDC_IRQn = 88, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
#endif /* STM32F429_439xx */
#if defined (STM32F401xx)
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
SDIO_IRQn = 49, /*!< SDIO global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
#endif /* STM32F401xx */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32f4xx.h"
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32; /*!< Read Only */
typedef const int16_t sc16; /*!< Read Only */
typedef const int8_t sc8; /*!< Read Only */
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32; /*!< Read Only */
typedef __I int16_t vsc16; /*!< Read Only */
typedef __I int8_t vsc8; /*!< Read Only */
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32; /*!< Read Only */
typedef const uint16_t uc16; /*!< Read Only */
typedef const uint8_t uc8; /*!< Read Only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32; /*!< Read Only */
typedef __I uint16_t vuc16; /*!< Read Only */
typedef __I uint8_t vuc8; /*!< Read Only */
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/**
* @}
*/
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual
AND triple modes, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
/**
* @brief Controller Area Network TxMailBox
*/
typedef struct
{
__IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
__IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
__IO uint32_t TDLR; /*!< CAN mailbox data low register */
__IO uint32_t TDHR; /*!< CAN mailbox data high register */
} CAN_TxMailBox_TypeDef;
/**
* @brief Controller Area Network FIFOMailBox
*/
typedef struct
{
__IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
__IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
__IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
__IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
} CAN_FIFOMailBox_TypeDef;
/**
* @brief Controller Area Network FilterRegister
*/
typedef struct
{
__IO uint32_t FR1; /*!< CAN Filter bank register 1 */
__IO uint32_t FR2; /*!< CAN Filter bank register 1 */
} CAN_FilterRegister_TypeDef;
/**
* @brief Controller Area Network
*/
typedef struct
{
__IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
__IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
__IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
__IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
__IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
__IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
__IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
__IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
__IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
__IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
uint32_t RESERVED2; /*!< Reserved, 0x208 */
__IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
uint32_t RESERVED3; /*!< Reserved, 0x210 */
__IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
uint32_t RESERVED4; /*!< Reserved, 0x218 */
__IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
} CAN_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
} DCMI_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
/**
* @brief DMA2D Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
__IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
__IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
__IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
__IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
__IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
__IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
__IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
__IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
__IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
__IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
__IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
__IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
__IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
__IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
__IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
__IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
} DMA2D_TypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR;
__IO uint32_t MACFFR;
__IO uint32_t MACHTHR;
__IO uint32_t MACHTLR;
__IO uint32_t MACMIIAR;
__IO uint32_t MACMIIDR;
__IO uint32_t MACFCR;
__IO uint32_t MACVLANTR; /* 8 */
uint32_t RESERVED0[2];
__IO uint32_t MACRWUFFR; /* 11 */
__IO uint32_t MACPMTCSR;
uint32_t RESERVED1[2];
__IO uint32_t MACSR; /* 15 */
__IO uint32_t MACIMR;
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR; /* 24 */
uint32_t RESERVED2[40];
__IO uint32_t MMCCR; /* 65 */
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR; /* 69 */
uint32_t RESERVED3[14];
__IO uint32_t MMCTGFSCCR; /* 84 */
__IO uint32_t MMCTGFMSCCR;
uint32_t RESERVED4[5];
__IO uint32_t MMCTGFCR;
uint32_t RESERVED5[10];
__IO uint32_t MMCRFCECR;
__IO uint32_t MMCRFAECR;
uint32_t RESERVED6[10];
__IO uint32_t MMCRGUFCR;
uint32_t RESERVED7[334];
__IO uint32_t PTPTSCR;
__IO uint32_t PTPSSIR;
__IO uint32_t PTPTSHR;
__IO uint32_t PTPTSLR;
__IO uint32_t PTPTSHUR;
__IO uint32_t PTPTSLUR;
__IO uint32_t PTPTSAR;
__IO uint32_t PTPTTHR;
__IO uint32_t PTPTTLR;
__IO uint32_t RESERVED8;
__IO uint32_t PTPTSSR;
uint32_t RESERVED9[565];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
__IO uint32_t DMARDLAR;
__IO uint32_t DMATDLAR;
__IO uint32_t DMASR;
__IO uint32_t DMAOMR;
__IO uint32_t DMAIER;
__IO uint32_t DMAMFBOCR;
__IO uint32_t DMARSWTR;
uint32_t RESERVED10[8];
__IO uint32_t DMACHTDR;
__IO uint32_t DMACHRDR;
__IO uint32_t DMACHTBAR;
__IO uint32_t DMACHRBAR;
} ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
__IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
__IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
} FLASH_TypeDef;
#if defined (STM32F40_41xxx)
/**
* @brief Flexible Static Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FSMC_Bank1_TypeDef;
/**
* @brief Flexible Static Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FSMC_Bank1E_TypeDef;
/**
* @brief Flexible Static Memory Controller Bank2
*/
typedef struct
{
__IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
__IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
__IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
__IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
uint32_t RESERVED0; /*!< Reserved, 0x70 */
__IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
} FSMC_Bank2_TypeDef;
/**
* @brief Flexible Static Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
__IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
__IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
__IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
} FSMC_Bank3_TypeDef;
/**
* @brief Flexible Static Memory Controller Bank4
*/
typedef struct
{
__IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
__IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
__IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
__IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
__IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
} FSMC_Bank4_TypeDef;
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank2
*/
typedef struct
{
__IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
__IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
__IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
__IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
uint32_t RESERVED0; /*!< Reserved, 0x70 */
__IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
} FMC_Bank2_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
__IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
__IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
__IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief Flexible Memory Controller Bank4
*/
typedef struct
{
__IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
__IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
__IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
__IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
__IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
} FMC_Bank4_TypeDef;
/**
* @brief Flexible Memory Controller Bank5_6
*/
typedef struct
{
__IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
__IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
__IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
__IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
__IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
} FMC_Bank5_6_TypeDef;
#endif /* STM32F427_437xx || STM32F429_439xx */
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
} SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
uint16_t RESERVED9; /*!< Reserved, 0x26 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
} IWDG_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved, 0x3C */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
uint32_t RESERVED4; /*!< Reserved, 0x5C */
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
uint32_t RESERVED7; /*!< Reserved, 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
} RTC_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief SD host Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
__I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
} SPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
uint16_t RESERVED9; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED10; /*!< Reserved, 0x32 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
uint16_t RESERVED11; /*!< Reserved, 0x46 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED12; /*!< Reserved, 0x4A */
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
uint16_t RESERVED13; /*!< Reserved, 0x4E */
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*!< Reserved, 0x52 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
} USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief Crypto Processor
*/
typedef struct
{
__IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
__IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
__IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
__IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
__IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
__IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
__IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
__IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
__IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
__IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
__IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
__IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
__IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
__IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
__IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
__IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
__IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
__IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
__IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
__IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
__IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
__IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
__IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
__IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
__IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
__IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
__IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
__IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
__IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
__IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
} CRYP_TypeDef;
/**
* @brief HASH
*/
typedef struct
{
__IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
__IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
__IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
__IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
__IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
} HASH_TypeDef;
/**
* @brief HASH_DIGEST
*/
typedef struct
{
__IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
} HASH_DIGEST_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#if defined (STM32F40_41xxx)
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
#endif /* STM32F427_437xx || STM32F429_439xx */
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
/*!< APB2 peripherals */
#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
#define ETH_MAC_BASE (ETH_BASE)
#define ETH_MMC_BASE (ETH_BASE + 0x0100)
#define ETH_PTP_BASE (ETH_BASE + 0x0700)
#define ETH_DMA_BASE (ETH_BASE + 0x1000)
#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
/*!< AHB2 peripherals */
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
#if defined (STM32F40_41xxx)
/*!< FSMC Bankx registers base address */
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/*!< FMC Bankx registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
#endif /* STM32F427_437xx || STM32F429_439xx */
/* Debug MCU registers base address */
#define DBGMCU_BASE ((uint32_t )0xE0042000)
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define UART7 ((USART_TypeDef *) UART7_BASE)
#define UART8 ((USART_TypeDef *) UART8_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
#define HASH ((HASH_TypeDef *) HASH_BASE)
#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#if defined (STM32F40_41xxx)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
#endif /* STM32F427_437xx || STM32F429_439xx */
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
/******************* Bit definition for ADC_CR1 register ********************/
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
/******************* Bit definition for ADC_CR2 register ********************/
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
/****************** Bit definition for ADC_SMPR1 register *******************/
#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
/****************** Bit definition for ADC_SMPR2 register *******************/
#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
/****************** Bit definition for ADC_JOFR1 register *******************/
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
/****************** Bit definition for ADC_JOFR2 register *******************/
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
/****************** Bit definition for ADC_JOFR3 register *******************/
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
/****************** Bit definition for ADC_JOFR4 register *******************/
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
/******************* Bit definition for ADC_HTR register ********************/
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
/******************* Bit definition for ADC_LTR register ********************/
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
/******************* Bit definition for ADC_SQR2 register *******************/
#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
/******************* Bit definition for ADC_SQR3 register *******************/
#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
/******************* Bit definition for ADC_JSQR register *******************/
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
/******************* Bit definition for ADC_JDR1 register *******************/
#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
/******************* Bit definition for ADC_JDR2 register *******************/
#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
/******************* Bit definition for ADC_JDR3 register *******************/
#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
/******************* Bit definition for ADC_JDR4 register *******************/
#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
/******************* Bit definition for ADC_CSR register ********************/
#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
/******************* Bit definition for ADC_CDR register ********************/
#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
/******************************************************************************/
/* */
/* Controller Area Network */
/* */
/******************************************************************************/
/*!<CAN control and status registers */
/******************* Bit definition for CAN_MCR register ********************/
#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
/******************* Bit definition for CAN_MSR register ********************/
#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
/******************* Bit definition for CAN_TSR register ********************/
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
/******************* Bit definition for CAN_RF0R register *******************/
#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
/******************* Bit definition for CAN_RF1R register *******************/
#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
/******************** Bit definition for CAN_IER register *******************/
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
/******************** Bit definition for CAN_ESR register *******************/
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
/******************* Bit definition for CAN_BTR register ********************/
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
/*!<Mailbox registers */
/****************** Bit definition for CAN_TI0R register ********************/
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
/****************** Bit definition for CAN_TDT0R register *******************/
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
/****************** Bit definition for CAN_TDL0R register *******************/
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
/****************** Bit definition for CAN_TDH0R register *******************/
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
/******************* Bit definition for CAN_TI1R register *******************/
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT1R register ******************/
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
/******************* Bit definition for CAN_TDL1R register ******************/
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
/******************* Bit definition for CAN_TDH1R register ******************/
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
/******************* Bit definition for CAN_TI2R register *******************/
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT2R register ******************/
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
/******************* Bit definition for CAN_TDL2R register ******************/
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
/******************* Bit definition for CAN_TDH2R register ******************/
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
/******************* Bit definition for CAN_RI0R register *******************/
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT0R register ******************/
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
/******************* Bit definition for CAN_RDL0R register ******************/
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
/******************* Bit definition for CAN_RDH0R register ******************/
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
/******************* Bit definition for CAN_RI1R register *******************/
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT1R register ******************/
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
/******************* Bit definition for CAN_RDL1R register ******************/
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
/******************* Bit definition for CAN_RDH1R register ******************/
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
/******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
/******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
/****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
/******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F1R1 register *******************/
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F2R1 register *******************/
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F3R1 register *******************/
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F4R1 register *******************/
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F5R1 register *******************/
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F6R1 register *******************/
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F7R1 register *******************/
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F8R1 register *******************/
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F9R1 register *******************/
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F10R1 register ******************/
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F11R1 register ******************/
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F12R1 register ******************/
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F13R1 register ******************/
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F0R2 register *******************/
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F1R2 register *******************/
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F2R2 register *******************/
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F3R2 register *******************/
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F4R2 register *******************/
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F5R2 register *******************/
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F6R2 register *******************/
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F7R2 register *******************/
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F8R2 register *******************/
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F9R2 register *******************/
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F10R2 register ******************/
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F11R2 register ******************/
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F12R2 register ******************/
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************* Bit definition for CAN_F13R2 register ******************/
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
/******************************************************************************/
/* */
/* Crypto Processor */
/* */
/******************************************************************************/
/******************* Bits definition for CRYP_CR register ********************/
#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
/****************** Bits definition for CRYP_SR register *********************/
#define CRYP_SR_IFEM ((uint32_t)0x00000001)
#define CRYP_SR_IFNF ((uint32_t)0x00000002)
#define CRYP_SR_OFNE ((uint32_t)0x00000004)
#define CRYP_SR_OFFU ((uint32_t)0x00000008)
#define CRYP_SR_BUSY ((uint32_t)0x00000010)
/****************** Bits definition for CRYP_DMACR register ******************/
#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
/***************** Bits definition for CRYP_IMSCR register ******************/
#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
/****************** Bits definition for CRYP_RISR register *******************/
#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
/****************** Bits definition for CRYP_MISR register *******************/
#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
#define DCMI_CR_CM ((uint32_t)0x00000002)
#define DCMI_CR_CROP ((uint32_t)0x00000004)
#define DCMI_CR_JPEG ((uint32_t)0x00000008)
#define DCMI_CR_ESS ((uint32_t)0x00000010)
#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
#define DCMI_CR_CRE ((uint32_t)0x00001000)
#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
#define DCMI_SR_FNE ((uint32_t)0x00000004)
/******************** Bits definition for DCMI_RISR register ****************/
#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
/******************** Bits definition for DCMI_MISR register ****************/
#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMA_SxCR register *****************/
#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
#define DMA_SxCR_ACK ((uint32_t)0x00100000)
#define DMA_SxCR_CT ((uint32_t)0x00080000)
#define DMA_SxCR_DBM ((uint32_t)0x00040000)
#define DMA_SxCR_PL ((uint32_t)0x00030000)
#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
#define DMA_SxCR_MINC ((uint32_t)0x00000400)
#define DMA_SxCR_PINC ((uint32_t)0x00000200)
#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
#define DMA_SxCR_EN ((uint32_t)0x00000001)
/******************** Bits definition for DMA_SxCNDTR register **************/
#define DMA_SxNDT ((uint32_t)0x0000FFFF)
#define DMA_SxNDT_0 ((uint32_t)0x00000001)
#define DMA_SxNDT_1 ((uint32_t)0x00000002)
#define DMA_SxNDT_2 ((uint32_t)0x00000004)
#define DMA_SxNDT_3 ((uint32_t)0x00000008)
#define DMA_SxNDT_4 ((uint32_t)0x00000010)
#define DMA_SxNDT_5 ((uint32_t)0x00000020)
#define DMA_SxNDT_6 ((uint32_t)0x00000040)
#define DMA_SxNDT_7 ((uint32_t)0x00000080)
#define DMA_SxNDT_8 ((uint32_t)0x00000100)
#define DMA_SxNDT_9 ((uint32_t)0x00000200)
#define DMA_SxNDT_10 ((uint32_t)0x00000400)
#define DMA_SxNDT_11 ((uint32_t)0x00000800)
#define DMA_SxNDT_12 ((uint32_t)0x00001000)
#define DMA_SxNDT_13 ((uint32_t)0x00002000)
#define DMA_SxNDT_14 ((uint32_t)0x00004000)
#define DMA_SxNDT_15 ((uint32_t)0x00008000)
/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
#define DMA_SxFCR_FS ((uint32_t)0x00000038)
#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
/******************************************************************************/
/* */
/* AHB Master DMA2D Controller (DMA2D) */
/* */
/******************************************************************************/
/******************** Bit definition for DMA2D_CR register ******************/
#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
/******************** Bit definition for DMA2D_ISR register *****************/
#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_IFSR register ****************/
#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_FGMAR register ***************/
#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************** Bit definition for DMA2D_FGOR register ****************/
#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
/******************** Bit definition for DMA2D_BGMAR register ***************/
#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************** Bit definition for DMA2D_BGOR register ****************/
#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
/******************** Bit definition for DMA2D_FGPFCCR register *************/
#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
/******************** Bit definition for DMA2D_FGCOLR register **************/
#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
/******************** Bit definition for DMA2D_BGPFCCR register *************/
#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
/******************** Bit definition for DMA2D_BGCOLR register **************/
#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
/******************** Bit definition for DMA2D_FGCMAR register **************/
#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************** Bit definition for DMA2D_BGCMAR register **************/
#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************** Bit definition for DMA2D_OPFCCR register **************/
#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
/******************** Bit definition for DMA2D_OCOLR register ***************/
/*!<Mode_ARGB8888/RGB888 */
#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
/*!<Mode_RGB565 */
#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
/*!<Mode_ARGB1555 */
#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
/*!<Mode_ARGB4444 */
#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
/******************** Bit definition for DMA2D_OMAR register ****************/
#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
/******************** Bit definition for DMA2D_OOR register *****************/
#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
/******************** Bit definition for DMA2D_NLR register *****************/
#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
/******************** Bit definition for DMA2D_LWR register *****************/
#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
/******************** Bit definition for DMA2D_AMTCR register ***************/
#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP ((uint32_t)0x00000001)
#define FLASH_SR_SOP ((uint32_t)0x00000002)
#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
#define FLASH_SR_BSY ((uint32_t)0x00010000)
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG ((uint32_t)0x00000001)
#define FLASH_CR_SER ((uint32_t)0x00000002)
#define FLASH_CR_MER ((uint32_t)0x00000004)
#define FLASH_CR_MER1 FLASH_CR_MER
#define FLASH_CR_SNB ((uint32_t)0x000000F8)
#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
#define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
#define FLASH_CR_MER2 ((uint32_t)0x00008000)
#define FLASH_CR_STRT ((uint32_t)0x00010000)
#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
#define FLASH_CR_LOCK ((uint32_t)0x80000000)
/******************* Bits definition for FLASH_OPTCR register ***************/
#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
/****************** Bits definition for FLASH_OPTCR1 register ***************/
#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
#if defined (STM32F40_41xxx)
/******************************************************************************/
/* */
/* Flexible Static Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FSMC_BCR1 register *******************/
#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BCR2 register *******************/
#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BCR3 register *******************/
#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BCR4 register *******************/
#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FSMC_BTR1 register ******************/
#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_BTR2 register *******************/
#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/******************* Bit definition for FSMC_BTR3 register *******************/
#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_BTR4 register *******************/
#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_BWTR1 register ******************/
#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_BWTR2 register ******************/
#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_BWTR3 register ******************/
#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_BWTR4 register ******************/
#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FSMC_PCR2 register *******************/
#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
/****************** Bit definition for FSMC_PCR3 register *******************/
#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
/****************** Bit definition for FSMC_PCR4 register *******************/
#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
/******************* Bit definition for FSMC_SR2 register *******************/
#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/******************* Bit definition for FSMC_SR3 register *******************/
#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/******************* Bit definition for FSMC_SR4 register *******************/
#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/****************** Bit definition for FSMC_PMEM2 register ******************/
#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_PMEM3 register ******************/
#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_PMEM4 register ******************/
#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_PATT2 register ******************/
#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_PATT3 register ******************/
#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_PATT4 register ******************/
#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_PIO4 register *******************/
#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FSMC_ECCR2 register ******************/
#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
/****************** Bit definition for FSMC_ECCR3 register ******************/
#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
/****************** Bit definition for FMC_BCR2 register *******************/
#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FMC_BCR3 register *******************/
#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FMC_BCR4 register *******************/
#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
/****************** Bit definition for FMC_BTR1 register ******************/
#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_BTR2 register *******************/
#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/******************* Bit definition for FMC_BTR3 register *******************/
#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_BTR4 register *******************/
#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_BWTR1 register ******************/
#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_BWTR2 register ******************/
#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_BWTR3 register ******************/
#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_BWTR4 register ******************/
#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
/****************** Bit definition for FMC_PCR2 register *******************/
#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
/****************** Bit definition for FMC_PCR3 register *******************/
#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
/****************** Bit definition for FMC_PCR4 register *******************/
#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
/******************* Bit definition for FMC_SR2 register *******************/
#define FMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/******************* Bit definition for FMC_SR3 register *******************/
#define FMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/******************* Bit definition for FMC_SR4 register *******************/
#define FMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
#define FMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
#define FMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
#define FMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
#define FMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
/****************** Bit definition for FMC_PMEM2 register ******************/
#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_PMEM3 register ******************/
#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_PMEM4 register ******************/
#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_PATT2 register ******************/
#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_PATT3 register ******************/
#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_PATT4 register ******************/
#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_PIO4 register *******************/
#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
/****************** Bit definition for FMC_ECCR2 register ******************/
#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
/****************** Bit definition for FMC_ECCR3 register ******************/
#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
/****************** Bit definition for FMC_SDCR1 register ******************/
#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
/****************** Bit definition for FMC_SDCR2 register ******************/
#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
/****************** Bit definition for FMC_SDTR1 register ******************/
#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
/****************** Bit definition for FMC_SDTR2 register ******************/
#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
/****************** Bit definition for FMC_SDCMR register ******************/
#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
/****************** Bit definition for FMC_SDRTR register ******************/
#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
#endif /* STM32F427_437xx || STM32F429_439xx */
/******************************************************************************/
/* */
/* General Purpose I/O */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/******************************************************************************/
/* */
/* HASH */
/* */
/******************************************************************************/
/****************** Bits definition for HASH_CR register ********************/
#define HASH_CR_INIT ((uint32_t)0x00000004)
#define HASH_CR_DMAE ((uint32_t)0x00000008)
#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
#define HASH_CR_MODE ((uint32_t)0x00000040)
#define HASH_CR_ALGO ((uint32_t)0x00040080)
#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
#define HASH_CR_NBW ((uint32_t)0x00000F00)
#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
#define HASH_CR_DINNE ((uint32_t)0x00001000)
#define HASH_CR_MDMAT ((uint32_t)0x00002000)
#define HASH_CR_LKEY ((uint32_t)0x00010000)
/****************** Bits definition for HASH_STR register *******************/
#define HASH_STR_NBW ((uint32_t)0x0000001F)
#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
#define HASH_STR_DCAL ((uint32_t)0x00000100)
/****************** Bits definition for HASH_IMR register *******************/
#define HASH_IMR_DINIM ((uint32_t)0x00000001)
#define HASH_IMR_DCIM ((uint32_t)0x00000002)
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS ((uint32_t)0x00000001)
#define HASH_SR_DCIS ((uint32_t)0x00000002)
#define HASH_SR_DMAS ((uint32_t)0x00000004)
#define HASH_SR_BUSY ((uint32_t)0x00000008)
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register ********************/
#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
/******************* Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
/******************* Bit definition for I2C_OAR2 register *******************/
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
/******************** Bit definition for I2C_DR register ********************/
#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
/******************* Bit definition for I2C_SR2 register ********************/
#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
/******************* Bit definition for I2C_CCR register ********************/
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
/****************** Bit definition for I2C_TRISE register *******************/
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
/****************** Bit definition for I2C_FLTR register *******************/
#define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */
#define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
/*!< PVD level configuration */
#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
#define PWR_CR_LPUDS ((uint32_t)0x00000400) /*!< Low-Power Regulator in Stop under-drive mode */
#define PWR_CR_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in Stop under-drive mode */
#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
#define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
#define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
#define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
#define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
/* Legacy define */
#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION ((uint32_t)0x00000001)
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
#define RCC_CR_HSEON ((uint32_t)0x00010000)
#define RCC_CR_HSERDY ((uint32_t)0x00020000)
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define RCC_CR_CSSON ((uint32_t)0x00080000)
#define RCC_CR_PLLON ((uint32_t)0x01000000)
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
/*!< RTCPRE configuration */
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
/*!< MCO1 configuration */
#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
/******************** Bit definition for RCC_CIR register *******************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
#define RCC_CIR_CSSC ((uint32_t)0x00800000)
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
/* maintained for legacy purpose */
#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3RSTR register **************/
#if defined(STM32F40_41xxx)
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx */
/******************** Bit definition for RCC_APB1RSTR register **************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
/* Old SPI1RST bit definition, maintained for legacy purpose */
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3ENR register ***************/
#if defined(STM32F40_41xxx)
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx */
/******************** Bit definition for RCC_APB1ENR register ***************/
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
/******************** Bit definition for RCC_AHB1LPENR register *************/
#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
/******************** Bit definition for RCC_AHB2LPENR register *************/
#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3LPENR register *************/
#if defined(STM32F40_41xxx)
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx */
/******************** Bit definition for RCC_APB1LPENR register *************/
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
/******************** Bit definition for RCC_APB2LPENR register *************/
#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001)
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define RCC_CSR_RMVF ((uint32_t)0x01000000)
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
/******************** Bit definition for RCC_SSCGR register *****************/
#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
/******************** Bit definition for RCC_PLLI2SCFGR register ************/
#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
/******************** Bit definition for RCC_PLLSAICFGR register ************/
#define RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0)
#define RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000)
#define RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000)
/******************** Bit definition for RCC_DCKCFGR register ***************/
#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN ((uint32_t)0x00000004)
#define RNG_CR_IE ((uint32_t)0x00000008)
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY ((uint32_t)0x00000001)
#define RNG_SR_CECS ((uint32_t)0x00000002)
#define RNG_SR_SECS ((uint32_t)0x00000004)
#define RNG_SR_CEIS ((uint32_t)0x00000020)
#define RNG_SR_SEIS ((uint32_t)0x00000040)
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM ((uint32_t)0x00400000)
#define RTC_TR_HT ((uint32_t)0x00300000)
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
#define RTC_TR_HU ((uint32_t)0x000F0000)
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
#define RTC_TR_MNT ((uint32_t)0x00007000)
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TR_MNU ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TR_ST ((uint32_t)0x00000070)
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
#define RTC_TR_SU ((uint32_t)0x0000000F)
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
#define RTC_TR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT ((uint32_t)0x00F00000)
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
#define RTC_DR_YU ((uint32_t)0x000F0000)
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
#define RTC_DR_WDU ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define RTC_DR_MT ((uint32_t)0x00001000)
#define RTC_DR_MU ((uint32_t)0x00000F00)
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
#define RTC_DR_DT ((uint32_t)0x00000030)
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
#define RTC_DR_DU ((uint32_t)0x0000000F)
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
#define RTC_DR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_COE ((uint32_t)0x00800000)
#define RTC_CR_OSEL ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define RTC_CR_POL ((uint32_t)0x00100000)
#define RTC_CR_COSEL ((uint32_t)0x00080000)
#define RTC_CR_BCK ((uint32_t)0x00040000)
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_WUTIE ((uint32_t)0x00004000)
#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
#define RTC_CR_ALRBE ((uint32_t)0x00000200)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_DCE ((uint32_t)0x00000080)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_WUTF ((uint32_t)0x00000400)
#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
/******************** Bits definition for RTC_CALIBR register ***************/
#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY ((uint32_t)0x000000FF)
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM ((uint32_t)0x00400000)
#define RTC_TSTR_HT ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TSTR_ST ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define RTC_TSDR_MT ((uint32_t)0x00001000)
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define RTC_TSDR_DT ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
/******************** Bits definition for RTC_CAL register *****************/
#define RTC_CALR_CALP ((uint32_t)0x00008000)
#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
#define RTC_CALR_CALM ((uint32_t)0x000001FF)
#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
/******************** Bits definition for RTC_TAFCR register ****************/
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_ALRMBSSR register *************/
#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP1R register ****************/
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP2R register ****************/
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP3R register ****************/
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP5R register ****************/
#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP6R register ****************/
#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP7R register ****************/
#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP8R register ****************/
#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP9R register ****************/
#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP10R register ***************/
#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP11R register ***************/
#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP12R register ***************/
#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP13R register ***************/
#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP14R register ***************/
#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP15R register ***************/
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP16R register ***************/
#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP17R register ***************/
#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP18R register ***************/
#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP19R register ***************/
#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
/******************************************************************************/
/* */
/* SD host Interface */
/* */
/******************************************************************************/
/****************** Bit definition for SDIO_POWER register ******************/
#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
/****************** Bit definition for SDIO_CLKCR register ******************/
#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
/******************* Bit definition for SDIO_ARG register *******************/
#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
/******************* Bit definition for SDIO_CMD register *******************/
#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
/***************** Bit definition for SDIO_RESPCMD register *****************/
#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
/****************** Bit definition for SDIO_RESP0 register ******************/
#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
/****************** Bit definition for SDIO_RESP1 register ******************/
#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
/****************** Bit definition for SDIO_RESP2 register ******************/
#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
/****************** Bit definition for SDIO_RESP3 register ******************/
#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
/****************** Bit definition for SDIO_RESP4 register ******************/
#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
/****************** Bit definition for SDIO_DTIMER register *****************/
#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
/****************** Bit definition for SDIO_DLEN register *******************/
#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
/****************** Bit definition for SDIO_DCTRL register ******************/
#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
/****************** Bit definition for SDIO_DCOUNT register *****************/
#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
/****************** Bit definition for SDIO_STA register ********************/
#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
/******************* Bit definition for SDIO_ICR register *******************/
#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
/****************** Bit definition for SDIO_MASK register *******************/
#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
/***************** Bit definition for SDIO_FIFOCNT register *****************/
#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
/****************** Bit definition for SDIO_FIFO register *******************/
#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
/******************************************************************************/
/* */
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) /*!<PJ[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) /*!<PK[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) /*!<PJ[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) /*!<PK[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) /*!<PJ[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) /*!<PK[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) /*!<PJ[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) /*!<PK[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) /*!<PJ[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) /*!<PK[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) /*!<PJ[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) /*!<PK[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) /*!<PJ[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) /*!<PK[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) /*!<PJ[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) /*!<PK[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) /*!<PJ[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) /*!<PJ[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) /*!<PJ[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) /*!<PJ[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) /*!<PI[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) /*!<PJ[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) /*!<PI[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) /*!<PJ[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) /*!<PI[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) /*!<PJ[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) /*!<PI[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) /*!<PJ[15] pin */
/****************** Bit definition for SYSCFG_CMPCR register ****************/
#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter */
/* */
/******************************************************************************/
/******************* Bit definition for USART_SR register *******************/
#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
/******************* Bit definition for USART_DR register *******************/
#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
/* DBG */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
/******************** Bit definition for DBGMCU_APB1_FZ register ************/
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
/* Old IWDGSTOP bit definition, maintained for legacy purpose */
#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
/******************** Bit definition for DBGMCU_APB1_FZ register ************/
#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
/******************************************************************************/
/* */
/* Ethernet MAC Registers bits definitions */
/* */
/******************************************************************************/
/* Bit definition for Ethernet MAC Control Register register */
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
/* Bit definition for Ethernet MAC Frame Filter Register */
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
/* Bit definition for Ethernet MAC MII Address Register */
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
/* Bit definition for Ethernet MAC MII Data Register */
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
/* Bit definition for Ethernet MAC Flow Control Register */
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
RSVD - Filter1 Command - RSVD - Filter0 Command
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
/* Bit definition for Ethernet MAC PMT Control and Status Register */
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
/* Bit definition for Ethernet MAC Status Register */
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
/* Bit definition for Ethernet MAC Interrupt Mask Register */
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
/* Bit definition for Ethernet MAC Address0 High Register */
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
/* Bit definition for Ethernet MAC Address0 Low Register */
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
/* Bit definition for Ethernet MAC Address1 High Register */
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
/* Bit definition for Ethernet MAC Address1 Low Register */
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
/* Bit definition for Ethernet MAC Address2 High Register */
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
/* Bit definition for Ethernet MAC Address2 Low Register */
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
/* Bit definition for Ethernet MAC Address3 High Register */
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
/* Bit definition for Ethernet MAC Address3 Low Register */
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
/******************************************************************************/
/* Ethernet MMC Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet MMC Contol Register */
#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
/* Bit definition for Ethernet MMC Receive Interrupt Register */
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Register */
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
/******************************************************************************/
/* Ethernet PTP Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
/* Bit definition for Ethernet PTP Sub-Second Increment Register */
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
/* Bit definition for Ethernet PTP Time Stamp High Register */
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
/* Bit definition for Ethernet PTP Time Stamp Low Register */
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
/* Bit definition for Ethernet PTP Time Stamp High Update Register */
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
/* Bit definition for Ethernet PTP Time Stamp Addend Register */
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
/* Bit definition for Ethernet PTP Target Time High Register */
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
/* Bit definition for Ethernet PTP Target Time Low Register */
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
/* Bit definition for Ethernet PTP Time Stamp Status Register */
#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
/******************************************************************************/
/* Ethernet DMA Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet DMA Bus Mode Register */
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
/* Bit definition for Ethernet DMA Receive Poll Demand Register */
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
/* Bit definition for Ethernet DMA Status Register */
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
/* combination with EBS[2:0] for GetFlagStatus function */
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
/* Bit definition for Ethernet DMA Operation Mode Register */
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
/* Bit definition for Ethernet DMA Interrupt Enable Register */
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
/**
*
*/
/**
* @}
*/
#ifdef USE_STDPERIPH_DRIVER
#include "stm32f4xx_conf.h"
#endif /* USE_STDPERIPH_DRIVER */
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F4xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| hyller/GladiatorCots | QP/v5.4.2/qpn/3rd_party/stm32f4-discovery/stm32f4xx.h | C | unlicense | 693,874 |
package thaumcraft.api.casters;
public interface IFocusElement {
public String getKey();
public String getResearch();
public EnumUnitType getType();
enum EnumUnitType {
EFFECT, MEDIUM, MOD, PACKAGE;
}
}
| HenryLoenwind/EnderIO | enderio-base/src/api/java/thaumcraft/api/casters/IFocusElement.java | Java | unlicense | 226 |
/*
EmbeddedGUI Library version 0.6.2
Copyright (C) 2011 WangChao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation ,either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
BufferDriver.h
*/
#include "EGUIMacro.h"
#ifdef WIN32_SIMULATE
#ifdef EG_SINGLE_COLOR
extern unsigned char EG_Sim_Buffer[EG_SUB_ROW][EG_COLUMN];
// set the pixel, PixelRow and PixelColumn are pixel index.
void EG_LCDSetPixel(unsigned int PixelRow,unsigned int PixelColumn);
// clear the pixel, PixelRow and PixelColumn are pixel index.
void EG_LCDClearPixel(unsigned int PixelRow,unsigned int PixelColumn);
// get the pixel, PixelRow and PixelColumn are pixel index.
// if pixel is 1,it will return non-zero value.
unsigned char EG_LCDGetPixel(unsigned int PixelRow,unsigned int PixelColumn);
// set a horizonal byte, PixelRow and PixelColumn are pixel index.
// example:
// _|_Pixel Position
// |XXXXXXXX <- val
// 01011111 if val=0x5F
void EG_LCDSetByte(unsigned int PixelRow,unsigned int PixelColumn,unsigned char val);
// clear the EG_LCD_Buffer.
void EG_LCDClearBuffer();
#else //EG_RGB_COLOR
#include "EComponent.h"
extern EColor EG_Sim_Buffer[EG_ROW][EG_COLUMN];
// clear the EG_LCD_Buffer.
void EG_LCDClearBuffer();
#endif //EG_RGB_COLOR
#endif //WIN32_SIMULATE
| hyller/CodeLibrary | EmbeddedGUI_0.6.2/0.6.2/example/mfc/EmbeddedGUI example/EmbeddedGUI/BufferDriver.h | C | unlicense | 1,940 |
//*****************************************************************************
//
// adc.c - Driver for the ADC.
//
// Copyright (c) 2005-2015 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.1.71 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup adc_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_adc.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_sysctl.h"
#include "driverlib/adc.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// These defines are used by the ADC driver to simplify access to the ADC
// sequencer's registers.
//
//*****************************************************************************
#define ADC_SEQ (ADC_O_SSMUX0)
#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0)
#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)
#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)
#define ADC_SSTSH (ADC_O_SSTSH0 - ADC_O_SSMUX0)
//*****************************************************************************
//
// The currently configured software oversampling factor for each of the ADC
// sequencers.
//
//*****************************************************************************
static uint8_t g_pui8OversampleFactor[3];
//*****************************************************************************
//
//! Returns the interrupt number for a given ADC base address and sequence
//! number.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function returns the interrupt number for the ADC module and sequence
//! number provided in the \e ui32Base and \e ui32SequenceNum parameters.
//!
//! \return Returns the ADC sequence interrupt number or 0 if the interrupt
//! does not exist.
//
//*****************************************************************************
static uint_fast8_t
_ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
uint_fast8_t ui8Int;
//
// Determine the interrupt to register based on the sequence number.
//
if(CLASS_IS_TM4C123)
{
ui8Int = ((ui32Base == ADC0_BASE) ?
(INT_ADC0SS0_TM4C123 + ui32SequenceNum) :
(INT_ADC1SS0_TM4C123 + ui32SequenceNum));
}
else if(CLASS_IS_TM4C129)
{
ui8Int = ((ui32Base == ADC0_BASE) ?
(INT_ADC0SS0_TM4C129 + ui32SequenceNum) :
(INT_ADC1SS0_TM4C129 + ui32SequenceNum));
}
else
{
ui8Int = 0;
}
return(ui8Int);
}
//*****************************************************************************
//
//! Registers an interrupt handler for an ADC interrupt.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param pfnHandler is a pointer to the function to be called when the
//! ADC sample sequence interrupt occurs.
//!
//! This function sets the handler to be called when a sample sequence
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; the sequence interrupt must be enabled with
//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the
//! interrupt source via ADCIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
void (*pfnHandler)(void))
{
uint_fast8_t ui8Int;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Determine the interrupt to register based on the sequence number.
//
ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum);
ASSERT(ui8Int != 0);
//
// Register the interrupt handler.
//
IntRegister(ui8Int, pfnHandler);
//
// Enable the timer interrupt.
//
IntEnable(ui8Int);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for an ADC interrupt.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function unregisters the interrupt handler. This function disables
//! the global interrupt in the interrupt controller; the sequence interrupt
//! must be disabled via ADCIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
uint_fast8_t ui8Int;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Determine the interrupt to unregister based on the sequence number.
//
ui8Int = _ADCIntNumberGet(ui32Base, ui32SequenceNum);
ASSERT(ui8Int != 0);
//
// Disable the interrupt.
//
IntDisable(ui8Int);
//
// Unregister the interrupt handler.
//
IntUnregister(ui8Int);
}
//*****************************************************************************
//
//! Disables a sample sequence interrupt.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function disables the requested sample sequence interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Disable this sample sequence interrupt.
//
HWREG(ui32Base + ADC_O_IM) &= ~(1 << ui32SequenceNum);
}
//*****************************************************************************
//
//! Enables a sample sequence interrupt.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function enables the requested sample sequence interrupt. Any
//! outstanding interrupts are cleared before enabling the sample sequence
//! interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Clear any outstanding interrupts on this sample sequence.
//
HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum;
//
// Enable this sample sequence interrupt.
//
HWREG(ui32Base + ADC_O_IM) |= 1 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This function returns the interrupt status for the specified sample
//! sequence. Either the raw interrupt status or the status of interrupts that
//! are allowed to reflect to the processor can be returned.
//!
//! \return The current raw or masked interrupt status.
//
//*****************************************************************************
uint32_t
ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, bool bMasked)
{
uint32_t ui32Temp;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
ui32Temp = HWREG(ui32Base + ADC_O_ISC) & (0x10001 << ui32SequenceNum);
}
else
{
ui32Temp = (HWREG(ui32Base + ADC_O_RIS) &
(0x10000 | (1 << ui32SequenceNum)));
//
// If the digital comparator status bit is set, reflect it to the
// appropriate sequence bit.
//
if(ui32Temp & 0x10000)
{
ui32Temp |= 0xF0000;
ui32Temp &= ~(0x10000 << ui32SequenceNum);
}
}
//
// Return the interrupt status
//
return(ui32Temp);
}
//*****************************************************************************
//
//! Clears sample sequence interrupt source.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! The specified sample sequence interrupt is cleared, so that it no longer
//! asserts. This function must be called in the interrupt handler to keep
//! the interrupt from being triggered again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Clear the interrupt.
//
HWREG(ui32Base + ADC_O_ISC) = 1 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Enables a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! Allows the specified sample sequence to be captured when its trigger is
//! detected. A sample sequence must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Enable the specified sequence.
//
HWREG(ui32Base + ADC_O_ACTSS) |= 1 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Disables a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! Prevents the specified sample sequence from being captured when its trigger
//! is detected. A sample sequence must be disabled before it is configured.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Disable the specified sequences.
//
HWREG(ui32Base + ADC_O_ACTSS) &= ~(1 << ui32SequenceNum);
}
//*****************************************************************************
//
//! Configures the trigger source and priority of a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param ui32Trigger is the trigger source that initiates the sample
//! sequence; must be one of the \b ADC_TRIGGER_* values.
//! \param ui32Priority is the relative priority of the sample sequence with
//! respect to the other sample sequences.
//!
//! This function configures the initiation criteria for a sample sequence.
//! Valid sample sequencers range from zero to three; sequencer zero captures
//! up to eight samples, sequencers one and two capture up to four samples,
//! and sequencer three captures a single sample. The trigger condition and
//! priority (with respect to other sample sequencer execution) are set.
//!
//! The \e ui32Trigger parameter can take on the following values:
//!
//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
//! ADCProcessorTrigger() function.
//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
//! B4 pin. Note that some microcontrollers can
//! select from any GPIO using the
//! GPIOADCTriggerEnable() function.
//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
//! TimerControlTrigger().
//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator;
//! configured with PWMGenIntTrigEnable().
//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
//! sample sequence to capture repeatedly (so long as
//! there is not a higher priority source active).
//!
//! When \b ADC_TRIGGER_PWM0, \b ADC_TRIGGER_PWM1, \b ADC_TRIGGER_PWM2 or
//! \b ADC_TRIGGER_PWM3 is specified, one of the following should be ORed into
//! \e ui32Trigger to select the PWM module from which the triggers will be
//! routed for this sequence:
//!
//! - \b ADC_TRIGGER_PWM_MOD0 - Selects PWM module 0 as the source of the
//! PWM0 to PWM3 triggers for this sequence.
//! - \b ADC_TRIGGER_PWM_MOD1 - Selects PWM module 1 as the source of the
//! PWM0 to PWM3 triggers for this sequence.
//!
//! Note that not all trigger sources are available on all Tiva family
//! members; consult the data sheet for the device in question to determine the
//! availability of triggers.
//!
//! The \e ui32Priority parameter is a value between 0 and 3, where 0
//! represents the highest priority and 3 the lowest. Note that when
//! programming the priority among a set of sample sequences, each must have
//! unique priority; it is up to the caller to guarantee the uniqueness of the
//! priorities.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Trigger, uint32_t ui32Priority)
{
//
// Check the arugments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
ASSERT(((ui32Trigger & 0xF) == ADC_TRIGGER_PROCESSOR) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_COMP0) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_COMP1) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_COMP2) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_EXTERNAL) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_TIMER) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_PWM0) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_PWM1) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_PWM2) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_PWM3) ||
((ui32Trigger & 0xF) == ADC_TRIGGER_ALWAYS) ||
((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD0) ||
((ui32Trigger & 0x30) == ADC_TRIGGER_PWM_MOD1));
ASSERT(ui32Priority < 4);
//
// Compute the shift for the bits that control this sample sequence.
//
ui32SequenceNum *= 4;
//
// Set the trigger event for this sample sequence.
//
HWREG(ui32Base + ADC_O_EMUX) = ((HWREG(ui32Base + ADC_O_EMUX) &
~(0xf << ui32SequenceNum)) |
((ui32Trigger & 0xf) << ui32SequenceNum));
//
// Set the priority for this sample sequence.
//
HWREG(ui32Base + ADC_O_SSPRI) = ((HWREG(ui32Base + ADC_O_SSPRI) &
~(0xf << ui32SequenceNum)) |
((ui32Priority & 0x3) <<
ui32SequenceNum));
//
// Set the source PWM module for this sequence's PWM triggers.
//
ui32SequenceNum *= 2;
HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) &
~(0x30 << ui32SequenceNum)) |
((ui32Trigger & 0x30) <<
ui32SequenceNum));
}
//*****************************************************************************
//
//! Configure a step of the sample sequencer.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param ui32Step is the step to be configured.
//! \param ui32Config is the configuration of this step; must be a logical OR
//! of \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of
//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7).
//!
//! This function configures the ADC for one step of a sample sequence. The
//! ADC can be configured for single-ended or differential operation (the
//! \b ADC_CTL_D bit selects differential operation when set), the channel to
//! be sampled can be chosen (the \b ADC_CTL_CH0 through \b ADC_CTL_CH23
//! values), and the internal temperature sensor can be selected (the
//! \b ADC_CTL_TS bit). Additionally, this step can be defined as the last in
//! the sequence (the \b ADC_CTL_END bit) and it can be configured to cause an
//! interrupt when the step is complete (the \b ADC_CTL_IE bit). If the
//! digital comparators are present on the device, this step may also be
//! configured to send the ADC sample to the selected comparator using
//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration is used by the
//! ADC at the appropriate time when the trigger for this sequence occurs.
//!
//! \note If the Digital Comparator is present and enabled using the
//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT
//! written into the ADC sequence data FIFO.
//!
//! The \e ui32Step parameter determines the order in which the samples are
//! captured by the ADC when the trigger occurs. It can range from zero to
//! seven for the first sample sequencer, from zero to three for the second and
//! third sample sequencer, and can only be zero for the fourth sample
//! sequencer.
//!
//! Differential mode only works with adjacent channel pairs (for example, 0
//! and 1). The channel select must be the number of the channel pair to
//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
//! and 3) or undefined results are returned by the ADC. Additionally, if
//! differential mode is selected when the temperature sensor is being sampled,
//! undefined results are returned by the ADC.
//!
//! It is the responsibility of the caller to ensure that a valid configuration
//! is specified; this function does not check the validity of the specified
//! configuration.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Step, uint32_t ui32Config)
{
uint32_t ui32Temp;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
ASSERT(((ui32SequenceNum == 0) && (ui32Step < 8)) ||
((ui32SequenceNum == 1) && (ui32Step < 4)) ||
((ui32SequenceNum == 2) && (ui32Step < 4)) ||
((ui32SequenceNum == 3) && (ui32Step < 1)));
//
// Get the offset of the sequence to be configured.
//
ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
//
// Compute the shift for the bits that control this step.
//
ui32Step *= 4;
//
// Set the analog mux value for this step.
//
HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) &
~(0x0000000f << ui32Step)) |
((ui32Config & 0x0f) << ui32Step));
//
// Set the upper bits of the analog mux value for this step.
//
HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) &
~(0x0000000f << ui32Step)) |
(((ui32Config & 0xf00) >> 8) << ui32Step));
//
// Set the control value for this step.
//
HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) &
~(0x0000000f << ui32Step)) |
(((ui32Config & 0xf0) >> 4) << ui32Step));
//
// Set the sample and hold time for this step. This is not available on
// all devices, however on devices that do not support this feature these
// reserved bits are ignored on write access.
//
HWREG(ui32Base + ADC_SSTSH) = ((HWREG(ui32Base + ADC_SSTSH) &
~(0x0000000f << ui32Step)) |
(((ui32Config & 0xf00000) >> 20) << ui32Step));
//
// Enable digital comparator if specified in the ui32Config bit-fields.
//
if(ui32Config & 0x000F0000)
{
//
// Program the comparator for the specified step.
//
ui32Temp = HWREG(ui32Base + ADC_SSDC);
ui32Temp &= ~(0xF << ui32Step);
ui32Temp |= (((ui32Config & 0x00070000) >> 16) << ui32Step);
HWREG(ui32Base + ADC_SSDC) = ui32Temp;
//
// Enable the comparator.
//
HWREG(ui32Base + ADC_SSOP) |= (1 << ui32Step);
}
//
// Disable digital comparator if not specified.
//
else
{
HWREG(ui32Base + ADC_SSOP) &= ~(1 << ui32Step);
}
}
//*****************************************************************************
//
//! Determines if a sample sequence overflow occurred.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function determines if a sample sequence overflow has occurred.
//! Overflow happens if the captured samples are not read from the FIFO before
//! the next trigger occurs.
//!
//! \return Returns zero if there was not an overflow, and non-zero if there
//! was.
//
//*****************************************************************************
int32_t
ADCSequenceOverflow(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Determine if there was an overflow on this sequence.
//
return(HWREG(ui32Base + ADC_O_OSTAT) & (1 << ui32SequenceNum));
}
//*****************************************************************************
//
//! Clears the overflow condition on a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function clears an overflow condition on one of the sample sequences.
//! The overflow condition must be cleared in order to detect a subsequent
//! overflow condition (it otherwise causes no harm).
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceOverflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Clear the overflow condition for this sequence.
//
HWREG(ui32Base + ADC_O_OSTAT) = 1 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Determines if a sample sequence underflow occurred.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function determines if a sample sequence underflow has occurred.
//! Underflow happens if too many samples are read from the FIFO.
//!
//! \return Returns zero if there was not an underflow, and non-zero if there
//! was.
//
//*****************************************************************************
int32_t
ADCSequenceUnderflow(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Determine if there was an underflow on this sequence.
//
return(HWREG(ui32Base + ADC_O_USTAT) & (1 << ui32SequenceNum));
}
//*****************************************************************************
//
//! Clears the underflow condition on a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function clears an underflow condition on one of the sample
//! sequencers. The underflow condition must be cleared in order to detect a
//! subsequent underflow condition (it otherwise causes no harm).
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceUnderflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Clear the underflow condition for this sequence.
//
HWREG(ui32Base + ADC_O_USTAT) = 1 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Gets the captured data for a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param pui32Buffer is the address where the data is stored.
//!
//! This function copies data from the specified sample sequencer output FIFO
//! to a memory resident buffer. The number of samples available in the
//! hardware FIFO are copied into the buffer, which is assumed to be large
//! enough to hold that many samples. This function only returns the samples
//! that are presently available, which may not be the entire sample sequence
//! if it is in the process of being executed.
//!
//! \return Returns the number of samples copied to the buffer.
//
//*****************************************************************************
int32_t
ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t *pui32Buffer)
{
uint32_t ui32Count;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Get the offset of the sequence to be read.
//
ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
//
// Read samples from the FIFO until it is empty.
//
ui32Count = 0;
while(!(HWREG(ui32Base + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) &&
(ui32Count < 8))
{
//
// Read the FIFO and copy it to the destination.
//
*pui32Buffer++ = HWREG(ui32Base + ADC_SSFIFO);
//
// Increment the count of samples read.
//
ui32Count++;
}
//
// Return the number of samples read.
//
return(ui32Count);
}
//*****************************************************************************
//
//! Causes a processor trigger for a sample sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number, with
//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it.
//!
//! This function triggers a processor-initiated sample sequence if the sample
//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If
//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the
//! processor-initiated trigger is delayed until a later processor-initiated
//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL,
//! allowing multiple ADCs to start from a processor-initiated trigger in a
//! synchronous manner.
//!
//! \return None.
//
//*****************************************************************************
void
ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Generate a processor trigger for this sample sequence.
//
HWREG(ui32Base + ADC_O_PSSI) |= ((ui32SequenceNum & 0xffff0000) |
(1 << (ui32SequenceNum & 0xf)));
}
//*****************************************************************************
//
//! Configures the software oversampling factor of the ADC.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param ui32Factor is the number of samples to be averaged.
//!
//! This function configures the software oversampling for the ADC, which can
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input.
//! Three different oversampling rates are supported; 2x, 4x, and 8x.
//!
//! Oversampling is only supported on the sample sequencers that are more than
//! one sample in depth (that is, the fourth sample sequencer is not
//! supported). Oversampling by 2x (for example) divides the depth of the
//! sample sequencer by two; so 2x oversampling on the first sample sequencer
//! can only provide four samples per trigger. This also means that 8x
//! oversampling is only available on the first sample sequencer.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Factor)
{
uint32_t ui32Value;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 3);
ASSERT(((ui32Factor == 2) || (ui32Factor == 4) || (ui32Factor == 8)) &&
((ui32SequenceNum == 0) || (ui32Factor != 8)));
//
// Convert the oversampling factor to a shift factor.
//
for(ui32Value = 0, ui32Factor >>= 1; ui32Factor;
ui32Value++, ui32Factor >>= 1)
{
}
//
// Save the shift factor.
//
g_pui8OversampleFactor[ui32SequenceNum] = ui32Value;
}
//*****************************************************************************
//
//! Configures a step of the software oversampled sequencer.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param ui32Step is the step to be configured.
//! \param ui32Config is the configuration of this step.
//!
//! This function configures a step of the sample sequencer when using the
//! software oversampling feature. The number of steps available depends on
//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
//! of \e ui32Config is the same as defined for ADCSequenceStepConfigure().
//!
//! \return None.
//
//*****************************************************************************
void
ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Step, uint32_t ui32Config)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 3);
ASSERT(((ui32SequenceNum == 0) &&
(ui32Step < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) ||
(ui32Step < (4 >> g_pui8OversampleFactor[ui32SequenceNum])));
//
// Get the offset of the sequence to be configured.
//
ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
//
// Compute the shift for the bits that control this step.
//
ui32Step *= 4 << g_pui8OversampleFactor[ui32SequenceNum];
//
// Loop through the hardware steps that make up this step of the software
// oversampled sequence.
//
for(ui32SequenceNum = 1 << g_pui8OversampleFactor[ui32SequenceNum];
ui32SequenceNum; ui32SequenceNum--)
{
//
// Set the analog mux value for this step.
//
HWREG(ui32Base + ADC_SSMUX) = ((HWREG(ui32Base + ADC_SSMUX) &
~(0x0000000f << ui32Step)) |
((ui32Config & 0x0f) << ui32Step));
//
// Set the upper bits of the analog mux value for this step.
//
HWREG(ui32Base + ADC_SSEMUX) = ((HWREG(ui32Base + ADC_SSEMUX) &
~(0x0000000f << ui32Step)) |
(((ui32Config & 0xf00) >> 8) <<
ui32Step));
//
// Set the control value for this step.
//
HWREG(ui32Base + ADC_SSCTL) = ((HWREG(ui32Base + ADC_SSCTL) &
~(0x0000000f << ui32Step)) |
(((ui32Config & 0xf0) >> 4) <<
ui32Step));
if(ui32SequenceNum != 1)
{
HWREG(ui32Base + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
ADC_SSCTL0_END0) << ui32Step);
}
//
// Go to the next hardware step.
//
ui32Step += 4;
}
}
//*****************************************************************************
//
//! Gets the captured data for a sample sequence using software oversampling.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//! \param pui32Buffer is the address where the data is stored.
//! \param ui32Count is the number of samples to be read.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer with software oversampling applied. The requested
//! number of samples are copied into the data buffer; if there are not enough
//! samples in the hardware FIFO to satisfy this many oversampled data items,
//! then incorrect results are returned. It is the caller's responsibility to
//! read only the samples that are available and wait until enough data is
//! available, for example as a result of receiving an interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t *pui32Buffer, uint32_t ui32Count)
{
uint32_t ui32Idx, ui32Accum;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 3);
ASSERT(((ui32SequenceNum == 0) &&
(ui32Count < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) ||
(ui32Count < (4 >> g_pui8OversampleFactor[ui32SequenceNum])));
//
// Get the offset of the sequence to be read.
//
ui32Base += ADC_SEQ + (ADC_SEQ_STEP * ui32SequenceNum);
//
// Read the samples from the FIFO until it is empty.
//
while(ui32Count--)
{
//
// Compute the sum of the samples.
//
ui32Accum = 0;
for(ui32Idx = 1 << g_pui8OversampleFactor[ui32SequenceNum]; ui32Idx;
ui32Idx--)
{
//
// Read the FIFO and add it to the accumulator.
//
ui32Accum += HWREG(ui32Base + ADC_SSFIFO);
}
//
// Write the averaged sample to the output buffer.
//
*pui32Buffer++ = ui32Accum >> g_pui8OversampleFactor[ui32SequenceNum];
}
}
//*****************************************************************************
//
//! Configures the hardware oversampling factor of the ADC.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Factor is the number of samples to be averaged.
//!
//! This function configures the hardware oversampling for the ADC, which can
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input. Six
//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
//! Specifying an oversampling factor of zero disables hardware
//! oversampling.
//!
//! Hardware oversampling applies uniformly to all sample sequencers. It does
//! not reduce the depth of the sample sequencers like the software
//! oversampling APIs; each sample written into the sample sequencer FIFO is a
//! fully oversampled analog input reading.
//!
//! Enabling hardware averaging increases the precision of the ADC at the cost
//! of throughput. For example, enabling 4x oversampling reduces the
//! throughput of a 250 k samples/second ADC to 62.5 k samples/second.
//!
//! \return None.
//
//*****************************************************************************
void
ADCHardwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32Factor)
{
uint32_t ui32Value;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(((ui32Factor == 0) || (ui32Factor == 2) || (ui32Factor == 4) ||
(ui32Factor == 8) || (ui32Factor == 16) || (ui32Factor == 32) ||
(ui32Factor == 64)));
//
// Convert the oversampling factor to a shift factor.
//
for(ui32Value = 0, ui32Factor >>= 1; ui32Factor;
ui32Value++, ui32Factor >>= 1)
{
}
//
// Write the shift factor to the ADC to configure the hardware oversampler.
//
HWREG(ui32Base + ADC_O_SAC) = ui32Value;
}
//*****************************************************************************
//
//! Configures an ADC digital comparator.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Comp is the index of the comparator to configure.
//! \param ui32Config is the configuration of the comparator.
//!
//! This function configures a comparator. The \e ui32Config parameter is
//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
//! \b ADC_COMP_INT_xxx values.
//!
//! The \b ADC_COMP_TRIG_xxx term can take on the following values:
//!
//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
//! ADC output is in the low-band.
//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
//! output transitions into the low-band.
//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
//! ADC output is in the low-band only if ADC output has been in the high-band
//! since the last trigger output.
//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
//! output transitions into low-band only if ADC output has been in the
//! high-band since the last trigger output.
//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
//! ADC output is in the mid-band.
//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
//! output transitions into the mid-band.
//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
//! ADC output is in the high-band.
//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
//! output transitions into the high-band.
//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
//! ADC output is in the high-band only if ADC output has been in the low-band
//! since the last trigger output.
//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
//! output transitions into high-band only if ADC output has been in the
//! low-band since the last trigger output.
//!
//! The \b ADC_COMP_INT_xxx term can take on the following values:
//!
//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
//! output is in the low-band.
//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
//! transitions into the low-band.
//! - \b ADC_COMP_INT_LOW_HALWAYS to always generate ADC interrupt when ADC
//! output is in the low-band only if ADC output has been in the high-band
//! since the last trigger output.
//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
//! transitions into low-band only if ADC output has been in the high-band
//! since the last trigger output.
//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
//! output is in the mid-band.
//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
//! transitions into the mid-band.
//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
//! output is in the high-band.
//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
//! transitions into the high-band.
//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
//! output is in the high-band only if ADC output has been in the low-band
//! since the last trigger output.
//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
//! transitions into high-band only if ADC output has been in the low-band
//! since the last trigger output.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32Config)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32Comp < 8);
//
// Save the new setting.
//
HWREG(ui32Base + ADC_O_DCCTL0 + (ui32Comp * 4)) = ui32Config;
}
//*****************************************************************************
//
//! Defines the ADC digital comparator regions.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Comp is the index of the comparator to configure.
//! \param ui32LowRef is the reference point for the low/mid band threshold.
//! \param ui32HighRef is the reference point for the mid/high band threshold.
//!
//! The ADC digital comparator operation is based on three ADC value regions:
//! - \b low-band is defined as any ADC value less than or equal to the
//! \e ui32LowRef value.
//! - \b mid-band is defined as any ADC value greater than the \e ui32LowRef
//! value but less than or equal to the \e ui32HighRef value.
//! - \b high-band is defined as any ADC value greater than the \e ui32HighRef
//! value.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32LowRef, uint32_t ui32HighRef)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32Comp < 8);
ASSERT((ui32LowRef < 4096) && (ui32LowRef <= ui32HighRef));
ASSERT(ui32HighRef < 4096);
//
// Save the new region settings.
//
HWREG(ui32Base + ADC_O_DCCMP0 + (ui32Comp * 4)) = ((ui32HighRef << 16) |
ui32LowRef);
}
//*****************************************************************************
//
//! Resets the current ADC digital comparator conditions.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Comp is the index of the comparator.
//! \param bTrigger is the flag to indicate reset of Trigger conditions.
//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
//!
//! Because the digital comparator uses current and previous ADC values, this
//! function allows the comparator to be reset to its initial
//! value to prevent stale data from being used when a sequence is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, bool bTrigger,
bool bInterrupt)
{
uint32_t ui32Temp;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32Comp < 8);
//
// Set the appropriate bits to reset the trigger and/or interrupt
// comparator conditions.
//
ui32Temp = 0;
if(bTrigger)
{
ui32Temp |= (1 << (16 + ui32Comp));
}
if(bInterrupt)
{
ui32Temp |= (1 << ui32Comp);
}
HWREG(ui32Base + ADC_O_DCRIC) = ui32Temp;
}
//*****************************************************************************
//
//! Disables a sample sequence comparator interrupt.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function disables the requested sample sequence comparator interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Disable this sample sequence comparator interrupt.
//
HWREG(ui32Base + ADC_O_IM) &= ~(0x10000 << ui32SequenceNum);
}
//*****************************************************************************
//
//! Enables a sample sequence comparator interrupt.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! This function enables the requested sample sequence comparator interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Enable this sample sequence interrupt.
//
HWREG(ui32Base + ADC_O_IM) |= 0x10000 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Gets the current comparator interrupt status.
//!
//! \param ui32Base is the base address of the ADC module.
//!
//! This function returns the digital comparator interrupt status bits. This
//! status is sequence agnostic.
//!
//! \return The current comparator interrupt status.
//
//*****************************************************************************
uint32_t
ADCComparatorIntStatus(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Return the digital comparator interrupt status.
//
return(HWREG(ui32Base + ADC_O_DCISC));
}
//*****************************************************************************
//
//! Clears sample sequence comparator interrupt source.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Status is the bit-mapped interrupts status to clear.
//!
//! The specified interrupt status is cleared.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Clear the interrupt.
//
HWREG(ui32Base + ADC_O_DCISC) = ui32Status;
}
//*****************************************************************************
//
//! Disables ADC interrupt sources.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
//!
//! This function disables the indicated ADC interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
//!
//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0.
//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1.
//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2.
//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3.
//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0.
//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1.
//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2.
//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3.
//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample
//! sequence 0.
//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample
//! sequence 1.
//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample
//! sequence 2.
//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample
//! sequence 3.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Disable the requested interrupts.
//
HWREG(ui32Base + ADC_O_IM) &= ~ui32IntFlags;
}
//*****************************************************************************
//
//! Enables ADC interrupt sources.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
//!
//! This function enables the indicated ADC interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
//!
//! - \b ADC_INT_SS0 - interrupt due to ADC sample sequence 0.
//! - \b ADC_INT_SS1 - interrupt due to ADC sample sequence 1.
//! - \b ADC_INT_SS2 - interrupt due to ADC sample sequence 2.
//! - \b ADC_INT_SS3 - interrupt due to ADC sample sequence 3.
//! - \b ADC_INT_DMA_SS0 - interrupt due to DMA on ADC sample sequence 0.
//! - \b ADC_INT_DMA_SS1 - interrupt due to DMA on ADC sample sequence 1.
//! - \b ADC_INT_DMA_SS2 - interrupt due to DMA on ADC sample sequence 2.
//! - \b ADC_INT_DMA_SS3 - interrupt due to DMA on ADC sample sequence 3.
//! - \b ADC_INT_DCON_SS0 - interrupt due to digital comparator on ADC sample
//! sequence 0.
//! - \b ADC_INT_DCON_SS1 - interrupt due to digital comparator on ADC sample
//! sequence 1.
//! - \b ADC_INT_DCON_SS2 - interrupt due to digital comparator on ADC sample
//! sequence 2.
//! - \b ADC_INT_DCON_SS3 - interrupt due to digital comparator on ADC sample
//! sequence 3.
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Enable the requested interrupts.
//
HWREG(ui32Base + ADC_O_IM) |= ui32IntFlags;
}
//*****************************************************************************
//
//! Gets interrupt status for the specified ADC module.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param bMasked specifies whether masked or raw interrupt status is
//! returned.
//!
//! If \e bMasked is set as \b true, then the masked interrupt status is
//! returned; otherwise, the raw interrupt status is returned.
//!
//! \return Returns the current interrupt status for the specified ADC module.
//! The value returned is the logical OR of the \b ADC_INT_* values that are
//! currently active.
//
//*****************************************************************************
uint32_t
ADCIntStatusEx(uint32_t ui32Base, bool bMasked)
{
uint32_t ui32Temp;
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Return either the masked interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
ui32Temp = HWREG(ui32Base + ADC_O_ISC);
}
else
{
//
// Read the Raw interrupt status to see if a digital comparator
// interrupt is active.
//
ui32Temp = HWREG(ui32Base + ADC_O_RIS);
//
// Since, the raw interrupt status only indicates that any one of the
// digital comparators caused an interrupt, if the raw interrupt status
// is set then the return value is modified to indicate that all sample
// sequences have a pending digital comparator interrupt.
// This is exactly how the hardware works so the return code is
// modified to match this behavior.
//
if(ui32Temp & ADC_RIS_INRDC)
{
ui32Temp |= (ADC_INT_DCON_SS3 | ADC_INT_DCON_SS2 |
ADC_INT_DCON_SS1 | ADC_INT_DCON_SS0);
}
}
return(ui32Temp);
}
//*****************************************************************************
//
//! Clears the specified ADC interrupt sources.
//!
//! \param ui32Base is the base address of the ADC port.
//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
//!
//! Clears the interrupt for the specified interrupt source(s).
//!
//! The \e ui32IntFlags parameter is the logical OR of the \b ADC_INT_* values.
//! See the ADCIntEnableEx() function for the list of possible \b ADC_INT*
//! values.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Note: The interrupt bits are "W1C" so we DO NOT use a logical OR
// here to clear the requested bits. Doing so would clear all outstanding
// interrupts rather than just those which the caller has specified.
//
HWREG(ui32Base + ADC_O_ISC) = ui32IntFlags;
}
//*****************************************************************************
//
//! Selects the ADC reference.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Ref is the reference to use.
//!
//! The ADC reference is set as specified by \e ui32Ref. It must be one of
//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or
//! external reference. If \b ADC_REF_INT is chosen, then an internal 3V
//! reference is used and no external reference is needed. If
//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the
//! AVREF pin. If \b ADC_REF_EXT_1V is chosen, then a 1V external reference
//! must be supplied to the AVREF pin.
//!
//! \note The ADC reference can only be selected on parts that have an external
//! reference. Consult the data sheet for your part to determine if there is
//! an external reference.
//!
//! \return None.
//
//*****************************************************************************
void
ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V) ||
(ui32Ref == ADC_REF_EXT_1V));
//
// Set the reference.
//
HWREG(ui32Base + ADC_O_CTL) =
(HWREG(ui32Base + ADC_O_CTL) & ~ADC_CTL_VREF_M) | ui32Ref;
}
//*****************************************************************************
//
//! Returns the current setting of the ADC reference.
//!
//! \param ui32Base is the base address of the ADC module.
//!
//! Returns the value of the ADC reference setting. The returned value is one
//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V.
//!
//! \note The value returned by this function is only meaningful if used on a
//! part that is capable of using an external reference. Consult the data
//! sheet for your part to determine if it has an external reference input.
//!
//! \return The current setting of the ADC reference.
//
//*****************************************************************************
uint32_t
ADCReferenceGet(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Return the value of the reference.
//
return(HWREG(ui32Base + ADC_O_CTL) & ADC_CTL_VREF_M);
}
//*****************************************************************************
//
//! Sets the phase delay between a trigger and the start of a sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32Phase is the phase delay, specified as one of \b ADC_PHASE_0,
//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
//!
//! This function sets the phase delay between the detection of an ADC trigger
//! event and the start of the sample sequence. By selecting a different phase
//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and
//! \b ADC_PHASE_180) and having each ADC module sample the same analog input,
//! it is possible to increase the sampling rate of the analog input (with
//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1,
//! N+3, N+5, and so on, coming from the second ADC). The ADC module has a
//! single phase delay that is applied to all sample sequences within that
//! module.
//!
//! \note This capability is not available on all parts.
//!
//! \return None.
//
//*****************************************************************************
void
ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT((ui32Phase == ADC_PHASE_0) || (ui32Phase == ADC_PHASE_22_5) ||
(ui32Phase == ADC_PHASE_45) || (ui32Phase == ADC_PHASE_67_5) ||
(ui32Phase == ADC_PHASE_90) || (ui32Phase == ADC_PHASE_112_5) ||
(ui32Phase == ADC_PHASE_135) || (ui32Phase == ADC_PHASE_157_5) ||
(ui32Phase == ADC_PHASE_180) || (ui32Phase == ADC_PHASE_202_5) ||
(ui32Phase == ADC_PHASE_225) || (ui32Phase == ADC_PHASE_247_5) ||
(ui32Phase == ADC_PHASE_270) || (ui32Phase == ADC_PHASE_292_5) ||
(ui32Phase == ADC_PHASE_315) || (ui32Phase == ADC_PHASE_337_5));
//
// Set the phase delay.
//
HWREG(ui32Base + ADC_O_SPC) = ui32Phase;
}
//*****************************************************************************
//
//! Gets the phase delay between a trigger and the start of a sequence.
//!
//! \param ui32Base is the base address of the ADC module.
//!
//! This function gets the current phase delay between the detection of an ADC
//! trigger event and the start of the sample sequence.
//!
//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0,
//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
//
//*****************************************************************************
uint32_t
ADCPhaseDelayGet(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Return the phase delay.
//
return(HWREG(ui32Base + ADC_O_SPC));
}
//*****************************************************************************
//
//! Enables DMA for sample sequencers.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! Allows DMA requests to be generated based on the FIFO level of the sample
//! sequencer.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Enable the DMA on the specified sequencer.
//
HWREG(ui32Base + ADC_O_ACTSS) |= 0x100 << ui32SequenceNum;
}
//*****************************************************************************
//
//! Disables DMA for sample sequencers.
//!
//! \param ui32Base is the base address of the ADC module.
//! \param ui32SequenceNum is the sample sequence number.
//!
//! Prevents the specified sample sequencer from generating DMA requests.
//!
//! \return None.
//
//*****************************************************************************
void
ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum)
{
//
// Check the arguments.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
ASSERT(ui32SequenceNum < 4);
//
// Disable the DMA on the specified sequencer.
//
HWREG(ui32Base + ADC_O_ACTSS) &= ~(0x100 << ui32SequenceNum);
}
//*****************************************************************************
//
//! Determines whether the ADC is busy or not.
//!
//! \param ui32Base is the base address of the ADC.
//!
//! This function allows the caller to determine whether or not the ADC is
//! currently sampling . If \b false is returned, then the ADC is not
//! sampling data.
//!
//! Use this function to detect that the ADC is finished sampling data before
//! putting the device into deep sleep. Before using this function, it is
//! highly recommended that the event trigger is changed to
//! \b ADC_TRIGGER_NEVER on all enabled sequencers to prevent the ADC from
//! starting after checking the busy status.
//!
//! \return Returns \b true if the ADC is sampling or \b false if all
//! samples are complete.
//
//*****************************************************************************
bool
ADCBusy(uint32_t ui32Base)
{
//
// Check the argument.
//
ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
//
// Determine if the ADC is busy.
//
return((HWREG(ui32Base + ADC_O_ACTSS) & ADC_ACTSS_BUSY) ? true : false);
}
//*****************************************************************************
//
//! Sets the clock configuration for the ADC.
//!
//! \param ui32Base is the base address of the ADC to configure, which must
//! always be \b ADC0_BASE.
//! \param ui32Config is a combination of the \b ADC_CLOCK_SRC_ and
//! \b ADC_CLOCK_RATE_* values used to configure the ADC clock input.
//! \param ui32ClockDiv is the input clock divider for the clock selected by
//! the \b ADC_CLOCK_SRC value.
//!
//! This function is used to configure the input clock to the ADC modules. The
//! clock configuration is shared across ADC units so \e ui32Base must
//! always be \b ADC0_BASE. The \e ui32Config value is logical OR of one
//! of the \b ADC_CLOCK_RATE_ and one of the \b ADC_CLOCK_SRC_ values defined
//! below. The \b ADC_CLOCK_SRC_* values determine the input clock for the ADC.
//! Not all values are available on all devices so check the device data sheet
//! to determine value configuration options. Regardless of the source, the
//! final frequency for TM4C123x devices must be 16 MHz and for TM4C129x parts
//! after dividing must be between 16 and 32 MHz.
//!
//! \note For TM4C123x devices, if the PLL is enabled, the PLL/25 is used as
//! the ADC clock unless ADC_CLOCK_SRC_PIOSC is specified. If the PLL is
//! disabled, the MOSC is used as the clock source unless ADC_CLOCK_SRC_PIOSC
//! is specified.
//!
//! - \b ADC_CLOCK_SRC_PLL - The main PLL output (TM4x129 class only).
//! - \b ADC_CLOCK_SRC_PIOSC - The internal PIOSC at 16 MHz.
//! - \b ADC_CLOCK_SRC_ALTCLK - The output of the ALTCLK in the system control
//! module (TM4x129 class only).
//! - \b ADC_CLOCK_SRC_MOSC - The external MOSC (TM4x129 class only).
//!
//! \b ADC_CLOCK_RATE values control how often samples are provided back to the
//! application. The values are the following:
//!
//! - \b ADC_CLOCK_RATE_FULL - All samples.
//! - \b ADC_CLOCK_RATE_HALF - Every other sample.
//! - \b ADC_CLOCK_RATE_QUARTER - Every fourth sample.
//! - \b ADC_CLOCK_RATE_EIGHTH - Every either sample.
//!
//! The \e ui32ClockDiv parameter allows for dividing a higher frequency down
//! into the valid range for the ADCs. This parameter is typically only used
//! \b ADC_CLOCK_SRC_PLL option because it is the only clock value that can be
//! with the in the correct range to use the divider. The actual value ranges
//! from 1 to 64.
//!
//! \b Example: ADC Clock Configurations
//!
//! \verbatim
//!
//! //
//! // Configure the ADC to use PIOSC divided by one (16 MHz) and sample at
//! // half the rate.
//! //
//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_HALF, 1);
//!
//! ...
//!
//! //
//! // Configure the ADC to use PLL at 480 MHz divided by 24 to get an ADC
//! // clock of 20 MHz.
//! //
//! ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 24);
//! \endverbatim
//!
//! \return None.
//
//*****************************************************************************
void
ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32ClockDiv)
{
//
// Check the argument.
//
ASSERT(ui32Base == ADC0_BASE);
//
// A rate must be supplied.
//
ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0);
//
// Clock must be valid divider.
//
ASSERT(((ui32ClockDiv - 1) & (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S)) == 0);
//
// Write the sample conversion rate.
//
HWREG(ui32Base + ADC_O_PC) = (ui32Config >> 4) & ADC_PC_SR_M;
//
// Write the clock select and divider.
//
HWREG(ui32Base + ADC_O_CC) = (ui32Config & ADC_CC_CS_M) |
(((ui32ClockDiv - 1) << ADC_CC_CLKDIV_S)) ;
}
//*****************************************************************************
//
//! Returns the clock configuration for the ADC.
//!
//! \param ui32Base is the base address of the ADC to configure, which must
//! always be \b ADC0_BASE.
//! \param pui32ClockDiv is a pointer to the input clock divider for the clock
//! selected by the \b ADC_CLOCK_SRC in use by the ADCs.
//!
//! This function returns the ADC clock configuration and the clock divider for
//! the ADCs.
//!
//! \b Example: Read the current ADC clock configuration.
//!
//! \verbatim
//! uint32_t ui32Config, ui32ClockDiv;
//!
//! //
//! // Read the current ADC clock configuration.
//! //
//! ui32Config = ADCClockConfigGet(ADC0_BASE, &ui32ClockDiv);
//! \endverbatim
//!
//! \return The current clock configuration of the ADC defined as a combination
//! of one of \b ADC_CLOCK_SRC_PLL, \b ADC_CLOCK_SRC_PIOSC,
//! \b ADC_CLOCK_SRC_MOSC, or \b ADC_CLOCK_SRC_ALTCLK logical ORed with one of
//! \b ADC_CLOCK_RATE_FULL, \b ADC_CLOCK_RATE_HALF, \b ADC_CLOCK_RATE_QUARTER,
//! or \b ADC_CLOCK_RATE_EIGHTH. See ADCClockConfigSet() for more information
//! on these values.
//
//*****************************************************************************
uint32_t
ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv)
{
uint32_t ui32Config;
//
// Check the argument.
//
ASSERT(ui32Base == ADC0_BASE);
//
// Read the current configuration.
//
ui32Config = HWREG(ui32Base + ADC_O_CC);
//
// If the clock divider was requested provide the current value.
//
if(pui32ClockDiv)
{
*pui32ClockDiv =
((ui32Config & ADC_CC_CLKDIV_M) >> ADC_CC_CLKDIV_S) + 1;
}
//
// Clear out the divider bits.
//
ui32Config &= ~ADC_CC_CLKDIV_M;
//
// Add in the sample interval to the configuration.
//
ui32Config = (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4;
return(ui32Config);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
| weedegee/x25519-cortexm4 | launchpad/driverlib/adc.c | C | unlicense | 73,307 |
package Person;
use 5.006;
use strict;
use warnings;
use parent qw( LivingCreature );
=head1 NAME
Person - The great new Person!
=head1 VERSION
Version 0.01
=cut
our $VERSION = '0.01';
=head1 SYNOPSIS
Quick summary of what the module does.
Perhaps a little code snippet.
use Person;
my $foo = Person->new();
...
=head1 EXPORT
A list of functions that can be exported. You can delete this section
if you don't export anything, such as for a purely object-oriented module.
=head1 SUBROUTINES/METHODS
=head2 speak
=cut
=head2 function2
=cut
sub sound {
'hummmm hummm hummmmmm';
}
=head1 AUTHOR
Ruddy Stream, C<< <ruddystream at gmail.com> >>
=head1 BUGS
Please report any bugs or feature requests to C<bug-. at rt.cpan.org>, or through
the web interface at L<http://rt.cpan.org/NoAuth/ReportBug.html?Queue=.>. I will be notified, and then you'll
automatically be notified of progress on your bug as I make changes.
=head1 SUPPORT
You can find documentation for this module with the perldoc command.
perldoc Person
You can also look for information at:
=over 4
=item * RT: CPAN's request tracker (report bugs here)
L<http://rt.cpan.org/NoAuth/Bugs.html?Dist=.>
=item * AnnoCPAN: Annotated CPAN documentation
L<http://annocpan.org/dist/.>
=item * CPAN Ratings
L<http://cpanratings.perl.org/d/.>
=item * Search CPAN
L<http://search.cpan.org/dist/./>
=back
=head1 ACKNOWLEDGEMENTS
=head1 LICENSE AND COPYRIGHT
Copyright 2017 Ruddy Stream.
This program is free software; you can redistribute it and/or modify it
under the terms of the the Artistic License (2.0). You may obtain a
copy of the full license at:
L<http://www.perlfoundation.org/artistic_license_2_0>
Any use, modification, and distribution of the Standard or Modified
Versions is governed by this Artistic License. By using, modifying or
distributing the Package, you accept this license. Do not use, modify,
or distribute the Package, if you do not accept this license.
If your Modified Version has been derived from a Modified Version made
by someone other than you, you are nevertheless required to ensure that
your Modified Version complies with the requirements of this license.
This license does not grant you the right to use any trademark, service
mark, tradename, or logo of the Copyright Holder.
This license includes the non-exclusive, worldwide, free-of-charge
patent license to make, have made, use, offer to sell, sell, import and
otherwise transfer the Package with respect to any patent claims
licensable by the Copyright Holder that are necessarily infringed by the
Package. If you institute patent litigation (including a cross-claim or
counterclaim) against any party alleging that the Package constitutes
direct or contributory patent infringement, then this Artistic License
to you shall terminate on the date that such litigation is filed.
Disclaimer of Warranty: THE PACKAGE IS PROVIDED BY THE COPYRIGHT HOLDER
AND CONTRIBUTORS "AS IS' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES.
THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED TO THE EXTENT PERMITTED BY
YOUR LOCAL LAW. UNLESS REQUIRED BY LAW, NO COPYRIGHT HOLDER OR
CONTRIBUTOR WILL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THE USE OF THE PACKAGE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=cut
1; # End of Person
| ruddystream/Intermediate-Perl | chapter-15/lib/Person.pm | Perl | unlicense | 3,457 |
/*
* Copyright (c) 2015 The WebRTC project authors. All Rights Reserved.
*
* Use of this source code is governed by a BSD-style license
* that can be found in the LICENSE file in the root of the source
* tree. An additional intellectual property rights grant can be found
* in the file PATENTS. All contributing project authors may
* be found in the AUTHORS file in the root of the source tree.
*/
#ifndef RTC_BASE_PLATFORM_THREAD_TYPES_H_
#define RTC_BASE_PLATFORM_THREAD_TYPES_H_
// clang-format off
// clang formating would change include order.
#if defined(WEBRTC_WIN)
// Include winsock2.h before including <windows.h> to maintain consistency with
// win32.h. To include win32.h directly, it must be broken out into its own
// build target.
#include <winsock2.h>
#include <windows.h>
#elif defined(WEBRTC_FUCHSIA)
#include <zircon/types.h>
#include <zircon/process.h>
#elif defined(WEBRTC_POSIX)
#include <pthread.h>
#include <unistd.h>
#endif
// clang-format on
namespace rtc {
#if defined(WEBRTC_WIN)
typedef DWORD PlatformThreadId;
typedef DWORD PlatformThreadRef;
#elif defined(WEBRTC_FUCHSIA)
typedef zx_handle_t PlatformThreadId;
typedef zx_handle_t PlatformThreadRef;
#elif defined(WEBRTC_POSIX)
typedef pid_t PlatformThreadId;
typedef pthread_t PlatformThreadRef;
#endif
// Retrieve the ID of the current thread.
PlatformThreadId CurrentThreadId();
// Retrieves a reference to the current thread. On Windows, this is the same
// as CurrentThreadId. On other platforms it's the pthread_t returned by
// pthread_self().
PlatformThreadRef CurrentThreadRef();
// Compares two thread identifiers for equality.
bool IsThreadRefEqual(const PlatformThreadRef& a, const PlatformThreadRef& b);
// Sets the current thread name.
void SetCurrentThreadName(const char* name);
} // namespace rtc
#endif // RTC_BASE_PLATFORM_THREAD_TYPES_H_
| grishka/libtgvoip | webrtc_dsp/rtc_base/platform_thread_types.h | C | unlicense | 1,864 |
//===----------------------------------------------------------------------===//
//
// PelotonDB
//
// tuple_address_expression.cpp
//
// Identification: src/backend/expression/tuple_address_expression.cpp
//
// Copyright (c) 2015, Carnegie Mellon University Database Group
//
//===----------------------------------------------------------------------===//
#include "backend/expression/tuple_address_expression.h"
#include "backend/common/logger.h"
#include "backend/expression/abstract_expression.h"
namespace peloton {
namespace expression {
TupleAddressExpression::TupleAddressExpression()
: AbstractExpression(EXPRESSION_TYPE_VALUE_TUPLE_ADDRESS) {}
TupleAddressExpression::~TupleAddressExpression() {}
} // End expression namespace
} // End peloton namespace
| eric-haibin-lin/peloton | src/backend/expression/tuple_address_expression.cpp | C++ | apache-2.0 | 800 |
/**
* Copyright 2014 The PlayN Authors
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except
* in compliance with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software distributed under the
* License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
* express or implied. See the License for the specific language governing permissions and
* limitations under the License.
*/
package playn.robovm;
import java.io.File;
import org.robovm.apple.avfoundation.AVAudioPlayer;
import org.robovm.apple.avfoundation.AVAudioSession;
import org.robovm.apple.avfoundation.AVAudioSessionSetActiveOptions;
import org.robovm.apple.foundation.NSErrorException;
import org.robovm.apple.foundation.NSURL;
import playn.core.Audio;
import playn.core.Sound;
import static playn.robovm.OpenAL.*;
public class RoboAudio extends Audio {
private final RoboPlatform plat;
private final AVAudioSession session;
private final long oalDevice;
private final long oalContext;
private final int[] sources;
private final RoboSoundOAL[] active;
private final int[] started;
public RoboAudio(RoboPlatform plat, int numSources) {
this.plat = plat;
session = AVAudioSession.getSharedInstance();
try {
session.setActive(true, AVAudioSessionSetActiveOptions.None);
} catch (NSErrorException e) {
plat.log().error("Unable to activate audio session: " + e);
}
oalDevice = alcOpenDevice(null);
if (oalDevice != 0) {
oalContext = alcCreateContext(oalDevice, null);
alcMakeContextCurrent(oalContext);
} else {
plat.log().warn("Unable to open OpenAL device. Disabling OAL sound.");
oalContext = 0;
}
// obtain our desired number of sources
sources = new int[numSources];
alGenSources(numSources, sources);
active = new RoboSoundOAL[sources.length];
started = new int[sources.length];
// TODO: this should use AVAudioSessionInterruptionNotification
// clear and restore our OAL context on audio session interruption
// AudioSession.add_Interrupted(new EventHandler(new EventHandler.Method() {
// public void Invoke(Object sender, EventArgs event) {
// // not needed?: session.setActive(false, null);
// OpenAL.alcMakeContextCurrent(0);
// }
// }));
// AudioSession.add_Resumed(new EventHandler(new EventHandler.Method() {
// public void Invoke(Object sender, EventArgs event) {
// OpenAL.alcMakeContextCurrent(alcContext);
// // not needed?: session.setActive(true, null);
// }
// }));
}
public Sound createSound(File path, boolean isMusic) {
// if the file is meant to be music, or if it's not uncompressed CAFF, we need to use
// AVAudioPlayer; if it's uncompressed CAFF, we can use OpenAL
return (isMusic || !path.getName().endsWith(".caf")) ?
createAVAP(new NSURL(path)) : createOAL(path);
}
Sound createAVAP(final NSURL url) {
final RoboSoundAVAP sound = new RoboSoundAVAP(plat);
plat.exec().invokeAsync(new Runnable() {
public void run () {
try {
sound.succeed(new AVAudioPlayer(url));
} catch (Exception e) {
plat.log().warn("Error loading sound [" + url + "]", e);
sound.fail(e);
}
}
});
return sound;
}
Sound createOAL(final File assetPath) {
final RoboSoundOAL sound = new RoboSoundOAL(plat);
plat.exec().invokeAsync(new Runnable() {
public void run () {
int bufferId = 0;
try {
bufferId = alGenBuffer();
CAFLoader.load(assetPath, bufferId);
sound.succeed(bufferId);
} catch (Throwable t) {
if (bufferId != 0) alDeleteBuffer(bufferId);
sound.fail(t);
}
}
});
return sound;
}
boolean isPlaying(int sourceIdx, RoboSoundOAL sound) {
if (active[sourceIdx] != sound)
return false;
int[] result = new int[1];
alGetSourcei(sources[sourceIdx], AL_SOURCE_STATE, result);
return (result[0] == AL_PLAYING);
}
int play(RoboSoundOAL sound, float volume, boolean looping) {
// find a source that's not currently playing
int sourceIdx = -1, eldestIdx = 0;
for (int ii = 0; ii < sources.length; ii++) {
if (!isPlaying(ii, active[ii])) {
sourceIdx = ii;
break;
} else if (started[ii] < started[eldestIdx]) {
eldestIdx = ii;
}
}
// if all of our sources are playing, stop the oldest source and steal it
if (sourceIdx < 0) {
stop(eldestIdx, active[eldestIdx]);
sourceIdx = eldestIdx;
}
// prepare the source to play this sound's buffer
int sourceId = sources[sourceIdx];
alSourcei(sourceId, AL_BUFFER, sound.bufferId());
alSourcef(sourceId, AL_GAIN, volume);
alSourcei(sourceId, AL_LOOPING, looping ? AL_TRUE : AL_FALSE);
alSourcePlay(sourceId);
active[sourceIdx] = sound;
started[sourceIdx] = plat.tick();
return sourceIdx;
}
void stop(int sourceIdx, RoboSoundOAL sound) {
if (active[sourceIdx] == sound) {
alSourceStop(sources[sourceIdx]);
}
}
void delete(RoboSoundOAL sound) {
alDeleteBuffer(sound.bufferId());
}
void setLooping(int sourceIdx, RoboSoundOAL sound, boolean looping) {
if (active[sourceIdx] == sound) {
alSourcei(sources[sourceIdx], AL_LOOPING, looping ? AL_TRUE : AL_FALSE);
}
}
void setVolume(int sourceIdx, RoboSoundOAL sound, float volume) {
if (active[sourceIdx] == sound) {
// OpenAL uses gain between 0 and 1, rather than raw db-based gain
alSourcef(sources[sourceIdx], AL_GAIN, volume);
}
}
void terminate() {
// TODO: ?
// if (actx.get_IsProcessing()) actx.Suspend();
// actx.Dispose();
}
}
| tinkerstudent/playn | robovm/src/playn/robovm/RoboAudio.java | Java | apache-2.0 | 5,945 |
/*
* Copyright 2019 the original author or authors.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package org.gradle.language;
import org.gradle.api.provider.SetProperty;
import org.gradle.nativeplatform.TargetMachine;
/**
* Represents a component that targets multiple target machines.
*
* @since 5.2
*/
public interface ComponentWithTargetMachines {
/**
* Specifies the target machines this component should be built for. The "machines" extension property (see {@link org.gradle.nativeplatform.TargetMachineFactory}) can be used to construct common operating system and architecture combinations.
*
* <p>For example:</p>
* <pre>
* targetMachines = [machines.linux.x86_64, machines.windows.x86_64]
* </pre>
*
* @since 5.2
*/
SetProperty<TargetMachine> getTargetMachines();
}
| gradle/gradle | subprojects/language-native/src/main/java/org/gradle/language/ComponentWithTargetMachines.java | Java | apache-2.0 | 1,355 |
/**
* Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0.
*/
#include <aws/cloudfront/model/CreateStreamingDistribution2020_05_31Request.h>
#include <aws/core/utils/xml/XmlSerializer.h>
#include <aws/core/utils/memory/stl/AWSStringStream.h>
#include <utility>
using namespace Aws::CloudFront::Model;
using namespace Aws::Utils::Xml;
using namespace Aws::Utils;
CreateStreamingDistribution2020_05_31Request::CreateStreamingDistribution2020_05_31Request() :
m_streamingDistributionConfigHasBeenSet(false)
{
}
Aws::String CreateStreamingDistribution2020_05_31Request::SerializePayload() const
{
XmlDocument payloadDoc = XmlDocument::CreateWithRootNode("StreamingDistributionConfig");
XmlNode parentNode = payloadDoc.GetRootElement();
parentNode.SetAttributeValue("xmlns", "http://cloudfront.amazonaws.com/doc/2020-05-31/");
m_streamingDistributionConfig.AddToNode(parentNode);
if(parentNode.HasChildren())
{
return payloadDoc.ConvertToString();
}
return {};
}
| awslabs/aws-sdk-cpp | aws-cpp-sdk-cloudfront/source/model/CreateStreamingDistribution2020_05_31Request.cpp | C++ | apache-2.0 | 1,052 |
// Copyright 2012 The Apache Software Foundation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/** [INTERNAL USE ONLY] Tapestry IOC service implementation classes; API subject to change. */
package org.apache.tapestry5.ioc.internal.services;
| agileowl/tapestry-5 | tapestry-ioc/src/main/java/org/apache/tapestry5/ioc/internal/services/package-info.java | Java | apache-2.0 | 771 |
/*
* Copyright 2012 AndroidPlot.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package com.androidplot.util;
import android.graphics.Canvas;
import android.graphics.Color;
import android.graphics.Paint;
import android.graphics.RectF;
import com.androidplot.Plot;
import com.androidplot.PlotListener;
/**
* !!! THIS CLASS IS STILL UNDER DEVELOPMENT AND MAY CONTAIN BUGS !!!
* Gathers performance statistics from a Plot. Instances of PlotStatistics
* should never be added to more than one Plot, otherwise the statiscs will
* be invalid.
*/
public class PlotStatistics implements PlotListener {
long minRenderTimeMs;
long maxRenderTimeMs;
long avgRenderTimeMs;
long fps;
long updateDelayMs;
long longestRenderMs = 0;
long shortestRenderMs = 0;
long lastStart = 0;
long lastLatency = 0;
long lastAnnotation;
long latencySamples = 0;
long latencySum = 0;
String annotationString = "";
private Paint paint;
{
paint = new Paint();
paint.setTextAlign(Paint.Align.CENTER);
paint.setColor(Color.WHITE);
paint.setTextSize(30);
resetCounters();
}
private boolean annotatePlotEnabled;
public PlotStatistics(long updateDelayMs, boolean annotatePlotEnabled) {
this.updateDelayMs = updateDelayMs;
this.annotatePlotEnabled = annotatePlotEnabled;
}
public void setAnnotatePlotEnabled(boolean enabled) {
this.annotatePlotEnabled = enabled;
}
private void resetCounters() {
longestRenderMs = 0;
shortestRenderMs = 999999999;
latencySamples = 0;
latencySum = 0;
}
private void annotatePlot(Plot source, Canvas canvas) {
long nowMs = System.currentTimeMillis();
// throttle the update frequency:
long msSinceUpdate = (nowMs - lastAnnotation);
if(msSinceUpdate >= updateDelayMs) {
float avgLatency = latencySamples > 0 ? latencySum/latencySamples : 0;
String overallFPS = String.format("%.2f", latencySamples > 0 ? (1000f/msSinceUpdate) * latencySamples : 0);
String potentialFPS = String.format("%.2f", latencySamples > 0 ? 1000f/avgLatency : 0);
annotationString = "FPS (potential): " + potentialFPS + " FPS (actual): " + overallFPS + " Latency (ms) Avg: " + lastLatency + " \nMin: " + shortestRenderMs +
" Max: " + longestRenderMs;
lastAnnotation = nowMs;
resetCounters();
}
RectF r = source.getDisplayDimensions().canvasRect;
if(annotatePlotEnabled) {
canvas.drawText(annotationString, r.centerX(), r.centerY(), paint);
}
}
@Override
public void onBeforeDraw(Plot source, Canvas canvas) {
lastStart = System.currentTimeMillis();
}
@Override
public void onAfterDraw(Plot source, Canvas canvas) {
lastLatency = System.currentTimeMillis() - lastStart;
if(lastLatency < shortestRenderMs) {
shortestRenderMs = lastLatency;
}
if(lastLatency > longestRenderMs) {
longestRenderMs = lastLatency;
}
latencySum += lastLatency;
latencySamples++;
annotatePlot(source, canvas);
}
}
| sayan801/Android-Chart-Graph-Samples | ChartPrototypeAndroidplot/app/libs/AndroidPlot-Core/src/main/java/com/androidplot/util/PlotStatistics.java | Java | apache-2.0 | 3,926 |
/**
* Copyright 2016 The AMP HTML Authors. All Rights Reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS-IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
import {
deepEquals,
getChildJsonConfig,
getValueForExpr,
recreateNonProtoObject,
tryParseJson,
} from '../../src/json';
describe('json', () => {
describe('getValueForExpr', () => {
it('should return self for "."', () => {
const obj = {str: 'A', num: 1, bool: true, val: null};
expect(getValueForExpr(obj, '.')).to.equal(obj);
});
it('should return a simple value', () => {
const obj = {str: 'A', num: 1, bool: true, val: null};
expect(getValueForExpr(obj, 'str')).to.equal('A');
expect(getValueForExpr(obj, 'num')).to.equal(1);
expect(getValueForExpr(obj, 'bool')).to.equal(true);
expect(getValueForExpr(obj, 'val')).to.be.null;
expect(getValueForExpr(obj, 'other')).to.be.undefined;
});
it('should return a nested value', () => {
const child = {str: 'A', num: 1, bool: true, val: null};
const obj = {child};
expect(getValueForExpr(obj, 'child')).to.deep.equal(child);
expect(getValueForExpr(obj, 'child.str')).to.equal('A');
expect(getValueForExpr(obj, 'child.num')).to.equal(1);
expect(getValueForExpr(obj, 'child.bool')).to.equal(true);
expect(getValueForExpr(obj, 'child.val')).to.be.null;
expect(getValueForExpr(obj, 'child.other')).to.be.undefined;
});
it('should return a nested value without proto', () => {
const child = {str: 'A', num: 1, bool: true, val: null};
const obj = recreateNonProtoObject({child});
expect(getValueForExpr(obj, 'child')).to.deep.equal(child);
expect(getValueForExpr(obj, 'child.str')).to.equal('A');
expect(getValueForExpr(obj, 'child.num')).to.equal(1);
expect(getValueForExpr(obj, 'child.bool')).to.equal(true);
expect(getValueForExpr(obj, 'child.val')).to.be.null;
expect(getValueForExpr(obj, 'child.other')).to.be.undefined;
});
it('should shortcircuit if a parent in chain missing', () => {
const child = {str: 'A'};
const obj = {child};
expect(getValueForExpr(obj, 'child.str')).to.equal('A');
expect(getValueForExpr(obj, 'unknown.str')).to.be.undefined;
expect(getValueForExpr(obj, 'unknown.chain.str')).to.be.undefined;
});
it('should shortcircuit if a parent in chain is not an object', () => {
const child = {str: 'A'};
const obj = {child, nonobj: 'B'};
expect(getValueForExpr(obj, 'child.str')).to.equal('A');
expect(getValueForExpr(obj, 'nonobj')).to.equal('B');
expect(getValueForExpr(obj, 'nonobj.str')).to.be.undefined;
});
it('should only search in own properties', () => {
const ancestor = {num: 1};
const obj = Object.create(ancestor);
obj.str = 'A';
expect(getValueForExpr(obj, 'str')).to.equal('A');
expect(getValueForExpr(ancestor, 'num')).to.equal(1);
expect(getValueForExpr(obj, 'num')).to.be.undefined;
expect(getValueForExpr(obj, '__proto__')).to.be.undefined;
});
it('should support array index', () => {
const child = {num: 1, str: 'A'};
const obj = {foo: [child]};
expect(getValueForExpr(obj, 'foo.0.num')).to.equal(1);
expect(getValueForExpr(obj, 'foo.0.str')).to.equal('A');
expect(getValueForExpr(obj, 'foo.0a.str')).to.be.undefined;
expect(getValueForExpr(obj, 'foo.1.num')).to.be.undefined;
expect(getValueForExpr(obj, 'foo.1.str')).to.be.undefined;
});
it('should only search in own properties of arrays', () => {
const arr = ['A'];
expect(getValueForExpr(arr, '0')).to.equal('A');
expect(getValueForExpr(arr, '1')).to.be.undefined;
expect(getValueForExpr(arr, 'concat')).to.be.undefined;
expect(getValueForExpr(arr, '__proto__')).to.be.undefined;
});
});
describe('recreateNonProtoObject', () => {
it('should recreate an empty object', () => {
const original = {};
const copy = recreateNonProtoObject(original);
expect(copy).to.deep.equal(original);
expect(copy).to.not.equal(original);
expect(copy.__proto__).to.be.undefined;
});
it('should recreate an object', () => {
const original = {str: 'A', num: 1, bool: true, val: null};
const copy = recreateNonProtoObject(original);
expect(copy).to.deep.equal(original);
expect(copy).to.not.equal(original);
expect(copy.__proto__).to.be.undefined;
expect(copy.val).to.be.null;
});
it('should recreate a nested object', () => {
const original = {child: {str: 'A', num: 1, bool: true, val: null}};
const copy = recreateNonProtoObject(original);
expect(copy).to.deep.equal(original);
expect(copy).to.not.equal(original);
expect(copy.__proto__).to.be.undefined;
expect(copy.child).to.deep.equal(original.child);
expect(copy.child).to.not.equal(original.child);
expect(copy.child.__proto__).to.be.undefined;
});
});
describe('tryParseJson', () => {
it('should return object for valid json', () => {
const json = '{"key": "value"}';
const result = tryParseJson(json);
expect(result.key).to.equal('value');
});
it('should not throw and return null for invalid json', () => {
const json = '{"key": "val';
expect(tryParseJson.bind(null, json)).to.not.throw;
const result = tryParseJson(json);
expect(result).to.be.null;
});
it('should call onFailed for invalid and not call for valid json', () => {
let onFailedCalled = false;
const validJson = '{"key": "value"}';
tryParseJson(validJson, () => {
onFailedCalled = true;
});
expect(onFailedCalled).to.be.false;
const invalidJson = '{"key": "val';
tryParseJson(invalidJson, err => {
onFailedCalled = true;
expect(err).to.exist;
});
expect(onFailedCalled).to.be.true;
});
});
describe('getChildJsonConfig', () => {
let element;
let script;
let text;
beforeEach(() => {
element = document.createElement('div');
script = document.createElement('script');
script.setAttribute('type', 'application/json');
text = '{"a":{"b": "c"}}';
script.textContent = text;
});
it('return json config', () => {
element.appendChild(script);
expect(getChildJsonConfig(element)).to.deep.equal({
'a': {
'b': 'c',
},
});
});
it('throw if not one script', () => {
expect(() => getChildJsonConfig(element)).to.throw(
'Found 0 <script> children. Expected 1');
element.appendChild(script);
const script2 = document.createElement('script');
element.appendChild(script2);
expect(() => getChildJsonConfig(element)).to.throw(
'Found 2 <script> children. Expected 1');
});
it('throw if type is not application/json', () => {
script.setAttribute('type', '');
element.appendChild(script);
expect(() => getChildJsonConfig(element)).to.throw(
'<script> child must have type="application/json"');
});
it('throw if cannot parse json', () => {
const invalidText = '{"a":{"b": "c",}}';
script.textContent = invalidText;
element.appendChild(script);
expect(() => getChildJsonConfig(element)).to.throw(
'Failed to parse <script> contents. Is it valid JSON?');
});
});
describe('deepEquals', () => {
it('should throw on non-finite depth arg', () => {
expect(() => {
deepEquals({}, {}, Number.POSITIVE_INFINITY);
}).to.throw(/Invalid depth/);
});
it('should handle null and empty objects', () => {
expect(deepEquals(null, null)).to.be.true;
expect(deepEquals({}, {})).to.be.true;
expect(deepEquals({}, null)).to.be.false;
expect(deepEquals([], [])).to.be.true;
expect(deepEquals([], null)).to.be.false;
});
it('should check strict equality', () => {
expect(deepEquals({x: 1}, {x: 1})).to.be.true;
expect(deepEquals({x: false}, {x: false})).to.be.true;
expect(deepEquals({x: 'abc'}, {x: 'abc'})).to.be.true;
expect(deepEquals({x: ''}, {x: false})).to.be.false;
expect(deepEquals({x: false}, {x: ''})).to.be.false;
expect(deepEquals({x: ''}, {x: 0})).to.be.false;
expect(deepEquals({x: 0}, {x: ''})).to.be.false;
expect(deepEquals({x: 1}, {x: true})).to.be.false;
expect(deepEquals({x: true}, {x: 1})).to.be.false;
expect(deepEquals({x: 1}, {x: '1'})).to.be.false;
expect(deepEquals({x: '1'}, {x: 1})).to.be.false;
expect(deepEquals({x: undefined}, {x: null})).to.be.false;
expect(deepEquals({x: null}, {x: undefined})).to.be.false;
expect(deepEquals({x: {}}, {x: '[object Object]'})).to.be.false;
expect(deepEquals({x: '[object Object]'}, {x: {}})).to.be.false;
});
it('should check deep equality in nested arrays and objects', () => {
expect(deepEquals({x: {y: 1}}, {x: {y: 1}})).to.be.true;
expect(deepEquals({x: {y: 1}}, {x: {}})).to.be.false;
expect(deepEquals({x: {y: 1}}, {x: {y: 0}})).to.be.false;
expect(deepEquals({x: {y: 1}}, {x: {y: 1, z: 2}})).to.be.false;
expect(deepEquals({x: [1, 2, 3]}, {x: [1, 2, 3]})).to.be.true;
expect(deepEquals({x: [1, 2, 3]}, {x: []})).to.be.false;
expect(deepEquals({x: [1, 2, 3]}, {x: [1, 2, 3, 4]})).to.be.false;
expect(deepEquals([1, 2, [3, 4]], [1, 2, [3, 4]])).to.be.true;
expect(deepEquals([1, 2, []], [1, 2, []])).to.be.true;
expect(deepEquals([1, 2, [3, 4]], [1, 2, [3, 4, 5]])).to.be.false;
});
it('should check array order', () => {
expect(deepEquals([1, 2], [2, 1])).to.be.false;
expect(deepEquals([1, 2, [3, 4]], [1, 2, [4, 3]])).to.be.false;
});
it('should not check object key order', () => {
expect(deepEquals({x: 1, y: 2, z: 3}, {y: 2, z: 3, x: 1})).to.be.true;
});
it('should stop diving once depth arg is exceeded', () => {
let depth = 0;
expect(deepEquals(1, 1, depth)).to.be.true;
expect(deepEquals('a', 'a', depth)).to.be.true;
expect(deepEquals([], [], depth)).to.be.false;
expect(deepEquals({}, {}, depth)).to.be.false;
depth = 1;
expect(deepEquals({x: 1}, {x: 1}, depth)).to.be.true;
expect(deepEquals([1, 2], [1, 2], depth)).to.be.true;
expect(deepEquals({x: {y: 1}}, {x: {y: 1}}, depth)).to.be.false;
expect(deepEquals({x: []}, {x: []}, depth)).to.be.false;
});
});
});
| techhtml/amphtml | test/unit/test-json.js | JavaScript | apache-2.0 | 11,089 |
/*!
\file usb_iap_core.h
\brief the header file of IAP driver
\version 2020-07-17, V3.0.0, firmware for GD32F10x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USB_IAP_CORE_H
#define __USB_IAP_CORE_H
#include "usbd_enum.h"
#include "usb_hid.h"
#define USB_DESC_LEN_IAP_REPORT 35U
#define USB_DESC_LEN_IAP_CONFIG_SET 41U
/* special commands with download request */
#define IAP_OPTION_BYTE 0x01U
#define IAP_ERASE 0x02U
#define IAP_DNLOAD 0x03U
#define IAP_LEAVE 0x04U
#define IAP_GETBIN_ADDRESS 0x05U
typedef void (*app_func) (void);
typedef struct
{
uint8_t report_buf[IAP_OUT_PACKET + 1U];
uint8_t option_byte[IAP_IN_PACKET];
/* state machine variables */
uint8_t dev_status[IAP_IN_PACKET];
uint8_t bin_addr[IAP_IN_PACKET];
uint8_t reportID;
uint8_t flag;
uint32_t protocol;
uint32_t idlestate;
uint16_t transfer_times;
uint16_t page_count;
uint16_t lps; /* last packet size */
uint32_t file_length;
uint32_t base_address;
} usbd_iap_handler;
extern usb_desc iap_desc;
extern usb_class iap_class;
/* function declarations */
/* send IAP report */
uint8_t iap_report_send(usb_dev *udev, uint8_t *report, uint16_t len);
#endif /* __USB_IAP_CORE_H */
| geniusgogo/rt-thread | bsp/gd32/libraries/GD32F10x_Firmware_Library/GD32F10x_usbd_library/class/device/iap/Include/usb_iap_core.h | C | apache-2.0 | 2,891 |
# Filesystem Bundle
## Container Format
This section defines a format for encoding a container as a *filesystem bundle* - a set of files organized in a certain way, and containing all the necessary data and metadata for any compliant runtime to perform all standard operations against it.
See also [OS X application bundles](http://en.wikipedia.org/wiki/Bundle_%28OS_X%29) for a similar use of the term *bundle*.
The definition of a bundle is only concerned with how a container, and its configuration data, are stored on a local file system so that it can be consumed by a compliant runtime.
A Standard Container bundle contains all the information needed to load and run a container.
This MUST include the following artifacts:
1. `config.json` : contains configuration data.
This REQUIRED file MUST reside in the root of the bundle directory and MUST be named `config.json`.
See [`config.json`](config.md) for more details.
2. A directory representing the root filesystem of the container.
While the name of this REQUIRED directory may be arbitrary, users should consider using a conventional name, such as `rootfs`.
This directory MUST be referenced from within the `config.json` file.
While these artifacts MUST all be present in a single directory on the local filesystem, that directory itself is not part of the bundle.
In other words, a tar archive of a *bundle* will have these artifacts at the root of the archive, not nested within a top-level directory.
| intelsdi-x/cri-o | vendor/github.com/opencontainers/runtime-spec/bundle.md | Markdown | apache-2.0 | 1,473 |
// Copyright 2012 Google Inc. All Rights Reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at: http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software distrib-
// uted under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES
// OR CONDITIONS OF ANY KIND, either express or implied. See the License for
// specific language governing permissions and limitations under the License.
// Author: [email protected] (Ka-Ping Yee)
function EditCommandTest() {
this.appState_ = new google.maps.MVCObject();
this.mapModel_ = cm.MapModel.newFromMapRoot(
{layers: [{id: 'layer0', type: 'KML'}],
topics: [{id: 'topic0', title: 'Gas', layer_ids: ['layer0']}]});
this.mapModel_.setValues({x: 4, y: 5, z: 6});
this.mapModel_.layers.getAt(0).setValues({x: 4, y: 5, z: 6});
this.mapModel_.topics.getAt(0).setValues({x: 4, y: 5, z: 6});
this.oldValues_ = {x: 1, y: null, z: undefined, map_type: 'ROADMAP'};
this.newValues_ = {x: 7, y: null, z: undefined, map_type: 'SATELLITE'};
}
registerTestSuite(EditCommandTest);
/** Tests execute() when editing a map object. */
EditCommandTest.prototype.testExecuteMap = function() {
var command = new cm.EditCommand(this.oldValues_, this.newValues_);
command.execute(this.appState_, this.mapModel_);
expectEq(7, this.mapModel_.x);
expectEq(null, this.mapModel_.y); // null means set to null
expectEq(6, this.mapModel_.z); // undefined means don't touch
expectEq('SATELLITE', this.appState_.get('map_type'));
};
/** Tests undo() when editing a map object. */
EditCommandTest.prototype.testUndoMap = function() {
var command = new cm.EditCommand(this.oldValues_, this.newValues_);
command.execute(this.appState_, this.mapModel_);
command.undo(this.appState_, this.mapModel_);
expectEq(1, this.mapModel_.x);
expectEq(null, this.mapModel_.y); // null means set to null
expectEq(6, this.mapModel_.z); // undefined means don't touch
expectEq('ROADMAP', this.appState_.get('map_type'));
};
/** Tests execute() when editing a layer object. */
EditCommandTest.prototype.testExecuteLayer = function() {
var command = new cm.EditCommand(this.oldValues_, this.newValues_, 'layer0');
var layer = this.mapModel_.layers.getAt(0);
command.execute(this.appState_, this.mapModel_);
expectEq(7, layer.x);
expectEq(null, layer.y);
expectEq(6, layer.z);
};
/** Tests undo() when editing a layer object. */
EditCommandTest.prototype.testUndoLayer = function() {
var command = new cm.EditCommand(this.oldValues_, this.newValues_, 'layer0');
var layer = this.mapModel_.layers.getAt(0);
command.execute(this.appState_, this.mapModel_);
command.undo(this.appState_, this.mapModel_);
expectEq(1, layer.x);
expectEq(null, layer.y);
expectEq(6, layer.z);
};
/** Tests execute() when editing a topic object. */
EditCommandTest.prototype.testExecuteTopic = function() {
var command = new cm.EditCommand(
this.oldValues_, this.newValues_, null, 'topic0');
var topic = this.mapModel_.topics.getAt(0);
command.execute(this.appState_, this.mapModel_);
expectEq(7, topic.x);
expectEq(null, topic.y);
expectEq(6, topic.z);
};
/** Tests undo() when editing a layer object. */
EditCommandTest.prototype.testUndoTopic = function() {
var command = new cm.EditCommand(
this.oldValues_, this.newValues_, null, 'topic0');
var topic = this.mapModel_.topics.getAt(0);
command.execute(this.appState_, this.mapModel_);
command.undo(this.appState_, this.mapModel_);
expectEq(1, topic.x);
expectEq(null, topic.y);
expectEq(6, topic.z);
};
| pnakka/googlecrisismap | js/edit_command_test.js | JavaScript | apache-2.0 | 3,754 |
/**
* @file application_changes_example.cpp
* @author Mislav Novakovic <[email protected]>
* @brief Example application that uses sysrepo as the configuration datastore. It
* prints the changes made in running data store.
*
* @copyright
* Copyright 2016 Deutsche Telekom AG.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <unistd.h>
#include <iostream>
#include <signal.h>
#include <stdlib.h>
#include <stdio.h>
#include "Session.h"
#define MAX_LEN 100
using namespace std;
volatile int exit_application = 0;
/* Function for printing out values depending on their type. */
void
print_value(S_Val value)
{
cout << value->xpath();
cout << " ";
switch (value->type()) {
case SR_CONTAINER_T:
case SR_CONTAINER_PRESENCE_T:
cout << "(container)" << endl;
break;
case SR_LIST_T:
cout << "(list instance)" << endl;
break;
case SR_STRING_T:
cout << "= " << value->data()->get_string() << endl;;
break;
case SR_BOOL_T:
if (value->data()->get_bool())
cout << "= true" << endl;
else
cout << "= false" << endl;
break;
case SR_ENUM_T:
cout << "= " << value->data()->get_enum() << endl;;
break;
case SR_UINT8_T:
cout << "= " << unsigned(value->data()->get_uint8()) << endl;
break;
case SR_UINT16_T:
cout << "= " << unsigned(value->data()->get_uint16()) << endl;
break;
case SR_UINT32_T:
cout << "= " << unsigned(value->data()->get_uint32()) << endl;
break;
case SR_UINT64_T:
cout << "= " << unsigned(value->data()->get_uint64()) << endl;
break;
case SR_INT8_T:
cout << "= " << value->data()->get_int8() << endl;
break;
case SR_INT16_T:
cout << "= " << value->data()->get_int16() << endl;
break;
case SR_INT32_T:
cout << "= " << value->data()->get_int32() << endl;
break;
case SR_INT64_T:
cout << "= " << value->data()->get_int64() << endl;
break;
case SR_DECIMAL64_T:
cout << "= " << std::to_string(value->data()->get_decimal64()) << endl;
break;
case SR_IDENTITYREF_T:
cout << "= " << value->data()->get_identityref() << endl;
break;
case SR_BITS_T:
cout << "= " << value->data()->get_bits() << endl;
break;
case SR_BINARY_T:
cout << "= " << value->data()->get_binary() << endl;
break;
default:
cout << "(unprintable)" << endl;
}
return;
}
/* Helper function for printing changes given operation, old and new value. */
static void
print_change(S_Change change) {
cout << endl;
switch(change->oper()) {
case SR_OP_CREATED:
if (NULL != change->new_val()) {
cout <<"CREATED: ";
print_value(change->new_val());
}
break;
case SR_OP_DELETED:
if (NULL != change->old_val()) {
cout << "DELETED: ";
print_value(change->old_val());
}
break;
case SR_OP_MODIFIED:
if (NULL != change->old_val() && NULL != change->new_val()) {
cout << "MODIFIED: ";
cout << "old value ";
print_value(change->old_val());
cout << "new value ";
print_value(change->new_val());
}
break;
case SR_OP_MOVED:
if (NULL != change->new_val()) {
cout<<"MOVED: " << change->new_val()->xpath() << " after " << change->old_val()->xpath() << endl;
}
break;
}
}
/* Function to print current configuration state.
* It does so by loading all the items of a session and printing them out. */
static void
print_current_config(S_Session session, const char *module_name)
{
char select_xpath[MAX_LEN];
try {
snprintf(select_xpath, MAX_LEN, "/%s:*//*", module_name);
auto values = session->get_items(&select_xpath[0]);
if (values == NULL)
return;
for(unsigned int i = 0; i < values->val_cnt(); i++)
print_value(values->val(i));
} catch( const std::exception& e ) {
cout << e.what() << endl;
}
}
/* Helper function for printing events. */
const char *ev_to_str(sr_notif_event_t ev) {
switch (ev) {
case SR_EV_VERIFY:
return "verify";
case SR_EV_APPLY:
return "apply";
case SR_EV_ABORT:
default:
return "abort";
}
}
class My_Callback:public Callback {
public:
/* Function to be called for subscribed client of given session whenever configuration changes. */
void module_change(S_Session sess, const char *module_name, sr_notif_event_t event, void *private_ctx)
{
char change_path[MAX_LEN];
try {
cout << "\n\n ========== Notification " << ev_to_str(event) << " =============================================";
if (SR_EV_APPLY == event) {
cout << "\n\n ========== CONFIG HAS CHANGED, CURRENT RUNNING CONFIG: ==========\n" << endl;
print_current_config(sess, module_name);
}
cout << "\n\n ========== CHANGES: =============================================\n" << endl;
snprintf(change_path, MAX_LEN, "/%s:*", module_name);
S_Subscribe subscribe(new Subscribe(sess));
auto it = subscribe->get_changes_iter(&change_path[0]);
while (auto change = subscribe->get_change_next(it)) {
print_change(change);
}
cout << "\n\n ========== END OF CHANGES =======================================\n" << endl;
} catch( const std::exception& e ) {
cout << e.what() << endl;
}
}
};
static void
sigint_handler(int signum)
{
exit_application = 1;
}
/* Notable difference between c implementation is using exception mechanism for open handling unexpected events.
* Here it is useful because `Conenction`, `Session` and `Subscribe` could throw an exception. */
int
main(int argc, char **argv)
{
const char *module_name = "ietf-interfaces";
try {
if (argc > 1) {
module_name = argv[1];
} else {
cout << "\nYou can pass the module name to be subscribed as the first argument" << endl;
}
cout << "Application will watch for changes in " << module_name << endl;
/* connect to sysrepo */
S_Connection conn(new Connection("example_application"));
/* start session */
S_Session sess(new Session(conn));
/* subscribe for changes in running config */
S_Subscribe subscribe(new Subscribe(sess));
S_Callback cb(new My_Callback());
subscribe->module_change_subscribe(module_name, cb);
/* read startup config */
cout << "\n\n ========== READING STARTUP CONFIG: ==========\n" << endl;
print_current_config(sess, module_name);
cout << "\n\n ========== STARTUP CONFIG APPLIED AS RUNNING ==========\n" << endl;
/* loop until ctrl-c is pressed / SIGINT is received */
signal(SIGINT, sigint_handler);
while (!exit_application) {
sleep(1000); /* or do some more useful work... */
}
cout << "Application exit requested, exiting." << endl;
} catch( const std::exception& e ) {
cout << e.what() << endl;
return -1;
}
return 0;
}
| rastislavszabo/sysrepo | swig/cpp/examples/cpp_application_changes_example.cpp | C++ | apache-2.0 | 7,869 |
"use strict";
const fs = require(`fs-extra`);
const got = require(`got`);
const {
createContentDigest
} = require(`gatsby-core-utils`);
const path = require(`path`);
const {
isWebUri
} = require(`valid-url`);
const Queue = require(`better-queue`);
const readChunk = require(`read-chunk`);
const fileType = require(`file-type`);
const {
createProgress
} = require(`./utils`);
const {
createFileNode
} = require(`./create-file-node`);
const {
getRemoteFileExtension,
getRemoteFileName,
createFilePath
} = require(`./utils`);
const cacheId = url => `create-remote-file-node-${url}`;
let bar; // Keep track of the total number of jobs we push in the queue
let totalJobs = 0;
/********************
* Type Definitions *
********************/
/**
* @typedef {GatsbyCache}
* @see gatsby/packages/gatsby/utils/cache.js
*/
/**
* @typedef {Reporter}
* @see gatsby/packages/gatsby-cli/lib/reporter.js
*/
/**
* @typedef {Auth}
* @type {Object}
* @property {String} htaccess_pass
* @property {String} htaccess_user
*/
/**
* @typedef {CreateRemoteFileNodePayload}
* @typedef {Object}
* @description Create Remote File Node Payload
*
* @param {String} options.url
* @param {GatsbyCache} options.cache
* @param {Function} options.createNode
* @param {Function} options.getCache
* @param {Auth} [options.auth]
* @param {Reporter} [options.reporter]
*/
const STALL_RETRY_LIMIT = 3;
const STALL_TIMEOUT = 30000;
const CONNECTION_RETRY_LIMIT = 5;
const CONNECTION_TIMEOUT = 30000;
/********************
* Queue Management *
********************/
/**
* Queue
* Use the task's url as the id
* When pushing a task with a similar id, prefer the original task
* as it's already in the processing cache
*/
const queue = new Queue(pushToQueue, {
id: `url`,
merge: (old, _, cb) => cb(old),
concurrent: process.env.GATSBY_CONCURRENT_DOWNLOAD || 200
}); // when the queue is empty we stop the progressbar
queue.on(`drain`, () => {
if (bar) {
bar.done();
}
totalJobs = 0;
});
/**
* @callback {Queue~queueCallback}
* @param {*} error
* @param {*} result
*/
/**
* pushToQueue
* --
* Handle tasks that are pushed in to the Queue
*
*
* @param {CreateRemoteFileNodePayload} task
* @param {Queue~queueCallback} cb
* @return {Promise<null>}
*/
async function pushToQueue(task, cb) {
try {
const node = await processRemoteNode(task);
return cb(null, node);
} catch (e) {
return cb(e);
}
}
/******************
* Core Functions *
******************/
/**
* requestRemoteNode
* --
* Download the requested file
*
* @param {String} url
* @param {Headers} headers
* @param {String} tmpFilename
* @param {Object} httpOpts
* @param {number} attempt
* @return {Promise<Object>} Resolves with the [http Result Object]{@link https://nodejs.org/api/http.html#http_class_http_serverresponse}
*/
const requestRemoteNode = (url, headers, tmpFilename, httpOpts, attempt = 1) => new Promise((resolve, reject) => {
let timeout; // Called if we stall for 30s without receiving any data
const handleTimeout = async () => {
fsWriteStream.close();
fs.removeSync(tmpFilename);
if (attempt < STALL_RETRY_LIMIT) {
// Retry by calling ourself recursively
resolve(requestRemoteNode(url, headers, tmpFilename, httpOpts, attempt + 1));
} else {
reject(`Failed to download ${url} after ${STALL_RETRY_LIMIT} attempts`);
}
};
const resetTimeout = () => {
if (timeout) {
clearTimeout(timeout);
}
timeout = setTimeout(handleTimeout, STALL_TIMEOUT);
};
const responseStream = got.stream(url, {
headers,
timeout: CONNECTION_TIMEOUT,
retries: CONNECTION_RETRY_LIMIT,
...httpOpts
});
const fsWriteStream = fs.createWriteStream(tmpFilename);
responseStream.pipe(fsWriteStream); // If there's a 400/500 response or other error.
responseStream.on(`error`, error => {
if (timeout) {
clearTimeout(timeout);
}
fs.removeSync(tmpFilename);
reject(error);
});
fsWriteStream.on(`error`, error => {
if (timeout) {
clearTimeout(timeout);
}
reject(error);
});
responseStream.on(`response`, response => {
resetTimeout();
fsWriteStream.on(`finish`, () => {
if (timeout) {
clearTimeout(timeout);
}
resolve(response);
});
});
});
/**
* processRemoteNode
* --
* Request the remote file and return the fileNode
*
* @param {CreateRemoteFileNodePayload} options
* @return {Promise<Object>} Resolves with the fileNode
*/
async function processRemoteNode({
url,
cache,
createNode,
parentNodeId,
auth = {},
httpHeaders = {},
createNodeId,
ext,
name
}) {
const pluginCacheDir = cache.directory; // See if there's response headers for this url
// from a previous request.
const cachedHeaders = await cache.get(cacheId(url));
const headers = { ...httpHeaders
};
if (cachedHeaders && cachedHeaders.etag) {
headers[`If-None-Match`] = cachedHeaders.etag;
} // Add htaccess authentication if passed in. This isn't particularly
// extensible. We should define a proper API that we validate.
const httpOpts = {};
if (auth && (auth.htaccess_pass || auth.htaccess_user)) {
httpOpts.auth = `${auth.htaccess_user}:${auth.htaccess_pass}`;
} // Create the temp and permanent file names for the url.
const digest = createContentDigest(url);
if (!name) {
name = getRemoteFileName(url);
}
if (!ext) {
ext = getRemoteFileExtension(url);
}
const tmpFilename = createFilePath(pluginCacheDir, `tmp-${digest}`, ext); // Fetch the file.
const response = await requestRemoteNode(url, headers, tmpFilename, httpOpts);
if (response.statusCode == 200) {
// Save the response headers for future requests.
await cache.set(cacheId(url), response.headers);
} // If the user did not provide an extension and we couldn't get one from remote file, try and guess one
if (ext === ``) {
const buffer = readChunk.sync(tmpFilename, 0, fileType.minimumBytes);
const filetype = fileType(buffer);
if (filetype) {
ext = `.${filetype.ext}`;
}
}
const filename = createFilePath(path.join(pluginCacheDir, digest), name, ext); // If the status code is 200, move the piped temp file to the real name.
if (response.statusCode === 200) {
await fs.move(tmpFilename, filename, {
overwrite: true
}); // Else if 304, remove the empty response.
} else {
await fs.remove(tmpFilename);
} // Create the file node.
const fileNode = await createFileNode(filename, createNodeId, {});
fileNode.internal.description = `File "${url}"`;
fileNode.url = url;
fileNode.parent = parentNodeId; // Override the default plugin as gatsby-source-filesystem needs to
// be the owner of File nodes or there'll be conflicts if any other
// File nodes are created through normal usages of
// gatsby-source-filesystem.
await createNode(fileNode, {
name: `gatsby-source-filesystem`
});
return fileNode;
}
/**
* Index of promises resolving to File node from remote url
*/
const processingCache = {};
/**
* pushTask
* --
* pushes a task in to the Queue and the processing cache
*
* Promisfy a task in queue
* @param {CreateRemoteFileNodePayload} task
* @return {Promise<Object>}
*/
const pushTask = task => new Promise((resolve, reject) => {
queue.push(task).on(`finish`, task => {
resolve(task);
}).on(`failed`, err => {
reject(`failed to process ${task.url}\n${err}`);
});
});
/***************
* Entry Point *
***************/
/**
* createRemoteFileNode
* --
*
* Download a remote file
* First checks cache to ensure duplicate requests aren't processed
* Then pushes to a queue
*
* @param {CreateRemoteFileNodePayload} options
* @return {Promise<Object>} Returns the created node
*/
module.exports = ({
url,
cache,
createNode,
getCache,
parentNodeId = null,
auth = {},
httpHeaders = {},
createNodeId,
ext = null,
name = null,
reporter
}) => {
// validation of the input
// without this it's notoriously easy to pass in the wrong `createNodeId`
// see gatsbyjs/gatsby#6643
if (typeof createNodeId !== `function`) {
throw new Error(`createNodeId must be a function, was ${typeof createNodeId}`);
}
if (typeof createNode !== `function`) {
throw new Error(`createNode must be a function, was ${typeof createNode}`);
}
if (typeof getCache === `function`) {
// use cache of this plugin and not cache of function caller
cache = getCache(`gatsby-source-filesystem`);
}
if (typeof cache !== `object`) {
throw new Error(`Neither "cache" or "getCache" was passed. getCache must be function that return Gatsby cache, "cache" must be the Gatsby cache, was ${typeof cache}`);
} // Check if we already requested node for this remote file
// and return stored promise if we did.
if (processingCache[url]) {
return processingCache[url];
}
if (!url || isWebUri(url) === undefined) {
return Promise.reject(`wrong url: ${url}`);
}
if (totalJobs === 0) {
bar = createProgress(`Downloading remote files`, reporter);
bar.start();
}
totalJobs += 1;
bar.total = totalJobs;
const fileDownloadPromise = pushTask({
url,
cache,
createNode,
parentNodeId,
createNodeId,
auth,
httpHeaders,
ext,
name
});
processingCache[url] = fileDownloadPromise.then(node => {
bar.tick();
return node;
});
return processingCache[url];
}; | BigBoss424/portfolio | v8/development/node_modules/gatsby-source-filesystem/create-remote-file-node.js | JavaScript | apache-2.0 | 9,568 |
import {Component, LifecycleEvent, View, ViewEncapsulation, Attribute} from 'angular2/angular2';
import {CONST} from 'angular2/src/core/facade/lang';
import {isPresent, isBlank} from 'angular2/src/core/facade/lang';
import {Math} from 'angular2/src/core/facade/math';
/** Different display / behavior modes for progress-linear. */
@CONST()
class ProgressMode {
@CONST() static DETERMINATE = 'determinate';
@CONST() static INDETERMINATE = 'indeterminate';
@CONST() static BUFFER = 'buffer';
@CONST() static QUERY = 'query';
}
@Component({
selector: 'md-progress-linear',
lifecycle: [LifecycleEvent.OnChanges],
properties: ['value', 'bufferValue'],
host: {
'role': 'progressbar',
'aria-valuemin': '0',
'aria-valuemax': '100',
'[attr.aria-valuenow]': 'value'
}
})
@View({
templateUrl: 'package:angular2_material/src/components/progress-linear/progress_linear.html',
directives: [],
encapsulation: ViewEncapsulation.NONE
})
export class MdProgressLinear {
/** Value for the primary bar. */
value_: number;
/** Value for the secondary bar. */
bufferValue: number;
/** The render mode for the progress bar. */
mode: string;
/** CSS `transform` property applied to the primary bar. */
primaryBarTransform: string;
/** CSS `transform` property applied to the secondary bar. */
secondaryBarTransform: string;
constructor(@Attribute('mode') mode: string) {
this.primaryBarTransform = '';
this.secondaryBarTransform = '';
this.mode = isPresent(mode) ? mode : ProgressMode.DETERMINATE;
}
get value() {
return this.value_;
}
set value(v) {
if (isPresent(v)) {
this.value_ = MdProgressLinear.clamp(v);
}
}
onChanges(_) {
// If the mode does not use a value, or if there is no value, do nothing.
if (this.mode == ProgressMode.QUERY || this.mode == ProgressMode.INDETERMINATE ||
isBlank(this.value)) {
return;
}
this.primaryBarTransform = this.transformForValue(this.value);
// The bufferValue is only used in buffer mode.
if (this.mode == ProgressMode.BUFFER) {
this.secondaryBarTransform = this.transformForValue(this.bufferValue);
}
}
/** Gets the CSS `transform` property for a progress bar based on the given value (0 - 100). */
transformForValue(value) {
// TODO(jelbourn): test perf gain of caching these, since there are only 101 values.
let scale = value / 100;
let translateX = (value - 100) / 2;
return `translateX(${translateX}%) scale(${scale}, 1)`;
}
/** Clamps a value to be between 0 and 100. */
static clamp(v) {
return Math.max(0, Math.min(100, v));
}
}
| pkdevbox/angular | modules/angular2_material/src/components/progress-linear/progress_linear.ts | TypeScript | apache-2.0 | 2,658 |
// DelayedFluidSimulator.cpp
// Interfaces to the cDelayedFluidSimulator class representing a fluid simulator that has a configurable delay
// before simulating a block. Each tick it takes a consecutive delay "slot" and simulates only blocks in that slot.
#include "Globals.h"
#include "DelayedFluidSimulator.h"
#include "../World.h"
#include "../Chunk.h"
////////////////////////////////////////////////////////////////////////////////
// cDelayedFluidSimulatorChunkData::cSlot
bool cDelayedFluidSimulatorChunkData::cSlot::Add(int a_RelX, int a_RelY, int a_RelZ)
{
ASSERT(a_RelZ >= 0);
ASSERT(a_RelZ < static_cast<int>(ARRAYCOUNT(m_Blocks)));
auto & Blocks = m_Blocks[a_RelZ];
const auto Index = cChunkDef::MakeIndex(a_RelX, a_RelY, a_RelZ);
for (const auto & Block : Blocks)
{
if (Block.Data == Index)
{
// Already present
return false;
}
} // for itr - Blocks[]
Blocks.emplace_back(a_RelX, a_RelY, a_RelZ, Index);
return true;
}
////////////////////////////////////////////////////////////////////////////////
// cDelayedFluidSimulatorChunkData:
cDelayedFluidSimulatorChunkData::cDelayedFluidSimulatorChunkData(int a_TickDelay) :
m_Slots(new cSlot[ToUnsigned(a_TickDelay)])
{
}
cDelayedFluidSimulatorChunkData::~cDelayedFluidSimulatorChunkData()
{
delete[] m_Slots;
m_Slots = nullptr;
}
////////////////////////////////////////////////////////////////////////////////
// cDelayedFluidSimulator:
cDelayedFluidSimulator::cDelayedFluidSimulator(cWorld & a_World, BLOCKTYPE a_Fluid, BLOCKTYPE a_StationaryFluid, int a_TickDelay) :
Super(a_World, a_Fluid, a_StationaryFluid),
m_TickDelay(a_TickDelay),
m_AddSlotNum(a_TickDelay - 1),
m_SimSlotNum(0),
m_TotalBlocks(0)
{
}
void cDelayedFluidSimulator::Simulate(float a_Dt)
{
m_AddSlotNum = m_SimSlotNum;
m_SimSlotNum += 1;
if (m_SimSlotNum >= m_TickDelay)
{
m_SimSlotNum = 0;
}
}
void cDelayedFluidSimulator::SimulateChunk(std::chrono::milliseconds a_Dt, int a_ChunkX, int a_ChunkZ, cChunk * a_Chunk)
{
auto ChunkDataRaw = (m_FluidBlock == E_BLOCK_WATER) ? a_Chunk->GetWaterSimulatorData() : a_Chunk->GetLavaSimulatorData();
cDelayedFluidSimulatorChunkData * ChunkData = static_cast<cDelayedFluidSimulatorChunkData *>(ChunkDataRaw);
cDelayedFluidSimulatorChunkData::cSlot & Slot = ChunkData->m_Slots[m_SimSlotNum];
// Simulate all the blocks in the scheduled slot:
for (size_t i = 0; i < ARRAYCOUNT(Slot.m_Blocks); i++)
{
auto & Blocks = Slot.m_Blocks[i];
if (Blocks.empty())
{
continue;
}
for (const auto & Block : Blocks)
{
SimulateBlock(a_Chunk, Block.x, Block.y, Block.z);
}
m_TotalBlocks -= static_cast<int>(Blocks.size());
Blocks.clear();
}
}
void cDelayedFluidSimulator::AddBlock(cChunk & a_Chunk, Vector3i a_Position, BLOCKTYPE a_Block)
{
if ((a_Block != m_FluidBlock) && (a_Block != m_StationaryFluidBlock))
{
return;
}
auto ChunkDataRaw = (m_FluidBlock == E_BLOCK_WATER) ? a_Chunk.GetWaterSimulatorData() : a_Chunk.GetLavaSimulatorData();
cDelayedFluidSimulatorChunkData * ChunkData = static_cast<cDelayedFluidSimulatorChunkData *>(ChunkDataRaw);
cDelayedFluidSimulatorChunkData::cSlot & Slot = ChunkData->m_Slots[m_AddSlotNum];
// Add, if not already present:
if (!Slot.Add(a_Position.x, a_Position.y, a_Position.z))
{
return;
}
++m_TotalBlocks;
}
void cDelayedFluidSimulator::WakeUp(cChunk & a_Chunk, Vector3i a_Position, BLOCKTYPE a_Block)
{
if (!cChunkDef::IsValidHeight(a_Position.y))
{
// Not inside the world (may happen when rclk with a full bucket - the client sends Y = -1)
return;
}
AddBlock(a_Chunk, a_Position, a_Block);
}
| mc-server/MCServer | src/Simulator/DelayedFluidSimulator.cpp | C++ | apache-2.0 | 3,636 |
# Copyright 2017 Google Inc. All Rights Reserved.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ==============================================================================
"""Test for dragnn.python.dragnn_model_saver_lib."""
from __future__ import absolute_import
from __future__ import division
from __future__ import print_function
import os
import tensorflow as tf
from google.protobuf import text_format
from tensorflow.python.framework import test_util
from tensorflow.python.platform import googletest
from dragnn.protos import export_pb2
from dragnn.protos import spec_pb2
from dragnn.python import dragnn_model_saver_lib
from syntaxnet import sentence_pb2
from syntaxnet import test_flags
_DUMMY_TEST_SENTENCE = """
token {
word: "sentence" start: 0 end: 7 break_level: NO_BREAK
}
token {
word: "0" start: 9 end: 9 break_level: SPACE_BREAK
}
token {
word: "." start: 10 end: 10 break_level: NO_BREAK
}
"""
class DragnnModelSaverLibTest(test_util.TensorFlowTestCase):
def LoadSpec(self, spec_path):
master_spec = spec_pb2.MasterSpec()
root_dir = os.path.join(test_flags.source_root(),
'dragnn/python')
with open(os.path.join(root_dir, 'testdata', spec_path), 'r') as fin:
text_format.Parse(fin.read().replace('TOPDIR', root_dir), master_spec)
return master_spec
def CreateLocalSpec(self, spec_path):
master_spec = self.LoadSpec(spec_path)
master_spec_name = os.path.basename(spec_path)
outfile = os.path.join(test_flags.temp_dir(), master_spec_name)
fout = open(outfile, 'w')
fout.write(text_format.MessageToString(master_spec))
return outfile
def ValidateAssetExistence(self, master_spec, export_path):
asset_path = os.path.join(export_path, 'assets.extra')
# The master spec should exist.
expected_path = os.path.join(asset_path, 'master_spec')
tf.logging.info('Validating existence of %s' % expected_path)
self.assertTrue(os.path.isfile(expected_path))
# For every part in every resource in every component, the resource should
# exist at [export_path]/assets.extra/[component file path]
path_list = []
for component_spec in master_spec.component:
for resource_spec in component_spec.resource:
for part in resource_spec.part:
expected_path = os.path.join(asset_path,
part.file_pattern.strip(os.path.sep))
tf.logging.info('Validating existence of %s' % expected_path)
self.assertTrue(os.path.isfile(expected_path))
path_list.append(expected_path)
# Return a set of all unique paths.
return set(path_list)
def GetHookNodeNames(self, master_spec):
"""Returns hook node names to use in tests.
Args:
master_spec: MasterSpec proto from which to infer hook node names.
Returns:
Tuple of (averaged hook node name, non-averaged hook node name, cell
subgraph hook node name).
Raises:
ValueError: If hook nodes cannot be inferred from the |master_spec|.
"""
# Find an op name we can use for testing runtime hooks. Assume that at
# least one component has a fixed feature (else what is the model doing?).
component_name = None
for component_spec in master_spec.component:
if component_spec.fixed_feature:
component_name = component_spec.name
break
if not component_name:
raise ValueError('Cannot infer hook node names')
non_averaged_hook_name = '{}/fixed_embedding_matrix_0/trimmed'.format(
component_name)
averaged_hook_name = '{}/ExponentialMovingAverage'.format(
non_averaged_hook_name)
cell_subgraph_hook_name = '{}/EXPORT/CellSubgraphSpec'.format(
component_name)
return averaged_hook_name, non_averaged_hook_name, cell_subgraph_hook_name
def testModelExport(self):
# Get the master spec and params for this graph.
master_spec = self.LoadSpec('ud-hungarian.master-spec')
params_path = os.path.join(
test_flags.source_root(),
'dragnn/python/testdata'
'/ud-hungarian.params')
# Export the graph via SavedModel. (Here, we maintain a handle to the graph
# for comparison, but that's usually not necessary.)
export_path = os.path.join(test_flags.temp_dir(), 'export')
dragnn_model_saver_lib.clean_output_paths(export_path)
saver_graph = tf.Graph()
shortened_to_original = dragnn_model_saver_lib.shorten_resource_paths(
master_spec)
dragnn_model_saver_lib.export_master_spec(master_spec, saver_graph)
dragnn_model_saver_lib.export_to_graph(
master_spec,
params_path,
export_path,
saver_graph,
export_moving_averages=False,
build_runtime_graph=False)
# Export the assets as well.
dragnn_model_saver_lib.export_assets(master_spec, shortened_to_original,
export_path)
# Validate that the assets are all in the exported directory.
path_set = self.ValidateAssetExistence(master_spec, export_path)
# This master-spec has 4 unique assets. If there are more, we have not
# uniquified the assets properly.
self.assertEqual(len(path_set), 4)
# Restore the graph from the checkpoint into a new Graph object.
restored_graph = tf.Graph()
restoration_config = tf.ConfigProto(
log_device_placement=False,
intra_op_parallelism_threads=10,
inter_op_parallelism_threads=10)
with tf.Session(graph=restored_graph, config=restoration_config) as sess:
tf.saved_model.loader.load(sess, [tf.saved_model.tag_constants.SERVING],
export_path)
averaged_hook_name, non_averaged_hook_name, _ = self.GetHookNodeNames(
master_spec)
# Check that the averaged runtime hook node does not exist.
with self.assertRaises(KeyError):
restored_graph.get_operation_by_name(averaged_hook_name)
# Check that the non-averaged version also does not exist.
with self.assertRaises(KeyError):
restored_graph.get_operation_by_name(non_averaged_hook_name)
def testModelExportWithAveragesAndHooks(self):
# Get the master spec and params for this graph.
master_spec = self.LoadSpec('ud-hungarian.master-spec')
params_path = os.path.join(
test_flags.source_root(),
'dragnn/python/testdata'
'/ud-hungarian.params')
# Export the graph via SavedModel. (Here, we maintain a handle to the graph
# for comparison, but that's usually not necessary.) Note that the export
# path must not already exist.
export_path = os.path.join(test_flags.temp_dir(), 'export2')
dragnn_model_saver_lib.clean_output_paths(export_path)
saver_graph = tf.Graph()
shortened_to_original = dragnn_model_saver_lib.shorten_resource_paths(
master_spec)
dragnn_model_saver_lib.export_master_spec(master_spec, saver_graph)
dragnn_model_saver_lib.export_to_graph(
master_spec,
params_path,
export_path,
saver_graph,
export_moving_averages=True,
build_runtime_graph=True)
# Export the assets as well.
dragnn_model_saver_lib.export_assets(master_spec, shortened_to_original,
export_path)
# Validate that the assets are all in the exported directory.
path_set = self.ValidateAssetExistence(master_spec, export_path)
# This master-spec has 4 unique assets. If there are more, we have not
# uniquified the assets properly.
self.assertEqual(len(path_set), 4)
# Restore the graph from the checkpoint into a new Graph object.
restored_graph = tf.Graph()
restoration_config = tf.ConfigProto(
log_device_placement=False,
intra_op_parallelism_threads=10,
inter_op_parallelism_threads=10)
with tf.Session(graph=restored_graph, config=restoration_config) as sess:
tf.saved_model.loader.load(sess, [tf.saved_model.tag_constants.SERVING],
export_path)
averaged_hook_name, non_averaged_hook_name, cell_subgraph_hook_name = (
self.GetHookNodeNames(master_spec))
# Check that an averaged runtime hook node exists.
restored_graph.get_operation_by_name(averaged_hook_name)
# Check that the non-averaged version does not exist.
with self.assertRaises(KeyError):
restored_graph.get_operation_by_name(non_averaged_hook_name)
# Load the cell subgraph.
cell_subgraph_bytes = restored_graph.get_tensor_by_name(
cell_subgraph_hook_name + ':0')
cell_subgraph_bytes = cell_subgraph_bytes.eval(
feed_dict={'annotation/ComputeSession/InputBatch:0': []})
cell_subgraph_spec = export_pb2.CellSubgraphSpec()
cell_subgraph_spec.ParseFromString(cell_subgraph_bytes)
tf.logging.info('cell_subgraph_spec = %s', cell_subgraph_spec)
# Sanity check inputs.
for cell_input in cell_subgraph_spec.input:
self.assertGreater(len(cell_input.name), 0)
self.assertGreater(len(cell_input.tensor), 0)
self.assertNotEqual(cell_input.type,
export_pb2.CellSubgraphSpec.Input.TYPE_UNKNOWN)
restored_graph.get_tensor_by_name(cell_input.tensor) # shouldn't raise
# Sanity check outputs.
for cell_output in cell_subgraph_spec.output:
self.assertGreater(len(cell_output.name), 0)
self.assertGreater(len(cell_output.tensor), 0)
restored_graph.get_tensor_by_name(cell_output.tensor) # shouldn't raise
# GetHookNames() finds a component with a fixed feature, so at least the
# first feature ID should exist.
self.assertTrue(
any(cell_input.name == 'fixed_channel_0_index_0_ids'
for cell_input in cell_subgraph_spec.input))
# Most dynamic components produce a logits layer.
self.assertTrue(
any(cell_output.name == 'logits'
for cell_output in cell_subgraph_spec.output))
def testModelExportProducesRunnableModel(self):
# Get the master spec and params for this graph.
master_spec = self.LoadSpec('ud-hungarian.master-spec')
params_path = os.path.join(
test_flags.source_root(),
'dragnn/python/testdata'
'/ud-hungarian.params')
# Export the graph via SavedModel. (Here, we maintain a handle to the graph
# for comparison, but that's usually not necessary.)
export_path = os.path.join(test_flags.temp_dir(), 'export')
dragnn_model_saver_lib.clean_output_paths(export_path)
saver_graph = tf.Graph()
shortened_to_original = dragnn_model_saver_lib.shorten_resource_paths(
master_spec)
dragnn_model_saver_lib.export_master_spec(master_spec, saver_graph)
dragnn_model_saver_lib.export_to_graph(
master_spec,
params_path,
export_path,
saver_graph,
export_moving_averages=False,
build_runtime_graph=False)
# Export the assets as well.
dragnn_model_saver_lib.export_assets(master_spec, shortened_to_original,
export_path)
# Restore the graph from the checkpoint into a new Graph object.
restored_graph = tf.Graph()
restoration_config = tf.ConfigProto(
log_device_placement=False,
intra_op_parallelism_threads=10,
inter_op_parallelism_threads=10)
with tf.Session(graph=restored_graph, config=restoration_config) as sess:
tf.saved_model.loader.load(sess, [tf.saved_model.tag_constants.SERVING],
export_path)
test_doc = sentence_pb2.Sentence()
text_format.Parse(_DUMMY_TEST_SENTENCE, test_doc)
test_reader_string = test_doc.SerializeToString()
test_inputs = [test_reader_string]
tf_out = sess.run(
'annotation/annotations:0',
feed_dict={'annotation/ComputeSession/InputBatch:0': test_inputs})
# We don't care about accuracy, only that the run sessions don't crash.
del tf_out
if __name__ == '__main__':
googletest.main()
| alexgorban/models | research/syntaxnet/dragnn/python/dragnn_model_saver_lib_test.py | Python | apache-2.0 | 12,583 |
/*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package org.apache.camel.processor;
import java.io.Closeable;
import java.io.IOException;
import java.util.ArrayList;
import java.util.Collection;
import java.util.Collections;
import java.util.Iterator;
import java.util.List;
import java.util.concurrent.ExecutorService;
import org.apache.camel.AggregationStrategy;
import org.apache.camel.AsyncCallback;
import org.apache.camel.AsyncProcessor;
import org.apache.camel.CamelContext;
import org.apache.camel.Exchange;
import org.apache.camel.ExchangePropertyKey;
import org.apache.camel.Expression;
import org.apache.camel.ExtendedExchange;
import org.apache.camel.Message;
import org.apache.camel.Processor;
import org.apache.camel.Route;
import org.apache.camel.RuntimeCamelException;
import org.apache.camel.Traceable;
import org.apache.camel.processor.aggregate.ShareUnitOfWorkAggregationStrategy;
import org.apache.camel.processor.aggregate.UseOriginalAggregationStrategy;
import org.apache.camel.support.ExchangeHelper;
import org.apache.camel.support.ObjectHelper;
import org.apache.camel.util.IOHelper;
import org.apache.camel.util.StringHelper;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
import static org.apache.camel.util.ObjectHelper.notNull;
/**
* Implements a dynamic <a href="http://camel.apache.org/splitter.html">Splitter</a> pattern where an expression is
* evaluated to iterate through each of the parts of a message and then each part is then send to some endpoint.
*/
public class Splitter extends MulticastProcessor implements AsyncProcessor, Traceable {
private static final Logger LOG = LoggerFactory.getLogger(Splitter.class);
private static final String IGNORE_DELIMITER_MARKER = "false";
private final Expression expression;
private final String delimiter;
public Splitter(CamelContext camelContext, Route route, Expression expression, Processor destination,
AggregationStrategy aggregationStrategy, boolean parallelProcessing,
ExecutorService executorService, boolean shutdownExecutorService, boolean streaming,
boolean stopOnException, long timeout, Processor onPrepare,
boolean useSubUnitOfWork, boolean parallelAggregate) {
this(camelContext, route, expression, destination, aggregationStrategy, parallelProcessing, executorService,
shutdownExecutorService, streaming, stopOnException, timeout,
onPrepare, useSubUnitOfWork, parallelAggregate, ",");
}
public Splitter(CamelContext camelContext, Route route, Expression expression, Processor destination,
AggregationStrategy aggregationStrategy, boolean parallelProcessing,
ExecutorService executorService, boolean shutdownExecutorService, boolean streaming,
boolean stopOnException, long timeout, Processor onPrepare,
boolean useSubUnitOfWork, boolean parallelAggregate, String delimiter) {
super(camelContext, route, Collections.singleton(destination), aggregationStrategy, parallelProcessing, executorService,
shutdownExecutorService, streaming, stopOnException,
timeout, onPrepare, useSubUnitOfWork, parallelAggregate);
this.expression = expression;
StringHelper.notEmpty(delimiter, "delimiter");
this.delimiter = delimiter;
notNull(expression, "expression");
notNull(destination, "destination");
}
@Override
public String getTraceLabel() {
return "split[" + expression + "]";
}
@Override
protected void doBuild() throws Exception {
super.doBuild();
// eager load classes
Object dummy = new SplitterIterable();
LOG.trace("Loaded {}", dummy.getClass().getName());
}
@Override
protected void doInit() throws Exception {
super.doInit();
expression.init(getCamelContext());
}
@Override
public boolean process(Exchange exchange, final AsyncCallback callback) {
AggregationStrategy strategy = getAggregationStrategy();
// set original exchange if not already pre-configured
if (strategy instanceof UseOriginalAggregationStrategy) {
// need to create a new private instance, as we can also have concurrency issue so we cannot store state
UseOriginalAggregationStrategy original = (UseOriginalAggregationStrategy) strategy;
AggregationStrategy clone = original.newInstance(exchange);
if (isShareUnitOfWork()) {
clone = new ShareUnitOfWorkAggregationStrategy(clone);
}
setAggregationStrategyOnExchange(exchange, clone);
}
// if no custom aggregation strategy is being used then fallback to keep the original
// and propagate exceptions which is done by a per exchange specific aggregation strategy
// to ensure it supports async routing
if (strategy == null) {
AggregationStrategy original = new UseOriginalAggregationStrategy(exchange, true);
if (isShareUnitOfWork()) {
original = new ShareUnitOfWorkAggregationStrategy(original);
}
setAggregationStrategyOnExchange(exchange, original);
}
return super.process(exchange, callback);
}
@Override
protected Iterable<ProcessorExchangePair> createProcessorExchangePairs(Exchange exchange)
throws Exception {
Object value = expression.evaluate(exchange, Object.class);
if (exchange.getException() != null) {
// force any exceptions occurred during evaluation to be thrown
throw exchange.getException();
}
Iterable<ProcessorExchangePair> answer = isStreaming()
? createProcessorExchangePairsIterable(exchange, value)
: createProcessorExchangePairsList(exchange, value);
if (exchange.getException() != null) {
// force any exceptions occurred during creation of exchange paris to be thrown
// before returning the answer;
throw exchange.getException();
}
return answer;
}
private Iterable<ProcessorExchangePair> createProcessorExchangePairsIterable(final Exchange exchange, final Object value) {
return new SplitterIterable(exchange, value);
}
private final class SplitterIterable implements Iterable<ProcessorExchangePair>, Closeable {
// create a copy which we use as master to copy during splitting
// this avoids any side effect reflected upon the incoming exchange
final Object value;
final Iterator<?> iterator;
private Exchange copy;
private final Route route;
private final Exchange original;
private SplitterIterable() {
// used for eager classloading
value = null;
iterator = null;
copy = null;
route = null;
original = null;
// for loading classes from iterator
Object dummy = iterator();
LOG.trace("Loaded {}", dummy.getClass().getName());
}
private SplitterIterable(Exchange exchange, Object value) {
this.original = exchange;
this.value = value;
if (IGNORE_DELIMITER_MARKER.equalsIgnoreCase(delimiter)) {
this.iterator = ObjectHelper.createIterator(value, null);
} else {
this.iterator = ObjectHelper.createIterator(value, delimiter);
}
this.copy = copyAndPrepareSubExchange(exchange, true);
this.route = ExchangeHelper.getRoute(exchange);
}
@Override
public Iterator<ProcessorExchangePair> iterator() {
return new Iterator<ProcessorExchangePair>() {
private final Processor processor = getProcessors().iterator().next();
private int index;
private boolean closed;
public boolean hasNext() {
if (closed) {
return false;
}
boolean answer = iterator.hasNext();
if (!answer) {
// we are now closed
closed = true;
// nothing more so we need to close the expression value in case it needs to be
try {
close();
} catch (IOException e) {
throw new RuntimeCamelException("Scanner aborted because of an IOException!", e);
}
}
return answer;
}
public ProcessorExchangePair next() {
Object part = iterator.next();
if (part != null) {
// create a correlated copy as the new exchange to be routed in the splitter from the copy
// and do not share the unit of work
Exchange newExchange = processorExchangeFactory.createCorrelatedCopy(copy, false);
newExchange.adapt(ExtendedExchange.class).setTransacted(original.isTransacted());
// If the splitter has an aggregation strategy
// then the StreamCache created by the child routes must not be
// closed by the unit of work of the child route, but by the unit of
// work of the parent route or grand parent route or grand grand parent route... (in case of nesting).
// Therefore, set the unit of work of the parent route as stream cache unit of work, if not already set.
if (newExchange.getProperty(ExchangePropertyKey.STREAM_CACHE_UNIT_OF_WORK) == null) {
newExchange.setProperty(ExchangePropertyKey.STREAM_CACHE_UNIT_OF_WORK, original.getUnitOfWork());
}
// if we share unit of work, we need to prepare the child exchange
if (isShareUnitOfWork()) {
prepareSharedUnitOfWork(newExchange, copy);
}
if (part instanceof Message) {
newExchange.setIn((Message) part);
} else {
Message in = newExchange.getIn();
in.setBody(part);
}
return createProcessorExchangePair(index++, processor, newExchange, route);
} else {
return null;
}
}
@Override
public void remove() {
throw new UnsupportedOperationException("Remove is not supported by this iterator");
}
};
}
@Override
public void close() throws IOException {
if (copy != null) {
processorExchangeFactory.release(copy);
// null copy to avoid releasing it back again as close may be called multiple times
copy = null;
IOHelper.closeIterator(value);
}
}
}
private Iterable<ProcessorExchangePair> createProcessorExchangePairsList(Exchange exchange, Object value) {
List<ProcessorExchangePair> result = new ArrayList<>();
// reuse iterable and add it to the result list
Iterable<ProcessorExchangePair> pairs = createProcessorExchangePairsIterable(exchange, value);
try {
for (ProcessorExchangePair pair : pairs) {
if (pair != null) {
result.add(pair);
}
}
} finally {
if (pairs instanceof Closeable) {
IOHelper.close((Closeable) pairs, "Splitter:ProcessorExchangePairs");
}
}
return result;
}
@Override
protected void updateNewExchange(Exchange exchange, int index, Iterable<ProcessorExchangePair> allPairs, boolean hasNext) {
exchange.setProperty(ExchangePropertyKey.SPLIT_INDEX, index);
if (allPairs instanceof Collection) {
// non streaming mode, so we know the total size already
exchange.setProperty(ExchangePropertyKey.SPLIT_SIZE, ((Collection<?>) allPairs).size());
}
if (hasNext) {
exchange.setProperty(ExchangePropertyKey.SPLIT_COMPLETE, Boolean.FALSE);
} else {
exchange.setProperty(ExchangePropertyKey.SPLIT_COMPLETE, Boolean.TRUE);
// streaming mode, so set total size when we are complete based on the index
exchange.setProperty(ExchangePropertyKey.SPLIT_SIZE, index + 1);
}
}
@Override
protected Integer getExchangeIndex(Exchange exchange) {
return exchange.getProperty(ExchangePropertyKey.SPLIT_INDEX, Integer.class);
}
public Expression getExpression() {
return expression;
}
private Exchange copyAndPrepareSubExchange(Exchange exchange, boolean preserveExchangeId) {
Exchange answer = processorExchangeFactory.createCopy(exchange);
if (preserveExchangeId) {
// must preserve exchange id
answer.setExchangeId(exchange.getExchangeId());
}
if (exchange.getContext().isMessageHistory()) {
// we do not want to copy the message history for split sub-messages
answer.removeProperty(ExchangePropertyKey.MESSAGE_HISTORY);
}
return answer;
}
}
| christophd/camel | core/camel-core-processor/src/main/java/org/apache/camel/processor/Splitter.java | Java | apache-2.0 | 14,523 |
package gitbucket.core.view
import java.text.Normalizer
import java.util.regex.Pattern
import java.util.Locale
import gitbucket.core.controller.Context
import gitbucket.core.service.{RepositoryService, RequestCache}
import gitbucket.core.util.StringUtil
import io.github.gitbucket.markedj._
import io.github.gitbucket.markedj.Utils._
object Markdown {
/**
* Converts Markdown of Wiki pages to HTML.
*
* @param repository the repository which contains the markdown
* @param enableWikiLink if true then wiki style link is available in markdown
* @param enableRefsLink if true then issue reference (e.g. #123) is rendered as link
* @param enableAnchor if true then anchor for headline is generated
* @param enableLineBreaks if true then render line breaks as <br>
* @param enableTaskList if true then task list syntax is available
* @param hasWritePermission true if user has writable to ths given repository
* @param pages the list of existing Wiki pages
*/
def toHtml(markdown: String,
repository: RepositoryService.RepositoryInfo,
enableWikiLink: Boolean,
enableRefsLink: Boolean,
enableAnchor: Boolean,
enableLineBreaks: Boolean,
enableTaskList: Boolean = false,
hasWritePermission: Boolean = false,
pages: List[String] = Nil)(implicit context: Context): String = {
// escape task list
val source = if(enableTaskList) escapeTaskList(markdown) else markdown
val options = new Options()
options.setSanitize(true)
options.setBreaks(enableLineBreaks)
val renderer = new GitBucketMarkedRenderer(options, repository,
enableWikiLink, enableRefsLink, enableAnchor, enableTaskList, hasWritePermission, pages)
Marked.marked(source, options, renderer)
}
/**
* Extends markedj Renderer for GitBucket
*/
class GitBucketMarkedRenderer(options: Options,
repository: RepositoryService.RepositoryInfo,
enableWikiLink: Boolean,
enableRefsLink: Boolean,
enableAnchor: Boolean,
enableTaskList: Boolean,
hasWritePermission: Boolean,
pages: List[String])
(implicit val context: Context) extends Renderer(options) with LinkConverter with RequestCache {
override def heading(text: String, level: Int, raw: String): String = {
val id = generateAnchorName(text)
val out = new StringBuilder()
out.append("<h" + level + " id=\"" + options.getHeaderPrefix + id + "\"")
if(enableAnchor){
out.append(" class=\"markdown-head\">")
out.append("<a class=\"markdown-anchor-link\" href=\"#" + id + "\"><span class=\"octicon octicon-link\"></span></a>")
out.append("<a class=\"markdown-anchor\" name=\"" + id + "\"></a>")
} else {
out.append(">")
}
out.append(text)
out.append("</h" + level + ">\n")
out.toString()
}
override def code(code: String, lang: String, escaped: Boolean): String = {
"<pre class=\"prettyprint" + (if(lang != null) s" ${options.getLangPrefix}${lang}" else "" )+ "\">" +
(if(escaped) code else escape(code, true)) + "</pre>"
}
override def list(body: String, ordered: Boolean): String = {
var listType: String = null
if (ordered) {
listType = "ol"
} else {
listType = "ul"
}
if(body.contains("""class="task-list-item-checkbox"""")){
"<" + listType + " class=\"task-list\">\n" + body + "</" + listType + ">\n"
} else {
"<" + listType + ">\n" + body + "</" + listType + ">\n"
}
}
override def listitem(text: String): String = {
if(text.contains("""class="task-list-item-checkbox" """)){
"<li class=\"task-list-item\">" + text + "</li>\n"
} else {
"<li>" + text + "</li>\n"
}
}
override def text(text: String): String = {
// convert commit id and username to link.
val t1 = if(enableRefsLink) convertRefsLinks(text, repository, "#", false) else text
// convert task list to checkbox.
val t2 = if(enableTaskList) convertCheckBox(t1, hasWritePermission) else t1
// decorate by TextDecorator plugins
helpers.decorateHtml(t2, repository)
}
override def link(href: String, title: String, text: String): String = {
super.link(fixUrl(href, false), title, text)
}
override def image(href: String, title: String, text: String): String = {
super.image(fixUrl(href, true), title, text)
}
override def nolink(text: String): String = {
if(enableWikiLink && text.startsWith("[[") && text.endsWith("]]")){
val link = text.replaceAll("(^\\[\\[|\\]\\]$)", "")
val (label, page) = if(link.contains('|')){
val i = link.indexOf('|')
(link.substring(0, i), link.substring(i + 1))
} else {
(link, link)
}
val url = repository.httpUrl.replaceFirst("/git/", "/").stripSuffix(".git") + "/wiki/" + StringUtil.urlEncode(page)
if(pages.contains(page)){
"<a href=\"" + url + "\">" + escape(label) + "</a>"
} else {
"<a href=\"" + url + "\" class=\"absent\">" + escape(label) + "</a>"
}
} else {
escape(text)
}
}
private def fixUrl(url: String, isImage: Boolean = false): String = {
lazy val urlWithRawParam: String = url + (if(isImage && !url.endsWith("?raw=true")) "?raw=true" else "")
if(url.startsWith("http://") || url.startsWith("https://") || url.startsWith("mailto:") || url.startsWith("/")){
url
} else if(url.startsWith("#")){
("#" + generateAnchorName(url.substring(1)))
} else if(!enableWikiLink){
if(context.currentPath.contains("/blob/")){
urlWithRawParam
} else if(context.currentPath.contains("/tree/")){
val paths = context.currentPath.split("/")
val branch = if(paths.length > 3) paths.drop(4).mkString("/") else repository.repository.defaultBranch
repository.httpUrl.replaceFirst("/git/", "/").stripSuffix(".git") + "/blob/" + branch + "/" + urlWithRawParam
} else {
val paths = context.currentPath.split("/")
val branch = if(paths.length > 3) paths.last else repository.repository.defaultBranch
repository.httpUrl.replaceFirst("/git/", "/").stripSuffix(".git") + "/blob/" + branch + "/" + urlWithRawParam
}
} else {
repository.httpUrl.replaceFirst("/git/", "/").stripSuffix(".git") + "/wiki/_blob/" + url
}
}
}
def escapeTaskList(text: String): String = {
Pattern.compile("""^( *)- \[([x| ])\] """, Pattern.MULTILINE).matcher(text).replaceAll("$1* task:$2: ")
}
def generateAnchorName(text: String): String = {
val normalized = Normalizer.normalize(text.replaceAll("<.*>", "").replaceAll("[\\s]", "-"), Normalizer.Form.NFD)
val encoded = StringUtil.urlEncode(normalized)
encoded.toLowerCase(Locale.ENGLISH)
}
def convertCheckBox(text: String, hasWritePermission: Boolean): String = {
val disabled = if (hasWritePermission) "" else "disabled"
text.replaceAll("task:x:", """<input type="checkbox" class="task-list-item-checkbox" checked="checked" """ + disabled + "/>")
.replaceAll("task: :", """<input type="checkbox" class="task-list-item-checkbox" """ + disabled + "/>")
}
}
| nobusugi246/gitbucket | src/main/scala/gitbucket/core/view/Markdown.scala | Scala | apache-2.0 | 7,606 |
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
package org.apache.hyracks.storage.am.common.api;
import org.apache.hyracks.api.exceptions.HyracksDataException;
import org.apache.hyracks.dataflow.common.data.accessors.ITupleReference;
public interface ITwoPCIndexBulkLoader {
/**
* Append a "delete" tuple to the index in the context of a bulk load.
*
* @param tuple
* "delete" Tuple to be inserted.
* @throws IndexException
* If the input stream is invalid for bulk loading (e.g., is not sorted).
* @throws HyracksDataException
* If the BufferCache throws while un/pinning or un/latching.
*/
public void delete(ITupleReference tuple) throws HyracksDataException;
/**
* Abort the bulk modify op
*/
public void abort() throws HyracksDataException;
}
| ecarm002/incubator-asterixdb | hyracks-fullstack/hyracks/hyracks-storage-am-common/src/main/java/org/apache/hyracks/storage/am/common/api/ITwoPCIndexBulkLoader.java | Java | apache-2.0 | 1,621 |
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<meta http-equiv="X-UA-Compatible" content="IE=edge"/>
<meta name="viewport" content="width=device-width, initial-scale=1, shrink-to-fit=no"/>
<title>Password Update Form</title>
<link href="../../static/css/cas.css" rel="stylesheet" th:remove="tag" />
<script th:inline="javascript">
/*<![CDATA[*/
var policyPattern = /*[[${policyPattern}]]*/;
var passwordStrengthI18n = {
0: /*[[#{screen.pm.password.strength.0}]]*/,
1: /*[[#{screen.pm.password.strength.1}]]*/,
2: /*[[#{screen.pm.password.strength.2}]]*/,
3: /*[[#{screen.pm.password.strength.3}]]*/,
4: /*[[#{screen.pm.password.strength.4}]]*/
};
/*]]>*/
</script>
</head>
<body>
<main role="main" class="container mt-3 mb-3">
<div class="alert alert-info">
<h3 th:utext="${expiredPass} ? #{screen.expiredpass.heading} : #{screen.mustchangepass.heading}">Change Password
Heading</h3>
<form id="passwordManagementForm" th:if="${passwordManagementEnabled}" method="post" th:object="${password}">
<div class="alert alert-danger" th:if="${#fields.hasErrors('*')}">
<span th:each="err : ${#fields.errors('*')}" th:utext="${err}">Error text</span>
</div>
<div class="form-group">
<label for="password" th:utext="#{screen.pm.enterpsw}">Enter Password:</label>
<input class="form-control" type="password" id="password" th:field="*{password}" required/>
</div>
<div class="form-group">
<label for="confirmedPassword" th:utext="#{screen.pm.confirmpsw}">Confirm Password:</label>
<input class="form-control" type="password" id="confirmedPassword" th:field="*{confirmedPassword}"
required/>
</div>
<div class="form-group">
<div>
<span th:text="#{screen.pm.password.strength}">Strength:</span>
<span id="password-strength-icon" class="fas" aria-hidden="true"></span>
</div>
<div class="progress">
<div id="strengthProgressBar" class="progress-bar"></div>
</div>
<div>
<span id="password-strength-warning"></span> <span id="password-strength-suggestions"></span>
</div>
</div>
<div class="form-group" id="password-strength-notes">
<div id="password-policy-violation-msg" class="alert alert-danger" role="alert" style="display: none;">
<span class="fas fa-exclamation-circle" aria-hidden="true"></span>
<strong th:text="#{screen.pm.password.policyViolation}">Password does not match the password policy requirement.</strong>
</div>
<div id="password-confirm-mismatch-msg" class="alert alert-danger" role="alert" style="display: none;">
<span class="fas fa-exclamation-circle" aria-hidden="true"></span>
<strong th:text="#{screen.pm.password.confirmMismatch}">Passwords do not match.</strong>
</div>
</div>
<div class="form-group text-center">
<input type="hidden" name="execution" th:value="${flowExecutionKey}"/>
<input type="hidden" name="_eventId" value="submit"/>
<input class="btn btn-submit"
name="submit"
accesskey="s"
th:value="#{screen.pm.button.submit}"
th:attr="data-processing-text=#{screen.welcome.button.loginwip}"
value="SUBMIT"
id="submit"
type="submit"
disabled="true"/>
<a class="btn btn-danger" th:href="@{/login}" th:text="#{screen.pm.button.cancel}">CANCEL</a>
</div>
</form>
<p th:unless="${passwordManagementEnabled}"
th:utext="${expiredPass} ? #{screen.expiredpass.message} : #{screen.mustchangepass.message}">Expired/Must
Change Password text</p>
</div>
</main>
</body>
</html>
| rrenomeron/cas | webapp/resources/templates/fragments/pwdupdateform.html | HTML | apache-2.0 | 4,369 |
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