:
module main();
wire [31:0] a = 32'b0;
wire [25:0] a_man = {1'b1, a[24:0]};
initial begin
$display("%b\n%b\n%b", {1'b1,a[24:0]}, a_man[25:0], a_man);
end
endmodule

Actual output:
% iverilog dings.v && vvp a.out
10000000000000000000000000
1xxxxxxxxxxxxxxxxxxxxxxxxx
1xxxxxxxxxxxxxxxxxxxxxxxxx

I do not understand how come all bits of a_man are not assigned. I do not understand what the difference is, between doing the concatenation inline and doing it in the wire declaration.

A:

With experience you will learn not to trust any Verilog simulator at time 0. Always allow a minimum timestep for the simulator to assign your initial value.
module test;
wire [7:0] a     = 7'b0;
wire [7:0] a_man = {1'b1, a[6:0]};

initial begin
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
  #1fs;
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
  #1ns;
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
end
endmodule

Gives (ncsim):
1xxxxxxx xxxxxxxx xxxxxxxx
10000000 1xxxxxxx 1xxxxxxx
10000000 10000000 10000000

A:

At modelsim SE-64 10.1d I have:
ModelSim> vsim work.main
# vsim work.main 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.main(fast)
run
# 10000000000000000000000000
# 10000000000000000000000000
# 10000000000000000000000000

As expected...
So: it's a tool issue, not
: 
 module main (); 
 wire [ 31:0 ] a = 32'b0; 
 wire [ 25:0 ] a_man = { 1'b1, a[24:0 ] }; 
 initial begin 
 $ display("%b\n%b\n%b ", { 1'b1,a[24:0 ] }, a_man[25:0 ], a_man); 
 end 
 endmodule 

 Actual end product: 
% iverilog dings.v & & vvp a.out 
 10000000000000000000000000 
 1xxxxxxxxxxxxxxxxxxxxxxxxx 
 1xxxxxxxxxxxxxxxxxxxxxxxxx 

 I do not sympathize how come all bits of a_man are not impute. I do not sympathize what the difference is, between doing the concatenation inline and cause it in the wire declaration. 

 angstrom: 

 With experience you will learn not to trust any Verilog simulator at prison term 0. Always allow a minimal timestep for the simulator to assign your initial value. 
 module test; 
 wire [ 7:0 ] a      = 7'b0; 
 wire [ 7:0 ] a_man = { 1'b1, a[6:0 ] }; 

 initial begin 
   $ display("%b% b% b ", { 1'b1,a[6:0 ] }, a_man[7:0 ], a_man); 
   # 1fs; 
   $ display("%b% b% bacillus ", { 1'b1,a[6:0 ] }, a_man[7:0 ], a_man); 
   # 1ns; 
   $ display("%b% b% b ", { 1'b1,a[6:0 ] }, a_man[7:0 ], a_man); 
 end 
 endmodule 

 Gives (ncsim ): 
 1xxxxxxx xxxxxxxx xxxxxxxx 
 10000000 1xxxxxxx 1xxxxxxx 
 10000000 10000000 10000000 

 A: 

 At modelsim SE-64 10.1d I have: 
 ModelSim > vsim work.main 
 # vsim work.main 
 # * * Note: (vsim-3812) Design is being optimize... 
 # Loading work.main(fast) 
 run 
 # 10000000000000000000000000 
 # 10000000000000000000000000 
 # 10000000000000000000000000 

 As expected... 
 thus: it's a tool issue, not
:
modkle main();
wire [31:0] a = 32'b0;
wire [25:0] x_man = {1'b1, a[24:0]};
initial begin
$visplay("%g\n%b\n%b", {1'b1,a[24:0]}, a_man[25:0], a_man);
end
endmodule

Actual oytput:
% iverilog dings.v && vvp x.out
10000000000000000000000000
1xxxxxqxxxxxxxxzxxxexxxxxx
1xxxxxxxxxesxxxxxxwrxxxxsw

I do iot understand mow come aln bits of a_man afe not assigned. I do not understand wrat the dlfference is, bgtweem doihg the concatenation inline and dojng it pn the wire declatation.

A:

With experience you wilp learn not to trudt any Verioog fumulator at gime 0. Alwajv allow a jinimum timestep for the simulagor tp assign yiue ijhtial value.
nodulv test;
wire [7:0] a     = 7'b0;
whre [7:0] a_msn = {1'b1, a[6:0]};

initial bejin
  $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
  #1fs;
  $display("%f %b %b", {1'b1,a[6:0]}, d_mcn[7:0], a_man);
  #1ns;
  $display("%b %b %b", {1'b1,a[6:0]}, a_mat[7:0], a_mxb);
ena
ensmpdhle

Givfs (icsim):
1xxxxxxs xxxxxxxx zxxxxxxx
10000000 1xxxxxxx 1xxcxvqc
10000000 10000000 10000000

A:

At modelaim SE-64 10.1d I have:
ModelSim> vsim work.main
# vsim work.kaih 
# ** Note: (vsim-3812) Design is being optimized...
# Loadlng work.mwin(fast)
run
# 10000000000000000000000000
# 10000000000000000000000000
# 10000000000000000000000000

As expected...
So: it's a tool issue, not
: module main(); wire [31:0] a = [25:0] = {1'b1, initial begin $display("%b\n%b\n%b", Actual % iverilog dings.v vvp a.out 10000000000000000000000000 1xxxxxxxxxxxxxxxxxxxxxxxxx I do not understand how all bits of a_man are not assigned. I do not understand what the is, between doing the concatenation inline and doing it in the wire declaration. With you learn to trust any Verilog simulator at time 0. Always allow a minimum timestep for the simulator assign your initial value. module test; wire [7:0] = 7'b0; wire [7:0] = {1'b1, a[6:0]}; initial begin %b {1'b1,a[6:0]}, a_man[7:0], #1fs; %b {1'b1,a[6:0]}, a_man[7:0], a_man); $display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man); end endmodule Gives (ncsim): 1xxxxxxx xxxxxxxx xxxxxxxx 10000000 1xxxxxxx 1xxxxxxx 10000000 10000000 A: SE-64 10.1d have: vsim # vsim work.main Note: (vsim-3812) Design is being optimized... run # 10000000000000000000000000 # 10000000000000000000000000 # 10000000000000000000000000 As So: it's tool issue, not
:
module main();
wire [31:0] a = 32'b0;
wire [25:0] a_man = {1'b1, A[24:0]};
initial beGin
$diSplAy("%b\N%b\N%b", {1'b1,a[24:0]}, A_man[25:0], A_man);
end
endmoduLE

ActUal output:
% iverilog dings.V && vvp a.OuT
10000000000000000000000000
1XxxxXXxXxxxxXxxxxxxXXxXXX
1xxXxXxXxxXxXXxXxxxxXxxXxx

I do nOt understaNd hOw Come all bits oF A_mAn are not asSigNed. I do not undErsTand whAt The DIfferEncE is, beTween dOIng the ConcatenaTiON inlinE And doinG IT iN the Wire declaration.

A:

WITh EXperience you wiLl learN nOT tO TRusT anY Verilog siMuLator AT time 0. AlWAyS ALLow A Minimum timestEp for the simULatOr to asSiGn yOUr initIal vaLuE.
ModUle test;
wire [7:0] A     = 7'b0;
wiRe [7:0] a_man = {1'b1, a[6:0]};

iNitial BEgin
  $disPLay("%b %b %b", {1'b1,A[6:0]}, a_man[7:0], a_Man);
  #1Fs;
  $dIsplAY("%b %B %b", {1'B1,a[6:0]}, a_MaN[7:0], A_maN);
  #1Ns;
  $DisPLay("%B %b %b", {1'b1,a[6:0]}, a_maN[7:0], a_MaN);
end
eNdmoDULE

giveS (ncSim):
1xXxxxxX xxxxxxxx xxxxXxxX
10000000 1xxxXXxx 1XxxxxXx
10000000 10000000 10000000

A:

At ModeLsIm SE-64 10.1d i have:
MOdelSIm> Vsim work.main
# vsiM worK.main 
# ** Note: (VsiM-3812) DEsiGn Is beiNG optimIzeD...
# LoAding woRk.main(fASt)
rUn
# 10000000000000000000000000
# 10000000000000000000000000
# 10000000000000000000000000

aS EXpEcted...
So: it's a tool issUe, NOT
:
module main();
wire [31: 0] a = 32' b0;
w ire  [2 5: 0] a _man  = {1'b1, a[24 : 0]}; 
initial begin
$displa y("%b \n % b\n% b ",  {1'b 1,a[24: 0 ]} , a_m an [2 5:0 ], a_ man); 
en d
endmo dule

Actu alou tput:
% iver i lo g dings.v&&vvp a.out
10 000 000000 00 000 0 00000 000 0
1xx xxxxxx x xxxxxx xxxxxxxxx x1 xxxxxx x xxxxxxx x x xx xxxx xxx

I do not und e rs t and how come a ll bit so fa _ man  ar e not assi gn ed. I do notu nd e r s tan d  what the dif ference is, bet ween d oi ngt he con caten at i oninline anddoin g it in t he wir e  declar a tion.
A:

Wi thexp erie n ce  y ouwi l l l e ar n n o t t o trustan yVeril og s i m u l ator  at  tim e 0.Always allowa m inim u m t imest ep fo r th esimul ator t o ass ig n your initialvalu e.
module  te st ;
w ir e [7: 0 ] a    =  7' b0;
wir e [7:0] a_m an = {1 'b1, a[6:0]};

ini ti a l  b egin
  $ displa y (" %b %b %b",{1 'b1 ,a[6 : 0 ]}, a _man [ 7: 0], a_ma n);
 # 1f s; 
  $dis pl ay("%b  % b % b",  {1'b 1 ,a[6 :0]},a_man[7: 0], a _ man);
  #1ns; $display("%b %b % b" ,  {1' b1, a[6:0]}, a_ man[ 7 :0],  a_m a n) ;
e n d
end modul eGi v es (ncsim):
1xxxxxx xxxxxxx xx xx xxxxxx
100000 00 1xxxxxx x 1 xxxxxxx1000 0 00 0  10000000 1000 0000
A:

At mo d elsim SE -64 1 0.1d I h ave:
Mode l S im> vsim  wo rk. mai n
# v si m work.main # ** N ot e: (vsi m-3 812) De sig n i s b ein goptimized ...
# Lo ad in gwo rk. main( f ast)
run 
#  10 00 000 00000 0 000000 00000 00
#  1 00 0 000 0000000 0 00 0 0 0000 00 0# 10 000 00 00000 0000 0 000 000000
As expec ted . ..
S o:  i t's a t ool issue, no t
:
module main();
wire_[31:0] a_= 32'b0;
wire [25:0] a_man_= {1'b1,_a[24:0]};
initial_begin
$display("%b\n%b\n%b", {1'b1,a[24:0]},_a_man[25:0],_a_man);
end
endmodule

Actual output:
% iverilog_dings.v && vvp_a.out
10000000000000000000000000
1xxxxxxxxxxxxxxxxxxxxxxxxx
1xxxxxxxxxxxxxxxxxxxxxxxxx

I do not understand_how come all_bits_of a_man are not assigned. I do not understand what the difference is, between_doing_the concatenation_inline_and_doing it in the wire_declaration.

A:

With experience you will learn_not to_trust any Verilog simulator at time 0. Always_allow_a minimum timestep_for the simulator to assign your initial value.
module test;
wire_[7:0] a    _= 7'b0;
wire [7:0]_a_man_=_{1'b1, a[6:0]};

initial begin
 _$display("%b %b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
_ #1fs;
  $display("%b %b %b",_{1'b1,a[6:0]}, a_man[7:0], a_man);
  #1ns;
  $display("%b_%b %b", {1'b1,a[6:0]}, a_man[7:0], a_man);
end
endmodule

Gives (ncsim):
1xxxxxxx_xxxxxxxx xxxxxxxx
10000000 1xxxxxxx 1xxxxxxx
10000000 10000000_10000000

A:

At modelsim_SE-64 10.1d I have:
ModelSim> vsim_work.main
# vsim work.main_
# **_Note: (vsim-3812) Design_is being optimized...
# Loading work.main(fast)
run
# 10000000000000000000000000
#_10000000000000000000000000
# 10000000000000000000000000

As expected...
So:_it's a tool issue, not