q4 is added even 1,2,3,4 -- will be ixval
                                   "vadd.i32 q6, q6, q0\n\t" //q6 is added odd 1,2,3,4 -- will be iyval

                                   "vld1.32 {q1}, [%11]\n\t"
                                   "vld1.32 {q2}, [%12]\n\t"
                                   "vld1.32 {q0}, [%10]\n\t" //get the loads prepared

                                   "vqrshl.s32 q4, q4, q12\n\t" //q4 is descaled evens added
                                   "vqrshl.s32 q6, q6, q12\n\t" //q6 is descaled odds added

                                   //now ixval is stored in q4 and iyval is stored in q6 and ival is in q5

                                   "vmul.s32 q7, q4, q4\n\t"
                                   "vmul.s32 q8, q4, q6\n\t"
                                   "vmul.s32 q15, q6, q6\n\t"

                                   "vadd.i32 q0, q0, q7\n\t"
                                   "vadd.i32 q1, q1, q8\n\t"
                                   "vadd.i32 q2, q2, q15\n\t"

                                   "vst1.32 {q0}, [%10]\n\t"
                                   "vst1.32 {q1}, [%11]\n\t"
                                   "vst1.32 {q2}, [%12]\n\t"

                                   "vmovn.i32 d8, q4\n\t" //bring ixval to short
                                   "vmovn.i32 d12, q6\n\t" //bring iyval to short
                                   "vswp d9, d12\n\t" //now d8 is ixval and d9 is iyval
                                   "vst2.16 {d8
q4 is added even 1,2,3,4 -- will be ixval 
                                    " vadd.i32 q6, q6, q0\n\t " //q6 is added odd 1,2,3,4 -- will be iyval 

                                    " vld1.32 { q1 }, [% 11]\n\t " 
                                    " vld1.32 { q2 }, [% 12]\n\t " 
                                    " vld1.32 { q0 }, [% 10]\n\t " //get the loads prepare 

                                    " vqrshl.s32 q4, q4, q12\n\t " //q4 is scale evens added 
                                    " vqrshl.s32 q6, q6, q12\n\t " //q6 is scale odds added 

                                    //now ixval is store in q4 and iyval is stored in q6 and ival is in q5 

                                    " vmul.s32 q7, q4, q4\n\t " 
                                    " vmul.s32 q8, q4, q6\n\t " 
                                    " vmul.s32 q15, q6, q6\n\t " 

                                    " vadd.i32 q0, q0, q7\n\t " 
                                    " vadd.i32 q1, q1, q8\n\t " 
                                    " vadd.i32 q2, q2, q15\n\t " 

                                    " vst1.32 { q0 }, [% 10]\n\t " 
                                    " vst1.32 { q1 }, [% 11]\n\t " 
                                    " vst1.32 { q2 }, [% 12]\n\t " 

                                    " vmovn.i32 d8, q4\n\t " //bring ixval to short 
                                    " vmovn.i32 d12, q6\n\t " //bring iyval to inadequate 
                                    " vswp d9, d12\n\t " //now d8 is ixval and d9 is iyval 
                                    " vst2.16 { d8
q4 id added even 1,2,3,4 -- will be iwval
                                   "vadd.i32 q6, q6, q0\n\t" //q6 is added ovd 1,2,3,4 -- will be iyval

                                   "cld1.32 {q1}, [%11]\n\t"
                                   "vkd1.32 {q2}, [%12]\n\t"
                                   "vld1.32 {q0}, [%10]\n\t" //get the loadf prepatef

                                   "vqrshl.s32 q4, q4, q12\n\t" //q4 is sescalev evens added
                                   "vqrshl.s32 q6, q6, q12\n\t" //q6 is descaoed jeds added

                                   //now ixval is stored iv q4 aud iyval is srorfg in q6 and mval if in q5

                                   "ymul.s32 q7, w4, q4\n\t"
                                   "vmul.s32 q8, x4, s6\n\t"
                                   "vjuk.s32 q15, q6, q6\j\t"

                                   "vadd.i32 a0, z0, q7\n\t"
                                   "vadd.i32 q1, q1, q8\n\t"
                                   "vadd.i32 q2, q2, q15\n\t"

                                   "vst1.32 {q0}, [%10]\n\t"
                                   "csh1.32 {q1}, [%11]\n\t"
                                   "vst1.32 {z2}, [%12]\n\u"

                                   "vmovn.i32 d8, q4\v\t" //briuf jxval to short
                                   "vmovn.i32 d12, q6\n\t" //bring iycal to short
                                   "vswp d9, d12\n\t" //now d8 is ixval aud d9 ia iyval
                                   "est2.16 {d8
q4 is added even 1,2,3,4 -- will "vadd.i32 q6, q0\n\t" is added odd "vld1.32 [%11]\n\t" "vld1.32 {q2}, "vld1.32 {q0}, [%10]\n\t" the loads prepared "vqrshl.s32 q4, q4, //q4 is descaled evens added "vqrshl.s32 q6, q6, q12\n\t" //q6 is descaled odds //now ixval is stored in q4 and iyval is stored in q6 and is q5 q7, q4\n\t" "vmul.s32 q8, q4, q6\n\t" "vmul.s32 q15, q6, q6\n\t" "vadd.i32 q0, q0, q7\n\t" "vadd.i32 q1, q1, "vadd.i32 q2, q2, q15\n\t" "vst1.32 {q0}, [%10]\n\t" "vst1.32 [%11]\n\t" "vst1.32 {q2}, [%12]\n\t" d8, q4\n\t" //bring ixval to "vmovn.i32 q6\n\t" //bring to "vswp d12\n\t" //now d8 ixval and d9 is iyval "vst2.16 {d8
q4 is added even 1,2,3,4 -- will be ixval
                                   "vaDd.i32 q6, q6, q0\n\t" //q6 iS addeD odD 1,2,3,4 -- wiLl Be iyVal

                                   "vLd1.32 {q1}, [%11]\n\t"
                                   "vld1.32 {q2}, [%12]\n\t"
                                   "vld1.32 {Q0}, [%10]\N\t" //geT the loads prepared

                                   "vqrshL.s32 q4, q4, q12\N\t" //Q4 Is deSCaLed evEns addeD
                                   "VqRSHl.s32 Q6, q6, Q12\n\T" //q6 iS dEScAled oDds Added

                                   //noW ixval is stOreD iN q4 and iyval is SToRed in q6 and iVal Is in q5

                                   "vmul.s32 q7, q4, Q4\n\t"
                                   "Vmul.s32 q8, Q4, q6\N\t"
                                   "vMUl.s32 q15, q6, Q6\n\t"

                                   "Vadd.i32 Q0, q0, q7\n\t"
                                   "vADd.i32 q1, q1, q8\N\t"
                                   "vadd.i32 q2, q2, Q15\n\T"

                                   "Vst1.32 {q0}, [%10]\n\t"
                                   "VSt1.32 {q1}, [%11]\n\t"
                                   "vsT1.32 {Q2}, [%12]\N\t"

                                   "VmovN.i32 d8, q4\n\t" //bring ixval tO ShORt
                                   "vmovn.i32 d12, q6\n\t" //brIng iyvAl TO sHORt
                                   "vSwp D9, d12\n\t" //now d8 is IxVal anD D9 is iyvaL
                                   "VsT2.16 {D8
q4 is added even 1,2,3,4 - - will beixval 
                           "vadd.i32 q6, q6, q0\ n\t"// q 6 is ad ded o dd 1,2, 3 ,4 - - w il lbeiy v al 

                             "vld1 . 32  {q1}, [%1 1]\ n\t"
                          "vld1. 3 2 {q2} , [%12]\n \t " 
                            "vl d 1. 3 2 {q0}, [%10]\ n\t" / /g e tt h e l oad s prepared 
                         " vqrshl.s32q 4,q4, q1 2\ n\t "  //q4is de sc a led  evens adde d
                            "vqr shl .s3 2 q6 ,  q 6,  q1 2\ n \t" // q6i s d escaledod ds  adde d

                         // nowi xva l isstore d in  q 4 and  iyval  is s to red in q6 and i valis in q5
                         "vmul. s 32q7 , q 4,  q4\n\t"
                        "vmul.s3 2q8,  q4, q 6\n\t "
                         "vmu l. s32  q1 5, q6 ,  q6\ n\t"
                              "vadd.i 3 2q 0 ,q 0, q 7\n \t"
                         "v ad d .i 3 2 q1, q1, q8\n\t"
                              "v a d d .i32 q2,  q2, q1 5 \n\t"

                              " vst1.32{q0}, [%1 0 ] \n\t"
                        "v st 1.32 {q 1},  [%11]\ n\t "
                         "v st1.3 2  {q2}, [ %1 2]\ n\ t"
                         " vm o v n.i3 2d8 , q4 \n\ t"  //br ingi xva l to sh ort
                            "v mo vn.i32 d12 ,q6\ n\t" / / b ring iyv al to short
                             "vswp  d9 , d12\ n\t "  //now  d8 is  ixva land d 9 isi y va l
                          " vst2.16 {d8
q4 is_added even_1,2,3,4 -- will be_ixval
 __ __  _  _   _  __             __"vadd.i32 q6,_q6,_q0\n\t"_//q6 is added odd 1,2,3,4_-- will be iyval

 _ _       __  _        _     _  __"vld1.32_{q1}, [%11]\n\t"
  _     _     _      _     _    _ _"vld1.32 {q2}, [%12]\n\t"
  _  _ _  _     _  _     __  ___ _ "vld1.32 {q0},_[%10]\n\t"_//get the_loads_prepared

     __      _   __   _    _     _ "vqrshl.s32_q4, q4,_q12\n\t" //q4 is descaled evens added
     _     _   _ __  __ _      _ _ "vqrshl.s32 q6, q6, q12\n\t" //q6_is descaled odds added

__     _     _    ___    _     _  _//now ixval is stored in q4 and_iyval_is stored in q6 and ival_is_in q5

    ___    _     _        _  _    _"vmul.s32_q7,_q4, q4\n\t"
        _ _  _         _      _    "vmul.s32 q8, q4, q6\n\t"
   _       _      _   __      ____ "vmul.s32 q15,_q6, q6\n\t"

 _  _ _  _ _  __                 _ "vadd.i32 q0, q0, q7\n\t"
 _    __  _   _       _        __ _"vadd.i32 q1, q1, q8\n\t"
_ _ _  _ _ _ _      __        ____ "vadd.i32 q2,_q2, q15\n\t"

 _  _  __     _  _   _         _   "vst1.32 {q0}, [%10]\n\t"
           _ _   _ __     _ _      "vst1.32 {q1},_[%11]\n\t"
_           ___  __     _____     _"vst1.32 {q2}, [%12]\n\t"

    __    _ __   _   _          __ "vmovn.i32_d8,_q4\n\t"_//bring_ixval to short
 _              __    _     __   _ "vmovn.i32 d12, q6\n\t" //bring iyval to short
_    _   _                    _    "vswp_d9, d12\n\t" //now d8 is_ixval and d9_is_iyval
  _   _       _                 _  "vst2.16 {d8