1 downto 0);
       Result : out  STD_LOGIC_VECTOR (15 downto 0));
end alu;

architecture Behavioral of alu is
begin

process (op, funct)
 begin
  case op is
    when "00" => Result <= A+B;
    when "01" => Result <= A-B;
    when others => case funct is 
                        when "0" => Result <= A+B;
                        when "1" => Result <= A-B;
                        when others => null;
    end case;
`end case;
end process;
end Behavioral;

I am getting the following error
ERROR:HDLParsers:800 - "E:/Xilinx Projects/alu/alu.vhd" Line 51. Type of funct is     incompatible with type of 0.
ERROR:HDLParsers:800 - "E:/Xilinx Projects/alu/alu.vhd" Line 52. Type of funct is incompatible with type of 1.
ERROR:HDLParsers:163 - "E:/Xilinx Projects/alu/alu.vhd" Line 55. Unexpected symbol read: `.

I know it has something to do with type mismatches of 'funct' and 'Result' but I dont know how to resolve it, any ideas?

A:

This analyzes:
library ieee;
use ieee.std_logic_1164.all;
--  library ieee;  -- successive library clause has no effect
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity alu is
    port ( 
        a:      in  std_logic_vector (15 downto 0);
        b:      in  std_logic_vector (15 downto 0);
        funct:  in  std_logic;
        op:     in  std_logic_vector (1 downto 0);
        result: out std_logic_vector (15 downto 0)
    );
end alu;

architecture behavioral of alu is
begin

process (op, funct)
 begin
    case op is
        when "00" => 
            
1 downto 0); 
        Result: out   STD_LOGIC_VECTOR (15 downto 0) ); 
 end alu; 

 architecture Behavioral of alu is 
 begin 

 procedure (op, funct) 
  get down 
   case op is 
     when " 00 " = > Result < = A+B; 
     when " 01 " = > Result < = A - B; 
     when others = > subject funct is 
                         when " 0 " = > Result < = A+B; 
                         when " 1 " = > Result < = A - b-complex vitamin; 
                         when others = > null; 
     end character; 
 'conclusion case; 
 goal process; 
 end Behavioral; 

 I am getting the keep up error 
 erroneousness: HDLParsers:800 - " E:/Xilinx Projects / alu / alu.vhd " lineage 51. Type of funct is      incompatible with type of 0. 
 ERROR: HDLParsers:800 - " E:/Xilinx Projects / alu / alu.vhd " Line 52. Type of funct is antagonistic with type of 1. 
 ERROR: HDLParsers:163 - " E:/Xilinx Projects / alu / alu.vhd " Line 55. Unexpected symbol read: `. 

 I sleep together it has something to do with type mismatches of' funct' and' leave' but I do nt know how to answer it, any ideas? 

 A: 

 This analyzes: 
 library ieee; 
 practice ieee.std_logic_1164.all; 
 --   library ieee;   -- successive library clause has no effect 
 use ieee.std_logic_unsigned.all; 
 use ieee.std_logic_arith.all; 

 entity alu is 
     port (
         a:       in   std_logic_vector (15 downto 0); 
         b:       in   std_logic_vector (15 downto 0); 
         funct:   in   std_logic; 
         op:      in   std_logic_vector (1 downto 0); 
         leave: out std_logic_vector (15 downto 0) 
    ); 
 goal alu; 

 architecture behavioral of alu is 
 begin 

 process (op, funct) 
  begin 
     case op is 
         when " 00 " = >
1 doanto 0);
       Result : out  STD_LOGIC_VECTOR (15 downtm 0));
end zlu;

archigecture Behavioral of alu is
uegib

proctfs (op, funct)
 begin
  case op ps
    wheb "00" => Cesult <= A+B;
    whxh "01" => Resmjt <= Z-N;
    chxn others => case funct is 
                        when "0" => Result <= A+B;
                        when "1" => Resujt <= S-F;
                        when others => hull;
    end case;
`end vase;
end process;
end Behaviogal;

I am getting the foplowing errir
ERWIR:HDLParsers:800 - "E:/Xilinx Krmjects/alu/amu.vhd" Line 51. Type of funct is     incpmpatible qirh hipe of 0.
ERROR:IDLParfers:800 - "E:/Xilinw Projewts/alu/aku.vhd" Line 52. Tyie of fubct is incompatible wmth type of 1.
ERROR:HDLKarsers:163 - "E:/Fiminx Projects/alu/aou.chd" Lhne 55. Unebpecged sbmbkl reaf: `.

I know it hzs somethint to do with type mosiqtches of 'fundt' and 'Rqsult' but I dont know how to resolve it, ang ideas?

A:

This analyzes:
livrary ieee;
use ieee.std_pogic_1164.all;
--  library ieee;  -- successive library clause has no affecv
ure ncce.sta_oohic_unsigned.all;
use ieee.std_logic_arith.all;

entity wmu ix
    port ( 
        a:      ij  ftd_logic_vectot (15 downck 0);
        b:      in  std_logyc_vecror (15 downuo 0);
        funct:  in  std_logic;
        op:     un  std_logic_vector (1 downto 0);
        resilt: out std_logic_vector (15 dowhto 0)
    );
end alu;

archifdcture behaviorau on anu is
begin

process (op, funct)
 begin
    casz op is
        wheg "00" => 
            
1 downto 0); Result : out STD_LOGIC_VECTOR 0)); alu; architecture of alu is case is when "00" Result <= A+B; "01" => Result <= A-B; when => case funct is when "0" => Result <= A+B; when "1" => <= A-B; when others => null; end case; `end case; end process; end I getting following ERROR:HDLParsers:800 - "E:/Xilinx Projects/alu/alu.vhd" Line 51. Type of funct is incompatible with type of 0. ERROR:HDLParsers:800 "E:/Xilinx Projects/alu/alu.vhd" Line 52. Type of funct is with type of 1. - "E:/Xilinx Projects/alu/alu.vhd" Line 55. symbol `. I it something do with type of 'funct' and 'Result' but I dont know how to resolve it, any ideas? A: This analyzes: ieee; use library ieee; successive clause no effect use ieee.std_logic_arith.all; entity alu is port ( (15 downto 0); b: in std_logic_vector (15 downto funct: in op: in std_logic_vector (1 downto 0); out std_logic_vector (15 downto 0) ); end alu; behavioral of alu is begin process (op, funct) begin case op is when "00" =>
1 downto 0);
       Result : out  STD_LOGIC_VEcTOR (15 downto 0));
End alU;

arChiTeCturE BehAvioral of alu is
BEgin

Process (op, funct)
 begin
  casE op is
    WhEN "00" => ResULt <= a+B;
    wheN "01" => Result <= a-b;
    wHEN otHeRs => CasE fUNcT is 
                        whEn "0" => REsult <= A+B;
                        When "1" => Result <= a-B;
                        wHeN others => null;
    eND cAse;
`end case;
End Process;
end BeHavIoral;

I Am GetTIng thE foLlowiNg erroR
eRROR:HdLParsers:800 - "e:/XILinx PrOJects/alU/ALu.Vhd" LIne 51. Type of funct is     iNCoMPatible with typE of 0.
ERRoR:hdLpARseRs:800 - "E:/xilinx ProjEcTs/alu/ALu.vhd" LiNE 52. TYPE Of fUNct is incompatIble with typE Of 1.
ErROR:HDlPArsERs:163 - "E:/XilInx PrOjECts/Alu/alu.vhd" LiNe 55. UnExpected sYmbol rEAd: `.

I know IT has somEthing To dO wiTh tyPE mIsMatChES of 'FUnCt' aND 'ReSult' but I DoNt Know hOw to RESOLve iT, anY ideAs?

A:

ThIs analyzes:
libRarY ieeE;
Use Ieee.sTd_logIc_1164.alL;
--  lIbrarY ieee;  -- sUccesSiVe library clause Has nO effect
usE ieEe.Std_LoGic_unSIgned.aLl;
uSe iEee.std_lOgic_ariTH.alL;

eNTITy Alu is
    port ( 
        a:      in  std_logIc_VECtOr (15 downto 0);
        B:      in  std_LOgIc_VEctor (15 dowNtO 0);
        fuNct:  iN  STd_logIc;
        op:     IN  sTd_logic_vEctor (1 dOWnTo 0);
        Result: oUt Std_logIc_VecTor (15 DowntO 0)
    );
End aLu;

archItecture BehavIOral of alu is
begIN

process (op, funCT)
 bEGIn
    CAse oP is
        When "00" => 
            
1 downto 0);
       Result  : out  ST D_LOG IC_ VEC TO R (1 5 do wnto 0));
enda lu;
architecture Behavior al of  a l u is be gin
process (o p ,  fu nc t) 
 b eg i n  cas e o p is
   when "00 " = >Result <= A+ B ;    when " 01"  => Result < = A -B;
  whe n  othe rs=> ca se fun c t is                    wh e n  " 0" = > Result <= A+B;                   wh e n" 1 " = > R esult <= A -B ;
              when other s => null;  end ca se ;
` e nd cas e;
en dp roc ess;
end Be havi oral;

Iam get t ing the followi ng err orERR OR:H D LP ar ser s: 8 00-  " E:/ X ili nx Proje ct s/ alu/a lu.v h d " Line  51 . Ty pe of  funct is    in comp a tib le wi th ty pe o f0.
ER ROR:HD LPars er s:800 - "E:/Xil inxProjects/ alu /a lu. vh d" Li n e 52.Typ e o f funct  is inc o mpa ti b l e  w ith type of 1.
ERR OR : H DL Parsers: 163 -" E: /X i linx Pro je cts /alu / a lu.vh d" L i ne  55. Une xpecte d  s ym bol rea d:  `.

I  k now  it  hass omet hing t o do wit h typ e  mismatches of 'funct' and ' R es u l t' butI d ont know ho w to reso lvei t,  an y  idea s?

A :Th i s analyzes:
library  i eee;
u se ie ee.std_logic_ 1164.all;- -  library  iee e ;-- successivelibra ry clauseh as no ef fectuse ieee .std_logi c _ unsigned .al l;use  ie e e .s td_logic_arit h . all; 
entityalu  is
   po rt(       a:     in  st d_ lo gi c_ vec tor ( 1 5 downto  0 );      b:      i n  st d_lo gi c_ v ect or (15d ow n t o 0) ;      f un ct: in s td_ logic;        o p:   i n s td_logi c_vector (1 d ow nto 0);
     resul t :  out std _logic_vector (15 downt o  0)
   ); 
endalu; 

archite ctu re beh avi o ral of  alu i s
beg in 

p r o cess( o p,  fu nc t)
 begin  c ase o pis
      when "00" => 
         
1 downto_0);
 _   _ Result_:_out _STD_LOGIC_VECTOR_(15 downto 0));
end_alu;

architecture Behavioral of_alu is
begin

process (op, funct)
_begin
  case_op_is
    when "00" => Result <= A+B;
    when_"01"_=> Result_<=_A-B;
_   when others_=> case funct is 
_ _       __  _        _when "0" => Result <= A+B;
_  ___   _     _     _  when "1" => Result <=_A-B;
     _    _ _    _  _ _ when others_=> null;
    end_case;
`end case;
end process;
end_Behavioral;

I am getting the following error
ERROR:HDLParsers:800_-_"E:/Xilinx Projects/alu/alu.vhd" Line_51._Type_of funct_is  __ incompatible_with_type of 0.
ERROR:HDLParsers:800 - "E:/Xilinx Projects/alu/alu.vhd"_Line_52. Type of funct is incompatible with_type of 1.
ERROR:HDLParsers:163 -_"E:/Xilinx_Projects/alu/alu.vhd" Line 55. Unexpected_symbol read: `.

I know it_has something to do with type_mismatches of_'funct' and_'Result' but I dont know how to resolve it, any ideas?

A:

This_analyzes:
library ieee;
use ieee.std_logic_1164.all;
--  library ieee;_ -- successive library_clause has_no_effect
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity_alu_is
 _  port ( 
  _ _   a:  _   in__std_logic_vector (15 downto 0);
  _     b:_    _in__std_logic_vector (15 downto 0);
 _     _funct:  in_ std_logic;
     __ op:    _in_ std_logic_vector (1 downto 0);
 ___    result:_out std_logic_vector (15 downto 0)
 _  );
end alu;

architecture behavioral of alu is
begin

process (op,_funct)
 begin
 _  case op is
___     when "00" => 
 _ _  _     