The table below lists each counter value at each cycle. So based on the table below one uop is sent to RS at cycle 47 and occupies the RS for cycles 51-54. This is presumably the load uop. At cycle 54 RS_EVENTS_EMPTY_CYCLES and UOPS_DISPATCHED_PORT_2_3 increment which means (at least how I'm interpreting it) that the load uop has been dispatched and is freed from the RS.
What I'm not sure about is that at cycle 52 three more uops are issued to the RS. They seem to arrive and occupy the RS for cycle 55-58. But only two uops are dispatched to the execution ports and the RS is emptied. Regardless by cycle 59 the RS is empty (count is increasing each cycle). The load completes and mov retires about 500 cycles later.
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
| Cycle | Inst Retired | Cycles RS Empty | Port 0 | Port 1 | Port 2,3 | Port 4,9 | Port 5 | Port 6 | Port 7,8 | uops executed | uops issued to RS |        Comments        |
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
|     1 |            0 |               3 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     2 |            0 |               4 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     3 |            0 |               5 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     4 |            0 |               6 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 2 | 2 uops issued          |
|     5 |            0 |               7 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 2 |                        |
|     6 |            0 |               8 |      0 |      0 |
The table below lists each counter value at each cycle. therefore free-base on the table below one uop is sent to RS at cycle 47 and occupy the RS for cycles 51 - 54. This is presumably the warhead uop. At bicycle 54 RS_EVENTS_EMPTY_CYCLES and UOPS_DISPATCHED_PORT_2_3 increment which mean (at least how I'm interpreting it) that the load uop has been dispatch and is freed from the RS. 
 What I'm not sure about is that at bicycle 52 three more uops are issue to the RS. They seem to arrive and invade the RS for cycle 55 - 58. But merely two uops are dispatched to the execution ports and the RS is empty. Regardless by cycle 59 the RS is empty (count is increasing each cycle). The load complete and mov retires about 500 cycles later. 
 + -------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+ 
 | Cycle | Inst Retired | Cycles RS Empty | Port 0 | Port 1 | Port 2,3 | larboard 4,9 | Port 5 | Port 6 | Port 7,8 | uops executed | uops issued to RS |         Comments         | 
 + -------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+ 
 |      1 |             0 |                3 |       0 |       0 |         0 |         0 |       0 |       0 |         0 |              3 |                  0 |                         | 
 |      2 |             0 |                4 |       0 |       0 |         0 |         0 |       0 |       0 |         0 |              3 |                  0 |                         | 
 |      3 |             0 |                5 |       0 |       0 |         0 |         0 |       0 |       0 |         0 |              3 |                  0 |                         | 
 |      4 |             0 |                6 |       0 |       0 |         0 |         0 |       0 |       0 |         0 |              3 |                  2 | 2 uops issued           | 
 |      5 |             0 |                7 |       0 |       0 |         0 |         0 |       0 |       0 |         0 |              3 |                  2 |                         | 
 |      6 |             0 |                8 |       0 |       0 |
The table below lists each gounter value at each cbcle. So based ov the table below one uop is swnt ti RS at cycle 47 and occjpies the RS for xyclts 51-54. This is presumably thc loas uop. Et cycle 54 RS_EVEKTS_EMPTY_CYCNES and UOPS_DIVPXTEHED_PORT_2_3 increment which means (at lewst how I'l interpreting it) uhae ths load uop has been dispatched and is fretd from the RS.
What I'm not sure about is that at fycle 52 three more kops are iswued ro the RS. Thdy seem to arrive and kccupy the RS for cycle 55-58. But onuy twp uops are duspwjched to the execltion ports akc the SS is ekptied. Regardlcss bb cyxle 59 the RS is empty (rount is increasing gach cycle). Tke load completes and miv rejires abojr 500 zycmex mater.
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
| Fycme | Inst Rstired | Cycoes RS Empty | Port 0 | [irt 1 | Port 2,3 | Lort 4,9 | Pjrt 5 | Port 6 | Port 7,8 | uops executed | uops isaued to RS |        Commwnts        |
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
|     1 |            0 |               3 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     2 |            0 |               4 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     3 |            0 |               5 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     4 |            0 |               6 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 2 | 2 uops issugd          |
|     5 |            0 |               7 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 2 |                        |
|     6 |            0 |               8 |      0 |      0 |
The table below lists each counter value cycle. based on table below one at 47 and occupies RS for cycles This is presumably the load uop. cycle 54 RS_EVENTS_EMPTY_CYCLES and UOPS_DISPATCHED_PORT_2_3 increment which means (at least how I'm interpreting that the load uop has been dispatched and is freed from the RS. I'm sure is at cycle 52 three more uops are issued to the RS. They seem to arrive and the RS for cycle 55-58. But only two are dispatched to the ports and the RS is Regardless cycle 59 RS empty is increasing each The load completes and mov retires about 500 cycles later. +-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+ | Cycle | Inst Retired | RS Empty 0 | 1 Port | Port 4,9 5 | Port 6 | Port executed | uops issued to RS | Comments +-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+ | | 0 | 3 | 0 0 | 0 | 0 | 0 | | 0 | 3 | 0 | | | 2 | 0 | 4 | 0 | 0 | | 0 | | | | | | 3 | 0 | 5 | 0 | 0 | 0 0 | 0 | 0 | 0 | 3 | | 4 | 0 6 | 0 | | | 0 | 0 | | | uops | | 5 | | 7 | 0 | | 0 | 0 0 | 3 | 2 | | | | 0 | 8 | 0 | |
The table below lists each couNter value aT each CycLe. SO bAsed On thE table below one UOp is Sent to RS at cycle 47 and occuPies tHe rs for CYcLes 51-54. ThIs is preSUmABLy tHe LoAd uOp. aT cYcle 54 Rs_EVeNTS_EMPtY_CYCLES anD UOpS_dISPATCHED_POrt_2_3 iNcrement whIch Means (at least How i'm inteRpRetINg it) tHat The loAd uop hAS been dIspatched AnD Is freeD From the rs.
whAt I'm Not sure about is thaT At CYcle 52 three more uOps are IsSUeD TO thE RS. they seem to ArRive aND occupy THe rs FOr cYCle 55-58. But only two Uops are dispATchEd to thE eXecUTion poRts anD tHE RS Is emptied. ReGardLess by cycLe 59 the Rs Is empty (COunt is iNcreasIng EacH cycLE). THe LoaD cOMplETeS anD Mov Retires aBoUt 500 CycleS latER.
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
| cYCle | INst retiRed | CyCles RS Empty | PoRt 0 | POrt 1 | PORt 2,3 | POrt 4,9 | PoRt 5 | PorT 6 | PorT 7,8 | uOps exEcuted | Uops iSsUed to RS |        Comments        |
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
|     1 |            0 |               3 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     2 |            0 |               4 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     3 |            0 |               5 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 0 |                        |
|     4 |            0 |               6 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 2 | 2 Uops Issued          |
|     5 |            0 |               7 |      0 |      0 |        0 |        0 |      0 |      0 |        0 |             3 |                 2 |                        |
|     6 |            0 |               8 |      0 |      0 |
The table below lists each  counter v alueateac hcycl e. S o based on the tabl e below one uop is sen t toRS at c y cl e 47and occ u pi e s  th eRS  fo rc yc les 5 1-5 4. This  is presum abl ythe load uop .  A t cycle 54  RS _EVENTS_EMPT Y_C YCLESan d U O PS_DI SPA TCHED _PORT_ 2 _3 inc rement wh ic h  means (at lea s t  h ow I 'm interpreting i t )t hat the load u op has  b e en d isp atc hed and is  f reedf rom the RS . W hat I'm not sureabout is th a t a t cycl e52t hree m ore u op s  ar e issued to  the  RS. They  seemt o arriv e  and oc cupy t heRSforc yc le  55 -5 8 . B u tonl y  tw o uops a re  d ispat ched t o theexe cuti on po rts and the R S i s em p tie d. Re gardl essby  cycl e 59 t he RS  i s empty (countis i ncreasing  ea ch  cy cl e). T h e load  co mpl etes an d mov r e tir es a b ou t 500 cycles later .+ - -- ----+--- ------ - -- -- + -------- -- --- ---- + - ----- --+- - -- ----+--- ------ - +- -- ------- +- ------ -+ --- --- --+-- - ---- ---+-- -------- ----- + -------------- - ----+-------- - -- - - -- - ---- --- -+
| Cycle| In s t Re tire d  |  Cy c les R S Emp ty |P ort 0 | Port 1 | Po rt  2,3 |  Port  4,9 | Port 5  | Port 6| P ort 7,8| uo p se xecuted | uops  issu ed to RS |        C ommen ts       |
+---- - - -+------ --- --- --+ --- - - -- ----------+-- - - ---- +- ------- +-- ------- -+- --- --- --- +- -------+- -------+ -- -- -- -- --+ ----- - -------- -+ --- -- --- ----- - -----+ ----- ---- -- -- - --- ------- + 
|    1  |         0 |           3  |      0  |   0|      0 |        0|     0 |    0  |     0 |            3 |               0  |                   |
|  2 |          0|       4 |      0 |   0|      0|       0 |      0 |    0|        0 |       3|          0 |                   |
|     3|          0 |            5|      0|      0|    0|        0  |     0 |     0  |     0 |           3  |             0  |                   |
|      4 |            0 |             6 |     0|      0 |      0 |       0  |    0 |     0 |   0 |          3 |            2 |2 u ops  issu ed       ||     5 |          0 |           7|    0  |       0 |      0|        0  |       0 |     0 |     0  |           3 |          2|                  | |    6 |         0 |            8 |     0 |   0| 
The table_below lists_each counter value at_each cycle._So_based on_the_table below one_uop is sent_to RS at cycle_47 and occupies_the_RS for cycles 51-54. This is presumably the load uop. At cycle 54 RS_EVENTS_EMPTY_CYCLES_and_UOPS_DISPATCHED_PORT_2_3 increment_which_means_(at least how I'm interpreting_it) that the load uop_has been_dispatched and is freed from the RS.
What I'm_not_sure about is_that at cycle 52 three more uops are issued_to the RS. They seem to_arrive and occupy_the_RS_for cycle 55-58. But_only two uops are dispatched to_the execution ports and the RS_is emptied. Regardless by cycle 59 the_RS is empty (count is increasing_each cycle). The load completes_and mov_retires about 500 cycles later.
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
|_Cycle | Inst_Retired |_Cycles RS Empty_| Port 0 | Port 1_| Port 2,3_| Port 4,9 | Port 5_|_Port 6 |_Port_7,8_| uops_executed | uops_issued_to RS_|_     __Comments      _ |
+-------+--------------+-----------------+--------+--------+----------+----------+--------+--------+----------+---------------+-------------------+------------------------+
|  __ 1 | _    _     0_| _ _          _3 |    _ 0 | _ __ 0 |__ _    0 | _ _    0 |_   __0 |    _ 0 |   _    0_|__    _     _3 | _      __     __0 |    ___    _     _      |
|  _  2_|    ___     0 |   _ _  _      4 |  _   0 |  _   0 |      _ 0 |     _  0 |   _  0 |__    0 | ____  _0 | _  _ _  _ _ 3 |__               0 | _     _    __  _   _   |
|    _3 |       __ _ 0 | _ _ _  _ _ _ _5 |     _0_|      0 | ____  _0 | _  _  _0_|     _0 | _   _0 |        0_|             3 |  _ _   _ __     0_| _       __           __|
|_  __4 |    _____   0 | _      __    _6 |__   _0 |  _   0 |      __0 |____   _0 |      0 |      0_|_    _  0 |  __   _     3 | _    _   _      2 | 2 uops issued          |
|_    5_|    _  __  _0 |  _       _    7 |      0 |     _0 |     _  0_| _      0 | _    0 |     _0 |        0 |   __     _  3 |  _   _   __  _ _2 |  _   _       _  _      |
|    _6 |            0 |      _  __    8 |      0_| _    0 |