As the resolution of ADCs increases from 12 to 16 bits and higher, the difficulty in testing the “no- missing-codes” specification grows proportionately. To fully guarantee no missing codes for a 16-bit ADC requires testing all 216 –1 possible output codes. Undertaking such a production test could add much extra cost to the ADC without a quick method for testing all codes. Fortunately, a simple approach can test the no-missing-codes specification for a 16-bit ADC—in this case, a 10-µsec ADS7805, in typically less than 7 sec (Figure 1).

This missing-codes tester comprises an analog ADC servo loop that you can also use to measure the integral nonlinearity and differential nonlinearity of 16-bit ADCs (Reference 1). The servo loop works by finding the ADC's input voltage that corresponds to the Code i -to-Code i+1 output transition. The circuit uses an 18-bit DAC729, IC 1 , as a pedestal DAC to quickly set the input voltage to the ADC under test to approximately the level corresponding to the programmed input code. The output transfer function of the pedestal DAC matches the transfer function of the ADC under test—in this case, ±10V for the ADS7805. The DAC729 MSB bit-adjustment pins, pins 36 to 40, are open because the unadjusted DAC729's linearity is sufficient for performing only the ADC missing codes test.

The procedure successively tests each possible output code of the ADC under test by programming a PC with the desired 16-bit code, Code i . Applying a 100-kHz clock to pin 24 of the ADC provides for continuous operation of the ADS7805. When the ADC completes a conversion, two 8-bit 74HC682 magnitude comparators, IC 2 and IC 3 , and accompanying interface logic, IC 4 and IC 5 , compare the ADC's output code to the programmed data-bus code. The signal output from IC 4A signifies whether the input voltage to the ADC needs to increase or decrease to achieve an ADC output equal to the programmed Code i . The signal from IC 4B indicates whether the output code from the ADC matches Code i ; a logic-low level indicates that the code was found.

Because both the and signals from IC 4A and IC 4B , respectively, can be momentarily indeterminate during the ADC conversion, the circuit latches these signals into flip-flops IC 6 and IC 7 when the conversion is complete. The clock signal for these latches is a delayed version—approximately 200 nsec—of the rising edge of the ADS7805 end-of-conversion signal, . The circuit uses the signal clocked into IC 6 to control the ramp direction of integrator op amp IC 8 . The 0 to 5V output of HC-type flip-flop IC 6 directly drives the integrator input of IC 8 . R 1 , R 2 , and the –15V power supply shift the 0 to 5V output level to approximately –2 to +2V. C 1 filters any high-speed transients that arise from the switching action of IC 6 's output.

Op amp IC 9 attenuates the integrator's output by 100 and sums the result with the output of the pedestal DAC. For the component values of IC 8 's integrator stage, the maximum ramp rate at the input of the ADC is approximately 2 µV/µsec, which is equivalent to 0.067 LSB per conversion. Feedback of the servo-loop circuit maintains the dc level of the integrator's output by continuously adjusting the input voltage of the ADS7805 to the level required for the Code i -to-Code i+1 output transition. Thus, the servo-loop circuit locks in the input voltage to the ADC to maintain the Code i -to-Code i+1 output transition.

The signal that the circuit clocks into flip-flop IC 7 indicates whether the programmed Code i exists for the ADC under test. The output of IC 7 connects to an input control line, CNTL 6 , on the controlling PC's I/O card. After the control program sends each new Code i to the tester, the PC reads the state of CNTL 6 . A high level on CNTL 6 indicates that Code i exists and is not missing.

Align pedestal DAC with ADC under test

Before starting the missing-codes test, the procedure requires alignment of the pedestal DAC's endpoints with those of the ADC under test. This alignment ensures that the pedestal DAC's output closely matches the corresponding ADC input voltage for all codes programmed to the tester. Under this condition, the voltage needed to sum with the pedestal DAC output should be only a few LSBs (referred to the ADC input), thus keeping the dc output level of the integrating op amp, IC 8 , close to 0V. Thus, for each Code i setting, the integrator output never needs to slew very far from the dc level of 0V.

Comparators IC 10A and IC 10B form a window comparator for the output of IC 8 . The window voltage is equal to 100 mV, which corresponds to approximately 3.3 LSBs, referred to the ADS7805 input. I/O control lines CNTL 4 and CNTL 5 read the outputs of IC 10A and IC 10B , respectively to determine the level of the integrator's output voltage. If CNTL 4 is high, the integrator output is more than 100 mV. If CNTL 5 is high, the integrator is less than –100 mV. If both CNTL 4 and CNTL 5 are low, the integrator output is within the 100-mV window.

A dual, 12-bit latched DAC, IC 11 , adjusts the pedestal DAC's endpoints. V OUT1 and V OUT2 adjust the pedestal DAC's offset and gain, respectively, to the endpoints of the ADC under test. First, the control program adjusts the DAC729's offset by programming and latching Code i to FFFE (hex) and then counting up or down accordingly so that V OUT1 brings the integrator voltage within the 100-mV setting of the window comparator. Next, the program sets IC 1 's gain by programming and latching Code i to 0000 and again counting up or down so that V OUT2 brings the integrator output to a null.

The same I/O data bus programs both the DAC2813 and the 74HC682 digital comparators. The 74HC139 decoder, IC 12 , selects either the input Code i latches, IC 13 and IC 14 , or the internal latches of the DAC2813. IC 11 has two input-latch-enable pins, one for each of its output DACs. Input loads the DAC's input latch data into the internal latches, thus simultaneously programming both V OUT1 and V OUT2 . I/O control lines CNTL 0 and CNTL 1 select the desired latch, and CNTL 2 strobes in the data from the bus.

Listing 1 contains the Pascal program for controlling the missing-codes tester. The section of the program that outputs codes to the data bus and reads the state of the CNTL 6 line is based on a custom I/O card built with an Intel 8255A programmable peripheral interface. The I/O routines are for reference only, and you should modify them according to the protocol used by the user's specific I/O card.

The EndPoints procedure in the listing aligns the offset and gain of the pedestal DAC to that of the ADC under test. It programs IC 11 as necessary to null the integrator output for both offset and gain. The Detect procedure programs each Code i , from 0 to 65534, to the missing-codes test board. After programming each new code, the program reads the state of the CNTL 6 line. If CNTL 6 is a logic high, indicating the programmed code exists, the Count variable is incremented. The Detect procedure loops for the given code until a minimum number of occurrences are detected, set by the variable MinCount. The variable MaxTry sets the maximum number of times that the program trys to find Code i . The program loops for an appropriate delay time to ensure that measurements of the state of the line occur only once per analog-to-digital conversion or, in the case of the ADS7805, approximately every 10 µsec. For the variable MinCount set to 3 and MaxTry set to 30, the missing-codes tester can test the 10-µsec ADS7805 for all 216 –1 codes in less than 7 sec. (DI #2334)

REFERENCE

1.Shill, Mark A, “Servo loop speeds tests of 16-bit ADCs,” Electronic Design, Feb 6, 1995, pg 93.

