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1 | static int32_t virtio_net_flush_tx(VirtIONet *n, VirtQueue *vq) { VirtQueueElement elem; int32_t num_packets = 0; if (!(n->vdev.status & VIRTIO_CONFIG_S_DRIVER_OK)) { return num_packets; } if (n->async_tx.elem.out_num) { virtio_queue_set_notification(n->tx_vq, 0); return num_packets; } while (virtqueue_pop(vq, &elem)) { ssize_t ret, len = 0; unsigned int out_num = elem.out_num; struct iovec *out_sg = &elem.out_sg[0]; unsigned hdr_len; /* hdr_len refers to the header received from the guest */ hdr_len = n->mergeable_rx_bufs ? sizeof(struct virtio_net_hdr_mrg_rxbuf) : sizeof(struct virtio_net_hdr); if (out_num < 1 || out_sg->iov_len != hdr_len) { error_report("virtio-net header not in first element"); exit(1); } /* ignore the header if GSO is not supported */ if (!n->has_vnet_hdr) { out_num--; out_sg++; len += hdr_len; } else if (n->mergeable_rx_bufs) { /* tapfd expects a struct virtio_net_hdr */ hdr_len -= sizeof(struct virtio_net_hdr); out_sg->iov_len -= hdr_len; len += hdr_len; } ret = qemu_sendv_packet_async(&n->nic->nc, out_sg, out_num, virtio_net_tx_complete); if (ret == 0) { virtio_queue_set_notification(n->tx_vq, 0); n->async_tx.elem = elem; n->async_tx.len = len; return -EBUSY; } len += ret; virtqueue_push(vq, &elem, len); virtio_notify(&n->vdev, vq); if (++num_packets >= n->tx_burst) { break; } } return num_packets; } | 19,988 |
1 | static int vmdk_read(BlockDriverState *bs, int64_t sector_num, uint8_t *buf, int nb_sectors) { BDRVVmdkState *s = bs->opaque; int ret; uint64_t n, index_in_cluster; VmdkExtent *extent = NULL; uint64_t cluster_offset; while (nb_sectors > 0) { extent = find_extent(s, sector_num, extent); if (!extent) { return -EIO; } ret = get_cluster_offset( bs, extent, NULL, sector_num << 9, 0, &cluster_offset); index_in_cluster = sector_num % extent->cluster_sectors; n = extent->cluster_sectors - index_in_cluster; if (n > nb_sectors) { n = nb_sectors; } if (ret) { /* if not allocated, try to read from parent image, if exist */ if (bs->backing_hd) { if (!vmdk_is_cid_valid(bs)) { return -EINVAL; } ret = bdrv_read(bs->backing_hd, sector_num, buf, n); if (ret < 0) { return ret; } } else { memset(buf, 0, 512 * n); } } else { ret = vmdk_read_extent(extent, cluster_offset, index_in_cluster * 512, buf, n); if (ret) { return ret; } } nb_sectors -= n; sector_num += n; buf += n * 512; } return 0; } | 19,989 |
1 | static void gen_mfsr(DisasContext *ctx) { #if defined(CONFIG_USER_ONLY) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); #else TCGv t0; if (unlikely(ctx->pr)) { gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); return; } t0 = tcg_const_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); #endif } | 19,990 |
1 | void fd_start_incoming_migration(const char *infd, Error **errp) { int fd; QEMUFile *f; DPRINTF("Attempting to start an incoming migration via fd\n"); fd = strtol(infd, NULL, 0); f = qemu_fdopen(fd, "rb"); if(f == NULL) { error_setg_errno(errp, errno, "failed to open the source descriptor"); return; } qemu_set_fd_handler2(fd, NULL, fd_accept_incoming_migration, NULL, f); } | 19,992 |
1 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu) { mmu_ctx_t ctx; int access_type; int ret = 0; if (rw == 2) { /* code access */ rw = 0; access_type = ACCESS_CODE; } else { /* data access */ /* XXX: put correct access by using cpu_restore_state() correctly */ access_type = ACCESS_INT; // access_type = env->access_type; } ret = get_physical_address(env, &ctx, address, rw, access_type, 1); if (ret == 0) { ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, mmu_idx, is_softmmu); } else if (ret < 0) { #if defined (DEBUG_MMU) if (loglevel != 0) cpu_dump_state(env, logfile, fprintf, 0); #endif if (access_type == ACCESS_CODE) { switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: env->exception_index = POWERPC_EXCP_IFTLB; env->error_code = 1 << 18; env->spr[SPR_IMISS] = address; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_74xx: env->exception_index = POWERPC_EXCP_IFTLB; goto tlb_miss_74xx; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: env->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: #endif env->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; break; case POWERPC_MMU_BOOKE: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(env, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; } break; case -2: /* Access rights violation */ env->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; break; case -3: /* No execute protection violation */ env->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; case -4: /* Direct store exception */ /* No code fetch is allowed in direct-store areas */ env->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; #if defined(TARGET_PPC64) case -5: /* No match in segment table */ env->exception_index = POWERPC_EXCP_ISEG; env->error_code = 0; break; #endif } } else { switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (rw == 1) { env->exception_index = POWERPC_EXCP_DSTLB; env->error_code = 1 << 16; } else { env->exception_index = POWERPC_EXCP_DLTLB; env->error_code = 0; } env->spr[SPR_DMISS] = address; env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; tlb_miss: env->error_code |= ctx.key << 19; env->spr[SPR_HASH1] = ctx.pg_addr[0]; env->spr[SPR_HASH2] = ctx.pg_addr[1]; break; case POWERPC_MMU_SOFT_74xx: if (rw == 1) { env->exception_index = POWERPC_EXCP_DSTLB; } else { env->exception_index = POWERPC_EXCP_DLTLB; } tlb_miss_74xx: /* Implement LRU algorithm */ env->error_code = ctx.key << 19; env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) | ((env->last_way + 1) & (env->nb_ways - 1)); env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; break; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: env->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; if (rw) env->spr[SPR_40x_ESR] = 0x00800000; else env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: #endif env->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) env->spr[SPR_DSISR] = 0x42000000; else env->spr[SPR_DSISR] = 0x40000000; break; case POWERPC_MMU_BOOKE: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(env, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; } break; case -2: /* Access rights violation */ env->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) env->spr[SPR_DSISR] = 0x0A000000; else env->spr[SPR_DSISR] = 0x08000000; break; case -4: /* Direct store exception */ switch (access_type) { case ACCESS_FLOAT: /* Floating point load/store */ env->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = address; break; case ACCESS_RES: /* lwarx, ldarx or stwcx. */ env->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) env->spr[SPR_DSISR] = 0x06000000; else env->spr[SPR_DSISR] = 0x04000000; break; case ACCESS_EXT: /* eciwx or ecowx */ env->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) env->spr[SPR_DSISR] = 0x06100000; else env->spr[SPR_DSISR] = 0x04100000; break; default: printf("DSI: invalid exception (%d)\n", ret); env->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; env->spr[SPR_DAR] = address; break; } break; #if defined(TARGET_PPC64) case -5: /* No match in segment table */ env->exception_index = POWERPC_EXCP_DSEG; env->error_code = 0; env->spr[SPR_DAR] = address; break; #endif } } #if 0 printf("%s: set exception to %d %02x\n", __func__, env->exception, env->error_code); #endif ret = 1; } return ret; } | 19,994 |
1 | void do_POWER_rac (void) { #if 0 mmu_ctx_t ctx; /* We don't have to generate many instances of this instruction, * as rac is supervisor only. */ if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0) T0 = ctx.raddr; #endif } | 19,995 |
1 | hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; target_ulong raddr; int prot; uint64_t asc = env->psw.mask & PSW_MASK_ASC; /* 31-Bit mode */ if (!(env->psw.mask & PSW_MASK_64)) { vaddr &= 0x7fffffff; } mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false); return raddr; } | 19,997 |
1 | static void msix_handle_mask_update(PCIDevice *dev, int vector) { if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) { msix_clr_pending(dev, vector); msix_notify(dev, vector); } } | 20,001 |
0 | static int dct_quantize_c(MpegEncContext *s, DCTELEM *block, int n, int qscale, int *overflow) { int i, j, level, last_non_zero, q; const int *qmat; int bias; int max=0; unsigned int threshold1, threshold2; av_fdct (block); /* we need this permutation so that we correct the IDCT permutation. will be moved into DCT code */ block_permute(block); if (s->mb_intra) { if (!s->h263_aic) { if (n < 4) q = s->y_dc_scale; else q = s->c_dc_scale; q = q << 3; } else /* For AIC we skip quant/dequant of INTRADC */ q = 1 << 3; /* note: block[0] is assumed to be positive */ block[0] = (block[0] + (q >> 1)) / q; i = 1; last_non_zero = 0; qmat = s->q_intra_matrix[qscale]; bias= s->intra_quant_bias<<(QMAT_SHIFT - 3 - QUANT_BIAS_SHIFT); } else { i = 0; last_non_zero = -1; qmat = s->q_inter_matrix[qscale]; bias= s->inter_quant_bias<<(QMAT_SHIFT - 3 - QUANT_BIAS_SHIFT); } threshold1= (1<<(QMAT_SHIFT - 3)) - bias - 1; threshold2= threshold1<<1; for(;i<64;i++) { j = zigzag_direct[i]; level = block[j]; level = level * qmat[j]; // if( bias+level >= (1<<(QMAT_SHIFT - 3)) // || bias-level >= (1<<(QMAT_SHIFT - 3))){ if(((unsigned)(level+threshold1))>threshold2){ if(level>0){ level= (bias + level)>>(QMAT_SHIFT - 3); block[j]= level; }else{ level= (bias - level)>>(QMAT_SHIFT - 3); block[j]= -level; } max |=level; last_non_zero = i; }else{ block[j]=0; } } *overflow= s->max_qcoeff < max; //overflow might have happend return last_non_zero; } | 20,002 |
0 | static void radix_sort(RCCMPEntry *data, int size) { int buckets[RADIX_PASSES][NBUCKETS]; RCCMPEntry *tmp = av_malloc_array(size, sizeof(*tmp)); radix_count(data, size, buckets); radix_sort_pass(tmp, data, size, buckets[0], 0); radix_sort_pass(data, tmp, size, buckets[1], 1); if (buckets[2][NBUCKETS - 1] || buckets[3][NBUCKETS - 1]) { radix_sort_pass(tmp, data, size, buckets[2], 2); radix_sort_pass(data, tmp, size, buckets[3], 3); } av_free(tmp); } | 20,003 |
0 | static inline void mix_3f_1r_to_stereo(AC3DecodeContext *ctx) { int i; float (*output)[256] = ctx->audio_block.block_output; for (i = 0; i < 256; i++) { output[1][i] += (output[2][i] + output[4][i]); output[2][i] += (output[3][i] + output[4][i]); } memset(output[3], 0, sizeof(output[3])); memset(output[4], 0, sizeof(output[4])); } | 20,004 |
0 | static int check(AVIOContext *pb, int64_t pos, uint32_t *ret_header) { int64_t ret = avio_seek(pb, pos, SEEK_SET); unsigned header; MPADecodeHeader sd; if (ret < 0) return ret; header = avio_rb32(pb); if (ff_mpa_check_header(header) < 0) return -1; if (avpriv_mpegaudio_decode_header(&sd, header) == 1) return -1; if (ret_header) *ret_header = header; return sd.frame_size; } | 20,006 |
0 | void ff_put_h264_qpel4_mc30_msa(uint8_t *dst, const uint8_t *src, ptrdiff_t stride) { avc_luma_hz_qrt_4w_msa(src - 2, stride, dst, stride, 4, 1); } | 20,007 |
0 | void ff_h264_pred_init_x86(H264PredContext *h, int codec_id, const int bit_depth, const int chroma_format_idc) { #if HAVE_YASM int mm_flags = av_get_cpu_flags(); if (bit_depth == 8) { if (mm_flags & AV_CPU_FLAG_MMX) { h->pred16x16[VERT_PRED8x8 ] = ff_pred16x16_vertical_mmx; h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_mmx; if (chroma_format_idc == 1) { h->pred8x8 [VERT_PRED8x8 ] = ff_pred8x8_vertical_mmx; h->pred8x8 [HOR_PRED8x8 ] = ff_pred8x8_horizontal_mmx; } if (codec_id == AV_CODEC_ID_VP8) { h->pred16x16[PLANE_PRED8x8 ] = ff_pred16x16_tm_vp8_mmx; h->pred8x8 [PLANE_PRED8x8 ] = ff_pred8x8_tm_vp8_mmx; h->pred4x4 [TM_VP8_PRED ] = ff_pred4x4_tm_vp8_mmx; } else { if (chroma_format_idc == 1) h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_plane_mmx; if (codec_id == AV_CODEC_ID_SVQ3) { if (mm_flags & AV_CPU_FLAG_CMOV) h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_svq3_mmx; } else if (codec_id == AV_CODEC_ID_RV40) { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_rv40_mmx; } else { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_h264_mmx; } } } if (mm_flags & AV_CPU_FLAG_MMXEXT) { h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_mmx2; h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_mmx2; if (chroma_format_idc == 1) h->pred8x8[HOR_PRED8x8 ] = ff_pred8x8_horizontal_mmx2; h->pred8x8l [TOP_DC_PRED ] = ff_pred8x8l_top_dc_mmxext; h->pred8x8l [DC_PRED ] = ff_pred8x8l_dc_mmxext; h->pred8x8l [HOR_PRED ] = ff_pred8x8l_horizontal_mmxext; h->pred8x8l [VERT_PRED ] = ff_pred8x8l_vertical_mmxext; h->pred8x8l [DIAG_DOWN_RIGHT_PRED ] = ff_pred8x8l_down_right_mmxext; h->pred8x8l [VERT_RIGHT_PRED ] = ff_pred8x8l_vertical_right_mmxext; h->pred8x8l [HOR_UP_PRED ] = ff_pred8x8l_horizontal_up_mmxext; h->pred8x8l [DIAG_DOWN_LEFT_PRED ] = ff_pred8x8l_down_left_mmxext; h->pred8x8l [HOR_DOWN_PRED ] = ff_pred8x8l_horizontal_down_mmxext; h->pred4x4 [DIAG_DOWN_RIGHT_PRED ] = ff_pred4x4_down_right_mmxext; h->pred4x4 [VERT_RIGHT_PRED ] = ff_pred4x4_vertical_right_mmxext; h->pred4x4 [HOR_DOWN_PRED ] = ff_pred4x4_horizontal_down_mmxext; h->pred4x4 [DC_PRED ] = ff_pred4x4_dc_mmxext; if (codec_id == AV_CODEC_ID_VP8 || codec_id == AV_CODEC_ID_H264) { h->pred4x4 [DIAG_DOWN_LEFT_PRED] = ff_pred4x4_down_left_mmxext; } if (codec_id == AV_CODEC_ID_SVQ3 || codec_id == AV_CODEC_ID_H264) { h->pred4x4 [VERT_LEFT_PRED ] = ff_pred4x4_vertical_left_mmxext; } if (codec_id != AV_CODEC_ID_RV40) { h->pred4x4 [HOR_UP_PRED ] = ff_pred4x4_horizontal_up_mmxext; } if (codec_id == AV_CODEC_ID_SVQ3 || codec_id == AV_CODEC_ID_H264) { if (chroma_format_idc == 1) { h->pred8x8[TOP_DC_PRED8x8 ] = ff_pred8x8_top_dc_mmxext; h->pred8x8[DC_PRED8x8 ] = ff_pred8x8_dc_mmxext; } } if (codec_id == AV_CODEC_ID_VP8) { h->pred16x16[PLANE_PRED8x8 ] = ff_pred16x16_tm_vp8_mmx2; h->pred8x8 [DC_PRED8x8 ] = ff_pred8x8_dc_rv40_mmxext; h->pred8x8 [PLANE_PRED8x8 ] = ff_pred8x8_tm_vp8_mmx2; h->pred4x4 [TM_VP8_PRED ] = ff_pred4x4_tm_vp8_mmx2; h->pred4x4 [VERT_PRED ] = ff_pred4x4_vertical_vp8_mmxext; } else { if (chroma_format_idc == 1) h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_plane_mmx2; if (codec_id == AV_CODEC_ID_SVQ3) { h->pred16x16[PLANE_PRED8x8 ] = ff_pred16x16_plane_svq3_mmx2; } else if (codec_id == AV_CODEC_ID_RV40) { h->pred16x16[PLANE_PRED8x8 ] = ff_pred16x16_plane_rv40_mmx2; } else { h->pred16x16[PLANE_PRED8x8 ] = ff_pred16x16_plane_h264_mmx2; } } } if (mm_flags & AV_CPU_FLAG_SSE) { h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_sse; } if (mm_flags & AV_CPU_FLAG_SSE2) { h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_sse2; h->pred8x8l [DIAG_DOWN_LEFT_PRED ] = ff_pred8x8l_down_left_sse2; h->pred8x8l [DIAG_DOWN_RIGHT_PRED ] = ff_pred8x8l_down_right_sse2; h->pred8x8l [VERT_RIGHT_PRED ] = ff_pred8x8l_vertical_right_sse2; h->pred8x8l [VERT_LEFT_PRED ] = ff_pred8x8l_vertical_left_sse2; h->pred8x8l [HOR_DOWN_PRED ] = ff_pred8x8l_horizontal_down_sse2; if (codec_id == AV_CODEC_ID_VP8) { h->pred16x16[PLANE_PRED8x8 ] = ff_pred16x16_tm_vp8_sse2; h->pred8x8 [PLANE_PRED8x8 ] = ff_pred8x8_tm_vp8_sse2; } else { if (chroma_format_idc == 1) h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_plane_sse2; if (codec_id == AV_CODEC_ID_SVQ3) { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_svq3_sse2; } else if (codec_id == AV_CODEC_ID_RV40) { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_rv40_sse2; } else { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_h264_sse2; } } } if (mm_flags & AV_CPU_FLAG_SSSE3) { h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_ssse3; h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_ssse3; if (chroma_format_idc == 1) h->pred8x8 [HOR_PRED8x8 ] = ff_pred8x8_horizontal_ssse3; h->pred8x8l [TOP_DC_PRED ] = ff_pred8x8l_top_dc_ssse3; h->pred8x8l [DC_PRED ] = ff_pred8x8l_dc_ssse3; h->pred8x8l [HOR_PRED ] = ff_pred8x8l_horizontal_ssse3; h->pred8x8l [VERT_PRED ] = ff_pred8x8l_vertical_ssse3; h->pred8x8l [DIAG_DOWN_LEFT_PRED ] = ff_pred8x8l_down_left_ssse3; h->pred8x8l [DIAG_DOWN_RIGHT_PRED ] = ff_pred8x8l_down_right_ssse3; h->pred8x8l [VERT_RIGHT_PRED ] = ff_pred8x8l_vertical_right_ssse3; h->pred8x8l [VERT_LEFT_PRED ] = ff_pred8x8l_vertical_left_ssse3; h->pred8x8l [HOR_UP_PRED ] = ff_pred8x8l_horizontal_up_ssse3; h->pred8x8l [HOR_DOWN_PRED ] = ff_pred8x8l_horizontal_down_ssse3; if (codec_id == AV_CODEC_ID_VP8) { h->pred8x8 [PLANE_PRED8x8 ] = ff_pred8x8_tm_vp8_ssse3; h->pred4x4 [TM_VP8_PRED ] = ff_pred4x4_tm_vp8_ssse3; } else { if (chroma_format_idc == 1) h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_plane_ssse3; if (codec_id == AV_CODEC_ID_SVQ3) { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_svq3_ssse3; } else if (codec_id == AV_CODEC_ID_RV40) { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_rv40_ssse3; } else { h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_plane_h264_ssse3; } } } } else if (bit_depth == 10) { if (mm_flags & AV_CPU_FLAG_MMXEXT) { h->pred4x4[DC_PRED ] = ff_pred4x4_dc_10_mmxext; h->pred4x4[HOR_UP_PRED ] = ff_pred4x4_horizontal_up_10_mmxext; if (chroma_format_idc == 1) h->pred8x8[DC_PRED8x8 ] = ff_pred8x8_dc_10_mmxext; h->pred8x8l[DC_128_PRED ] = ff_pred8x8l_128_dc_10_mmxext; h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_10_mmxext; h->pred16x16[TOP_DC_PRED8x8 ] = ff_pred16x16_top_dc_10_mmxext; h->pred16x16[DC_128_PRED8x8 ] = ff_pred16x16_128_dc_10_mmxext; h->pred16x16[LEFT_DC_PRED8x8 ] = ff_pred16x16_left_dc_10_mmxext; h->pred16x16[VERT_PRED8x8 ] = ff_pred16x16_vertical_10_mmxext; h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_10_mmxext; } if (mm_flags & AV_CPU_FLAG_SSE2) { h->pred4x4[DIAG_DOWN_LEFT_PRED ] = ff_pred4x4_down_left_10_sse2; h->pred4x4[DIAG_DOWN_RIGHT_PRED] = ff_pred4x4_down_right_10_sse2; h->pred4x4[VERT_LEFT_PRED ] = ff_pred4x4_vertical_left_10_sse2; h->pred4x4[VERT_RIGHT_PRED ] = ff_pred4x4_vertical_right_10_sse2; h->pred4x4[HOR_DOWN_PRED ] = ff_pred4x4_horizontal_down_10_sse2; if (chroma_format_idc == 1) { h->pred8x8[DC_PRED8x8 ] = ff_pred8x8_dc_10_sse2; h->pred8x8[TOP_DC_PRED8x8 ] = ff_pred8x8_top_dc_10_sse2; h->pred8x8[PLANE_PRED8x8 ] = ff_pred8x8_plane_10_sse2; h->pred8x8[VERT_PRED8x8 ] = ff_pred8x8_vertical_10_sse2; h->pred8x8[HOR_PRED8x8 ] = ff_pred8x8_horizontal_10_sse2; } h->pred8x8l[VERT_PRED ] = ff_pred8x8l_vertical_10_sse2; h->pred8x8l[HOR_PRED ] = ff_pred8x8l_horizontal_10_sse2; h->pred8x8l[DC_PRED ] = ff_pred8x8l_dc_10_sse2; h->pred8x8l[DC_128_PRED ] = ff_pred8x8l_128_dc_10_sse2; h->pred8x8l[TOP_DC_PRED ] = ff_pred8x8l_top_dc_10_sse2; h->pred8x8l[DIAG_DOWN_LEFT_PRED ] = ff_pred8x8l_down_left_10_sse2; h->pred8x8l[DIAG_DOWN_RIGHT_PRED] = ff_pred8x8l_down_right_10_sse2; h->pred8x8l[VERT_RIGHT_PRED ] = ff_pred8x8l_vertical_right_10_sse2; h->pred8x8l[HOR_UP_PRED ] = ff_pred8x8l_horizontal_up_10_sse2; h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_10_sse2; h->pred16x16[TOP_DC_PRED8x8 ] = ff_pred16x16_top_dc_10_sse2; h->pred16x16[DC_128_PRED8x8 ] = ff_pred16x16_128_dc_10_sse2; h->pred16x16[LEFT_DC_PRED8x8 ] = ff_pred16x16_left_dc_10_sse2; h->pred16x16[VERT_PRED8x8 ] = ff_pred16x16_vertical_10_sse2; h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_10_sse2; } if (mm_flags & AV_CPU_FLAG_SSSE3) { h->pred4x4[DIAG_DOWN_RIGHT_PRED] = ff_pred4x4_down_right_10_ssse3; h->pred4x4[VERT_RIGHT_PRED ] = ff_pred4x4_vertical_right_10_ssse3; h->pred4x4[HOR_DOWN_PRED ] = ff_pred4x4_horizontal_down_10_ssse3; h->pred8x8l[HOR_PRED ] = ff_pred8x8l_horizontal_10_ssse3; h->pred8x8l[DIAG_DOWN_LEFT_PRED ] = ff_pred8x8l_down_left_10_ssse3; h->pred8x8l[DIAG_DOWN_RIGHT_PRED] = ff_pred8x8l_down_right_10_ssse3; h->pred8x8l[VERT_RIGHT_PRED ] = ff_pred8x8l_vertical_right_10_ssse3; h->pred8x8l[HOR_UP_PRED ] = ff_pred8x8l_horizontal_up_10_ssse3; } #if HAVE_AVX if (mm_flags & AV_CPU_FLAG_AVX) { h->pred4x4[DIAG_DOWN_LEFT_PRED ] = ff_pred4x4_down_left_10_avx; h->pred4x4[DIAG_DOWN_RIGHT_PRED] = ff_pred4x4_down_right_10_avx; h->pred4x4[VERT_LEFT_PRED ] = ff_pred4x4_vertical_left_10_avx; h->pred4x4[VERT_RIGHT_PRED ] = ff_pred4x4_vertical_right_10_avx; h->pred4x4[HOR_DOWN_PRED ] = ff_pred4x4_horizontal_down_10_avx; h->pred8x8l[VERT_PRED ] = ff_pred8x8l_vertical_10_avx; h->pred8x8l[HOR_PRED ] = ff_pred8x8l_horizontal_10_avx; h->pred8x8l[DC_PRED ] = ff_pred8x8l_dc_10_avx; h->pred8x8l[TOP_DC_PRED ] = ff_pred8x8l_top_dc_10_avx; h->pred8x8l[DIAG_DOWN_RIGHT_PRED] = ff_pred8x8l_down_right_10_avx; h->pred8x8l[DIAG_DOWN_LEFT_PRED ] = ff_pred8x8l_down_left_10_avx; h->pred8x8l[VERT_RIGHT_PRED ] = ff_pred8x8l_vertical_right_10_avx; h->pred8x8l[HOR_UP_PRED ] = ff_pred8x8l_horizontal_up_10_avx; } #endif /* HAVE_AVX */ } #endif /* HAVE_YASM */ } | 20,008 |
1 | static void qobject_input_optional(Visitor *v, const char *name, bool *present) { QObjectInputVisitor *qiv = to_qiv(v); QObject *qobj = qobject_input_get_object(qiv, name, false, NULL); if (!qobj) { *present = false; return; } *present = true; } | 20,010 |
1 | static int coroutine_fn copy_sectors(BlockDriverState *bs, uint64_t start_sect, uint64_t cluster_offset, int n_start, int n_end) { BDRVQcowState *s = bs->opaque; QEMUIOVector qiov; struct iovec iov; int n, ret; n = n_end - n_start; if (n <= 0) { return 0; } iov.iov_len = n * BDRV_SECTOR_SIZE; iov.iov_base = qemu_blockalign(bs, iov.iov_len); qemu_iovec_init_external(&qiov, &iov, 1); BLKDBG_EVENT(bs->file, BLKDBG_COW_READ); if (!bs->drv) { return -ENOMEDIUM; } /* Call .bdrv_co_readv() directly instead of using the public block-layer * interface. This avoids double I/O throttling and request tracking, * which can lead to deadlock when block layer copy-on-read is enabled. */ ret = bs->drv->bdrv_co_readv(bs, start_sect + n_start, n, &qiov); if (ret < 0) { goto out; } if (s->crypt_method) { qcow2_encrypt_sectors(s, start_sect + n_start, iov.iov_base, iov.iov_base, n, 1, &s->aes_encrypt_key); } ret = qcow2_pre_write_overlap_check(bs, 0, cluster_offset + n_start * BDRV_SECTOR_SIZE, n * BDRV_SECTOR_SIZE); if (ret < 0) { goto out; } BLKDBG_EVENT(bs->file, BLKDBG_COW_WRITE); ret = bdrv_co_writev(bs->file, (cluster_offset >> 9) + n_start, n, &qiov); if (ret < 0) { goto out; } ret = 0; out: qemu_vfree(iov.iov_base); return ret; } | 20,011 |
1 | static uint32_t ahci_port_read(AHCIState *s, int port, int offset) { uint32_t val; AHCIPortRegs *pr; pr = &s->dev[port].port_regs; switch (offset) { case PORT_LST_ADDR: val = pr->lst_addr; break; case PORT_LST_ADDR_HI: val = pr->lst_addr_hi; break; case PORT_FIS_ADDR: val = pr->fis_addr; break; case PORT_FIS_ADDR_HI: val = pr->fis_addr_hi; break; case PORT_IRQ_STAT: val = pr->irq_stat; break; case PORT_IRQ_MASK: val = pr->irq_mask; break; case PORT_CMD: val = pr->cmd; break; case PORT_TFDATA: val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | s->dev[port].port.ifs[0].status; break; case PORT_SIG: val = pr->sig; break; case PORT_SCR_STAT: if (s->dev[port].port.ifs[0].bs) { val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; } else { val = SATA_SCR_SSTATUS_DET_NODEV; } break; case PORT_SCR_CTL: val = pr->scr_ctl; break; case PORT_SCR_ERR: val = pr->scr_err; break; case PORT_SCR_ACT: pr->scr_act &= ~s->dev[port].finished; s->dev[port].finished = 0; val = pr->scr_act; break; case PORT_CMD_ISSUE: val = pr->cmd_issue; break; case PORT_RESERVED: default: val = 0; } DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); return val; } | 20,012 |
0 | av_cold void ff_wmv2_common_init(Wmv2Context *w) { MpegEncContext *const s = &w->s; ff_blockdsp_init(&s->bdsp, s->avctx); ff_wmv2dsp_init(&w->wdsp); s->idsp.perm_type = w->wdsp.idct_perm; ff_init_scantable_permutation(s->idsp.idct_permutation, w->wdsp.idct_perm); ff_init_scantable(s->idsp.idct_permutation, &w->abt_scantable[0], ff_wmv2_scantableA); ff_init_scantable(s->idsp.idct_permutation, &w->abt_scantable[1], ff_wmv2_scantableB); ff_init_scantable(s->idsp.idct_permutation, &s->intra_scantable, ff_wmv1_scantable[1]); ff_init_scantable(s->idsp.idct_permutation, &s->intra_h_scantable, ff_wmv1_scantable[2]); ff_init_scantable(s->idsp.idct_permutation, &s->intra_v_scantable, ff_wmv1_scantable[3]); ff_init_scantable(s->idsp.idct_permutation, &s->inter_scantable, ff_wmv1_scantable[0]); s->idsp.idct_put = w->wdsp.idct_put; s->idsp.idct_add = w->wdsp.idct_add; s->idsp.idct = NULL; } | 20,013 |
1 | static int decode_subpacket(COOKContext *q, uint8_t *inbuffer, int sub_packet_size, int16_t *outbuffer) { int i,j; int value; float* tmp_ptr; /* packet dump */ // for (i=0 ; i<sub_packet_size ; i++) { // av_log(NULL, AV_LOG_ERROR, "%02x", inbuffer[i]); // } // av_log(NULL, AV_LOG_ERROR, "\n"); decode_bytes(inbuffer, q->decoded_bytes_buffer, sub_packet_size); init_get_bits(&q->gb, q->decoded_bytes_buffer, sub_packet_size*8); decode_gain_info(&q->gb, &q->gain_current); memcpy(&q->gain_copy, &q->gain_current ,sizeof(COOKgain)); //This copy does not seem to be used. FIXME if(q->nb_channels==2 && q->joint_stereo==1){ joint_decode(q, q->decode_buf_ptr[0], q->decode_buf_ptr[2]); /* Swap buffer pointers. */ tmp_ptr = q->decode_buf_ptr[1]; q->decode_buf_ptr[1] = q->decode_buf_ptr[0]; q->decode_buf_ptr[0] = tmp_ptr; tmp_ptr = q->decode_buf_ptr[3]; q->decode_buf_ptr[3] = q->decode_buf_ptr[2]; q->decode_buf_ptr[2] = tmp_ptr; /* FIXME: Rethink the gainbuffer handling, maybe a rename? now/previous swap */ q->gain_now_ptr = &q->gain_now; q->gain_previous_ptr = &q->gain_previous; for (i=0 ; i<q->nb_channels ; i++){ cook_imlt(q, q->decode_buf_ptr[i*2], q->mono_mdct_output, q->mlt_tmp); gain_compensate(q, q->mono_mdct_output, q->gain_now_ptr, q->gain_previous_ptr, q->previous_buffer_ptr[0]); /* Swap out the previous buffer. */ tmp_ptr = q->previous_buffer_ptr[0]; q->previous_buffer_ptr[0] = q->previous_buffer_ptr[1]; q->previous_buffer_ptr[1] = tmp_ptr; /* Clip and convert the floats to 16 bits. */ for (j=0 ; j<q->samples_per_frame ; j++){ value = lrintf(q->mono_mdct_output[j]); if(value < -32768) value = -32768; else if(value > 32767) value = 32767; outbuffer[2*j+i] = value; } } memcpy(&q->gain_now, &q->gain_previous, sizeof(COOKgain)); memcpy(&q->gain_previous, &q->gain_current, sizeof(COOKgain)); } else if (q->nb_channels==2 && q->joint_stereo==0) { /* channel 0 */ mono_decode(q, q->decode_buf_ptr[0]); tmp_ptr = q->decode_buf_ptr[0]; q->decode_buf_ptr[0] = q->decode_buf_ptr[1]; q->decode_buf_ptr[1] = q->decode_buf_ptr[2]; q->decode_buf_ptr[2] = q->decode_buf_ptr[3]; q->decode_buf_ptr[3] = tmp_ptr; q->gain_now_ptr = &q->gain_now; q->gain_previous_ptr = &q->gain_previous; cook_imlt(q, q->decode_buf_ptr[0], q->mono_mdct_output,q->mlt_tmp); gain_compensate(q, q->mono_mdct_output, q->gain_now_ptr, q->gain_previous_ptr, q->previous_buffer_ptr[0]); /* Swap out the previous buffer. */ tmp_ptr = q->previous_buffer_ptr[0]; q->previous_buffer_ptr[0] = q->previous_buffer_ptr[1]; q->previous_buffer_ptr[1] = tmp_ptr; for (j=0 ; j<q->samples_per_frame ; j++){ value = lrintf(q->mono_mdct_output[j]); if(value < -32768) value = -32768; else if(value > 32767) value = 32767; outbuffer[2*j+1] = value; } /* channel 1 */ //av_log(NULL,AV_LOG_ERROR,"bits = %d\n",get_bits_count(&q->gb)); init_get_bits(&q->gb, q->decoded_bytes_buffer, sub_packet_size*8+q->bits_per_subpacket); decode_gain_info(&q->gb, &q->gain_current); //memcpy(&q->gain_copy, &q->gain_current ,sizeof(COOKgain)); mono_decode(q, q->decode_buf_ptr[0]); tmp_ptr = q->decode_buf_ptr[0]; q->decode_buf_ptr[1] = q->decode_buf_ptr[2]; q->decode_buf_ptr[2] = q->decode_buf_ptr[3]; q->decode_buf_ptr[3] = tmp_ptr; q->gain_now_ptr = &q->gain_now; q->gain_previous_ptr = &q->gain_previous; cook_imlt(q, q->decode_buf_ptr[0], q->mono_mdct_output,q->mlt_tmp); gain_compensate(q, q->mono_mdct_output, q->gain_now_ptr, q->gain_previous_ptr, q->previous_buffer_ptr[0]); /* Swap out the previous buffer. */ tmp_ptr = q->previous_buffer_ptr[0]; q->previous_buffer_ptr[0] = q->previous_buffer_ptr[1]; q->previous_buffer_ptr[1] = tmp_ptr; for (j=0 ; j<q->samples_per_frame ; j++){ value = lrintf(q->mono_mdct_output[j]); if(value < -32768) value = -32768; else if(value > 32767) value = 32767; outbuffer[2*j] = value; } /* Swap out the previous buffer. */ memcpy(&q->gain_now, &q->gain_previous, sizeof(COOKgain)); memcpy(&q->gain_previous, &q->gain_current, sizeof(COOKgain)); } else { mono_decode(q, q->decode_buf_ptr[0]); /* Swap buffer pointers. */ tmp_ptr = q->decode_buf_ptr[1]; q->decode_buf_ptr[1] = q->decode_buf_ptr[0]; q->decode_buf_ptr[0] = tmp_ptr; /* FIXME: Rethink the gainbuffer handling, maybe a rename? now/previous swap */ q->gain_now_ptr = &q->gain_now; q->gain_previous_ptr = &q->gain_previous; cook_imlt(q, q->decode_buf_ptr[0], q->mono_mdct_output,q->mlt_tmp); gain_compensate(q, q->mono_mdct_output, q->gain_now_ptr, q->gain_previous_ptr, q->mono_previous_buffer1); /* Clip and convert the floats to 16 bits */ for (j=0 ; j<q->samples_per_frame ; j++){ value = lrintf(q->mono_mdct_output[j]); if(value < -32768) value = -32768; else if(value > 32767) value = 32767; outbuffer[j] = value; } memcpy(&q->gain_now, &q->gain_previous, sizeof(COOKgain)); memcpy(&q->gain_previous, &q->gain_current, sizeof(COOKgain)); } return q->samples_per_frame * sizeof(int16_t); } | 20,014 |
0 | void ff_put_h264_qpel16_mc00_msa(uint8_t *dst, const uint8_t *src, ptrdiff_t stride) { copy_width16_msa(src, stride, dst, stride, 16); } | 20,015 |
0 | static int process_output_surface(AVCodecContext *avctx, AVPacket *pkt, NvencSurface *tmpoutsurf) { NvencContext *ctx = avctx->priv_data; NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs; NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs; uint32_t slice_mode_data; uint32_t *slice_offsets = NULL; NV_ENC_LOCK_BITSTREAM lock_params = { 0 }; NVENCSTATUS nv_status; int res = 0; enum AVPictureType pict_type; switch (avctx->codec->id) { case AV_CODEC_ID_H264: slice_mode_data = ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData; break; case AV_CODEC_ID_H265: slice_mode_data = ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData; break; default: av_log(avctx, AV_LOG_ERROR, "Unknown codec name\n"); res = AVERROR(EINVAL); goto error; } slice_offsets = av_mallocz(slice_mode_data * sizeof(*slice_offsets)); if (!slice_offsets) { res = AVERROR(ENOMEM); goto error; } lock_params.version = NV_ENC_LOCK_BITSTREAM_VER; lock_params.doNotWait = 0; lock_params.outputBitstream = tmpoutsurf->output_surface; lock_params.sliceOffsets = slice_offsets; nv_status = p_nvenc->nvEncLockBitstream(ctx->nvencoder, &lock_params); if (nv_status != NV_ENC_SUCCESS) { res = nvenc_print_error(avctx, nv_status, "Failed locking bitstream buffer"); goto error; } if (res = ff_alloc_packet2(avctx, pkt, lock_params.bitstreamSizeInBytes,0)) { p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface); goto error; } memcpy(pkt->data, lock_params.bitstreamBufferPtr, lock_params.bitstreamSizeInBytes); nv_status = p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface); if (nv_status != NV_ENC_SUCCESS) nvenc_print_error(avctx, nv_status, "Failed unlocking bitstream buffer, expect the gates of mordor to open"); if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) { ctx->registered_frames[tmpoutsurf->reg_idx].mapped -= 1; if (ctx->registered_frames[tmpoutsurf->reg_idx].mapped == 0) { p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->registered_frames[tmpoutsurf->reg_idx].in_map.mappedResource); p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[tmpoutsurf->reg_idx].regptr); ctx->registered_frames[tmpoutsurf->reg_idx].regptr = NULL; } else if (ctx->registered_frames[tmpoutsurf->reg_idx].mapped < 0) { res = AVERROR_BUG; goto error; } av_frame_unref(tmpoutsurf->in_ref); tmpoutsurf->input_surface = NULL; } switch (lock_params.pictureType) { case NV_ENC_PIC_TYPE_IDR: pkt->flags |= AV_PKT_FLAG_KEY; case NV_ENC_PIC_TYPE_I: pict_type = AV_PICTURE_TYPE_I; break; case NV_ENC_PIC_TYPE_P: pict_type = AV_PICTURE_TYPE_P; break; case NV_ENC_PIC_TYPE_B: pict_type = AV_PICTURE_TYPE_B; break; case NV_ENC_PIC_TYPE_BI: pict_type = AV_PICTURE_TYPE_BI; break; default: av_log(avctx, AV_LOG_ERROR, "Unknown picture type encountered, expect the output to be broken.\n"); av_log(avctx, AV_LOG_ERROR, "Please report this error and include as much information on how to reproduce it as possible.\n"); res = AVERROR_EXTERNAL; goto error; } #if FF_API_CODED_FRAME FF_DISABLE_DEPRECATION_WARNINGS avctx->coded_frame->pict_type = pict_type; FF_ENABLE_DEPRECATION_WARNINGS #endif ff_side_data_set_encoder_stats(pkt, (lock_params.frameAvgQP - 1) * FF_QP2LAMBDA, NULL, 0, pict_type); res = nvenc_set_timestamp(avctx, &lock_params, pkt); if (res < 0) goto error2; av_free(slice_offsets); return 0; error: timestamp_queue_dequeue(ctx->timestamp_list); error2: av_free(slice_offsets); return res; } | 20,016 |
0 | static int img_read_header(AVFormatContext *s1) { VideoDemuxData *s = s1->priv_data; int first_index, last_index; AVStream *st; enum AVPixelFormat pix_fmt = AV_PIX_FMT_NONE; s1->ctx_flags |= AVFMTCTX_NOHEADER; st = avformat_new_stream(s1, NULL); if (!st) { return AVERROR(ENOMEM); } if (s->pixel_format && (pix_fmt = av_get_pix_fmt(s->pixel_format)) == AV_PIX_FMT_NONE) { av_log(s1, AV_LOG_ERROR, "No such pixel format: %s.\n", s->pixel_format); return AVERROR(EINVAL); } av_strlcpy(s->path, s1->filename, sizeof(s->path)); s->img_number = 0; s->img_count = 0; /* find format */ if (s1->iformat->flags & AVFMT_NOFILE) s->is_pipe = 0; else { s->is_pipe = 1; st->need_parsing = AVSTREAM_PARSE_FULL; } if (s->ts_from_file) avpriv_set_pts_info(st, 60, 1, 1); else avpriv_set_pts_info(st, 60, s->framerate.den, s->framerate.num); if (s->width && s->height) { st->codec->width = s->width; st->codec->height = s->height; } if (!s->is_pipe) { if (s->pattern_type == PT_GLOB_SEQUENCE) { s->use_glob = is_glob(s->path); if (s->use_glob) { char *p = s->path, *q, *dup; int gerr; av_log(s1, AV_LOG_WARNING, "Pattern type 'glob_sequence' is deprecated: " "use pattern_type 'glob' instead\n"); #if HAVE_GLOB dup = q = av_strdup(p); while (*q) { /* Do we have room for the next char and a \ insertion? */ if ((p - s->path) >= (sizeof(s->path) - 2)) break; if (*q == '%' && strspn(q + 1, "%*?[]{}")) ++q; else if (strspn(q, "\\*?[]{}")) *p++ = '\\'; *p++ = *q++; } *p = 0; av_free(dup); gerr = glob(s->path, GLOB_NOCHECK|GLOB_BRACE|GLOB_NOMAGIC, NULL, &s->globstate); if (gerr != 0) { return AVERROR(ENOENT); } first_index = 0; last_index = s->globstate.gl_pathc - 1; #endif } } if ((s->pattern_type == PT_GLOB_SEQUENCE && !s->use_glob) || s->pattern_type == PT_SEQUENCE) { if (find_image_range(&first_index, &last_index, s->path, s->start_number, s->start_number_range) < 0) { av_log(s1, AV_LOG_ERROR, "Could find no file with with path '%s' and index in the range %d-%d\n", s->path, s->start_number, s->start_number + s->start_number_range - 1); return AVERROR(ENOENT); } } else if (s->pattern_type == PT_GLOB) { #if HAVE_GLOB int gerr; gerr = glob(s->path, GLOB_NOCHECK|GLOB_BRACE|GLOB_NOMAGIC, NULL, &s->globstate); if (gerr != 0) { return AVERROR(ENOENT); } first_index = 0; last_index = s->globstate.gl_pathc - 1; s->use_glob = 1; #else av_log(s1, AV_LOG_ERROR, "Pattern type 'glob' was selected but globbing " "is not supported by this libavformat build\n"); return AVERROR(ENOSYS); #endif } else if (s->pattern_type != PT_GLOB_SEQUENCE) { av_log(s1, AV_LOG_ERROR, "Unknown value '%d' for pattern_type option\n", s->pattern_type); return AVERROR(EINVAL); } s->img_first = first_index; s->img_last = last_index; s->img_number = first_index; /* compute duration */ st->start_time = 0; st->duration = last_index - first_index + 1; } if (s1->video_codec_id) { st->codec->codec_type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = s1->video_codec_id; } else if (s1->audio_codec_id) { st->codec->codec_type = AVMEDIA_TYPE_AUDIO; st->codec->codec_id = s1->audio_codec_id; } else { const char *str = strrchr(s->path, '.'); s->split_planes = str && !av_strcasecmp(str + 1, "y"); st->codec->codec_type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = ff_guess_image2_codec(s->path); if (st->codec->codec_id == AV_CODEC_ID_LJPEG) st->codec->codec_id = AV_CODEC_ID_MJPEG; } if (st->codec->codec_type == AVMEDIA_TYPE_VIDEO && pix_fmt != AV_PIX_FMT_NONE) st->codec->pix_fmt = pix_fmt; return 0; } | 20,018 |
0 | static void rgba32_to_rgb24(AVPicture *dst, AVPicture *src, int width, int height) { const uint8_t *s; uint8_t *d; int src_wrap, dst_wrap, j, y; unsigned int v; s = src->data[0]; src_wrap = src->linesize[0] - width * 4; d = dst->data[0]; dst_wrap = dst->linesize[0] - width * 3; for(y=0;y<height;y++) { for(j = 0;j < width; j++) { v = *(uint32_t *)s; s += 4; d[0] = v >> 16; d[1] = v >> 8; d[2] = v; d += 3; } s += src_wrap; d += dst_wrap; } } | 20,020 |
0 | int opt_codec_debug(void *optctx, const char *opt, const char *arg) { av_log_set_level(AV_LOG_DEBUG); return opt_default(NULL, opt, arg); } | 20,021 |
1 | void mips_r4k_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; char *filename; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); MemoryRegion *isa_io = g_new(MemoryRegion, 1); MemoryRegion *isa_mem = g_new(MemoryRegion, 1); int bios_size; MIPSCPU *cpu; CPUMIPSState *env; ResetData *reset_info; int i; qemu_irq *i8259; ISABus *isa_bus; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *dinfo; int be; /* init CPUs */ if (cpu_model == NULL) { #ifdef TARGET_MIPS64 cpu_model = "R4000"; #else cpu_model = "24Kf"; #endif } cpu = cpu_mips_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } env = &cpu->env; reset_info = g_malloc0(sizeof(ResetData)); reset_info->cpu = cpu; reset_info->vector = env->active_tc.PC; qemu_register_reset(main_cpu_reset, reset_info); /* allocate RAM */ if (ram_size > (256 << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", ((unsigned int)ram_size / (1 << 20))); exit(1); } memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size); memory_region_add_subregion(address_space_mem, 0, ram); memory_region_init_io(iomem, NULL, &mips_qemu_ops, NULL, "mips-qemu", 0x10000); memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem); /* Try to load a BIOS image. If this fails, we continue regardless, but initialize the hardware ourselves. When a kernel gets preloaded we also initialize the hardware, since the BIOS wasn't run. */ if (bios_name == NULL) bios_name = BIOS_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { bios_size = get_image_size(filename); } else { bios_size = -1; } #ifdef TARGET_WORDS_BIGENDIAN be = 1; #else be = 0; #endif if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { bios = g_new(MemoryRegion, 1); memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE, &error_abort); vmstate_register_ram_global(bios); memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios); load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { uint32_t mips_rom = 0x00400000; if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom, blk_by_legacy_dinfo(dinfo), sector_len, mips_rom / sector_len, 4, 0, 0, 0, 0, be)) { fprintf(stderr, "qemu: Error registering flash memory.\n"); } } else if (!qtest_enabled()) { /* not fatal */ fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", bios_name); } g_free(filename); if (kernel_filename) { loaderparams.ram_size = ram_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; reset_info->vector = load_kernel(); } /* Init CPU internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */ memory_region_init_alias(isa_io, NULL, "isa-io", get_system_io(), 0, 0x00010000); memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); memory_region_add_subregion(get_system_memory(), 0x14000000, isa_io); memory_region_add_subregion(get_system_memory(), 0x10000000, isa_mem); isa_bus = isa_bus_new(NULL, isa_mem, get_system_io()); /* The PIC is attached to the MIPS CPU INT0 pin */ i8259 = i8259_init(isa_bus, env->irq[2]); isa_bus_irqs(isa_bus, i8259); rtc_init(isa_bus, 2000, NULL); pit = pit_init(isa_bus, 0x40, 0, NULL); serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); isa_vga_init(isa_bus); if (nd_table[0].used) isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]); ide_drive_get(hd, ARRAY_SIZE(hd)); for(i = 0; i < MAX_IDE_BUS; i++) isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); isa_create_simple(isa_bus, "i8042"); } | 20,024 |
1 | static int get_packetheader(NUTContext *nut, ByteIOContext *bc, int calculate_checksum) { int64_t start, size; // start= url_ftell(bc) - 8; size= get_v(bc); init_checksum(bc, calculate_checksum ? av_crc04C11DB7_update : NULL, 1); // nut->packet_start[2] = start; // nut->written_packet_size= size; return size; } | 20,025 |
1 | static int decode_slice(AVCodecContext *avctx, void *tdata) { ProresThreadData *td = tdata; ProresContext *ctx = avctx->priv_data; int mb_x_pos = td->x_pos; int mb_y_pos = td->y_pos; int pic_num = ctx->pic_num; int slice_num = td->slice_num; int mbs_per_slice = td->slice_width; const uint8_t *buf; uint8_t *y_data, *u_data, *v_data, *a_data; AVFrame *pic = ctx->frame; int i, sf, slice_width_factor; int slice_data_size, hdr_size; int y_data_size, u_data_size, v_data_size, a_data_size; int y_linesize, u_linesize, v_linesize, a_linesize; int coff[4]; int ret; buf = ctx->slice_data[slice_num].index; slice_data_size = ctx->slice_data[slice_num + 1].index - buf; slice_width_factor = av_log2(mbs_per_slice); y_data = pic->data[0]; u_data = pic->data[1]; v_data = pic->data[2]; a_data = pic->data[3]; y_linesize = pic->linesize[0]; u_linesize = pic->linesize[1]; v_linesize = pic->linesize[2]; a_linesize = pic->linesize[3]; if (pic->interlaced_frame) { if (!(pic_num ^ pic->top_field_first)) { y_data += y_linesize; u_data += u_linesize; v_data += v_linesize; if (a_data) a_data += a_linesize; } y_linesize <<= 1; u_linesize <<= 1; v_linesize <<= 1; a_linesize <<= 1; } y_data += (mb_y_pos << 4) * y_linesize + (mb_x_pos << 5); u_data += (mb_y_pos << 4) * u_linesize + (mb_x_pos << ctx->mb_chroma_factor); v_data += (mb_y_pos << 4) * v_linesize + (mb_x_pos << ctx->mb_chroma_factor); if (a_data) a_data += (mb_y_pos << 4) * a_linesize + (mb_x_pos << 5); if (slice_data_size < 6) { av_log(avctx, AV_LOG_ERROR, "slice data too small\n"); return AVERROR_INVALIDDATA; } /* parse slice header */ hdr_size = buf[0] >> 3; coff[0] = hdr_size; y_data_size = AV_RB16(buf + 2); coff[1] = coff[0] + y_data_size; u_data_size = AV_RB16(buf + 4); coff[2] = coff[1] + u_data_size; v_data_size = hdr_size > 7 ? AV_RB16(buf + 6) : slice_data_size - coff[2]; coff[3] = coff[2] + v_data_size; a_data_size = ctx->alpha_info ? slice_data_size - coff[3] : 0; /* if V or alpha component size is negative that means that previous component sizes are too large */ if (v_data_size < 0 || a_data_size < 0 || hdr_size < 6) { av_log(avctx, AV_LOG_ERROR, "invalid data size\n"); return AVERROR_INVALIDDATA; } sf = av_clip(buf[1], 1, 224); sf = sf > 128 ? (sf - 96) << 2 : sf; /* scale quantization matrixes according with slice's scale factor */ /* TODO: this can be SIMD-optimized a lot */ if (ctx->qmat_changed || sf != td->prev_slice_sf) { td->prev_slice_sf = sf; for (i = 0; i < 64; i++) { td->qmat_luma_scaled[ctx->dsp.idct_permutation[i]] = ctx->qmat_luma[i] * sf; td->qmat_chroma_scaled[ctx->dsp.idct_permutation[i]] = ctx->qmat_chroma[i] * sf; } } /* decode luma plane */ ret = decode_slice_plane(ctx, td, buf + coff[0], y_data_size, (uint16_t*) y_data, y_linesize, mbs_per_slice, 4, slice_width_factor + 2, td->qmat_luma_scaled, 0); if (ret < 0) return ret; /* decode U chroma plane */ ret = decode_slice_plane(ctx, td, buf + coff[1], u_data_size, (uint16_t*) u_data, u_linesize, mbs_per_slice, ctx->num_chroma_blocks, slice_width_factor + ctx->chroma_factor - 1, td->qmat_chroma_scaled, 1); if (ret < 0) return ret; /* decode V chroma plane */ ret = decode_slice_plane(ctx, td, buf + coff[2], v_data_size, (uint16_t*) v_data, v_linesize, mbs_per_slice, ctx->num_chroma_blocks, slice_width_factor + ctx->chroma_factor - 1, td->qmat_chroma_scaled, 1); if (ret < 0) return ret; /* decode alpha plane if available */ if (a_data && a_data_size) decode_alpha_plane(ctx, td, buf + coff[3], a_data_size, (uint16_t*) a_data, a_linesize, mbs_per_slice); return 0; } | 20,027 |
0 | static int put_v(ByteIOContext *bc, uint64_t val) { int i; // if (bytes_left(s)*8 < 9) // return -1; if (bytes_left(bc) < 1) return -1; val &= 0x7FFFFFFFFFFFFFFFULL; // FIXME can only encode upto 63 bits currently i= get_length(val); for (i-=7; i>0; i-=7){ put_byte(bc, 0x80 | (val>>i)); } put_byte(bc, val&0x7f); return 0; } | 20,028 |
1 | static inline void gen_bcond(DisasContext *ctx, int type) { uint32_t bo = BO(ctx->opcode); int l1; TCGv target; ctx->exception = POWERPC_EXCP_BRANCH; if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { target = tcg_temp_local_new(); if (type == BCOND_CTR) tcg_gen_mov_tl(target, cpu_ctr); else if (type == BCOND_TAR) gen_load_spr(target, SPR_TAR); else tcg_gen_mov_tl(target, cpu_lr); } else { TCGV_UNUSED(target); } if (LK(ctx->opcode)) gen_setlr(ctx, ctx->nip); l1 = gen_new_label(); if ((bo & 0x4) == 0) { /* Decrement and test CTR */ TCGv temp = tcg_temp_new(); if (unlikely(type == BCOND_CTR)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); if (NARROW_MODE(ctx)) { tcg_gen_ext32u_tl(temp, cpu_ctr); } else { tcg_gen_mov_tl(temp, cpu_ctr); } if (bo & 0x2) { tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); } else { tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); } tcg_temp_free(temp); } if ((bo & 0x10) == 0) { /* Test CR */ uint32_t bi = BI(ctx->opcode); uint32_t mask = 1 << (3 - (bi & 0x03)); TCGv_i32 temp = tcg_temp_new_i32(); if (bo & 0x8) { tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); } else { tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); } tcg_temp_free_i32(temp); } gen_update_cfar(ctx, ctx->nip); if (type == BCOND_IM) { target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); if (likely(AA(ctx->opcode) == 0)) { gen_goto_tb(ctx, 0, ctx->nip + li - 4); } else { gen_goto_tb(ctx, 0, li); } gen_set_label(l1); gen_goto_tb(ctx, 1, ctx->nip); } else { if (NARROW_MODE(ctx)) { tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); } else { tcg_gen_andi_tl(cpu_nip, target, ~3); } tcg_gen_exit_tb(0); gen_set_label(l1); gen_update_nip(ctx, ctx->nip); tcg_gen_exit_tb(0); } if (type == BCOND_LR || type == BCOND_CTR) { tcg_temp_free(target); } } | 20,029 |
1 | void arm_handle_psci_call(ARMCPU *cpu) { /* * This function partially implements the logic for dispatching Power State * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b), * to the extent required for bringing up and taking down secondary cores, * and for handling reset and poweroff requests. * Additional information about the calling convention used is available in * the document 'SMC Calling Convention' (ARM DEN 0028) */ CPUARMState *env = &cpu->env; uint64_t param[4]; uint64_t context_id, mpidr; target_ulong entry; int32_t ret = 0; int i; for (i = 0; i < 4; i++) { /* * All PSCI functions take explicit 32-bit or native int sized * arguments so we can simply zero-extend all arguments regardless * of which exact function we are about to call. */ param[i] = is_a64(env) ? env->xregs[i] : env->regs[i]; } if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) { ret = QEMU_PSCI_RET_INVALID_PARAMS; goto err; } switch (param[0]) { CPUState *target_cpu_state; ARMCPU *target_cpu; case QEMU_PSCI_0_2_FN_PSCI_VERSION: ret = QEMU_PSCI_0_2_RET_VERSION_0_2; break; case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ break; case QEMU_PSCI_0_2_FN_AFFINITY_INFO: case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: mpidr = param[1]; switch (param[2]) { case 0: target_cpu_state = arm_get_cpu_by_id(mpidr); if (!target_cpu_state) { ret = QEMU_PSCI_RET_INVALID_PARAMS; break; } target_cpu = ARM_CPU(target_cpu_state); ret = target_cpu->powered_off ? 1 : 0; break; default: /* Everything above affinity level 0 is always on. */ ret = 0; } break; case QEMU_PSCI_0_2_FN_SYSTEM_RESET: qemu_system_reset_request(); /* QEMU reset and shutdown are async requests, but PSCI * mandates that we never return from the reset/shutdown * call, so power the CPU off now so it doesn't execute * anything further. */ goto cpu_off; case QEMU_PSCI_0_2_FN_SYSTEM_OFF: qemu_system_shutdown_request(); goto cpu_off; case QEMU_PSCI_0_1_FN_CPU_ON: case QEMU_PSCI_0_2_FN_CPU_ON: case QEMU_PSCI_0_2_FN64_CPU_ON: { /* The PSCI spec mandates that newly brought up CPUs start * in the highest exception level which exists and is enabled * on the calling CPU. Since the QEMU PSCI implementation is * acting as a "fake EL3" or "fake EL2" firmware, this for us * means that we want to start at the highest NS exception level * that we are providing to the guest. * The execution mode should be that which is currently in use * by the same exception level on the calling CPU. * The CPU should be started with the context_id value * in x0 (if AArch64) or r0 (if AArch32). */ int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; bool target_aarch64 = arm_el_is_aa64(env, target_el); mpidr = param[1]; entry = param[2]; context_id = param[3]; ret = arm_set_cpu_on(mpidr, entry, context_id, target_el, target_aarch64); break; } case QEMU_PSCI_0_1_FN_CPU_OFF: case QEMU_PSCI_0_2_FN_CPU_OFF: goto cpu_off; case QEMU_PSCI_0_1_FN_CPU_SUSPEND: case QEMU_PSCI_0_2_FN_CPU_SUSPEND: case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: /* Affinity levels are not supported in QEMU */ if (param[1] & 0xfffe0000) { ret = QEMU_PSCI_RET_INVALID_PARAMS; break; } /* Powerdown is not supported, we always go into WFI */ if (is_a64(env)) { env->xregs[0] = 0; } else { env->regs[0] = 0; } helper_wfi(env); break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: ret = QEMU_PSCI_RET_NOT_SUPPORTED; break; default: g_assert_not_reached(); } err: if (is_a64(env)) { env->xregs[0] = ret; } else { env->regs[0] = ret; } return; cpu_off: ret = arm_set_cpu_off(cpu->mp_affinity); /* notreached */ /* sanity check in case something failed */ assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); } | 20,030 |
1 | static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest) { int rd; uint32_t offset; TCGv tmp; rd = (insn >> 16) & 0xf; tmp = load_reg(s, rd); offset = (insn & 0xff) << ((insn >> 7) & 2); if (insn & (1 << 24)) { /* Pre indexed */ if (insn & (1 << 23)) tcg_gen_addi_i32(tmp, tmp, offset); else tcg_gen_addi_i32(tmp, tmp, -offset); tcg_gen_mov_i32(dest, tmp); if (insn & (1 << 21)) store_reg(s, rd, tmp); else dead_tmp(tmp); } else if (insn & (1 << 21)) { /* Post indexed */ tcg_gen_mov_i32(dest, tmp); if (insn & (1 << 23)) tcg_gen_addi_i32(tmp, tmp, offset); else tcg_gen_addi_i32(tmp, tmp, -offset); store_reg(s, rd, tmp); } else if (!(insn & (1 << 23))) return 1; return 0; } | 20,031 |
1 | static MOVFragmentStreamInfo * get_current_frag_stream_info( MOVFragmentIndex *frag_index) { MOVFragmentIndexItem * item = &frag_index->item[frag_index->current]; if (item->current >= 0 && item->current < item->nb_stream_info) return &item->stream_info[item->current]; // This shouldn't happen } | 20,033 |
1 | static void v9fs_wstat(void *opaque) { int32_t fid; int err = 0; int16_t unused; V9fsStat v9stat; size_t offset = 7; struct stat stbuf; V9fsFidState *fidp; V9fsPDU *pdu = opaque; V9fsState *s = pdu->s; pdu_unmarshal(pdu, offset, "dwS", &fid, &unused, &v9stat); fidp = get_fid(pdu, fid); if (fidp == NULL) { err = -EINVAL; goto out_nofid; } /* do we need to sync the file? */ if (donttouch_stat(&v9stat)) { err = v9fs_co_fsync(pdu, fidp, 0); goto out; } if (v9stat.mode != -1) { uint32_t v9_mode; err = v9fs_co_lstat(pdu, &fidp->path, &stbuf); if (err < 0) { goto out; } v9_mode = stat_to_v9mode(&stbuf); if ((v9stat.mode & P9_STAT_MODE_TYPE_BITS) != (v9_mode & P9_STAT_MODE_TYPE_BITS)) { /* Attempting to change the type */ err = -EIO; goto out; } err = v9fs_co_chmod(pdu, &fidp->path, v9mode_to_mode(v9stat.mode, &v9stat.extension)); if (err < 0) { goto out; } } if (v9stat.mtime != -1 || v9stat.atime != -1) { struct timespec times[2]; if (v9stat.atime != -1) { times[0].tv_sec = v9stat.atime; times[0].tv_nsec = 0; } else { times[0].tv_nsec = UTIME_OMIT; } if (v9stat.mtime != -1) { times[1].tv_sec = v9stat.mtime; times[1].tv_nsec = 0; } else { times[1].tv_nsec = UTIME_OMIT; } err = v9fs_co_utimensat(pdu, &fidp->path, times); if (err < 0) { goto out; } } if (v9stat.n_gid != -1 || v9stat.n_uid != -1) { err = v9fs_co_chown(pdu, &fidp->path, v9stat.n_uid, v9stat.n_gid); if (err < 0) { goto out; } } if (v9stat.name.size != 0) { err = v9fs_complete_rename(pdu, fidp, -1, &v9stat.name); if (err < 0) { goto out; } } if (v9stat.length != -1) { err = v9fs_co_truncate(pdu, &fidp->path, v9stat.length); if (err < 0) { goto out; } } err = offset; out: put_fid(pdu, fidp); out_nofid: v9fs_stat_free(&v9stat); complete_pdu(s, pdu, err); } | 20,037 |
1 | static void vnc_colordepth(VncState *vs) { if (vnc_has_feature(vs, VNC_FEATURE_WMVI)) { /* Sending a WMVi message to notify the client*/ vnc_lock_output(vs); vnc_write_u8(vs, VNC_MSG_SERVER_FRAMEBUFFER_UPDATE); vnc_write_u8(vs, 0); vnc_write_u16(vs, 1); /* number of rects */ vnc_framebuffer_update(vs, 0, 0, surface_width(vs->vd->ds), surface_height(vs->vd->ds), VNC_ENCODING_WMVi); pixel_format_message(vs); vnc_unlock_output(vs); vnc_flush(vs); } else { set_pixel_conversion(vs); } } | 20,038 |
1 | static void output_audio_block(AC3EncodeContext *s, int blk) { int ch, i, baie, bnd, got_cpl, ch0; AC3Block *block = &s->blocks[blk]; /* block switching */ if (!s->eac3) { for (ch = 0; ch < s->fbw_channels; ch++) put_bits(&s->pb, 1, 0); } /* dither flags */ if (!s->eac3) { for (ch = 0; ch < s->fbw_channels; ch++) put_bits(&s->pb, 1, 1); } /* dynamic range codes */ put_bits(&s->pb, 1, 0); /* spectral extension */ if (s->eac3) put_bits(&s->pb, 1, 0); /* channel coupling */ if (!s->eac3) put_bits(&s->pb, 1, block->new_cpl_strategy); if (block->new_cpl_strategy) { if (!s->eac3) put_bits(&s->pb, 1, block->cpl_in_use); if (block->cpl_in_use) { int start_sub, end_sub; if (s->eac3) put_bits(&s->pb, 1, 0); /* enhanced coupling */ if (!s->eac3 || s->channel_mode != AC3_CHMODE_STEREO) { for (ch = 1; ch <= s->fbw_channels; ch++) put_bits(&s->pb, 1, block->channel_in_cpl[ch]); } if (s->channel_mode == AC3_CHMODE_STEREO) put_bits(&s->pb, 1, 0); /* phase flags in use */ start_sub = (s->start_freq[CPL_CH] - 37) / 12; end_sub = (s->cpl_end_freq - 37) / 12; put_bits(&s->pb, 4, start_sub); put_bits(&s->pb, 4, end_sub - 3); /* coupling band structure */ if (s->eac3) { put_bits(&s->pb, 1, 0); /* use default */ } else { for (bnd = start_sub+1; bnd < end_sub; bnd++) put_bits(&s->pb, 1, ff_eac3_default_cpl_band_struct[bnd]); } } } /* coupling coordinates */ if (block->cpl_in_use) { for (ch = 1; ch <= s->fbw_channels; ch++) { if (block->channel_in_cpl[ch]) { if (!s->eac3 || block->new_cpl_coords[ch] != 2) put_bits(&s->pb, 1, block->new_cpl_coords[ch]); if (block->new_cpl_coords[ch]) { put_bits(&s->pb, 2, block->cpl_master_exp[ch]); for (bnd = 0; bnd < s->num_cpl_bands; bnd++) { put_bits(&s->pb, 4, block->cpl_coord_exp [ch][bnd]); put_bits(&s->pb, 4, block->cpl_coord_mant[ch][bnd]); } } } } } /* stereo rematrixing */ if (s->channel_mode == AC3_CHMODE_STEREO) { if (!s->eac3 || blk > 0) put_bits(&s->pb, 1, block->new_rematrixing_strategy); if (block->new_rematrixing_strategy) { /* rematrixing flags */ for (bnd = 0; bnd < block->num_rematrixing_bands; bnd++) put_bits(&s->pb, 1, block->rematrixing_flags[bnd]); } } /* exponent strategy */ if (!s->eac3) { for (ch = !block->cpl_in_use; ch <= s->fbw_channels; ch++) put_bits(&s->pb, 2, s->exp_strategy[ch][blk]); if (s->lfe_on) put_bits(&s->pb, 1, s->exp_strategy[s->lfe_channel][blk]); } /* bandwidth */ for (ch = 1; ch <= s->fbw_channels; ch++) { if (s->exp_strategy[ch][blk] != EXP_REUSE && !block->channel_in_cpl[ch]) put_bits(&s->pb, 6, s->bandwidth_code); } /* exponents */ for (ch = !block->cpl_in_use; ch <= s->channels; ch++) { int nb_groups; int cpl = (ch == CPL_CH); if (s->exp_strategy[ch][blk] == EXP_REUSE) continue; /* DC exponent */ put_bits(&s->pb, 4, block->grouped_exp[ch][0] >> cpl); /* exponent groups */ nb_groups = exponent_group_tab[cpl][s->exp_strategy[ch][blk]-1][block->end_freq[ch]-s->start_freq[ch]]; for (i = 1; i <= nb_groups; i++) put_bits(&s->pb, 7, block->grouped_exp[ch][i]); /* gain range info */ if (ch != s->lfe_channel && !cpl) put_bits(&s->pb, 2, 0); } /* bit allocation info */ if (!s->eac3) { baie = (blk == 0); put_bits(&s->pb, 1, baie); if (baie) { put_bits(&s->pb, 2, s->slow_decay_code); put_bits(&s->pb, 2, s->fast_decay_code); put_bits(&s->pb, 2, s->slow_gain_code); put_bits(&s->pb, 2, s->db_per_bit_code); put_bits(&s->pb, 3, s->floor_code); } } /* snr offset */ if (!s->eac3) { put_bits(&s->pb, 1, block->new_snr_offsets); if (block->new_snr_offsets) { put_bits(&s->pb, 6, s->coarse_snr_offset); for (ch = !block->cpl_in_use; ch <= s->channels; ch++) { put_bits(&s->pb, 4, s->fine_snr_offset[ch]); put_bits(&s->pb, 3, s->fast_gain_code[ch]); } } } else { put_bits(&s->pb, 1, 0); /* no converter snr offset */ } /* coupling leak */ if (block->cpl_in_use) { if (!s->eac3 || block->new_cpl_leak != 2) put_bits(&s->pb, 1, block->new_cpl_leak); if (block->new_cpl_leak) { put_bits(&s->pb, 3, s->bit_alloc.cpl_fast_leak); put_bits(&s->pb, 3, s->bit_alloc.cpl_slow_leak); } } if (!s->eac3) { put_bits(&s->pb, 1, 0); /* no delta bit allocation */ put_bits(&s->pb, 1, 0); /* no data to skip */ } /* mantissas */ got_cpl = !block->cpl_in_use; for (ch = 1; ch <= s->channels; ch++) { int b, q; if (!got_cpl && ch > 1 && block->channel_in_cpl[ch-1]) { ch0 = ch - 1; ch = CPL_CH; got_cpl = 1; } for (i = s->start_freq[ch]; i < block->end_freq[ch]; i++) { q = block->qmant[ch][i]; b = s->ref_bap[ch][blk][i]; switch (b) { case 0: break; case 1: if (q != 128) put_bits (&s->pb, 5, q); break; case 2: if (q != 128) put_bits (&s->pb, 7, q); break; case 3: put_sbits(&s->pb, 3, q); break; case 4: if (q != 128) put_bits (&s->pb, 7, q); break; case 14: put_sbits(&s->pb, 14, q); break; case 15: put_sbits(&s->pb, 16, q); break; default: put_sbits(&s->pb, b-1, q); break; } } if (ch == CPL_CH) ch = ch0; } } | 20,039 |
1 | void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, VirtIOBlockDataPlane **dataplane, Error **errp) { VirtIOBlockDataPlane *s; Error *local_err = NULL; BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev))); VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); *dataplane = NULL; if (!conf->data_plane && !conf->iothread) { return; } /* Don't try if transport does not support notifiers. */ if (!k->set_guest_notifiers || !k->set_host_notifier) { error_setg(errp, "device is incompatible with x-data-plane " "(transport does not support notifiers)"); return; } /* If dataplane is (re-)enabled while the guest is running there could be * block jobs that can conflict. */ if (blk_op_is_blocked(conf->conf.blk, BLOCK_OP_TYPE_DATAPLANE, &local_err)) { error_setg(errp, "cannot start dataplane thread: %s", error_get_pretty(local_err)); error_free(local_err); return; } s = g_new0(VirtIOBlockDataPlane, 1); s->vdev = vdev; s->conf = conf; if (conf->iothread) { s->iothread = conf->iothread; object_ref(OBJECT(s->iothread)); } else { /* Create per-device IOThread if none specified. This is for * x-data-plane option compatibility. If x-data-plane is removed we * can drop this. */ object_initialize(&s->internal_iothread_obj, sizeof(s->internal_iothread_obj), TYPE_IOTHREAD); user_creatable_complete(OBJECT(&s->internal_iothread_obj), &error_abort); s->iothread = &s->internal_iothread_obj; } s->ctx = iothread_get_aio_context(s->iothread); s->bh = aio_bh_new(s->ctx, notify_guest_bh, s); error_setg(&s->blocker, "block device is in use by data plane"); blk_op_block_all(conf->conf.blk, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_RESIZE, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_DRIVE_DEL, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_BACKUP_SOURCE, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_COMMIT, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_MIRROR, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_STREAM, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_REPLACE, s->blocker); *dataplane = s; } | 20,041 |
0 | static inline int parse_nal_units(AVCodecParserContext *s, AVCodecContext *avctx, const uint8_t *buf, int buf_size) { HEVCContext *h = &((HEVCParseContext *)s->priv_data)->h; GetBitContext *gb = &h->HEVClc->gb; SliceHeader *sh = &h->sh; const uint8_t *buf_end = buf + buf_size; int state = -1, i; HEVCNAL *nal; /* set some sane default values */ s->pict_type = AV_PICTURE_TYPE_I; s->key_frame = 0; s->picture_structure = AV_PICTURE_STRUCTURE_UNKNOWN; h->avctx = avctx; if (!buf_size) return 0; if (h->nals_allocated < 1) { HEVCNAL *tmp = av_realloc_array(h->nals, 1, sizeof(*tmp)); if (!tmp) return AVERROR(ENOMEM); h->nals = tmp; memset(h->nals, 0, sizeof(*tmp)); h->nals_allocated = 1; } nal = &h->nals[0]; for (;;) { int src_length, consumed; buf = avpriv_find_start_code(buf, buf_end, &state); if (--buf + 2 >= buf_end) break; src_length = buf_end - buf; h->nal_unit_type = (*buf >> 1) & 0x3f; h->temporal_id = (*(buf + 1) & 0x07) - 1; if (h->nal_unit_type <= NAL_CRA_NUT) { // Do not walk the whole buffer just to decode slice segment header if (src_length > 20) src_length = 20; } consumed = ff_hevc_extract_rbsp(h, buf, src_length, nal); if (consumed < 0) return consumed; init_get_bits8(gb, nal->data + 2, nal->size); switch (h->nal_unit_type) { case NAL_VPS: ff_hevc_decode_nal_vps(h); break; case NAL_SPS: ff_hevc_decode_nal_sps(h); break; case NAL_PPS: ff_hevc_decode_nal_pps(h); break; case NAL_SEI_PREFIX: case NAL_SEI_SUFFIX: ff_hevc_decode_nal_sei(h); break; case NAL_TRAIL_N: case NAL_TRAIL_R: case NAL_TSA_N: case NAL_TSA_R: case NAL_STSA_N: case NAL_STSA_R: case NAL_RADL_N: case NAL_RADL_R: case NAL_RASL_N: case NAL_RASL_R: case NAL_BLA_W_LP: case NAL_BLA_W_RADL: case NAL_BLA_N_LP: case NAL_IDR_W_RADL: case NAL_IDR_N_LP: case NAL_CRA_NUT: sh->first_slice_in_pic_flag = get_bits1(gb); s->picture_structure = h->picture_struct; s->field_order = h->picture_struct; if (IS_IRAP(h)) { s->key_frame = 1; sh->no_output_of_prior_pics_flag = get_bits1(gb); } sh->pps_id = get_ue_golomb(gb); if (sh->pps_id >= MAX_PPS_COUNT || !h->pps_list[sh->pps_id]) { av_log(h->avctx, AV_LOG_ERROR, "PPS id out of range: %d\n", sh->pps_id); return AVERROR_INVALIDDATA; } h->pps = (HEVCPPS*)h->pps_list[sh->pps_id]->data; if (h->pps->sps_id >= MAX_SPS_COUNT || !h->sps_list[h->pps->sps_id]) { av_log(h->avctx, AV_LOG_ERROR, "SPS id out of range: %d\n", h->pps->sps_id); return AVERROR_INVALIDDATA; } if (h->sps != (HEVCSPS*)h->sps_list[h->pps->sps_id]->data) { h->sps = (HEVCSPS*)h->sps_list[h->pps->sps_id]->data; h->vps = (HEVCVPS*)h->vps_list[h->sps->vps_id]->data; } if (!sh->first_slice_in_pic_flag) { int slice_address_length; if (h->pps->dependent_slice_segments_enabled_flag) sh->dependent_slice_segment_flag = get_bits1(gb); else sh->dependent_slice_segment_flag = 0; slice_address_length = av_ceil_log2_c(h->sps->ctb_width * h->sps->ctb_height); sh->slice_segment_addr = get_bits(gb, slice_address_length); if (sh->slice_segment_addr >= h->sps->ctb_width * h->sps->ctb_height) { av_log(h->avctx, AV_LOG_ERROR, "Invalid slice segment address: %u.\n", sh->slice_segment_addr); return AVERROR_INVALIDDATA; } } else sh->dependent_slice_segment_flag = 0; if (sh->dependent_slice_segment_flag) break; for (i = 0; i < h->pps->num_extra_slice_header_bits; i++) skip_bits(gb, 1); // slice_reserved_undetermined_flag[] sh->slice_type = get_ue_golomb(gb); if (!(sh->slice_type == I_SLICE || sh->slice_type == P_SLICE || sh->slice_type == B_SLICE)) { av_log(h->avctx, AV_LOG_ERROR, "Unknown slice type: %d.\n", sh->slice_type); return AVERROR_INVALIDDATA; } s->pict_type = sh->slice_type == B_SLICE ? AV_PICTURE_TYPE_B : sh->slice_type == P_SLICE ? AV_PICTURE_TYPE_P : AV_PICTURE_TYPE_I; if (h->pps->output_flag_present_flag) sh->pic_output_flag = get_bits1(gb); if (h->sps->separate_colour_plane_flag) sh->colour_plane_id = get_bits(gb, 2); if (!IS_IDR(h)) { sh->pic_order_cnt_lsb = get_bits(gb, h->sps->log2_max_poc_lsb); s->output_picture_number = h->poc = ff_hevc_compute_poc(h, sh->pic_order_cnt_lsb); } else s->output_picture_number = h->poc = 0; if (h->temporal_id == 0 && h->nal_unit_type != NAL_TRAIL_N && h->nal_unit_type != NAL_TSA_N && h->nal_unit_type != NAL_STSA_N && h->nal_unit_type != NAL_RADL_N && h->nal_unit_type != NAL_RASL_N && h->nal_unit_type != NAL_RADL_R && h->nal_unit_type != NAL_RASL_R) h->pocTid0 = h->poc; return 0; /* no need to evaluate the rest */ } buf += consumed; } /* didn't find a picture! */ av_log(h->avctx, AV_LOG_ERROR, "missing picture in access unit\n"); return -1; } | 20,042 |
1 | static void filter_mb_fast( H264Context *h, int mb_x, int mb_y, uint8_t *img_y, uint8_t *img_cb, uint8_t *img_cr, unsigned int linesize, unsigned int uvlinesize) { MpegEncContext * const s = &h->s; int mb_xy, mb_type; int qp, qp0, qp1, qpc, qpc0, qpc1, qp_thresh; mb_xy = mb_x + mb_y*s->mb_stride; if(mb_x==0 || mb_y==0 || !s->dsp.h264_loop_filter_strength || (h->deblocking_filter == 2 && (h->slice_table[mb_xy] != h->slice_table[h->top_mb_xy] || h->slice_table[mb_xy] != h->slice_table[mb_xy - 1]))) { filter_mb(h, mb_x, mb_y, img_y, img_cb, img_cr, linesize, uvlinesize); return; } assert(!FRAME_MBAFF); mb_type = s->current_picture.mb_type[mb_xy]; qp = s->current_picture.qscale_table[mb_xy]; qp0 = s->current_picture.qscale_table[mb_xy-1]; qp1 = s->current_picture.qscale_table[h->top_mb_xy]; qpc = get_chroma_qp( h, qp ); qpc0 = get_chroma_qp( h, qp0 ); qpc1 = get_chroma_qp( h, qp1 ); qp0 = (qp + qp0 + 1) >> 1; qp1 = (qp + qp1 + 1) >> 1; qpc0 = (qpc + qpc0 + 1) >> 1; qpc1 = (qpc + qpc1 + 1) >> 1; qp_thresh = 15 - h->slice_alpha_c0_offset; if(qp <= qp_thresh && qp0 <= qp_thresh && qp1 <= qp_thresh && qpc <= qp_thresh && qpc0 <= qp_thresh && qpc1 <= qp_thresh) return; if( IS_INTRA(mb_type) ) { int16_t bS4[4] = {4,4,4,4}; int16_t bS3[4] = {3,3,3,3}; if( IS_8x8DCT(mb_type) ) { filter_mb_edgev( h, &img_y[4*0], linesize, bS4, qp0 ); filter_mb_edgev( h, &img_y[4*2], linesize, bS3, qp ); filter_mb_edgeh( h, &img_y[4*0*linesize], linesize, bS4, qp1 ); filter_mb_edgeh( h, &img_y[4*2*linesize], linesize, bS3, qp ); } else { filter_mb_edgev( h, &img_y[4*0], linesize, bS4, qp0 ); filter_mb_edgev( h, &img_y[4*1], linesize, bS3, qp ); filter_mb_edgev( h, &img_y[4*2], linesize, bS3, qp ); filter_mb_edgev( h, &img_y[4*3], linesize, bS3, qp ); filter_mb_edgeh( h, &img_y[4*0*linesize], linesize, bS4, qp1 ); filter_mb_edgeh( h, &img_y[4*1*linesize], linesize, bS3, qp ); filter_mb_edgeh( h, &img_y[4*2*linesize], linesize, bS3, qp ); filter_mb_edgeh( h, &img_y[4*3*linesize], linesize, bS3, qp ); } filter_mb_edgecv( h, &img_cb[2*0], uvlinesize, bS4, qpc0 ); filter_mb_edgecv( h, &img_cb[2*2], uvlinesize, bS3, qpc ); filter_mb_edgecv( h, &img_cr[2*0], uvlinesize, bS4, qpc0 ); filter_mb_edgecv( h, &img_cr[2*2], uvlinesize, bS3, qpc ); filter_mb_edgech( h, &img_cb[2*0*uvlinesize], uvlinesize, bS4, qpc1 ); filter_mb_edgech( h, &img_cb[2*2*uvlinesize], uvlinesize, bS3, qpc ); filter_mb_edgech( h, &img_cr[2*0*uvlinesize], uvlinesize, bS4, qpc1 ); filter_mb_edgech( h, &img_cr[2*2*uvlinesize], uvlinesize, bS3, qpc ); return; } else { DECLARE_ALIGNED_8(int16_t, bS[2][4][4]); uint64_t (*bSv)[4] = (uint64_t(*)[4])bS; int edges; if( IS_8x8DCT(mb_type) && (h->cbp&7) == 7 ) { edges = 4; bSv[0][0] = bSv[0][2] = bSv[1][0] = bSv[1][2] = 0x0002000200020002ULL; } else { int mask_edge1 = (mb_type & (MB_TYPE_16x16 | MB_TYPE_8x16)) ? 3 : (mb_type & MB_TYPE_16x8) ? 1 : 0; int mask_edge0 = (mb_type & (MB_TYPE_16x16 | MB_TYPE_8x16)) && (s->current_picture.mb_type[mb_xy-1] & (MB_TYPE_16x16 | MB_TYPE_8x16)) ? 3 : 0; int step = IS_8x8DCT(mb_type) ? 2 : 1; edges = (mb_type & MB_TYPE_16x16) && !(h->cbp & 15) ? 1 : 4; s->dsp.h264_loop_filter_strength( bS, h->non_zero_count_cache, h->ref_cache, h->mv_cache, (h->slice_type == B_TYPE), edges, step, mask_edge0, mask_edge1 ); } if( IS_INTRA(s->current_picture.mb_type[mb_xy-1]) ) bSv[0][0] = 0x0004000400040004ULL; if( IS_INTRA(s->current_picture.mb_type[h->top_mb_xy]) ) bSv[1][0] = 0x0004000400040004ULL; #define FILTER(hv,dir,edge)\ if(bSv[dir][edge]) {\ filter_mb_edge##hv( h, &img_y[4*edge*(dir?linesize:1)], linesize, bS[dir][edge], edge ? qp : qp##dir );\ if(!(edge&1)) {\ filter_mb_edgec##hv( h, &img_cb[2*edge*(dir?uvlinesize:1)], uvlinesize, bS[dir][edge], edge ? qpc : qpc##dir );\ filter_mb_edgec##hv( h, &img_cr[2*edge*(dir?uvlinesize:1)], uvlinesize, bS[dir][edge], edge ? qpc : qpc##dir );\ }\ } if( edges == 1 ) { FILTER(v,0,0); FILTER(h,1,0); } else if( IS_8x8DCT(mb_type) ) { FILTER(v,0,0); FILTER(v,0,2); FILTER(h,1,0); FILTER(h,1,2); } else { FILTER(v,0,0); FILTER(v,0,1); FILTER(v,0,2); FILTER(v,0,3); FILTER(h,1,0); FILTER(h,1,1); FILTER(h,1,2); FILTER(h,1,3); } #undef FILTER } } | 20,043 |
1 | static int decode_frame_header(NUTContext *nut, int64_t *pts, int *stream_id, uint8_t *header_idx, int frame_code) { AVFormatContext *s = nut->avf; AVIOContext *bc = s->pb; StreamContext *stc; int size, flags, size_mul, pts_delta, i, reserved_count; uint64_t tmp; if (avio_tell(bc) > nut->last_syncpoint_pos + nut->max_distance) { av_log(s, AV_LOG_ERROR, "Last frame must have been damaged %"PRId64" > %"PRId64" + %d\n", avio_tell(bc), nut->last_syncpoint_pos, nut->max_distance); return AVERROR_INVALIDDATA; } flags = nut->frame_code[frame_code].flags; size_mul = nut->frame_code[frame_code].size_mul; size = nut->frame_code[frame_code].size_lsb; *stream_id = nut->frame_code[frame_code].stream_id; pts_delta = nut->frame_code[frame_code].pts_delta; reserved_count = nut->frame_code[frame_code].reserved_count; *header_idx = nut->frame_code[frame_code].header_idx; if (flags & FLAG_INVALID) return AVERROR_INVALIDDATA; if (flags & FLAG_CODED) flags ^= ffio_read_varlen(bc); if (flags & FLAG_STREAM_ID) { GET_V(*stream_id, tmp < s->nb_streams); } stc = &nut->stream[*stream_id]; if (flags & FLAG_CODED_PTS) { int coded_pts = ffio_read_varlen(bc); // FIXME check last_pts validity? if (coded_pts < (1 << stc->msb_pts_shift)) { *pts = ff_lsb2full(stc, coded_pts); } else *pts = coded_pts - (1 << stc->msb_pts_shift); } else *pts = stc->last_pts + pts_delta; if (flags & FLAG_SIZE_MSB) size += size_mul * ffio_read_varlen(bc); if (flags & FLAG_MATCH_TIME) get_s(bc); if (flags & FLAG_HEADER_IDX) *header_idx = ffio_read_varlen(bc); if (flags & FLAG_RESERVED) reserved_count = ffio_read_varlen(bc); for (i = 0; i < reserved_count; i++) ffio_read_varlen(bc); if (*header_idx >= (unsigned)nut->header_count) { av_log(s, AV_LOG_ERROR, "header_idx invalid\n"); return AVERROR_INVALIDDATA; } if (size > 4096) *header_idx = 0; size -= nut->header_len[*header_idx]; if (flags & FLAG_CHECKSUM) { avio_rb32(bc); // FIXME check this } else if (size > 2 * nut->max_distance || FFABS(stc->last_pts - *pts) > stc->max_pts_distance) { av_log(s, AV_LOG_ERROR, "frame size > 2max_distance and no checksum\n"); return AVERROR_INVALIDDATA; } stc->last_pts = *pts; stc->last_flags = flags; return size; } | 20,044 |
1 | static int vmstate_n_elems(void *opaque, VMStateField *field) { int n_elems = 1; if (field->flags & VMS_ARRAY) { n_elems = field->num; } else if (field->flags & VMS_VARRAY_INT32) { n_elems = *(int32_t *)(opaque+field->num_offset); } else if (field->flags & VMS_VARRAY_UINT32) { n_elems = *(uint32_t *)(opaque+field->num_offset); } else if (field->flags & VMS_VARRAY_UINT16) { n_elems = *(uint16_t *)(opaque+field->num_offset); } else if (field->flags & VMS_VARRAY_UINT8) { n_elems = *(uint8_t *)(opaque+field->num_offset); } return n_elems; } | 20,045 |
1 | static void mm_decode_intra(MmContext * s, int half_horiz, int half_vert, const uint8_t *buf, int buf_size) { int i, x, y; i=0; x=0; y=0; while(i<buf_size) { int run_length, color; if (buf[i] & 0x80) { run_length = 1; color = buf[i]; i++; }else{ run_length = (buf[i] & 0x7f) + 2; color = buf[i+1]; i+=2; } if (half_horiz) run_length *=2; if (color) { memset(s->frame.data[0] + y*s->frame.linesize[0] + x, color, run_length); if (half_vert) memset(s->frame.data[0] + (y+1)*s->frame.linesize[0] + x, color, run_length); } x+= run_length; if (x >= s->avctx->width) { x=0; y += 1 + half_vert; } } } | 20,046 |
1 | static void dnxhd_decode_dct_block_10_444(const DNXHDContext *ctx, RowContext *row, int n) { dnxhd_decode_dct_block(ctx, row, n, 6, 32, 6); } | 20,047 |
1 | int qemu_accept(int s, struct sockaddr *addr, socklen_t *addrlen) { int ret; #ifdef CONFIG_ACCEPT4 ret = accept4(s, addr, addrlen, SOCK_CLOEXEC); #else ret = accept(s, addr, addrlen); if (ret >= 0) { qemu_set_cloexec(ret); } #endif return ret; } | 20,048 |
0 | static int aac_decode_frame(AVCodecContext * avccontext, void * data, int * data_size, const uint8_t * buf, int buf_size) { AACContext * ac = avccontext->priv_data; GetBitContext gb; enum RawDataBlockType elem_type; int err, elem_id, data_size_tmp; init_get_bits(&gb, buf, buf_size*8); if (show_bits(&gb, 12) == 0xfff) { if ((err = parse_adts_frame_header(ac, &gb)) < 0) { av_log(avccontext, AV_LOG_ERROR, "Error decoding AAC frame header.\n"); return -1; } if (ac->m4ac.sampling_index > 11) { av_log(ac->avccontext, AV_LOG_ERROR, "invalid sampling rate index %d\n", ac->m4ac.sampling_index); return -1; } } // parse while ((elem_type = get_bits(&gb, 3)) != TYPE_END) { elem_id = get_bits(&gb, 4); err = -1; if(elem_type == TYPE_SCE && elem_id == 1 && !ac->che[TYPE_SCE][elem_id] && ac->che[TYPE_LFE][0]) { /* Some streams incorrectly code 5.1 audio as SCE[0] CPE[0] CPE[1] SCE[1] instead of SCE[0] CPE[0] CPE[0] LFE[0]. If we seem to have encountered such a stream, transfer the LFE[0] element to SCE[1] */ ac->che[TYPE_SCE][elem_id] = ac->che[TYPE_LFE][0]; ac->che[TYPE_LFE][0] = NULL; } if(elem_type < TYPE_DSE) { if(!ac->che[elem_type][elem_id]) return -1; if(elem_type != TYPE_CCE) ac->che[elem_type][elem_id]->coup.coupling_point = 4; } switch (elem_type) { case TYPE_SCE: err = decode_ics(ac, &ac->che[TYPE_SCE][elem_id]->ch[0], &gb, 0, 0); break; case TYPE_CPE: err = decode_cpe(ac, &gb, elem_id); break; case TYPE_CCE: err = decode_cce(ac, &gb, ac->che[TYPE_CCE][elem_id]); break; case TYPE_LFE: err = decode_ics(ac, &ac->che[TYPE_LFE][elem_id]->ch[0], &gb, 0, 0); break; case TYPE_DSE: skip_data_stream_element(&gb); err = 0; break; case TYPE_PCE: { enum ChannelPosition new_che_pos[4][MAX_ELEM_ID]; memset(new_che_pos, 0, 4 * MAX_ELEM_ID * sizeof(new_che_pos[0][0])); if((err = decode_pce(ac, new_che_pos, &gb))) break; err = output_configure(ac, ac->che_pos, new_che_pos); break; } case TYPE_FIL: if (elem_id == 15) elem_id += get_bits(&gb, 8) - 1; while (elem_id > 0) elem_id -= decode_extension_payload(ac, &gb, elem_id); err = 0; /* FIXME */ break; default: err = -1; /* should not happen, but keeps compiler happy */ break; } if(err) return err; } spectral_to_sample(ac); if (!ac->is_saved) { ac->is_saved = 1; *data_size = 0; return buf_size; } data_size_tmp = 1024 * avccontext->channels * sizeof(int16_t); if(*data_size < data_size_tmp) { av_log(avccontext, AV_LOG_ERROR, "Output buffer too small (%d) or trying to output too many samples (%d) for this frame.\n", *data_size, data_size_tmp); return -1; } *data_size = data_size_tmp; ac->dsp.float_to_int16_interleave(data, (const float **)ac->output_data, 1024, avccontext->channels); return buf_size; } | 20,049 |
0 | void ff_h264dsp_init(H264DSPContext *c, const int bit_depth, const int chroma_format_idc) { #undef FUNC #define FUNC(a, depth) a ## _ ## depth ## _c #define ADDPX_DSP(depth) \ c->h264_add_pixels4 = FUNC(ff_h264_add_pixels4, depth);\ c->h264_add_pixels8 = FUNC(ff_h264_add_pixels8, depth) if (bit_depth > 8 && bit_depth <= 16) { ADDPX_DSP(16); } else { ADDPX_DSP(8); } #define H264_DSP(depth) \ c->h264_idct_add= FUNC(ff_h264_idct_add, depth);\ c->h264_idct8_add= FUNC(ff_h264_idct8_add, depth);\ c->h264_idct_dc_add= FUNC(ff_h264_idct_dc_add, depth);\ c->h264_idct8_dc_add= FUNC(ff_h264_idct8_dc_add, depth);\ c->h264_idct_add16 = FUNC(ff_h264_idct_add16, depth);\ c->h264_idct8_add4 = FUNC(ff_h264_idct8_add4, depth);\ if (chroma_format_idc == 1)\ c->h264_idct_add8 = FUNC(ff_h264_idct_add8, depth);\ else\ c->h264_idct_add8 = FUNC(ff_h264_idct_add8_422, depth);\ c->h264_idct_add16intra= FUNC(ff_h264_idct_add16intra, depth);\ c->h264_luma_dc_dequant_idct= FUNC(ff_h264_luma_dc_dequant_idct, depth);\ if (chroma_format_idc == 1)\ c->h264_chroma_dc_dequant_idct= FUNC(ff_h264_chroma_dc_dequant_idct, depth);\ else\ c->h264_chroma_dc_dequant_idct= FUNC(ff_h264_chroma422_dc_dequant_idct, depth);\ \ c->weight_h264_pixels_tab[0]= FUNC(weight_h264_pixels16, depth);\ c->weight_h264_pixels_tab[1]= FUNC(weight_h264_pixels8, depth);\ c->weight_h264_pixels_tab[2]= FUNC(weight_h264_pixels4, depth);\ c->weight_h264_pixels_tab[3]= FUNC(weight_h264_pixels2, depth);\ c->biweight_h264_pixels_tab[0]= FUNC(biweight_h264_pixels16, depth);\ c->biweight_h264_pixels_tab[1]= FUNC(biweight_h264_pixels8, depth);\ c->biweight_h264_pixels_tab[2]= FUNC(biweight_h264_pixels4, depth);\ c->biweight_h264_pixels_tab[3]= FUNC(biweight_h264_pixels2, depth);\ \ c->h264_v_loop_filter_luma= FUNC(h264_v_loop_filter_luma, depth);\ c->h264_h_loop_filter_luma= FUNC(h264_h_loop_filter_luma, depth);\ c->h264_h_loop_filter_luma_mbaff= FUNC(h264_h_loop_filter_luma_mbaff, depth);\ c->h264_v_loop_filter_luma_intra= FUNC(h264_v_loop_filter_luma_intra, depth);\ c->h264_h_loop_filter_luma_intra= FUNC(h264_h_loop_filter_luma_intra, depth);\ c->h264_h_loop_filter_luma_mbaff_intra= FUNC(h264_h_loop_filter_luma_mbaff_intra, depth);\ c->h264_v_loop_filter_chroma= FUNC(h264_v_loop_filter_chroma, depth);\ if (chroma_format_idc == 1)\ c->h264_h_loop_filter_chroma= FUNC(h264_h_loop_filter_chroma, depth);\ else\ c->h264_h_loop_filter_chroma= FUNC(h264_h_loop_filter_chroma422, depth);\ if (chroma_format_idc == 1)\ c->h264_h_loop_filter_chroma_mbaff= FUNC(h264_h_loop_filter_chroma_mbaff, depth);\ else\ c->h264_h_loop_filter_chroma_mbaff= FUNC(h264_h_loop_filter_chroma422_mbaff, depth);\ c->h264_v_loop_filter_chroma_intra= FUNC(h264_v_loop_filter_chroma_intra, depth);\ if (chroma_format_idc == 1)\ c->h264_h_loop_filter_chroma_intra= FUNC(h264_h_loop_filter_chroma_intra, depth);\ else\ c->h264_h_loop_filter_chroma_intra= FUNC(h264_h_loop_filter_chroma422_intra, depth);\ if (chroma_format_idc == 1)\ c->h264_h_loop_filter_chroma_mbaff_intra= FUNC(h264_h_loop_filter_chroma_mbaff_intra, depth);\ else\ c->h264_h_loop_filter_chroma_mbaff_intra= FUNC(h264_h_loop_filter_chroma422_mbaff_intra, depth);\ c->h264_loop_filter_strength= NULL; switch (bit_depth) { case 9: H264_DSP(9); break; case 10: H264_DSP(10); break; case 12: H264_DSP(12); break; case 14: H264_DSP(14); break; default: av_assert0(bit_depth<=8); H264_DSP(8); break; } if (ARCH_ARM) ff_h264dsp_init_arm(c, bit_depth, chroma_format_idc); if (HAVE_ALTIVEC) ff_h264dsp_init_ppc(c, bit_depth, chroma_format_idc); if (ARCH_X86) ff_h264dsp_init_x86(c, bit_depth, chroma_format_idc); } | 20,050 |
0 | int redir_open(AVFormatContext **ic_ptr, ByteIOContext *f) { char buf[4096], *q; int c; AVFormatContext *ic = NULL; /* parse each URL and try to open it */ c = url_fgetc(f); while (c != URL_EOF) { /* skip spaces */ for(;;) { if (!redir_isspace(c)) break; c = url_fgetc(f); } if (c == URL_EOF) break; /* record url */ q = buf; for(;;) { if (c == URL_EOF || redir_isspace(c)) break; if ((q - buf) < sizeof(buf) - 1) *q++ = c; c = url_fgetc(f); } *q = '\0'; //printf("URL='%s'\n", buf); /* try to open the media file */ if (av_open_input_file(&ic, buf, NULL, 0, NULL) == 0) break; } *ic_ptr = ic; if (!ic) return AVERROR(EIO); else return 0; } | 20,051 |
0 | static int common_init(AVCodecContext *avctx){ SnowContext *s = avctx->priv_data; int width, height; int level, orientation, plane_index, dec; s->avctx= avctx; dsputil_init(&s->dsp, avctx); #define mcf(dx,dy)\ s->dsp.put_qpel_pixels_tab [0][dy+dx/4]=\ s->dsp.put_no_rnd_qpel_pixels_tab[0][dy+dx/4]=\ mc_block ## dx ## dy; mcf( 0, 0) mcf( 4, 0) mcf( 8, 0) mcf(12, 0) mcf( 0, 4) mcf( 4, 4) mcf( 8, 4) mcf(12, 4) mcf( 0, 8) mcf( 4, 8) mcf( 8, 8) mcf(12, 8) mcf( 0,12) mcf( 4,12) mcf( 8,12) mcf(12,12) #define mcfh(dx,dy)\ s->dsp.put_pixels_tab [0][dy/4+dx/8]=\ s->dsp.put_no_rnd_pixels_tab[0][dy/4+dx/8]=\ mc_block_hpel ## dx ## dy; mcfh(0, 0) mcfh(8, 0) mcfh(0, 8) mcfh(8, 8) dec= s->spatial_decomposition_count= 5; s->spatial_decomposition_type= avctx->prediction_method; //FIXME add decorrelator type r transform_type s->chroma_h_shift= 1; //FIXME XXX s->chroma_v_shift= 1; // dec += FFMAX(s->chroma_h_shift, s->chroma_v_shift); s->b_width = (s->avctx->width +(1<<dec)-1)>>dec; s->b_height= (s->avctx->height+(1<<dec)-1)>>dec; s->spatial_dwt_buffer= av_mallocz(s->b_width*s->b_height*sizeof(DWTELEM)<<(2*dec)); s->pred_buffer= av_mallocz(s->b_width*s->b_height*sizeof(DWTELEM)<<(2*dec)); s->mv_scale= (s->avctx->flags & CODEC_FLAG_QPEL) ? 2 : 4; for(plane_index=0; plane_index<3; plane_index++){ int w= s->avctx->width; int h= s->avctx->height; if(plane_index){ w>>= s->chroma_h_shift; h>>= s->chroma_v_shift; } s->plane[plane_index].width = w; s->plane[plane_index].height= h; //av_log(NULL, AV_LOG_DEBUG, "%d %d\n", w, h); for(level=s->spatial_decomposition_count-1; level>=0; level--){ for(orientation=level ? 1 : 0; orientation<4; orientation++){ SubBand *b= &s->plane[plane_index].band[level][orientation]; b->buf= s->spatial_dwt_buffer; b->level= level; b->stride= s->plane[plane_index].width << (s->spatial_decomposition_count - level); b->width = (w + !(orientation&1))>>1; b->height= (h + !(orientation>1))>>1; if(orientation&1) b->buf += (w+1)>>1; if(orientation>1) b->buf += b->stride>>1; if(level) b->parent= &s->plane[plane_index].band[level-1][orientation]; } w= (w+1)>>1; h= (h+1)>>1; } } //FIXME init_subband() ? s->mb_band.stride= s->mv_band[0].stride= s->mv_band[1].stride= s->mb_band.width = s->mv_band[0].width = s->mv_band[1].width = (s->avctx->width + 15)>>4; s->mb_band.height= s->mv_band[0].height= s->mv_band[1].height= (s->avctx->height+ 15)>>4; s->mb_band .buf= av_mallocz(s->mb_band .stride * s->mb_band .height*sizeof(DWTELEM)); s->mv_band[0].buf= av_mallocz(s->mv_band[0].stride * s->mv_band[0].height*sizeof(DWTELEM)); s->mv_band[1].buf= av_mallocz(s->mv_band[1].stride * s->mv_band[1].height*sizeof(DWTELEM)); reset_contexts(s); /* width= s->width= avctx->width; height= s->height= avctx->height; assert(width && height); */ s->avctx->get_buffer(s->avctx, &s->mconly_picture); return 0; } | 20,052 |
0 | USBDevice *usbdevice_create(const char *cmdline) { USBBus *bus = usb_bus_find(-1 /* any */); DeviceInfo *info; USBDeviceInfo *usb; char driver[32]; const char *params; int len; params = strchr(cmdline,':'); if (params) { params++; len = params - cmdline; if (len > sizeof(driver)) len = sizeof(driver); pstrcpy(driver, len, cmdline); } else { params = ""; pstrcpy(driver, sizeof(driver), cmdline); } for (info = device_info_list; info != NULL; info = info->next) { if (info->bus_info != &usb_bus_info) continue; usb = DO_UPCAST(USBDeviceInfo, qdev, info); if (usb->usbdevice_name == NULL) continue; if (strcmp(usb->usbdevice_name, driver) != 0) continue; break; } if (info == NULL) { #if 0 /* no error because some drivers are not converted (yet) */ error_report("usbdevice %s not found", driver); #endif return NULL; } if (!usb->usbdevice_init) { if (params) { error_report("usbdevice %s accepts no params", driver); return NULL; } return usb_create_simple(bus, usb->qdev.name); } return usb->usbdevice_init(params); } | 20,053 |
0 | static int net_init_nic(QemuOpts *opts, Monitor *mon, const char *name, VLANState *vlan) { int idx; NICInfo *nd; const char *netdev; idx = nic_get_free_idx(); if (idx == -1 || nb_nics >= MAX_NICS) { qemu_error("Too Many NICs\n"); return -1; } nd = &nd_table[idx]; memset(nd, 0, sizeof(*nd)); if ((netdev = qemu_opt_get(opts, "netdev"))) { nd->netdev = qemu_find_netdev(netdev); if (!nd->netdev) { qemu_error("netdev '%s' not found\n", netdev); return -1; } } else { assert(vlan); nd->vlan = vlan; } if (name) { nd->name = qemu_strdup(name); } if (qemu_opt_get(opts, "model")) { nd->model = qemu_strdup(qemu_opt_get(opts, "model")); } if (qemu_opt_get(opts, "addr")) { nd->devaddr = qemu_strdup(qemu_opt_get(opts, "addr")); } nd->macaddr[0] = 0x52; nd->macaddr[1] = 0x54; nd->macaddr[2] = 0x00; nd->macaddr[3] = 0x12; nd->macaddr[4] = 0x34; nd->macaddr[5] = 0x56 + idx; if (qemu_opt_get(opts, "macaddr") && net_parse_macaddr(nd->macaddr, qemu_opt_get(opts, "macaddr")) < 0) { qemu_error("invalid syntax for ethernet address\n"); return -1; } nd->nvectors = qemu_opt_get_number(opts, "vectors", NIC_NVECTORS_UNSPECIFIED); if (nd->nvectors != NIC_NVECTORS_UNSPECIFIED && (nd->nvectors < 0 || nd->nvectors > 0x7ffffff)) { qemu_error("invalid # of vectors: %d\n", nd->nvectors); return -1; } nd->used = 1; if (vlan) { nd->vlan->nb_guest_devs++; } nb_nics++; return idx; } | 20,057 |
0 | print_insn_sparc (bfd_vma memaddr, disassemble_info *info) { FILE *stream = info->stream; bfd_byte buffer[4]; unsigned long insn; sparc_opcode_hash *op; /* Nonzero of opcode table has been initialized. */ static int opcodes_initialized = 0; /* bfd mach number of last call. */ static unsigned long current_mach = 0; bfd_vma (*getword) (const unsigned char *); if (!opcodes_initialized || info->mach != current_mach) { int i; current_arch_mask = compute_arch_mask (info->mach); if (!opcodes_initialized) sorted_opcodes = malloc (sparc_num_opcodes * sizeof (sparc_opcode *)); /* Reset the sorted table so we can resort it. */ for (i = 0; i < sparc_num_opcodes; ++i) sorted_opcodes[i] = &sparc_opcodes[i]; qsort ((char *) sorted_opcodes, sparc_num_opcodes, sizeof (sorted_opcodes[0]), compare_opcodes); build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); current_mach = info->mach; opcodes_initialized = 1; } { int status = (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); if (status != 0) { (*info->memory_error_func) (status, memaddr, info); return -1; } } /* On SPARClite variants such as DANlite (sparc86x), instructions are always big-endian even when the machine is in little-endian mode. */ if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) getword = bfd_getb32; else getword = bfd_getl32; insn = getword (buffer); info->insn_info_valid = 1; /* We do return this info. */ info->insn_type = dis_nonbranch; /* Assume non branch insn. */ info->branch_delay_insns = 0; /* Assume no delay. */ info->target = 0; /* Assume no target known. */ for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) { const sparc_opcode *opcode = op->opcode; /* If the insn isn't supported by the current architecture, skip it. */ if (! (opcode->architecture & current_arch_mask)) continue; if ((opcode->match & insn) == opcode->match && (opcode->lose & insn) == 0) { /* Nonzero means that we have found an instruction which has the effect of adding or or'ing the imm13 field to rs1. */ int imm_added_to_rs1 = 0; int imm_ored_to_rs1 = 0; /* Nonzero means that we have found a plus sign in the args field of the opcode table. */ int found_plus = 0; /* Nonzero means we have an annulled branch. */ /* int is_annulled = 0; */ /* see FIXME below */ /* Do we have an `add' or `or' instruction combining an immediate with rs1? */ if (opcode->match == 0x80102000) /* or */ imm_ored_to_rs1 = 1; if (opcode->match == 0x80002000) /* add */ imm_added_to_rs1 = 1; if (X_RS1 (insn) != X_RD (insn) && strchr (opcode->args, 'r') != NULL) /* Can't do simple format if source and dest are different. */ continue; if (X_RS2 (insn) != X_RD (insn) && strchr (opcode->args, 'O') != NULL) /* Can't do simple format if source and dest are different. */ continue; (*info->fprintf_func) (stream, opcode->name); { const char *s; if (opcode->args[0] != ',') (*info->fprintf_func) (stream, " "); for (s = opcode->args; *s != '\0'; ++s) { while (*s == ',') { (*info->fprintf_func) (stream, ","); ++s; switch (*s) { case 'a': (*info->fprintf_func) (stream, "a"); /* is_annulled = 1; */ /* see FIXME below */ ++s; continue; case 'N': (*info->fprintf_func) (stream, "pn"); ++s; continue; case 'T': (*info->fprintf_func) (stream, "pt"); ++s; continue; default: break; } } (*info->fprintf_func) (stream, " "); switch (*s) { case '+': found_plus = 1; /* Fall through. */ default: (*info->fprintf_func) (stream, "%c", *s); break; case '#': (*info->fprintf_func) (stream, "0"); break; #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) case '1': case 'r': reg (X_RS1 (insn)); break; case '2': case 'O': reg (X_RS2 (insn)); break; case 'd': reg (X_RD (insn)); break; #undef reg #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) case 'e': freg (X_RS1 (insn)); break; case 'v': /* Double/even. */ case 'V': /* Quad/multiple of 4. */ fregx (X_RS1 (insn)); break; case 'f': freg (X_RS2 (insn)); break; case 'B': /* Double/even. */ case 'R': /* Quad/multiple of 4. */ fregx (X_RS2 (insn)); break; case 'g': freg (X_RD (insn)); break; case 'H': /* Double/even. */ case 'J': /* Quad/multiple of 4. */ fregx (X_RD (insn)); break; #undef freg #undef fregx #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) case 'b': creg (X_RS1 (insn)); break; case 'c': creg (X_RS2 (insn)); break; case 'D': creg (X_RD (insn)); break; #undef creg case 'h': (*info->fprintf_func) (stream, "%%hi(%#x)", ((unsigned) 0xFFFFFFFF & ((int) X_IMM22 (insn) << 10))); break; case 'i': /* 13 bit immediate. */ case 'I': /* 11 bit immediate. */ case 'j': /* 10 bit immediate. */ { int imm; if (*s == 'i') imm = X_SIMM (insn, 13); else if (*s == 'I') imm = X_SIMM (insn, 11); else imm = X_SIMM (insn, 10); /* Check to see whether we have a 1+i, and take note of that fact. Note: because of the way we sort the table, we will be matching 1+i rather than i+1, so it is OK to assume that i is after +, not before it. */ if (found_plus) imm_added_to_rs1 = 1; if (imm <= 9) (*info->fprintf_func) (stream, "%d", imm); else (*info->fprintf_func) (stream, "%#x", imm); } break; case 'X': /* 5 bit unsigned immediate. */ case 'Y': /* 6 bit unsigned immediate. */ { int imm = X_IMM (insn, *s == 'X' ? 5 : 6); if (imm <= 9) (info->fprintf_func) (stream, "%d", imm); else (info->fprintf_func) (stream, "%#x", (unsigned) imm); } break; case '3': (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); break; case 'K': { int mask = X_MEMBAR (insn); int bit = 0x40, printed_one = 0; const char *name; if (mask == 0) (info->fprintf_func) (stream, "0"); else while (bit) { if (mask & bit) { if (printed_one) (info->fprintf_func) (stream, "|"); name = sparc_decode_membar (bit); (info->fprintf_func) (stream, "%s", name); printed_one = 1; } bit >>= 1; } break; } case 'k': info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; (*info->print_address_func) (info->target, info); break; case 'G': info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; (*info->print_address_func) (info->target, info); break; case '6': case '7': case '8': case '9': (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); break; case 'z': (*info->fprintf_func) (stream, "%%icc"); break; case 'Z': (*info->fprintf_func) (stream, "%%xcc"); break; case 'E': (*info->fprintf_func) (stream, "%%ccr"); break; case 's': (*info->fprintf_func) (stream, "%%fprs"); break; case 'o': (*info->fprintf_func) (stream, "%%asi"); break; case 'W': (*info->fprintf_func) (stream, "%%tick"); break; case 'P': (*info->fprintf_func) (stream, "%%pc"); break; case '?': if (X_RS1 (insn) == 31) (*info->fprintf_func) (stream, "%%ver"); else if ((unsigned) X_RS1 (insn) < 17) (*info->fprintf_func) (stream, "%%%s", v9_priv_reg_names[X_RS1 (insn)]); else (*info->fprintf_func) (stream, "%%reserved"); break; case '!': if ((unsigned) X_RD (insn) < 17) (*info->fprintf_func) (stream, "%%%s", v9_priv_reg_names[X_RD (insn)]); else (*info->fprintf_func) (stream, "%%reserved"); break; case '$': if ((unsigned) X_RS1 (insn) < 32) (*info->fprintf_func) (stream, "%%%s", v9_hpriv_reg_names[X_RS1 (insn)]); else (*info->fprintf_func) (stream, "%%reserved"); break; case '%': if ((unsigned) X_RD (insn) < 32) (*info->fprintf_func) (stream, "%%%s", v9_hpriv_reg_names[X_RD (insn)]); else (*info->fprintf_func) (stream, "%%reserved"); break; case '/': if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) (*info->fprintf_func) (stream, "%%reserved"); else (*info->fprintf_func) (stream, "%%%s", v9a_asr_reg_names[X_RS1 (insn)-16]); break; case '_': if (X_RD (insn) < 16 || X_RD (insn) > 25) (*info->fprintf_func) (stream, "%%reserved"); else (*info->fprintf_func) (stream, "%%%s", v9a_asr_reg_names[X_RD (insn)-16]); break; case '*': { const char *name = sparc_decode_prefetch (X_RD (insn)); if (name) (*info->fprintf_func) (stream, "%s", name); else (*info->fprintf_func) (stream, "%ld", X_RD (insn)); break; } case 'M': (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); break; case 'm': (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); break; case 'L': info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; (*info->print_address_func) (info->target, info); break; case 'n': (*info->fprintf_func) (stream, "%#x", SEX (X_DISP22 (insn), 22)); break; case 'l': info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; (*info->print_address_func) (info->target, info); break; case 'A': { const char *name; if ((info->mach == bfd_mach_sparc_v8plusa) || ((info->mach >= bfd_mach_sparc_v9) && (info->mach <= bfd_mach_sparc_v9b))) name = sparc_decode_asi_v9 (X_ASI (insn)); else name = sparc_decode_asi_v8 (X_ASI (insn)); if (name) (*info->fprintf_func) (stream, "%s", name); else (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); break; } case 'C': (*info->fprintf_func) (stream, "%%csr"); break; case 'F': (*info->fprintf_func) (stream, "%%fsr"); break; case 'p': (*info->fprintf_func) (stream, "%%psr"); break; case 'q': (*info->fprintf_func) (stream, "%%fq"); break; case 'Q': (*info->fprintf_func) (stream, "%%cq"); break; case 't': (*info->fprintf_func) (stream, "%%tbr"); break; case 'w': (*info->fprintf_func) (stream, "%%wim"); break; case 'x': (*info->fprintf_func) (stream, "%ld", ((X_LDST_I (insn) << 8) + X_ASI (insn))); break; case 'y': (*info->fprintf_func) (stream, "%%y"); break; case 'u': case 'U': { int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); const char *name = sparc_decode_sparclet_cpreg (val); if (name) (*info->fprintf_func) (stream, "%s", name); else (*info->fprintf_func) (stream, "%%cpreg(%d)", val); break; } } } } /* If we are adding or or'ing something to rs1, then check to see whether the previous instruction was a sethi to the same register as in the sethi. If so, attempt to print the result of the add or or (in this context add and or do the same thing) and its symbolic value. */ if (imm_ored_to_rs1 || imm_added_to_rs1) { unsigned long prev_insn; int errcode; if (memaddr >= 4) errcode = (*info->read_memory_func) (memaddr - 4, buffer, sizeof (buffer), info); else errcode = 1; prev_insn = getword (buffer); if (errcode == 0) { /* If it is a delayed branch, we need to look at the instruction before the delayed branch. This handles sequences such as: sethi %o1, %hi(_foo), %o1 call _printf or %o1, %lo(_foo), %o1 */ if (is_delayed_branch (prev_insn)) { if (memaddr >= 8) errcode = (*info->read_memory_func) (memaddr - 8, buffer, sizeof (buffer), info); else errcode = 1; prev_insn = getword (buffer); } } /* If there was a problem reading memory, then assume the previous instruction was not sethi. */ if (errcode == 0) { /* Is it sethi to the same register? */ if ((prev_insn & 0xc1c00000) == 0x01000000 && X_RD (prev_insn) == X_RS1 (insn)) { (*info->fprintf_func) (stream, "\t! "); info->target = ((unsigned) 0xFFFFFFFF & ((int) X_IMM22 (prev_insn) << 10)); if (imm_added_to_rs1) info->target += X_SIMM (insn, 13); else info->target |= X_SIMM (insn, 13); (*info->print_address_func) (info->target, info); info->insn_type = dis_dref; info->data_size = 4; /* FIXME!!! */ } } } if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) { /* FIXME -- check is_annulled flag. */ if (opcode->flags & F_UNBR) info->insn_type = dis_branch; if (opcode->flags & F_CONDBR) info->insn_type = dis_condbranch; if (opcode->flags & F_JSR) info->insn_type = dis_jsr; if (opcode->flags & F_DELAYED) info->branch_delay_insns = 1; } return sizeof (buffer); } } info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ (*info->fprintf_func) (stream, _("unknown")); return sizeof (buffer); } | 20,058 |
0 | static int max7310_tx(I2CSlave *i2c, uint8_t data) { MAX7310State *s = MAX7310(i2c); uint8_t diff; int line; if (s->len ++ > 1) { #ifdef VERBOSE printf("%s: message too long (%i bytes)\n", __FUNCTION__, s->len); #endif return 1; } if (s->i2c_command_byte) { s->command = data; s->i2c_command_byte = 0; return 0; } switch (s->command) { case 0x01: /* Output port */ for (diff = (data ^ s->level) & ~s->direction; diff; diff &= ~(1 << line)) { line = ffs(diff) - 1; if (s->handler[line]) qemu_set_irq(s->handler[line], (data >> line) & 1); } s->level = (s->level & s->direction) | (data & ~s->direction); break; case 0x02: /* Polarity inversion */ s->polarity = data; break; case 0x03: /* Configuration */ s->level &= ~(s->direction ^ data); s->direction = data; break; case 0x04: /* Timeout */ s->status = data; break; case 0x00: /* Input port - ignore writes */ break; default: #ifdef VERBOSE printf("%s: unknown register %02x\n", __FUNCTION__, s->command); #endif return 1; } return 0; } | 20,059 |
0 | BlockInterfaceErrorAction drive_get_onerror(BlockDriverState *bdrv) { DriveInfo *dinfo; TAILQ_FOREACH(dinfo, &drives, next) { if (dinfo->bdrv == bdrv) return dinfo->onerror; } return BLOCK_ERR_STOP_ENOSPC; } | 20,061 |
0 | static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) { if (check_fit_tl(arg, 12)) tcg_out_movi_imm13(s, ret, arg); else { tcg_out_sethi(s, ret, arg); if (arg & 0x3ff) tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); } } | 20,062 |
0 | static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg) { uint8_t type; while (dev) { if (!pci_is_express(dev)) { /* just ignore it */ /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR? * Consider e.g. a PCI bridge above a PCI Express device. */ return; } type = pcie_cap_get_type(dev); if ((type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) && !pcie_aer_msg_vbridge(dev, msg)) { return; } if (!pcie_aer_msg_alldev(dev, msg)) { return; } if (type == PCI_EXP_TYPE_ROOT_PORT) { pcie_aer_msg_root_port(dev, msg); /* Root port can notify system itself, or send the error message to root complex event collector. */ /* * if root port is associated with an event collector, * return the root complex event collector here. * For now root complex event collector isn't supported. */ return; } dev = pci_bridge_get_device(dev->bus); } } | 20,063 |
0 | static int ide_drive_pio_post_load(void *opaque, int version_id) { IDEState *s = opaque; if (s->end_transfer_fn_idx < 0 || s->end_transfer_fn_idx > ARRAY_SIZE(transfer_end_table)) { return -EINVAL; } s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx]; s->data_ptr = s->io_buffer + s->cur_io_buffer_offset; s->data_end = s->data_ptr + s->cur_io_buffer_len; return 0; } | 20,065 |
0 | void timer_del(QEMUTimer *ts) { QEMUTimer **pt, *t; pt = &ts->timer_list->active_timers; for(;;) { t = *pt; if (!t) break; if (t == ts) { *pt = t->next; break; } pt = &t->next; } } | 20,066 |
0 | static int xen_host_pci_get_value(XenHostPCIDevice *d, const char *name, unsigned int *pvalue, int base) { char path[PATH_MAX]; char buf[XEN_HOST_PCI_GET_VALUE_BUFFER_SIZE]; int fd, rc; unsigned long value; char *endptr; xen_host_pci_sysfs_path(d, name, path, sizeof(path)); fd = open(path, O_RDONLY); if (fd == -1) { XEN_HOST_PCI_LOG("Error: Can't open %s: %s\n", path, strerror(errno)); return -errno; } do { rc = read(fd, &buf, sizeof (buf) - 1); if (rc < 0 && errno != EINTR) { rc = -errno; goto out; } } while (rc < 0); buf[rc] = 0; value = strtol(buf, &endptr, base); if (endptr == buf || *endptr != '\n') { rc = -1; } else if ((value == LONG_MIN || value == LONG_MAX) && errno == ERANGE) { rc = -errno; } else { rc = 0; *pvalue = value; } out: close(fd); return rc; } | 20,069 |
0 | uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } return wt2; } | 20,071 |
0 | static void test_visitor_in_native_list_int16(TestInputVisitorData *data, const void *unused) { test_native_list_integer_helper(data, unused, USER_DEF_NATIVE_LIST_UNION_KIND_S16); } | 20,072 |
0 | int get_osversion(void) { static int osversion; struct new_utsname buf; const char *s; int i, n, tmp; if (osversion) return osversion; if (qemu_uname_release && *qemu_uname_release) { s = qemu_uname_release; } else { if (sys_uname(&buf)) return 0; s = buf.release; } tmp = 0; for (i = 0; i < 3; i++) { n = 0; while (*s >= '0' && *s <= '9') { n *= 10; n += *s - '0'; s++; } tmp = (tmp << 8) + n; if (*s == '.') s++; } osversion = tmp; return osversion; } | 20,073 |
0 | static int colo_packet_compare_common(Packet *ppkt, Packet *spkt) { trace_colo_compare_ip_info(ppkt->size, inet_ntoa(ppkt->ip->ip_src), inet_ntoa(ppkt->ip->ip_dst), spkt->size, inet_ntoa(spkt->ip->ip_src), inet_ntoa(spkt->ip->ip_dst)); if (ppkt->size == spkt->size) { return memcmp(ppkt->data, spkt->data, spkt->size); } else { trace_colo_compare_main("Net packet size are not the same"); return -1; } } | 20,074 |
0 | static int gdb_handle_packet(GDBState *s, const char *line_buf) { CPUState *env; const char *p; int ch, reg_size, type, res, thread; char buf[MAX_PACKET_LENGTH]; uint8_t mem_buf[MAX_PACKET_LENGTH]; uint8_t *registers; target_ulong addr, len; #ifdef DEBUG_GDB printf("command='%s'\n", line_buf); #endif p = line_buf; ch = *p++; switch(ch) { case '?': /* TODO: Make this return the correct value for user-mode. */ snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP, s->c_cpu->cpu_index+1); put_packet(s, buf); /* Remove all the breakpoints when this query is issued, * because gdb is doing and initial connect and the state * should be cleaned up. */ gdb_breakpoint_remove_all(); break; case 'c': if (*p != '\0') { addr = strtoull(p, (char **)&p, 16); #if defined(TARGET_I386) s->c_cpu->eip = addr; #elif defined (TARGET_PPC) s->c_cpu->nip = addr; #elif defined (TARGET_SPARC) s->c_cpu->pc = addr; s->c_cpu->npc = addr + 4; #elif defined (TARGET_ARM) s->c_cpu->regs[15] = addr; #elif defined (TARGET_SH4) s->c_cpu->pc = addr; #elif defined (TARGET_MIPS) s->c_cpu->active_tc.PC = addr; #elif defined (TARGET_CRIS) s->c_cpu->pc = addr; #elif defined (TARGET_ALPHA) s->c_cpu->pc = addr; #endif } s->signal = 0; gdb_continue(s); return RS_IDLE; case 'C': s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16)); if (s->signal == -1) s->signal = 0; gdb_continue(s); return RS_IDLE; case 'k': /* Kill the target */ fprintf(stderr, "\nQEMU: Terminated via GDBstub\n"); exit(0); case 'D': /* Detach packet */ gdb_breakpoint_remove_all(); gdb_continue(s); put_packet(s, "OK"); break; case 's': if (*p != '\0') { addr = strtoull(p, (char **)&p, 16); #if defined(TARGET_I386) s->c_cpu->eip = addr; #elif defined (TARGET_PPC) s->c_cpu->nip = addr; #elif defined (TARGET_SPARC) s->c_cpu->pc = addr; s->c_cpu->npc = addr + 4; #elif defined (TARGET_ARM) s->c_cpu->regs[15] = addr; #elif defined (TARGET_SH4) s->c_cpu->pc = addr; #elif defined (TARGET_MIPS) s->c_cpu->active_tc.PC = addr; #elif defined (TARGET_CRIS) s->c_cpu->pc = addr; #elif defined (TARGET_ALPHA) s->c_cpu->pc = addr; #endif } cpu_single_step(s->c_cpu, sstep_flags); gdb_continue(s); return RS_IDLE; case 'F': { target_ulong ret; target_ulong err; ret = strtoull(p, (char **)&p, 16); if (*p == ',') { p++; err = strtoull(p, (char **)&p, 16); } else { err = 0; } if (*p == ',') p++; type = *p; if (gdb_current_syscall_cb) gdb_current_syscall_cb(s->c_cpu, ret, err); if (type == 'C') { put_packet(s, "T02"); } else { gdb_continue(s); } } break; case 'g': len = 0; for (addr = 0; addr < num_g_regs; addr++) { reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr); len += reg_size; } memtohex(buf, mem_buf, len); put_packet(s, buf); break; case 'G': registers = mem_buf; len = strlen(p) / 2; hextomem((uint8_t *)registers, p, len); for (addr = 0; addr < num_g_regs && len > 0; addr++) { reg_size = gdb_write_register(s->g_cpu, registers, addr); len -= reg_size; registers += reg_size; } put_packet(s, "OK"); break; case 'm': addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, NULL, 16); if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) { put_packet (s, "E14"); } else { memtohex(buf, mem_buf, len); put_packet(s, buf); } break; case 'M': addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, (char **)&p, 16); if (*p == ':') p++; hextomem(mem_buf, p, len); if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) put_packet(s, "E14"); else put_packet(s, "OK"); break; case 'p': /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable. This works, but can be very slow. Anything new enough to understand XML also knows how to use this properly. */ if (!gdb_has_xml) goto unknown_command; addr = strtoull(p, (char **)&p, 16); reg_size = gdb_read_register(s->g_cpu, mem_buf, addr); if (reg_size) { memtohex(buf, mem_buf, reg_size); put_packet(s, buf); } else { put_packet(s, "E14"); } break; case 'P': if (!gdb_has_xml) goto unknown_command; addr = strtoull(p, (char **)&p, 16); if (*p == '=') p++; reg_size = strlen(p) / 2; hextomem(mem_buf, p, reg_size); gdb_write_register(s->g_cpu, mem_buf, addr); put_packet(s, "OK"); break; case 'Z': case 'z': type = strtoul(p, (char **)&p, 16); if (*p == ',') p++; addr = strtoull(p, (char **)&p, 16); if (*p == ',') p++; len = strtoull(p, (char **)&p, 16); if (ch == 'Z') res = gdb_breakpoint_insert(addr, len, type); else res = gdb_breakpoint_remove(addr, len, type); if (res >= 0) put_packet(s, "OK"); else if (res == -ENOSYS) put_packet(s, ""); else put_packet(s, "E22"); break; case 'H': type = *p++; thread = strtoull(p, (char **)&p, 16); if (thread == -1 || thread == 0) { put_packet(s, "OK"); break; } for (env = first_cpu; env != NULL; env = env->next_cpu) if (env->cpu_index + 1 == thread) break; if (env == NULL) { put_packet(s, "E22"); break; } switch (type) { case 'c': s->c_cpu = env; put_packet(s, "OK"); break; case 'g': s->g_cpu = env; put_packet(s, "OK"); break; default: put_packet(s, "E22"); break; } break; case 'T': thread = strtoull(p, (char **)&p, 16); #ifndef CONFIG_USER_ONLY if (thread > 0 && thread < smp_cpus + 1) #else if (thread == 1) #endif put_packet(s, "OK"); else put_packet(s, "E22"); break; case 'q': case 'Q': /* parse any 'q' packets here */ if (!strcmp(p,"qemu.sstepbits")) { /* Query Breakpoint bit definitions */ snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", SSTEP_ENABLE, SSTEP_NOIRQ, SSTEP_NOTIMER); put_packet(s, buf); break; } else if (strncmp(p,"qemu.sstep",10) == 0) { /* Display or change the sstep_flags */ p += 10; if (*p != '=') { /* Display current setting */ snprintf(buf, sizeof(buf), "0x%x", sstep_flags); put_packet(s, buf); break; } p++; type = strtoul(p, (char **)&p, 16); sstep_flags = type; put_packet(s, "OK"); break; } else if (strcmp(p,"C") == 0) { /* "Current thread" remains vague in the spec, so always return * the first CPU (gdb returns the first thread). */ put_packet(s, "QC1"); break; } else if (strcmp(p,"fThreadInfo") == 0) { s->query_cpu = first_cpu; goto report_cpuinfo; } else if (strcmp(p,"sThreadInfo") == 0) { report_cpuinfo: if (s->query_cpu) { snprintf(buf, sizeof(buf), "m%x", s->query_cpu->cpu_index+1); put_packet(s, buf); s->query_cpu = s->query_cpu->next_cpu; } else put_packet(s, "l"); break; } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) { thread = strtoull(p+16, (char **)&p, 16); for (env = first_cpu; env != NULL; env = env->next_cpu) if (env->cpu_index + 1 == thread) { len = snprintf((char *)mem_buf, sizeof(mem_buf), "CPU#%d [%s]", env->cpu_index, env->halted ? "halted " : "running"); memtohex(buf, mem_buf, len); put_packet(s, buf); break; } break; } #ifdef CONFIG_LINUX_USER else if (strncmp(p, "Offsets", 7) == 0) { TaskState *ts = s->c_cpu->opaque; snprintf(buf, sizeof(buf), "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx ";Bss=" TARGET_ABI_FMT_lx, ts->info->code_offset, ts->info->data_offset, ts->info->data_offset); put_packet(s, buf); break; } #endif if (strncmp(p, "Supported", 9) == 0) { snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH); #ifdef GDB_CORE_XML strcat(buf, ";qXfer:features:read+"); #endif put_packet(s, buf); break; } #ifdef GDB_CORE_XML if (strncmp(p, "Xfer:features:read:", 19) == 0) { const char *xml; target_ulong total_len; gdb_has_xml = 1; p += 19; xml = get_feature_xml(p, &p); if (!xml) { snprintf(buf, sizeof(buf), "E00"); put_packet(s, buf); break; } if (*p == ':') p++; addr = strtoul(p, (char **)&p, 16); if (*p == ',') p++; len = strtoul(p, (char **)&p, 16); total_len = strlen(xml); if (addr > total_len) { snprintf(buf, sizeof(buf), "E00"); put_packet(s, buf); break; } if (len > (MAX_PACKET_LENGTH - 5) / 2) len = (MAX_PACKET_LENGTH - 5) / 2; if (len < total_len - addr) { buf[0] = 'm'; len = memtox(buf + 1, xml + addr, len); } else { buf[0] = 'l'; len = memtox(buf + 1, xml + addr, total_len - addr); } put_packet_binary(s, buf, len + 1); break; } #endif /* Unrecognised 'q' command. */ goto unknown_command; default: unknown_command: /* put empty packet */ buf[0] = '\0'; put_packet(s, buf); break; } return RS_IDLE; } | 20,075 |
0 | static void s390_memory_init(ram_addr_t mem_size) { MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); /* allocate RAM for core */ memory_region_allocate_system_memory(ram, NULL, "s390.ram", mem_size); memory_region_add_subregion(sysmem, 0, ram); /* Initialize storage key device */ s390_skeys_init(); /* Initialize storage attributes device */ s390_stattrib_init(); } | 20,076 |
0 | static int read_braindead_odml_indx(AVFormatContext *s, int frame_num){ AVIContext *avi = s->priv_data; AVIOContext *pb = s->pb; int longs_pre_entry= avio_rl16(pb); int index_sub_type = avio_r8(pb); int index_type = avio_r8(pb); int entries_in_use = avio_rl32(pb); int chunk_id = avio_rl32(pb); int64_t base = avio_rl64(pb); int stream_id= 10*((chunk_id&0xFF) - '0') + (((chunk_id>>8)&0xFF) - '0'); AVStream *st; AVIStream *ast; int i; int64_t last_pos= -1; int64_t filesize= avio_size(s->pb); av_dlog(s, "longs_pre_entry:%d index_type:%d entries_in_use:%d chunk_id:%X base:%16"PRIX64"\n", longs_pre_entry,index_type, entries_in_use, chunk_id, base); if(stream_id >= s->nb_streams || stream_id < 0) return -1; st= s->streams[stream_id]; ast = st->priv_data; if(index_sub_type) return -1; avio_rl32(pb); if(index_type && longs_pre_entry != 2) return -1; if(index_type>1) return -1; if(filesize > 0 && base >= filesize){ av_log(s, AV_LOG_ERROR, "ODML index invalid\n"); if(base>>32 == (base & 0xFFFFFFFF) && (base & 0xFFFFFFFF) < filesize && filesize <= 0xFFFFFFFF) base &= 0xFFFFFFFF; else return -1; } for(i=0; i<entries_in_use; i++){ if(index_type){ int64_t pos= avio_rl32(pb) + base - 8; int len = avio_rl32(pb); int key= len >= 0; len &= 0x7FFFFFFF; av_dlog(s, "pos:%"PRId64", len:%X\n", pos, len); if(pb->eof_reached) return -1; if(last_pos == pos || pos == base - 8) avi->non_interleaved= 1; if(last_pos != pos && (len || !ast->sample_size)) av_add_index_entry(st, pos, ast->cum_len, len, 0, key ? AVINDEX_KEYFRAME : 0); ast->cum_len += get_duration(ast, len); last_pos= pos; }else{ int64_t offset, pos; int duration; offset = avio_rl64(pb); avio_rl32(pb); /* size */ duration = avio_rl32(pb); if(pb->eof_reached) return -1; pos = avio_tell(pb); if(avi->odml_depth > MAX_ODML_DEPTH){ av_log(s, AV_LOG_ERROR, "Too deeply nested ODML indexes\n"); return -1; } avio_seek(pb, offset+8, SEEK_SET); avi->odml_depth++; read_braindead_odml_indx(s, frame_num); avi->odml_depth--; frame_num += duration; avio_seek(pb, pos, SEEK_SET); } } avi->index_loaded=1; return 0; } | 20,078 |
0 | static void qapi_dealloc_start_list(Visitor *v, const char *name, Error **errp) { QapiDeallocVisitor *qov = to_qov(v); qapi_dealloc_push(qov, NULL); } | 20,079 |
0 | int event_notifier_set_handler(EventNotifier *e, EventNotifierHandler *handler) { return qemu_set_fd_handler(e->fd, (IOHandler *)handler, NULL, e); } | 20,080 |
0 | static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc = NULL; char *typename; int i; if (cpu_model == NULL) { return NULL; } oc = object_class_by_name(cpu_model); if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && !object_class_is_abstract(oc)) { return oc; } for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { oc = object_class_by_name(alpha_cpu_aliases[i].typename); assert(oc != NULL && !object_class_is_abstract(oc)); return oc; } } typename = g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model); oc = object_class_by_name(typename); g_free(typename); if (oc != NULL && object_class_is_abstract(oc)) { oc = NULL; } return oc; } | 20,081 |
0 | void qmp_migrate(const char *uri, bool has_blk, bool blk, bool has_inc, bool inc, bool has_detach, bool detach, Error **errp) { Error *local_err = NULL; MigrationState *s = migrate_get_current(); MigrationParams params; const char *p; params.blk = has_blk && blk; params.shared = has_inc && inc; if (migration_is_setup_or_active(s->state) || s->state == MIGRATION_STATUS_CANCELLING) { error_setg(errp, QERR_MIGRATION_ACTIVE); return; } if (runstate_check(RUN_STATE_INMIGRATE)) { error_setg(errp, "Guest is waiting for an incoming migration"); return; } if (migration_is_blocked(errp)) { return; } s = migrate_init(¶ms); if (strstart(uri, "tcp:", &p)) { tcp_start_outgoing_migration(s, p, &local_err); #ifdef CONFIG_RDMA } else if (strstart(uri, "rdma:", &p)) { rdma_start_outgoing_migration(s, p, &local_err); #endif } else if (strstart(uri, "exec:", &p)) { exec_start_outgoing_migration(s, p, &local_err); } else if (strstart(uri, "unix:", &p)) { unix_start_outgoing_migration(s, p, &local_err); } else if (strstart(uri, "fd:", &p)) { fd_start_outgoing_migration(s, p, &local_err); } else { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "uri", "a valid migration protocol"); migrate_set_state(&s->state, MIGRATION_STATUS_SETUP, MIGRATION_STATUS_FAILED); return; } if (local_err) { migrate_fd_error(s, local_err); error_propagate(errp, local_err); return; } } | 20,082 |
0 | static void imx_avic_write(void *opaque, target_phys_addr_t offset, uint64_t val, unsigned size) { IMXAVICState *s = (IMXAVICState *)opaque; /* Vector Registers not yet supported */ if (offset >= 0x100 && offset <= 0x2fc) { IPRINTF("imx_avic_write to vector register %d ignored\n", (unsigned int)((offset - 0x100) >> 2)); return; } DPRINTF("imx_avic_write(0x%x) = %x\n", (unsigned int)offset>>2, (unsigned int)val); switch (offset >> 2) { case 0: /* Interrupt Control Register, INTCNTL */ s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM); if (s->intcntl & ABFEN) { s->intcntl &= ~(val & ABFLAG); } break; case 1: /* Normal Interrupt Mask Register, NIMASK */ s->intmask = val & 0x1f; break; case 2: /* Interrupt Enable Number Register, INTENNUM */ DPRINTF("enable(%d)\n", (int)val); val &= 0x3f; s->enabled |= (1ULL << val); break; case 3: /* Interrupt Disable Number Register, INTDISNUM */ DPRINTF("disable(%d)\n", (int)val); val &= 0x3f; s->enabled &= ~(1ULL << val); break; case 4: /* Interrupt Enable Number Register High */ s->enabled = (s->enabled & 0xffffffffULL) | (val << 32); break; case 5: /* Interrupt Enable Number Register Low */ s->enabled = (s->enabled & 0xffffffff00000000ULL) | val; break; case 6: /* Interrupt Type Register High */ s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32); break; case 7: /* Interrupt Type Register Low */ s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val; break; case 8: /* Normal Interrupt Priority Register 7 */ case 9: /* Normal Interrupt Priority Register 6 */ case 10:/* Normal Interrupt Priority Register 5 */ case 11:/* Normal Interrupt Priority Register 4 */ case 12:/* Normal Interrupt Priority Register 3 */ case 13:/* Normal Interrupt Priority Register 2 */ case 14:/* Normal Interrupt Priority Register 1 */ case 15:/* Normal Interrupt Priority Register 0 */ s->prio[15-(offset>>2)] = val; break; /* Read-only registers, writes ignored */ case 16:/* Normal Interrupt Vector and Status register */ case 17:/* Fast Interrupt vector and status register */ case 18:/* Interrupt source register high */ case 19:/* Interrupt source register low */ return; case 20:/* Interrupt Force Register high */ s->pending = (s->pending & 0xffffffffULL) | (val << 32); break; case 21:/* Interrupt Force Register low */ s->pending = (s->pending & 0xffffffff00000000ULL) | val; break; case 22:/* Normal Interrupt Pending Register High */ case 23:/* Normal Interrupt Pending Register Low */ case 24: /* Fast Interrupt Pending Register High */ case 25: /* Fast Interrupt Pending Register Low */ return; default: IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset); } imx_avic_update(s); } | 20,083 |
0 | QemuOpts *qemu_opts_create(QemuOptsList *list, const char *id, int fail_if_exists) { QemuOpts *opts = NULL; if (id) { opts = qemu_opts_find(list, id); if (opts != NULL) { if (fail_if_exists) { fprintf(stderr, "tried to create id \"%s\" twice for \"%s\"\n", id, list->name); return NULL; } else { return opts; } } } opts = qemu_mallocz(sizeof(*opts)); if (id) { opts->id = qemu_strdup(id); } opts->list = list; TAILQ_INIT(&opts->head); TAILQ_INSERT_TAIL(&list->head, opts, next); return opts; } | 20,084 |
0 | static void tco_timer_expired(void *opaque) { TCOIORegs *tr = opaque; ICH9LPCPMRegs *pm = container_of(tr, ICH9LPCPMRegs, tco_regs); ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm); uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS); tr->tco.rld = 0; tr->tco.sts1 |= TCO_TIMEOUT; if (++tr->timeouts_no == 2) { tr->tco.sts2 |= TCO_SECOND_TO_STS; tr->tco.sts2 |= TCO_BOOT_STS; tr->timeouts_no = 0; if (!(gcs & ICH9_CC_GCS_NO_REBOOT)) { watchdog_perform_action(); tco_timer_stop(tr); return; } } if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) { ich9_generate_smi(); } else { ich9_generate_nmi(); } tr->tco.rld = tr->tco.tmr; tco_timer_reload(tr); } | 20,085 |
0 | static void access_with_adjusted_size(hwaddr addr, uint64_t *value, unsigned size, unsigned access_size_min, unsigned access_size_max, void (*access)(MemoryRegion *mr, hwaddr addr, uint64_t *value, unsigned size, unsigned shift, uint64_t mask), MemoryRegion *mr) { uint64_t access_mask; unsigned access_size; unsigned i; if (!access_size_min) { access_size_min = 1; } if (!access_size_max) { access_size_max = 4; } /* FIXME: support unaligned access? */ access_size = MAX(MIN(size, access_size_max), access_size_min); access_mask = -1ULL >> (64 - access_size * 8); for (i = 0; i < size; i += access_size) { #ifdef TARGET_WORDS_BIGENDIAN access(mr, addr + i, value, access_size, (size - access_size - i) * 8, access_mask); #else access(mr, addr + i, value, access_size, i * 8, access_mask); #endif } } | 20,087 |
0 | static void scsi_disk_emulate_write_same(SCSIDiskReq *r, uint8_t *inbuf) { SCSIRequest *req = &r->req; SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, req->dev); uint32_t nb_sectors = scsi_data_cdb_length(r->req.cmd.buf); WriteSameCBData *data; uint8_t *buf; int i; /* Fail if PBDATA=1 or LBDATA=1 or ANCHOR=1. */ if (nb_sectors == 0 || (req->cmd.buf[1] & 0x16)) { scsi_check_condition(r, SENSE_CODE(INVALID_FIELD)); return; } if (bdrv_is_read_only(s->qdev.conf.bs)) { scsi_check_condition(r, SENSE_CODE(WRITE_PROTECTED)); return; } if (!check_lba_range(s, r->req.cmd.lba, nb_sectors)) { scsi_check_condition(r, SENSE_CODE(LBA_OUT_OF_RANGE)); return; } if (buffer_is_zero(inbuf, s->qdev.blocksize)) { int flags = (req->cmd.buf[1] & 0x8) ? BDRV_REQ_MAY_UNMAP : 0; /* The request is used as the AIO opaque value, so add a ref. */ scsi_req_ref(&r->req); block_acct_start(bdrv_get_stats(s->qdev.conf.bs), &r->acct, nb_sectors * s->qdev.blocksize, BLOCK_ACCT_WRITE); r->req.aiocb = bdrv_aio_write_zeroes(s->qdev.conf.bs, r->req.cmd.lba * (s->qdev.blocksize / 512), nb_sectors * (s->qdev.blocksize / 512), flags, scsi_aio_complete, r); return; } data = g_new0(WriteSameCBData, 1); data->r = r; data->sector = r->req.cmd.lba * (s->qdev.blocksize / 512); data->nb_sectors = nb_sectors * (s->qdev.blocksize / 512); data->iov.iov_len = MIN(data->nb_sectors * 512, SCSI_WRITE_SAME_MAX); data->iov.iov_base = buf = qemu_blockalign(s->qdev.conf.bs, data->iov.iov_len); qemu_iovec_init_external(&data->qiov, &data->iov, 1); for (i = 0; i < data->iov.iov_len; i += s->qdev.blocksize) { memcpy(&buf[i], inbuf, s->qdev.blocksize); } scsi_req_ref(&r->req); block_acct_start(bdrv_get_stats(s->qdev.conf.bs), &r->acct, data->iov.iov_len, BLOCK_ACCT_WRITE); r->req.aiocb = bdrv_aio_writev(s->qdev.conf.bs, data->sector, &data->qiov, data->iov.iov_len / 512, scsi_write_same_complete, data); } | 20,088 |
0 | static int kvm_put_msr_feature_control(X86CPU *cpu) { struct { struct kvm_msrs info; struct kvm_msr_entry entry; } msr_data; kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, cpu->env.msr_ia32_feature_control); msr_data.info.nmsrs = 1; return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); } | 20,089 |
0 | static void ppc_prep_init (int ram_size, int vga_ram_size, const char *boot_device, DisplayState *ds, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL, *envs[MAX_CPUS]; char buf[1024]; nvram_t nvram; m48t59_t *m48t59; int PPC_io_memory; int linux_boot, i, nb_nics1, bios_size; unsigned long bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; qemu_irq *i8259; int ppc_boot_device; sysctrl = qemu_mallocz(sizeof(sysctrl_t)); if (sysctrl == NULL) return; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) cpu_model = "default"; for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); qemu_register_reset(&cpu_ppc_reset, env); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); envs[i] = env; } /* allocate RAM */ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); /* allocate and load BIOS */ bios_offset = ram_size + vga_ram_size; if (bios_name == NULL) bios_name = BIOS_FILENAME; snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); bios_size = load_image(buf, phys_ram_base + bios_offset); if (bios_size < 0 || bios_size > BIOS_SIZE) { cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf); exit(1); } if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); } bios_size = (bios_size + 0xfff) & ~0xfff; cpu_register_physical_memory((uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM); if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); if (kernel_size < 0) { cpu_abort(env, "qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image(initrd_filename, phys_ram_base + initrd_base); if (initrd_size < 0) { cpu_abort(env, "qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } } else { initrd_base = 0; initrd_size = 0; } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; /* For now, OHW cannot boot from the network. */ for (i = 0; boot_device[i] != '\0'; i++) { if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for Mac99 machine\n"); exit(1); } } isa_mem_base = 0xc0000000; if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { cpu_abort(env, "Only 6xx bus is supported on PREP machine\n"); exit(1); } i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); pci_bus = pci_prep_init(i8259); // pci_bus = i440fx_init(); /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read, PPC_prep_io_write, sysctrl); cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); /* init basic PC hardware */ pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size, 0, 0); // openpic = openpic_init(0x00000000, 0xF0000000, 1); // pit = pit_init(0x40, i8259[0]); rtc_init(0x70, i8259[8]); serial_init(0x3f8, i8259[4], serial_hds[0]); nb_nics1 = nb_nics; if (nb_nics1 > NE2000_NB_MAX) nb_nics1 = NE2000_NB_MAX; for(i = 0; i < nb_nics1; i++) { if (nd_table[i].model == NULL || strcmp(nd_table[i].model, "ne2k_isa") == 0) { isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); } else { pci_nic_init(pci_bus, &nd_table[i], -1); } } for(i = 0; i < 2; i++) { isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], bs_table[2 * i], bs_table[2 * i + 1]); } i8042_init(i8259[1], i8259[12], 0x60); DMA_init(1); // AUD_init(); // SB16_init(); fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); /* Register speaker port */ register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); /* Register fake IO ports for PREP */ sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); /* System control ports */ register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); /* PCI intack location */ PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read, PPC_intack_write, NULL); cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); /* PowerPC control and status register group */ #if 0 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL); cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); #endif if (usb_enabled) { usb_ohci_init_pci(pci_bus, 3, -1); } m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); if (m48t59 == NULL) return; sysctrl->nvram = m48t59; /* Initialise NVRAM */ nvram.opaque = m48t59; nvram.read_fn = &m48t59_read; nvram.write_fn = &m48t59_write; PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, kernel_base, kernel_size, kernel_cmdline, initrd_base, initrd_size, /* XXX: need an option to load a NVRAM image */ 0, graphic_width, graphic_height, graphic_depth); /* Special port to get debug messages from Open-Firmware */ register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); } | 20,090 |
0 | static void mpeg1_skip_picture(MpegEncContext *s, int pict_num) { assert(s->codec_id == CODEC_ID_MPEG1VIDEO); // mpeg2 can do these repeat things /* mpeg1 picture header */ put_header(s, PICTURE_START_CODE); /* temporal reference */ put_bits(&s->pb, 10, pict_num & 0x3ff); put_bits(&s->pb, 3, P_TYPE); put_bits(&s->pb, 16, 0xffff); /* non constant bit rate */ put_bits(&s->pb, 1, 1); /* integer coordinates */ put_bits(&s->pb, 3, 1); /* forward_f_code */ put_bits(&s->pb, 1, 0); /* extra bit picture */ /* only one slice */ put_header(s, SLICE_MIN_START_CODE); put_bits(&s->pb, 5, 1); /* quantizer scale */ put_bits(&s->pb, 1, 0); /* slice extra information */ encode_mb_skip_run(s, 0); /* empty macroblock */ put_bits(&s->pb, 3, 1); /* motion only */ /* zero motion x & y */ put_bits(&s->pb, 1, 1); put_bits(&s->pb, 1, 1); /* output a number of empty slice */ encode_mb_skip_run(s, s->mb_width * s->mb_height - 2); /* empty macroblock */ put_bits(&s->pb, 3, 1); /* motion only */ /* zero motion x & y */ put_bits(&s->pb, 1, 1); put_bits(&s->pb, 1, 1); } | 20,091 |
0 | static int ehci_process_itd(EHCIState *ehci, EHCIitd *itd, uint32_t addr) { USBDevice *dev; USBEndpoint *ep; uint32_t i, len, pid, dir, devaddr, endp; uint32_t pg, off, ptr1, ptr2, max, mult; ehci->periodic_sched_active = PERIODIC_ACTIVE; dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); for(i = 0; i < 8; i++) { if (itd->transact[i] & ITD_XACT_ACTIVE) { pg = get_field(itd->transact[i], ITD_XACT_PGSEL); off = itd->transact[i] & ITD_XACT_OFFSET_MASK; ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); len = get_field(itd->transact[i], ITD_XACT_LENGTH); if (len > max * mult) { len = max * mult; } if (len > BUFF_SIZE) { return -1; } qemu_sglist_init(&ehci->isgl, DEVICE(ehci), 2, ehci->as); if (off + len > 4096) { /* transfer crosses page border */ uint32_t len2 = off + len - 4096; uint32_t len1 = len - len2; qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); qemu_sglist_add(&ehci->isgl, ptr2, len2); } else { qemu_sglist_add(&ehci->isgl, ptr1 + off, len); } pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; dev = ehci_find_device(ehci, devaddr); ep = usb_ep_get(dev, pid, endp); if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false, (itd->transact[i] & ITD_XACT_IOC) != 0); usb_packet_map(&ehci->ipacket, &ehci->isgl); usb_handle_packet(dev, &ehci->ipacket); usb_packet_unmap(&ehci->ipacket, &ehci->isgl); } else { DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); ehci->ipacket.status = USB_RET_NAK; ehci->ipacket.actual_length = 0; } qemu_sglist_destroy(&ehci->isgl); switch (ehci->ipacket.status) { case USB_RET_SUCCESS: break; default: fprintf(stderr, "Unexpected iso usb result: %d\n", ehci->ipacket.status); /* Fall through */ case USB_RET_IOERROR: case USB_RET_NODEV: /* 3.3.2: XACTERR is only allowed on IN transactions */ if (dir) { itd->transact[i] |= ITD_XACT_XACTERR; ehci_raise_irq(ehci, USBSTS_ERRINT); } break; case USB_RET_BABBLE: itd->transact[i] |= ITD_XACT_BABBLE; ehci_raise_irq(ehci, USBSTS_ERRINT); break; case USB_RET_NAK: /* no data for us, so do a zero-length transfer */ ehci->ipacket.actual_length = 0; break; } if (!dir) { set_field(&itd->transact[i], len - ehci->ipacket.actual_length, ITD_XACT_LENGTH); /* OUT */ } else { set_field(&itd->transact[i], ehci->ipacket.actual_length, ITD_XACT_LENGTH); /* IN */ } if (itd->transact[i] & ITD_XACT_IOC) { ehci_raise_irq(ehci, USBSTS_INT); } itd->transact[i] &= ~ITD_XACT_ACTIVE; } } return 0; } | 20,092 |
0 | uint64_t helper_fctid (uint64_t arg) { CPU_DoubleU farg; farg.ll = arg; if (unlikely(float64_is_signaling_nan(farg.d))) { /* sNaN conversion */ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) { /* qNan / infinity conversion */ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); } else { farg.ll = float64_to_int64(farg.d, &env->fp_status); } return farg.ll; } | 20,093 |
0 | static void pc_q35_init(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); Q35PCIHost *q35_host; PCIHostState *phb; PCIBus *host_bus; PCIDevice *lpc; BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; MemoryRegion *pci_memory; MemoryRegion *rom_memory; MemoryRegion *ram_memory; GSIState *gsi_state; ISABus *isa_bus; int pci_enabled = 1; qemu_irq *gsi; qemu_irq *i8259; int i; ICH9LPCState *ich9_lpc; PCIDevice *ahci; DeviceState *icc_bridge; PcGuestInfo *guest_info; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). * If it doesn't, we need to split it in chunks below and above 4G. * In any case, try to make sure that guest addresses aligned at * 1G boundaries get mapped to host addresses aligned at 1G boundaries. * For old machine types, use whatever split we used historically to avoid * breaking migration. */ if (machine->ram_size >= 0xb0000000) { lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; } else { lowmem = 0xb0000000; } /* Handle the machine opt max-ram-below-4g. It is basically doing * min(qemu limit, user limit). */ if (lowmem > pcms->max_ram_below_4g) { lowmem = pcms->max_ram_below_4g; if (machine->ram_size - lowmem > lowmem && lowmem & ((1ULL << 30) - 1)) { error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 ") not a multiple of 1G; possible bad performance.", pcms->max_ram_below_4g); } } if (machine->ram_size >= lowmem) { pcms->above_4g_mem_size = machine->ram_size - lowmem; pcms->below_4g_mem_size = lowmem; } else { pcms->above_4g_mem_size = 0; pcms->below_4g_mem_size = machine->ram_size; } if (xen_enabled() && xen_hvm_init(pcms, &ram_memory) != 0) { fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); exit(1); } icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); object_property_add_child(qdev_get_machine(), "icc-bridge", OBJECT(icc_bridge), NULL); pc_cpus_init(machine->cpu_model, icc_bridge); pc_acpi_init("q35-acpi-dsdt.aml"); kvmclock_create(); /* pci enabled */ if (pci_enabled) { pci_memory = g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory = pci_memory; } else { pci_memory = NULL; rom_memory = get_system_memory(); } guest_info = pc_guest_info_init(pcms); guest_info->isapc_ram_fw = false; guest_info->has_acpi_build = has_acpi_build; guest_info->has_reserved_memory = has_reserved_memory; guest_info->rsdp_in_ram = rsdp_in_ram; /* Migration was not supported in 2.0 for Q35, so do not bother * with this hack (see hw/i386/acpi-build.c). */ guest_info->legacy_acpi_table_size = 0; if (smbios_defaults) { /* These values are guest ABI, do not change */ smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", mc->name, smbios_legacy_mode, smbios_uuid_encoded, SMBIOS_ENTRY_POINT_21); } /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, guest_info); } /* irq lines */ gsi_state = g_malloc0(sizeof(*gsi_state)); if (kvm_irqchip_in_kernel()) { kvm_pc_setup_irq_routing(pci_enabled); gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, GSI_NUM_PINS); } else { gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); } /* create pci host bus */ q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); q35_host->mch.ram_memory = ram_memory; q35_host->mch.pci_address_space = pci_memory; q35_host->mch.system_memory = get_system_memory(); q35_host->mch.address_space_io = get_system_io(); q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size; q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size; q35_host->mch.guest_info = guest_info; /* pci */ qdev_init_nofail(DEVICE(q35_host)); phb = PCI_HOST_BRIDGE(q35_host); host_bus = phb->bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, (Object **)&pcms->acpi_dev, object_property_allow_set_link, OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); object_property_set_link(OBJECT(machine), OBJECT(lpc), PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); ich9_lpc = ICH9_LPC_DEVICE(lpc); ich9_lpc->pic = gsi; ich9_lpc->ioapic = gsi_state->ioapic_irq; pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); isa_bus = ich9_lpc->isa_bus; /*end early*/ isa_bus_irqs(isa_bus, gsi); if (kvm_irqchip_in_kernel()) { i8259 = kvm_i8259_init(isa_bus); } else if (xen_enabled()) { i8259 = xen_interrupt_controller_init(); } else { i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); } for (i = 0; i < ISA_NUM_IRQS; i++) { gsi_state->i8259_irq[i] = i8259[i]; } if (pci_enabled) { ioapic_init_gsi(gsi_state, "q35"); } qdev_init_nofail(icc_bridge); pc_register_ferr_irq(gsi[13]); assert(pcms->vmport != ON_OFF_AUTO_MAX); if (pcms->vmport == ON_OFF_AUTO_AUTO) { pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; } /* init basic PC hardware */ pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy, (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104); /* connect pm stuff to lpc */ ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms), !mc->no_tco); /* ahci and SATA device, for q35 1 ahci controller is built-in */ ahci = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), true, "ich9-ahci"); idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); ahci_ide_create_devs(ahci, hd); if (usb_enabled()) { /* Should we create 6 UHCI according to ich9 spec? */ ehci_create_ich9_with_companions(host_bus, 0x1d); } /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(ich9_smb_init(host_bus, PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 0xb100), 8, NULL, 0); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); /* the rest devices to which pci devfn is automatically assigned */ pc_vga_init(isa_bus, host_bus); pc_nic_init(isa_bus, host_bus); if (pci_enabled) { pc_pci_device_init(host_bus); } } | 20,094 |
0 | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) { M48t59State *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr) << 24; retval |= m48t59_read(NVRAM, addr + 1) << 16; retval |= m48t59_read(NVRAM, addr + 2) << 8; retval |= m48t59_read(NVRAM, addr + 3); return retval; } | 20,096 |
0 | static void tcg_out_label(TCGContext *s, int label_index, tcg_insn_unit *ptr) { TCGLabel *l = &s->labels[label_index]; intptr_t value = (intptr_t)ptr; TCGRelocation *r; assert(!l->has_value); for (r = l->u.first_reloc; r != NULL; r = r->next) { patch_reloc(r->ptr, r->type, value, r->addend); } l->has_value = 1; l->u.value_ptr = ptr; } | 20,097 |
0 | static CharDriverState *qemu_chr_open_mux(CharDriverState *drv) { CharDriverState *chr; MuxDriver *d; chr = g_malloc0(sizeof(CharDriverState)); d = g_malloc0(sizeof(MuxDriver)); chr->opaque = d; d->drv = drv; d->focus = -1; chr->chr_write = mux_chr_write; chr->chr_update_read_handler = mux_chr_update_read_handler; chr->chr_accept_input = mux_chr_accept_input; /* Frontend guest-open / -close notification is not support with muxes */ chr->chr_set_fe_open = NULL; /* only default to opened state if we've realized the initial * set of muxes */ chr->explicit_be_open = muxes_realized ? 0 : 1; chr->is_mux = 1; return chr; } | 20,099 |
0 | static int xen_domain_watcher(void) { int qemu_running = 1; int fd[2], i, n, rc; char byte; if (pipe(fd) != 0) { qemu_log("%s: Huh? pipe error: %s\n", __FUNCTION__, strerror(errno)); return -1; } if (fork() != 0) return 0; /* not child */ /* close all file handles, except stdio/out/err, * our watch pipe and the xen interface handle */ n = getdtablesize(); for (i = 3; i < n; i++) { if (i == fd[0]) continue; if (i == xen_xc) continue; close(i); } /* ignore term signals */ signal(SIGINT, SIG_IGN); signal(SIGTERM, SIG_IGN); /* wait for qemu exiting */ while (qemu_running) { rc = read(fd[0], &byte, 1); switch (rc) { case -1: if (errno == EINTR) continue; qemu_log("%s: Huh? read error: %s\n", __FUNCTION__, strerror(errno)); qemu_running = 0; break; case 0: /* EOF -> qemu exited */ qemu_running = 0; break; default: qemu_log("%s: Huh? data on the watch pipe?\n", __FUNCTION__); break; } } /* cleanup */ qemu_log("%s: destroy domain %d\n", __FUNCTION__, xen_domid); xc_domain_destroy(xen_xc, xen_domid); _exit(0); } | 20,100 |
0 | static int vnc_update_client(VncState *vs, int has_dirty, bool sync) { if (vs->need_update && vs->csock != -1) { VncDisplay *vd = vs->vd; VncJob *job; int y; int height; int n = 0; if (vs->output.offset && !vs->audio_cap && !vs->force_update) /* kernel send buffers are full -> drop frames to throttle */ return 0; if (!has_dirty && !vs->audio_cap && !vs->force_update) return 0; /* * Send screen updates to the vnc client using the server * surface and server dirty map. guest surface updates * happening in parallel don't disturb us, the next pass will * send them to the client. */ job = vnc_job_new(vs); height = MIN(pixman_image_get_height(vd->server), vs->client_height); y = 0; for (;;) { int x, h; unsigned long x2; unsigned long offset = find_next_bit((unsigned long *) &vs->dirty, height * VNC_DIRTY_BPL(vs), y * VNC_DIRTY_BPL(vs)); if (offset == height * VNC_DIRTY_BPL(vs)) { /* no more dirty bits */ break; } y = offset / VNC_DIRTY_BPL(vs); x = offset % VNC_DIRTY_BPL(vs); x2 = find_next_zero_bit((unsigned long *) &vs->dirty[y], VNC_DIRTY_BPL(vs), x); bitmap_clear(vs->dirty[y], x, x2 - x); h = find_and_clear_dirty_height(vs, y, x, x2, height); n += vnc_job_add_rect(job, x * VNC_DIRTY_PIXELS_PER_BIT, y, (x2 - x) * VNC_DIRTY_PIXELS_PER_BIT, h); } vnc_job_push(job); vs->force_update = 0; return n; } if (vs->csock == -1) { vnc_disconnect_finish(vs); } else if (sync) { vnc_jobs_join(vs); } return 0; } | 20,101 |
0 | static int input_init(struct XenDevice *xendev) { struct XenInput *in = container_of(xendev, struct XenInput, c.xendev); if (!in->c.ds) { xen_be_printf(xendev, 1, "ds not set (yet)\n"); return -1; } xenstore_write_be_int(xendev, "feature-abs-pointer", 1); return 0; } | 20,103 |
0 | static int start_auth_vnc(VncState *vs) { make_challenge(vs); /* Send client a 'random' challenge */ vnc_write(vs, vs->challenge, sizeof(vs->challenge)); vnc_flush(vs); vnc_read_when(vs, protocol_client_auth_vnc, sizeof(vs->challenge)); return 0; } | 20,104 |
0 | static void io_region_del(MemoryListener *listener, MemoryRegionSection *section) { isa_unassign_ioport(section->offset_within_address_space, int128_get64(section->size)); } | 20,107 |
0 | static void disas_thumb_insn(CPUState *env, DisasContext *s) { uint32_t val, insn, op, rm, rn, rd, shift, cond; int32_t offset; int i; TCGv tmp; TCGv tmp2; TCGv addr; if (s->condexec_mask) { cond = s->condexec_cond; if (cond != 0x0e) { /* Skip conditional when condition is AL. */ s->condlabel = gen_new_label(); gen_test_cc(cond ^ 1, s->condlabel); s->condjmp = 1; } } insn = lduw_code(s->pc); s->pc += 2; switch (insn >> 12) { case 0: case 1: rd = insn & 7; op = (insn >> 11) & 3; if (op == 3) { /* add/subtract */ rn = (insn >> 3) & 7; tmp = load_reg(s, rn); if (insn & (1 << 10)) { /* immediate */ tmp2 = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); } else { /* reg */ rm = (insn >> 6) & 7; tmp2 = load_reg(s, rm); } if (insn & (1 << 9)) { if (s->condexec_mask) tcg_gen_sub_i32(tmp, tmp, tmp2); else gen_helper_sub_cc(tmp, tmp, tmp2); } else { if (s->condexec_mask) tcg_gen_add_i32(tmp, tmp, tmp2); else gen_helper_add_cc(tmp, tmp, tmp2); } tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); } else { /* shift immediate */ rm = (insn >> 3) & 7; shift = (insn >> 6) & 0x1f; tmp = load_reg(s, rm); gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); if (!s->condexec_mask) gen_logic_CC(tmp); store_reg(s, rd, tmp); } break; case 2: case 3: /* arithmetic large immediate */ op = (insn >> 11) & 3; rd = (insn >> 8) & 0x7; if (op == 0) { /* mov */ tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, insn & 0xff); if (!s->condexec_mask) gen_logic_CC(tmp); store_reg(s, rd, tmp); } else { tmp = load_reg(s, rd); tmp2 = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, insn & 0xff); switch (op) { case 1: /* cmp */ gen_helper_sub_cc(tmp, tmp, tmp2); tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp2); break; case 2: /* add */ if (s->condexec_mask) tcg_gen_add_i32(tmp, tmp, tmp2); else gen_helper_add_cc(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); break; case 3: /* sub */ if (s->condexec_mask) tcg_gen_sub_i32(tmp, tmp, tmp2); else gen_helper_sub_cc(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); break; } } break; case 4: if (insn & (1 << 11)) { rd = (insn >> 8) & 7; /* load pc-relative. Bit 1 of PC is ignored. */ val = s->pc + 2 + ((insn & 0xff) * 4); val &= ~(uint32_t)2; addr = tcg_temp_new_i32(); tcg_gen_movi_i32(addr, val); tmp = gen_ld32(addr, IS_USER(s)); tcg_temp_free_i32(addr); store_reg(s, rd, tmp); break; } if (insn & (1 << 10)) { /* data processing extended or blx */ rd = (insn & 7) | ((insn >> 4) & 8); rm = (insn >> 3) & 0xf; op = (insn >> 8) & 3; switch (op) { case 0: /* add */ tmp = load_reg(s, rd); tmp2 = load_reg(s, rm); tcg_gen_add_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); break; case 1: /* cmp */ tmp = load_reg(s, rd); tmp2 = load_reg(s, rm); gen_helper_sub_cc(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp); break; case 2: /* mov/cpy */ tmp = load_reg(s, rm); store_reg(s, rd, tmp); break; case 3:/* branch [and link] exchange thumb register */ tmp = load_reg(s, rm); if (insn & (1 << 7)) { val = (uint32_t)s->pc | 1; tmp2 = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, val); store_reg(s, 14, tmp2); } gen_bx(s, tmp); break; } break; } /* data processing register */ rd = insn & 7; rm = (insn >> 3) & 7; op = (insn >> 6) & 0xf; if (op == 2 || op == 3 || op == 4 || op == 7) { /* the shift/rotate ops want the operands backwards */ val = rm; rm = rd; rd = val; val = 1; } else { val = 0; } if (op == 9) { /* neg */ tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, 0); } else if (op != 0xf) { /* mvn doesn't read its first operand */ tmp = load_reg(s, rd); } else { TCGV_UNUSED(tmp); } tmp2 = load_reg(s, rm); switch (op) { case 0x0: /* and */ tcg_gen_and_i32(tmp, tmp, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp); break; case 0x1: /* eor */ tcg_gen_xor_i32(tmp, tmp, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp); break; case 0x2: /* lsl */ if (s->condexec_mask) { gen_helper_shl(tmp2, tmp2, tmp); } else { gen_helper_shl_cc(tmp2, tmp2, tmp); gen_logic_CC(tmp2); } break; case 0x3: /* lsr */ if (s->condexec_mask) { gen_helper_shr(tmp2, tmp2, tmp); } else { gen_helper_shr_cc(tmp2, tmp2, tmp); gen_logic_CC(tmp2); } break; case 0x4: /* asr */ if (s->condexec_mask) { gen_helper_sar(tmp2, tmp2, tmp); } else { gen_helper_sar_cc(tmp2, tmp2, tmp); gen_logic_CC(tmp2); } break; case 0x5: /* adc */ if (s->condexec_mask) gen_adc(tmp, tmp2); else gen_helper_adc_cc(tmp, tmp, tmp2); break; case 0x6: /* sbc */ if (s->condexec_mask) gen_sub_carry(tmp, tmp, tmp2); else gen_helper_sbc_cc(tmp, tmp, tmp2); break; case 0x7: /* ror */ if (s->condexec_mask) { tcg_gen_andi_i32(tmp, tmp, 0x1f); tcg_gen_rotr_i32(tmp2, tmp2, tmp); } else { gen_helper_ror_cc(tmp2, tmp2, tmp); gen_logic_CC(tmp2); } break; case 0x8: /* tst */ tcg_gen_and_i32(tmp, tmp, tmp2); gen_logic_CC(tmp); rd = 16; break; case 0x9: /* neg */ if (s->condexec_mask) tcg_gen_neg_i32(tmp, tmp2); else gen_helper_sub_cc(tmp, tmp, tmp2); break; case 0xa: /* cmp */ gen_helper_sub_cc(tmp, tmp, tmp2); rd = 16; break; case 0xb: /* cmn */ gen_helper_add_cc(tmp, tmp, tmp2); rd = 16; break; case 0xc: /* orr */ tcg_gen_or_i32(tmp, tmp, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp); break; case 0xd: /* mul */ tcg_gen_mul_i32(tmp, tmp, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp); break; case 0xe: /* bic */ tcg_gen_andc_i32(tmp, tmp, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp); break; case 0xf: /* mvn */ tcg_gen_not_i32(tmp2, tmp2); if (!s->condexec_mask) gen_logic_CC(tmp2); val = 1; rm = rd; break; } if (rd != 16) { if (val) { store_reg(s, rm, tmp2); if (op != 0xf) tcg_temp_free_i32(tmp); } else { store_reg(s, rd, tmp); tcg_temp_free_i32(tmp2); } } else { tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp2); } break; case 5: /* load/store register offset. */ rd = insn & 7; rn = (insn >> 3) & 7; rm = (insn >> 6) & 7; op = (insn >> 9) & 7; addr = load_reg(s, rn); tmp = load_reg(s, rm); tcg_gen_add_i32(addr, addr, tmp); tcg_temp_free_i32(tmp); if (op < 3) /* store */ tmp = load_reg(s, rd); switch (op) { case 0: /* str */ gen_st32(tmp, addr, IS_USER(s)); break; case 1: /* strh */ gen_st16(tmp, addr, IS_USER(s)); break; case 2: /* strb */ gen_st8(tmp, addr, IS_USER(s)); break; case 3: /* ldrsb */ tmp = gen_ld8s(addr, IS_USER(s)); break; case 4: /* ldr */ tmp = gen_ld32(addr, IS_USER(s)); break; case 5: /* ldrh */ tmp = gen_ld16u(addr, IS_USER(s)); break; case 6: /* ldrb */ tmp = gen_ld8u(addr, IS_USER(s)); break; case 7: /* ldrsh */ tmp = gen_ld16s(addr, IS_USER(s)); break; } if (op >= 3) /* load */ store_reg(s, rd, tmp); tcg_temp_free_i32(addr); break; case 6: /* load/store word immediate offset */ rd = insn & 7; rn = (insn >> 3) & 7; addr = load_reg(s, rn); val = (insn >> 4) & 0x7c; tcg_gen_addi_i32(addr, addr, val); if (insn & (1 << 11)) { /* load */ tmp = gen_ld32(addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); gen_st32(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(addr); break; case 7: /* load/store byte immediate offset */ rd = insn & 7; rn = (insn >> 3) & 7; addr = load_reg(s, rn); val = (insn >> 6) & 0x1f; tcg_gen_addi_i32(addr, addr, val); if (insn & (1 << 11)) { /* load */ tmp = gen_ld8u(addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); gen_st8(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(addr); break; case 8: /* load/store halfword immediate offset */ rd = insn & 7; rn = (insn >> 3) & 7; addr = load_reg(s, rn); val = (insn >> 5) & 0x3e; tcg_gen_addi_i32(addr, addr, val); if (insn & (1 << 11)) { /* load */ tmp = gen_ld16u(addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); gen_st16(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(addr); break; case 9: /* load/store from stack */ rd = (insn >> 8) & 7; addr = load_reg(s, 13); val = (insn & 0xff) * 4; tcg_gen_addi_i32(addr, addr, val); if (insn & (1 << 11)) { /* load */ tmp = gen_ld32(addr, IS_USER(s)); store_reg(s, rd, tmp); } else { /* store */ tmp = load_reg(s, rd); gen_st32(tmp, addr, IS_USER(s)); } tcg_temp_free_i32(addr); break; case 10: /* add to high reg */ rd = (insn >> 8) & 7; if (insn & (1 << 11)) { /* SP */ tmp = load_reg(s, 13); } else { /* PC. bit 1 is ignored. */ tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2); } val = (insn & 0xff) * 4; tcg_gen_addi_i32(tmp, tmp, val); store_reg(s, rd, tmp); break; case 11: /* misc */ op = (insn >> 8) & 0xf; switch (op) { case 0: /* adjust stack pointer */ tmp = load_reg(s, 13); val = (insn & 0x7f) * 4; if (insn & (1 << 7)) val = -(int32_t)val; tcg_gen_addi_i32(tmp, tmp, val); store_reg(s, 13, tmp); break; case 2: /* sign/zero extend. */ ARCH(6); rd = insn & 7; rm = (insn >> 3) & 7; tmp = load_reg(s, rm); switch ((insn >> 6) & 3) { case 0: gen_sxth(tmp); break; case 1: gen_sxtb(tmp); break; case 2: gen_uxth(tmp); break; case 3: gen_uxtb(tmp); break; } store_reg(s, rd, tmp); break; case 4: case 5: case 0xc: case 0xd: /* push/pop */ addr = load_reg(s, 13); if (insn & (1 << 8)) offset = 4; else offset = 0; for (i = 0; i < 8; i++) { if (insn & (1 << i)) offset += 4; } if ((insn & (1 << 11)) == 0) { tcg_gen_addi_i32(addr, addr, -offset); } for (i = 0; i < 8; i++) { if (insn & (1 << i)) { if (insn & (1 << 11)) { /* pop */ tmp = gen_ld32(addr, IS_USER(s)); store_reg(s, i, tmp); } else { /* push */ tmp = load_reg(s, i); gen_st32(tmp, addr, IS_USER(s)); } /* advance to the next address. */ tcg_gen_addi_i32(addr, addr, 4); } } TCGV_UNUSED(tmp); if (insn & (1 << 8)) { if (insn & (1 << 11)) { /* pop pc */ tmp = gen_ld32(addr, IS_USER(s)); /* don't set the pc until the rest of the instruction has completed */ } else { /* push lr */ tmp = load_reg(s, 14); gen_st32(tmp, addr, IS_USER(s)); } tcg_gen_addi_i32(addr, addr, 4); } if ((insn & (1 << 11)) == 0) { tcg_gen_addi_i32(addr, addr, -offset); } /* write back the new stack pointer */ store_reg(s, 13, addr); /* set the new PC value */ if ((insn & 0x0900) == 0x0900) gen_bx(s, tmp); break; case 1: case 3: case 9: case 11: /* czb */ rm = insn & 7; tmp = load_reg(s, rm); s->condlabel = gen_new_label(); s->condjmp = 1; if (insn & (1 << 11)) tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); else tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); tcg_temp_free_i32(tmp); offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; val = (uint32_t)s->pc + 2; val += offset; gen_jmp(s, val); break; case 15: /* IT, nop-hint. */ if ((insn & 0xf) == 0) { gen_nop_hint(s, (insn >> 4) & 0xf); break; } /* If Then. */ s->condexec_cond = (insn >> 4) & 0xe; s->condexec_mask = insn & 0x1f; /* No actual code generated for this insn, just setup state. */ break; case 0xe: /* bkpt */ gen_exception_insn(s, 2, EXCP_BKPT); break; case 0xa: /* rev */ ARCH(6); rn = (insn >> 3) & 0x7; rd = insn & 0x7; tmp = load_reg(s, rn); switch ((insn >> 6) & 3) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; case 1: gen_rev16(tmp); break; case 3: gen_revsh(tmp); break; default: goto illegal_op; } store_reg(s, rd, tmp); break; case 6: /* cps */ ARCH(6); if (IS_USER(s)) break; if (IS_M(env)) { tmp = tcg_const_i32((insn & (1 << 4)) != 0); /* PRIMASK */ if (insn & 1) { addr = tcg_const_i32(16); gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); } /* FAULTMASK */ if (insn & 2) { addr = tcg_const_i32(17); gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); } tcg_temp_free_i32(tmp); gen_lookup_tb(s); } else { if (insn & (1 << 4)) shift = CPSR_A | CPSR_I | CPSR_F; else shift = 0; gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); } break; default: goto undef; } break; case 12: /* load/store multiple */ rn = (insn >> 8) & 0x7; addr = load_reg(s, rn); for (i = 0; i < 8; i++) { if (insn & (1 << i)) { if (insn & (1 << 11)) { /* load */ tmp = gen_ld32(addr, IS_USER(s)); store_reg(s, i, tmp); } else { /* store */ tmp = load_reg(s, i); gen_st32(tmp, addr, IS_USER(s)); } /* advance to the next address */ tcg_gen_addi_i32(addr, addr, 4); } } /* Base register writeback. */ if ((insn & (1 << rn)) == 0) { store_reg(s, rn, addr); } else { tcg_temp_free_i32(addr); } break; case 13: /* conditional branch or swi */ cond = (insn >> 8) & 0xf; if (cond == 0xe) goto undef; if (cond == 0xf) { /* swi */ gen_set_pc_im(s->pc); s->is_jmp = DISAS_SWI; break; } /* generate a conditional jump to next instruction */ s->condlabel = gen_new_label(); gen_test_cc(cond ^ 1, s->condlabel); s->condjmp = 1; /* jump to the offset */ val = (uint32_t)s->pc + 2; offset = ((int32_t)insn << 24) >> 24; val += offset << 1; gen_jmp(s, val); break; case 14: if (insn & (1 << 11)) { if (disas_thumb2_insn(env, s, insn)) goto undef32; break; } /* unconditional branch */ val = (uint32_t)s->pc; offset = ((int32_t)insn << 21) >> 21; val += (offset << 1) + 2; gen_jmp(s, val); break; case 15: if (disas_thumb2_insn(env, s, insn)) goto undef32; break; } return; undef32: gen_exception_insn(s, 4, EXCP_UDEF); return; illegal_op: undef: gen_exception_insn(s, 2, EXCP_UDEF); } | 20,108 |
1 | static int ape_decode_frame(AVCodecContext *avctx, void *data, int *data_size, AVPacket *avpkt) { const uint8_t *buf = avpkt->data; int buf_size = avpkt->size; APEContext *s = avctx->priv_data; int16_t *samples = data; int nblocks; int i, n; int blockstodecode; int bytes_used; /* should not happen but who knows */ if (BLOCKS_PER_LOOP * 2 * avctx->channels > *data_size) { av_log (avctx, AV_LOG_ERROR, "Output buffer is too small.\n"); return AVERROR(EINVAL); } if(!s->samples){ void *tmp_data = av_realloc(s->data, (buf_size + 3) & ~3); if (!tmp_data) return AVERROR(ENOMEM); s->data = tmp_data; s->dsp.bswap_buf((uint32_t*)s->data, (const uint32_t*)buf, buf_size >> 2); s->ptr = s->last_ptr = s->data; s->data_end = s->data + buf_size; nblocks = s->samples = bytestream_get_be32(&s->ptr); n = bytestream_get_be32(&s->ptr); if(n < 0 || n > 3){ av_log(avctx, AV_LOG_ERROR, "Incorrect offset passed\n"); s->data = NULL; return AVERROR_INVALIDDATA; } s->ptr += n; s->currentframeblocks = nblocks; buf += 4; if (s->samples <= 0) { *data_size = 0; return buf_size; } memset(s->decoded0, 0, sizeof(s->decoded0)); memset(s->decoded1, 0, sizeof(s->decoded1)); /* Initialize the frame decoder */ init_frame_decoder(s); } if (!s->data) { *data_size = 0; return buf_size; } nblocks = s->samples; blockstodecode = FFMIN(BLOCKS_PER_LOOP, nblocks); s->error=0; if ((s->channels == 1) || (s->frameflags & APE_FRAMECODE_PSEUDO_STEREO)) ape_unpack_mono(s, blockstodecode); else ape_unpack_stereo(s, blockstodecode); emms_c(); if(s->error || s->ptr > s->data_end){ s->samples=0; av_log(avctx, AV_LOG_ERROR, "Error decoding frame\n"); return AVERROR_INVALIDDATA; } for (i = 0; i < blockstodecode; i++) { *samples++ = s->decoded0[i]; if(s->channels == 2) *samples++ = s->decoded1[i]; } s->samples -= blockstodecode; *data_size = blockstodecode * 2 * s->channels; bytes_used = s->samples ? s->ptr - s->last_ptr : buf_size; s->last_ptr = s->ptr; return bytes_used; } | 20,111 |
1 | static void aarch64_numa_cpu(const void *data) { char *cli; QDict *resp; QList *cpus; const QObject *e; cli = make_cli(data, "-smp 2 " "-numa node,nodeid=0 -numa node,nodeid=1 " "-numa cpu,node-id=1,thread-id=0 " "-numa cpu,node-id=0,thread-id=1"); qtest_start(cli); cpus = get_cpus(&resp); g_assert(cpus); while ((e = qlist_pop(cpus))) { QDict *cpu, *props; int64_t thread, node; cpu = qobject_to_qdict(e); g_assert(qdict_haskey(cpu, "props")); props = qdict_get_qdict(cpu, "props"); g_assert(qdict_haskey(props, "node-id")); node = qdict_get_int(props, "node-id"); g_assert(qdict_haskey(props, "thread-id")); thread = qdict_get_int(props, "thread-id"); if (thread == 0) { g_assert_cmpint(node, ==, 1); } else if (thread == 1) { g_assert_cmpint(node, ==, 0); } else { g_assert(false); } } QDECREF(resp); qtest_end(); g_free(cli); } | 20,112 |
0 | static int unpack_vlcs(Vp3DecodeContext *s, GetBitContext *gb, VLC *table, int coeff_index, int first_fragment, int last_fragment, int eob_run) { int i; int token; int zero_run = 0; DCTELEM coeff = 0; Vp3Fragment *fragment; uint8_t *perm= s->scantable.permutated; int bits_to_get; if ((first_fragment >= s->fragment_count) || (last_fragment >= s->fragment_count)) { av_log(s->avctx, AV_LOG_ERROR, " vp3:unpack_vlcs(): bad fragment number (%d -> %d ?)\n", first_fragment, last_fragment); return 0; } for (i = first_fragment; i <= last_fragment; i++) { int fragment_num = s->coded_fragment_list[i]; if (s->coeff_counts[fragment_num] > coeff_index) continue; fragment = &s->all_fragments[fragment_num]; if (!eob_run) { /* decode a VLC into a token */ token = get_vlc2(gb, table->table, 5, 3); /* use the token to get a zero run, a coefficient, and an eob run */ if (token <= 6) { eob_run = eob_run_base[token]; if (eob_run_get_bits[token]) eob_run += get_bits(gb, eob_run_get_bits[token]); coeff = zero_run = 0; } else { bits_to_get = coeff_get_bits[token]; if (!bits_to_get) coeff = coeff_tables[token][0]; else coeff = coeff_tables[token][get_bits(gb, bits_to_get)]; zero_run = zero_run_base[token]; if (zero_run_get_bits[token]) zero_run += get_bits(gb, zero_run_get_bits[token]); } } if (!eob_run) { s->coeff_counts[fragment_num] += zero_run; if (s->coeff_counts[fragment_num] < 64){ fragment->next_coeff->coeff= coeff; fragment->next_coeff->index= perm[s->coeff_counts[fragment_num]++]; //FIXME perm here already? fragment->next_coeff->next= s->next_coeff; s->next_coeff->next=NULL; fragment->next_coeff= s->next_coeff++; } } else { s->coeff_counts[fragment_num] |= 128; eob_run--; } } return eob_run; } | 20,113 |
1 | static inline void vmxnet3_ring_init(Vmxnet3Ring *ring, hwaddr pa, size_t size, size_t cell_size, bool zero_region) { ring->pa = pa; ring->size = size; ring->cell_size = cell_size; ring->gen = VMXNET3_INIT_GEN; ring->next = 0; if (zero_region) { vmw_shmem_set(pa, 0, size * cell_size); } } | 20,114 |
1 | uint32_t virtio_config_readw(VirtIODevice *vdev, uint32_t addr) { VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); uint16_t val; k->get_config(vdev, vdev->config); if (addr > (vdev->config_len - sizeof(val))) return (uint32_t)-1; val = lduw_p(vdev->config + addr); return val; } | 20,115 |
1 | static int get_qcx(Jpeg2000DecoderContext *s, int n, Jpeg2000QuantStyle *q) { int i, x; if (s->buf_end - s->buf < 1) return AVERROR_INVALIDDATA; x = bytestream_get_byte(&s->buf); // Sqcd q->nguardbits = x >> 5; q->quantsty = x & 0x1f; if (q->quantsty == JPEG2000_QSTY_NONE) { n -= 3; if (s->buf_end - s->buf < n) return AVERROR_INVALIDDATA; for (i = 0; i < n; i++) q->expn[i] = bytestream_get_byte(&s->buf) >> 3; } else if (q->quantsty == JPEG2000_QSTY_SI) { if (s->buf_end - s->buf < 2) return AVERROR_INVALIDDATA; x = bytestream_get_be16(&s->buf); q->expn[0] = x >> 11; q->mant[0] = x & 0x7ff; for (i = 1; i < JPEG2000_MAX_DECLEVELS * 3; i++) { int curexpn = FFMAX(0, q->expn[0] - (i - 1) / 3); q->expn[i] = curexpn; q->mant[i] = q->mant[0]; } } else { n = (n - 3) >> 1; if (s->buf_end - s->buf < n) return AVERROR_INVALIDDATA; for (i = 0; i < n; i++) { x = bytestream_get_be16(&s->buf); q->expn[i] = x >> 11; q->mant[i] = x & 0x7ff; } } return 0; } | 20,116 |
1 | static void qemu_kvm_eat_signals(CPUState *env) { struct timespec ts = { 0, 0 }; siginfo_t siginfo; sigset_t waitset; sigset_t chkset; int r; sigemptyset(&waitset); sigaddset(&waitset, SIG_IPI); sigaddset(&waitset, SIGBUS); do { r = sigtimedwait(&waitset, &siginfo, &ts); if (r == -1 && !(errno == EAGAIN || errno == EINTR)) { perror("sigtimedwait"); exit(1); } switch (r) { case SIGBUS: if (kvm_on_sigbus_vcpu(env, siginfo.si_code, siginfo.si_addr)) { sigbus_reraise(); } break; default: break; } r = sigpending(&chkset); if (r == -1) { perror("sigpending"); exit(1); } } while (sigismember(&chkset, SIG_IPI) || sigismember(&chkset, SIGBUS)); #ifndef CONFIG_IOTHREAD if (sigismember(&chkset, SIGIO) || sigismember(&chkset, SIGALRM)) { qemu_notify_event(); } #endif } | 20,117 |
0 | static int mov_read_default(MOVContext *c, AVIOContext *pb, MOVAtom atom) { int64_t total_size = 0; MOVAtom a; int i; if (atom.size < 0) atom.size = INT64_MAX; while (total_size + 8 <= atom.size && !url_feof(pb)) { int (*parse)(MOVContext*, AVIOContext*, MOVAtom) = NULL; a.size = atom.size; a.type=0; if (atom.size >= 8) { a.size = avio_rb32(pb); a.type = avio_rl32(pb); total_size += 8; if (a.size == 1) { /* 64 bit extended size */ a.size = avio_rb64(pb) - 8; total_size += 8; } } av_dlog(c->fc, "type: %08x '%.4s' parent:'%.4s' sz: %"PRId64" %"PRId64" %"PRId64"\n", a.type, (char*)&a.type, (char*)&atom.type, a.size, total_size, atom.size); if (a.size == 0) { a.size = atom.size - total_size + 8; if (a.size <= 8) break; } a.size -= 8; if (a.size < 0) break; a.size = FFMIN(a.size, atom.size - total_size); for (i = 0; mov_default_parse_table[i].type; i++) if (mov_default_parse_table[i].type == a.type) { parse = mov_default_parse_table[i].parse; break; } // container is user data if (!parse && (atom.type == MKTAG('u','d','t','a') || atom.type == MKTAG('i','l','s','t'))) parse = mov_read_udta_string; if (!parse) { /* skip leaf atoms data */ avio_skip(pb, a.size); } else { int64_t start_pos = avio_tell(pb); int64_t left; int err = parse(c, pb, a); if (err < 0) return err; if (c->found_moov && c->found_mdat && (!pb->seekable || start_pos + a.size == avio_size(pb))) return 0; left = a.size - avio_tell(pb) + start_pos; if (left > 0) /* skip garbage at atom end */ avio_skip(pb, left); } total_size += a.size; } if (total_size < atom.size && atom.size < 0x7ffff) avio_skip(pb, atom.size - total_size); return 0; } | 20,118 |
1 | int check_intra_pred8x8_mode_emuedge(int mode, int mb_x, int mb_y) { switch (mode) { case DC_PRED8x8: return check_dc_pred8x8_mode(mode, mb_x, mb_y); case VERT_PRED8x8: return !mb_y ? DC_127_PRED8x8 : mode; case HOR_PRED8x8: return !mb_x ? DC_129_PRED8x8 : mode; case PLANE_PRED8x8: /* TM */ return check_tm_pred8x8_mode(mode, mb_x, mb_y); } return mode; } | 20,119 |
1 | static int jpeg_write_trailer(AVFormatContext *s1) { JpegContext *s = s1->priv_data; av_free(s); return 0; } | 20,120 |
0 | static int ljpeg_decode_yuv_scan(MJpegDecodeContext *s, int predictor, int point_transform){ int i, mb_x, mb_y; const int nb_components=3; for(mb_y = 0; mb_y < s->mb_height; mb_y++) { for(mb_x = 0; mb_x < s->mb_width; mb_x++) { if (s->restart_interval && !s->restart_count) s->restart_count = s->restart_interval; if(mb_x==0 || mb_y==0 || s->interlaced){ for(i=0;i<nb_components;i++) { uint8_t *ptr; int n, h, v, x, y, c, j, linesize; n = s->nb_blocks[i]; c = s->comp_index[i]; h = s->h_scount[i]; v = s->v_scount[i]; x = 0; y = 0; linesize= s->linesize[c]; for(j=0; j<n; j++) { int pred; ptr = s->picture.data[c] + (linesize * (v * mb_y + y)) + (h * mb_x + x); //FIXME optimize this crap if(y==0 && mb_y==0){ if(x==0 && mb_x==0){ pred= 128 << point_transform; }else{ pred= ptr[-1]; } }else{ if(x==0 && mb_x==0){ pred= ptr[-linesize]; }else{ PREDICT(pred, ptr[-linesize-1], ptr[-linesize], ptr[-1], predictor); } } if (s->interlaced && s->bottom_field) ptr += linesize >> 1; *ptr= pred + (mjpeg_decode_dc(s, s->dc_index[i]) << point_transform); if (++x == h) { x = 0; y++; } } } }else{ for(i=0;i<nb_components;i++) { uint8_t *ptr; int n, h, v, x, y, c, j, linesize; n = s->nb_blocks[i]; c = s->comp_index[i]; h = s->h_scount[i]; v = s->v_scount[i]; x = 0; y = 0; linesize= s->linesize[c]; for(j=0; j<n; j++) { int pred; ptr = s->picture.data[c] + (linesize * (v * mb_y + y)) + (h * mb_x + x); //FIXME optimize this crap PREDICT(pred, ptr[-linesize-1], ptr[-linesize], ptr[-1], predictor); *ptr= pred + (mjpeg_decode_dc(s, s->dc_index[i]) << point_transform); if (++x == h) { x = 0; y++; } } } } if (s->restart_interval && !--s->restart_count) { align_get_bits(&s->gb); skip_bits(&s->gb, 16); /* skip RSTn */ } } } return 0; } | 20,121 |
0 | static void filter_mb_mbaff_edgecv( H264Context *h, uint8_t *pix, int stride, const int16_t bS[7], int bsi, int qp ) { const int qp_bd_offset = 6 * (h->sps.bit_depth_luma - 8); int index_a = qp - qp_bd_offset + h->slice_alpha_c0_offset; int alpha = alpha_table[index_a]; int beta = beta_table[qp - qp_bd_offset + h->slice_beta_offset]; if (alpha ==0 || beta == 0) return; if( bS[0] < 4 ) { int8_t tc[4]; tc[0] = tc0_table[index_a][bS[0*bsi]] + 1; tc[1] = tc0_table[index_a][bS[1*bsi]] + 1; tc[2] = tc0_table[index_a][bS[2*bsi]] + 1; tc[3] = tc0_table[index_a][bS[3*bsi]] + 1; h->h264dsp.h264_h_loop_filter_chroma_mbaff(pix, stride, alpha, beta, tc); } else { h->h264dsp.h264_h_loop_filter_chroma_mbaff_intra(pix, stride, alpha, beta); } } | 20,122 |
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