ID
int64 383
2.08k
| Split
stringclasses 1
value | Domain
stringclasses 4
values | SubDomain
stringclasses 24
values | Format
stringclasses 1
value | Tag
stringclasses 2
values | Language
stringclasses 1
value | Question
stringlengths 28
336
| Answer
stringclasses 2
values | Explanation
stringlengths 29
771
⌀ |
|---|---|---|---|---|---|---|---|---|---|
895 |
Test
|
Computer Organization
|
Overview
|
Assertion
|
Knowledge
|
English
|
The word length of storage refers to the combination of binary codes stored in a single storage cell.
|
False
| null |
896 |
Test
|
Computer Organization
|
Overview
|
Assertion
|
Knowledge
|
English
|
A 32-bit microcomputer refers to a computer whose CPU has 32 registers.
|
False
| null |
897 |
Test
|
Computer Organization
|
Overview
|
Assertion
|
Reasoning
|
English
|
The current important technological approach to designing high-performance computers is the adoption of parallel processing technology.
|
True
|
Increasing the CPU clock speed and expanding the main memory capacity have limited effects on performance improvement. Adopting parallel computing techniques is an important approach to achieving high-performance computing, and modern supercomputers all utilize multiple processors to enhance parallel processing capabilities.
|
898 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
The decimal number corresponding to the 8421 code 1001 is 9.
|
True
| null |
899 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
In an 8-bit machine using two's complement representation, the smallest negative number is -128.
|
True
| null |
900 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
In floating-point arithmetic, normalization of the mantissa refers to ensuring that the first digit of the mantissa is always 1.
|
True
| null |
901 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
In fixed-point number representation, when using the ones' complement notation, negative numbers are represented with the sign bit set to 1, and the magnitude part remains unchanged.
|
False
| null |
902 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
An 8-bit machine number using two's complement representation can represent the smallest negative integer as -128.
|
True
| null |
903 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
In the 8421 code, when the sum of two numbers is 11010, the corrected result after adjustment is 11000.
|
False
| null |
904 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
For an 8-bit machine number using ones' complement representation, the maximum positive number it can represent is 127.
|
True
| null |
905 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
In the 8421 code, the correct representation of the number 0 is 1.
|
False
| null |
906 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
In the IEEE754 standard, the mantissa part of a normalized long floating-point number is represented using 23 bits of binary.
|
False
| null |
907 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Knowledge
|
English
|
The representation range of a 16-bit unsigned binary number is 0~65535.
|
True
| null |
908 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Reasoning
|
English
|
If the two's complement is 1.1101010, then the true form is 1.0010110.
|
True
|
If X is a negative number, the rule for converting its complement to true form is "keep the sign bit unchanged, invert the value bits, and add 1 to the last bit," that is, [X]_true = 0010101 + 1 = 0010110.
|
909 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Reasoning
|
English
|
The two's complement and offset binary representations of zero are the same.
|
False
|
Taking a machine word length of 5 bits as an example, [0] in two's complement is 00000, [0] in excess notation is 2^4+0=10000, [0] is not equal to [0] in excess notation, indicating they are different. However, the representation in either two's complement or excess notation is unique.
|
910 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Reasoning
|
English
|
If the content of the register is 10000000, and it equals -0, then it is in true form (sign-magnitude representation).
|
True
|
A value equal to -0 indicates that it can only be in true form or ones' complement form.
|
911 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Reasoning
|
English
|
The purpose of using a carry-lookahead adder is to ensure the reliability of the adder.
|
False
|
Parallel carry can improve the operational speed of adders.
|
912 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Reasoning
|
English
|
If a double sign bit is used, the characteristic of overflow when two positive numbers are added is that the double sign bit is 01.
|
True
|
When using double sign bits, the first sign bit represents the sign of the final result, and the second sign bit indicates whether the operation result has overflowed. If the second bit is the same as the first sign bit, there is no overflow; if different, there is overflow. If a positive overflow occurs, the double sign bits are 01; if a negative overflow occurs, the double sign bits are 10.
|
913 |
Test
|
Computer Organization
|
Data Representation and Operation
|
Assertion
|
Reasoning
|
English
|
The value of the number 45100000H represented in the single-precision floating-point format of the IEEE 754 standard is (+1.125)_{10}x2^{11}.
|
True
|
The binary representation is 0100 0101 0001 0000 0000 0000 0000 0000, where the first bit is the sign bit, with 0 indicating a positive number. The following 8 bits (float type) 1000 1010 represent the exponent in excess-127 notation, so subtracting 0111 1111 yields the decimal number 11. In the IEEE 754 standard for single-precision floating-point numbers, there is an implied 1 in the mantissa when the exponent is non-zero. Therefore, the mantissa is (1.0010){B} = (1.125){D}, making the value of the number (+1.125)_{10}x2^11.
|
914 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
Cache and main memory can directly exchange information with the CPU, while auxiliary memory exchanges information with the CPU through the main memory.
|
True
| null |
915 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
In the storage system, the characteristic of data movement between Cache and main memory is that it requires manual data manipulation by the application programmer.
|
False
| null |
916 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
Magnetic core memory belongs to semiconductor memory.
|
False
| null |
917 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
The data movement between main memory and Cache is automatically handled by hardware and is transparent to all programmers.
|
True
| null |
918 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
The address structure of the fully associative mapping method for Cache includes the main memory block tag and the Cache block address (line number).
|
False
| null |
919 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
In the classification of memory, serial access memory usually refers to sequential access memory.
|
True
| null |
920 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
In the hierarchical structure of memory, the primary purpose of Cache is to store persistent data.
|
False
| null |
921 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
The main characteristic of Mask ROM (MROM) is that once written, its content cannot be altered by anyone.
|
True
| null |
922 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
The function of the chip select line in semiconductor memory is to convert the input address into the memory address.
|
False
| null |
923 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
In the memory hierarchy architecture, the arrangement of memory from fastest to slowest is registers, Cache, main memory, and auxiliary memory.
|
True
| null |
924 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
SRAM is faster but has a lower integration density, whereas DRAM is slightly slower but has a higher integration density.
|
True
| null |
925 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
USB flash drives belong to the type of primary storage devices.
|
False
| null |
926 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
A certain computer system has its operating system stored on the hard drive, and its memory should use ROM.
|
False
| null |
927 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
EPROM is rewritable, but cannot be used as random access memory (RAM).
|
True
| null |
928 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
Four 16Kx8 bit memory chips can be configured to form an 8Kx16 bit memory capacity.
|
False
| null |
929 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
The address sent by the CPU when accessing the three-level storage hierarchy composed of cache, main memory, and hard disk is the physical address of the main memory.
|
True
| null |
930 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Knowledge
|
English
|
The primary purpose of adopting virtual memory is to increase the access speed of the main memory.
|
False
| null |
931 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
Multi-level storage systems are designed to reduce storage costs.
|
True
|
The data movement between main memory and auxiliary memory in virtual memory is transparent to application-level programmers. The CPU can directly exchange information with the Cache, but exchanging information with the main memory may also require going through the Cache.
|
932 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
The characteristic of dynamic semiconductor memory is that the content of the memory changes during operation, and a complete refresh process requires occupying two memory cycles.
|
False
|
Dynamic Random Access Memory (DRAM) utilizes the characteristic of capacitors to store charge for recording information. Due to the discharge of capacitors, it is necessary to recharge them before the charge is lost, which is known as refreshing. The method involves rewriting the original content at regular intervals, so the reading mentioned here does not involve transferring information into the CPU or from the CPU to the main memory. It simply reads the information out, passes it through a refresh amplifier, and then stores it back into the memory cell. The refresh amplifier is integrated on the RAM chip. Therefore, only one memory access occurs, which occupies a single access cycle. Statements II and IV are correct, while statements I and III are incorrect.
|
933 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
The main memory of the machine requires up to 64 chips of 512Kx8 bit RAM.
|
False
|
The total capacity of the main memory is 512Kx8 bits = 4M bits, and the number of required memory chips is (4M)/(512K) = 128 chips.
|
934 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
To constitute a memory address from 90000H to CFFFFH with a 16Kx8 bit memory, at least 16 chips are required.
|
True
|
The address range is CFFFFH - 90000H + 1 = 40000H, which requires 16 pieces of 16Kx8 bit memory chips.
|
935 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
When the main memory capacity is 4096 times that of the Cache, the Cache is divided into 64 blocks, and the address uses direct mapping, the size of the address mapping table should be 64x13bit.
|
True
|
In direct mapping mode, each row of the tag array stores one tag entry, with the main memory tag entry being 12 bits and requiring 64 rows.
|
936 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
According to the problem description, the logical space consists of 8 pages, with each page being 1024 bytes, thus the logical address is composed of 13 valid bits. The physical storage area has 32 blocks, so the physical address is composed of at least 15 bits.
|
True
|
The logical address is 13 bits in total, and the physical address is at least 15 bits.
|
937 |
Test
|
Computer Organization
|
Storage System
|
Assertion
|
Reasoning
|
English
|
To ensure that the virtual memory system functions effectively as intended, the characteristic that the programs being run should have is that their size should not be smaller than the actual memory capacity.
|
False
|
A virtual storage system (or virtual memory) allows a computer to run programs that are larger than its actual physical memory. Virtual memory achieves this by dividing the program into smaller blocks and dynamically swapping these blocks between physical memory and storage devices (such as hard drives) as needed. Therefore, one of the main advantages of a virtual storage system is that it allows programs to run even if their size exceeds the capacity of the physical memory.
|
938 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Knowledge
|
English
|
In three-address instructions, the result of the operation is typically stored at the address of the first operand.
|
False
| null |
939 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Knowledge
|
English
|
One characteristic of the CISC architecture is that all instructions are completed within a single cycle.
|
False
| null |
940 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Knowledge
|
English
|
The characteristic of the instruction set in CISC architecture is that the instruction word length is fixed.
|
False
| null |
941 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Knowledge
|
English
|
The RISC architecture optimizes the performance efficiency of the code generated by the compiler.
|
True
| null |
942 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Knowledge
|
English
|
In CISC architecture, there are usually no general-purpose registers.
|
False
| null |
943 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Knowledge
|
English
|
Assuming that the instruction address code specifies the effective address of the operand, then the instruction uses direct addressing.
|
True
| null |
944 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Reasoning
|
English
|
The instruction set is the complete set of instructions that a machine's hardware can execute.
|
False
|
The instruction set is the language system of computer hardware and is related to machine language.
|
945 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Reasoning
|
English
|
In the instruction format, the purpose of adopting an extended opcode design is to increase the addressing space while keeping the instruction word length unchanged.
|
False
|
The extension of the operation code does not change the length of the instruction; instead, it increases the length of the operation code as the address code decreases.
|
946 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Reasoning
|
English
|
The effective address EA of the operand in indexed indirect addressing mode is (X)+(A).
|
False
|
The effective address in indexed addressing is (X) + A, followed by indirect addressing, which means the content retrieved from (X) + A is used as the actual address EA, that is, EA=((X)+A). The content of the register added to the instruction address code yields the address code of the operand.
|
947 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Reasoning
|
English
|
There are two types of instruction addressing modes: sequential and jump. The use of jump addressing mode can achieve program relocation.
|
False
|
Jump addressing is achieved through branch instructions (such as relative addressing), which can be used to implement conditional or unconditional branching in a program.
|
948 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Reasoning
|
English
|
Privileged instructions are typically used only for implementing system software and are generally not made available to users.
|
True
|
Privileged instructions are typically used only for implementing system software and are generally not available to users.
|
949 |
Test
|
Computer Organization
|
Instruction System
|
Assertion
|
Reasoning
|
English
|
After adopting RISC technology, the computer architecture has returned to its early state.
|
False
|
RISC selects some commonly used register-based instructions, not for compatibility with CISC; RISC cannot be compatible with CISC, so A is incorrect. RISC represents a change in CPU architecture that generally does not affect the overall structure of the computer, and even CPUs that utilize RISC technology cannot have an architecture as simple as in the early days, making B incorrect. RISC instructions are simple in functionality, and complex instructions are achieved through the combination of simple ones, which makes C incorrect; however, the main goal of RISC to reduce the number of instructions is correct.
|
950 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
Control hazards (control conflicts) are typically caused by the previous instruction not having completed execution.
|
False
| null |
951 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
In the instruction pipeline, the execution method where the execution stage of one instruction and the fetch stage of the next instruction occur simultaneously is called single-level overlap execution.
|
True
| null |
952 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
Memory, input devices, and output devices receive address information through the control bus within the CPU's control unit architecture.
|
False
| null |
953 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The main characteristic of a hard-wired controller is that it is composed of complex combinational logic gate circuits and some flip-flops.
|
True
| null |
954 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
In the CPU, the main function of the Instruction Register (IR) is to store the instruction that is currently being executed.
|
True
| null |
955 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The fundamental concept of microprogramming is to write each machine instruction as a microprogram.
|
True
| null |
956 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
During the instruction execution process in the CPU, the main task of the indirect addressing cycle is to fetch the effective address of the operand.
|
True
| null |
957 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The Program Counter (PC) is part of the controller.
|
True
| null |
958 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The number of bits in the program counter depends on the instruction word length.
|
False
| null |
959 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The general-purpose registers in the CPU can hold data and addresses, and can also substitute for the instruction register.
|
False
| null |
960 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The Program Status Word (PSW) register is a component in computer systems that represents the state of the program and the machine's operational status.
|
True
| null |
961 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
At the end of the indirect cycle, the content in the CPU's internal register MDR is the instruction.
|
False
| null |
962 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The minimum working time cycle of a computer is the clock cycle.
|
True
| null |
963 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
During the cycle of an unconditional jump instruction, the value of the Program Counter (PC) was modified once.
|
False
| null |
964 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
Due to the fast internal operations of the CPU and the longer time it takes for the CPU to access memory, the machine cycle is usually determined by the memory access cycle.
|
True
| null |
965 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The data path can distinguish whether the contents stored in the memory unit are instructions or data.
|
False
| null |
966 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
The fetch instruction operation is an inherent function of the controller and does not need to be performed under the control of an operation code.
|
True
| null |
967 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Knowledge
|
English
|
In a microprogrammed controller, a control signal sent from the control unit to the execution unit is called a microinstruction.
|
False
| null |
968 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Reasoning
|
English
|
Compared to the data path that uses the CPU internal bus, the data path that does not use the CPU internal bus has more severe data contention issues.
|
False
|
Characteristics of the data path using the CPU internal bus method: simple structure, easy to implement, lower performance, and more conflicts; Characteristics of the data path not using the CPU internal bus method: complex structure, large hardware volume, difficult to implement, high performance, and virtually no data conflicts.
|
969 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Reasoning
|
English
|
The speedup of this pipeline is 3.4, where the instructions are completed by three subcomponents: fetch, decode, and execute, each taking time t, and it uses a conventional scalar single pipeline processor to execute 8 instructions consecutively.
|
False
|
When using a pipeline, the first instruction is completed in 3t, and thereafter an instruction is completed after each interval, so the total time required is 3t + (8 - 1)t = 10t; without using a pipeline, completing 8 instructions in total requires 8 * 3t = 24t, thus the speedup ratio of the pipeline = 24t / 10t = 2.4.
|
970 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Reasoning
|
English
|
Inserting NOPs (No Operation) into branch instructions can avoid control hazards.
|
False
|
The use of forwarding (bypass) technology can resolve data hazards, not control hazards.
|
971 |
Test
|
Computer Organization
|
Central Processing Unit
|
Assertion
|
Reasoning
|
English
|
The cores of a multi-core CPU are completely symmetrical, each possessing its own Cache.
|
False
|
Multi-core CPUs can have independent caches for each core, statement C is correct. Any program can run on multiple cores simultaneously, but it requires the program to support multi-threading and concurrency to take advantage of multi-core processing, statement B is incorrect. Multitasking operating systems can run not only on multi-core CPUs but also on single-core CPUs, statement D is incorrect.
|
972 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
USB is a bus standard for connecting external devices, featuring plug-and-play and hot-swapping capabilities.
|
True
| null |
973 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
SATA is a serial hardware drive interface based on industry standards, used for hard disk interface specifications.
|
True
| null |
974 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
The independent request method is a type of bus arbitration that does not require a central arbitrator; each potential master module has its own arbitration number and arbitrator.
|
False
| null |
975 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
The EISA bus is one of the earliest system bus standards for microcomputers, used in IBM's AT machines, and is fully compatible with ISA.
|
True
| null |
976 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
SATA is a bus standard used for information transfer between computer systems or between a computer system and other systems (such as remote communication devices, test equipment).
|
False
| null |
977 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
SCSI is a high-performance 32-bit or 64-bit bus standard used for connecting highly integrated peripherals, expansion boards, and processor/memory systems.
|
False
| null |
978 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
The data bus is a bus standard used for the common connection lines that link the internal registers of a computer with each other and with the ALU (Arithmetic Logic Unit).
|
True
| null |
979 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
In computer systems, the address bus is used to transmit the main memory address information, indicating the address of the main memory cell or I/O interface where the source data or destination data on the data bus is located.
|
True
| null |
980 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
The function of the address lines in the system bus is to select the device for information transmission.
|
False
| null |
981 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Knowledge
|
English
|
Time-division multiplexing is a method where different signals are transmitted in sequence over the same signal line.
|
False
| null |
982 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Reasoning
|
English
|
In a 32-bit bus system with a clock frequency of 500MHz, it takes 5 clock cycles to transfer a 32-bit word, thus the data transfer rate of this bus is 800MB/s.
|
False
|
Bus bandwidth = Bus width X Bus frequency, resulting in a data transfer rate of 400MB/s.
|
983 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Reasoning
|
English
|
The signals completely transmitted on the control bus in a microcomputer include the address codes of memory and IO devices, the timing signals and control signals for all memory and I/O devices, as well as the response signals from I/O devices and memory.
|
False
|
The signals transmitted on the control bus include timing signals and response signals from I/O devices and memory.
|
984 |
Test
|
Computer Organization
|
Bus
|
Assertion
|
Reasoning
|
English
|
Synchronous communication has a higher transmission rate than asynchronous communication because it does not require acknowledgment signals and has shorter bus lengths.
|
False
|
Considering multiple factors.
|
985 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
In I/O control methods, the program polling method requires the CPU to continuously check through the program whether the I/O device is ready, and then control the exchange of information between the I/O device and the host.
|
True
| null |
986 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
In the functions of the I/O interface, address decoding and device selection are used to implement address decoding and device selection.
|
True
| null |
987 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
One difference between DMA mode and interrupt mode is that interrupt mode does not occupy CPU resources, while DMA mode does occupy CPU resources.
|
True
| null |
988 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
In the I/O interface, the part that implements data format conversion and the transmission of control commands is the internal interface.
|
True
| null |
989 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
In DMA mode, the DMA request trigger is set when the CPU executes the interrupt service routine.
|
False
| null |
990 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
The interrupt return instruction in the interrupt service routine is commonly used to allow the CPU to return to the breakpoint of the original program and continue execution.()
|
True
| null |
991 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
In the addressing modes of I/O interfaces, the unified addressing mode treats I/O ports as memory units for address allocation.
|
True
| null |
992 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
In DMA mode, the DMA request trigger is cleared when the CPU executes the interrupt service routine.
|
False
| null |
993 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
The format of I/O instructions is the same as that of general instructions.
|
True
| null |
994 |
Test
|
Computer Organization
|
Input/Output System
|
Assertion
|
Knowledge
|
English
|
The channel program is stored in the main memory.
|
True
| null |
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