<p>I have a "watcher" module that is currently using global hierarchies inside it.  I need to instantiate a second instance of this with a second global hierarchy.</p>

<p>Currently:</p>

<pre><code>module watcher;
wire sig = `HIER.sig;
wire bar = `HIER.foo.bar;
...
endmodule

watcher w; // instantiation
</code></pre>

<p>Desired:</p>

<pre><code>module watcher(input base_hier);
wire sig = base_hier.sig;
wire bar = base_hier.foo.bar;
...
endmodule

watcher w1(`HIER1); // instantiation
watcher w2(`HIER2); // second instantiation, except with a different hierarchy
</code></pre>

<p>My best idea is to use vpp (the Verilog preprocessor) to brute-force generate two virtually-identical modules (one with each hierarchy), but is there a more elegant way?</p>

[{'answer_id': 68376, 'author': 'DMC', 'author_id': 3148, 'author_profile': 'https://Stackoverflow.com/users/3148', 'pm_score': 3, 'selected': False, 'text': '<p>My preference is to have a single module (or a small number of modules) in your testbench that contains all your probes but no other functionality. All other modules in your testbench that require probes then connect to that "probe module". Use SystemVerilog interfaces in preference to raw wires if that\'s an option for you. This circumvents your problem since no watcher will require global hierarchies and your testbench on the whole will be considerably easier to maintain. See the <a href="http://en.wikipedia.org/wiki/Law_of_Demeter" rel="noreferrer" title="Law of Demeter">Law of Demeter</a>.</p>\n\n<p>Alternatively... (but this puts hierarchy in your instantiations...)</p>\n\n<pre><code>module watcher(sig, bar);\n  input sig;\n  input bar;\n...\nendmodule\n\nwatcher w1(`HIER1.sig, `HIER1.foo.bar); // instantiation\nwatcher w2(`HIER2.sig, `HIER2.foo.bar); // second instantiation, except with a different hierarchy\n</code></pre>\n\n<p>Subsequently you can also:</p>\n\n<pre><code>`define WATCHER_INST(NAME, HIER) watcher NAME(HIER.sig, HIER.foo.sig)\n\n`WATCHER_INST(w1, `HIER1);\n`WATCHER_INST(w2, `HIER2);\n</code></pre>\n'}, {'answer_id': 899614, 'author': 'd3jones', 'author_id': 111215, 'author_profile': 'https://Stackoverflow.com/users/111215', 'pm_score': 2, 'selected': False, 'text': '<p>Can you use the SystemVerilog <code>bind</code> keyword to bind the module into every hierarchy that requires it? (This requires that you use SystemVerilog, and have a license for a simulator.)</p>\n\n<p>Using bind is like instantiating a module in the normal way, except that you provide a path to hierarchy into which the module is "remotely" instantiated:</p>\n\n<pre><code>bind top.my.hier my_module instance_name(.*);\nbind top.my_other.hier my_module instance_name(.*);\n</code></pre>\n\n<p>Even better: assume that each hierarchy that you are binding into is a separate instance of the same module. Then:</p>\n\n<pre><code>bind remote_module my_module instance_name(.*);\n</code></pre>\n\n<p>This binds your module into <strong>every instance</strong> of the target, no matter where it is in the design. This is very powerful if your module is a verification checker.</p>\n'}]
['https://Stackoverflow.com/questions/67418', 'https://Stackoverflow.com', 'https://Stackoverflow.com/users/8598/']