<p>Older K&amp;R (2nd ed.) and other C-language texts I have read that discuss the implementation of a dynamic memory allocator in the style of <code>malloc()</code> and <code>free()</code> usually also mention, in passing, something about data type alignment restrictions. Apparently certain computer hardware architectures (CPU, registers, and memory access) restrict how you can store and address certain value types. For example, there may be a requirement that a 4 byte (<code>long</code>) integer must be stored beginning at addresses that are multiples of four.</p>

<p>What restrictions, if any, do major platforms (Intel &amp; AMD, SPARC, Alpha) impose for memory allocation and memory access, or can I safely ignore aligning memory allocations on specific address boundaries?</p>

[{'answer_id': 36459, 'author': 'Greg Hewgill', 'author_id': 893, 'author_profile': 'https://Stackoverflow.com/users/893', 'pm_score': 2, 'selected': False, 'text': "<p>Alignment is still quite important today. Some processors (the 68k family jumps to mind) would throw an exception if you tried to access a word value on an odd boundary. Today, most processors will run two memory cycles to fetch an unaligned word, but this will definitely be slower than an aligned fetch. Some other processors won't even throw an exception, but will fetch an <em>incorrect</em> value from memory!</p>\n\n<p>If for no other reason than performance, it is wise to try to follow your processor's alignment preferences. Usually, your compiler will take care of all the details, but if you're doing anything where you lay out the memory structure yourself, then it's worth considering.</p>\n"}, {'answer_id': 36466, 'author': 'Rob Walker', 'author_id': 3631, 'author_profile': 'https://Stackoverflow.com/users/3631', 'pm_score': 1, 'selected': False, 'text': '<p>You still need to be aware of alignment issues when laying out a class or struct in C(++).  In these cases the compiler will do the right thing for you, but the overall size of the struct/class may be more wastefull than necessary</p>\n\n<p>For example:</p>\n\n<pre><code>struct\n{ \n    char A;\n    int B;\n    char C;\n    int D;\n};\n</code></pre>\n\n<p>Would have a size of 4 * 4 = 16 bytes (assume Windows on x86) whereas</p>\n\n<pre><code>struct\n{ \n    char A;\n    char C;\n    int B;\n    int D;\n};\n</code></pre>\n\n<p>Would have a size of 4*3 = 12 bytes.</p>\n\n<p>This is because the compiler enforces a 4 byte alignment for integers, but only 1 byte for chars.</p>\n\n<p>In general pack member variables of the same size (type) together to minimize wasted space.</p>\n'}, {'answer_id': 36544, 'author': 'denis phillips', 'author_id': 748, 'author_profile': 'https://Stackoverflow.com/users/748', 'pm_score': 1, 'selected': False, 'text': '<p>As Greg mentioned it is still important today (perhaps more so in some ways) and compilers usually take care of the alignment based on the target of the architecture. In managed environments, the JIT compiler can optimize the alignment based on the runtime architecture.</p>\n\n<p>You may see pragma directives (in C/C++) that change the alignment. This should only be used when very specific alignment is required.</p>\n\n<pre><code>// For example, this changes the pack to 2 byte alignment.\n#pragma pack(2)\n</code></pre>\n'}, {'answer_id': 47276, 'author': 'DGentry', 'author_id': 4761, 'author_profile': 'https://Stackoverflow.com/users/4761', 'pm_score': 3, 'selected': False, 'text': '<p>Sparc, MIPS, Alpha, and most other "classical RISC" architectures only allow aligned accesses to memory, even today. An unaligned access will cause an exception, but some operating systems will handle the exception by copying from the desired address in software using smaller loads and stores. The application code won\'t know there was a problem, except that the performance will be very bad.</p>\n\n<p>MIPS has special instructions (lwl and lwr) which can be used to access 32 bit quantities from unaligned addresses. Whenever the compiler can tell that the address is likely unaligned it will use this two instruction sequence instead of a normal lw instruction.</p>\n\n<p>x86 can handle unaligned memory accesses in hardware without an exception, but there is still a performance hit of up to 3X compared to aligned accesses.</p>\n\n<p>Ulrich Drepper wrote a comprehensive paper on this and other memory-related topics, <A HREF="http://people.redhat.com/drepper/cpumemory.pdf" rel="noreferrer">What Every Programmer Should Know About Memory</A>. It is a very long writeup, but filled with chewy goodness.</p>\n'}, {'answer_id': 47281, 'author': 'Pramod', 'author_id': 1386292, 'author_profile': 'https://Stackoverflow.com/users/1386292', 'pm_score': 1, 'selected': False, 'text': '<p>Note that even on IA-32 and the AMD64, some of the SSE instructions/intrinsics require aligned data. These instructions will throw an exception if the data is unaligned, so at least you won\'t have to debug "wrong data" bugs. There are equivalent unaligned instructions as well, but like Denton says, they\'re are slower.</p>\n\n<p>If you\'re using VC++, then besides the #pragma pack directives, you also have the __declspec(align) directives for precise alignment. VC++ documentation also mentions an __aligned_malloc function for specific alignment requirements.</p>\n\n<p>As a rule of thumb, unless you are moving data across compilers/languages or are using the SSE instructions, you can probably ignore alignment issues.</p>\n'}]
['https://Stackoverflow.com/questions/36455', 'https://Stackoverflow.com', 'https://Stackoverflow.com/users/-1/']