<p>In our embedded system (using a PowerPC processor), we want to disable the processor cache. What steps do we need to take?</p>

<p>To clarify a bit, the application in question must have as constant a speed of execution as we can make it.
Variability in executing the same code path is not acceptable. This is the reason to turn off the cache.</p>

[{'answer_id': 73316, 'author': 'Benoit', 'author_id': 10703, 'author_profile': 'https://Stackoverflow.com/users/10703', 'pm_score': 2, 'selected': False, 'text': '<p>From the E600 reference manual:<br>\nThe HID0 special-purpose register contains several bits that invalidate, disable, and lock the instruction and data caches.</p>\n\n<p>You should use HID0[DCE] = 0 to disable the data cache.<br>\nYou should use HID0[ICE] = 0 to disable the instruction cache.</p>\n\n<p>Note that at power up, both caches are disabled.\nYou will need to write this in assembly code.</p>\n'}, {'answer_id': 164483, 'author': 'KeyserSoze', 'author_id': 14116, 'author_profile': 'https://Stackoverflow.com/users/14116', 'pm_score': 1, 'selected': False, 'text': "<p>Perhaps you don't want to globally disable cache, you only want to disable it for a particular address range?</p>\n\n<p>On some processors you can configure TLB (translation lookaside buffer) entries for address ranges such that each range could have caching enabled or disabled.  This way you can disable caching for memory mapped I/O, and still leave caching on for the main block of RAM.</p>\n\n<p>The only PowerPC I've done this on was a PowerPC 440EP (from IBM, then AMCC), so I don't know if all PowerPCs work the same way.</p>\n"}, {'answer_id': 164525, 'author': 'jakobengblom2', 'author_id': 23054, 'author_profile': 'https://Stackoverflow.com/users/23054', 'pm_score': 1, 'selected': False, 'text': '<p>What kind of PPC core is it? The cache control is very different between different cores from different vendors... also, disabling the cache is in general considered a really bad thing to do to the machine. Performance becomes so crawlingly slow that you would do as well with an old 8-bit processor (exaggerating a bit).  Some ARM variants have TCMs, tightly-coupled memories, that work instead of caches, but I am not aware of any PPC variant with that facility. </p>\n\n<p>Maybe a better solution is to keep Level 1 caches active, and use the on-chip L2 caches as statically mapped RAM instead? That is common on modern PowerQUICC devices, at least. </p>\n'}, {'answer_id': 258673, 'author': 'Dan', 'author_id': 28574, 'author_profile': 'https://Stackoverflow.com/users/28574', 'pm_score': 3, 'selected': True, 'text': "<p>I'm kind of late to the question, and also it's been a while since I did all the low-level processor init code on PPCs, but I seem to remember the cache &amp; MMU being pretty tightly coupled (one had to be enabled to enable the other) and I <em>think</em> in the MMU page tables, you could define the cacheable attribute.</p>\n\n<p>So my point is this: if there's a certain subset of code that must run in deterministic time, maybe you locate that code (via a linker command file) in a region of memory that is defined as non-cacheable in the page tables?  That way all the code that can/should benefit from the cache does, and the (hopefully) subset of code that shouldn't, doesn't.</p>\n\n<p>I'd handle it this way anyway, so that later, if you want to enable caching for part of the system, you just need to flip a few bits in the MMU page tables, instead of (re-)writing the init code to set up all the page tables &amp; caching.</p>\n"}, {'answer_id': 1485180, 'author': 'Community', 'author_id': -1, 'author_profile': 'https://Stackoverflow.com/users/-1', 'pm_score': 1, 'selected': False, 'text': "<p>Turning off the cache will do you no good at all.  Your execution speed will drop by an order of magnitude.  You would never ship a system like this, so its performance under these conditions is of no interest.</p>\n\n<p>To achieve a steady execution speed, consider one of these approaches:</p>\n\n<p>1) Lock some or all of the cache.  All current PowerPC chips from Freescale, IBM, and AMCC offer this feature.</p>\n\n<p>2) If it's a Freescale chip with L2 cache, consider mapping part of that cache as on-chip memory.</p>\n"}]
['https://Stackoverflow.com/questions/73312', 'https://Stackoverflow.com', 'https://Stackoverflow.com/users/10703/']